//===========================================================================
#include <cyg/hal/hal_misc.h>
+#include CYGHWR_MEMORY_LAYOUT_H
// Get the pagesize for a particular virtual address:
// This does not depend on the vaddr.
-#define HAL_MM_PAGESIZE(vaddr, pagesize) CYG_MACRO_START \
- (pagesize) = SZ_1M; \
-CYG_MACRO_END
+#define HAL_MM_PAGESIZE(vaddr, pagesize) \
+ CYG_MACRO_START \
+ (pagesize) = SZ_1M; \
+ CYG_MACRO_END
// Get the physical address from a virtual address:
-#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START \
- cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
- if ( _v_ < 128 * SZ_1M ) /* SDRAM */ \
- _v_ += SDRAM_BASE_ADDR; \
- else /* Rest of it */ \
- /* no change */ ; \
- (paddr) = _v_; \
-CYG_MACRO_END
+#define HAL_VIRT_TO_PHYS_ADDRESS(vaddr, paddr) \
+ CYG_MACRO_START \
+ cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
+ if (_v_ < 128 * SZ_1M) /* SDRAM */ \
+ _v_ += SDRAM_BASE_ADDR; \
+ else /* Rest of it */ \
+ /* no change */ ; \
+ (paddr) = _v_; \
+ CYG_MACRO_END
/*
* translate the virtual address of ram space to physical address
* It is dependent on the implementation of hal_mmu_init
*/
+#if 1
+/*
+ * translate the virtual address of ram space to physical address
+ * It is dependent on the implementation of hal_mmu_init
+ */
+#ifndef RAM_BANK0_SIZE
+#warning using SDRAM_SIZE for RAM_BANK0_SIZE
+#define RAM_BANK0_SIZE SDRAM_SIZE
+#endif
+
+static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
+{
+ /* SDRAM mappings:
+ 80000000 -> 80000000
+ 90000000 -> 80000000 + (SDRAM_SIZE / 2)
+ */
+ if (virt < 0x08000000) {
+ return virt | (virt < RAM_BANK0_SIZE ? CSD0_BASE_ADDR : CSD1_BASE_ADDR);
+ }
+ if ((virt & 0xF0000000) == CSD0_BASE_ADDR) {
+ virt &= ~0x08000000;
+ if (virt >= CSD0_BASE_ADDR + RAM_BANK0_SIZE) {
+ virt = virt - CSD0_BASE_ADDR + CSD1_BASE_ADDR - RAM_BANK0_SIZE;
+ }
+ }
+ return virt;
+}
+
+/*
+ * remap the physical address of ram space to uncacheable virtual address space
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
+{
+ /* 0x88000000~0x88FFFFFF is uncacheable memory space which is mapped to SDRAM */
+ if ((phy & 0xF0000000) == CSD0_BASE_ADDR) {
+ phy |= 0x08000000;
+ }
+ if ((phy & 0xF0000000) == CSD1_BASE_ADDR) {
+ phy = (phy - CSD1_BASE_ADDR + CSD0_BASE_ADDR + RAM_BANK0_SIZE) | 0x08000000;
+ }
+ return phy;
+}
+#else
static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
{
- if(virt < 0x08000000) {
- return virt|0x80000000;
- }
- if((virt & 0xF0000000) == 0x80000000) {
- return virt&(~0x08000000);
- }
- return virt;
+ if (virt < 0x08000000) {
+ return virt|0x80000000;
+ }
+ if((virt & 0xF0000000) == 0x80000000) {
+ return virt&(~0x08000000);
+ }
+ return virt;
}
/*
*/
static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
{
- /* 0x88000000~0x87FFFFFF is uncacheable meory space which is mapped to SDRAM*/
- if((phy & 0xF0000000) == 0x80000000) {
- phy |= 0x08000000;
- }
- return phy;
+ /* 0x88000000~0x87FFFFFF is uncacheable meory space which is mapped to SDRAM*/
+ if ((phy & 0xF0000000) == 0x80000000) {
+ phy |= 0x08000000;
+ }
+ return phy;
}
+#endif
//---------------------------------------------------------------------------
#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H