#define CYGHWR_HAL_ROM_VADDR 0x0
-//#define TX27_DEBUG
+#define DEBUG_LED_BIT 13
+#define DEBUG_LED_PORT GPIOF_BASE
-#ifndef TX27_DEBUG
+#ifndef CYGOPT_HAL_ARM_TX27_DEBUG
#define LED_ON
#define LED_OFF
.macro LED_CTRL,val
.macro DELAY,val
.endm
#else
-#define CYGHWR_LED_MACRO LED_BLINK \x
+#define CYGHWR_LED_MACRO LED_BLINK #\x
#define LED_ON bl led_on
#define LED_OFF bl led_off
+
.macro DELAY,ms
ldr r10, =\ms
111:
.macro LED_CTRL,val
// switch user LED (PF13) on STK5
- ldr r10, GPIOF_BASE
+ ldr r10, DEBUG_LED_PORT
// PTF_DR
mov r9, \val
cmp r9, #0
- movne r9, #(1 << 13) // LED ON
- moveq r9, #0 // LED OFF
+ ldr r9, [r10, #GPIO_DR]
+ orrne r9, #(1 << DEBUG_LED_BIT) // LED ON
+ biceq r9, #(1 << DEBUG_LED_BIT) // LED OFF
str r9, [r10, #GPIO_DR]
.endm
.macro LED_BLINK,val
- mov r2, #\val
+ mov r3, \val
211:
- subs r2, r2, #1
+ subs r3, r3, #1
bmi 212f
LED_CTRL #1
DELAY 200
.macro LED_INIT
// initialize GPIO PF13 for LED on STK5
- ldr r10, GPIOF_BASE
+ ldr r10, DEBUG_LED_PORT
+ // PTF_DR
+ ldr r9, [r10, #GPIO_DR]
+ bic r9, #(1 << DEBUG_LED_BIT)
+ str r9, [r10, #GPIO_DR]
+ // PTF_OCR1
+ ldr r9, [r10, #GPIO_OCR1]
+ orr r9, #(3 << (2 * (DEBUG_LED_BIT % 16)))
+ str r9, [r10, #GPIO_OCR1]
// PTF_GIUS
ldr r9, [r10, #GPIO_GIUS]
- orr r9, r9, #(1 << 13)
+ orr r9, r9, #(1 << DEBUG_LED_BIT)
str r9, [r10, #GPIO_GIUS]
// PTF_DDIR
- mov r9,#(1 << 13)
+ ldr r9, [r10, #GPIO_DDIR]
+ orr r9, #(1 << DEBUG_LED_BIT)
str r9, [r10, #GPIO_DDIR]
- // PTF_OCR1
- mov r9, #(3 << (2 * 13))
- str r9, [r10, #GPIO_OCR1]
.endm
+ .macro WDOG_RESET
+ ldr r10, SOC_CRM_BASE_W
+ ldr r9, [r10, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+ orr r9, r9, #(1 << 2) /* enable FPM */
+ str r9, [r10, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+
+ ldr r10, WDOG_BASE
+ mov r9, #0
+ str r9, [r10, #0]
+ .endm
// This macro represents the initial startup code for the platform
// r11 is reserved to contain chip rev info in this file
.macro _platform_setup1
- b KARO_TX27_SETUP_START
-#ifdef TX27_DEBUG
-led_on:
- ldr r10, GPIOF_BASE
- // PTF_DR
- mov r9, #(1 << 13) // LED ON
- str r9, [r10, #GPIO_DR]
- mov pc, lr
-
-led_off:
- ldr r10, GPIOF_BASE
- // PTF_DR
- mov r9, #0 // LED OFF
- str r9, [r10, #GPIO_DR]
- mov pc, lr
-#endif
-
-nfc_cmd_input:
- strh r3, [r4, #NAND_FLASH_CMD_REG_OFF]
- mov r3, #NAND_FLASH_CONFIG2_FCMD_EN
- strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
- b nfc_wait_op_done
-
-nfc_addr_input:
- and r3, r3, #0xFF
- strh r3, [r4, #NAND_FLASH_ADD_REG_OFF]
- mov r3, #NAND_FLASH_CONFIG2_FADD_EN
- strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
- b nfc_wait_op_done
-
-nfc_data_output:
- mov r3, #FDO_PAGE_SPARE_VAL
- strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
- add r8, r8, #1
- b nfc_wait_op_done
-
-nfc_wait_op_done:
-311:
- ldrh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
- ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
- movne r3, #0x0
- strneh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
- movne pc, lr
- b 311b
-
KARO_TX27_SETUP_START:
// invalidate I/D cache/TLB
mov r0, #0
init_aipi_start:
init_aipi
-#if 1
- mov r0, #SDRAM_NON_FLASH_BOOT
- ldr r1, AVIC_VECTOR0_ADDR_W
- str r0, [r1] // for checking boot source from nand or sdram
-#endif
+
+ /* configure GPIO PB22 (OSC26M enable) as output high */
+ ldr r10, GPIOB_BASE
+ // PTB_OCR1
+ ldr r9, [r10, #GPIO_OCR2]
+ orr r9, #(3 << (2 * (22 % 16)))
+ str r9, [r10, #GPIO_OCR2]
+ // PTB_DR
+ ldr r9, [r10, #GPIO_DR]
+ orr r9, r9, #(1 << 22)
+ str r9, [r10, #GPIO_DR]
+ // PTB_GIUS
+ ldr r9, [r10, #GPIO_GIUS]
+ orr r9, r9, #(1 << 22)
+ str r9, [r10, #GPIO_GIUS]
+ // PTB_DDIR
+ ldr r9, [r10, #GPIO_DDIR]
+ orr r9, #(1 << 22)
+ str r9, [r10, #GPIO_DDIR]
+
+ LED_INIT
+
// setup System Controls
ldr r0, SOC_SYSCTRL_BASE_W
mov r1, #0x03
init_max_start:
init_max
init_drive_strength_start:
- init_drive_strength
-#if 0
-init_cs4_start:
- init_cs4
-#endif
-
-#if 0
-init_cs0_start:
- init_cs0
-#endif
- LED_INIT
+@ init_drive_strength
// check if sdram has been setup
cmp pc, #SDRAM_BASE_ADDR
init_clock_start:
init_clock
init_sdram_start:
+ LED_BLINK #1
setup_sdram_ddr
-
+ LED_BLINK #2
HWInitialise_skip_SDRAM_setup:
ldr r0, NFC_BASE_W
add r2, r0, #0x800 // 2K window
NAND_Boot_Start:
/* Copy image from flash to SDRAM first */
- ldr r1, MXC_REDBOOT_ROM_START
+ ldr r1, MXC_REDBOOT_RAM_START
1:
ldmia r0!, {r3-r10}
stmia r1!, {r3-r10}
blo 1b
LED_ON
- ldr r1, MXC_REDBOOT_ROM_START
+ ldr r1, MXC_REDBOOT_RAM_START
ldr r0, NFC_BASE_W
2:
ldr r3, [r1], #4
LED_OFF
b 4f
3:
- LED_BLINK 3
+#ifdef CYGOPT_HAL_ARM_TX27_DEBUG
+ LED_BLINK #3
+#else
+ WDOG_RESET
+#endif
b 3b
4:
LED_ON
/* Jump to SDRAM */
- jump_to_sdram
+ bl jump_to_sdram
LED_OFF
-#if 1
- mov r0, #NAND_FLASH_BOOT
- ldr r1, AVIC_VECTOR0_ADDR_W
- str r0, [r1]
- mov r0, #MXCFIS_NAND
- ldr r1, AVIC_VECTOR1_ADDR_W
- str r0, [r1]
-#endif
NAND_Copy_Main:
ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
mov r1, #TX27_NAND_PAGE_SIZE //r1: starting flash addr to be copied. Updated constantly
- add r2, r0, #TX27_NAND_PAGE_SIZE //r2: end of 3st RAM buf. Doesn't change
+ add r2, r0, #TX27_NAND_PAGE_SIZE //r2: end of 1st RAM buf. Doesn't change
add r4, r0, #0xE00 //r4: NFC register base. Doesn't change
- ldr r5, MXC_REDBOOT_ROM_START
+ ldr r5, MXC_REDBOOT_RAM_START
add r6, r5, #REDBOOT_IMAGE_SIZE //r6: end of SDRAM address for copying. Doesn't change
add r5, r5, r1 //r5: starting SDRAM address for copying. Updated constantly
LED_ON
strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
bl nfc_data_output
-#if 1
+
// check for bad block
mov r3, r1, lsl #(32-17) // get rid of block number
cmp r3, #(TX27_NAND_PAGE_SIZE << (32-17)) // check if not first or second page in block
bhi Copy_Good_Blk
-#else
- b Copy_Good_Blk
-#endif
+
add r9, r0, #TX27_NAND_PAGE_SIZE //r3 -> spare area buf 0
ldrh r9, [r9, #0x4]
and r9, r9, #0xFF00
sub r5, r5, #TX27_NAND_PAGE_SIZE //rewind 1 page for the sdram pointer
sub r1, r1, #TX27_NAND_PAGE_SIZE //rewind 1 page for the flash pointer
Skip_bad_block:
-#ifdef TX27_DEBUG
- LED_BLINK 1
+#ifdef CYGOPT_HAL_ARM_TX27_DEBUG
+ LED_BLINK #1
b Skip_bad_block
#endif
add r1, r1, #(TX27_NAND_BLKS_PER_PAGE*TX27_NAND_PAGE_SIZE)
NAND_Copy_Main_done:
Normal_Boot_Continue:
- jump_to_sdram
+// bl jump_to_sdram
// Code and all data used up to here must fit within the first 2KiB of FLASH ROM!
-Now_in_SDRAM:
- ///LED_BLINK 3
-
#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
/* Copy image from flash to SDRAM first */
ldr r0, =0xFFFFF000
and r0, r0, pc
- ldr r1, MXC_REDBOOT_ROM_START
+ ldr r1, MXC_REDBOOT_RAM_START
cmp r0, r1
beq HWInitialise_skip_SDRAM_copy
cmp r0, r2
ble 1b
- jump_to_sdram
+ bl jump_to_sdram
+Now_in_SDRAM:
+ LED_BLINK #3
#endif /* CYG_HAL_STARTUP_ROMRAM */
HWInitialise_skip_SDRAM_copy:
- ///LED_BLINK 2
+ LED_BLINK #2
init_cs0_sync_start:
init_cs0_sync
b 9f
.align 5
9:
- mov pc,r2 /* Change address spaces */
+ mov pc, r2 /* Change address spaces */
10:
nop
.endm // _platform_setup1
orr r1, r1, #0x000C0000 // restart SPLL and MPLL
orr r1, r1, #0x00000003 // enable SPLL and MPLL
str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
-
- // add some delay here
- mov r1, #0x1000
1:
- subs r1, r1, #0x1
+ ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+ tst r1, #0x000C0000
bne 1b
- ldr r2, SOC_CRM_CSCR2_W
- str r2, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+ ldr r1, SOC_CRM_CSCR2_W
+ str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
// Set divider of H264_CLK to zero, NFC to 3.
- ldr r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
- bic r2, r2, #0x0000FC00
- str r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
+ ldr r1, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
+ bic r1, r1, #0x0000FC00
+ str r1, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
- /* Configure PCDR */
/* Configure PCDR1 */
ldr r1, SOC_CRM_PCDR1_W
str r1, [r0, #(SOC_CRM_PCDR1 - SOC_CRM_BASE)]
// base address of SDRAM for SET MODE commands written to SDRAM via address lines
mov r2, #SOC_CSD0_BASE
- mov r1, #(1 << 3) // delay line soft reset
+ mov r1, #(1 << 1) // SDRAM controller reset
str r1, [r0, #ESDCTL_ESDMISC]
1:
// wait until SDRAMRDY bit is set indicating SDRAM is usable
tst r1, #(1 << 31)
beq 1b
- mov r1, #(1 << 2) // enable DDR pipeline
+ mov r1, #(1 << 3) @ delay line soft reset
+ str r1, [r0, #ESDCTL_ESDMISC]
+1:
+ // wait until SDRAMRDY bit is set indicating SDRAM is usable
+ ldr r1, [r0, #ESDCTL_ESDMISC]
+ tst r1, #(1 << 31)
+ beq 1b
+
+ mov r1, #(1 << 2) @ enable DDR pipeline
str r1, [r0, #ESDCTL_ESDMISC]
ldr r1, SDRAM_ESDCFG0_VAL
str r1, [r0, #ESDCTL_ESDCFG0]
+ ldr r1, SDRAM_DLY_VAL
+ str r1, [r0, #ESDCTL_ESDCDLY1]
+ str r1, [r0, #ESDCTL_ESDCDLY2]
+ str r1, [r0, #ESDCTL_ESDCDLY3]
+ str r1, [r0, #ESDCTL_ESDCDLY4]
+ str r1, [r0, #ESDCTL_ESDCDLY5]
+
ldr r1, SDRAM_PRE_ALL_CMD
str r1, [r0, #ESDCTL_ESDCTL0]
- str r1, [r2, #(1 << 10)] // contents of r1 irrelevant, data written via A0-A12
+ str r1, [r2, #(1 << 10)] @ contents of r1 irrelevant, data written via A0-A11
+
ldr r1, SDRAM_AUTO_REF_CMD
str r1, [r0, #ESDCTL_ESDCTL0]
-
- // initiate 8 auto refresh cycles
- mov r3, #7
-1:
- str r1, [r2, #(1 << 10)] // contents of r1 irrelevant, data written via A0-A12
- subs r3, r3, #1
- bpl 1b
+ @ initiate 2 auto refresh cycles
+ .rept 2
+ str r1, [r2]
+ .endr
ldr r1, SDRAM_SET_MODE_REG_CMD
str r1, [r0, #ESDCTL_ESDCTL0]
- strb r1, [r2, #0x0033] // actually a write to SDRAM MODE register
+ @ address offset for extended mode register
+ add r3, r2, #(2 << 24)
+ @ select drive strength via extended mode register:
+ @ 0=full 1=half 2=quarter 3=3-quarter
+ ldrb r1, [r3, #(0 << 5)]
+
+ ldrb r1, [r2, #0x033] @ write to SDRAM MODE register (via A0-A12)
ldr r1, SDRAM_NORMAL_MODE
str r1, [r0, #ESDCTL_ESDCTL0]
str r1, [r2]
- mov r1, #((1 << 3) | (1 << 2))
+ mov r1, #((1 << 3) | (1 << 2) | (1 << 5))
str r1, [r0, #ESDCTL_ESDMISC]
.endm // setup_sdram_ddr
- .macro jump_to_sdram
- mov r0, #0
+#ifdef CYGOPT_HAL_ARM_TX27_DEBUG
+led_on:
+ ldr r10, GPIOF_BASE
+ // PTF_DR
+ mov r9, #(1 << 13) // LED ON
+ str r9, [r10, #GPIO_DR]
+ mov pc, lr
+
+led_off:
+ ldr r10, GPIOF_BASE
+ // PTF_DR
+ mov r9, #0 // LED OFF
+ str r9, [r10, #GPIO_DR]
+ mov pc, lr
+#endif
+
+nfc_cmd_input:
+ strh r3, [r4, #NAND_FLASH_CMD_REG_OFF]
+ mov r3, #NAND_FLASH_CONFIG2_FCMD_EN
+ strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
+ b nfc_wait_op_done
+
+nfc_addr_input:
+ and r3, r3, #0xFF
+ strh r3, [r4, #NAND_FLASH_ADD_REG_OFF]
+ mov r3, #NAND_FLASH_CONFIG2_FADD_EN
+ strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
+ b nfc_wait_op_done
+
+nfc_data_output:
+ mov r3, #FDO_PAGE_SPARE_VAL
+ strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
+ add r8, r8, #1
+ b nfc_wait_op_done
+
+nfc_wait_op_done:
+311:
+ ldrh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
+ ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
+ movne r3, #0x0
+ strneh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
+ movne pc, lr
+ b 311b
+
+jump_to_sdram:
+ b 1f
+ .align 5
+1:
mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
mcr 15, 0, r0, c7, c10, 4 /* Data Write Barrier */
ldr r0, SDRAM_ADDR_MASK
- ldr r1, MXC_REDBOOT_ROM_START
- and r0, pc, r0
+ ldr r1, MXC_REDBOOT_RAM_START
+ and r0, lr, r0
sub r0, r1, r0
- add pc, pc, r0
- nop
+ add lr, lr, r0
+ mov pc, lr
+
+#define PLATFORM_VECTORS _platform_vectors
+ .macro _platform_vectors
+ .globl _KARO_MAGIC
+_KARO_MAGIC:
+ .ascii "KARO_CE6"
+ .globl _KARO_STRUCT_SIZE
+_KARO_STRUCT_SIZE:
+ .word 0 // reserve space structure length
+
+ .globl _KARO_CECFG_START
+_KARO_CECFG_START:
+ .rept 1024/4
+ .word 0 // reserve space for CE configuration
+ .endr
+
+ .globl _KARO_CECFG_END
+_KARO_CECFG_END:
.endm
.align 5
.ascii "KARO TX27 " __DATE__ " " __TIME__
.align
+
+/* SDRAM configuration */
+#define RA_BITS 2 /* row addr bits - 11 */
+#define CA_BITS (SDRAM_SIZE / SZ_64M) /* 0-2: col addr bits - 8 3: rsrvd */
+#define DSIZ 2 /* 0: D[31..16] 1: D[15..D0] 2: D[31..0] 3: rsrvd */
+#define SREFR 3 /* 0: disabled 1-5: 2^n rows/clock *: rsrvd */
+#define PWDT 1 /* 0: disabled 1: precharge pwdn
+ 2: pwdn after 64 clocks 3: pwdn after 128 clocks */
+#define FP 0 /* 0: not full page 1: full page */
+#define BL 1 /* 0: 4(not for LPDDR) 1: 8 */
+#define PRCT 5 /* 0: disabled *: clks / 2 (0..63) */
+#define ESDCTLVAL (0x80000000 | (RA_BITS << 24) | (CA_BITS << 20) | \
+ (DSIZ << 16) | (SREFR << 13) | (PWDT << 10) | (FP << 8) | \
+ (BL << 7) | (PRCT << 0))
+
+/* SDRAM timing definitions */
+#define SDRAM_CLK 133
+#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
+
+ .macro CK_VAL, name, clks, offs
+ .iflt \clks - \offs
+ .set \name, 0
+ .else
+ .ifle \clks - 16
+ .set \name, \clks - \offs
+ .else
+ .set \name, 0
+ .endif
+ .endif
+ .endm
+
+ .macro NS_VAL, name, ns, offs
+ .iflt \ns - \offs
+ .set \name, 0
+ .else
+ CK_VAL \name, NS_TO_CK(\ns), \offs
+ .endif
+ .endm
+
+#if SDRAM_SIZE <= SZ_64M
+/* MT46H16M32LF-75 */
+CK_VAL tXP, 2, 1 /* clks - 1 (0..7) */
+CK_VAL tWTR, 2, 1 /* clks - 1 (0..1) */
+NS_VAL tRP, 23, 2 /* clks - 2 (0..3) */
+CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
+NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
+NS_VAL tRAS, 45, 1 /* clks - 1 (0..15) */
+CK_VAL tCAS, 3, 0 /* clks - 1 (0..3) */
+NS_VAL tRRD, 15, 1 /* clks - 1 (0..3) */
+NS_VAL tRCD, 23, 1 /* clks - 1 (0..7) */
+/* tRC is actually max(tRC,tRFC,tXSR) */
+NS_VAL tRC, 120, 1 /* 0: 20 *: clks - 1 (0..15) */
+#else
+/* MT46H32M32LF-6 or -75 */
+NS_VAL tXP, 25, 1 /* clks - 1 (0..7) */
+CK_VAL tWTR, 1, 1 /* clks - 1 (0..1) */
+NS_VAL tRP, 23, 2 /* clks - 2 (0..3) */
+CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
+NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
+NS_VAL tRAS, 45, 1 /* clks - 1 (0..15) */
+CK_VAL tCAS, 3, 0 /* clks - 1 (0..3) */
+NS_VAL tRRD, 15, 1 /* clks - 1 (0..3) */
+NS_VAL tRCD, 23, 1 /* clks - 1 (0..7) */
+NS_VAL tRC, 138, 1 /* 0: 20 *: clks - 1 (0..15) */
+#endif
+
+#define ESDCFGVAL ((tXP << 21) | (tWTR << 20) | (tRP << 18) | (tMRD << 16) | \
+ (tWR << 15) | (tRAS << 12) | (tRRD << 10) | (tCAS << 8) | \
+ (tRCD << 4) | (tRC << 0))
+
// All these constants need to be in the first 2KiB of FLASH
+WDOG_BASE: .word WDOG_BASE_ADDR
+GPIOB_BASE: .word 0x10015100
GPIOF_BASE: .word 0x10015500
-CONST_0xFFF: .word 0xfff
-SDRAM_ADDR_MASK: .word 0xfff00000
-MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x00100000
-AVIC_VECTOR0_ADDR_W: .word MXCBOOT_FLAG_REG
-AVIC_VECTOR1_ADDR_W: .word MXCFIS_FLAG_REG
+SDRAM_ADDR_MASK: .word 0xffff0000
+MXC_REDBOOT_RAM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
SOC_SYSCTRL_BASE_W: .word SOC_SYSCTRL_BASE
SOC_MAX_BASE_W: .word SOC_MAX_BASE
SOC_MAX_MPR_VAL: .word 0x00302145
SOC_CRM_BASE_W: .word SOC_CRM_BASE
-CRM_MPCTL0_VAL_W: .word CRM_MPCTL0_VAL
-CRM_SPCTL0_VAL_W: .word CRM_SPCTL0_VAL
-CRM_MPCTL0_VAL_27MHZ_W: .word CRM_MPCTL0_VAL_27MHZ
-CRM_SPCTL0_VAL_27MHZ_W: .word CRM_SPCTL0_VAL_27MHZ
-SOC_CRM_CSCR_W: .word CRM_CSCR_VAL
CRM_MPCTL0_VAL2_W: .word CRM_MPCTL0_VAL2
CRM_SPCTL0_VAL2_W: .word CRM_SPCTL0_VAL2
-CRM_MPCTL0_VAL2_27MHZ_W: .word CRM_MPCTL0_VAL2_27MHZ
-CRM_SPCTL0_VAL2_27MHZ_W: .word CRM_SPCTL0_VAL2_27MHZ
SOC_CRM_CSCR2_W: .word CRM_CSCR_VAL2
SOC_CRM_PCDR1_W: .word 0x09030913 // p1=20 p2=10 p3=4 p4=10
SOC_CRM_PCCR0_W: .word 0x3108480F
CS4_CSCRA_VAL: .word 0x44443302
NFC_BASE_W: .word NFC_BASE
SOC_ESDCTL_BASE_W: .word SOC_ESDCTL_BASE
-SDRAM_ESDCFG0_VAL: .word 0x00395728
-SDRAM_PRE_ALL_CMD: .word 0x92200000
-SDRAM_AUTO_REF_CMD: .word 0xA2200000
-SDRAM_SET_MODE_REG_CMD: .word 0xB2200000
-SDRAM_NORMAL_MODE: .word 0x82124485
+SDRAM_ESDCFG0_VAL: .word ESDCFGVAL
+SDRAM_DLY_VAL: .word 0x002c0000
+SDRAM_PRE_ALL_CMD: .word 0x92120000
+SDRAM_AUTO_REF_CMD: .word 0xA2120000
+SDRAM_SET_MODE_REG_CMD: .word 0xB2120000
+SDRAM_NORMAL_MODE: .word ESDCTLVAL
CS0_CSCRU_VAL: .word 0x0000CC03
CS0_CSCRL_VAL: .word 0xA0330D01
CS0_CSCRA_VAL: .word 0x00220800
projects / karo-tx-redboot.git / blobdiff