.macro flash_header
b reset_vector
.org 0x400
-app_code_jump_v: .long reset_vector
-app_code_barker: .long 0xB1
-app_code_csf: .long 0
-dcd_ptr_ptr: .long dcd_ptr
-super_root_key: .long 0
-dcd_ptr: .long dcd_data
-app_dest_ptr: .long 0xAFF00000
+app_code_jump_v: .long reset_vector
+app_code_barker: .long 0xB1
+app_code_csf: .long 0
+dcd_ptr_ptr: .long dcd_ptr
+super_root_key: .long 0
+dcd_ptr: .long dcd_data
+app_dest_ptr: .long 0xAFF00000
-dcd_data: .long 0xB17219E9 // Fixed. can't change.
-dcd_len: .long (20*12)
+dcd_data: .long 0xB17219E9 // Fixed. can't change.
+dcd_len: .long (56*12)
//DCD
- // ldr r0, ESDCTL_BASE_W
- // /* Set CSD0 */
- // ldr r1, =0x80000000
- // str r1, [r0, #ESDCTL_ESDCTL0]
-DCDGEN(1, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x80000000)
- // /* Precharge command */
- // ldr r1, SDRAM_0x04008008
- // str r1, [r0, #ESDCTL_ESDSCR]
-DCDGEN(2, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
- // /* 2 refresh commands */
- // ldr r1, SDRAM_0x00008010
- // str r1, [r0, #ESDCTL_ESDSCR]
-DCDGEN(3, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
- // str r1, [r0, #ESDCTL_ESDSCR]
-DCDGEN(4, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
- // /* LMR with CAS=3 and BL=3 */
- // ldr r1, SDRAM_0x00338018
- // str r1, [r0, #ESDCTL_ESDSCR]
-DCDGEN(5, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00338018)
- // /* 14 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
- // ldr r1, SDRAM_0xB2220000
- // str r1, [r0, #ESDCTL_ESDCTL0]
-DCDGEN(6, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xC3220000)
- // /* Timing parameters */
- // ldr r1, SDRAM_0xB02567A9
- // str r1, [r0, #ESDCTL_ESDCFG0]
-DCDGEN(7, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0xB08567A9)
- // /* MDDR enable, RLAT=2 */
- // ldr r1, SDRAM_0x000A0104
- // str r1, [r0, #ESDCTL_ESDMISC]
-DCDGEN(8, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000A0104)
- // /* Normal mode */
- // ldr r1, =0x00000000
- // str r1, [r0, #ESDCTL_ESDSCR]
-DCDGEN(9, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0)
-
-//////////////////// csd1 //////////////////
-DCDGEN(10, 4, 0x83fd9008, 0x80000000)
- //Precharge command
- //setmem /32 0x83fd9014 = 0x0400800C // [MK]
-DCDGEN(11, 4, 0x83fd9014, 0x0400800C)
- //2 Refresh commands
- //setmem /32 0x83fd9014 = 0x00008014 // [MK]
-DCDGEN(12, 4, 0x83fd9014, 0x00008014)
- //setmem /32 0x83fd9014 = 0x00008014 // [MK]
-DCDGEN(13, 4, 0x83fd9014, 0x00008014)
- //LMR with CAS=3 and BL=3
- //setmem /32 0x83fd9014 = 0x0033801C // [MK]
-DCDGEN(14, 4, 0x83fd9014, 0x0033801C)
- //14 ROW, 10 COL, 32Bit, SREF=8 Micron Model
- //setmem /32 0x83fd9008 = 0xC3220000
-DCDGEN(15, 4, 0x83fd9008, 0xC3220000)
- //Timing parameters
- //setmem /32 0x83fd900C = 0xB08567A9
-DCDGEN(16, 4, 0x83fd900C, 0xB08567A9)
- //MDDR enable, RLAT=2
- //setmem /32 0x83fd9010 = 0x000a0104
-DCDGEN(17, 4, 0x83fd9010, 0x000a0104)
- //Normal mode
- //setmem /32 0x83fd9014 = 0x00000004 // [DB]
-DCDGEN(18, 4, 0x83fd9014, 0x00000004)
- //setmem /32 0x90000000 = 0x00000000
-DCDGEN(19, 4, 0x90000000, 0x00000000)
- //setmem /32 0xA0000000 = 0x00000000
-DCDGEN(20, 4, 0xA0000000, 0x00000000)
+//DDR2 IOMUX configuration
+DCDGEN(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200)
+DCDGEN(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5)
+DCDGEN(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5)
+DCDGEN(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2)
+DCDGEN(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2)
+DCDGEN(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7)
+DCDGEN(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45)
+DCDGEN(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45)
+DCDGEN(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45)
+DCDGEN(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45)
+DCDGEN(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0)
+DCDGEN(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3)
+DCDGEN(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3)
+DCDGEN(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3)
+DCDGEN(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3)
+DCDGEN(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3)
+DCDGEN(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3)
+DCDGEN(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2)
+//Set drive strength to HIGH
+DCDGEN(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x4)
+DCDGEN(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x4)
+DCDGEN(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x4)
+DCDGEN(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x4)
+//13 ROW, 10 COL, 32Bit, SREF=4 Micron Model
+//CAS=3, BL=4
+DCDGEN(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000)
+DCDGEN(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000)
+DCDGEN(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0)
+DCDGEN(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x3F3584AB)
+DCDGEN(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x3F3584AB)
+// Init DRAM on CS0
+DCDGEN(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+DCDGEN(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a)
+DCDGEN(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b)
+DCDGEN(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00448019)
+DCDGEN(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018)
+DCDGEN(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+DCDGEN(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+DCDGEN(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+DCDGEN(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018)
+DCDGEN(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019)
+DCDGEN(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00408019)
+DCDGEN(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000)
+
+// Init DRAM on CS1
+DCDGEN(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
+DCDGEN(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e)
+DCDGEN(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f)
+DCDGEN(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d)
+DCDGEN(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c)
+DCDGEN(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
+DCDGEN(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
+DCDGEN(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
+DCDGEN(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c)
+DCDGEN(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d)
+DCDGEN(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0040801d)
+DCDGEN(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004)
+
+DCDGEN(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000)
+DCDGEN(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000)
+DCDGEN(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
+DCDGEN(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000)
+DCDGEN(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
image_len: .long 256*1024
FSL_BOARD_SETUP_START:
// mrc p15, 0, r0, c1, c1, 0 // Read Secure Configuration Register data. Why doesn't work???
// mcr p15, 0, <Rd>, c1, c1, 0 ; Write Secure Configuration Register data
+
+ ldr r0, GPIO1_BASE_ADDR_W
+ ldr r1, [r0, #0x0]
+ orr r1, r1, #(1 << 23)
+ str r1, [r0, #0x0]
+ ldr r1, [r0, #0x4]
+ orr r1, r1, #(1 << 23)
+ str r1, [r0, #0x4]
+
#ifdef ENABLE_IMPRECISE_ABORT
- mrs r1, spsr // save old spsr
- mrs r0, cpsr // read out the cpsr
- bic r0, r0, #0x100 // clear the A bit
- msr spsr, r0 // update spsr
- add lr, pc, #0x8 // update lr
- movs pc, lr // update cpsr
- nop
- nop
- nop
- nop
- msr spsr, r1 // restore old spsr
+ mrs r1, spsr // save old spsr
+ mrs r0, cpsr // read out the cpsr
+ bic r0, r0, #0x100 // clear the A bit
+ msr spsr, r0 // update spsr
+ add lr, pc, #0x8 // update lr
+ movs pc, lr // update cpsr
+ nop
+ nop
+ nop
+ nop
+ msr spsr, r1 // restore old spsr
#endif
// explicitly disable L2 cache
mrc 15, 0, r0, c1, c0, 1
// reconfigure L2 cache aux control reg
mov r0, #0xC0 // tag RAM
add r0, r0, #0x4 // data RAM
- orr r0, r0, #(1 << 25) // disable write combine
orr r0, r0, #(1 << 24) // disable write allocate delay
orr r0, r0, #(1 << 23) // disable write allocate combine
orr r0, r0, #(1 << 22) // disable write allocate
+ ldr r1, =ROM_BASE_ADDRESS
+ ldr r3, [r1, #ROM_SI_REV_OFFSET]
+ cmp r3, #0x10
+ orrls r0, r0, #(1 << 25) // disable write combine for TO 2 and lower revs
+
mcr 15, 1, r0, c9, c0, 2
-init_spba_start:
- init_spba
init_aips_start:
init_aips
-init_max_start:
- init_max
init_m4if_start:
init_m4if
-init_iomux_start:
-// init_iomux
-
- // disable wdog
- ldr r0, =0x30
- ldr r1, WDOG1_BASE_W
- strh r0, [r1]
-
-init_clock_start:
- init_clock
-
#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
- /* Copy image from flash to SDRAM first */
+ /* Check if need to copy image to Redboot ROM space */
ldr r0, =0xFFFFF000
and r0, r0, pc
ldr r1, MXC_REDBOOT_ROM_START
#endif /* CYG_HAL_STARTUP_ROMRAM */
HWInitialise_skip_SDRAM_copy:
+ /* Skip clock setup if already booted up */
+ ldr r0, =IRAM_BASE_ADDR
+ ldr r0, [r0]
+ ldr r1, =FROM_SPI_NOR_FLASH
+ cmp r0, r1
+ beq Normal_Boot_Continue
+ ldr r1, =FROM_MMC_FLASH
+ cmp r0, r1
+ beq Normal_Boot_Continue
+
+init_clock_start:
+ init_clock
-init_cs1_start:
-// init_cs1 -- moved to plf_hardware_init()
+Normal_Boot_Continue:
/*
* Note:
// Create MMU tables
bl hal_mmu_init
+ /* Workaround for arm errata #709718 */
+ //Setup PRRR so device is always mapped to non-shared
+ mrc MMU_CP, 0, r1, c10, c2, 0 // Read Primary Region Remap Register
+ bic r1, #(3 << 16)
+ mcr MMU_CP, 0, r1, c10, c2, 0 // Write Primary Region Remap Register
+
// Enable MMU
ldr r2, =10f
- ldr r0, =ROM_BASE_ADDRESS
- ldr r3, [r0, #ROM_SI_REV_OFFSET]
- cmp r3, #0x1
- bne skip_L1_workaround
- // Workaround for L1 cache issue
- mrc MMU_CP, 0, r1, c10, c2, 1 // Read normal memory remap register
- bic r1, r1, #(3 << 14) // Remap inner attribute for TEX[0],C,B = b111 as noncacheable
- bic r1, r1, #(3 << 6) // Remap inner attribute for TEX[0],C,B = b011 as noncacheable
- bic r1, r1, #(3 << 4) // Remap inner attribute for TEX[0],C,B = b010 as noncacheable
- mcr MMU_CP, 0, r1, c10, c2, 1 // Write normal memory remap register
-skip_L1_workaround:
- mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
+ mrc MMU_CP, 0, r1, MMU_Control, c0
orr r1, r1, #7 // enable MMU bit
- orr r1, r1, #0x800 // enable z bit
- orrne r1, r1, #(1 << 28) // Enable TEX remap, workaround for L1 cache issue
+ orr r1, r1, #0x800 // enable z bit
+ orr r1, r1, #(1 << 28) // Enable TEX remap
mcr MMU_CP, 0, r1, MMU_Control, c0
+
+ /* Workaround for arm errata #621766 */
+ mrc MMU_CP, 0, r1, MMU_Control, c0, 1
+ orr r1, r1, #(1 << 5) // enable L1NEON bit
+ mcr MMU_CP, 0, r1, MMU_Control, c0, 1
+
mov pc,r2 /* Change address spaces */
nop
nop
#define PLATFORM_SETUP1
#endif
- /* Do nothing */
- .macro init_spba
- .endm /* init_spba */
-
/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
.macro init_aips
/*
.endm /* init_aips */
- /* MAX (Multi-Layer AHB Crossbar Switch) setup */
- .macro init_max
- .endm /* init_max */
-
.macro init_clock
ldr r0, CCM_BASE_ADDR_W
+
+ /* Gate of clocks to the peripherals first */
+ ldr r1, =0x3FFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ ldr r1, =0x0
+ str r1, [r0, #CLKCTL_CCGR1]
+ str r1, [r0, #CLKCTL_CCGR2]
+ str r1, [r0, #CLKCTL_CCGR3]
+
+ ldr r1, =0x00030000
+ str r1, [r0, #CLKCTL_CCGR4]
+ ldr r1, =0x00FFF030
+ str r1, [r0, #CLKCTL_CCGR5]
+ ldr r1, =0x00000300
+ str r1, [r0, #CLKCTL_CCGR6]
+
/* Disable IPU and HSC dividers */
mov r1, #0x60000
str r1, [r0, #CLKCTL_CCDR]
+ /* Make sure to switch the DDR away from PLL 1 */
+ ldr r1, CCM_VAL_0x19239145
+ str r1, [r0, #CLKCTL_CBCDR]
+ /* make sure divider effective */
+ 1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
/* Switch ARM to step clock */
mov r1, #0x4
str r1, [r0, #CLKCTL_CCSR]
setup_pll PLL1, 800
+ setup_pll PLL3, 665
/* Switch peripheral to PLL 3 */
ldr r0, CCM_BASE_ADDR_W
- ldr r1, CCM_VAL_0x0000D3C0
+ ldr r1, CCM_VAL_0x000010C0
str r1, [r0, #CLKCTL_CBCMR]
- ldr r1, CCM_VAL_0x033B9145
+ ldr r1, CCM_VAL_0x13239145
str r1, [r0, #CLKCTL_CBCDR]
setup_pll PLL2, 665
/* Switch peripheral to PLL 2 */
ldr r0, CCM_BASE_ADDR_W
- ldr r1, CCM_VAL_0x013B9145
+ ldr r1, CCM_VAL_0x19239145
str r1, [r0, #CLKCTL_CBCDR]
- ldr r1, CCM_VAL_0x0000E3C0
+ ldr r1, CCM_VAL_0x000020C0
str r1, [r0, #CLKCTL_CBCMR]
setup_pll PLL3, 216
ldr r1, PLATFORM_CLOCK_DIV_W
str r1, [r0, #PLATFORM_ICGC]
- /* Switch ARM back to PLL 1. */
ldr r0, CCM_BASE_ADDR_W
+ /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */
+ ldr r1, =ROM_BASE_ADDRESS
+ ldr r3, [r1, #ROM_SI_REV_OFFSET]
+ cmp r3, #0x10
+ movls r1, #0x1
+ movhi r1, #0
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Switch ARM back to PLL 1. */
mov r1, #0x0
str r1, [r0, #CLKCTL_CCSR]
/* setup the rest */
- mov r1, #0
- str r1, [r0, #CLKCTL_CACRR]
-
/* Use lp_apm (24MHz) source for perclk */
- ldr r1, CCM_VAL_0x0000E3C2
+ ldr r1, CCM_VAL_0x000020C2
str r1, [r0, #CLKCTL_CBCMR]
- // emi=ahb, all perclk dividers are 1 since using 24MHz
- // DDR divider=6 to have 665/6=110MHz
- ldr r1, CCM_VAL_0x013D9100
+ // ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
+ ldr r1, CCM_VAL_0x59239100
str r1, [r0, #CLKCTL_CBCDR]
+ /* Restore the default values in the Gate registers */
+ ldr r1, =0xFFFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ str r1, [r0, #CLKCTL_CCGR1]
+ str r1, [r0, #CLKCTL_CCGR2]
+ str r1, [r0, #CLKCTL_CCGR3]
+ str r1, [r0, #CLKCTL_CCGR4]
+ str r1, [r0, #CLKCTL_CCGR5]
+ str r1, [r0, #CLKCTL_CCGR6]
+
/* Use PLL 2 for UART's, get 66.5MHz from it */
ldr r1, CCM_VAL_0xA5A2A020
str r1, [r0, #CLKCTL_CSCMR1]
/* Now restart PLL */
ldr r1, PLL_VAL_0x1232
str r1, [r0, #PLL_DP_CTL]
-wait_pll_lock\pll_nr:
+wait_pll_lock\pll_nr\mhz:
ldr r1, [r0, #PLL_DP_CTL]
ands r1, r1, #0x1
- beq wait_pll_lock\pll_nr
+ beq wait_pll_lock\pll_nr\mhz
.endm
/* M4IF setup */
.macro init_m4if
- /* Configure M4IF registers, VPU and IPU given higher priority (=0x4)
- IPU accesses with ID=0x1 given highest priority (=0xA) */
ldr r1, M4IF_BASE_W
- ldr r0, M4IF_0x00000a01
- str r0, [r1, #M4IF_FIDBP]
-
- ldr r0, M4IF_0x00000404
+ ldr r0, M4IF_0x00000203
str r0, [r1, #M4IF_FBPM0]
- .endm /* init_m4if */
- .macro init_iomux
- // do nothing
- .endm /* init_iomux */
+ ldr r0, =0x0
+ str r0, [r1, #M4IF_FBPM1]
+
+ ldr r0, M4IF_0x00120125
+ str r0, [r1, #M4IF_FPWC]
+
+ ldr r0, M4IF_0x001901A3
+ str r0, [r1, #M4IF_MIF4]
+ .endm /* init_m4if */
#define PLATFORM_VECTORS _platform_vectors
.macro _platform_vectors
_board_CFG: .long 0 // Board Configuration (read at RESET)
.endm
-WDOG1_BASE_W: .word WDOG1_BASE_ADDR
-IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
AIPS1_PARAM_W: .word 0x77777777
-MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
-MAX_PARAM1: .word 0x00302154
-ESDCTL_BASE_W: .word ESDCTL_BASE_ADDR
M4IF_BASE_W: .word M4IF_BASE_ADDR
-M4IF_0x00000a01: .word 0x00000a01
-M4IF_0x00000404: .word 0x00000404
-NFC_BASE_W: .word NFC_BASE_ADDR_AXI
-NFC_IP_BASE_W: .word NFC_IP_BASE
-IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
+M4IF_0x00120125: .word 0x00120125
+M4IF_0x001901A3: .word 0x001901A3
+M4IF_0x00000203: .word 0x00000203
MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
-CONST_0x0FFF: .word 0x0FFF
+GPIO1_BASE_ADDR_W: .word GPIO1_BASE_ADDR
CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
-CCM_VAL_0x0000E3C2: .word 0x0000E3C2
-CCM_VAL_0x013D9100: .word 0x013D9100
+CCM_VAL_0x000020C2: .word 0x000020C2
+CCM_VAL_0x59239100: .word 0x59239100
+CCM_VAL_0x19239145: .word 0x19239145
CCM_VAL_0xA5A2A020: .word 0xA5A2A020
CCM_VAL_0x00C30321: .word 0x00C30321
-CCM_VAL_0x0000D3C0: .word 0x0000D3C0
-CCM_VAL_0x033B9145: .word 0x033B9145
-CCM_VAL_0x013B9145: .word 0x013B9145
-CCM_VAL_0x0000E3C0: .word 0x0000E3C0
+CCM_VAL_0x000010C0: .word 0x000010C0
+CCM_VAL_0x13239145: .word 0x13239145
+CCM_VAL_0x000020C0: .word 0x000020C0
PLL_VAL_0x222: .word 0x222
PLL_VAL_0x232: .word 0x232
BASE_ADDR_W_PLL1: .word PLL1_BASE_ADDR
W_DP_OP_800: .word DP_OP_800
W_DP_MFD_800: .word DP_MFD_800
W_DP_MFN_800: .word DP_MFN_800
-W_DP_OP_700: .word DP_OP_700
-W_DP_MFD_700: .word DP_MFD_700
-W_DP_MFN_700: .word DP_MFN_700
-W_DP_OP_400: .word DP_OP_400
-W_DP_MFD_400: .word DP_MFD_400
-W_DP_MFN_400: .word DP_MFN_400
-W_DP_OP_532: .word DP_OP_532
-W_DP_MFD_532: .word DP_MFD_532
-W_DP_MFN_532: .word DP_MFN_532
W_DP_OP_665: .word DP_OP_665
W_DP_MFD_665: .word DP_MFD_665
W_DP_MFN_665: .word DP_MFN_665
W_DP_MFD_216: .word DP_MFD_216
W_DP_MFN_216: .word DP_MFN_216
PLATFORM_BASE_ADDR_W: .word PLATFORM_BASE_ADDR
-PLATFORM_CLOCK_DIV_W: .word 0x00000725
-_nand_pg_sz: .word 0
+PLATFORM_CLOCK_DIV_W: .word 0x00000124
/*---------------------------------------------------------------------------*/
/* end of hal_platform_setup.h */
projects / karo-tx-redboot.git / blobdiff