/*FEC_MDIO*/
writel(0x3, IOMUXC_BASE_ADDR + 0x0D4);
- writel(0x1FD, IOMUXC_BASE_ADDR + 0x0470);
- writel(0x0, IOMUXC_BASE_ADDR + 0x09B0);
+ writel(0x1FD, IOMUXC_BASE_ADDR + 0x0468);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x0954);
- /*FEC_RDATA1*/
- writel(0x3, IOMUXC_BASE_ADDR + 0x0D8);
- writel(0x180, IOMUXC_BASE_ADDR + 0x0474);
- writel(0x0, IOMUXC_BASE_ADDR + 0x09B8);
-
- /*FEC_RDATA2*/
- writel(0x3, IOMUXC_BASE_ADDR + 0x0E8);
- writel(0x180, IOMUXC_BASE_ADDR + 0x0484);
- writel(0x0, IOMUXC_BASE_ADDR + 0x09BC);
+ /*FEC_MDC*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x13C);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x0524);
- /*FEC_RDATA3*/
+ /* FEC RDATA[3] */
writel(0x3, IOMUXC_BASE_ADDR + 0x0EC);
- writel(0x180, IOMUXC_BASE_ADDR + 0x0488);
- writel(0x0, IOMUXC_BASE_ADDR + 0x09C0);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x0480);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x0964);
- /*FEC_RX_ERR*/
- writel(0x3, IOMUXC_BASE_ADDR + 0x0F0);
- writel(0x180, IOMUXC_BASE_ADDR + 0x048C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x09CC);
-
- /*FEC_CRS*/
- writel(0x3, IOMUXC_BASE_ADDR + 0x0F4);
- writel(0x180, IOMUXC_BASE_ADDR + 0x0490);
- writel(0x0, IOMUXC_BASE_ADDR + 0x09AC);
-
- /*FEC_COL*/
- writel(0x1, IOMUXC_BASE_ADDR + 0x0124);
- writel(0x180, IOMUXC_BASE_ADDR + 0x05CC);
- writel(0x0, IOMUXC_BASE_ADDR + 0x9A8);
-
- /*FEC_RX_CLK*/
- writel(0x1, IOMUXC_BASE_ADDR + 0x0128);
- writel(0x180, IOMUXC_BASE_ADDR + 0x05D0);
- writel(0x0, IOMUXC_BASE_ADDR + 0x09C4);
-
- /*FEC_RX_DV*/
- writel(0x1, IOMUXC_BASE_ADDR + 0x012C);
- writel(0x180, IOMUXC_BASE_ADDR + 0x05D4);
- writel(0x0, IOMUXC_BASE_ADDR + 0x09C8);
+ /* FEC RDATA[2] */
+ writel(0x3, IOMUXC_BASE_ADDR + 0x0E8);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x047C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x0960);
- /*FEC_RDATA0*/
- writel(0x1, IOMUXC_BASE_ADDR + 0x0134);
- writel(0x2180, IOMUXC_BASE_ADDR + 0x05DC);
- writel(0x0, IOMUXC_BASE_ADDR + 0x09B4);
+ /* FEC RDATA[1] */
+ writel(0x3, IOMUXC_BASE_ADDR + 0x0d8);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x046C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x095C);
- /*FEC_TDATA0*/
- writel(0x1, IOMUXC_BASE_ADDR + 0x0138);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x5E0);
+ /* FEC RDATA[0] */
+ writel(0x2, IOMUXC_BASE_ADDR + 0x016C);
+ writel(0x2180, IOMUXC_BASE_ADDR + 0x0554);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x0958);
- /*FEC_TX_ERR*/
- writel(0x2, IOMUXC_BASE_ADDR + 0x0144);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x05EC);
+ /* FEC TDATA[3] */
+ writel(0x2, IOMUXC_BASE_ADDR + 0x148);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x0530);
- /*FEC_MDC*/
- writel(0x2, IOMUXC_BASE_ADDR + 0x0148);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x05F0);
+ /* FEC TDATA[2] */
+ writel(0x2, IOMUXC_BASE_ADDR + 0x144);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x052C);
- /*FEC_TDATA1*/
- writel(0x2, IOMUXC_BASE_ADDR + 0x014C);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x05F4);
+ /* FEC TDATA[1] */
+ writel(0x2, IOMUXC_BASE_ADDR + 0x140);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x0528);
- /*FEC_TDATA2*/
- writel(0x2, IOMUXC_BASE_ADDR + 0x0150);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x05F8);
+ /* FEC TDATA[0] */
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0170);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x0558);
- /*FEC_TDATA3*/
- writel(0x2, IOMUXC_BASE_ADDR + 0x0154);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x05FC);
+ /* FEC TX_EN */
+ writel(0x1, IOMUXC_BASE_ADDR + 0x014C);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x0534);
- /*FEC_TX_EN*/
- writel(0x1, IOMUXC_BASE_ADDR + 0x0158);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x0600);
+ /* FEC TX_ER */
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0138);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x0520);
- /*FEC_TX_CLK*/
- writel(0x1, IOMUXC_BASE_ADDR + 0x015C);
- writel(0x2180, IOMUXC_BASE_ADDR + 0x0604);
- writel(0x0, IOMUXC_BASE_ADDR + 0x09D0);
+ /* FEC TX_CLK */
+ writel(0x1, IOMUXC_BASE_ADDR + 0x0150);
+ writel(0x2180, IOMUXC_BASE_ADDR + 0x0538);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x0974);
- reg = readl(GPIO2_BASE_ADDR + 0x0);
- reg &= ~0x4000; // Lower reset line
- writel(reg, GPIO2_BASE_ADDR + 0x0);
+ /* FEC COL */
+ writel(0x1, IOMUXC_BASE_ADDR + 0x0124);
+ writel(0x2180, IOMUXC_BASE_ADDR + 0x0500);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x094c);
- reg = readl(GPIO2_BASE_ADDR + 0x4);
- reg |= 0x4000; // configure GPIO lines as output
- writel(reg, GPIO2_BASE_ADDR + 0x4);
+ /* FEC RX_CLK */
+ writel(0x1, IOMUXC_BASE_ADDR + 0x0128);
+ writel(0x2180, IOMUXC_BASE_ADDR + 0x0504);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x0968);
- /* Reset the ethernet controller over GPIO */
- writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
+ /* FEC CRS */
+ writel(0x3, IOMUXC_BASE_ADDR + 0x0f4);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x0488);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x0950);
- hal_delay_us(200);
+ /* FEC RX_ER */
+ writel(0x3, IOMUXC_BASE_ADDR + 0x0f0);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x0484);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x0970);
- reg = readl(GPIO2_BASE_ADDR + 0x0);
- reg |= 0x4000;
- writel(reg, GPIO2_BASE_ADDR + 0x0);
+ /* FEC RX_DV */
+ writel(0x2, IOMUXC_BASE_ADDR + 0x164);
+ writel(0x2180, IOMUXC_BASE_ADDR + 0x054C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x096C);
}
#include <cyg/io/imx_spi.h>
freq : 25000000,
ss_pol : IMX_SPI_ACTIVE_HIGH,
ss : 0, // slave select 0
- fifo_sz : 64 * 4,
+ fifo_sz : 32,
reg : &spi_pmic_reg,
};
freq : 25000000,
ss_pol : IMX_SPI_ACTIVE_LOW,
ss : 1, // slave select 1
- fifo_sz : 64 * 4,
+ fifo_sz : 32,
us_delay: 0,
reg : &spi_nor_reg,
};
//
// Platform specific initialization
//
+static void babbage_power_init(void);
void plf_hardware_init(void)
{
unsigned int reg;
- /* Disable IPU and HSC dividers */
- writel(0x60000, CCM_BASE_ADDR + CLKCTL_CCDR);
- /* Change the DDR divider to run at 166MHz on CPU 2 */
- reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
- reg = (reg & (~0x70000)) | 0x40000;
- writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR);
- /* make sure divider effective */
- while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0);
- writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
+ spi_nor_init = (imx_spi_init_func_t *)imx_spi_init_v2_3;
+ spi_nor_xfer = (imx_spi_xfer_func_t *)imx_spi_xfer_v2_3;
+
+ spi_pmic_init = (imx_spi_init_func_t *)imx_spi_init_v2_3;
+ spi_pmic_xfer = (imx_spi_xfer_func_t *)imx_spi_xfer_v2_3;
+ spi_pmic_init(&imx_spi_pmic);
+
+ babbage_power_init();
// UART1
//RXD
- writel(0x0, IOMUXC_BASE_ADDR + 0x234);
- writel(0x1C5, IOMUXC_BASE_ADDR + 0x6E4);
-
+ writel(0x0, IOMUXC_BASE_ADDR + 0x228);
+ writel(0x1C5, IOMUXC_BASE_ADDR + 0x618);
//TXD
- writel(0x0, IOMUXC_BASE_ADDR + 0x238);
- writel(0x1C5, IOMUXC_BASE_ADDR + 0x6E8);
-
+ writel(0x0, IOMUXC_BASE_ADDR + 0x22c);
+ writel(0x1C5, IOMUXC_BASE_ADDR + 0x61c);
//RTS
- writel(0x0, IOMUXC_BASE_ADDR + 0x23C);
- writel(0x1C4, IOMUXC_BASE_ADDR + 0x6EC);
-
+ writel(0x0, IOMUXC_BASE_ADDR + 0x230);
+ writel(0x1C4, IOMUXC_BASE_ADDR + 0x620);
//CTS
- writel(0x0, IOMUXC_BASE_ADDR + 0x240);
- writel(0x1C4, IOMUXC_BASE_ADDR + 0x6F0);
-
+ writel(0x0, IOMUXC_BASE_ADDR + 0x234);
+ writel(0x1C4, IOMUXC_BASE_ADDR + 0x624);
// enable GPIO1_9 for CLKO and GPIO1_8 for CLKO2
- writel(0x00000004, 0x73fa83F4);
- writel(0x00000004, 0x73fa83F0);
+ writel(0x00000004, 0x73fa83E8);
+ writel(0x00000004, 0x73fa83Ec);
+
// enable ARM clock div by 8
writel(0x010900F0, CCM_BASE_ADDR + CLKCTL_CCOSR);
- spi_nor_init = (imx_spi_init_func_t *)imx_spi_init_v2_3;
- spi_nor_xfer = (imx_spi_xfer_func_t *)imx_spi_xfer_v2_3;
+ /* Configure UART3_RXD pin for GPIO */
+ writel(0x3, IOMUXC_BASE_ADDR + 0x240);
+ reg = readl(GPIO1_BASE_ADDR + 0x4);
+ reg &= ~0x400000; // configure GPIO lines as input
+ writel(reg, GPIO1_BASE_ADDR + 0x4);
- spi_pmic_init = (imx_spi_init_func_t *)imx_spi_init_v2_3;
- spi_pmic_xfer = (imx_spi_xfer_func_t *)imx_spi_xfer_v2_3;
+ if ((readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0) {
+ /* Babbage 2.5 */
+ system_rev |= 0x1 << BOARD_VER_OFFSET;
+ HAL_PLATFORM_EXTRA[32] = '5';
+ }
}
void mxc_mmc_init(unsigned int base_address)
{
switch(base_address) {
case MMC_SDHC1_BASE_ADDR:
- //diag_printf("Configure IOMUX of ESDHC1 on i.MX51\n");
/* SD1 CMD, SION bit */
- writel(0x10, IOMUXC_BASE_ADDR + 0x39c);
-
- /* SD1 CD, as gpio1_0 */
- writel(0x01, IOMUXC_BASE_ADDR + 0x3b4);
+ writel(0x10, IOMUXC_BASE_ADDR + 0x394);
/* Configure SW PAD */
/* SD1 CMD */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x868);
+ writel(0xd5, IOMUXC_BASE_ADDR + 0x79C);
/* SD1 CLK */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x86c);
+ writel(0xd5, IOMUXC_BASE_ADDR + 0x7A0);
/* SD1 DAT0 */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x870);
+ writel(0xd5, IOMUXC_BASE_ADDR + 0x7A4);
/* SD1 DAT1 */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x874);
+ writel(0xd5, IOMUXC_BASE_ADDR + 0x7A8);
/* SD1 DAT2 */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x878);
+ writel(0xd5, IOMUXC_BASE_ADDR + 0x7AC);
/* SD1 DAT3 */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x87c);
- /* SD1 CD as gpio1_0 */
- writel(0x1e2, IOMUXC_BASE_ADDR + 0x880);
+ writel(0xd5, IOMUXC_BASE_ADDR + 0x7B0);
break;
+ case MMC_SDHC2_BASE_ADDR:
+ /* SD2 CMD, SION bit */
+ writel(0x10, IOMUXC_BASE_ADDR + 0x3b4);
+ /* Configure SW PAD */
+ /* SD2 CMD */
+ writel(0x20f4, IOMUXC_BASE_ADDR + 0x7bc);
+ /* SD2 CLK */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x7c0);
+ /* SD2 DAT0 */
+ writel(0x20e4, IOMUXC_BASE_ADDR + 0x7c4);
+ /* SD2 DAT1 */
+ writel(0x21d4, IOMUXC_BASE_ADDR + 0x7c8);
+ /* SD2 DAT2 */
+ writel(0x21d4, IOMUXC_BASE_ADDR + 0x7cc);
+ /* SD2 DAT3 */
+ writel(0x20e4, IOMUXC_BASE_ADDR + 0x7d0);
default:
break;
}
static void babbage_power_init(void)
{
unsigned int val;
+ volatile unsigned int reg;
- /* power up the system first */
- pmic_reg(34, 0x00200000, 1);
+ /* Write needed to Power Gate 2 register */
+ val = pmic_reg(34, 0, 0);
+ val &= ~0x10000;
+ pmic_reg(34, val, 1);
- if (pll_clock(PLL1) > 800000000) {
- /* Set core voltage to 1.175V */
+ /* Write needed to update Charger 0 */
+ pmic_reg(48, 0x0023807F, 1);
+
+ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) <= 0x2) {
+ /* Set core voltage to 1.1V */
val = pmic_reg(24, 0, 0);
- val = val & (~0x1F) | 0x17;
+ val = val & (~0x1F) | 0x14;
pmic_reg(24, val, 1);
+
+ /* Setup VCC (SW2) to 1.25 */
+ val = pmic_reg(25, 0, 0);
+ val = val & (~0x1F) | 0x1A;
+ pmic_reg(25, val, 1);
+
+ /* Setup 1V2_DIG1 (SW3) to 1.25 */
+ val = pmic_reg(26, 0, 0);
+ val = val & (~0x1F) | 0x1A;
+ pmic_reg(26, val, 1);
+ hal_delay_us(50);
+ /* Raise the core frequency to 800MHz */
+ writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
+ } else {
+ /* TO 3.0 */
+ /* Setup VCC (SW2) to 1.225 */
+ val = pmic_reg(25, 0, 0);
+ val = val & (~0x1F) | 0x19;
+ pmic_reg(25, val, 1);
+
+ /* Setup 1V2_DIG1 (SW3) to 1.2 */
+ val = pmic_reg(26, 0, 0);
+ val = val & (~0x1F) | 0x18;
+ pmic_reg(26, val, 1);
+ }
+
+ if (((pmic_reg(7, 0, 0) & 0x1F) < REV_ATLAS_LITE_2_0) || (((pmic_reg(7, 0, 0) >> 9) & 0x3) == 0)) {
+ /* Set switchers in PWM mode for Atlas 2.0 and lower */
+ /* Setup the switcher mode for SW1 & SW2*/
+ val = pmic_reg(28, 0, 0);
+ val = val & (~0x3C0F) | 0x1405;
+ pmic_reg(28, val, 1);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ val = pmic_reg(29, 0, 0);
+ val = val & (~0xF0F) | 0x505;
+ pmic_reg(29, val, 1);
+ } else {
+ /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
+ /* Setup the switcher mode for SW1 & SW2*/
+ val = pmic_reg(28, 0, 0);
+ val = val & (~0x3C0F) | 0x2008;
+ pmic_reg(28, val, 1);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ val = pmic_reg(29, 0, 0);
+ val = val & (~0xF0F) | 0x808;
+ pmic_reg(29, val, 1);
}
/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */
val |= 0x10020;
pmic_reg(30, val, 1);
- /* Set VVIDEO to 2.775V, VAUDIO to 2.775V, VSD to 3.15V */
+ /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
val = pmic_reg(31, 0, 0);
val &= ~0x1FC;
val |= 0x1F4;
pmic_reg(33, val, 1);
hal_delay_us(200);
- /* Enable VGEN1 regulator */
- val = pmic_reg(32, val, 0);
- val |= 0x1;
- pmic_reg(32, val, 1);
+ reg = readl(GPIO2_BASE_ADDR + 0x0);
+ reg &= ~0x4000; // Lower reset line
+ writel(reg, GPIO2_BASE_ADDR + 0x0);
+
+ reg = readl(GPIO2_BASE_ADDR + 0x4);
+ reg |= 0x4000; // configure GPIO lines as output
+ writel(reg, GPIO2_BASE_ADDR + 0x4);
+
+ /* Reset the ethernet controller over GPIO */
+ writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
val = 0x49249;
pmic_reg(33, val, 1);
- hal_delay_us(200);
+ hal_delay_us(500);
+
+ reg = readl(GPIO2_BASE_ADDR + 0x0);
+ reg |= 0x4000;
+ writel(reg, GPIO2_BASE_ADDR + 0x0);
/* Setup the FEC after enabling the regulators */
mxc_fec_setup();
}
-RedBoot_init(babbage_power_init, RedBoot_INIT_PRIO(900));
-
void io_cfg_spi(struct imx_spi_dev *dev)
{
switch (dev->base) {
case CSPI1_BASE_ADDR:
// 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1
- writel(0x0, IOMUXC_BASE_ADDR + 0x21C);
- writel(0x105, IOMUXC_BASE_ADDR + 0x6CC);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x210);
+ writel(0x105, IOMUXC_BASE_ADDR + 0x600);
// 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1.
- writel(0x0, IOMUXC_BASE_ADDR + 0x220);
- writel(0x105, IOMUXC_BASE_ADDR + 0x6D0);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x214);
+ writel(0x105, IOMUXC_BASE_ADDR + 0x604);
if (dev->ss == 0) {
// de-select SS1 of instance: ecspi1.
- writel(0x3, IOMUXC_BASE_ADDR + 0x228);
- writel(0x85, IOMUXC_BASE_ADDR + 0x6D8);
+ writel(0x3, IOMUXC_BASE_ADDR + 0x21C);
+ writel(0x85, IOMUXC_BASE_ADDR + 0x60C);
// 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1.
- writel(0x0, IOMUXC_BASE_ADDR + 0x224);
- writel(0x185, IOMUXC_BASE_ADDR + 0x6D4);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x218);
+ writel(0x185, IOMUXC_BASE_ADDR + 0x608);
} else if (dev->ss == 1) {
// de-select SS0 of instance: ecspi1.
- writel(0x3, IOMUXC_BASE_ADDR + 0x224);
- writel(0x85, IOMUXC_BASE_ADDR + 0x6D4);
+ writel(0x3, IOMUXC_BASE_ADDR + 0x218);
+ writel(0x85, IOMUXC_BASE_ADDR + 0x608);
// 000: Select mux mode: ALT0 mux port: SS1 of instance: ecspi1.
- writel(0x0, IOMUXC_BASE_ADDR + 0x228);
- writel(0x105, IOMUXC_BASE_ADDR + 0x6D8);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x21C);
+ writel(0x105, IOMUXC_BASE_ADDR + 0x60C);
}
// 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1.
- writel(0x0, IOMUXC_BASE_ADDR + 0x22C);
- writel(0x180, IOMUXC_BASE_ADDR + 0x6DC);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x220);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x610);
// 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1.
- writel(0x0, IOMUXC_BASE_ADDR + 0x230);
- writel(0x105, IOMUXC_BASE_ADDR + 0x6E0);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x224);
+ writel(0x105, IOMUXC_BASE_ADDR + 0x614);
break;
case CSPI2_BASE_ADDR:
default:
projects / karo-tx-redboot.git / blobdiff