STK5 Release 1.10

[karo-tx-redboot.git] / packages / hal / arm / mx51 / karo / v1_0 / include / hal_platform_setup.h

diff --git a/packages/hal/arm/mx51/karo/v1_0/include/hal_platform_setup.h b/packages/hal/arm/mx51/karo/v1_0/include/hal_platform_setup.h
index c01422cc90f45015f44b121388633e104bea2e69..60117ce3c34a3da7c4100deba39ad443546e897c 100644 (file)
--- a/packages/hal/arm/mx51/karo/v1_0/include/hal_platform_setup.h
+++ b/packages/hal/arm/mx51/karo/v1_0/include/hal_platform_setup.h
@@ -487,7 +487,8 @@ _KARO_CECFG_END:
 #define ESDCTL_VAL     (0x80000000 | (SREFR << 28) | (RA_BITS << 24) | (CA_BITS << 20) | \
                         (DSIZ << 16) | (SRT << 14) | (PWDT << 12))
 
-#define SDRAM_CLK      200
+#define SDRAM_CLK      CYGNUM_HAL_ARM_TX51_SDRAM_CLK
+
 #define NS_TO_CK(ns)   (((ns) * SDRAM_CLK + 999) / 1000)
 
        .macro          CK_VAL, name, clks, offs
@@ -506,32 +507,32 @@ _KARO_CECFG_END:
        .endif
        .endm
 
-#if SDRAM_SIZE <= SZ_128M
+#if SDRAM_CLK < 200
 /* MT46H32M32LF-6 */
-NS_VAL tRFC,   125, 10 /* clks - 10 (0..15) */
-NS_VAL tXSR,   138, 25 /* clks - 25 (0..15) */
-NS_VAL tXP,    25, 1   /* clks - 1 (0..7)  */
-CK_VAL tWTR,   1, 1    /* clks - 1 (0..1)  */
-NS_VAL tRP,    18, 2   /* clks - 2 (0..3)  */
-CK_VAL tMRD,   2, 1    /* clks - 1 (0..3)  */
-NS_VAL tWR,    15, 2   /* clks - 2 (0..1)  */
-NS_VAL tRAS,   42, 1   /* clks - 1 (0..15) */
-NS_VAL tRRD,   12, 1   /* clks - 1 (0..3)  */
-NS_VAL tRCD,   18, 1   /* clks - 1 (0..7) */
-NS_VAL tRC,    60, 1   /* 0: 20 *: clks - 1 (0..15) */
+NS_VAL tRFC, 125, 10   /* clks - 10 (0..15) */
+NS_VAL tXSR, 138, 25   /* clks - 25 (0..15) */
+NS_VAL tXP,   25,  1   /* clks - 1 (0..7)  */
+CK_VAL tWTR,   1,  1   /* clks - 1 (0..1)  */
+NS_VAL tRP,   18,  2   /* clks - 2 (0..3)  */
+CK_VAL tMRD,   2,  1   /* clks - 1 (0..3)  */
+NS_VAL tWR,   15,  2   /* clks - 2 (0..1)  */
+NS_VAL tRAS,  42,  1   /* clks - 1 (0..15) */
+NS_VAL tRRD,  12,  1   /* clks - 1 (0..3)  */
+NS_VAL tRCD,  18,  1   /* clks - 1 (0..7) */
+NS_VAL tRC,   60,  1   /* 0: 20 *: clks - 1 (0..15) */
 #else
 /* MT46H64M32LF-5 or -6 */
-NS_VAL tRFC,   72, 10  /* clks - 10 (0..15) */
-NS_VAL tXSR,   113, 25 /* clks - 25 (0..15) */
-CK_VAL tXP,    2, 1    /* clks - 1 (0..7)  */
-CK_VAL tWTR,   2, 1    /* clks - 1 (0..1)  */
-NS_VAL tRP,    18, 2   /* clks - 2 (0..3)  */
-CK_VAL tMRD,   2, 1    /* clks - 1 (0..3)  */
-NS_VAL tWR,    15, 2   /* clks - 2 (0..1)  */
-NS_VAL tRAS,   42, 1   /* clks - 1 (0..15) */
-NS_VAL tRRD,   12, 1   /* clks - 1 (0..3)  */
-NS_VAL tRCD,   18, 1   /* clks - 1 (0..7) */
-NS_VAL tRC,    60, 1   /* 0: 20 *: clks - 1 (0..15) */
+NS_VAL tRFC,  72, 10   /* clks - 10 (0..15) */
+NS_VAL tXSR, 113, 25   /* clks - 25 (0..15) */
+CK_VAL tXP,    2,  1   /* clks - 1 (0..7)  */
+CK_VAL tWTR,   2,  1   /* clks - 1 (0..1)  */
+NS_VAL tRP,   18,  2   /* clks - 2 (0..3)  */
+CK_VAL tMRD,   2,  1   /* clks - 1 (0..3)  */
+NS_VAL tWR,   15,  2   /* clks - 2 (0..1)  */
+NS_VAL tRAS,  42,  1   /* clks - 1 (0..15) */
+NS_VAL tRRD,  12,  1   /* clks - 1 (0..3)  */
+NS_VAL tRCD,  18,  1   /* clks - 1 (0..7) */
+NS_VAL tRC,   60,  1   /* 0: 20 *: clks - 1 (0..15) */
 #endif
 
 #define ESDCFG_VAL     ((tRFC << 28) | (tXSR << 24) | (tXP << 21) | \
@@ -605,7 +606,7 @@ CCM_CBCDR_VAL2:             .word   0x13239145
 #if SDRAM_CLK == 200
 CCM_CBCDR_VAL3:                .word   0x59E35100
 #else
-CCM_CBCDR_VAL3:                .word   0x21E35100
+CCM_CBCDR_VAL3:                .word   0x01E35100
 #endif
 CCM_CBCMR_VAL1:                .word   0x000010C0
 CCM_CBCMR_VAL2:                .word   0x000020C0