STK5 Release 1.10

[karo-tx-redboot.git] / packages / hal / arm / mx51 / var / v2_0 / src / cmds.c

diff --git a/packages/hal/arm/mx51/var/v2_0/src/cmds.c b/packages/hal/arm/mx51/var/v2_0/src/cmds.c
index ee6af36cceb3bc200e05b2d649eaa408bcff8d7c..ec2ef66ef7706d20b70479b00e9ed5d3027ecb96 100644 (file)
--- a/packages/hal/arm/mx51/var/v2_0/src/cmds.c
+++ b/packages/hal/arm/mx51/var/v2_0/src/cmds.c
@@ -464,7 +464,13 @@ print_clock:
        diag_printf("========================================\n");
        diag_printf("%-16d%-16d%-16d\n\n", pll_clock(PLL1), pll_clock(PLL2),
                                pll_clock(PLL3));
-       diag_printf("CPU\t\tAHB\t\tIPG\t\tEMI_CLK\n");
+       diag_printf("AXI_A\t\tAXI_B\t\tEMI_SLOW_CLK\n");
+       diag_printf("========================================================\n");
+       diag_printf("%-16d%-16d%-16d\n\n",
+                               get_main_clock(AXI_A_CLK),
+                               get_main_clock(AXI_B_CLK),
+                               get_main_clock(EMI_SLOW_CLK));
+       diag_printf("CPU\t\tAHB\t\tIPG\t\tDDR_CLK\n");
        diag_printf("========================================================\n");
        diag_printf("%-16d%-16d%-16d%-16d\n\n",
                                get_main_clock(CPU_CLK),
@@ -593,17 +599,38 @@ u32 get_main_clock(enum main_clocks clk)
                pll = pll_clock(PLL1);
                ret_val = pll / (pdf + 1);
                break;
+
        case AHB_CLK:
                max_pdf = (cbcdr >> 10) & 0x7;
                pll = get_periph_clk();
                ret_val = pll / (max_pdf + 1);
                break;
+
+       case AXI_A_CLK:
+               pdf = (cbcdr >> 16) & 0x7;
+               pll = get_periph_clk();
+               ret_val = pll / (pdf + 1);
+               break;
+
+       case AXI_B_CLK:
+               pdf = (cbcdr >> 19) & 0x7;
+               pll = get_periph_clk();
+               ret_val = pll / (pdf + 1);
+               break;
+
+       case EMI_SLOW_CLK:
+               pll = get_emi_core_clk();
+               pdf = (cbcdr >> 22) & 0x7;
+               ret_val = pll / (pdf + 1);
+               break;
+
        case IPG_CLK:
                max_pdf = (cbcdr >> 10) & 0x7;
                ipg_pdf = (cbcdr >> 8) & 0x3;
                pll = get_periph_clk();
                ret_val = pll / ((max_pdf + 1) * (ipg_pdf + 1));
                break;
+
        case IPG_PER_CLK:
                clk_sel = cbcmr & 1;
                if (clk_sel == 0) {
@@ -622,6 +649,7 @@ u32 get_main_clock(enum main_clocks clk)
                        ret_val = pll / ((max_pdf + 1) * (ipg_pdf + 1));
                }
                break;
+
        case DDR_CLK:
                if (cbcdr & (1 << 30)) {
                        pll = pll_clock(PLL1);
@@ -647,12 +675,14 @@ u32 get_main_clock(enum main_clocks clk)
 
                ret_val = pll / (pdf + 1);
                break;
+
        case NFC_CLK:
                pdf = (cbcdr >> 22) & 0x7;
                nfc_pdf = (cbcdr >> 13) & 0x7;
                pll = get_emi_core_clk();
                ret_val = pll / ((pdf + 1) * (nfc_pdf + 1));
                break;
+
        case USB_CLK:
                clk_sel = (cscmr1 >> 22) & 3;
                if (clk_sel == 0) {
@@ -668,6 +698,7 @@ u32 get_main_clock(enum main_clocks clk)
                max_pdf = (cscdr1 >> 6) & 0x3;
                ret_val = pll / ((pdf + 1) * (max_pdf + 1));
                break;
+
        default:
                diag_printf("Unknown clock: %d\n", clk);
                return ERR_WRONG_CLK;