arm: mx53: karo: select core voltage according to frequency range rather than single...

[karo-tx-redboot.git] / packages / hal / arm / mx53 / karo / v1_0 / include / hal_platform_setup.h

diff --git a/packages/hal/arm/mx53/karo/v1_0/include/hal_platform_setup.h b/packages/hal/arm/mx53/karo/v1_0/include/hal_platform_setup.h
index de331e089b410264982ea1c06dcd4c0ba06737a8..fed8b8dfad92411c77650be9ebf9193323789144 100644 (file)
--- a/packages/hal/arm/mx53/karo/v1_0/include/hal_platform_setup.h
+++ b/packages/hal/arm/mx53/karo/v1_0/include/hal_platform_setup.h
@@ -54,10 +54,10 @@
 
 #define SDRAM_CLK                      400
 
-#define DEBUG_LED_BIT          20
-#define LED_GPIO_BASE          GPIO2_BASE_ADDR
-#define LED_MUX_OFFSET         0x174
-#define LED_MUX_MODE           0x11
+#define DEBUG_LED_BIT                  20
+#define LED_GPIO_BASE                  GPIO2_BASE_ADDR
+#define LED_MUX_OFFSET                 0x174
+#define LED_MUX_MODE                   0x11
 
 #ifdef CYGOPT_HAL_ARM_TX53_DEBUG
 #define LED_ON                         bl      led_on
@@ -480,7 +480,7 @@ GPU Memory                       0xF8020000 0xF805FFFF
        .endif
        .endm
 
-#define MXC_DCD_ITEM(addr, val)                mxc_dcd_item    addr, val
+#define MXC_DCD_ITEM(addr, val)                mxc_dcd_item    (addr), (val)
 
 #define MXC_DCD_CMD_SZ_BYTE            1
 #define MXC_DCD_CMD_SZ_SHORT           2
@@ -656,8 +656,8 @@ CK_MAX      tCKSRE, NS_TO_CK(10), 5, 0, 7
        .iflt   tWR - 7
        .set    mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ |    \
                        (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
-                       ((tWR + 1 - 4) << 9) |                          \
-                       ((((tCL + 3) - 4) & 0x7) << 4) |                \
+                       ((tWR + 1 - 4) << 9) |                          \
+                       ((((tCL + 3) - 4) & 0x7) << 4) |                \
                        ((((tCL + 3) - 4) & 0x8) >> 1))
        .else
        .set    mr0_val, ((1 << 8) /* DLL Reset */ |                    \
@@ -677,7 +677,7 @@ CK_MAX      tCKSRE, NS_TO_CK(10), 5, 0, 7
                                         (Rtt_WR << 9) /* dynamic ODT */ |      \
                                         (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \
                                         (1 << 6) | /* ASR: Automatic Self Refresh */\
-                                        (((tCWL + 2) - 5) << 3) |              \
+                                        (((tCWL + 2) - 5) << 3) |              \
                                        0)
 #define mr3_val                                0