/* Physical Virtual Size Attributes access permissions Function */
/* Base Base MB cached? buffered? */
/* xxx00000 xxx00000 */
- X_ARM_MMU_SECTION(0x000, 0x200, 0x001, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Boot Rom */
-// X_ARM_MMU_SECTION(0x1FF, 0x1FF, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IRAM */
- X_ARM_MMU_SECTION(0x180, 0x180, 0x080, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IPUv3D */
+ X_ARM_MMU_SECTION(0x000, 0xfff, 0x001, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Boot Rom */
+ X_ARM_MMU_SECTION(0xF80, 0xF80, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IRAM */
+ X_ARM_MMU_SECTION(0x180, 0x480, 0x080, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IPUv3D */
X_ARM_MMU_SECTION(0x500, 0x500, 0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Internal Registers */
X_ARM_MMU_SECTION(SD_P0, 0x000, SD_S0, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
X_ARM_MMU_SECTION(SD_P0, SD_C0, SD_S0, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
X_ARM_MMU_SECTION(SD_P1, SD_C1, SD_S1, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
X_ARM_MMU_SECTION(SD_P1, SD_U1, SD_S1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
/* make sure the last MiB in the upper bank of SDRAM (where RedBoot resides)
- * has a unity mapping (required when switching MMU on) */
+ * has a unity mapping (required when switching MMU on).
+ * This mapping will overwrite the last MiB of the uncached mapping above
+ * which will be restored in plf_hardware_init().
+ */
X_ARM_MMU_SECTION(SD_HI, SD_HI, 0x001, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RO_RO); /* SDRAM bank1 identity mapping */
#endif
X_ARM_MMU_SECTION(0xF40, 0xF40, 0x040, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control & NFC buffer */
void plf_hardware_init(void)
{
#ifdef RAM_BANK1_SIZE
- /* destroy mapping for high area in SDRAM */
- X_ARM_MMU_SECTION(SD_HI, 0, 0, 0, 0, ARM_ACCESS_PERM_NONE_NONE);
+ /* overwrite temporary mapping for high area in SDRAM with actual mapping */
+ X_ARM_MMU_SECTION(SD_P0 + SD_S0 - 1, SD_U0 + SD_S0 - 1, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
+ HAL_CACHE_FLUSH_ALL();
#endif
uart_gpio_init();
fec_gpio_init();
stack_ptr = old_stack;
}
-#if CYGNUM_HAL_ARM_TX53_SDRAM_TYPE == 2
-#define PMIC_NAME "LP3972"
-#elif CYGNUM_HAL_ARM_TX53_SDRAM_TYPE == 3
#define PMIC_NAME "LT3598"
-#else
-#error Bad CYGNUM_HAL_ARM_TX53_SDRAM_TYPE
-#endif
static int pmic_reg_read(cyg_uint8 reg)
{
if (ret < 0)
diag_printf("Failed to read %s reg 0x%02x %d\n", PMIC_NAME,
reg, ret);
+#ifdef DEBUG
+ else
+ diag_printf("read %02x from reg %02x\n", ret, reg);
+#endif
return ret;
}
if (ret)
diag_printf("Failed to write 0x%02x to %s reg 0x%02x: %d\n",
val, PMIC_NAME, reg, ret);
+#ifdef DEBUG
+ else
+ diag_printf("wrote %02x to reg %02x\n", val, reg);
+#endif
return ret;
}
-#if CYGNUM_HAL_ARM_TX53_SDRAM_TYPE == 2
-int tx53_fuse_voltage(int on)
-{
- int ret;
-
- ret = pmic_reg_read(0x81);
- if (ret < 0)
- return ret;
-
- /* Try to enable FUSE_VDD by asserting LP3972 GPIO1 */
- ret = (ret & ~0x3) | (on ? 1 : 3);
- ret = pmic_reg_write(0x81, ret);
- if (ret) {
- return ret;
- }
- ret = pmic_reg_read(0x81);
- if ((ret & 0x3) != (on ? 0x1 : 0x3)) {
- return -EIO;
- }
- return 0;
-}
-
-#define CORE_VOLTAGE_HIGH 0x1b
-#define CORE_VOLTAGE_LOW 0x03
-#if CYGNUM_HAL_ARM_TX53_SDRAM_SIZE == SZ_512M
-#define SDRAM_SIZE_STR '0'
-#else
-#if CYGNUM_HAL_ARM_TX53_CPU_CLK == 1000
-#define SDRAM_SIZE_STR '2'
-#else
-#define SDRAM_SIZE_STR '1'
-#endif /* CYGNUM_HAL_ARM_TX53_CPU_CLK == 1000 */
-#endif /* CYGNUM_HAL_ARM_TX53_SDRAM_SIZE == SZ512M */
-
-#elif CYGNUM_HAL_ARM_TX53_SDRAM_TYPE == 3
int tx53_fuse_voltage(int on)
{
int ret;
+ int retries = 0;
if (on) {
ret = pmic_reg_read(0x33);
return ret;
if (!(ret & (1 << 6))) {
- ret |= 1 << 6; /* LDO4 Startup: don't wait for output < 300mV */
- ret = pmic_reg_write(0x12, ret);
+ ret = pmic_reg_write(0x12, ret | (1 << 6));
if (ret)
- return -EIO;
- ret = pmic_reg_read(0x12);
- if (!(ret & (1 << 6))) {
- diag_printf("Could not set LT3589 LDO4 Startup control\n");
- return -EIO;
+ return ret;
+ }
+
+ /* enable SW regulator control and all regulators */
+ ret = pmic_reg_write(0x10, 0xff);
+ if (ret)
+ return ret;
+
+ for (;;) {
+ ret = pmic_reg_read(0x13);
+ if (ret < 0)
+ return ret;
+ if (ret & (1 << 7))
+ break;
+
+#ifdef DEBUG
+ if (retries == 0)
+ diag_printf("Waiting for LDO4 PGOOD\n");
+#endif
+ HAL_DELAY_US(100);
+ if (++retries >= 1000) {
+ diag_printf("Failed to enable LDO4\n");
+ return -ETIMEDOUT;
}
}
+ } else {
+ ret = pmic_reg_write(0x10, 0xbf);
+ if (ret)
+ return ret;
+
+ ret = pmic_reg_read(0x12);
+ if (ret < 0)
+ return ret;
+ if (ret & (1 << 6)) {
+ ret = pmic_reg_write(0x12, ret & ~(1 << 6));
+ if (ret)
+ return ret;
+ }
}
- /* enable SW regulator control and all regulators (except LDO4, if !on) */
- ret = pmic_reg_write(0x10, 0xbf | (!!on << 6));
- if (ret)
- return ret;
ret = pmic_reg_read(0x10);
if (ret < 0)
return ret;
if (!(ret & (1 << 6)) ^ !on) {
- diag_printf("Could not enable LT3589 LDO4 output\n");
+ diag_printf("Could not %sable LT3589 LDO4 output\n",
+ on ? "en" : "dis");
return -EIO;
}
return 0;
}
-#define CORE_VOLTAGE_HIGH 0x1c
-#define CORE_VOLTAGE_LOW 0x17
-#if CYGNUM_HAL_ARM_TX53_SDRAM_SIZE == SZ_512M
-#define SDRAM_SIZE_STR '0'
-#else
-#define SDRAM_SIZE_STR '1'
-#endif
-#endif
+#define LT3589_PGOOD_MASK (1 << 5)
+#define LT3589_SLEW_RATE(n) (((n) & 3) << 6)
+#define CORE_VOLTAGE_1200 0x1e
+#define CORE_VOLTAGE_1000 0x19
+#define CORE_VOLTAGE_800 0x13
-void increase_core_voltage(bool high)
+int adjust_core_voltage(unsigned int clock)
{
int ret;
- const int volt = high ? CORE_VOLTAGE_HIGH : CORE_VOLTAGE_LOW;
+ int volt;
+ int retries = 0;
+
+ switch (clock) {
+ case 1200:
+ volt = CORE_VOLTAGE_1200;
+ break;
+
+ case 1000:
+ volt = CORE_VOLTAGE_1000;
+ break;
+
+ case 800:
+ volt = CORE_VOLTAGE_800;
+ break;
+
+ default:
+ if (clock > 1200) {
+ diag_printf("No core voltage assigned for %u MHz core clock\n",
+ clock);
+ return -EINVAL;
+ }
+ volt = CORE_VOLTAGE_800;
+ }
ret = pmic_reg_read(0x23);
if (ret < 0) {
- diag_printf("Failed to read core voltage: %d\n", ret);
- return;
+ return ret;
}
- ret = pmic_reg_write(0x23, volt);
+ ret = pmic_reg_write(0x23, volt | LT3589_SLEW_RATE(3) | LT3589_PGOOD_MASK);
if (ret < 0) {
- diag_printf("Failed to write core voltage: %d\n", ret);
+ return ret;
}
-}
-static void display_board_type(void)
-{
- char cpu_freq;
- const char *ddr_type = _stringify(CYGNUM_HAL_ARM_TX53_SDRAM_TYPE);
-
- switch (CYGNUM_HAL_ARM_TX53_CPU_CLK) {
- case 800:
- cpu_freq = '8';
- break;
+ ret = pmic_reg_read(0x20);
+ if (ret < 0)
+ return ret;
- case 1000:
- cpu_freq = '1';
- break;
+ /* Select V1 reference and enable slew */
+ ret = pmic_reg_write(0x20, (ret & ~(1 << 1)) | (1 << 0));
+ if (ret)
+ return ret;
- default:
- cpu_freq = '?';
- }
+ do {
+ ret = pmic_reg_read(0x20);
+ if (ret < 0)
+ return ret;
+ if (++retries >= 1000)
+ return -ETIMEDOUT;
+ HAL_DELAY_US(100);
+ } while (ret & (1 << 0));
+ return ret;
+}
- diag_printf("\nBoard Type: Ka-Ro TX53-%c%c%s%c\n",
- cpu_freq, CYGNUM_HAL_ARM_TX53_SDRAM_TYPE == 2 ? '0' : 'x',
- ddr_type, SDRAM_SIZE_STR);
+static void display_board_type(void)
+{
+ diag_printf("\nBoard Type: Ka-Ro TX53 v3\n");
}
static void display_board_info(void)
projects / karo-tx-redboot.git / blobdiff