X-Git-Url: https://git.karo-electronics.de/?p=karo-tx-redboot.git;a=blobdiff_plain;f=packages%2Fhal%2Farm%2Fmx25%2Fvar%2Fv2_0%2Fsrc%2Fcmds.c;h=ef960cd26b8057aeb137b915a2209ccde16e3b80;hp=c1f39bd21c72793fc442de9e5b2de9b4cc9076d0;hb=d018e3f678d0bbc67e64e26c78f3926ef6489826;hpb=06e00636bab554f0b6a5c836eeba82088236f1f4 diff --git a/packages/hal/arm/mx25/var/v2_0/src/cmds.c b/packages/hal/arm/mx25/var/v2_0/src/cmds.c index c1f39bd2..ef960cd2 100644 --- a/packages/hal/arm/mx25/var/v2_0/src/cmds.c +++ b/packages/hal/arm/mx25/var/v2_0/src/cmds.c @@ -107,19 +107,23 @@ static void clock_setup(int argc,char *argv[]) arm_src = 0; arm_div = 1 - 1; break; + case 399: arm_src = 1; arm_div = 1 - 1; break; + case 199: case 200: arm_src = 1; arm_div = 2 - 1; break; + case 133: arm_src = 1; arm_div = 3 - 1; break; + default: diag_printf("Illegal core clock value specified\n"); return; @@ -207,14 +211,17 @@ u32 get_main_clock(enum main_clocks clk) div = ((cctl >> CRM_CCTL_ARM_OFFSET) & 3) + 1; ret_val /= div; break; + case AHB_CLK: div = ((cctl >> CRM_CCTL_AHB_OFFSET) & 3) + 1; ret_val = get_main_clock(CPU_CLK) / div; break; + case IPG_CLK: case IPG_PER_CLK: ret_val = get_main_clock(AHB_CLK) / 2; break; + default: diag_printf("Unknown clock: %d\n", clk); } @@ -236,10 +243,26 @@ u32 get_peri_clock(enum peri_clocks clk) div = (pcdr >> 24) + 1; ret_val = get_main_clock(AHB_CLK) / div; break; + case SPI1_CLK: case SPI2_CLK: ret_val = get_main_clock(IPG_CLK); break; + + case LCDC_CLK: + writel(readl(CCM_BASE_ADDR + CLKCTL_MCR) | (1 << 7), + CCM_BASE_ADDR + CLKCTL_MCR); + pcdr = readl(CCM_BASE_ADDR + CLKCTL_PCDR1); + pcdr &= ~(0xff << 24); + writel(pcdr, CCM_BASE_ADDR + CLKCTL_PCDR1); + div = (pcdr >> 24) + 1; + if (readl(CCM_BASE_ADDR + CLKCTL_MCR) & (1 << 7)) { + ret_val = pll_clock(USB_PLL) / div; + } else { + ret_val = get_main_clock(AHB_CLK) / div; + } + break; + default: diag_printf("%s(): This clock: %d not supported yet\n", __FUNCTION__, clk);