X-Git-Url: https://git.karo-electronics.de/?p=karo-tx-redboot.git;a=blobdiff_plain;f=packages%2Fhal%2Farm%2Fmx27%2Fvar%2Fv2_0%2Finclude%2Fhal_var_ints.h;h=504d9f4902d087a8f47e851a89d98979cda31d49;hp=c8191d3a7dd21e363881577f17d8272a49da0877;hb=6ff32795;hpb=991357cee5b6e631fd70adb139ee5b28ff42e34d diff --git a/packages/hal/arm/mx27/var/v2_0/include/hal_var_ints.h b/packages/hal/arm/mx27/var/v2_0/include/hal_var_ints.h index c8191d3a..504d9f49 100644 --- a/packages/hal/arm/mx27/var/v2_0/include/hal_var_ints.h +++ b/packages/hal/arm/mx27/var/v2_0/include/hal_var_ints.h @@ -41,87 +41,90 @@ //####ECOSGPLCOPYRIGHTEND#### //========================================================================== -#include // registers +#include // registers -#define CYGNUM_HAL_INTERRUPT_GPIO0 0 -#define CYGNUM_HAL_INTERRUPT_GPIO1 1 -#define CYGNUM_HAL_INTERRUPT_GPIO2 2 -#define CYGNUM_HAL_INTERRUPT_GPIO3 3 -#define CYGNUM_HAL_INTERRUPT_GPIO4 4 -#define CYGNUM_HAL_INTERRUPT_GPIO5 5 -#define CYGNUM_HAL_INTERRUPT_GPIO6 6 -#define CYGNUM_HAL_INTERRUPT_GPIO7 7 -#define CYGNUM_HAL_INTERRUPT_GPIO8 8 -#define CYGNUM_HAL_INTERRUPT_GPIO9 9 -#define CYGNUM_HAL_INTERRUPT_GPIO10 10 -#define CYGNUM_HAL_INTERRUPT_GPIO 11 // Don't use directly! -#define CYGNUM_HAL_INTERRUPT_LCD 12 -#define CYGNUM_HAL_INTERRUPT_UDC 13 -#define CYGNUM_HAL_INTERRUPT_UART1 15 -#define CYGNUM_HAL_INTERRUPT_UART2 16 -#define CYGNUM_HAL_INTERRUPT_UART3 17 -#define CYGNUM_HAL_INTERRUPT_UART4 17 -#define CYGNUM_HAL_INTERRUPT_MCP 18 -#define CYGNUM_HAL_INTERRUPT_SSP 19 -#define CYGNUM_HAL_INTERRUPT_TIMER0 26 -#define CYGNUM_HAL_INTERRUPT_TIMER1 27 -#define CYGNUM_HAL_INTERRUPT_TIMER2 28 -#define CYGNUM_HAL_INTERRUPT_TIMER3 29 -#define CYGNUM_HAL_INTERRUPT_HZ 30 -#define CYGNUM_HAL_INTERRUPT_ALARM 31 +#define CYGNUM_HAL_INTERRUPT_GPIO0 0 +#define CYGNUM_HAL_INTERRUPT_GPIO1 1 +#define CYGNUM_HAL_INTERRUPT_GPIO2 2 +#define CYGNUM_HAL_INTERRUPT_GPIO3 3 +#define CYGNUM_HAL_INTERRUPT_GPIO4 4 +#define CYGNUM_HAL_INTERRUPT_GPIO5 5 +#define CYGNUM_HAL_INTERRUPT_GPIO6 6 +#define CYGNUM_HAL_INTERRUPT_GPIO7 7 +#define CYGNUM_HAL_INTERRUPT_GPIO8 8 +#define CYGNUM_HAL_INTERRUPT_GPIO9 9 +#define CYGNUM_HAL_INTERRUPT_GPIO10 10 +#define CYGNUM_HAL_INTERRUPT_GPIO 11 // Don't use directly! +#define CYGNUM_HAL_INTERRUPT_LCD 12 +#define CYGNUM_HAL_INTERRUPT_UDC 13 +#define CYGNUM_HAL_INTERRUPT_UART1 15 +#define CYGNUM_HAL_INTERRUPT_UART2 16 +#define CYGNUM_HAL_INTERRUPT_UART3 17 +#define CYGNUM_HAL_INTERRUPT_UART4 17 +#define CYGNUM_HAL_INTERRUPT_MCP 18 +#define CYGNUM_HAL_INTERRUPT_SSP 19 +#define CYGNUM_HAL_INTERRUPT_TIMER0 26 +#define CYGNUM_HAL_INTERRUPT_TIMER1 27 +#define CYGNUM_HAL_INTERRUPT_TIMER2 28 +#define CYGNUM_HAL_INTERRUPT_TIMER3 29 +#define CYGNUM_HAL_INTERRUPT_HZ 30 +#define CYGNUM_HAL_INTERRUPT_ALARM 31 // GPIO bits 31..11 can generate interrupts as well, but they all // end up clumped into interrupt signal #11. Using the symbols // below allow for detection of these separately. -#define CYGNUM_HAL_INTERRUPT_GPIO11 (32+11) -#define CYGNUM_HAL_INTERRUPT_GPIO12 (32+12) -#define CYGNUM_HAL_INTERRUPT_GPIO13 (32+13) -#define CYGNUM_HAL_INTERRUPT_GPIO14 (32+14) -#define CYGNUM_HAL_INTERRUPT_GPIO15 (32+15) -#define CYGNUM_HAL_INTERRUPT_GPIO16 (32+16) -#define CYGNUM_HAL_INTERRUPT_GPIO17 (32+17) -#define CYGNUM_HAL_INTERRUPT_GPIO18 (32+18) -#define CYGNUM_HAL_INTERRUPT_GPIO19 (32+19) -#define CYGNUM_HAL_INTERRUPT_GPIO20 (32+20) -#define CYGNUM_HAL_INTERRUPT_GPIO21 (32+21) -#define CYGNUM_HAL_INTERRUPT_GPIO22 (32+22) -#define CYGNUM_HAL_INTERRUPT_GPIO23 (32+23) -#define CYGNUM_HAL_INTERRUPT_GPIO24 (32+24) -#define CYGNUM_HAL_INTERRUPT_GPIO25 (32+25) -#define CYGNUM_HAL_INTERRUPT_GPIO26 (32+26) -#define CYGNUM_HAL_INTERRUPT_GPIO27 (32+27) +#define CYGNUM_HAL_INTERRUPT_GPIO11 (32 + 11) +#define CYGNUM_HAL_INTERRUPT_GPIO12 (32 + 12) +#define CYGNUM_HAL_INTERRUPT_GPIO13 (32 + 13) +#define CYGNUM_HAL_INTERRUPT_GPIO14 (32 + 14) +#define CYGNUM_HAL_INTERRUPT_GPIO15 (32 + 15) +#define CYGNUM_HAL_INTERRUPT_GPIO16 (32 + 16) +#define CYGNUM_HAL_INTERRUPT_GPIO17 (32 + 17) +#define CYGNUM_HAL_INTERRUPT_GPIO18 (32 + 18) +#define CYGNUM_HAL_INTERRUPT_GPIO19 (32 + 19) +#define CYGNUM_HAL_INTERRUPT_GPIO20 (32 + 20) +#define CYGNUM_HAL_INTERRUPT_GPIO21 (32 + 21) +#define CYGNUM_HAL_INTERRUPT_GPIO22 (32 + 22) +#define CYGNUM_HAL_INTERRUPT_GPIO23 (32 + 23) +#define CYGNUM_HAL_INTERRUPT_GPIO24 (32 + 24) +#define CYGNUM_HAL_INTERRUPT_GPIO25 (32 + 25) +#define CYGNUM_HAL_INTERRUPT_GPIO26 (32 + 26) +#define CYGNUM_HAL_INTERRUPT_GPIO27 (32 + 27) -#define CYGNUM_HAL_INTERRUPT_NONE -1 +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX (27 + 32) -#define CYGNUM_HAL_ISR_MIN 0 -#define CYGNUM_HAL_ISR_MAX (27+32) - -#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1) +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1) // The vector used by the Real time clock -#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0 +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0 // The vector used by the Ethernet -#define CYGNUM_HAL_INTERRUPT_ETH CYGNUM_HAL_INTERRUPT_GPIO0 +#define CYGNUM_HAL_INTERRUPT_ETH CYGNUM_HAL_INTERRUPT_GPIO0 // method for reading clock interrupt latency #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY externC void hal_clock_latency(cyg_uint32 *); -# define HAL_CLOCK_LATENCY( _pvalue_ ) \ - hal_clock_latency( (cyg_uint32 *)(_pvalue_) ) +# define HAL_CLOCK_LATENCY( _pvalue_ ) \ + hal_clock_latency( (cyg_uint32 *)(_pvalue_) ) #endif //---------------------------------------------------------------------------- // Reset. -#define HAL_PLATFORM_RESET() \ - CYG_MACRO_START \ - *(volatile unsigned long *)SOC_CRM_PCCR1 |= 0x01000000; \ - *(volatile unsigned short *)SOC_WDOG_BASE = \ - (*(volatile unsigned short *)SOC_WDOG_BASE & ~(1 << 4)) | (1 << 2); \ - /* hang here forever if reset fails */ \ - while (1) { } \ - CYG_MACRO_END +#define HAL_PLATFORM_RESET() \ + CYG_MACRO_START \ + \ + /* Enable WDT clock */ \ + writel(readl(SOC_CRM_PCCR1) | (1 << 24), SOC_CRM_PCCR1); \ + /* Enable FPM */ \ + writel(readl(SOC_CRM_CSCR) | (1 << 2), SOC_CRM_CSCR); \ + HAL_DELAY_US(1000); \ + /* Assert Softreset */ \ + writew(readw(SOC_WDOG_BASE) & ~(1 << 4), SOC_WDOG_BASE); \ + /* hang here forever if reset fails */ \ + while (1) { } \ + CYG_MACRO_END // Fallback (never really used) #define HAL_PLATFORM_RESET_ENTRY 0x00000000