--- /dev/null
+# ====================================================================
+#
+# hal_arm_board.cdl
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+
+cdl_package CYGPKG_HAL_ARM_MX25_3STACK {
+ display "Freescale board"
+ parent CYGPKG_HAL_ARM_MX25
+ hardware
+ include_dir cyg/hal
+ define_header hal_arm_board.h
+ description "
+ This HAL platform package provides generic
+ support for the Freescale i.MX25 3-Stack Board."
+
+ compile board_misc.c board_diag.c
+ implements CYGINT_HAL_DEBUG_GDB_STUBS
+ implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+ implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+
+ implements CYGHWR_HAL_ARM_SOC_UART1
+
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_soc.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_board.h>"
+ puts $::cdl_header "#define HAL_PLATFORM_CPU \"i.MX25 \""
+ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Freescale\""
+ puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 1771"
+ puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK board_program_new_stack"
+ }
+
+ cdl_component CYG_HAL_STARTUP {
+ display "Startup type"
+ flavor data
+ default_value {"ROM"}
+ legal_values {"RAM" "ROM" "ROMRAM"}
+ no_define
+ define -file system.h CYG_HAL_STARTUP
+ description "
+ When targetting the eval board it is possible to build
+ the system for either RAM bootstrap or ROM bootstrap(s). Select
+ 'ram' when building programs to load into RAM using eCos GDB
+ stubs. Select 'rom' when building a stand-alone application
+ which will be put into ROM, or for the special case of
+ building the eCos GDB stubs themselves. Using ROMRAM will allow
+ the program to exist in ROM, but be copied to RAM during startup."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_DUART_UARTA {
+ display "ST16552 UARTA available as diagnostic/debug channel"
+ description "
+ The board has a ST16552 DUART chip. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_DUART_UARTB {
+ display "ST16552 UARTB available as diagnostic/debug channel"
+ description "
+ The board has a ST16552 DUART chip. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ display "Diagnostic serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the console port.
+ Note: this should match the value chosen for the GDB port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ display "GDB serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the GDB port.
+ Note: this should match the value chosen for the console port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the board"
+ flavor data
+ calculated 5
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ The board has three serial ports. This option
+ chooses which port will be used to connect to a host
+ running GDB."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+ display "Default console channel."
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ calculated 0
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Console serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ description "
+ The board has only three serial ports. This option
+ chooses which port will be used for console output."
+ }
+
+ cdl_component CYGBLD_GLOBAL_OPTIONS {
+ display "Global build options"
+ flavor none
+ no_define
+ description "
+ Global build options including control over
+ compiler flags, linker flags and choice of toolchain."
+
+
+ parent CYGPKG_NONE
+
+ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ display "Global command prefix"
+ flavor data
+ no_define
+ default_value { "arm-none-eabi" }
+ description "
+ This option specifies the command prefix used when
+ invoking the build tools."
+ }
+
+ cdl_option CYGBLD_GLOBAL_CFLAGS {
+ display "Global compiler flags"
+ flavor data
+ no_define
+ default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ description "
+ This option controls the global compiler flags which are used to
+ compile all packages by default. Individual packages may define
+ options which override these global flags."
+ }
+
+ cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ display "Global linker flags"
+ flavor data
+ no_define
+ default_value { "-Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" }
+ description "
+ This option controls the global linker flags. Individual
+ packages may define options which override these global flags."
+ }
+
+ cdl_option CYGBLD_BUILD_GDB_STUBS {
+ display "Build GDB stub ROM image"
+ default_value 0
+ requires { CYG_HAL_STARTUP == "ROM" }
+ requires CYGSEM_HAL_ROM_MONITOR
+ requires CYGBLD_BUILD_COMMON_GDB_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ no_define
+ description "
+ This option enables the building of the GDB stubs for the
+ board. The common HAL controls takes care of most of the
+ build process, but the final conversion from ELF image to
+ binary data is handled by the platform CDL, allowing
+ relocation of the data if necessary."
+
+ make -priority 320 {
+ <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
+ $(OBJCOPY) --remove-section=.fixed_vectors -O binary $< $@
+ }
+ }
+ }
+
+ cdl_component CYGPKG_HAL_ARM_BOARD_OPTIONS {
+ display "Freescale MXC Board build options"
+ flavor none
+ no_define
+ description "
+ Package specific build options including control over
+ compiler flags used only in building this package,
+ and details of which tests are built."
+
+ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the board HAL. These flags are used in addition
+ to the set of global flags."
+ }
+
+ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_REMOVE {
+ display "Suppressed compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the board HAL. These flags are removed from
+ the set of global flags if present."
+ }
+
+ }
+
+ cdl_component CYGHWR_MEMORY_LAYOUT {
+ display "Memory layout"
+ flavor data
+ no_define
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_board_ram" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" :
+ "arm_board_rom" }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ display "Memory layout linker script fragment"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.ldi>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.ldi>" :
+ "<pkgconf/mlt_arm_board_rom.ldi>" }
+ }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ display "Memory layout header file"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_H
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.h>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.h>" :
+ "<pkgconf/mlt_arm_board_rom.h>" }
+ }
+ }
+
+ cdl_option CYGSEM_HAL_ROM_MONITOR {
+ display "Behave as a ROM monitor"
+ flavor bool
+ default_value 0
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+ description "
+ Enable this option if this program is to be used as a ROM monitor,
+ i.e. applications will be loaded into RAM on the board, and this
+ ROM monitor may process exceptions or interrupts generated from the
+ application. This enables features such as utilizing a separate
+ interrupt stack when exceptions are generated."
+ }
+
+ cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ display "Work with a ROM monitor"
+ flavor booldata
+ legal_values { "Generic" "GDB_stubs" }
+ default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "RAM" }
+ description "
+ Support can be enabled for different varieties of ROM monitor.
+ This support changes various eCos semantics such as the encoding
+ of diagnostic output, or the overriding of hardware interrupt
+ vectors.
+ Firstly there is \"Generic\" support which prevents the HAL
+ from overriding the hardware vectors that it does not use, to
+ instead allow an installed ROM monitor to handle them. This is
+ the most basic support which is likely to be common to most
+ implementations of ROM monitor.
+ \"GDB_stubs\" provides support when GDB stubs are included in
+ the ROM monitor or boot ROM."
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ display "Redboot HAL options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+ description "
+ This option lists the target's requirements for a valid Redboot
+ configuration."
+
+ compile -library=libextras.a redboot_cmds.c
+
+ cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ display "Build Redboot ROM binary image"
+ active_if CYGBLD_BUILD_REDBOOT
+ default_value 1
+ no_define
+ description "This option enables the conversion of the Redboot ELF
+ image to a binary image suitable for ROM programming."
+
+ make -priority 325 {
+ <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+ $(OBJCOPY) -O binary $< $@
+ }
+ }
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_BOARD_OPTIONS {
+ display "Redboot HAL variant options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+
+ # RedBoot details
+ requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x80008000 }
+ define_proc {
+ puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00"
+ }
+ }
+}
--- /dev/null
+#ifndef CYGONCE_FSL_BOARD_H
+#define CYGONCE_FSL_BOARD_H
+
+//=============================================================================
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+
+#define CPLD_SPI_BASE CSPI1_BASE_ADDR
+#define CPLD_SPI_CHIP_SELECT_NO SPI_CTRL_CS0
+#define CPLD_SPI_CTRL_MODE_MASTER SPI_CTRL_MODE_MASTER
+
+#define PBC_BASE CS5_BASE_ADDR /* Peripheral Bus Controller */
+#define PBC_LED_CTRL (PBC_BASE + 0x20000)
+#define PBC_SB_STAT (PBC_BASE + 0x20008)
+#define PBC_ID_AAAA (PBC_BASE + 0x20040)
+#define PBC_ID_5555 (PBC_BASE + 0x20048)
+#define PBC_VERSION (PBC_BASE + 0x20050)
+#define PBC_ID_CAFE (PBC_BASE + 0x20058)
+#define PBC_INT_STAT (PBC_BASE + 0x20010)
+#define PBC_INT_MASK (PBC_BASE + 0x20038)
+#define PBC_INT_REST (PBC_BASE + 0x20020)
+#define PBC_SW_RESET (PBC_BASE + 0x20060)
+#define BOARD_CS_LAN_BASE (PBC_BASE + 0x300)
+#define BOARD_CS_UART_BASE (PBC_BASE + 0x8000)
+
+#define BOARD_FLASH_START CS0_BASE_ADDR
+#define REDBOOT_IMAGE_SIZE 0x40000
+
+#define SDRAM_BASE_ADDR CSD0_BASE_ADDR
+#define SDRAM_SIZE 0x08000000
+#define RAM_BANK0_BASE CSD0_BASE_ADDR
+#define RAM_BANK1_BASE CSD1_BASE_ADDR
+
+#ifdef CYGPKG_DEVS_MXC_SPI
+#define LAN92XX_REG_READ(reg_offset) ( \
+ cpld_reg_xfer(reg_offset, 0x0, 1) | \
+ (cpld_reg_xfer(reg_offset + 0x2, 0x0, 1) << 16))
+
+#define LAN92XX_REG_WRITE(reg_offset, val) do {\
+ cpld_reg_xfer(reg_offset, val, 0); \
+ (cpld_reg_xfer(reg_offset + 0x2, (val >> 16), 0)); } while (0)
+#endif
+
+#define FEC_PHY_ADDR 0x1
+
+#define LED_MAX_NUM 8
+#define LED_IS_ON(n) ((readw(PBC_LED_CTRL) & (1<<(n))) != 0)
+#define TURN_LED_ON(n) writew((readw(PBC_LED_CTRL)|(1<<(n))), PBC_LED_CTRL)
+#define TURN_LED_OFF(n) writew((readw(PBC_LED_CTRL)&(~(1<<(n)))), PBC_LED_CTRL)
+
+#define BOARD_DEBUG_LED(n) \
+ CYG_MACRO_START \
+ if (n >= 0 && n < LED_MAX_NUM) { \
+ if (LED_IS_ON(n)) \
+ TURN_LED_OFF(n); \
+ else \
+ TURN_LED_ON(n); \
+ } \
+ CYG_MACRO_END
+
+#endif /* CYGONCE_FSL_BOARD_H */
--- /dev/null
+#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
+#define CYGONCE_HAL_PLATFORM_SETUP_H
+
+//=============================================================================
+//
+// hal_platform_setup.h
+//
+// Platform specific support for HAL (assembly code)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <pkgconf/system.h> // System-wide configuration info
+#include CYGBLD_HAL_VARIANT_H // Variant specific configuration
+#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
+#include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
+#include <cyg/hal/hal_mmu.h> // MMU definitions
+#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1 _platform_setup1
+#define CYGHWR_HAL_ARM_HAS_MMU
+
+#define INTERNAL_BOOT_MODE
+
+#if defined(INTERNAL_BOOT_MODE)
+#define PLATFORM_PREAMBLE setup_flash_header
+#endif
+
+#ifdef CYG_HAL_STARTUP_ROMRAM
+#define CYGSEM_HAL_ROM_RESET_USES_JUMP
+#endif
+
+#define CYGHWR_HAL_ROM_VADDR 0x0
+
+// This macro represents the initial startup code for the platform
+// r11 is reserved to contain chip rev info in this file
+ .macro _platform_setup1
+FSL_BOARD_SETUP_START:
+ // invalidate I/D cache/TLB and drain write buffer
+ mov r0, #0
+ mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
+ mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+ mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
+
+#if defined(INTERNAL_BOOT_MODE)
+ // On internal boot mode, check MEM CTRL bits for boot source
+ mov r0, #NAND_FLASH_BOOT
+ ldr r1, CCM_BASE_ADDR_W
+ ldr r1, [r1, #CLKCTL_RCSR]
+ tst r1, #0x80000000
+ movne r0, #MMC_FLASH_BOOT
+ ldr r1, MXCBOOT_FLAG_ADDR_W
+ str r0, [r1]
+#else
+ mov r0, #SDRAM_NON_FLASH_BOOT
+ ldr r1, MXCBOOT_FLAG_ADDR_W
+ str r0, [r1] // for checking boot source from nand, nor or sdram
+#endif
+
+ .globl init_spba_start, init_aips_start, init_max_start, init_m3if_start
+init_spba_start:
+ init_spba
+init_aips_start:
+ init_aips
+init_max_start:
+ init_max
+init_m3if_start:
+ init_m3if
+
+#ifndef INTERNAL_BOOT_MODE
+ // check if sdram has been setup
+ cmp pc, #SDRAM_BASE_ADDR
+ blo init_clock_start
+ cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
+ blo HWInitialise_skip_SDRAM_setup
+
+ // Now we must boot from Flash
+ mov r0, #NOR_FLASH_BOOT
+ ldr r1, MXCBOOT_FLAG_ADDR_W
+ str r0, [r1]
+#endif
+init_clock_start:
+ init_clock
+init_cs5_start:
+#ifndef INTERNAL_BOOT_MODE
+ init_cs5
+
+init_sdram_start:
+ /* Assume DDR memory */
+ setup_sdram
+#endif
+
+HWInitialise_skip_SDRAM_setup:
+ mov r0, #NFC_BASE
+ add r2, r0, #0x1000 // 4K window
+ cmp pc, r0
+ blo Normal_Boot_Continue
+ cmp pc, r2
+ bhi Normal_Boot_Continue
+NAND_Boot_Start:
+ /* Copy image from flash to SDRAM first */
+ ldr r1, MXC_REDBOOT_ROM_START
+
+1: ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ blo 1b
+
+ /* Jump to SDRAM */
+ ldr r1, CONST_0x0FFF
+ and r0, pc, r1 /* offset of pc */
+ ldr r1, MXC_REDBOOT_ROM_START
+ add r1, r1, #0x10
+ add pc, r0, r1
+ nop
+ nop
+ nop
+ nop
+NAND_Copy_Main:
+ mov r0, #NAND_FLASH_BOOT
+ ldr r1, MXCBOOT_FLAG_ADDR_W
+ str r0, [r1]
+ mov r0, #MXCFIS_NAND
+ ldr r1, MXCFIS_FLAG_ADDR_W
+ str r0, [r1]
+
+ mov r0, #NFC_BASE; //r0: nfc base. Reloaded after each page copying
+ add r12, r0, #0x1E00 //r12: NFC register base. Doesn't change
+ ldrh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+ orr r3, r3, #0x1
+
+ /* Setting NFC */
+ ldr r7, CCM_BASE_ADDR_W
+ ldr r1, [r7, #CLKCTL_RCSR]
+ /*BUS WIDTH setting*/
+ tst r1, #0x20000000
+ orrne r1, r1, #0x4000
+ biceq r1, r1, #0x4000
+
+ /*4K PAGE*/
+ tst r1, #0x10000000
+ orrne r1, r1, #0x200
+ bne 1f
+ /*2K PAGE*/
+ bic r1, r1, #0x200
+ tst r1, #0x08000000
+ orrne r1, r1, #0x100 /*2KB page size*/
+ biceq r1, r1, #0x100 /*512B page size*/
+ movne r2, #32 /*64 bytes*/
+ moveq r2, #8 /*16 bytes*/
+ b NAND_setup
+1:
+ tst r1, #0x08000000
+ bicne r3, r3, #1 /*Enable 8bit ECC mode*/
+ movne r2, #109 /*218 bytes*/
+ moveq r2, #64 /*128 bytes*/
+NAND_setup:
+ str r1, [r7, #CLKCTL_RCSR]
+ strh r2, [r12, #ECC_RSLT_SPARE_AREA_REG_OFF]
+ strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+
+ //unlock internal buffer
+ mov r3, #0x2
+ strh r3, [r12, #NFC_CONFIGURATION_REG_OFF]
+ //unlock nand device
+ mov r3, #0
+ strh r3, [r12, #UNLOCK_START_BLK_ADD_REG_OFF]
+ sub r3, r3, #1
+ strh r3, [r12, #UNLOCK_END_BLK_ADD_REG_OFF]
+ mov r3, #4
+ strh r3, [r12, #NF_WR_PROT_REG_OFF]
+
+ /* r0: NFC base address. RAM buffer base address. [constantly]
+ * r1: starting flash address to be copied. [constantly]
+ * r2: page size. [Doesn't change]
+ * r3: used as argument.
+ * r11: starting SDRAM address for copying. [Updated constantly].
+ * r12: NFC register base address. [constantly].
+ * r13: end of SDRAM address for copying. [Doesn't change].
+ */
+
+ mov r1, #0x1000
+ ldr r3, [r7, #CLKCTL_RCSR]
+ tst r3, #0x200
+ movne r2, #0x1000
+ bne 1f
+ tst r3, #0x100
+ mov r1, #0x800 /*Strang Why is not 4K offset*/
+ movne r2, #0x800
+ moveq r2, #0x200
+1: /*Update the indicator of copy area */
+ ldr r11, MXC_REDBOOT_ROM_START
+ add r13, r11, #REDBOOT_IMAGE_SIZE
+ add r11, r11, r1
+
+Nfc_Read_Page:
+ mov r3, #0x0
+ nfc_cmd_input
+
+ cmp r2, #0x800
+ bhi nfc_addr_ops_4kb
+ beq nfc_addr_ops_2kb
+
+ mov r3, r1
+ do_addr_input //1st addr cycle
+ mov r3, r1, lsr #9
+ do_addr_input //2nd addr cycle
+ mov r3, r1, lsr #17
+ do_addr_input //3rd addr cycle
+ mov r3, r1, lsr #25
+ do_addr_input //4th addr cycle
+ b end_of_nfc_addr_ops
+
+nfc_addr_ops_2kb:
+ mov r3, #0
+ do_addr_input //1st addr cycle
+ mov r3, #0
+ do_addr_input //2nd addr cycle
+ mov r3, r1, lsr #11
+ do_addr_input //3rd addr cycle
+ mov r3, r1, lsr #19
+ do_addr_input //4th addr cycle
+ mov r3, r1, lsr #27
+ do_addr_input //5th addr cycle
+
+ mov r3, #0x30
+ nfc_cmd_input
+ b end_of_nfc_addr_ops
+
+nfc_addr_ops_4kb:
+ mov r3, #0
+ do_addr_input //1st addr cycle
+ mov r3, #0
+ do_addr_input //2nd addr cycle
+ mov r3, r1, lsr #12
+ do_addr_input //3rd addr cycle
+ mov r3, r1, lsr #20
+ do_addr_input //4th addr cycle
+ mov r3, r1, lsr #27
+ do_addr_input //5th addr cycle
+
+ mov r3, #0x30
+ nfc_cmd_input
+
+end_of_nfc_addr_ops:
+ mov r8, #0
+ bl nfc_data_output
+ bl do_wait_op_done
+ // Check if x16/2kb page
+ cmp r2, #0x800
+ bhi nfc_addr_data_output_done_4k
+ beq nfc_addr_data_output_done_2k
+ beq nfc_addr_data_output_done_512
+
+ // check for bad block
+// mov r3, r1, lsl #(32-17) // get rid of block number
+// cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
+ b nfc_addr_data_output_done
+
+nfc_addr_data_output_done_4k:
+//TODO
+ b nfc_addr_data_output_done
+
+nfc_addr_data_output_done_2k:
+// end of 4th
+ // check for bad block
+//TODO mov r3, r1, lsl #(32-17) // get rid of block number
+// cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
+ b nfc_addr_data_output_done
+
+nfc_addr_data_output_done_512:
+ // check for bad block
+// TODO mov r3, r1, lsl #(32-5-9) // get rid of block number
+// TODO cmp r3, #(512 << (32-5-9)) // check if not page 0 or 1
+
+nfc_addr_data_output_done:
+#if 0
+ bhi Copy_Good_Blk
+ add r4, r0, #0x1000 //r3 -> spare area buf 0
+ ldrh r4, [r4, #0x4]
+ and r4, r4, #0xFF00
+ cmp r4, #0xFF00
+ beq Copy_Good_Blk
+ // really sucks. Bad block!!!!
+ cmp r3, #0x0
+ beq Skip_bad_block
+ // even suckier since we already read the first page!
+ // Check if x16/2kb page
+ cmp r2, #0x800
+ // for 4k page
+ subhi r11, r11, #0x1000 //rewind 1 page for the sdram pointer
+ subhi r1, r1, #0x1000 //rewind 1 page for the flash pointer
+ // for 2k page
+ subeq r11, r11, #0x800 //rewind 1 page for the sdram pointer
+ subeq r1, r1, #0x800 //rewind 1 page for the flash pointer
+ // for 512 page
+ sublo r11, r11, #512 //rewind 1 page for the sdram pointer
+ sublo r1, r1, #512 //rewind 1 page for the flash pointer
+Skip_bad_block:
+ // Check if x16/2kb page
+ ldr r7, CCM_BASE_ADDR_W
+ ldr r7, [r7, #CLKCTL_RCSR]
+ tst r7, #0x200
+ addne r1, r1, #(128*4096)
+ bne Skip_bad_block_done
+ tst r7, #0x100
+ addeq r1, r1, #(32*512)
+ addne r1, r1, #(64*2048)
+Skip_bad_block_done:
+ b Nfc_Read_Page
+#endif
+Copy_Good_Blk:
+ //copying page
+ add r2, r2, #NFC_BASE
+1: ldmia r0!, {r3-r10}
+ stmia r11!, {r3-r10}
+ cmp r0, r2
+ blo 1b
+ sub r2, r2, #NFC_BASE
+
+ cmp r11, r13
+ bge NAND_Copy_Main_done
+ // Check if x16/2kb page
+ add r1, r1, r2
+ mov r0, #NFC_BASE
+ b Nfc_Read_Page
+
+NAND_Copy_Main_done:
+
+Normal_Boot_Continue:
+
+#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
+ /* Copy image from flash to SDRAM first */
+ ldr r0, =0xFFFFF000
+ and r0, r0, pc
+ ldr r1, MXC_REDBOOT_ROM_START
+ cmp r0, r1
+ beq HWInitialise_skip_SDRAM_copy
+
+ add r2, r0, #REDBOOT_IMAGE_SIZE
+
+1: ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ ble 1b
+
+ /* Jump to SDRAM */
+ ldr r1, =0xFFFF
+ and r0, pc, r1 /* offset of pc */
+ ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
+ add pc, r0, r1
+ nop
+ nop
+ nop
+ nop
+#endif /* CYG_HAL_STARTUP_ROMRAM */
+
+HWInitialise_skip_SDRAM_copy:
+
+STACK_Setup:
+ // Set up a stack [for calling C code]
+ ldr r1, =__startup_stack
+ ldr r2, =RAM_BANK0_BASE
+ orr sp, r1, r2
+
+ // Create MMU tables
+ bl hal_mmu_init
+
+ // Enable MMU
+ ldr r2, =10f
+ mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
+ orr r1, r1, #7 // enable MMU bit
+ mcr MMU_CP, 0, r1, MMU_Control, c0
+ mov pc,r2 /* Change address spaces */
+ nop
+ nop
+ nop
+10:
+ // Save shadow copy of BCR, also hardware configuration
+ ldr r1, =_board_BCR
+ str r2,[r1]
+ ldr r1, =_board_CFG
+ str r9,[r1] // Saved far above...
+
+ .endm // _platform_setup1
+
+do_wait_op_done:
+ 1:
+ ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
+ beq 1b
+ bx lr // do_wait_op_done
+
+
+nfc_data_output:
+ ldrh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+ orr r3, r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
+ strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+
+ strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
+
+ mov r3, #FDO_PAGE_SPARE_VAL
+ strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ bx lr
+
+#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1
+#endif
+
+ /* Do nothing */
+ .macro init_spba
+ .endm /* init_spba */
+
+ /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
+ .macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, AIPS1_CTRL_BASE_ADDR_W
+ ldr r1, AIPS1_PARAM_W
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ ldr r0, AIPS2_CTRL_BASE_ADDR_W
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ .endm /* init_aips */
+
+ /* MAX (Multi-Layer AHB Crossbar Switch) setup */
+ .macro init_max
+ ldr r0, MAX_BASE_ADDR_W
+ /* MPR - priority for MX25 is IAHB>DAHB>USBOTG>RTIC>(SDHC2/SDMA) */
+ ldr r1, MAX_PARAM1
+ str r1, [r0, #0x000] /* for S0 */
+ str r1, [r0, #0x100] /* for S1 */
+ str r1, [r0, #0x200] /* for S2 */
+ str r1, [r0, #0x300] /* for S3 */
+ str r1, [r0, #0x400] /* for S4 */
+ /* SGPCR - always park on last master */
+ ldr r1, =0x10
+ str r1, [r0, #0x010] /* for S0 */
+ str r1, [r0, #0x110] /* for S1 */
+ str r1, [r0, #0x210] /* for S2 */
+ str r1, [r0, #0x310] /* for S3 */
+ str r1, [r0, #0x410] /* for S4 */
+ /* MGPCR - restore default values */
+ ldr r1, =0x0
+ str r1, [r0, #0x800] /* for M0 */
+ str r1, [r0, #0x900] /* for M1 */
+ str r1, [r0, #0xA00] /* for M2 */
+ str r1, [r0, #0xB00] /* for M3 */
+ str r1, [r0, #0xC00] /* for M4 */
+ .endm /* init_max */
+
+ /* Clock setup */
+ .macro init_clock
+ ldr r0, CCM_BASE_ADDR_W
+
+ /* default CLKO to 1/32 of the ARM core */
+ ldr r1, [r0, #CLKCTL_MCR]
+ bic r1, r1, #0x00F00000
+ bic r1, r1, #0x7F000000
+ mov r2, #0x5F000000
+ add r2, r2, #0x00200000
+ orr r1, r1, r2
+ str r1, [r0, #CLKCTL_MCR]
+
+ /* enable all the clocks */
+ ldr r2, CCM_CGR0_W
+ str r2, [r0, #CLKCTL_CGR0]
+ ldr r2, CCM_CGR1_W
+ str r2, [r0, #CLKCTL_CGR1]
+ ldr r2, CCM_CGR2_W
+ str r2, [r0, #CLKCTL_CGR2]
+ .endm /* init_clock */
+
+ /* M3IF setup */
+ .macro init_m3if
+ /* Configure M3IF registers */
+ ldr r1, M3IF_BASE_W
+ /*
+ * M3IF Control Register (M3IFCTL) for MX25
+ * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
+ * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
+ * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
+ * MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
+ * MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000
+ * MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000
+ * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
+ * ----------
+ * 0x00000001
+ */
+ ldr r0, =0x00000001
+ str r0, [r1] /* M3IF control reg */
+ .endm /* init_m3if */
+
+ /* CPLD on CS5 setup */
+ .macro init_cs5
+ ldr r0, WEIM_CTRL_CS5_W
+ ldr r1, CS5_CSCRU_0x0000D843
+ str r1, [r0, #CSCRU]
+ ldr r1, CS5_CSCRL_0x22252521
+ str r1, [r0, #CSCRL]
+ ldr r1, CS5_CSCRA_0x22220A00
+ str r1, [r0, #CSCRA]
+ .endm /* init_cs5 */
+
+ .macro setup_sdram
+ ldr r0, ESDCTL_BASE_W
+ mov r3, #0x2000
+ str r3, [r0, #0x0]
+ str r3, [r0, #0x8]
+
+ mov r12, #0x00
+ mov r2, #0x1 /* mDDR */
+ mov r1, #RAM_BANK0_BASE
+ bl setup_sdram_bank
+ cmp r3, #0x0
+ orreq r12, r12, #1
+ eorne r2, r2, #0x1
+ blne setup_sdram_bank
+
+ ldr r3, ESDCTL_DELAY5
+ str r3, [r0, #0x30]
+ .endm
+
+ .macro nfc_cmd_input
+ strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
+ mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
+ strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ bl do_wait_op_done
+ .endm // nfc_cmd_input
+
+ .macro do_addr_input
+ and r3, r3, #0xFF
+ strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
+ mov r3, #NAND_FLASH_CONFIG2_FADD_EN
+ strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ bl do_wait_op_done
+ .endm // do_addr_input
+
+ /* To support 133MHz DDR */
+ .macro init_iomuxc
+ mov r0, #0x2
+ ldr r1, IOMUXC_BASE_ADDR_W
+ add r1, r1, #0x368
+ add r2, r1, #0x4C8 - 0x368
+1: str r0, [r1], #4
+ cmp r1, r2
+ ble 1b
+ .endm /* init_iomuxc */
+
+/*
+ * r0: control base, r1: ram bank base
+ * r2: ddr type(0:DDR2, 1:MDDR) r3, r4: working
+ */
+setup_sdram_bank:
+ mov r3, #0xE /*0xA + 0x4*/
+ tst r2, #0x1
+ orreq r3, r3, #0x300 /*DDR2*/
+ str r3, [r0, #0x10]
+ bic r3, r3, #0x00A
+ str r3, [r0, #0x10]
+ beq 2f
+
+ mov r3, #0x20000
+1: subs r3, r3, #1
+ bne 1b
+
+2: adr r4, ESDCTL_CONFIG
+ tst r2, #0x1
+ ldreq r3, [r4, #0x0]
+ ldrne r3, [r4, #0x4]
+ cmp r1, #RAM_BANK1_BASE
+ strlo r3, [r0, #0x4]
+ strhs r3, [r0, #0xC]
+
+ ldr r3, ESDCTL_0x92220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ mov r3, #0xDA
+ ldr r4, RAM_PARAM1_MDDR
+ strb r3, [r1, r4]
+
+ tst r2, #0x1
+ bne skip_set_mode
+
+ cmp r1, #RAM_BANK1_BASE
+ ldr r3, ESDCTL_0xB2220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ mov r3, #0xDA
+ ldr r4, RAM_PARAM4_MDDR
+ strb r3, [r1, r4]
+ ldr r4, RAM_PARAM5_MDDR
+ strb r3, [r1, r4]
+ ldr r4, RAM_PARAM3_MDDR
+ strb r3, [r1, r4]
+ ldr r4, RAM_PARAM2_MDDR
+ strb r3, [r1, r4]
+
+ ldr r3, ESDCTL_0x92220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ mov r3, #0xDA
+ ldr r4, RAM_PARAM1_MDDR
+ strb r3, [r1, r4]
+
+skip_set_mode:
+ cmp r1, #RAM_BANK1_BASE
+ ldr r3, ESDCTL_0xA2220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ mov r3, #0xDA
+ strb r3, [r1]
+ strb r3, [r1]
+
+ ldr r3, ESDCTL_0xB2220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ adr r4, RAM_PARAM6_MDDR
+ tst r2, #0x1
+ ldreq r4, [r4, #0x0]
+ ldrne r4, [r4, #0x4]
+ mov r3, #0xDA
+ strb r3, [r1, r4]
+ ldreq r4, RAM_PARAM7_MDDR
+ streqb r3, [r1, r4]
+ adr r4, RAM_PARAM3_MDDR
+ ldreq r4, [r4, #0x0]
+ ldrne r4, [r4, #0x4]
+ strb r3, [r1, r4]
+
+ cmp r1, #RAM_BANK1_BASE
+ ldr r3, ESDCTL_0x82226080
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+
+ tst r2, #0x1
+ moveq r4, #0x20000
+ movne r4, #0x200
+1: subs r4, r4, #1
+ bne 1b
+
+ str r3, [r1, #0x100]
+ ldr r4, [r1, #0x100]
+ cmp r3, r4
+ movne r3, #1
+ moveq r3, #0
+
+ mov pc, lr
+
+#define PLATFORM_VECTORS _platform_vectors
+ .macro _platform_vectors
+ .globl _board_BCR, _board_CFG
+_board_BCR: .long 0 // Board Control register shadow
+_board_CFG: .long 0 // Board Configuration (read at RESET)
+ .endm
+
+//Internal Boot, from MMC/SD cards or NAND flash
+#ifdef INTERNAL_BOOT_MODE
+#define DCDGEN(i,type, addr, data) \
+dcd_##i: ;\
+ .long type ;\
+ .long addr ;\
+ .long data
+
+#define FHEADER_OFFSET 0x400
+
+ .macro setup_flash_header
+ b reset_vector
+#if defined(FHEADER_OFFSET)
+ .org FHEADER_OFFSET
+#endif
+app_code_jump_v: .long reset_vector
+app_code_barker: .long 0xB1
+app_code_csf: .long 0
+hwcfg_ptr_ptr: .long hwcfg_ptr
+super_root_key: .long 0
+hwcfg_ptr: .long dcd_data
+app_dest_ptr: .long SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
+dcd_data: .long 0xB17219E9
+#ifdef MEMORY_MDDR_ENABLE
+ .long 12*15
+#else
+ .long 12*24
+#endif
+
+// real dcd data table
+
+// WEIM config-CS5 init -- CPLD
+DCDGEN( 1, 4, 0xB8002050, 0x0000D843) // CS5_CSCRU
+DCDGEN( 2, 4, 0xB8002054, 0x22252521) // CS5_CSCRL
+DCDGEN( 3, 4, 0xB8002058, 0x22220A00) // CS5_CSCRA
+
+#ifdef MEMORY_MDDR_ENABLE
+// MDDR init
+DCDGEN( 4, 4, 0xB8001010, 0x00000004) // enable mDDR
+DCDGEN( 5, 4, 0xB8001000, 0x92100000) // precharge command
+DCDGEN( 6, 1, 0x80000400, 0x12344321) // precharge all dummy write
+DCDGEN( 7, 4, 0xB8001000, 0xA2100000) // auto-refresh command
+DCDGEN( 8, 4, 0x80000000, 0x12344321) // dummy write for refresh
+DCDGEN( 9, 4, 0x80000000, 0x12344321) // dummy write for refresh
+DCDGEN(10, 4, 0xB8001000, 0xB2100000) // Load Mode Register command - cas=3 bl=8
+DCDGEN(11, 1, 0x80000033, 0xda) // dummy write -- address has the mode bits
+DCDGEN(12, 1, 0x81000000, 0xff) // dummy write -- address has the mode bits
+//
+// For DDR clock speed max = 133 MHz, HYB18M1G320BF-7.5 memory
+// based on data sheet HYx18M1G16x_BF_rev100.pdf.
+//
+// ESDCTL0=0x82216880:
+// SDE=1 ESDRAM Controller Enable: Enabled
+// SMODE=000 SDRAM Controller Operating Mode: Normal Read/Write
+// SP=0 Supervisor Protect: User mode accesses allowed
+// ROW=010 Row Address Width: 13 Row Addresses
+// COL=10 Column Address Width: 10 Column Addresses
+// DSIZ=01 SDRAM Memory Data Width: 16-bit memory width aligned to D[15:0]
+// SREFR=011 SDRAM Refresh Rate: 4 rows each refresh clock,
+// 8192 rows/64 mS @ 32 kHz
+// 7.81 uS row rate at 32 kHz
+// PWDT=10 Power Down Timer: 64 clocks (HCLK) after completion of last access
+// with Active Power Down (most aggressive)
+// FP=0 Full Page: Not Full Page
+// BL=1 Burst Length: 8
+// PRCT=000000 Precharge Timer: Disabled
+//
+DCDGEN(13, 4, 0xB8001000, 0x82216880)
+//
+// ESDCFG0=0x00295729:
+// tXP=01 LPDDR exit power down to next valid command delay: 2 clocks
+// tWTR=0 LPDDR WRITE to READ Command Delay: 1 clock
+// tRP=10 SDRAM Row Precharge Delay: 3 clocks
+// tMRD=01 SDRAM Load Mode Register to ACTIVE Command: 2 clocks
+// tWR=0 SDRAM WRITE to PRECHARGE Command: 2 clocks
+// tRAS=101 SDRAM ACTIVE to PRECHARGE Command: 6 clocks
+// tRRD=01 ACTIVE Bank A to ACTIVE Bank B Command: 2 clocks
+// tCAS=11 SDRAM CAS Latency: 3 clocks
+// tRCD=010 SDRAM Row to Column Delay: 3 clocks
+// tRC=1001 SDRAM Row Cycle Delay: 9 clocks
+//
+DCDGEN(14, 4, 0xB8001004, 0x00295729)
+#else
+// DDR2 init
+DCDGEN( 4, 4, 0xB8001004, 0x0076E83A) // initial value for ESDCFG0
+DCDGEN( 5, 4, 0xB8001010, 0x00000204) // ESD_MISC
+DCDGEN( 6, 4, 0xB8001000, 0x92210000) // CS0 precharge command
+DCDGEN( 7, 4, 0x80000f00, 0x12344321) // precharge all dummy write
+DCDGEN( 8, 4, 0xB8001000, 0xB2210000) // Load Mode Register command
+DCDGEN( 9, 1, 0x82000000, 0xda) // dummy write -- Load EMR2
+DCDGEN(10, 1, 0x83000000, 0xda) // dummy write -- Load EMR3
+DCDGEN(11, 1, 0x81000400, 0xda) // dummy write -- Load EMR1; enable DLL
+DCDGEN(12, 1, 0x80000333, 0xda) // dummy write -- Load MR; reset DLL
+
+DCDGEN(13, 4, 0xB8001000, 0x92210000) // CS0 precharge command
+DCDGEN(14, 1, 0x80000400, 0x12345678) // precharge all dummy write
+
+DCDGEN(15, 4, 0xB8001000, 0xA2210000) // select manual refresh mode
+DCDGEN(16, 4, 0x80000000, 0x87654321) // manual refresh
+DCDGEN(17, 4, 0x80000000, 0x87654321) // manual refresh twice
+
+DCDGEN(18, 4, 0xB8001000, 0xB2210000) // Load Mode Register command
+DCDGEN(19, 1, 0x80000233, 0xda) // -- Load MR; CL=3, BL=8, end DLL reset
+DCDGEN(20, 1, 0x81000780, 0xda) // -- Load EMR1; OCD default
+DCDGEN(21, 1, 0x81000400, 0xda) // -- Load EMR1; OCD exit
+
+// ESD_ESDCTL0 SDE_SMODE_SP_ROW_00_COL_00_DSIZ_SREFR_0_PWDT_0_FP_BL_0__PRCT
+// ESD_ESDCTL0 32'b1_000__0__010_00__10_00___10___011_0___00_0__0__0_0_000000
+// @; normal mode row=010//col=10//dzize=10//self ref=011//PWDT =00//BL =0//prct =000000
+DCDGEN(22, 4, 0xB8001000, 0x82216080)
+
+// Init IOMUXC_SW_PAD_CTL_GRP_DDRTYPE_GRP(1-5)
+DCDGEN(23, 4, 0x43FAC454, 0x00001000)
+#endif
+//
+// CLK
+DCDGEN(99, 4, 0x53F80008, 0x20034000) // CLKCTL ARM=400 AHB=133
+
+//CARD_FLASH_CFG_PARMS_T---length
+card_cfg: .long REDBOOT_IMAGE_SIZE
+ .endm
+#endif
+
+AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
+AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
+AIPS1_PARAM_W: .word 0x77777777
+MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
+MAX_PARAM1: .word 0x00043210
+ESDCTL_BASE_W: .word ESDCTL_BASE_ADDR
+M3IF_BASE_W: .word M3IF_BASE
+RAM_PARAM1_MDDR: .word 0x00000400
+RAM_PARAM2_MDDR: .word 0x00000333
+RAM_PARAM3_MDDR: .word 0x02000400
+ .word 0x02000000
+RAM_PARAM4_MDDR: .word 0x04000000
+RAM_PARAM5_MDDR: .word 0x06000000
+RAM_PARAM6_MDDR: .word 0x00000233
+ .word 0x00000033
+RAM_PARAM7_MDDR: .word 0x02000780
+ESDCTL_0x92220000: .word 0x92220000
+ESDCTL_0xA2220000: .word 0xA2220000
+ESDCTL_0xB2220000: .word 0xB2220000
+ESDCTL_0x82226080: .word 0x82226080
+ESDCTL_CONFIG: .word 0x007FFC3F
+ .word 0x007FFC3F
+ESDCTL_DELAY5: .word 0x00F49F00
+IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
+CCM_CCTL_W: .word 0x20034000 // ARM clk = 400, AHB clk = 133
+MPCTL_PARAM_399_W: .word MPCTL_PARAM_399
+MPCTL_PARAM_532_W: .word MPCTL_PARAM_532
+UPCTL_PARAM_W: .word UPCTL_PARAM_300
+CCM_CGR0_W: .word 0x1FFFFFFF
+CCM_CGR1_W: .word 0xFFFFFFFF
+CCM_CGR2_W: .word 0x000FDFFF
+MXCBOOT_FLAG_ADDR_W: .word MXCBOOT_FLAG_REG
+MXCFIS_FLAG_ADDR_W: .word MXCFIS_FLAG_REG
+MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
+CONST_0x0FFF: .word 0x0FFF
+CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
+WEIM_CTRL_CS5_W: .word WEIM_CTRL_CS5
+WEIM_CTRL_CS0_W: .word WEIM_CTRL_CS0
+CS0_CSCRU_0x0000CC03: .word 0x0000DCF6
+CS0_CSCRL_0xA0330D01: .word 0x444A4541
+CS0_CSCRA_0x00220800: .word 0x44443302
+CS5_CSCRU_0x0000D843: .word 0x0000D843
+CS5_CSCRL_0x22252521: .word 0x22252521
+CS5_CSCRA_0x22220A00: .word 0x22220A00
+/*---------------------------------------------------------------------------*/
+/* end of hal_platform_setup.h */
+#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x00000000)
+#define CYGMEM_REGION_ram_SIZE (0x7F00000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0x87F00000)
+#define CYGMEM_REGION_rom_SIZE (0x100000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ ram : ORIGIN = 0, LENGTH = 0x7F00000
+ rom : ORIGIN = 0x87F00000, LENGTH = 0x100000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_rom_vectors (rom, 0x87F00000, LMA_EQ_VMA)
+ SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
+ SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table))
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
--- /dev/null
+version 0
+region ram 0 7F00000 0 !
+region rom 87F00000 100000 1 !
+section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
+section data 0 1 1 1 1 1 0 0 8000 bss !
+section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
+section heap1 0 8 0 0 0 0 0 0 !
+section rom_vectors 0 1 0 1 1 1 1 1 87F00000 87F00000 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata rodata !
+section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 4 0 1 0 0 0 1 data !
--- /dev/null
+#ifndef CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+#define CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+
+//=============================================================================
+//
+// plf_io.h
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/hal/fsl_board.h>
+#include <cyg/hal/hal_soc.h>
+
+#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \
+ CYG_MACRO_START \
+ { \
+ extern unsigned int system_rev; \
+ /* Next ATAG_MEM. */ \
+ _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_MEM; \
+ /* Round up so there's only one bit set in the memory size. \
+ * Don't double it if it's already a power of two, though. \
+ */ \
+ _p_->u.mem.size = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE); \
+ if (_p_->u.mem.size < (CYGMEM_REGION_ram_SIZE)) \
+ _p_->u.mem.size <<= 1; \
+ _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram); \
+ _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size); \
+ _p_->hdr.size = ((sizeof(struct tag_revision)) + sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_REVISION; \
+ _p_->u.revision.rev = system_rev; \
+ } \
+ CYG_MACRO_END
+#endif // CYGONCE_HAL_ARM_BOARD_PLF_IO_H
--- /dev/null
+#ifndef CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+#define CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+//=============================================================================
+//
+// plf_mmap.h
+//
+// Platform specific memory map support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_misc.h>
+
+// Get the pagesize for a particular virtual address:
+
+// This does not depend on the vaddr.
+#define HAL_MM_PAGESIZE(vaddr, pagesize) CYG_MACRO_START \
+ (pagesize) = SZ_1M; \
+CYG_MACRO_END
+
+// Get the physical address from a virtual address:
+
+#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START \
+ cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
+ if ( _v_ < 128 * SZ_1M ) /* SDRAM */ \
+ _v_ += SDRAM_BASE_ADDR; \
+ else /* Rest of it */ \
+ /* no change */ ; \
+ (paddr) = _v_; \
+CYG_MACRO_END
+
+/*
+ * translate the virtual address of ram space to physical address
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
+{
+ if(virt < 0x08000000) {
+ return virt|0x80000000;
+ }
+ if((virt & 0xF0000000) == 0x80000000) {
+ return virt&(~0x08000000);
+ }
+ return virt;
+}
+
+/*
+ * remap the physical address of ram space to uncacheable virtual address space
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
+{
+ /* 0x88000000~0x87FFFFFF is uncacheable meory space which is mapped to SDRAM*/
+ if((phy & 0xF0000000) == 0x80000000) {
+ phy |= 0x08000000;
+ }
+ return phy;
+}
+
+//---------------------------------------------------------------------------
+#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
--- /dev/null
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware mx25_3stack ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM current ;
+ package -hardware CYGPKG_HAL_ARM_MX25 current ;
+ package -hardware CYGPKG_HAL_ARM_MX25_3STACK current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ;
+ package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ;
+ package -hardware CYGPKG_DEVS_ETH_FEC current ;
+ package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ;
+ package -hardware CYGPKG_COMPRESS_ZLIB current ;
+ package -hardware CYGPKG_DIAGNOSIS current ;
+ package -hardware CYGPKG_IO_FLASH current ;
+ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+ package -hardware CYGPKG_DEVS_FLASH_IMX_3STACK_SPANSION current ;
+ package -hardware CYGPKG_DEVS_MXC_SPI current ;
+ package -hardware CYGPKG_DEVS_MXC_I2C current ;
+ package -hardware CYGPKG_DEVS_PMIC_ARM_IMX25_3STACK current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package CYGPKG_MEMALLOC current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL512N {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FSL_SPI_VER_0_7 {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_PMIC_I2C {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_PMIC_I2C_PORT {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_PMIC_I2C_ADDR {
+ inferred_value 0x54
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MMC {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_MX25_MDDR {
+ inferred_value 1
+};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+ inferred_value 3
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
+ user_value 50
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ inferred_value 0x00040000
+};
+
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+ inferred_value 0x80008000
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_component CYG_HAL_STARTUP {
+ user_value ROMRAM
+};
+
+cdl_component CYGPKG_MEMORY_DIAGNOSIS {
+ user_value 1
+};
+
+cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+ inferred_value 1
+};
+
+
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+ user_value 1 "FSL 200904"
+};
--- /dev/null
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware mx25_3stack ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM current ;
+ package -hardware CYGPKG_HAL_ARM_MX25 current ;
+ package -hardware CYGPKG_HAL_ARM_MX25_3STACK current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ;
+ package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ;
+ package -hardware CYGPKG_DEVS_ETH_FEC current ;
+ package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ;
+ package -hardware CYGPKG_COMPRESS_ZLIB current ;
+ package -hardware CYGPKG_DIAGNOSIS current ;
+ package -hardware CYGPKG_IO_FLASH current ;
+ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+ package -hardware CYGPKG_DEVS_FLASH_IMX_3STACK_SPANSION current ;
+ package -hardware CYGPKG_DEVS_MXC_SPI current ;
+ package -hardware CYGPKG_DEVS_MXC_I2C current ;
+ package -hardware CYGPKG_DEVS_PMIC_ARM_IMX25_3STACK current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package CYGPKG_MEMALLOC current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL512N {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FSL_SPI_VER_0_7 {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_PMIC_I2C {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_PMIC_I2C_PORT {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_PMIC_I2C_ADDR {
+ inferred_value 0x54
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MMC {
+ inferred_value 1
+};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+ inferred_value 3
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
+ user_value 50
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ inferred_value 0x00040000
+};
+
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+ inferred_value 0x80008000
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_component CYG_HAL_STARTUP {
+ user_value ROMRAM
+};
+
+cdl_component CYGPKG_MEMORY_DIAGNOSIS {
+ user_value 1
+};
+
+cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+ inferred_value 1
+};
+
+
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+ user_value 1 "FSL 200904"
+};
--- /dev/null
+/*=============================================================================
+//
+// board_diag.c
+//
+// HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_arch.h> // basic machine info
+#include <cyg/hal/hal_intr.h> // interrupt macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_if.h> // Calling-if API
+#include <cyg/hal/drv_api.h> // driver API
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/fsl_board.h> // Platform specifics
+
+static void cyg_hal_plf_duart_init(void);
+extern void cyg_hal_plf_serial_init(void);
+
+void cyg_hal_plf_comms_init(void)
+{
+ static int initialized = 0;
+
+ if (initialized)
+ return;
+
+ initialized = 1;
+ cyg_hal_plf_duart_init();
+ cyg_hal_plf_serial_init();
+}
+
+//=============================================================================
+// ST16552 DUART driver
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// Only one external UART.
+#define CYG_DEV_SERIAL_BASE_A (BOARD_CS_UART_BASE + 0x00)
+
+//-----------------------------------------------------------------------------
+// Based on 3.6864 MHz xtal
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x18
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x0C
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x06
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x04
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x02
+#endif
+
+#ifndef CYG_DEV_SERIAL_BAUD_MSB
+#error Missing/incorrect serial baud rate defined - CDL error?
+#endif
+
+//-----------------------------------------------------------------------------
+// Define the serial registers. The board is equipped with a 16552
+// serial chip.
+
+#if defined (EXT_UART_x16)
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT16
+#define HAL_READ_UINT_UART HAL_READ_UINT16
+typedef cyg_uint16 uart_width;
+#elif defined (EXT_UART_x32)
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT32
+#define HAL_READ_UINT_UART HAL_READ_UINT32
+typedef cyg_uint32 uart_width;
+#else //_x8
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT8
+#define HAL_READ_UINT_UART HAL_READ_UINT8
+typedef cyg_uint8 uart_width;
+#endif
+
+#define CYG_DEV_SERIAL_RHR 0x00 // receiver buffer register, read, dlab = 0
+#define CYG_DEV_SERIAL_THR 0x00 // transmitter holding register, write, dlab = 0
+#define CYG_DEV_SERIAL_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IER 0x01 // interrupt enable register, read/write, dlab = 0
+#define CYG_DEV_SERIAL_DLM 0x01 // divisor latch (MS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IIR 0x02 // interrupt identification register, read, dlab = 0
+#define CYG_DEV_SERIAL_FCR 0x02 // fifo control register, write, dlab = 0
+#define CYG_DEV_SERIAL_AFR 0x02 // alternate function register, read/write, dlab = 1
+#define CYG_DEV_SERIAL_LCR 0x03 // line control register, read/write
+#define CYG_DEV_SERIAL_MCR 0x04
+#define CYG_DEV_SERIAL_MCR_A 0x04
+#define CYG_DEV_SERIAL_MCR_B 0x04
+#define CYG_DEV_SERIAL_LSR 0x05 // line status register, read
+#define CYG_DEV_SERIAL_MSR 0x06 // modem status register, read
+#define CYG_DEV_SERIAL_SCR 0x07 // scratch pad register
+
+// The interrupt enable register bits.
+#define SIO_IER_ERDAI 0x01 // enable received data available irq
+#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
+#define SIO_IER_ELSI 0x04 // enable receiver line status irq
+#define SIO_IER_EMSI 0x08 // enable modem status interrupt
+
+// The interrupt identification register bits.
+#define SIO_IIR_IP 0x01 // 0 if interrupt pending
+#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
+#define ISR_Tx 0x02
+#define ISR_Rx 0x04
+
+// The line status register bits.
+#define SIO_LSR_DR 0x01 // data ready
+#define SIO_LSR_OE 0x02 // overrun error
+#define SIO_LSR_PE 0x04 // parity error
+#define SIO_LSR_FE 0x08 // framing error
+#define SIO_LSR_BI 0x10 // break interrupt
+#define SIO_LSR_THRE 0x20 // transmitter holding register empty
+#define SIO_LSR_TEMT 0x40 // transmitter register empty
+#define SIO_LSR_ERR 0x80 // any error condition
+
+// The modem status register bits.
+#define SIO_MSR_DCTS 0x01 // delta clear to send
+#define SIO_MSR_DDSR 0x02 // delta data set ready
+#define SIO_MSR_TERI 0x04 // trailing edge ring indicator
+#define SIO_MSR_DDCD 0x08 // delta data carrier detect
+#define SIO_MSR_CTS 0x10 // clear to send
+#define SIO_MSR_DSR 0x20 // data set ready
+#define SIO_MSR_RI 0x40 // ring indicator
+#define SIO_MSR_DCD 0x80 // data carrier detect
+
+// The line control register bits.
+#define SIO_LCR_WLS0 0x01 // word length select bit 0
+#define SIO_LCR_WLS1 0x02 // word length select bit 1
+#define SIO_LCR_STB 0x04 // number of stop bits
+#define SIO_LCR_PEN 0x08 // parity enable
+#define SIO_LCR_EPS 0x10 // even parity select
+#define SIO_LCR_SP 0x20 // stick parity
+#define SIO_LCR_SB 0x40 // set break
+#define SIO_LCR_DLAB 0x80 // divisor latch access bit
+
+// The FIFO control register
+#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
+#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
+#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
+
+//-----------------------------------------------------------------------------
+
+typedef struct {
+ uart_width* base;
+ cyg_int32 msec_timeout;
+ int isr_vector;
+} channel_data_t;
+
+static channel_data_t channels[] = {
+#if CYGHWR_HAL_ARM_DUART_UARTA != 0
+ {(uart_width*)CYG_DEV_SERIAL_BASE_A, 1000, 0},
+#endif
+#if CYGHWR_HAL_ARM_DUART_UARTB != 0
+ {(uart_width*)CYG_DEV_SERIAL_BASE_B, 1000, 0}
+#endif
+};
+
+//-----------------------------------------------------------------------------
+
+static void init_duart_channel(channel_data_t* __ch_data)
+{
+ uart_width* base = __ch_data->base;
+ uart_width lcr;
+
+ // 8-1-no parity.
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR,
+ SIO_LCR_WLS0 | SIO_LCR_WLS1);
+
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ lcr |= SIO_LCR_DLAB;
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLL, CYG_DEV_SERIAL_BAUD_LSB);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLM, CYG_DEV_SERIAL_BAUD_MSB);
+ lcr &= ~SIO_LCR_DLAB;
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_FCR, 0x07); // Enable & clear FIFO
+}
+
+//#define x_debug_uart_log_buf
+#ifdef x_debug_uart_log_buf
+#define x_DIAG_BUFSIZE 2048
+static char __x_log_buf[x_DIAG_BUFSIZE];
+static int x_diag_bp = 0;
+#endif
+
+void cyg_hal_plf_duart_putc(void* __ch_data, cyg_uint8 c)
+{
+ uart_width* base = ((channel_data_t*)__ch_data)->base;
+ uart_width lsr;
+
+#ifdef x_debug_uart_log_buf
+ __x_log_buf[x_diag_bp++] = c;
+#endif
+ CYGARC_HAL_SAVE_GP();
+
+ do {
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ } while ((lsr & SIO_LSR_THRE) == 0);
+
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_THR, c);
+
+ // Hang around until the character has been safely sent.
+ do {
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ } while ((lsr & SIO_LSR_THRE) == 0);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool cyg_hal_plf_duart_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+ uart_width* base = ((channel_data_t*)__ch_data)->base;
+ uart_width lsr, ch16;
+
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ if ((lsr & SIO_LSR_DR) == 0)
+ return false;
+
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_RHR, ch16);
+
+ *ch = (cyg_uint8) (ch16 & 0x00FF);
+
+ return true;
+}
+
+cyg_uint8 cyg_hal_plf_duart_getc(void* __ch_data)
+{
+ cyg_uint8 ch;
+
+ CYGARC_HAL_SAVE_GP();
+
+ while (!cyg_hal_plf_duart_getc_nonblock(__ch_data, &ch));
+
+ CYGARC_HAL_RESTORE_GP();
+ return ch;
+}
+
+static void cyg_hal_plf_duart_write(void* __ch_data, const cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while (__len-- > 0)
+ cyg_hal_plf_duart_putc(__ch_data, *__buf++);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static void cyg_hal_plf_duart_read(void* __ch_data, cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while (__len-- > 0)
+ *__buf++ = cyg_hal_plf_duart_getc(__ch_data);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool cyg_hal_plf_duart_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+ int delay_count;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_bool res;
+
+ CYGARC_HAL_SAVE_GP();
+
+ delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+ for (;;) {
+ res = cyg_hal_plf_duart_getc_nonblock(__ch_data, ch);
+ if (res || 0 == delay_count--)
+ break;
+
+ CYGACC_CALL_IF_DELAY_US(100);
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static int cyg_hal_plf_duart_control(void *__ch_data,
+ __comm_control_cmd_t __func, ...)
+{
+ static int irq_state = 0;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ uart_width ier;
+ int ret = 0;
+
+ CYGARC_HAL_SAVE_GP();
+
+ switch (__func) {
+ case __COMMCTL_IRQ_ENABLE:
+ HAL_INTERRUPT_UNMASK(chan->isr_vector);
+ HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ ier |= SIO_IER_ERDAI;
+ HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ irq_state = 1;
+ break;
+ case __COMMCTL_IRQ_DISABLE:
+ ret = irq_state;
+ irq_state = 0;
+ HAL_INTERRUPT_MASK(chan->isr_vector);
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ ier &= ~SIO_IER_ERDAI;
+ HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ break;
+ case __COMMCTL_DBG_ISR_VECTOR:
+ ret = chan->isr_vector;
+ break;
+ case __COMMCTL_SET_TIMEOUT:
+ {
+ va_list ap;
+
+ va_start(ap, __func);
+
+ ret = chan->msec_timeout;
+ chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+ va_end(ap);
+ }
+ break;
+ default:
+ break;
+ }
+ CYGARC_HAL_RESTORE_GP();
+ return ret;
+}
+
+static int cyg_hal_plf_duart_isr(void *__ch_data, int* __ctrlc,
+ CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ uart_width _iir;
+ int res = 0;
+ CYGARC_HAL_SAVE_GP();
+
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IIR, _iir);
+ _iir &= SIO_IIR_ID_MASK;
+
+ *__ctrlc = 0;
+ if ( ISR_Rx == _iir ) {
+ uart_width c, lsr;
+ cyg_uint8 c8;
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_LSR, lsr);
+ if (lsr & SIO_LSR_DR) {
+
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_RHR, c);
+
+ c8 = (cyg_uint8) (c & 0x00FF);
+
+ if (cyg_hal_is_break( &c8 , 1 ))
+ *__ctrlc = 1;
+ }
+
+ // Acknowledge the interrupt
+ HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+ res = CYG_ISR_HANDLED;
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static void cyg_hal_plf_duart_init(void)
+{
+ hal_virtual_comm_table_t* comm;
+ int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ int i;
+
+ // Init channels
+#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
+ for (i = 0; i < NUMOF(channels); i++) {
+ HAL_INTERRUPT_MASK(channels[i].isr_vector);
+ init_duart_channel(&channels[i]);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_duart_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_duart_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_duart_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_duart_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_duart_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_duart_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_duart_getc_timeout);
+ }
+
+ // Restore original console
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
+
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
+#define __BASE CMA101_DUARTA
+#define _INT CYGNUM_HAL_INTERRUPT_SERIAL_A
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1)
+#define __BASE CMA101_DUARTB
+#define _INT CYGNUM_HAL_INTERRUPT_SERIAL_B
+#endif
+
+#ifdef __BASE
+
+#ifdef CYGSEM_HAL_ROM_MONITOR
+#define CYG_HAL_STARTUP_ROM
+#define CYG_HAL_STARTUP_ROMRAM
+#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#endif
+
+#if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define HAL_DIAG_USES_HARDWARE
+#elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
+#define HAL_DIAG_USES_HARDWARE
+#elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+#define HAL_DIAG_USES_HARDWARE
+#endif
+
+static channel_data_t channel = {
+ (uart_width*) _BASE, 0, 0
+};
+
+#ifdef HAL_DIAG_USES_HARDWARE
+
+void hal_diag_init(void)
+{
+ static int init = 0;
+ char *msg = "\n\rARM eCos\n\r";
+ uart_width lcr;
+
+ if (init++) return;
+
+ init_duart_channel(&channel);
+
+ while (*msg) hal_diag_write_char(*msg++);
+}
+
+#ifdef DEBUG_DIAG
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define DIAG_BUFSIZE 32
+#else
+#define DIAG_BUFSIZE 2048
+#endif
+static char diag_buffer[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+
+void hal_diag_write_char(char c)
+{
+ uart_width lsr;
+
+ hal_diag_init();
+
+ cyg_hal_plf_duart_putc(&channel, c)
+
+#ifdef DEBUG_DIAG
+ diag_buffer[diag_bp++] = c;
+ if (diag_bp == DIAG_BUFSIZE) {
+ while (1) ;
+ diag_bp = 0;
+ }
+#endif
+}
+
+void hal_diag_read_char(char *c)
+{
+ *c = cyg_hal_plf_duart_getc(&channel);
+}
+
+#else // HAL_DIAG relies on GDB
+
+// Initialize diag port - assume GDB channel is already set up
+void hal_diag_init(void)
+{
+ if (0) init_duart_channel(&channel); // avoid warning
+}
+
+// Actually send character down the wire
+static void hal_diag_write_char_serial(char c)
+{
+ cyg_hal_plf_duart_putc(&channel, c);
+}
+
+static bool hal_diag_read_serial(char *c)
+{
+ long timeout = 1000000000; // A long time...
+
+ while (!cyg_hal_plf_duart_getc_nonblock(&channel, c))
+ if (0 == --timeout) return false;
+
+ return true;
+}
+
+void hal_diag_read_char(char *c)
+{
+ while (!hal_diag_read_serial(c)) ;
+}
+
+void hal_diag_write_char(char c)
+{
+ static char line[100];
+ static int pos = 0;
+
+ // No need to send CRs
+ if (c == '\r') return;
+
+ line[pos++] = c;
+
+ if (c == '\n' || pos == sizeof(line)) {
+ CYG_INTERRUPT_STATE old;
+
+ // Disable interrupts. This prevents GDB trying to interrupt us
+ // while we are in the middle of sending a packet. The serial
+ // receive interrupt will be seen when we re-enable interrupts
+ // later.
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+#else
+ HAL_DISABLE_INTERRUPTS(old);
+#endif
+
+ while (1) {
+ static char hex[] = "0123456789ABCDEF";
+ cyg_uint8 csum = 0;
+ int i;
+ char c1;
+
+ hal_diag_write_char_serial('$');
+ hal_diag_write_char_serial('O');
+ csum += 'O';
+ for (i = 0; i < pos; i++) {
+ char ch = line[i];
+ char h = hex[(ch>>4)&0xF];
+ char l = hex[ch&0xF];
+ hal_diag_write_char_serial(h);
+ hal_diag_write_char_serial(l);
+ csum += h;
+ csum += l;
+ }
+ hal_diag_write_char_serial('#');
+ hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
+ hal_diag_write_char_serial(hex[csum&0xF]);
+
+ // Wait for the ACK character '+' from GDB here and handle
+ // receiving a ^C instead. This is the reason for this clause
+ // being a loop.
+ if (!hal_diag_read_serial(&c1))
+ continue; // No response - try sending packet again
+
+ if ( c1 == '+' )
+ break; // a good acknowledge
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
+ if ( c1 == 3 ) {
+ // Ctrl-C: breakpoint.
+ cyg_hal_gdb_interrupt (__builtin_return_address(0));
+ break;
+ }
+#endif
+ // otherwise, loop round again
+ }
+
+ pos = 0;
+
+ // And re-enable interrupts
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+#else
+ HAL_RESTORE_INTERRUPTS(old);
+#endif
+
+ }
+}
+#endif
+
+#endif // __BASE
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
--- /dev/null
+//==========================================================================
+//
+// board_misc.c
+//
+// HAL misc board support code for the board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include <redboot.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h> // Interrupt names
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/fsl_board.h> // Platform specifics
+
+#include <cyg/infra/diag.h> // diag_printf
+
+// All the MM table layout is here:
+#include <cyg/hal/hal_mm.h>
+
+externC void* memset(void *, int, size_t);
+static void mxc_fec_setup(void);
+static void mxc_serial_setup(void);
+
+void hal_mmu_init(void)
+{
+ unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
+ unsigned long i;
+
+ /*
+ * Set the TTB register
+ */
+ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
+
+ /*
+ * Set the Domain Access Control Register
+ */
+ i = ARM_ACCESS_DACR_DEFAULT;
+ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+
+ /*
+ * First clear all TT entries - ie Set them to Faulting
+ */
+ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+
+ /* Actual Virtual Size Attributes Function */
+ /* Base Base MB cached? buffered? access permissions */
+ /* xxx00000 xxx00000 */
+ X_ARM_MMU_SECTION(0x000, 0xF00, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */
+ X_ARM_MMU_SECTION(0x400, 0x400, 0x400, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Internal Regsisters upto SDRAM*/
+ X_ARM_MMU_SECTION(0x800, 0x000, 0x080, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
+ X_ARM_MMU_SECTION(0x800, 0x800, 0x080, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
+ X_ARM_MMU_SECTION(0x800, 0x880, 0x080, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
+ X_ARM_MMU_SECTION(0xB00, 0xB00, 0x20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PSRAM */
+ X_ARM_MMU_SECTION(0xB20, 0xB20, 0x1E0, ARM_UNCACHEABLE, ARM_UNBUFFERABLE,ARM_ACCESS_PERM_RW_RW); /* ESDCTL, WEIM, M3IF, EMI, NFC, External I/O */
+}
+
+//
+// Platform specific initialization
+//
+
+unsigned int g_clock_src;
+
+void plf_hardware_init(void)
+{
+ g_clock_src = FREQ_24MHZ;
+
+ mxc_serial_setup();
+ mxc_fec_setup();
+}
+
+static void mxc_serial_setup(void)
+{
+ // UART1
+ /*RXD1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x170);
+ writel(0x1E0, IOMUXC_BASE_ADDR + 0x368);
+
+ /*TXD1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x174);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x36c);
+
+ /*RTS1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x178);
+ writel(0x1E0, IOMUXC_BASE_ADDR + 0x370);
+
+ /*CTS1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x17c);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x374);
+}
+
+static void mxc_fec_setup(void)
+{
+ unsigned int val;
+
+ /* FEC_TX_CLK */
+ writel(0, IOMUXC_BASE_ADDR + 0x01E8);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x03E0);
+
+ /* FEC_RX_DV */
+ writel(0, IOMUXC_BASE_ADDR + 0x01E4);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x03DC);
+
+ /* FEC_RDATA0 */
+ writel(0, IOMUXC_BASE_ADDR + 0x01DC);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x03D4);
+
+ /* FEC_TDATA0 */
+ writel(0, IOMUXC_BASE_ADDR + 0x01D0);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x03C8);
+
+ /* FEC_TX_EN */
+ writel(0, IOMUXC_BASE_ADDR + 0x01D8);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x03D0);
+
+ /* FEC_MDC */
+ writel(0, IOMUXC_BASE_ADDR + 0x01C8);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x03C0);
+
+ /* FEC_MDIO */
+ writel(0, IOMUXC_BASE_ADDR + 0x01CC);
+ writel(0x1F0, IOMUXC_BASE_ADDR + 0x03C4);
+
+ /* FEC_RDATA1 */
+ writel(0, IOMUXC_BASE_ADDR + 0x01E0);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x03D8);
+
+ /* FEC_TDATA1 */
+ writel(0, IOMUXC_BASE_ADDR + 0x01D4);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x03CC);
+
+ /*
+ * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins.
+ * Assert FEC_RESET_B, then power up the PHY by asserting
+ * FEC_ENABLE, at the same time lifting FEC_RESET_B.
+ *
+ * FEC_RESET_B: gpio2[3] is ALT 5 mode of pin A17
+ * FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin D12
+ */
+ writel(0x5, IOMUXC_BASE_ADDR + 0x001C);
+ writel(0x5, IOMUXC_BASE_ADDR + 0x0094);
+
+ writel(0x8, IOMUXC_BASE_ADDR + 0x0238); // open drain
+ writel(0x0, IOMUXC_BASE_ADDR + 0x028C); // cmos, no pu/pd
+
+ /* make the pins output */
+ val = (1 << 3) | readl(GPIO2_BASE_ADDR + GPIO_GDIR);
+ writel(val, GPIO2_BASE_ADDR + GPIO_GDIR);
+
+ val = (1 << 8) | readl(GPIO4_BASE_ADDR + GPIO_GDIR);
+ writel(val, GPIO4_BASE_ADDR + GPIO_GDIR);
+
+ /* drop PHY power */
+ val = readl(GPIO2_BASE_ADDR + GPIO_DR) & ~(1 << 3);
+ writel(val, GPIO2_BASE_ADDR + GPIO_DR);
+
+ /* assert reset */
+ val = readl(GPIO4_BASE_ADDR + GPIO_DR) & ~(1 << 8);
+ writel(val, GPIO4_BASE_ADDR + GPIO_DR);
+ hal_delay_us(2); // spec says 1us min
+
+ /* turn on power & lift reset */
+ val = (1 << 3) | readl(GPIO2_BASE_ADDR + GPIO_DR);
+ writel(val, GPIO2_BASE_ADDR + GPIO_DR);
+ val = (1 << 8) | readl(GPIO4_BASE_ADDR + GPIO_DR);
+ writel(val, GPIO4_BASE_ADDR + GPIO_DR);
+}
+
+static void mxc_cspi_setup(void)
+{
+ /*CSPI1*/
+ /*SCLK*/
+ writel(0, IOMUXC_BASE_ADDR + 0x180);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x5c4);
+ /*SPI_RDY*/
+ writel(0, IOMUXC_BASE_ADDR + 0x184);
+ writel(0x1E0, IOMUXC_BASE_ADDR + 0x5c8);
+ /*MOSI*/
+ writel(0, IOMUXC_BASE_ADDR + 0x170);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x5b4);
+ /*MISO*/
+ writel(0, IOMUXC_BASE_ADDR + 0x174);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x5b8);
+ /*SS1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x17C);
+ writel(0x1E0, IOMUXC_BASE_ADDR + 0x5C0);
+}
+
+void mxc_i2c_init(unsigned int module_base)
+{
+ switch(module_base) {
+ case I2C_BASE_ADDR:
+ /* Pins: SION */
+ writel(0x10, IOMUXC_BASE_ADDR + 0x150); /* I2C1_CLK */
+ writel(0x10, IOMUXC_BASE_ADDR + 0x154); /* I2C1_DAT */
+
+ /* Pads: HYS, 100k Pull-up, open drain */
+ writel(0x1E8, IOMUXC_BASE_ADDR + 0x348); /* I2C1_CLK */
+ writel(0x1E8, IOMUXC_BASE_ADDR + 0x34c); /* I2C1_DAT */
+ break;
+ case I2C2_BASE_ADDR:
+ /* Pins: ALT1 (of FEC_RDATA1, FEC_RX_DV pins), SION */
+ writel(0x11, IOMUXC_BASE_ADDR + 0x1e0); /* I2C2_CLK */
+ writel(0x11, IOMUXC_BASE_ADDR + 0x1e4); /* I2C2_DAT */
+
+ /* Pads: HYS, 100k Pull-up, open drain */
+ writel(0x1E8, IOMUXC_BASE_ADDR + 0x3d8); /* I2C2_CLK */
+ writel(0x1E8, IOMUXC_BASE_ADDR + 0x3dc); /* I2C2_DAT */
+ break;
+ case I2C3_BASE_ADDR:
+ /* Pins: ALT2 (of HSYNC, VSYNC pins), SION */
+ writel(0x12, IOMUXC_BASE_ADDR + 0x108); /* I2C3_CLK */
+ writel(0x12, IOMUXC_BASE_ADDR + 0x10c); /* I2C3_DAT */
+
+ /* Pads: HYS, 100k Pull-up, open drain */
+ writel(0x1E8, IOMUXC_BASE_ADDR + 0x300); /* I2C2_CLK */
+ writel(0x1E8, IOMUXC_BASE_ADDR + 0x304); /* I2C2_DAT */
+ break;
+ default:
+ break;
+ }
+}
+void mxc_mmc_init(base_address)
+{
+ unsigned int val;
+
+ switch(base_address) {
+ case MMC_SDHC1_BASE_ADDR:
+ /* Pins */
+ writel(0x10, IOMUXC_BASE_ADDR + 0x190); /* SD1_CMD */
+ writel(0x10, IOMUXC_BASE_ADDR + 0x194); /* SD1_CLK */
+ writel(0x00, IOMUXC_BASE_ADDR + 0x198); /* SD1_DATA0 */
+ writel(0x00, IOMUXC_BASE_ADDR + 0x19c); /* SD1_DATA1 */
+ writel(0x00, IOMUXC_BASE_ADDR + 0x1a0); /* SD1_DATA2 */
+ writel(0x00, IOMUXC_BASE_ADDR + 0x1a4); /* SD1_DATA3 */
+ writel(0x06, IOMUXC_BASE_ADDR + 0x094); /* D12 (SD1_DATA4) */
+ writel(0x06, IOMUXC_BASE_ADDR + 0x090); /* D13 (SD1_DATA5) */
+ writel(0x06, IOMUXC_BASE_ADDR + 0x08c); /* D14 (SD1_DATA6) */
+ writel(0x06, IOMUXC_BASE_ADDR + 0x088); /* D15 (SD1_DATA7) */
+ writel(0x05, IOMUXC_BASE_ADDR + 0x010); /* A14 (SD1_WP) */
+ writel(0x05, IOMUXC_BASE_ADDR + 0x014); /* A15 (SD1_DET) */
+
+ /* Pads */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x388); /* SD1_CMD */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x38c); /* SD1_CLK */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x390); /* SD1_DATA0 */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x394); /* SD1_DATA1 */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x398); /* SD1_DATA2 */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x39c); /* SD1_DATA3 */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x28c); /* D12 (SD1_DATA4) */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x288); /* D13 (SD1_DATA5) */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x284); /* D14 (SD1_DATA6) */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x280); /* D15 (SD1_DATA7) */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x230); /* A14 (SD1_WP) */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x234); /* A15 (SD1_DET) */
+
+ /*
+ * Set write protect and card detect gpio as inputs
+ * A14 (SD1_WP) and A15 (SD1_DET)
+ */
+ val = ~(3 << 0) & readl(GPIO1_BASE_ADDR + GPIO_GDIR);
+ writel(val, GPIO1_BASE_ADDR + GPIO_GDIR);
+
+ break;
+ case MMC_SDHC2_BASE_ADDR:
+ /* Pins */
+ writel(0x16, IOMUXC_BASE_ADDR + 0x0e8); /* LD8 (SD1_CMD) */
+ writel(0x16, IOMUXC_BASE_ADDR + 0x0ec); /* LD9 (SD1_CLK) */
+ writel(0x06, IOMUXC_BASE_ADDR + 0x0f0); /* LD10 (SD1_DATA0) */
+ writel(0x06, IOMUXC_BASE_ADDR + 0x0f4); /* LD11 (SD1_DATA1) */
+ writel(0x06, IOMUXC_BASE_ADDR + 0x0f8); /* LD12 (SD1_DATA2) */
+ writel(0x06, IOMUXC_BASE_ADDR + 0x0fc); /* LD13 (SD1_DATA3) */
+ writel(0x02, IOMUXC_BASE_ADDR + 0x120); /* CSI_D2 (SD1_DATA4) */
+ writel(0x02, IOMUXC_BASE_ADDR + 0x124); /* CSI_D3 (SD1_DATA5) */
+ writel(0x02, IOMUXC_BASE_ADDR + 0x128); /* CSI_D4 (SD1_DATA6) */
+ writel(0x02, IOMUXC_BASE_ADDR + 0x12c); /* CSI_D5 (SD1_DATA7) */
+
+ /* Pads */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x2e0); /* LD8 (SD1_CMD) */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x2e4); /* LD9 (SD1_CLK) */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x2e8); /* LD10 (SD1_DATA0) */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x2ec); /* LD11 (SD1_DATA1) */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x2f0); /* LD12 (SD1_DATA2) */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x2f4); /* LD13 (SD1_DATA3) */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x318); /* CSI_D2 (SD1_DATA4) */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x31c); /* CSI_D3 (SD1_DATA5) */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x320); /* CSI_D4 (SD1_DATA6) */
+ writel(0xD1, IOMUXC_BASE_ADDR + 0x324); /* CSI_D5 (SD1_DATA7) */
+
+ default:
+ break;
+ }
+}
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+typedef void code_fun(void);
+
+void board_program_new_stack(void *func)
+{
+ register CYG_ADDRESS stack_ptr asm("sp");
+ register CYG_ADDRESS old_stack asm("r4");
+ register code_fun *new_func asm("r0");
+ old_stack = stack_ptr;
+ stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
+ new_func = (code_fun*)func;
+ new_func();
+ stack_ptr = old_stack;
+}
+
+static void display_clock_src(void)
+{
+ diag_printf("\n");
+ diag_printf("Clock input is 24 MHz");
+}
+RedBoot_init(display_clock_src, RedBoot_INIT_LAST);
+
+// ------------------------------------------------------------------------
--- /dev/null
+//==========================================================================
+//
+// redboot_cmds.c
+//
+// Board [platform] specific RedBoot commands
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+#include <redboot.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/plf_mmap.h>
+#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <flash_config.h>
+
+#if (REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE)
+#error REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE
+#endif
+
+RedBoot_config_option("Board specifics",
+ brd_specs,
+ ALWAYS_ENABLED,
+ true,
+ CONFIG_INT,
+ 0
+ );
+#endif //CYGSEM_REDBOOT_FLASH_CONFIG
+
+char HAL_PLATFORM_EXTRA[55] = " PASS 1.0 [x32 DDR]";
+
+static void runImg(int argc, char *argv[]);
+
+RedBoot_cmd("run",
+ "Run an image at a location with MMU off",
+ "[<virtual addr>]",
+ runImg
+ );
+
+void launchRunImg(unsigned long addr)
+{
+ asm volatile ("mov r12, r0;");
+ HAL_MMU_OFF();
+ asm volatile (
+ "mov r0, #0;"
+ "mov r1, r12;"
+ "mov r11, #0;"
+ "mov r12, #0;"
+ "mrs r10, cpsr;"
+ "bic r10, r10, #0xF0000000;"
+ "msr cpsr_f, r10;"
+ "mov pc, r1"
+ );
+}
+
+extern unsigned long entry_address;
+
+static void runImg(int argc,char *argv[])
+{
+ unsigned int virt_addr, phys_addr;
+
+ // Default physical entry point for Symbian
+ if (entry_address == 0xFFFFFFFF)
+ virt_addr = 0x800000;
+ else
+ virt_addr = entry_address;
+
+ if (!scan_opts(argc,argv,1,0,0,(void*)&virt_addr,
+ OPTION_ARG_TYPE_NUM, "virtual address"))
+ return;
+
+ if (entry_address != 0xFFFFFFFF)
+ diag_printf("load entry_address=0x%lx\n", entry_address);
+ HAL_VIRT_TO_PHYS_ADDRESS(virt_addr, phys_addr);
+
+ diag_printf("virt_addr=0x%x\n",virt_addr);
+ diag_printf("phys_addr=0x%x\n",phys_addr);
+
+ launchRunImg(phys_addr);
+}
+
+#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYG_HAL_STARTUP_ROMRAM)
+
+RedBoot_cmd("romupdate",
+ "Update Redboot with currently running image",
+ "",
+ romupdate
+ );
+
+extern int flash_program(void *_addr, void *_data, int len, void **err_addr);
+extern int flash_erase(void *addr, int len, void **err_addr);
+extern char *flash_errmsg(int err);
+extern unsigned char *ram_end; //ram end is where the redboot starts FIXME: use PC value
+
+#ifdef CYGPKG_IO_FLASH
+void romupdate(int argc, char *argv[])
+{
+ void *err_addr, *base_addr;
+ int stat;
+
+ if (IS_FIS_FROM_MMC()) {
+ diag_printf("Updating ROM in MMC/SD flash\n");
+ base_addr = (void*)0;
+ /* Read the first 1K from the card */
+ mmc_data_read((cyg_uint32*)ram_end, 0x400, base_addr);
+ diag_printf("Programming Redboot to MMC/SD flash\n");
+ mmc_data_write((cyg_uint32*)ram_end, CYGBLD_REDBOOT_MIN_IMAGE_SIZE, (cyg_uint32)base_addr);
+ return;
+ } else if (IS_FIS_FROM_NAND()) {
+ base_addr = (void*)MXC_NAND_BASE_DUMMY;
+ diag_printf("Updating ROM in NAND flash\n");
+ } else if (IS_FIS_FROM_NOR()) {
+ base_addr = (void*)BOARD_FLASH_START;
+ diag_printf("Updating ROM in NOR flash\n");
+ } else {
+ diag_printf("romupdate not supported\n");
+ diag_printf("Use \"factive [NOR|NAND|MMC]\" to select either NOR, NAND or MMC flash\n");
+ return;
+ }
+
+ // Erase area to be programmed
+ if ((stat = flash_erase((void *)base_addr,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ (void **)&err_addr)) != 0) {
+ diag_printf("Can't erase region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ return;
+ }
+ // Now program it
+ if ((stat = flash_program((void *)base_addr, (void *)ram_end,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ (void **)&err_addr)) != 0) {
+ diag_printf("Can't program region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ }
+}
+
+RedBoot_cmd("factive",
+ "Enable one flash media for Redboot",
+ "[NOR | NAND | MMC]",
+ factive
+ );
+
+void factive(int argc, char *argv[])
+{
+ unsigned long phys_addr;
+
+ if (argc != 2) {
+ diag_printf("Invalid factive cmd\n");
+ return;
+ }
+
+ if (strcasecmp(argv[1], "NOR") == 0) {
+#ifndef MXCFLASH_SELECT_NOR
+ diag_printf("Not supported\n");
+ return;
+#else
+ MXC_ASSERT_NOR_BOOT();
+#endif
+ } else if (strcasecmp(argv[1], "NAND") == 0) {
+#ifndef MXCFLASH_SELECT_NAND
+ diag_printf("Not supported\n");
+ return;
+#else
+ MXC_ASSERT_NAND_BOOT();
+#endif
+ } else if (strcasecmp(argv[1], "MMC") == 0) {
+#ifndef MXCFLASH_SELECT_MMC
+ diag_printf("Not supported\n");
+ return;
+#else
+ MXC_ASSERT_MMC_BOOT();
+#endif
+ } else {
+ diag_printf("Invalid command: %s\n", argv[1]);
+ return;
+ }
+ HAL_VIRT_TO_PHYS_ADDRESS(ram_end, phys_addr);
+
+ launchRunImg(phys_addr);
+}
+#endif //CYGPKG_IO_FLASH
+#endif /* CYG_HAL_STARTUP_ROMRAM */
+
+static void setcorevol(int argc, char *argv[]);
+
+RedBoot_cmd("setcorevol",
+ "Set the core voltage. Setting is not checked against current core frequency.",
+ "[1.16 | 1.2 | 1.23 | 1.27 | 1.3 | 1.34 | 1.38 | 1.41 | 1.45 | 1.49 | 1.52 | 1.56 | 1.59 | 1.63 | 1.67 | 1.7]",
+ setcorevol
+ );
+
+static void setcorevol(int argc, char *argv[])
+{
+ unsigned int coreVol;
+
+ /* check if the number of args is OK. 1 arg expected. argc = 2 */
+ if(argc != 2) {
+ diag_printf("Invalid argument. Need to specify a voltage\n");
+ return;
+ }
+
+ /* check if the argument is valid. */
+ if (strcasecmp(argv[1], "1.16") == 0) { /* -20% */
+ coreVol = 0x8;
+ } else if (strcasecmp(argv[1], "1.2") == 0) {
+ coreVol = 0x9;
+ } else if (strcasecmp(argv[1], "1.23") == 0) {
+ coreVol = 0xA;
+ } else if (strcasecmp(argv[1], "1.27") == 0) {
+ coreVol = 0xB;
+ } else if (strcasecmp(argv[1], "1.3") == 0) {
+ coreVol = 0xC;
+ } else if (strcasecmp(argv[1], "1.34") == 0) {
+ coreVol = 0xD;
+ } else if (strcasecmp(argv[1], "1.38") == 0) {
+ coreVol = 0xE;
+ } else if (strcasecmp(argv[1], "1.41") == 0) {
+ coreVol = 0xF;
+ } else if (strcasecmp(argv[1], "1.45") == 0) { /* 0% */
+ coreVol = 0x0;
+ } else if (strcasecmp(argv[1], "1.49") == 0) {
+ coreVol = 0x1;
+ } else if (strcasecmp(argv[1], "1.52") == 0) {
+ coreVol = 0x2;
+ } else if (strcasecmp(argv[1], "1.56") == 0) {
+ coreVol = 0x3;
+ } else if (strcasecmp(argv[1], "1.59") == 0) {
+ coreVol = 0x4;
+ } else if (strcasecmp(argv[1], "1.63") == 0) {
+ coreVol = 0x5;
+ } else if (strcasecmp(argv[1], "1.67") == 0) {
+ coreVol = 0x6;
+ } else if (strcasecmp(argv[1], "1.7") == 0) { /* +17.5% */
+ coreVol = 0x7;
+ } else {
+ diag_printf("Invalid argument. Type \"help setcorevol\" for valid settings\n");
+ return;
+ }
+
+ pmic_reg(0x08, coreVol << 1, 1);
+
+ return;
+}
--- /dev/null
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): gthomas
+# Original data: gthomas
+# Contributors:
+# Date: 2000-05-08
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+cdl_package CYGPKG_HAL_ARM_MX25 {
+ display "Freescale SoC architecture"
+ parent CYGPKG_HAL_ARM
+ hardware
+ include_dir cyg/hal
+ define_header hal_arm_soc.h
+ description "
+ This HAL variant package provides generic
+ support for the Freescale SoC. It is also
+ necessary to select a specific target platform HAL
+ package."
+
+ implements CYGINT_HAL_ARM_ARCH_ARM9
+ implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+
+ # Let the architectural HAL see this variant's interrupts file -
+ # the SoC has no variation between targets here.
+ define_proc {
+ puts $::cdl_header "#define CYGBLD_HAL_VAR_INTS_H <cyg/hal/hal_var_ints.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H"
+
+ puts $::cdl_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 1000000"
+ }
+
+ compile soc_diag.c soc_misc.c
+ compile -library=libextras.a cmds.c
+
+ cdl_option CYGHWR_MX25_MDDR {
+ display "mDDR/DDR2 support"
+ default_value 0
+ description "
+ When this option is enabled, it indicates support
+ for Mobile DDR on the MX25 3stack CPU board. mDDR
+ was used on TO1.0 boards. Subsequent boards use
+ DDR2 memory."
+ define_proc {
+ puts $::cdl_system_header "#define MEMORY_MDDR_ENABLE"
+ }
+ }
+
+ cdl_option CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK {
+ display "Processor clock rate"
+ active_if { CYG_HAL_STARTUP == "ROM" }
+ flavor data
+ legal_values 150000 200000
+ default_value { CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT ?
+ CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT : 150000}
+ description "
+ The processor can run at various frequencies.
+ These values are expressed in KHz. Note that there are
+ several steppings of the rated to run at different
+ maximum frequencies. Check the specs to make sure that your
+ particular processor can run at the rate you select here."
+ }
+
+ # Real-time clock/counter specifics
+ cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+ display "Real-time clock constants"
+ flavor none
+ no_define
+
+ cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+ display "Real-time clock numerator"
+ flavor data
+ calculated 1000000000
+ }
+ cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+ display "Real-time clock denominator"
+ flavor data
+ default_value 100
+ description "
+ This option selects the heartbeat rate for the real-time clock.
+ The rate is specified in ticks per second. Change this value
+ with caution - too high and your system will become saturated
+ just handling clock interrupts, too low and some operations
+ such as thread scheduling may become sluggish."
+ }
+ cdl_option CYGNUM_HAL_RTC_PERIOD {
+ display "Real-time clock period"
+ flavor data
+ calculated (3686400/CYGNUM_HAL_RTC_DENOMINATOR) ;# Clock for OS Timer is 3.6864MHz
+ }
+ }
+
+ # Control over hardware layout.
+ cdl_interface CYGHWR_HAL_ARM_SOC_UART1 {
+ display "UART1 available as diagnostic/debug channel"
+ description "
+ The chip has multiple serial channels which may be
+ used for different things on different platforms. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_SOC_UART2 {
+ display "UART2 available as diagnostic/debug channel"
+ description "
+ The chip has multiple serial channels which may be
+ used for different things on different platforms. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_SOC_UART3 {
+ display "UART3 available as diagnostic/debug channel"
+ description "
+ The chip has multiple serial channels which may be
+ used for different things on different platforms. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_SOC_UART4 {
+ display "UART4 available as diagnostic/debug channel"
+ description "
+ The chip has multiple serial channels which may be
+ used for different things on different platforms. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_SOC_UART5 {
+ display "UART5 available as diagnostic/debug channel"
+ description "
+ The chip has multiple serial channels which may be
+ used for different things on different platforms. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGINT_DEVS_ETH_FEC_REQUIRED {
+ display "FEC ethernet driver required"
+ }
+
+ implements CYGINT_DEVS_ETH_FEC_REQUIRED
+}
--- /dev/null
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+
+//=============================================================================
+//
+// hal_cache.h
+//
+// HAL cache control API
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
+
+//-----------------------------------------------------------------------------
+// Cache dimensions
+
+// Data cache
+#define HAL_DCACHE_SIZE 0x4000 // 16KB Size of data cache in bytes
+#define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
+#define HAL_DCACHE_WAYS 64 // Associativity of the cache
+
+// Instruction cache
+#define HAL_ICACHE_SIZE 0x4000 // Size of cache in bytes
+#define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
+#define HAL_ICACHE_WAYS 64 // Associativity of the cache
+
+#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
+#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
+
+# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
+# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x20
+# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x100
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mrc p15,0,r1,c1,c0,0;" \
+ "orr r1,r1,#0x0007;" /* enable DCache (also ensures */ \
+ /* the MMU, alignment faults, and */ \
+ "mcr p15,0,r1,c1,c0,0" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mov r1,#0;" \
+ "mcr p15,0,r1,c7,c6,0;" /* clear data cache */ \
+ "mrc p15,0,r1,c1,c0,0;" \
+ "bic r1,r1,#0x0004;" /* disable DCache */ \
+ /* but not MMU and alignment faults */ \
+ "mcr p15,0,r1,c1,c0,0" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Sync data cache in range
+#define HAL_DCACHE_SYNC_RANGE(start, end) \
+CYG_MACRO_START \
+ asm volatile ( \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ " bic %0, %0, %3;" \
+ " add %1, %1, %3;" \
+ " bic %1, %1, %3;" \
+ "1: cmp %1, %0;" \
+ " mcrhi p15, 0, %0, c7, c14, 1;" \
+ " addhi %0, %0, %2;" \
+ " bhi 1b;" \
+ " mov %0, #0;" \
+ " mcr p15, 0, %0, c7, c10, 4" \
+ : \
+ :"r"(start), "r"(end), \
+ "I"(HAL_DCACHE_LINE_SIZE), \
+ "I"(HAL_DCACHE_LINE_SIZE-1) \
+ ); \
+CYG_MACRO_END
+
+// Invalidate data cache in range
+#define HAL_DCACHE_INVALID_RANGE(start, end) \
+CYG_MACRO_START \
+ asm volatile ( \
+ " bic %0, %0, %3;" \
+ " add %1, %1, %3;" \
+ " bic %1, %1, %3;" \
+ "1: mcr p15, 0, %0, c7, c6, 1;" \
+ " add %0, %0, %2;" \
+ " cmp %0, %1;" \
+ " blo 1b" \
+ : \
+ :"r"(start), "r"(end), \
+ "I"(HAL_DCACHE_LINE_SIZE), \
+ "I"(HAL_DCACHE_LINE_SIZE-1) \
+ ); \
+CYG_MACRO_END
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL() \
+CYG_MACRO_START /* this macro can discard dirty cache lines. */ \
+ asm volatile ( \
+ "mov r0,#0;" \
+ "mcr p15,0,r0,c7,c6,0;" /* flush d-cache */ \
+ "mcr p15,0,r0,c8,c7,0;" /* flush i+d-TLBs */ \
+ : \
+ : \
+ : "r0","memory" /* clobber list */); \
+CYG_MACRO_END
+
+// Synchronize the contents of the cache with memory.
+// using ARM9's defined(CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX)
+#if 1
+#define HAL_DCACHE_SYNC() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "1: " \
+ "mrc p15, 0, r15, c7, c14, 3;" \
+ "bne 1b;" \
+ "mov r0, #0x0;" \
+ "mcr p15,0,r0,c7,c10,4;" /* drain the write buffer */ \
+ : \
+ : \
+ : "r0" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+#else
+#define HAL_DCACHE_SYNC() \
+CYG_MACRO_START \
+ cyg_uint32 _tmp1, _tmp2; \
+ asm volatile ( \
+ "mov %0, #0;" \
+ "1: " \
+ "mov %1, #0;" \
+ "2: " \
+ "orr r0,%0,%1;" \
+ "mcr p15,0,r0,c7,c14,2;" /* clean index in DCache */ \
+ "add %1,%1,%2;" \
+ "cmp %1,%3;" \
+ "bne 2b;" \
+ "add %0,%0,#0x04000000;" /* get to next index */ \
+ "cmp %0,#0;" \
+ "bne 1b;" \
+ "mov r0, #0x0;" \
+ "mcr p15,0,r0,c7,c10,4;" /* drain the write buffer */ \
+ : "=r" (_tmp1), "=r" (_tmp2) \
+ : "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP), \
+ "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT) \
+ : "r0" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+#endif
+
+// Query the state of the data cache
+#define HAL_DCACHE_IS_ENABLED(_state_) \
+CYG_MACRO_START \
+ register int reg; \
+ asm volatile ( \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "mrc p15,0,%0,c1,c0,0;" \
+ : "=r"(reg) \
+ : \
+ ); \
+ (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \
+CYG_MACRO_END
+
+// Purge contents of data cache
+//#define HAL_DCACHE_PURGE_ALL() -- not used
+
+// Set the data cache refill burst size
+//#define HAL_DCACHE_BURST_SIZE(_size_)
+
+// Set the data cache write mode
+//#define HAL_DCACHE_WRITE_MODE( _mode_ )
+
+//#define HAL_DCACHE_WRITETHRU_MODE 0
+//#define HAL_DCACHE_WRITEBACK_MODE 1
+
+// Load the contents of the given address range into the data cache
+// and then lock the cache so that it stays there.
+//#define HAL_DCACHE_LOCK(_base_, _size_)
+
+// Undo a previous lock operation
+//#define HAL_DCACHE_UNLOCK(_base_, _size_)
+
+// Unlock entire cache
+//#define HAL_DCACHE_UNLOCK_ALL()
+
+//-----------------------------------------------------------------------------
+// Data cache line control
+
+// Allocate cache lines for the given address range without reading its
+// contents from memory.
+//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
+
+// Write dirty cache lines to memory and invalidate the cache entries
+// for the given address range.
+//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
+
+// Invalidate cache lines in the given range without writing to memory.
+//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
+
+// Write dirty cache lines to memory for the given address range.
+//#define HAL_DCACHE_STORE( _base_ , _size_ )
+
+// Preread the given range into the cache with the intention of reading
+// from it later.
+//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
+
+// Preread the given range into the cache with the intention of writing
+// to it later.
+//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
+
+// Allocate and zero the cache lines associated with the given range.
+//#define HAL_DCACHE_ZERO( _base_ , _size_ )
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mrc p15,0,r1,c1,c0,0;" \
+ "orr r1,r1,#0x1000;" \
+ "orr r1,r1,#0x0003;" /* enable ICache (also ensures */ \
+ /* that MMU and alignment faults */ \
+ /* are enabled) */ \
+ "mcr p15,0,r1,c1,c0,0" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Query the state of the instruction cache
+#define HAL_ICACHE_IS_ENABLED(_state_) \
+CYG_MACRO_START \
+ register cyg_uint32 reg; \
+ asm volatile ("mrc p15,0,%0,c1,c0,0" \
+ : "=r"(reg) \
+ : \
+ ); \
+ (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \
+CYG_MACRO_END
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mrc p15,0,r1,c1,c0,0;" \
+ "bic r1,r1,#0x1000;" /* disable ICache (but not MMU, etc) */ \
+ "mcr p15,0,r1,c1,c0,0;" \
+ "mov r1,#0;" \
+ "mcr p15,0,r1,c7,c5,0;" /* flush ICache */ \
+ "nop;" /* next few instructions may be via cache */ \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL() \
+CYG_MACRO_START \
+ /* this macro can discard dirty cache lines (N/A for ICache) */ \
+ asm volatile ( \
+ "mov r1,#0;" \
+ "mcr p15,0,r1,c7,c5,0;" /* flush ICache */ \
+ "mcr p15,0,r1,c8,c5,0;" /* flush ITLB only */ \
+ "nop;" /* next few instructions may be via cache */ \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Synchronize the contents of the cache with memory.
+// (which includes flushing out pending writes)
+#define HAL_ICACHE_SYNC() \
+CYG_MACRO_START \
+ HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
+ HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
+CYG_MACRO_END
+
+#else
+
+
+// Set the instruction cache refill burst size
+//#define HAL_ICACHE_BURST_SIZE(_size_)
+
+// Load the contents of the given address range into the instruction cache
+// and then lock the cache so that it stays there.
+//#define HAL_ICACHE_LOCK(_base_, _size_)
+
+// Undo a previous lock operation
+//#define HAL_ICACHE_UNLOCK(_base_, _size_)
+
+// Unlock entire cache
+//#define HAL_ICACHE_UNLOCK_ALL()
+
+//-----------------------------------------------------------------------------
+// Instruction cache line control
+
+// Invalidate cache lines in the given range without writing to memory.
+//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_CACHE_H
+// End of hal_cache.h
--- /dev/null
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+
+/*=============================================================================
+//
+// hal_diag.h
+//
+// HAL Support for Kernel Diagnostic Routines
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+#include <cyg/hal/hal_if.h>
+
+#define HAL_DIAG_INIT() hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
+
+#else // everything by steam
+
+/*---------------------------------------------------------------------------*/
+/* functions implemented in hal_diag.c */
+
+externC void hal_diag_init(void);
+externC void hal_diag_write_char(char c);
+externC void hal_diag_read_char(char *c);
+
+/*---------------------------------------------------------------------------*/
+
+#define HAL_DIAG_INIT() hal_diag_init()
+
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_)
+
+#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_)
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
+// LED
+
+externC void hal_diag_led(int n);
+
+/*---------------------------------------------------------------------------*/
+/* end of hal_diag.h */
+#endif /* CYGONCE_HAL_DIAG_H */
--- /dev/null
+#ifndef CYGONCE_HAL_MM_H
+#define CYGONCE_HAL_MM_H
+
+//=============================================================================
+//
+// hal_mm.h
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+// -------------------------------------------------------------------------
+// MMU initialization:
+//
+// These structures are laid down in memory to define the translation
+// table.
+//
+
+/*
+ * Translation Table Base Bit Masks
+ */
+#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
+
+/*
+ * Domain Access Control Bit Masks
+ */
+#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2)
+
+struct ARM_MMU_FIRST_LEVEL_FAULT {
+ unsigned int id : 2;
+ unsigned int sbz : 30;
+};
+
+#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
+
+struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
+ unsigned int id : 2;
+ unsigned int imp : 2;
+ unsigned int domain : 4;
+ unsigned int sbz : 1;
+ unsigned int base_address : 23;
+};
+
+#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
+
+struct ARM_MMU_FIRST_LEVEL_SECTION {
+ unsigned int id : 2;
+ unsigned int b : 1;
+ unsigned int c : 1;
+ unsigned int imp : 1;
+ unsigned int domain : 4;
+ unsigned int sbz0 : 1;
+ unsigned int ap : 2;
+ unsigned int sbz1 : 8;
+ unsigned int base_address : 12;
+};
+
+#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
+
+struct ARM_MMU_FIRST_LEVEL_RESERVED {
+ unsigned int id : 2;
+ unsigned int sbz : 30;
+};
+
+#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
+
+#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
+ (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
+
+#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
+
+#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
+ cacheable, bufferable, perm) \
+ CYG_MACRO_START \
+ register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
+ \
+ desc.word = 0; \
+ desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
+ desc.section.domain = 0; \
+ desc.section.c = (cacheable); \
+ desc.section.b = (bufferable); \
+ desc.section.ap = (perm); \
+ desc.section.base_address = (actual_base); \
+ *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
+ = desc.word; \
+ CYG_MACRO_END
+
+#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \
+ { \
+ int i; int j = abase; int k = vbase; \
+ for (i = size; i > 0 ; i--,j++,k++) { \
+ ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
+ } \
+ }
+
+union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
+ unsigned long word;
+ struct ARM_MMU_FIRST_LEVEL_FAULT fault;
+ struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
+ struct ARM_MMU_FIRST_LEVEL_SECTION section;
+ struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
+};
+
+#define ARM_UNCACHEABLE 0
+#define ARM_CACHEABLE 1
+#define ARM_UNBUFFERABLE 0
+#define ARM_BUFFERABLE 1
+
+#define ARM_ACCESS_PERM_NONE_NONE 0
+#define ARM_ACCESS_PERM_RO_NONE 0
+#define ARM_ACCESS_PERM_RO_RO 0
+#define ARM_ACCESS_PERM_RW_NONE 1
+#define ARM_ACCESS_PERM_RW_RO 2
+#define ARM_ACCESS_PERM_RW_RW 3
+
+/*
+ * Initialization for the Domain Access Control Register
+ */
+#define ARM_ACCESS_DACR_DEFAULT ( \
+ ARM_ACCESS_TYPE_MANAGER(0) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(1) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(2) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(3) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(4) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(5) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(6) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(7) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(8) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(9) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(10) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(11) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(12) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(13) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(14) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(15) )
+
+// ------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_MM_H
+// End of hal_mm.h
+
+
+
+
+
--- /dev/null
+//==========================================================================
+//
+// hal_soc.h
+//
+// SoC chip definitions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#ifndef __HAL_SOC_H__
+#define __HAL_SOC_H__
+
+#ifdef __ASSEMBLER__
+
+#define REG8_VAL(a) (a)
+#define REG16_VAL(a) (a)
+#define REG32_VAL(a) (a)
+
+#define REG8_PTR(a) (a)
+#define REG16_PTR(a) (a)
+#define REG32_PTR(a) (a)
+
+#else /* __ASSEMBLER__ */
+
+extern char HAL_PLATFORM_EXTRA[];
+#define REG8_VAL(a) ((unsigned char)(a))
+#define REG16_VAL(a) ((unsigned short)(a))
+#define REG32_VAL(a) ((unsigned int)(a))
+
+#define REG8_PTR(a) ((volatile unsigned char *)(a))
+#define REG16_PTR(a) ((volatile unsigned short *)(a))
+#define REG32_PTR(a) ((volatile unsigned int *)(a))
+#define readb(a) (*(volatile unsigned char *)(a))
+#define readw(a) (*(volatile unsigned short *)(a))
+#define readl(a) (*(volatile unsigned int *)(a))
+#define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
+#define writew(v,a) (*(volatile unsigned short *)(a) = (v))
+#define writel(v,a) (*(volatile unsigned int *)(a) = (v))
+
+#endif /* __ASSEMBLER__ */
+
+/*
+ * Default Memory Layout Definitions
+ */
+
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR 0x43F00000
+#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
+#define MAX_BASE_ADDR 0x43F04000
+#define CLKCTL_BASE_ADDR 0x43F08000
+#define ETB_SLOT4_BASE_ADDR 0x43F0C000
+#define ETB_SLOT5_BASE_ADDR 0x43F1000l
+#define ECT_CTIO_BASE_ADDR 0x43F18000
+#define I2C_BASE_ADDR 0x43F80000
+#define I2C3_BASE_ADDR 0x43F84000
+#define CAN1_BASE_ADDR 0x43F88000
+#define CAN2_BASE_ADDR 0x43F8C000
+#define UART1_BASE_ADDR 0x43F90000
+#define UART2_BASE_ADDR 0x43F94000
+#define I2C2_BASE_ADDR 0x43F98000
+#define OWIRE_BASE_ADDR 0x43F9C000
+#define CSPI1_BASE_ADDR 0x43FA4000
+#define KPP_BASE_ADDR 0x43FA8000
+#define IOMUXC_BASE_ADDR 0x43FAC000
+#define AUDMUX_BASE_ADDR 0x43FB0000
+#define ECT_IP1_BASE_ADDR 0x43FB8000
+#define ECT_IP2_BASE_ADDR 0x43FBC000
+
+/*
+ * SPBA
+ */
+#define SPBA_BASE_ADDR 0x50000000
+#define CSPI3_BASE_ADDR 0x50040000
+#define UART4_BASE_ADDR 0x50008000
+#define UART3_BASE_ADDR 0x5000C000
+#define CSPI2_BASE_ADDR 0x50010000
+#define SSI2_BASE_ADDR 0x50014000
+#define ESAI_BASE_ADDR 0x50018000
+#define ATA_DMA_BASE_ADDR 0x50020000
+#define SIM1_BASE_ADDR 0x50024000
+#define SIM2_BASE_ADDR 0x50028000
+#define UART5_BASE_ADDR 0x5002C000
+#define TSC_BASE_ADDR 0x50030000
+#define SSI1_BASE_ADDR 0x50034000
+#define FEC_BASE_ADDR 0x50038000
+#define SOC_FEC_BASE FEC_BASE_ADDR
+#define SPBA_CTRL_BASE_ADDR 0x5003C000
+
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR 0x53F00000
+#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
+#define CCM_BASE_ADDR 0x53F80000
+#define GPT4_BASE_ADDR 0x53F84000
+#define GPT3_BASE_ADDR 0x53F88000
+#define GPT2_BASE_ADDR 0x53F8C000
+#define GPT1_BASE_ADDR 0x53F90000
+#define EPIT1_BASE_ADDR 0x53F94000
+#define EPIT2_BASE_ADDR 0x53F98000
+#define GPIO4_BASE_ADDR 0x53F9C000
+#define PWM2_BASE_ADDR 0x53FA0000
+#define GPIO3_BASE_ADDR 0x53FA4000
+#define PWM3_BASE_ADDR 0x53FA8000
+#define SCC_BASE_ADDR 0x53FAC000
+#define SCM_BASE_ADDR 0x53FAE000
+#define SMN_BASE_ADDR 0x53FAF000
+#define RNGD_BASE_ADDR 0x53FB0000
+#define MMC_SDHC1_BASE_ADDR 0x53FB4000
+#define MMC_SDHC2_BASE_ADDR 0x53FB8000
+#define ESDHC1_REG_BASE MMC_SDHC1_BASE_ADDR
+#define LCDC_BASE_ADDR 0x53FBC000
+#define SLCDC_BASE_ADDR 0x53FC0000
+#define PWM4_BASE_ADDR 0x53FC8000
+#define GPIO1_BASE_ADDR 0x53FCC000
+#define GPIO2_BASE_ADDR 0x53FD0000
+#define SDMA_BASE_ADDR 0x53FD4000
+#define WDOG_BASE_ADDR 0x53FDC000
+#define PWM1_BASE_ADDR 0x53FE0000
+#define RTIC_BASE_ADDR 0x53FEC000
+#define IIM_BASE_ADDR 0x53FF0000
+#define USB_BASE_ADDR 0x53FF4000
+#define CSI_BASE_ADDR 0x53FF8000
+#define DRYICE_BASE_ADDR 0x53FFC000
+
+/*
+ * ROMPATCH and AVIC
+ */
+#define ROMPATCH_BASE_ADDR 0x60000000
+#define ASIC_BASE_ADDR 0x68000000
+
+#define RAM_BASE_ADDR 0x78000000
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define EXT_MEM_CTRL_BASE 0xB8000000
+#define ESDCTL_BASE_ADDR 0xB8001000
+#define WEIM_BASE_ADDR 0xB8002000
+#define WEIM_CTRL_CS0 WEIM_BASE_ADDR
+#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10)
+#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20)
+#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30)
+#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40)
+#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50)
+#define M3IF_BASE 0xB8003000
+#define EMI_BASE 0xB8004000
+
+#define NFC_BASE 0xBB000000
+/*
+ * Memory regions and CS
+ */
+#define CSD0_BASE_ADDR 0x80000000
+#define CSD1_BASE_ADDR 0x90000000
+#define CS0_BASE_ADDR 0xA0000000
+#define CS1_BASE_ADDR 0xA8000000
+#define CS2_BASE_ADDR 0xB0000000
+#define CS3_BASE_ADDR 0xB2000000
+#define CS4_BASE_ADDR 0xB4000000
+#define CS5_BASE_ADDR 0xB6000000
+
+/*
+ * IRQ Controller Register Definitions.
+ */
+#define ASIC_NIMASK REG32_PTR(ASIC_BASE_ADDR + (0x04))
+#define ASIC_INTTYPEH REG32_PTR(ASIC_BASE_ADDR + (0x18))
+#define ASIC_INTTYPEL REG32_PTR(ASIC_BASE_ADDR + (0x1C))
+
+/* CCM */
+#define CLKCTL_MPCTL 0x00
+#define CLKCTL_UPCTL 0x04
+#define CLKCTL_CCTL 0x08
+#define CLKCTL_CGR0 0x0C
+#define CLKCTL_CGR1 0x10
+#define CLKCTL_CGR2 0x14
+#define CLKCTL_PCDR0 0x18
+#define CLKCTL_PCDR1 0x1C
+#define CLKCTL_PCDR2 0x20
+#define CLKCTL_PCDR3 0x24
+#define CLKCTL_RCSR 0x28
+#define CLKCTL_CRDR 0x2C
+#define CLKCTL_DCVR0 0x30
+#define CLKCTL_DCVR1 0x34
+#define CLKCTL_DCVR2 0x38
+#define CLKCTL_DCVR3 0x3C
+#define CLKCTL_LTR0 0x40
+#define CLKCTL_LTR1 0x44
+#define CLKCTL_LTR2 0x48
+#define CLKCTL_LTR3 0x4C
+#define CLKCTL_LTBR0 0x50
+#define CLKCTL_LTBR1 0x54
+#define CLKCTL_PCMR0 0x58
+#define CLKCTL_PCMR1 0x5C
+#define CLKCTL_PCMR2 0x60
+#define CLKCTL_MCR 0x64
+#define CLKCTL_LPIMR0 0x68
+#define CLKCTL_LPIMR1 0x6C
+
+#define CRM_CCTL_ARM_SRC (1 << 14)
+#define CRM_CCTL_AHB_OFFSET 28
+
+
+#define FREQ_24MHZ 24000000
+#define PLL_REF_CLK FREQ_24MHZ
+
+/*
+ * FIXME-DALE - Constants verified up to this point.
+ * Offsets and derived constants below should be confirmed.
+ */
+
+#define CLKMODE_AUTO 0
+#define CLKMODE_CONSUMER 1
+
+/* WEIM - CS0 */
+#define CSCRU 0x00
+#define CSCRL 0x04
+#define CSCRA 0x08
+
+#define CHIP_REV_1_0 0x0 /* PASS 1.0 */
+#define CHIP_REV_1_1 0x1 /* PASS 1.1 */
+#define CHIP_REV_2_0 0x2 /* PASS 2.0 */
+#define CHIP_LATEST CHIP_REV_1_1
+
+#define IIM_STAT_OFF 0x00
+#define IIM_STAT_BUSY (1 << 7)
+#define IIM_STAT_PRGD (1 << 1)
+#define IIM_STAT_SNSD (1 << 0)
+#define IIM_STATM_OFF 0x04
+#define IIM_ERR_OFF 0x08
+#define IIM_ERR_PRGE (1 << 7)
+#define IIM_ERR_WPE (1 << 6)
+#define IIM_ERR_OPE (1 << 5)
+#define IIM_ERR_RPE (1 << 4)
+#define IIM_ERR_WLRE (1 << 3)
+#define IIM_ERR_SNSE (1 << 2)
+#define IIM_ERR_PARITYE (1 << 1)
+#define IIM_EMASK_OFF 0x0C
+#define IIM_FCTL_OFF 0x10
+#define IIM_UA_OFF 0x14
+#define IIM_LA_OFF 0x18
+#define IIM_SDAT_OFF 0x1C
+#define IIM_PREV_OFF 0x20
+#define IIM_SREV_OFF 0x24
+#define IIM_PREG_P_OFF 0x28
+#define IIM_SCS0_OFF 0x2C
+#define IIM_SCS1_OFF 0x30
+#define IIM_SCS2_OFF 0x34
+#define IIM_SCS3_OFF 0x38
+
+#define EPIT_BASE_ADDR EPIT1_BASE_ADDR
+#define EPITCR 0x00
+#define EPITSR 0x04
+#define EPITLR 0x08
+#define EPITCMPR 0x0C
+#define EPITCNR 0x10
+
+#define GPT_BASE_ADDR GPT1_BASE_ADDR
+#define GPTCR 0x00
+#define GPTPR 0x04
+#define GPTSR 0x08
+#define GPTIR 0x0C
+#define GPTOCR1 0x10
+#define GPTOCR2 0x14
+#define GPTOCR3 0x18
+#define GPTICR1 0x1C
+#define GPTICR2 0x20
+#define GPTCNT 0x24
+
+/* ESDCTL */
+#define ESDCTL_ESDCTL0 0x00
+#define ESDCTL_ESDCFG0 0x04
+#define ESDCTL_ESDCTL1 0x08
+#define ESDCTL_ESDCFG1 0x0C
+#define ESDCTL_ESDMISC 0x10
+
+/* DRYICE */
+#define DRYICE_DTCMR 0x00
+#define DRYICE_DTCLR 0x04
+#define DRYICE_DCAMR 0x08
+#define DRYICE_DCALR 0x0C
+#define DRYICE_DCR 0x10
+#define DRYICE_DSR 0x14
+#define DRYICE_DIER 0x18
+#define DRYICE_DMCR 0x1C
+#define DRYICE_DKSR 0x20
+#define DRYICE_DKCR 0x24
+#define DRYICE_DTCR 0x28
+#define DRYICE_DACR 0x2C
+#define DRYICE_DGPR 0x3C
+#define DRYICE_DPKR0 0x40
+#define DRYICE_DPKR1 0x44
+#define DRYICE_DPKR2 0x48
+#define DRYICE_DPKR3 0x4C
+#define DRYICE_DPKR4 0x50
+#define DRYICE_DPKR5 0x54
+#define DRYICE_DPKR6 0x58
+#define DRYICE_DPKR7 0x5C
+#define DRYICE_DRKR0 0x60
+#define DRYICE_DRKR1 0x64
+#define DRYICE_DRKR2 0x68
+#define DRYICE_DRKR3 0x6C
+#define DRYICE_DRKR4 0x70
+#define DRYICE_DRKR5 0x74
+#define DRYICE_DRKR6 0x78
+#define DRYICE_DRKR7 0x7C
+
+/* GPIO */
+#define GPIO_DR 0x00
+#define GPIO_GDIR 0x04
+#define GPIO_PSR0 0x08
+#define GPIO_ICR1 0x0C
+#define GPIO_ICR2 0x10
+#define GPIO_IMR 0x14
+#define GPIO_ISR 0x18
+#define GPIO_EDGE_SEL 0x1C
+
+
+#if (PLL_REF_CLK != 24000000)
+#error Wrong PLL reference clock! The following macros will not work.
+#endif
+
+/* Assuming 24MHz input clock */
+/* PD MFD MFI MFN */
+#define MPCTL_PARAM_399 (((1-1) << 26) + ((16-1) << 16) + (8 << 10) + (5 << 0))
+#define MPCTL_PARAM_532 ((1 << 31) + ((1-1) << 26) + ((12-1) << 16) + (11 << 10) + (1 << 0))
+#define MPCTL_PARAM_665 (((1-1) << 26) + ((48-1) << 16) + (13 << 10) + (41 << 0))
+
+/* UPCTL PD MFD MFI MFN */
+#define UPCTL_PARAM_300 (((1-1) << 26) + ((4-1) << 16) + (6 << 10) + (1 << 0))
+
+#define NFC_V1_1
+
+#define NAND_REG_BASE (NFC_BASE + 0x1E00)
+#define NFC_BUFSIZE_REG_OFF (0 + 0x00)
+#define RAM_BUFFER_ADDRESS_REG_OFF (0 + 0x04)
+#define NAND_FLASH_ADD_REG_OFF (0 + 0x06)
+#define NAND_FLASH_CMD_REG_OFF (0 + 0x08)
+#define NFC_CONFIGURATION_REG_OFF (0 + 0x0A)
+#define ECC_STATUS_RESULT_REG_OFF (0 + 0x0C)
+#define ECC_RSLT_MAIN_AREA_REG_OFF (0 + 0x0E)
+#define ECC_RSLT_SPARE_AREA_REG_OFF (0 + 0x10)
+#define NF_WR_PROT_REG_OFF (0 + 0x12)
+#define NAND_FLASH_WR_PR_ST_REG_OFF (0 + 0x18)
+#define NAND_FLASH_CONFIG1_REG_OFF (0 + 0x1A)
+#define NAND_FLASH_CONFIG2_REG_OFF (0 + 0x1C)
+#define UNLOCK_START_BLK_ADD_REG_OFF (0 + 0x20)
+#define UNLOCK_END_BLK_ADD_REG_OFF (0 + 0x22)
+#define RAM_BUFFER_ADDRESS_RBA_3 0x3
+#define NFC_BUFSIZE_1KB 0x0
+#define NFC_BUFSIZE_2KB 0x1
+#define NFC_CONFIGURATION_UNLOCKED 0x2
+#define ECC_STATUS_RESULT_NO_ERR 0x0
+#define ECC_STATUS_RESULT_1BIT_ERR 0x1
+#define ECC_STATUS_RESULT_2BIT_ERR 0x2
+#define NF_WR_PROT_UNLOCK 0x4
+#define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7)
+#define NAND_FLASH_CONFIG1_RST (1 << 6)
+#define NAND_FLASH_CONFIG1_BIG (1 << 5)
+#define NAND_FLASH_CONFIG1_INT_MSK (1 << 4)
+#define NAND_FLASH_CONFIG1_ECC_EN (1 << 3)
+#define NAND_FLASH_CONFIG1_SP_EN (1 << 2)
+#define NAND_FLASH_CONFIG2_INT_DONE (1 << 15)
+#define NAND_FLASH_CONFIG2_FDO_PAGE (0 << 3)
+#define NAND_FLASH_CONFIG2_FDO_ID (2 << 3)
+#define NAND_FLASH_CONFIG2_FDO_STATUS (4 << 3)
+#define NAND_FLASH_CONFIG2_FDI_EN (1 << 2)
+#define NAND_FLASH_CONFIG2_FADD_EN (1 << 1)
+#define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0)
+#define FDO_PAGE_SPARE_VAL 0x8
+#define NAND_BUF_NUM 8
+
+#define MXC_NAND_BASE_DUMMY 0x00000000
+#define MXC_MMC_BASE_DUMMY 0x00000000
+#define NOR_FLASH_BOOT 0
+#define NAND_FLASH_BOOT 0x10000000
+#define SDRAM_NON_FLASH_BOOT 0x20000000
+#define MMC_FLASH_BOOT 0x40000000
+#define MXCBOOT_FLAG_REG (CSI_BASE_ADDR + 0x28) // use CSIDMASA-FB1
+#define MXCFIS_NOTHING 0x00000000
+#define MXCFIS_NAND 0x10000000
+#define MXCFIS_NOR 0x20000000
+#define MXCFIS_MMC 0x40000000
+#define MXCFIS_FLAG_REG (CSI_BASE_ADDR + 0x2C) // use CSIDMASA-FB2
+
+#define IS_BOOTING_FROM_NAND() (readl(MXCBOOT_FLAG_REG) == NAND_FLASH_BOOT)
+#define IS_BOOTING_FROM_NOR() (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
+#define IS_BOOTING_FROM_SDRAM() (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
+#define IS_BOOTING_FROM_MMC() (readl(MXCBOOT_FLAG_REG) == MMC_FLASH_BOOT)
+
+#ifndef MXCFLASH_SELECT_NAND
+#define IS_FIS_FROM_NAND() 0
+#else
+#define IS_FIS_FROM_NAND() (readl(MXCFIS_FLAG_REG) == MXCFIS_NAND)
+#endif
+
+#ifndef MXCFLASH_SELECT_MMC
+#define IS_FIS_FROM_MMC() 0
+#else
+#define IS_FIS_FROM_MMC() (readl(MXCFIS_FLAG_REG) == MXCFIS_MMC)
+#endif
+
+#ifndef MXCFLASH_SELECT_NOR
+#define IS_FIS_FROM_NOR() 0
+#else
+#define IS_FIS_FROM_NOR() (readl(MXCFIS_FLAG_REG) == MXCFIS_NOR)
+#endif
+
+#define MXC_ASSERT_NOR_BOOT() writel(MXCFIS_NOR, MXCFIS_FLAG_REG)
+#define MXC_ASSERT_NAND_BOOT() writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
+#define MXC_ASSERT_MMC_BOOT() writel(MXCFIS_MMC, MXCFIS_FLAG_REG)
+
+/*
+ * This macro is used to get certain bit field from a number
+ */
+#define MXC_GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1))
+
+/*
+ * This macro is used to set certain bit field inside a number
+ */
+#define MXC_SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
+
+#define UART_WIDTH_32 /* internal UART is 32bit access only */
+
+#if !defined(__ASSEMBLER__)
+void cyg_hal_plf_serial_init(void);
+void cyg_hal_plf_serial_stop(void);
+void hal_delay_us(unsigned int usecs);
+#define HAL_DELAY_US(n) hal_delay_us(n)
+
+enum plls {
+ MCU_PLL = CCM_BASE_ADDR + CLKCTL_MPCTL,
+ USB_PLL = CCM_BASE_ADDR + CLKCTL_UPCTL,
+};
+
+enum main_clocks {
+ CPU_CLK,
+ AHB_CLK,
+ IPG_CLK,
+ IPG_PER_CLK, // not there on MX25 but simulated for compatibility
+};
+
+enum peri_clocks {
+ PER_UART_CLK,
+ SPI1_CLK = CSPI1_BASE_ADDR,
+ SPI2_CLK = CSPI2_BASE_ADDR,
+};
+
+unsigned int pll_clock(enum plls pll);
+
+unsigned int get_main_clock(enum main_clocks clk);
+
+unsigned int get_peri_clock(enum peri_clocks clk);
+
+typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
+
+#endif //#if !defined(__ASSEMBLER__)
+
+#define HAL_MMU_OFF() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "1: " \
+ "mrc p15, 0, r15, c7, c14, 3;" /*test clean and inval*/ \
+ "bne 1b;" \
+ "mov r0, #0;" \
+ "mcr p15,0,r0,c7,c10,4;" /*drain write buffer*/ \
+ "mcr p15,0,r0,c7,c5,0;" /* invalidate I cache */ \
+ "mrc p15,0,r0,c1,c0,0;" /* read c1 */ \
+ "bic r0,r0,#0x7;" /* disable DCache and MMU */ \
+ "bic r0,r0,#0x1000;" /* disable ICache */ \
+ "mcr p15,0,r0,c1,c0,0;" /* */ \
+ "nop;" /* flush i+d-TLBs */ \
+ "nop;" /* flush i+d-TLBs */ \
+ "nop;" /* flush i+d-TLBs */ \
+ : \
+ : \
+ : "r0","memory" /* clobber list */); \
+CYG_MACRO_END
+
+#endif /* __HAL_SOC_H__ */
--- /dev/null
+#ifndef CYGONCE_HAL_VAR_INTS_H
+#define CYGONCE_HAL_VAR_INTS_H
+//==========================================================================
+//
+// hal_var_ints.h
+//
+// HAL Interrupt and clock support
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+
+#include <cyg/hal/hal_soc.h> // registers
+
+#define CYGNUM_HAL_INTERRUPT_GPIO0 0
+#define CYGNUM_HAL_INTERRUPT_GPIO1 1
+#define CYGNUM_HAL_INTERRUPT_GPIO2 2
+#define CYGNUM_HAL_INTERRUPT_GPIO3 3
+#define CYGNUM_HAL_INTERRUPT_GPIO4 4
+#define CYGNUM_HAL_INTERRUPT_GPIO5 5
+#define CYGNUM_HAL_INTERRUPT_GPIO6 6
+#define CYGNUM_HAL_INTERRUPT_GPIO7 7
+#define CYGNUM_HAL_INTERRUPT_GPIO8 8
+#define CYGNUM_HAL_INTERRUPT_GPIO9 9
+#define CYGNUM_HAL_INTERRUPT_GPIO10 10
+#define CYGNUM_HAL_INTERRUPT_GPIO 11 // Don't use directly!
+#define CYGNUM_HAL_INTERRUPT_LCD 12
+#define CYGNUM_HAL_INTERRUPT_UDC 13
+#define CYGNUM_HAL_INTERRUPT_UART1 15
+#define CYGNUM_HAL_INTERRUPT_UART2 16
+#define CYGNUM_HAL_INTERRUPT_UART3 17
+#define CYGNUM_HAL_INTERRUPT_UART4 17
+#define CYGNUM_HAL_INTERRUPT_MCP 18
+#define CYGNUM_HAL_INTERRUPT_SSP 19
+#define CYGNUM_HAL_INTERRUPT_TIMER0 26
+#define CYGNUM_HAL_INTERRUPT_TIMER1 27
+#define CYGNUM_HAL_INTERRUPT_TIMER2 28
+#define CYGNUM_HAL_INTERRUPT_TIMER3 29
+#define CYGNUM_HAL_INTERRUPT_HZ 30
+#define CYGNUM_HAL_INTERRUPT_ALARM 31
+
+// GPIO bits 31..11 can generate interrupts as well, but they all
+// end up clumped into interrupt signal #11. Using the symbols
+// below allow for detection of these separately.
+
+#define CYGNUM_HAL_INTERRUPT_GPIO11 (32+11)
+#define CYGNUM_HAL_INTERRUPT_GPIO12 (32+12)
+#define CYGNUM_HAL_INTERRUPT_GPIO13 (32+13)
+#define CYGNUM_HAL_INTERRUPT_GPIO14 (32+14)
+#define CYGNUM_HAL_INTERRUPT_GPIO15 (32+15)
+#define CYGNUM_HAL_INTERRUPT_GPIO16 (32+16)
+#define CYGNUM_HAL_INTERRUPT_GPIO17 (32+17)
+#define CYGNUM_HAL_INTERRUPT_GPIO18 (32+18)
+#define CYGNUM_HAL_INTERRUPT_GPIO19 (32+19)
+#define CYGNUM_HAL_INTERRUPT_GPIO20 (32+20)
+#define CYGNUM_HAL_INTERRUPT_GPIO21 (32+21)
+#define CYGNUM_HAL_INTERRUPT_GPIO22 (32+22)
+#define CYGNUM_HAL_INTERRUPT_GPIO23 (32+23)
+#define CYGNUM_HAL_INTERRUPT_GPIO24 (32+24)
+#define CYGNUM_HAL_INTERRUPT_GPIO25 (32+25)
+#define CYGNUM_HAL_INTERRUPT_GPIO26 (32+26)
+#define CYGNUM_HAL_INTERRUPT_GPIO27 (32+27)
+
+#define CYGNUM_HAL_INTERRUPT_NONE -1
+
+#define CYGNUM_HAL_ISR_MIN 0
+#define CYGNUM_HAL_ISR_MAX (27+32)
+
+#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1)
+
+// The vector used by the Real time clock
+#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0
+
+// The vector used by the Ethernet
+#define CYGNUM_HAL_INTERRUPT_ETH CYGNUM_HAL_INTERRUPT_GPIO0
+
+// method for reading clock interrupt latency
+#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
+externC void hal_clock_latency(cyg_uint32 *);
+# define HAL_CLOCK_LATENCY( _pvalue_ ) \
+ hal_clock_latency( (cyg_uint32 *)(_pvalue_) )
+#endif
+
+//----------------------------------------------------------------------------
+// Reset.
+#define HAL_PLATFORM_RESET() \
+ CYG_MACRO_START \
+ *(volatile unsigned short *)WDOG_BASE_ADDR |= 0x4; \
+ /* hang here forever if reset fails */ \
+ while (1){} \
+ CYG_MACRO_END
+
+// Fallback (never really used)
+#define HAL_PLATFORM_RESET_ENTRY 0x00000000
+
+#endif // CYGONCE_HAL_VAR_INTS_H
--- /dev/null
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+// plf_stub.h
+//
+// Platform header for GDB stub support.
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM
+
+#include <cyg/hal/hal_soc.h> // registers
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_intr.h> // Interrupt macros
+#include <cyg/hal/arm_stub.h> // architecture stub support
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init()
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
--- /dev/null
+#ifndef CYGONCE_VAR_IO_H
+#define CYGONCE_VAR_IO_H
+
+//=============================================================================
+//
+// var_io.h
+//
+// Variant specific IO support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/hal/plf_io.h> // Platform specifics
+
+//-----------------------------------------------------------------------------
+
+// Memory mapping details
+#ifndef CYGARC_PHYSICAL_ADDRESS
+#ifdef SRAM_BASE_ADDR
+#if (SDRAM_BASE_ADDR==SRAM_BASE_ADDR)
+#define CYGARC_PHYSICAL_ADDRESS(x) \
+ (((unsigned long)(x) & 0x00FFFFFF) + SRAM_BASE_ADDR)
+/*#elif (SDRAM_BASE_ADDR == RAM_BANK0_BASE)
+ #define CYGARC_PHYSICAL_ADDRESS(x) \
+ (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK0_BASE)*/
+#else
+#define CYGARC_PHYSICAL_ADDRESS(x) \
+ ((((unsigned long)x & 0x1FFFFFFF) > 0x0FFFFFFF)? \
+ (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK1_BASE): \
+ (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK0_BASE))
+#endif
+#else //SRAM_BASE_ADDR
+#if (SDRAM_BASE_ADDR == RAM_BANK0_BASE)
+#define CYGARC_PHYSICAL_ADDRESS(x) \
+ ((((unsigned long)x & 0x1FFFFFFF) > 0x0FFFFFFF)? \
+ (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK1_BASE): \
+ (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK0_BASE))
+#else
+#define CYGARC_PHYSICAL_ADDRESS(x) \
+ ((((unsigned long)x & 0x1FFFFFFF) > 0x0FFFFFFF)? \
+ (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK0_BASE): \
+ (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK1_BASE))
+#endif
+#endif //SRAM_BASE_ADDr
+#endif
+
+//-----------------------------------------------------------------------------
+// end of var_io.h
+#endif // CYGONCE_VAR_IO_H
--- /dev/null
+//==========================================================================
+//
+// cmds.c
+//
+// SoC [platform] specific RedBoot commands
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+#include <redboot.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/plf_mmap.h>
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/hal_cache.h>
+
+#define IIM_FUSE_DEBUG
+
+typedef unsigned long long u64;
+typedef unsigned int u32;
+typedef unsigned short u16;
+typedef unsigned char u8;
+
+u32 pll_clock(enum plls pll);
+u32 get_main_clock(enum main_clocks clk);
+u32 get_peri_clock(enum peri_clocks clk);
+
+static void clock_setup(int argc, char *argv[]);
+
+RedBoot_cmd("clock",
+ "Setup/Display clock\nSyntax:",
+ "[<ARM core clock in MHz> [:<ARM-AHB clock divider>]\n\
+If a selection is zero or no divider is specified, the optimal divider values\n\
+will be chosen. Examples:\n\
+ [clock] -> Show various clocks\n\
+ [clock 399] -> Core=399 AHB=133 IPG=66.5(AHB/2)\n\
+ [clock 532:4] -> Core=532 AHB=133(Core/4) IPG=66.5(AHB/2)\n\
+ [clock 399:4] -> Core=399 AHB=99.75(Core/4) IPG=49.875(AHB/2)\n\
+ [clock 199:3] -> Core=199.5 AHB=66.5(Core/3) IPG=33.25(AHB/2)\n\
+ [clock 133:2] -> Core=133 AHB=66.5(Core/2) IPG=33.25(AHB/2)\n\
+ Core range: 532-133, AHB range: 133-66.5, IPG is always AHB/2\n",
+ clock_setup
+ );
+
+void clock_spi_enable(unsigned int spi_clk)
+{
+ diag_printf("%s: stubbed\n", __func__);
+}
+
+static void clock_setup(int argc,char *argv[])
+{
+ u32 i, data[2], temp, core_clk, ahb_div, cctl, arm_src, arm_div;
+
+ if (argc == 1)
+ goto print_clock;
+
+ for (i = 0; i < 2; i++) {
+ if (!parse_num(*(&argv[1]), (unsigned long *)&temp, &argv[1], ":")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ data[i] = temp;
+ }
+
+ core_clk = data[0];
+ ahb_div = data[1] - 1;
+
+ if (core_clk / (ahb_div + 1) > 133 ||
+ core_clk / (ahb_div + 1) < 66) {
+ diag_printf("Illegal AHB divider value specified\n");
+ return;
+ }
+
+ switch (core_clk) {
+ case 532:
+ arm_src = 0;
+ arm_div = 1 - 1;
+ break;
+ case 399:
+ arm_src = 1;
+ arm_div = 1 - 1;
+ break;
+ case 199:
+ case 200:
+ arm_src = 1;
+ arm_div = 2 - 1;
+ break;
+ case 133:
+ arm_src = 1;
+ arm_div = 3 - 1;
+ break;
+ default:
+ diag_printf("Illegal core clock value specified\n");
+ return;
+ }
+
+ cctl = readl(CCM_BASE_ADDR + CLKCTL_CCTL);
+ cctl &= ~0xF0004000;
+ cctl |= arm_div << 30;
+ cctl |= ahb_div << 28;
+ cctl |= arm_src << 14;
+ writel(cctl, CCM_BASE_ADDR + CLKCTL_CCTL);
+
+ diag_printf("\n<<<New clock settings>>>\n");
+
+ // Now printing clocks
+print_clock:
+ diag_printf("\nMPLL\t\tUPLL\n");
+ diag_printf("=========================\n");
+ diag_printf("%-16d%-16d\n\n", pll_clock(MCU_PLL), pll_clock(USB_PLL));
+ diag_printf("CPU\t\tAHB\t\tIPG\n");
+ diag_printf("========================================\n");
+ diag_printf("%-16d%-16d%-16d\n\n",
+ get_main_clock(CPU_CLK),
+ get_main_clock(AHB_CLK),
+ get_main_clock(IPG_CLK));
+
+ diag_printf("UART\n");
+ diag_printf("========\n");
+ diag_printf("%-16d\n\n",
+ get_peri_clock(PER_UART_CLK));
+
+ diag_printf("SPI\n");
+ diag_printf("========\n");
+ diag_printf("%-16d\n\n",
+ get_peri_clock(SPI1_CLK));
+}
+
+/*!
+ * This function returns the PLL output value in Hz based on pll.
+ */
+u32 pll_clock(enum plls pll)
+{
+ u64 mfi, mfn, mfd, pdf, ref_clk, pll_out;
+ u64 reg = readl(pll);
+
+ pdf = (reg >> 26) & 0xF;
+ mfd = (reg >> 16) & 0x3FF;
+ mfi = (reg >> 10) & 0xF;
+ mfi = (mfi <= 5) ? 5: mfi;
+ mfn = reg & 0x3FF;
+
+ ref_clk = PLL_REF_CLK;
+
+ pll_out = (2 * ref_clk * mfi + ((2 * ref_clk * mfn) / (mfd + 1))) /
+ (pdf + 1);
+
+ return (u32)pll_out;
+}
+
+/*!
+ * This function returns the main clock value in Hz.
+ */
+u32 get_main_clock(enum main_clocks clk)
+{
+ u32 cctl = readl(CCM_BASE_ADDR + CLKCTL_CCTL);
+ u32 ahb_div;
+ u32 ret_val = 0;
+
+ switch (clk) {
+ case CPU_CLK:
+ ret_val = pll_clock(MCU_PLL);
+ if (cctl & CRM_CCTL_ARM_SRC) {
+ ret_val *= 3;
+ ret_val /= 4;
+ }
+ break;
+ case AHB_CLK:
+ ahb_div = ((cctl >> CRM_CCTL_AHB_OFFSET) & 3) + 1;
+ ret_val = get_main_clock(CPU_CLK) / ahb_div;
+ break;
+ case IPG_CLK:
+ case IPG_PER_CLK:
+ ret_val = get_main_clock(AHB_CLK) / 2;
+ break;
+ default:
+ diag_printf("Unknown clock: %d\n", clk);
+ break;
+ }
+
+ return ret_val;
+}
+
+/*!
+ * This function returns the peripheral clock value in Hz.
+ */
+u32 get_peri_clock(enum peri_clocks clk)
+{
+ u32 ret_val = 0;
+ u32 pcdr, div;
+
+ switch (clk) {
+ case PER_UART_CLK:
+ pcdr = readl(CCM_BASE_ADDR + CLKCTL_PCDR3);
+ div = (pcdr >> 24) + 1;
+ ret_val = get_main_clock(AHB_CLK) / div;
+ break;
+ case SPI1_CLK:
+ case SPI2_CLK:
+ ret_val = get_main_clock(IPG_CLK);
+ break;
+ default:
+ diag_printf("%s(): This clock: %d not supported yet \n",
+ __FUNCTION__, clk);
+ break;
+ }
+ return ret_val;
+}
+
+
+#define IIM_ERR_SHIFT 8
+#define POLL_FUSE_PRGD (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT))
+#define POLL_FUSE_SNSD (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT))
+
+static void fuse_op_start(void)
+{
+ /* Do not generate interrupt */
+ writel(0, IIM_BASE_ADDR + IIM_STATM_OFF);
+ // clear the status bits and error bits
+ writel(0x3, IIM_BASE_ADDR + IIM_STAT_OFF);
+ writel(0xFE, IIM_BASE_ADDR + IIM_ERR_OFF);
+}
+
+/*
+ * The action should be either:
+ * POLL_FUSE_PRGD
+ * or:
+ * POLL_FUSE_SNSD
+ */
+static int poll_fuse_op_done(int action)
+{
+
+ u32 status, error;
+
+ if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) {
+ diag_printf("%s(%d) invalid operation\n", __FUNCTION__, action);
+ return -1;
+ }
+
+ /* Poll busy bit till it is NOT set */
+ while ((readl(IIM_BASE_ADDR + IIM_STAT_OFF) & IIM_STAT_BUSY) != 0 ) {
+ }
+
+ /* Test for successful write */
+ status = readl(IIM_BASE_ADDR + IIM_STAT_OFF);
+ error = readl(IIM_BASE_ADDR + IIM_ERR_OFF);
+
+ if ((status & action) != 0 && (error & (action >> IIM_ERR_SHIFT)) == 0) {
+ if (error) {
+ diag_printf("Even though the operation seems successful...\n");
+ diag_printf("There are some error(s) at addr=0x%x: 0x%x\n",
+ (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+ }
+ return 0;
+ }
+ diag_printf("%s(%d) failed\n", __FUNCTION__, action);
+ diag_printf("status address=0x%x, value=0x%x\n",
+ (IIM_BASE_ADDR + IIM_STAT_OFF), status);
+ diag_printf("There are some error(s) at addr=0x%x: 0x%x\n",
+ (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+ return -1;
+}
+
+static void sense_fuse(int bank, int row, int bit)
+{
+ int addr, addr_l, addr_h, reg_addr;
+
+ fuse_op_start();
+
+ addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+ /* Set IIM Program Upper Address */
+ addr_h = (addr >> 8) & 0x000000FF;
+ /* Set IIM Program Lower Address */
+ addr_l = (addr & 0x000000FF);
+
+#ifdef IIM_FUSE_DEBUG
+ diag_printf("%s: addr_h=0x%x, addr_l=0x%x\n",
+ __FUNCTION__, addr_h, addr_l);
+#endif
+ writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
+ writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
+ /* Start sensing */
+ writel(0x8, IIM_BASE_ADDR + IIM_FCTL_OFF);
+ if (poll_fuse_op_done(POLL_FUSE_SNSD) != 0) {
+ diag_printf("%s(bank: %d, row: %d, bit: %d failed\n",
+ __FUNCTION__, bank, row, bit);
+ }
+ reg_addr = IIM_BASE_ADDR + IIM_SDAT_OFF;
+ diag_printf("fuses at (bank:%d, row:%d) = 0x%x\n", bank, row, readl(reg_addr));
+}
+
+void do_fuse_read(int argc, char *argv[])
+{
+ int bank, row;
+
+ if (argc == 1) {
+ diag_printf("Useage: fuse_read <bank> <row>\n");
+ return;
+ } else if (argc == 3) {
+ if (!parse_num(*(&argv[1]), (unsigned long *)&bank, &argv[1], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(*(&argv[2]), (unsigned long *)&row, &argv[2], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+
+ diag_printf("Read fuse at bank:%d row:%d\n", bank, row);
+ sense_fuse(bank, row, 0);
+
+ } else {
+ diag_printf("Passing in wrong arguments: %d\n", argc);
+ diag_printf("Useage: fuse_read <bank> <row>\n");
+ }
+}
+
+/* Blow fuses based on the bank, row and bit positions (all 0-based)
+*/
+static int fuse_blow(int bank,int row,int bit)
+{
+ int addr, addr_l, addr_h, ret = -1;
+
+ fuse_op_start();
+
+ /* Disable IIM Program Protect */
+ writel(0xAA, IIM_BASE_ADDR + IIM_PREG_P_OFF);
+
+ addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+ /* Set IIM Program Upper Address */
+ addr_h = (addr >> 8) & 0x000000FF;
+ /* Set IIM Program Lower Address */
+ addr_l = (addr & 0x000000FF);
+
+#ifdef IIM_FUSE_DEBUG
+ diag_printf("blowing addr_h=0x%x, addr_l=0x%x\n", addr_h, addr_l);
+#endif
+
+ writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
+ writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
+ /* Start Programming */
+ writel(0x71, IIM_BASE_ADDR + IIM_FCTL_OFF);
+ if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) {
+ ret = 0;
+ }
+
+ /* Enable IIM Program Protect */
+ writel(0x0, IIM_BASE_ADDR + IIM_PREG_P_OFF);
+ return ret;
+}
+
+/*
+ * This command is added for burning IIM fuses
+ */
+RedBoot_cmd("fuse_read",
+ "read some fuses",
+ "<bank> <row>",
+ do_fuse_read
+ );
+
+RedBoot_cmd("fuse_blow",
+ "blow some fuses",
+ "<bank> <row> <value>",
+ do_fuse_blow
+ );
+
+#define INIT_STRING "12345678"
+static char ready_to_blow[] = INIT_STRING;
+
+void quick_itoa(u32 num, char *a)
+{
+ int i, j, k;
+ for (i = 0; i <= 7; i++) {
+ j = (num >> (4 * i)) & 0xF;
+ k = (j < 10) ? '0' : ('a' - 0xa);
+ a[i] = j + k;
+ }
+}
+
+void do_fuse_blow(int argc, char *argv[])
+{
+ int bank, row, value, i;
+
+ if (argc == 1) {
+ diag_printf("It is too dangeous for you to use this command.\n");
+ return;
+ } else if (argc == 2) {
+ if (strcasecmp(argv[1], "nandboot") == 0) {
+ quick_itoa(readl(EPIT_BASE_ADDR + EPITCNR), ready_to_blow);
+ diag_printf("%s\n", ready_to_blow);
+ }
+ return;
+ } else if (argc == 3) {
+ if (strcasecmp(argv[1], "nandboot") == 0 &&
+ strcasecmp(argv[2], ready_to_blow) == 0) {
+#if defined(CYGPKG_HAL_ARM_MXC91131) || defined(CYGPKG_HAL_ARM_MX21) || defined(CYGPKG_HAL_ARM_MX27) || defined(CYGPKG_HAL_ARM_MX31) ||defined(CYGPKG_HAL_ARM_MX35) || defined(CYGPKG_HAL_ARM_MX25)
+ diag_printf("No need to blow any fuses for NAND boot on this platform\n\n");
+#else
+#error "Are you sure you want this?"
+ diag_printf("Ready to burn NAND boot fuses\n");
+ if (fuse_blow(0, 16, 1) != 0 || fuse_blow(0, 16, 7) != 0) {
+ diag_printf("NAND BOOT fuse blown failed miserably ...\n");
+ } else {
+ diag_printf("NAND BOOT fuse blown successfully ...\n");
+ }
+ } else {
+ diag_printf("Not ready: %s, %s\n", argv[1], argv[2]);
+#endif
+ }
+ } else if (argc == 4) {
+ if (!parse_num(*(&argv[1]), (unsigned long *)&bank, &argv[1], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(*(&argv[2]), (unsigned long *)&row, &argv[2], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(*(&argv[3]), (unsigned long *)&value, &argv[3], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+
+ diag_printf("Blowing fuse at bank:%d row:%d value:%d\n",
+ bank, row, value);
+ for (i = 0; i < 8; i++) {
+ if (((value >> i) & 0x1) == 0) {
+ continue;
+ }
+ if (fuse_blow(bank, row, i) != 0) {
+ diag_printf("fuse_blow(bank: %d, row: %d, bit: %d failed\n",
+ bank, row, i);
+ } else {
+ diag_printf("fuse_blow(bank: %d, row: %d, bit: %d successful\n",
+ bank, row, i);
+ }
+ }
+ sense_fuse(bank, row, 0);
+
+ } else {
+ diag_printf("Passing in wrong arguments: %d\n", argc);
+ }
+ /* Reset to default string */
+ strcpy(ready_to_blow, INIT_STRING);;
+}
+
+/* precondition: m>0 and n>0. Let g=gcd(m,n). */
+int gcd(int m, int n)
+{
+ int t;
+ while(m > 0) {
+ if(n > m) {t = m; m = n; n = t;} /* swap */
+ m -= n;
+ }
+ return n;
+}
+
--- /dev/null
+/*=============================================================================
+//
+// hal_diag.c
+//
+// HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_arch.h> // basic machine info
+#include <cyg/hal/hal_intr.h> // interrupt macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_if.h> // Calling interface definitions
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/drv_api.h> // cyg_drv_interrupt_acknowledge
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+
+/*
+ * UART Control Register 0 Bit Fields.
+ */
+#define EUartUCR1_ADEN (1 << 15) // Auto dectect interrupt
+#define EUartUCR1_ADBR (1 << 14) // Auto detect baud rate
+#define EUartUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable
+#define EUartUCR1_IDEN (1 << 12) // Idle condition interrupt
+#define EUartUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable
+#define EUartUCR1_RDMAEN (1 << 8) // Recv ready DMA enable
+#define EUartUCR1_IREN (1 << 7) // Infrared interface enable
+#define EUartUCR1_TXMPTYEN (1 << 6) // Transimitter empty interrupt enable
+#define EUartUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable
+#define EUartUCR1_SNDBRK (1 << 4) // Send break
+#define EUartUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable
+#define EUartUCR1_DOZE (1 << 1) // Doze
+#define EUartUCR1_UARTEN (1 << 0) // UART enabled
+#define EUartUCR2_ESCI (1 << 15) // Escape seq interrupt enable
+#define EUartUCR2_IRTS (1 << 14) // Ignore RTS pin
+#define EUartUCR2_CTSC (1 << 13) // CTS pin control
+#define EUartUCR2_CTS (1 << 12) // Clear to send
+#define EUartUCR2_ESCEN (1 << 11) // Escape enable
+#define EUartUCR2_PREN (1 << 8) // Parity enable
+#define EUartUCR2_PROE (1 << 7) // Parity odd/even
+#define EUartUCR2_STPB (1 << 6) // Stop
+#define EUartUCR2_WS (1 << 5) // Word size
+#define EUartUCR2_RTSEN (1 << 4) // Request to send interrupt enable
+#define EUartUCR2_ATEN (1 << 3) // Aging timer enable
+#define EUartUCR2_TXEN (1 << 2) // Transmitter enabled
+#define EUartUCR2_RXEN (1 << 1) // Receiver enabled
+#define EUartUCR2_SRST_ (1 << 0) // SW reset
+#define EUartUCR3_PARERREN (1 << 12) // Parity enable
+#define EUartUCR3_FRAERREN (1 << 11) // Frame error interrupt enable
+#define EUartUCR3_ADNIMP (1 << 7) // Autobaud detection not improved
+#define EUartUCR3_RXDSEN (1 << 6) // Receive status interrupt enable
+#define EUartUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable
+#define EUartUCR3_AWAKEN (1 << 4) // Async wake interrupt enable
+#define EUartUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected
+#define EUartUCR3_INVT (1 << 1) // Inverted Infrared transmission
+#define EUartUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable
+#define EUartUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars)
+#define EUartUCR4_INVR (1 << 9) // Inverted infrared reception
+#define EUartUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable
+#define EUartUCR4_WKEN (1 << 7) // Wake interrupt enable
+#define EUartUCR4_IRSC (1 << 5) // IR special case
+#define EUartUCR4_LPBYP (1 << 4) // Low power bypass
+#define EUartUCR4_TCEN (1 << 3) // Transmit complete interrupt enable
+#define EUartUCR4_BKEN (1 << 2) // Break condition interrupt enable
+#define EUartUCR4_OREN (1 << 1) // Receiver overrun interrupt enable
+#define EUartUCR4_DREN (1 << 0) // Recv data ready interrupt enable
+#define EUartUFCR_RXTL_SHF 0 // Receiver trigger level shift
+#define EUartUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div 1)
+#define EUartUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div 2)
+#define EUartUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3)
+#define EUartUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4)
+#define EUartUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5)
+#define EUartUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6)
+#define EUartUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7)
+#define EUartUFCR_TXTL_SHF 10 // Transmitter trigger level shift
+#define EUartUSR1_PARITYERR (1 << 15) // Parity error interrupt flag
+#define EUartUSR1_RTSS (1 << 14) // RTS pin status
+#define EUartUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag
+#define EUartUSR1_RTSD (1 << 12) // RTS delta
+#define EUartUSR1_ESCF (1 << 11) // Escape seq interrupt flag
+#define EUartUSR1_FRAMERR (1 << 10) // Frame error interrupt flag
+#define EUartUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag
+#define EUartUSR1_AGTIM (1 << 8) // Aging timeout interrupt status
+#define EUartUSR1_RXDS (1 << 6) // Receiver idle interrupt flag
+#define EUartUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag
+#define EUartUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag
+#define EUartUSR2_ADET (1 << 15) // Auto baud rate detect complete
+#define EUartUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty
+#define EUartUSR2_IDLE (1 << 12) // Idle condition
+#define EUartUSR2_ACST (1 << 11) // Autobaud counter stopped
+#define EUartUSR2_IRINT (1 << 8) // Serial infrared interrupt flag
+#define EUartUSR2_WAKE (1 << 7) // Wake
+#define EUartUSR2_RTSF (1 << 4) // RTS edge interrupt flag
+#define EUartUSR2_TXDC (1 << 3) // Transmitter complete
+#define EUartUSR2_BRCD (1 << 2) // Break condition
+#define EUartUSR2_ORE (1 << 1) // Overrun error
+#define EUartUSR2_RDR (1 << 0) // Recv data ready
+#define EUartUTS_FRCPERR (1 << 13) // Force parity error
+#define EUartUTS_LOOP (1 << 12) // Loop tx and rx
+#define EUartUTS_TXEMPTY (1 << 6) // TxFIFO empty
+#define EUartUTS_RXEMPTY (1 << 5) // RxFIFO empty
+#define EUartUTS_TXFULL (1 << 4) // TxFIFO full
+#define EUartUTS_RXFULL (1 << 3) // RxFIFO full
+#define EUartUTS_SOFTRST (1 << 0) // Software reset
+
+#define EUartUFCR_RFDIV EUartUFCR_RFDIV_1
+
+#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_1)
+#define MXC_UART_REFFREQ (get_peri_clock(PER_UART_CLK) / 1)
+#endif
+
+#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_2)
+#define MXC_UART_REFFREQ (get_peri_clock(PER_UART_CLK) / 2)
+#endif
+
+#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_4)
+#define MXC_UART_REFFREQ (get_peri_clock(PER_UART_CLK) / 4)
+#endif
+
+#if 0
+void
+cyg_hal_plf_comms_init(void)
+{
+ static int initialized = 0;
+
+ if (initialized)
+ return;
+
+ initialized = 1;
+
+ cyg_hal_plf_serial_init();
+}
+#endif
+
+//=============================================================================
+// MXC Serial Port (UARTx) for Debug
+//=============================================================================
+#ifdef UART_WIDTH_32
+struct mxc_serial {
+ volatile cyg_uint32 urxd[16];
+ volatile cyg_uint32 utxd[16];
+ volatile cyg_uint32 ucr1;
+ volatile cyg_uint32 ucr2;
+ volatile cyg_uint32 ucr3;
+ volatile cyg_uint32 ucr4;
+ volatile cyg_uint32 ufcr;
+ volatile cyg_uint32 usr1;
+ volatile cyg_uint32 usr2;
+ volatile cyg_uint32 uesc;
+ volatile cyg_uint32 utim;
+ volatile cyg_uint32 ubir;
+ volatile cyg_uint32 ubmr;
+ volatile cyg_uint32 ubrc;
+ volatile cyg_uint32 onems;
+ volatile cyg_uint32 uts;
+};
+#else
+struct mxc_serial {
+ volatile cyg_uint16 urxd[1];
+ volatile cyg_uint16 resv0[31];
+
+ volatile cyg_uint16 utxd[1];
+ volatile cyg_uint16 resv1[31];
+ volatile cyg_uint16 ucr1;
+ volatile cyg_uint16 resv2;
+ volatile cyg_uint16 ucr2;
+ volatile cyg_uint16 resv3;
+ volatile cyg_uint16 ucr3;
+ volatile cyg_uint16 resv4;
+ volatile cyg_uint16 ucr4;
+ volatile cyg_uint16 resv5;
+ volatile cyg_uint16 ufcr;
+ volatile cyg_uint16 resv6;
+ volatile cyg_uint16 usr1;
+ volatile cyg_uint16 resv7;
+ volatile cyg_uint16 usr2;
+ volatile cyg_uint16 resv8;
+ volatile cyg_uint16 uesc;
+ volatile cyg_uint16 resv9;
+ volatile cyg_uint16 utim;
+ volatile cyg_uint16 resv10;
+ volatile cyg_uint16 ubir;
+ volatile cyg_uint16 resv11;
+ volatile cyg_uint16 ubmr;
+ volatile cyg_uint16 resv12;
+ volatile cyg_uint16 ubrc;
+ volatile cyg_uint16 resv13;
+ volatile cyg_uint16 onems;
+ volatile cyg_uint16 resv14;
+ volatile cyg_uint16 uts;
+ volatile cyg_uint16 resv15;
+};
+#endif
+
+typedef struct {
+ volatile struct mxc_serial* base;
+ cyg_int32 msec_timeout;
+ int isr_vector;
+ int baud_rate;
+} channel_data_t;
+
+static channel_data_t channels[] = {
+#if CYGHWR_HAL_ARM_SOC_UART1 != 0
+ {(volatile struct mxc_serial*)UART1_BASE_ADDR, 1000,
+ CYGNUM_HAL_INTERRUPT_UART1, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#endif
+#if CYGHWR_HAL_ARM_SOC_UART2 != 0
+ {(volatile struct mxc_serial*)UART2_BASE_ADDR, 1000,
+ CYGNUM_HAL_INTERRUPT_UART2, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#endif
+#if CYGHWR_HAL_ARM_SOC_UART3 != 0
+ {(volatile struct mxc_serial*)UART3_BASE_ADDR, 1000,
+ CYGNUM_HAL_INTERRUPT_UART3, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#endif
+};
+
+/*---------------------------------------------------------------------------*/
+
+static void init_serial_channel(channel_data_t* __ch_data)
+{
+ volatile struct mxc_serial* base = __ch_data->base;
+
+ /* Wait for UART to finish transmitting */
+ while (!(base->uts & EUartUTS_TXEMPTY));
+
+ /* Disable UART */
+ base->ucr1 &= ~EUartUCR1_UARTEN;
+
+ /* Set to default POR state */
+ base->ucr1 = 0x00000000;
+ base->ucr2 = 0x00000000;
+
+ while (!(base->ucr2 & EUartUCR2_SRST_));
+
+ base->ucr3 = 0x00000704;
+ base->ucr4 = 0x00008000;
+ base->ufcr = 0x00000801;
+ base->uesc = 0x0000002B;
+ base->utim = 0x00000000;
+ base->ubir = 0x00000000;
+ base->ubmr = 0x00000000;
+ base->onems = 0x00000000;
+ base->uts = 0x00000000;
+
+ /* Configure FIFOs */
+ base->ufcr = (1 << EUartUFCR_RXTL_SHF) | EUartUFCR_RFDIV
+ | (2 << EUartUFCR_TXTL_SHF);
+
+ /* Setup One MS timer */
+ base->onems = (MXC_UART_REFFREQ / 1000);
+
+ /* Set to 8N1 */
+ base->ucr2 &= ~EUartUCR2_PREN;
+ base->ucr2 |= EUartUCR2_WS;
+ base->ucr2 &= ~EUartUCR2_STPB;
+
+ /* Ignore RTS */
+ base->ucr2 |= EUartUCR2_IRTS;
+
+ /* Enable UART */
+ base->ucr1 |= EUartUCR1_UARTEN;
+
+ /* Enable FIFOs */
+ base->ucr2 |= EUartUCR2_SRST_ | EUartUCR2_RXEN | EUartUCR2_TXEN;
+
+ /* Clear status flags */
+ base->usr2 |= EUartUSR2_ADET |
+ EUartUSR2_IDLE |
+ EUartUSR2_IRINT |
+ EUartUSR2_WAKE |
+ EUartUSR2_RTSF |
+ EUartUSR2_BRCD |
+ EUartUSR2_ORE |
+ EUartUSR2_RDR;
+
+ /* Clear status flags */
+ base->usr1 |= EUartUSR1_PARITYERR |
+ EUartUSR1_RTSD |
+ EUartUSR1_ESCF |
+ EUartUSR1_FRAMERR |
+ EUartUSR1_AIRINT |
+ EUartUSR1_AWAKE;
+
+ /* Set the numerator value minus one of the BRM ratio */
+ base->ubir = (__ch_data->baud_rate / 100) - 1;
+
+ /* Set the denominator value minus one of the BRM ratio */
+ base->ubmr = ((MXC_UART_REFFREQ / 1600) - 1);
+
+}
+
+static void stop_serial_channel(channel_data_t* __ch_data)
+{
+ volatile struct mxc_serial* base = __ch_data->base;
+
+ /* Wait for UART to finish transmitting */
+ while (!(base->uts & EUartUTS_TXEMPTY));
+
+ /* Disable UART */
+ base->ucr1 &= ~EUartUCR1_UARTEN;
+}
+
+//#define debug_uart_log_buf
+#ifdef debug_uart_log_buf
+#define DIAG_BUFSIZE 2048
+static char __log_buf[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+
+void cyg_hal_plf_serial_putc(void *__ch_data, char c)
+{
+ volatile struct mxc_serial* base = ((channel_data_t*)__ch_data)->base;
+
+#ifdef debug_uart_log_buf
+ __log_buf[diag_bp++] = c;
+#endif
+
+ CYGARC_HAL_SAVE_GP();
+
+ // Wait for Tx FIFO not full
+ while (base->uts & EUartUTS_TXFULL)
+ ;
+ base->utxd[0] = c;
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool cyg_hal_plf_serial_getc_nonblock(void* __ch_data,
+ cyg_uint8* ch)
+{
+ volatile struct mxc_serial* base = ((channel_data_t*)__ch_data)->base;
+
+ // If receive fifo is empty, return false
+ if (base->uts & EUartUTS_RXEMPTY)
+ return false;
+
+ *ch = (char)base->urxd[0];
+
+ return true;
+}
+
+cyg_uint8 cyg_hal_plf_serial_getc(void* __ch_data)
+{
+ cyg_uint8 ch;
+ CYGARC_HAL_SAVE_GP();
+
+ while (!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
+
+ CYGARC_HAL_RESTORE_GP();
+ return ch;
+}
+
+static void cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while(__len-- > 0)
+ cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static void cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while (__len-- > 0)
+ *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool cyg_hal_plf_serial_getc_timeout(void* __ch_data,
+ cyg_uint8* ch)
+{
+ int delay_count;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_bool res;
+ CYGARC_HAL_SAVE_GP();
+
+ delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+
+ for(;;) {
+ res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
+ if (res || 0 == delay_count--)
+ break;
+
+ CYGACC_CALL_IF_DELAY_US(100);
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static int cyg_hal_plf_serial_control(void *__ch_data,
+ __comm_control_cmd_t __func, ...)
+{
+ static int irq_state = 0;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ int ret = -1;
+ va_list ap;
+
+ CYGARC_HAL_SAVE_GP();
+ va_start(ap, __func);
+
+ switch (__func) {
+ case __COMMCTL_GETBAUD:
+ ret = chan->baud_rate;
+ break;
+ case __COMMCTL_SETBAUD:
+ chan->baud_rate = va_arg(ap, cyg_int32);
+ // Should we verify this value here?
+ init_serial_channel(chan);
+ ret = 0;
+ break;
+ case __COMMCTL_IRQ_ENABLE:
+ irq_state = 1;
+
+ chan->base->ucr1 |= EUartUCR1_RRDYEN;
+
+ HAL_INTERRUPT_UNMASK(chan->isr_vector);
+ break;
+ case __COMMCTL_IRQ_DISABLE:
+ ret = irq_state;
+ irq_state = 0;
+
+ chan->base->ucr1 &= ~EUartUCR1_RRDYEN;
+
+ HAL_INTERRUPT_MASK(chan->isr_vector);
+ break;
+ case __COMMCTL_DBG_ISR_VECTOR:
+ ret = chan->isr_vector;
+ break;
+ case __COMMCTL_SET_TIMEOUT:
+ ret = chan->msec_timeout;
+ chan->msec_timeout = va_arg(ap, cyg_uint32);
+ break;
+ default:
+ break;
+ }
+ va_end(ap);
+ CYGARC_HAL_RESTORE_GP();
+ return ret;
+}
+
+static int cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
+ CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+ int res = 0;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ char c;
+
+ CYGARC_HAL_SAVE_GP();
+
+ cyg_drv_interrupt_acknowledge(chan->isr_vector);
+
+ *__ctrlc = 0;
+ if (!(chan->base->uts & EUartUTS_RXEMPTY)) {
+ c = (char)chan->base->urxd[0];
+
+ if (cyg_hal_is_break( &c , 1 ))
+ *__ctrlc = 1;
+
+ res = CYG_ISR_HANDLED;
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+void cyg_hal_plf_serial_init(void)
+{
+ hal_virtual_comm_table_t* comm;
+ int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ int i;
+ static int jjj = 0;
+
+ // Init channels
+#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
+ for (i = 0; i < NUMOF(channels); i++) {
+ init_serial_channel(&channels[i]);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(i+2);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+ if (jjj == 0) {
+ cyg_hal_plf_serial_putc(&channels[i], '+');
+ jjj++;
+ }
+ cyg_hal_plf_serial_putc(&channels[i], '+');
+ }
+
+ // Restore original console
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+void cyg_hal_plf_serial_stop(void)
+{
+ int i;
+
+ // Init channels
+#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
+ for (i = 0; i < NUMOF(channels); i++) {
+ stop_serial_channel(&channels[i]);
+ }
+}
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
+
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 2)
+#define __BASE ((void*)UART1_BASE_ADDR)
+#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART1
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 3)
+#define __BASE ((void*)UART2_BASE_ADDR)
+#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART2
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 4)
+#define __BASE ((void*)UART3_BASE_ADDR)
+#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART3
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 5)
+#define __BASE ((void*)UART4_BASE_ADDR)
+#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART4
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 6)
+#define __BASE ((void*)UART5_BASE_ADDR)
+#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART5
+#endif
+
+#ifdef __BASE
+
+#ifdef CYGSEM_HAL_ROM_MONITOR
+#define CYG_HAL_STARTUP_ROM
+#define CYG_HAL_STARTUP_ROMRAM
+#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#endif
+
+#if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define HAL_DIAG_USES_HARDWARE
+#elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
+#define HAL_DIAG_USES_HARDWARE
+#elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+#define HAL_DIAG_USES_HARDWARE
+#endif
+
+static channel_data_t channel = {
+ (volatile struct mxc_serial*)__BASE, 0, CYGHWR_HAL_GDB_PORT_VECTOR
+};
+
+#ifdef HAL_DIAG_USES_HARDWARE
+
+void hal_diag_init(void)
+{
+ static int init = 0;
+ char *msg = "\n\rARM eCos\n\r";
+ cyg_uint8 lcr;
+
+ if (init++) return;
+
+ init_serial_channel(&channel);
+
+ while (*msg) hal_diag_write_char(*msg++);
+}
+
+#ifdef DEBUG_DIAG
+#ifndef CYG_HAL_STARTUP_ROM
+#define DIAG_BUFSIZE 2048
+static char diag_buffer[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+#endif
+
+void hal_diag_write_char(char c)
+{
+#ifdef DEBUG_DIAG
+#ifndef CYG_HAL_STARTUP_ROM
+ diag_buffer[diag_bp++] = c;
+ if (diag_bp == sizeof(diag_buffer)) diag_bp = 0;
+#endif
+#endif
+ cyg_hal_plf_serial_putc(&channel, c);
+}
+
+void hal_diag_read_char(char *c)
+{
+ *c = cyg_hal_plf_serial_getc(&channel);
+}
+
+#else // not HAL_DIAG_USES_HARDWARE - it uses GDB protocol
+
+void hal_diag_read_char(char *c)
+{
+ *c = cyg_hal_plf_serial_getc(&channel);
+}
+
+void hal_diag_write_char(char c)
+{
+ static char line[100];
+ static int pos = 0;
+
+ // FIXME: Some LED blinking might be nice right here.
+
+ // No need to send CRs
+ if( c == '\r' ) return;
+
+ line[pos++] = c;
+
+ if (c == '\n' || pos == sizeof(line)) {
+ CYG_INTERRUPT_STATE old;
+
+ // Disable interrupts. This prevents GDB trying to interrupt us
+ // while we are in the middle of sending a packet. The serial
+ // receive interrupt will be seen when we re-enable interrupts
+ // later.
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+#else
+ HAL_DISABLE_INTERRUPTS(old);
+#endif
+
+ while (1) {
+ static char hex[] = "0123456789ABCDEF";
+ cyg_uint8 csum = 0;
+ int i;
+#ifndef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ char c1;
+#endif
+ cyg_hal_plf_serial_putc(&channel, '$');
+ cyg_hal_plf_serial_putc(&channel, 'O');
+ csum += 'O';
+ for(i = 0; i < pos; i++) {
+ char ch = line[i];
+ char h = hex[(ch>>4)&0xF];
+ char l = hex[ch&0xF];
+ cyg_hal_plf_serial_putc(&channel, h);
+ cyg_hal_plf_serial_putc(&channel, l);
+ csum += h;
+ csum += l;
+ }
+ cyg_hal_plf_serial_putc(&channel, '#');
+ cyg_hal_plf_serial_putc(&channel, hex[(csum>>4)&0xF]);
+ cyg_hal_plf_serial_putc(&channel, hex[csum&0xF]);
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+
+ break; // regardless
+
+#else // not CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT Ie. usually...
+
+ // Wait for the ACK character '+' from GDB here and handle
+ // receiving a ^C instead. This is the reason for this clause
+ // being a loop.
+ c1 = cyg_hal_plf_serial_getc(&channel);
+
+ if( c1 == '+' )
+ break; // a good acknowledge
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ cyg_drv_interrupt_acknowledge(CYGHWR_HAL_GDB_PORT_VECTOR);
+ if( c1 == 3 ) {
+ // Ctrl-C: breakpoint.
+ cyg_hal_gdb_interrupt(
+ (target_register_t)__builtin_return_address(0) );
+ break;
+ }
+#endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+
+#endif // ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ // otherwise, loop round again
+ }
+
+ pos = 0;
+
+ // And re-enable interrupts
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+#else
+ HAL_RESTORE_INTERRUPTS(old);
+#endif
+
+ }
+}
+#endif
+
+#endif // __BASE
+
+#endif // !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
+/* End of hal_diag.c */
--- /dev/null
+//==========================================================================
+//
+// soc_misc.c
+//
+// HAL misc board support code
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#include <redboot.h>
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_misc.h> // Size constants
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h> // Interrupt names
+#include <cyg/hal/hal_cache.h> // Cache control
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/hal_mm.h> // MMap table definitions
+
+#include <cyg/infra/diag.h> // diag_printf
+
+// Most initialization has already been done before we get here.
+// All we do here is set up the interrupt environment.
+// FIXME: some of the stuff in hal_platform_setup could be moved here.
+
+externC void plf_hardware_init(void);
+
+#define IIM_PROD_REV_SH 3
+#define IIM_PROD_REV_LEN 5
+#define IIM_SREV_REV_SH 4
+#define IIM_SREV_REV_LEN 4
+
+#define PROD_SIGNATURE_MX25 0x1
+
+#define PROD_SIGNATURE_SUPPORTED_1 PROD_SIGNATURE_MX25
+
+#define CHIP_VERSION_NONE 0xFFFFFFFF // invalid product ID
+#define CHIP_VERSION_UNKNOWN 0xDEADBEEF // invalid chip rev
+
+#define PART_NUMBER_OFFSET (12)
+#define MAJOR_NUMBER_OFFSET (4)
+#define MINOR_NUMBER_OFFSET (0)
+
+/*
+ * System_rev will have the following format
+ * 31-12 = part # (0x31, 0x32, 0x27, 0x91131, 0x91321, 0x35, etc)
+ * 11-8 = unused
+ * 7-4 = major (1.y)
+ * 3-0 = minor (x.0)
+ */
+unsigned int system_rev = CHIP_REV_1_0;
+static int find_correct_chip;
+extern char HAL_PLATFORM_EXTRA[55];
+
+/*
+ * This functions reads the IIM module and returns the system revision number.
+ * It returns the IIM silicon revision reg value if valid product rev is found.
+ . Otherwise, it returns -1.
+ */
+static int read_system_rev(void)
+{
+ int val;
+
+ val = readl(IIM_BASE_ADDR + IIM_PREV_OFF);
+
+ system_rev = 0x25 << PART_NUMBER_OFFSET; /* For MX25 Platform*/
+ /* If the IIM doesn't contain valid product signature, return
+ * the lowest revision number */
+ if ((MXC_GET_FIELD(val, IIM_PROD_REV_LEN, IIM_PROD_REV_SH) !=
+ PROD_SIGNATURE_SUPPORTED_1)) {
+ return CHIP_VERSION_NONE;
+ }
+
+ /* Now trying to retrieve the silicon rev from IIM's SREV register */
+ return readl(IIM_BASE_ADDR + IIM_SREV_OFF);
+}
+
+extern nfc_setup_func_t *nfc_setup;
+unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz,
+ unsigned int is_mlc, unsigned int num_of_chips);
+void hal_hardware_init(void)
+{
+ int ver;
+
+ ver = read_system_rev();
+ find_correct_chip = ver;
+
+ // Mask all interrupts
+ writel(0xFFFFFFFF, ASIC_NIMASK);
+
+ // Make all interrupts do IRQ and not FIQ
+ // FIXME: Change this if you use FIQs.
+ writel(0, ASIC_INTTYPEH);
+ writel(0, ASIC_INTTYPEL);
+
+ // Enable caches
+ HAL_ICACHE_ENABLE();
+ HAL_DCACHE_ENABLE();
+
+ // enable EPIT and start it with 32KHz input clock
+ writel(0x00010000, EPIT_BASE_ADDR + EPITCR);
+
+ // make sure reset is complete
+ while ((readl(EPIT_BASE_ADDR + EPITCR) & 0x10000) != 0) {
+ }
+
+ writel(0x030E0002, EPIT_BASE_ADDR + EPITCR);
+ writel(0x030E0003, EPIT_BASE_ADDR + EPITCR);
+
+ writel(0, EPIT_BASE_ADDR + EPITCMPR); // always compare with 0
+
+ if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
+ // increase the WDOG timeout value to the max
+ writew(readw(WDOG_BASE_ADDR) | 0xFF00, WDOG_BASE_ADDR);
+ }
+
+ // Perform any platform specific initializations
+ plf_hardware_init();
+
+ // Set up eCos/ROM interfaces
+ hal_if_init();
+
+ nfc_setup = (nfc_setup_func_t*)mxc_nfc_soc_setup;
+}
+
+// -------------------------------------------------------------------------
+void hal_clock_initialize(cyg_uint32 period)
+{
+}
+
+// This routine is called during a clock interrupt.
+
+// Define this if you want to ensure that the clock is perfect (i.e. does
+// not drift). One reason to leave it turned off is that it costs some
+// us per system clock interrupt for this maintenance.
+#undef COMPENSATE_FOR_CLOCK_DRIFT
+
+void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
+{
+}
+
+// Read the current value of the clock, returning the number of hardware
+// "ticks" that have occurred (i.e. how far away the current value is from
+// the start)
+
+// Note: The "contract" for this function is that the value is the number
+// of hardware clocks that have happened since the last interrupt (i.e.
+// when it was reset). This value is used to measure interrupt latencies.
+// However, since the hardware counter runs freely, this routine computes
+// the difference between the current clock period and the number of hardware
+// ticks left before the next timer interrupt.
+void hal_clock_read(cyg_uint32 *pvalue)
+{
+}
+
+// This is to cope with the test read used by tm_basic with
+// CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY defined; we read the count ASAP
+// in the ISR, *before* resetting the clock. Which returns 1tick +
+// latency if we just use plain hal_clock_read().
+void hal_clock_latency(cyg_uint32 *pvalue)
+{
+}
+
+unsigned int hal_timer_count(void)
+{
+ return (0xFFFFFFFF - readl(EPIT_BASE_ADDR + EPITCNR));
+}
+
+#define WDT_MAGIC_1 0x5555
+#define WDT_MAGIC_2 0xAAAA
+#define MXC_WDT_WSR 0x2
+
+unsigned int i2c_base_addr[] = {
+ I2C_BASE_ADDR,
+ I2C2_BASE_ADDR,
+ I2C3_BASE_ADDR
+};
+unsigned int i2c_num = 3;
+
+static unsigned int led_on = 0;
+//
+// Delay for some number of micro-seconds
+//
+void hal_delay_us(unsigned int usecs)
+{
+ /*
+ * This causes overflow.
+ * unsigned int delayCount = (usecs * 32000) / 1000000;
+ * So use the following one instead
+ */
+ unsigned int delayCount = (usecs*4 + 124) / 125;
+
+ if (delayCount == 0) {
+ return;
+ }
+
+ // issue the service sequence instructions
+ if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
+ writew(WDT_MAGIC_1, WDOG_BASE_ADDR + MXC_WDT_WSR);
+ writew(WDT_MAGIC_2, WDOG_BASE_ADDR + MXC_WDT_WSR);
+ }
+
+ writel(0x01, EPIT_BASE_ADDR + EPITSR); // clear the compare status bit
+
+ writel(delayCount, EPIT_BASE_ADDR + EPITLR);
+
+ while ((0x1 & readl(EPIT_BASE_ADDR + EPITSR)) == 0); // return until compare bit is set
+ if ((++led_on % 2000) == 0)
+ BOARD_DEBUG_LED(0);
+}
+
+// -------------------------------------------------------------------------
+
+// This routine is called to respond to a hardware interrupt (IRQ). It
+// should interrogate the hardware and return the IRQ vector number.
+int hal_IRQ_handler(void)
+{
+#ifdef HAL_EXTENDED_IRQ_HANDLER
+ cyg_uint32 index;
+
+ // Use platform specific IRQ handler, if defined
+ // Note: this macro should do a 'return' with the appropriate
+ // interrupt number if such an extended interrupt exists. The
+ // assumption is that the line after the macro starts 'normal' processing.
+ HAL_EXTENDED_IRQ_HANDLER(index);
+#endif
+
+ return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
+}
+
+//
+// Interrupt control
+//
+
+void hal_interrupt_mask(int vector)
+{
+// diag_printf("6hal_interrupt_mask(vector=%d) \n", vector);
+#ifdef HAL_EXTENDED_INTERRUPT_MASK
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_MASK(vector);
+#endif
+}
+
+void hal_interrupt_unmask(int vector)
+{
+// diag_printf("7hal_interrupt_unmask(vector=%d) \n", vector);
+
+#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_UNMASK(vector);
+#endif
+}
+
+void hal_interrupt_acknowledge(int vector)
+{
+
+// diag_printf("8hal_interrupt_acknowledge(vector=%d) \n", vector);
+#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector);
+#endif
+}
+
+void hal_interrupt_configure(int vector, int level, int up)
+{
+
+#ifdef HAL_EXTENDED_INTERRUPT_CONFIGURE
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_CONFIGURE(vector, level, up);
+#endif
+}
+
+void hal_interrupt_set_level(int vector, int level)
+{
+
+#ifdef HAL_EXTENDED_INTERRUPT_SET_LEVEL
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_SET_LEVEL(vector, level);
+#endif
+
+ // Interrupt priorities are not configurable.
+}
+
+unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz, unsigned int is_mlc, unsigned int num_of_chips)
+{
+ unsigned int tmp ;
+ if (is_mlc) {
+ tmp = readw(NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF) | (1 << 8);
+ } else {
+ tmp = readw(NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF) & (~(1 << 8));
+ }
+
+ writew(tmp, NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF);
+ tmp = readl(CCM_BASE_ADDR + CLKCTL_RCSR);
+ if (io_sz == 16) {
+ tmp |= (1 << 14);
+ } else {
+ tmp &= (~(1 << 14));
+ }
+
+ tmp &= ~(3<<8);
+ switch(pg_sz = 2048){
+ case 2048:
+ tmp |= (1<<8);
+ break;
+ case 4096:
+ tmp |= (1<<9);
+ break;
+ }
+
+ writel(tmp, CCM_BASE_ADDR + CLKCTL_RCSR);
+ diag_printf("NAND: RCSR=%x\n", tmp);
+ return 0x10;
+}
+
+static void check_reset_source(void)
+{
+ unsigned int rest = readl(CCM_BASE_ADDR + CLKCTL_RCSR) & 0xF;
+
+ if (rest == 0)
+ diag_printf("hardware reset by POR\n");
+ else if (rest == 1)
+ diag_printf("hardware reset by Board reset signal\n");
+ else if ((rest & 2) == 2)
+ diag_printf("hardware reset by WDOG\n");
+ else if ((rest & 4) == 4)
+ diag_printf("hardware reset by SOFT RESET\n");
+ else if ((rest & 8) == 8)
+ diag_printf("hardware reset by JTAG SW RESET\n");
+ else
+ diag_printf("hardware reset by unknown source (REST=%x)\n", rest);
+}
+
+RedBoot_init(check_reset_source, RedBoot_INIT_LAST);
+
+static void check_correct_chip(void)
+{
+ if (find_correct_chip == CHIP_VERSION_UNKNOWN) {
+ diag_printf("Unrecognized chip version: 0x%x!!!\n", read_system_rev());
+ diag_printf("Assuming chip version=0x%x\n", system_rev);
+ } else if (find_correct_chip == CHIP_VERSION_NONE) {
+ diag_printf("Unrecognized chip: 0x%x!!!\n", readl(IIM_BASE_ADDR + IIM_PREV_OFF));
+ }
+}
+
+RedBoot_init(check_correct_chip, RedBoot_INIT_LAST);
--- /dev/null
+# ====================================================================
+#
+# hal_arm_board.cdl
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+
+cdl_package CYGPKG_HAL_ARM_MX27_3STACK {
+ display "Freescale board"
+ parent CYGPKG_HAL_ARM_MX27
+ hardware
+ include_dir cyg/hal
+ define_header hal_arm_board.h
+ description "
+ This HAL platform package provides generic
+ support for the Freescale 3-Stack Board."
+
+ compile board_misc.c board_diag.c
+ implements CYGINT_HAL_DEBUG_GDB_STUBS
+ implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+ implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+
+ implements CYGHWR_HAL_ARM_DUART_UARTA
+ implements CYGHWR_HAL_ARM_SOC_UART1
+ implements CYGHWR_DEVS_FLASH_MXC_NAND_RESET_WORKAROUND
+
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_soc.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_board.h>"
+ puts $::cdl_header "#define HAL_PLATFORM_CPU \"Freescale i.MX27 based\""
+ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"MX27 3-Stack\""
+ puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 1430"
+ puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK board_program_new_stack"
+ }
+
+ cdl_component CYG_HAL_STARTUP {
+ display "Startup type"
+ flavor data
+ default_value {"ROM"}
+ legal_values {"RAM" "ROM" "ROMRAM"}
+ no_define
+ define -file system.h CYG_HAL_STARTUP
+ description "
+ When targetting the eval board it is possible to build
+ the system for either RAM bootstrap or ROM bootstrap(s). Select
+ 'ram' when building programs to load into RAM using eCos GDB
+ stubs. Select 'rom' when building a stand-alone application
+ which will be put into ROM, or for the special case of
+ building the eCos GDB stubs themselves. Using ROMRAM will allow
+ the program to exist in ROM, but be copied to RAM during startup."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_DUART_UARTA {
+ display "ST16552 UARTA available as diagnostic/debug channel"
+ description "
+ The board has a ST16552 DUART chip. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_DUART_UARTB {
+ display "ST16552 UARTB available as diagnostic/debug channel"
+ description "
+ The board has a ST16552 DUART chip. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ display "Diagnostic serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the console port.
+ Note: this should match the value chosen for the GDB port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ display "GDB serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the GDB port.
+ Note: this should match the value chosen for the console port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the board"
+ flavor data
+ calculated 6
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ The board has three serial ports. This option
+ chooses which port will be used to connect to a host
+ running GDB."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+ display "Default console channel."
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ calculated 0
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Console serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ description "
+ The board has only three serial ports. This option
+ chooses which port will be used for console output."
+ }
+
+ cdl_component CYGBLD_GLOBAL_OPTIONS {
+ display "Global build options"
+ flavor none
+ no_define
+ description "
+ Global build options including control over
+ compiler flags, linker flags and choice of toolchain."
+
+
+ parent CYGPKG_NONE
+
+ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ display "Global command prefix"
+ flavor data
+ no_define
+ default_value { "arm-none-eabi" }
+ description "
+ This option specifies the command prefix used when
+ invoking the build tools."
+ }
+
+ cdl_option CYGBLD_GLOBAL_CFLAGS {
+ display "Global compiler flags"
+ flavor data
+ no_define
+ default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ description "
+ This option controls the global compiler flags which are used to
+ compile all packages by default. Individual packages may define
+ options which override these global flags."
+ }
+
+ cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ display "Global linker flags"
+ flavor data
+ no_define
+ default_value { "-Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" }
+ description "
+ This option controls the global linker flags. Individual
+ packages may define options which override these global flags."
+ }
+
+ cdl_option CYGBLD_BUILD_GDB_STUBS {
+ display "Build GDB stub ROM image"
+ default_value 0
+ requires { CYG_HAL_STARTUP == "ROM" }
+ requires CYGSEM_HAL_ROM_MONITOR
+ requires CYGBLD_BUILD_COMMON_GDB_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ no_define
+ description "
+ This option enables the building of the GDB stubs for the
+ board. The common HAL controls takes care of most of the
+ build process, but the final conversion from ELF image to
+ binary data is handled by the platform CDL, allowing
+ relocation of the data if necessary."
+
+ make -priority 320 {
+ <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
+ $(OBJCOPY) --remove-section=.fixed_vectors -O binary $< $@
+ }
+ }
+ }
+
+ cdl_component CYGPKG_HAL_ARM_BOARD_OPTIONS {
+ display "Freescale MXC Board build options"
+ flavor none
+ no_define
+ description "
+ Package specific build options including control over
+ compiler flags used only in building this package,
+ and details of which tests are built."
+
+ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the board HAL. These flags are used in addition
+ to the set of global flags."
+ }
+
+ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_REMOVE {
+ display "Suppressed compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the board HAL. These flags are removed from
+ the set of global flags if present."
+ }
+
+ }
+
+ cdl_component CYGHWR_MEMORY_LAYOUT {
+ display "Memory layout"
+ flavor data
+ no_define
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_board_ram" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" :
+ "arm_board_rom" }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ display "Memory layout linker script fragment"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.ldi>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.ldi>" :
+ "<pkgconf/mlt_arm_board_rom.ldi>" }
+ }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ display "Memory layout header file"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_H
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.h>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.h>" :
+ "<pkgconf/mlt_arm_board_rom.h>" }
+ }
+ }
+
+ cdl_option CYGSEM_HAL_ROM_MONITOR {
+ display "Behave as a ROM monitor"
+ flavor bool
+ default_value 0
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+ description "
+ Enable this option if this program is to be used as a ROM monitor,
+ i.e. applications will be loaded into RAM on the board, and this
+ ROM monitor may process exceptions or interrupts generated from the
+ application. This enables features such as utilizing a separate
+ interrupt stack when exceptions are generated."
+ }
+
+ cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ display "Work with a ROM monitor"
+ flavor booldata
+ legal_values { "Generic" "GDB_stubs" }
+ default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "RAM" }
+ description "
+ Support can be enabled for different varieties of ROM monitor.
+ This support changes various eCos semantics such as the encoding
+ of diagnostic output, or the overriding of hardware interrupt
+ vectors.
+ Firstly there is \"Generic\" support which prevents the HAL
+ from overriding the hardware vectors that it does not use, to
+ instead allow an installed ROM monitor to handle them. This is
+ the most basic support which is likely to be common to most
+ implementations of ROM monitor.
+ \"GDB_stubs\" provides support when GDB stubs are included in
+ the ROM monitor or boot ROM."
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ display "Redboot HAL options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+ description "
+ This option lists the target's requirements for a valid Redboot
+ configuration."
+
+ compile -library=libextras.a redboot_cmds.c
+
+ cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ display "Build Redboot ROM binary image"
+ active_if CYGBLD_BUILD_REDBOOT
+ default_value 1
+ no_define
+ description "This option enables the conversion of the Redboot ELF
+ image to a binary image suitable for ROM programming."
+
+ make -priority 325 {
+ <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+ $(OBJCOPY) -O binary $< $@
+ }
+ }
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_BOARD_OPTIONS {
+ display "Redboot HAL variant options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+
+ # RedBoot details
+ requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0xA0008000 }
+ define_proc {
+ puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00"
+ }
+ }
+}
--- /dev/null
+#ifndef CYGONCE_FSL_BOARD_H
+#define CYGONCE_FSL_BOARD_H
+
+//=============================================================================
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+
+#define PMIC_SPI_BASE CSPI2_BASE_ADDR
+#define PMIC_SPI_CHIP_SELECT_NO SPI_CTRL_CS0
+
+#define PBC_BASE SOC_CS5_BASE /* Peripheral Bus Controller */
+#define PBC_LED_CTRL (PBC_BASE + 0x20000)
+#define PBC_SB_STAT (PBC_BASE + 0x20008)
+#define PBC_ID_AAAA (PBC_BASE + 0x20040)
+#define PBC_ID_5555 (PBC_BASE + 0x20048)
+#define PBC_VERSION (PBC_BASE + 0x20050)
+#define PBC_ID_CAFE (PBC_BASE + 0x20058)
+#define PBC_INT_STAT (PBC_BASE + 0x20068)
+#define PBC_INT_MASK (PBC_BASE + 0x20010)
+#define PBC_INT_REST (PBC_BASE + 0x20020)
+#define PBC_SW_RESET (PBC_BASE + 0x20060)
+
+#define BOARD_CS_LAN_BASE (SOC_CS5_BASE + 0x00000)
+#define BOARD_CS_UART_BASE (SOC_CS5_BASE + 0x08000)
+
+#define BOARD_FLASH_START SOC_CS0_BASE
+#define REDBOOT_IMAGE_SIZE 0x40000
+
+#define RAM_BANK0_BASE SOC_CSD0_BASE
+
+#define SDRAM_BASE_ADDR SOC_CSD0_BASE
+#define SDRAM_SIZE 0x08000000
+
+#define EXT_UART_x16
+//#define EXT_UART_x32
+#define LED_MAX_NUM 8
+#define LED_IS_ON(n) ((readw(PBC_LED_CTRL) & (1<<(n))) != 0)
+#define TURN_LED_ON(n) writew((readw(PBC_LED_CTRL)|(1<<(n))), PBC_LED_CTRL)
+#define TURN_LED_OFF(n) writew((readw(PBC_LED_CTRL)&(~(1<<(n)))), PBC_LED_CTRL)
+
+#define FEC_PHY_ADDR 0x1F
+
+#define BOARD_DEBUG_LED(n) \
+ CYG_MACRO_START \
+ if (n >= 0 && n < LED_MAX_NUM) { \
+ if (LED_IS_ON(n)) \
+ TURN_LED_OFF(n); \
+ else \
+ TURN_LED_ON(n); \
+ } \
+ CYG_MACRO_END
+
+#define BOARD_PBC_VERSION (*(volatile unsigned short*)(PBC_VERSION))
+
+#if !defined(__ASSEMBLER__)
+enum {
+ BOARD_TYPE_UNKNOWN,
+ BOARD_TYPE_3STACK,
+};
+#endif
+
+#endif /* CYGONCE_FSL_BOARD_H */
--- /dev/null
+#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
+#define CYGONCE_HAL_PLATFORM_SETUP_H
+
+//=============================================================================
+//
+// hal_platform_setup.h
+//
+// Platform specific support for HAL (assembly code)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <pkgconf/system.h> // System-wide configuration info
+#include CYGBLD_HAL_VARIANT_H // Variant specific configuration
+#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
+#include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
+#include <cyg/hal/hal_mmu.h> // MMU definitions
+#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1 _platform_setup1
+#define CYGHWR_HAL_ARM_HAS_MMU
+
+#ifdef CYG_HAL_STARTUP_ROMRAM
+#define CYGSEM_HAL_ROM_RESET_USES_JUMP
+#endif
+
+#define CYGHWR_HAL_ROM_VADDR 0x0
+
+// This macro represents the initial startup code for the platform
+// r11 is reserved to contain chip rev info in this file
+ .macro _platform_setup1
+FSL_BOARD_SETUP_START:
+ // invalidate I/D cache/TLB and drain write buffer
+ mov r0, #0
+ mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
+ mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+ mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
+
+init_aipi_start:
+ init_aipi
+
+ mov r0, #SDRAM_NON_FLASH_BOOT
+ ldr r1, AVIC_VECTOR0_ADDR_W
+ str r0, [r1] // for checking boot source from nand, nor or sdram
+
+ // setup System Controls
+ ldr r0, SOC_SYSCTRL_BASE_W
+ mov r1, #0x03
+ str r1, [r0, #(SOC_SYSCTRL_PCSR - SOC_SYSCTRL_BASE)]
+ ldr r1, [r0, #(SOC_SYSCTRL_FMCR - SOC_SYSCTRL_BASE)]
+ and r1, r1, #0xFFFFFFF0
+ orr r1, r1, #9
+ str r1, [r0, #(SOC_SYSCTRL_FMCR - SOC_SYSCTRL_BASE)]
+
+init_max_start:
+ init_max
+init_drive_strength_start:
+ init_drive_strength
+init_cs5_start:
+ init_cs5
+
+ // check if sdram has been setup
+ cmp pc, #SDRAM_BASE_ADDR
+ blo init_clock_start
+ cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
+ blo HWInitialise_skip_SDRAM_setup
+init_clock_start:
+ init_clock
+
+ // Now we must boot from Flash
+ mov r0, #NOR_FLASH_BOOT
+ ldr r1, AVIC_VECTOR0_ADDR_W
+ str r0, [r1]
+
+init_sdram_start:
+ setup_sdram_ddr
+
+HWInitialise_skip_SDRAM_setup:
+ ldr r0, NFC_BASE_W
+ add r2, r0, #0x800 // 2K window
+ cmp pc, r0
+ blo Normal_Boot_Continue
+ cmp pc, r2
+ bhi Normal_Boot_Continue
+NAND_Boot_Start:
+ /* Copy image from flash to SDRAM first */
+ ldr r1, MXC_REDBOOT_ROM_START
+
+1: ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ blo 1b
+
+ /* Jump to SDRAM */
+ ldr r1, CONST_0xFFF
+ and r0, pc, r1 /* offset of pc */
+ ldr r1, MXC_REDBOOT_ROM_START
+ add r1, r1, #0x10
+ add pc, r0, r1
+ nop
+ nop
+ nop
+ nop
+
+NAND_Copy_Main:
+ // Check if x16/2kb page
+ ldr r7, SOC_SYSCTRL_BASE_W
+ ldr r7, [r7, #0x14]
+ ands r7, r7, #(1 << 5)
+
+ mov r0, #NAND_FLASH_BOOT
+ ldr r1, AVIC_VECTOR0_ADDR_W
+ str r0, [r1]
+ mov r0, #MXCFIS_NAND
+ ldr r1, AVIC_VECTOR1_ADDR_W
+ str r0, [r1]
+
+ ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
+ mov r1, #0x800 //r1: starting flash addr to be copied. Updated constantly
+ add r2, r0, #0x800 //2K Page:: r2: end of 1st RAM buf. Doesn't change
+ addeq r2, r0, #0x200 //512 Page:: r2: end of 1st RAM buf. Doesn't change
+ add r12, r0, #0xE00 //r12: NFC register base. Doesn't change
+ ldr r11, MXC_REDBOOT_ROM_START
+ add r13, r11, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
+ add r11, r11, r1 //r11: starting SDRAM address for copying. Updated constantly
+
+ //unlock internal buffer
+ mov r3, #0x2
+ strh r3, [r12, #0xA]
+
+Nfc_Read_Page:
+// NFC_CMD_INPUT(FLASH_Read_Mode1);
+ mov r3, #0x0
+ nfc_cmd_input
+
+ // Check if x16/2kb page
+ ldr r7, SOC_SYSCTRL_BASE_W
+ ldr r7, [r7, #0x14]
+ ands r7, r7, #(1 << 5)
+
+ bne nfc_addr_ops_2kb
+// start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
+ mov r3, r1
+ do_addr_input //1st addr cycle
+ mov r3, r1, lsr #9
+ do_addr_input //2nd addr cycle
+ mov r3, r1, lsr #17
+ do_addr_input //3rd addr cycle
+ mov r3, r1, lsr #25
+ do_addr_input //4th addr cycle
+ b end_of_nfc_addr_ops
+
+nfc_addr_ops_2kb:
+// start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
+ mov r3, #0
+ do_addr_input //1st addr cycle
+ mov r3, #0
+ do_addr_input //2nd addr cycle
+ mov r3, r1, lsr #11
+ do_addr_input //3rd addr cycle
+ mov r3, r1, lsr #19
+ do_addr_input //4th addr cycle
+ mov r3, r1, lsr #27
+ do_addr_input //4th addr cycle
+
+// NFC_CMD_INPUT(FLASH_Read_Mode1_2K);
+ mov r3, #0x30
+ nfc_cmd_input
+
+end_of_nfc_addr_ops:
+// NFC_DATA_OUTPUT(buf, FDO_PAGE_SPARE_VAL);
+// writew(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN,
+// NAND_FLASH_CONFIG1_REG);
+ mov r8, #0
+ bl nfc_data_output
+ bl do_wait_op_done
+ // Check if x16/2kb page
+ ldr r7, SOC_SYSCTRL_BASE_W
+ ldr r7, [r7, #0x14]
+ ands r7, r7, #(1 << 5)
+
+ beq nfc_addr_data_output_done_512
+
+// For 2K page - 2nd 512
+ mov r8, #1
+ bl nfc_data_output
+ bl do_wait_op_done
+
+// 3rd 512
+ mov r8, #2
+ bl nfc_data_output
+ bl do_wait_op_done
+
+// 4th 512
+ mov r8, #3
+ bl nfc_data_output
+ bl do_wait_op_done
+// end of 4th
+
+ // check for bad block
+ mov r3, r1, lsl #(32-17) // get rid of block number
+ cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
+ b nfc_addr_data_output_done
+nfc_addr_data_output_done_512:
+ // check for bad block
+ mov r3, r1, lsl #(32-5-9) // get rid of block number
+ cmp r3, #(512 << (32-5-9)) // check if not page 0 or 1
+
+nfc_addr_data_output_done:
+ bhi Copy_Good_Blk
+ add r4, r0, #0x800 //r3 -> spare area buf 0
+ ldrh r4, [r4, #0x4]
+ and r4, r4, #0xFF00
+ cmp r4, #0xFF00
+ beq Copy_Good_Blk
+ // really sucks. Bad block!!!!
+ cmp r3, #0x0
+ beq Skip_bad_block
+ // even suckier since we already read the first page!
+
+ // Check if x16/2kb page
+ ldr r7, SOC_SYSCTRL_BASE_W
+ ldr r7, [r7, #0x14]
+ ands r7, r7, #(1 << 5)
+
+ subeq r11, r11, #512 //rewind 1 page for the sdram pointer
+ subeq r1, r1, #512 //rewind 1 page for the flash pointer
+
+ // for 2k page
+ subne r11, r11, #0x800 //rewind 1 page for the sdram pointer
+ subne r1, r1, #0x800 //rewind 1 page for the flash pointer
+
+Skip_bad_block:
+ // Check if x16/2kb page
+ ldr r7, SOC_SYSCTRL_BASE_W
+ ldr r7, [r7, #0x14]
+ ands r7, r7, #(1 << 5)
+
+ addeq r1, r1, #(32*512)
+ addne r1, r1, #(64*2048)
+
+ b Nfc_Read_Page
+Copy_Good_Blk:
+ //copying page
+1: ldmia r0!, {r3-r10}
+ stmia r11!, {r3-r10}
+ cmp r0, r2
+ blo 1b
+ cmp r11, r13
+ bge NAND_Copy_Main_done
+ // Check if x16/2kb page
+ ldr r7, SOC_SYSCTRL_BASE_W
+ ldr r7, [r7, #0x14]
+ ands r7, r7, #(1 << 5)
+
+ addeq r1, r1, #0x200
+ addne r1, r1, #0x800
+ mov r0, #NFC_BASE
+ b Nfc_Read_Page
+
+NAND_Copy_Main_done:
+
+Normal_Boot_Continue:
+
+#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
+ /* Copy image from flash to SDRAM first */
+ ldr r0, =0xFFFFF000
+ and r0, r0, pc
+ ldr r1, MXC_REDBOOT_ROM_START
+ cmp r0, r1
+ beq HWInitialise_skip_SDRAM_copy
+
+ add r2, r0, #REDBOOT_IMAGE_SIZE
+
+1: ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ ble 1b
+
+ /* Jump to SDRAM */
+ ldr r1, =0xFFFF
+ and r0, pc, r1 /* offset of pc */
+ ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
+ add pc, r0, r1
+ nop
+ nop
+ nop
+ nop
+#endif /* CYG_HAL_STARTUP_ROMRAM */
+
+HWInitialise_skip_SDRAM_copy:
+
+//trace
+init_cs0_sync_start:
+ init_cs0_sync
+
+NAND_ClockSetup:
+ ldr r1, =(SOC_CRM_BASE)
+ ldr r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
+/*Get chip ID://eq:i.MX27 TO1; neq:i.MX27 TO2*/
+ ldr r1, =SOC_SI_ID_REG
+ ldr r1, [r1]
+ ands r1, r1, #0xF0000000
+
+ orreq r2, r2, #0xF000
+ orrne r2, r2, #0x01C0
+
+ ldr r1, =(SOC_CRM_BASE)
+ str r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
+
+/* end of NAND clock divider setup */
+
+ // TLSbo76381: enable USB/PP/DMA burst override bits in GPCR
+ ldr r1, =(SOC_SYSCTRL_GPCR)
+ ldr r2, [r1]
+ orr r2, r2, #0x700
+ str r2, [r1]
+
+ // Set up a stack [for calling C code]
+ ldr r1, =__startup_stack
+ ldr r2, =RAM_BANK0_BASE
+ orr sp, r1, r2
+
+ // Create MMU tables
+ bl hal_mmu_init
+
+ // Enable MMU
+ ldr r2, =10f
+ mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
+ orr r1, r1, #7 // enable MMU bit
+ mcr MMU_CP, 0, r1, MMU_Control, c0
+ mov pc,r2 /* Change address spaces */
+ nop
+ nop
+ nop
+10:
+ // Save shadow copy of BCR, also hardware configuration
+ ldr r1, =_board_BCR
+ str r2,[r1]
+ ldr r1, =_board_CFG
+ str r9,[r1] // Saved far above...
+
+ .endm // _platform_setup1
+
+do_wait_op_done:
+ 1:
+ ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
+ beq 1b
+ bx lr // do_wait_op_done
+
+nfc_data_output:
+ mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
+ strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+
+ // writew(buf_no, RAM_BUFFER_ADDRESS_REG);
+ strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
+ // writew(FDO_PAGE_SPARE_VAL & 0xFF, NAND_FLASH_CONFIG2_REG);
+ mov r3, #FDO_PAGE_SPARE_VAL
+ strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ bx lr
+
+#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1
+#endif
+
+ .macro init_clock
+ ldr r0, SOC_CRM_BASE_W
+ // disable MPLL/SPLL first
+ ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+ bic r1, r1, #0x3
+ str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+
+ /* Get the chip version and configure PLLs*/
+ ldr r1, SOC_SI_ID_REG_W
+ ldr r1, [r1]
+ ands r1, r1, #0xF0000000
+
+ ldreq r1, CRM_MPCTL0_VAL_W
+ ldrne r1, CRM_MPCTL0_VAL2_W
+ str r1, [r0, #(SOC_CRM_MPCTL0 - SOC_CRM_BASE)]
+
+ ldreq r1, CRM_SPCTL0_VAL_W
+ ldrne r1, CRM_SPCTL0_VAL2_W
+ str r1, [r0, #(SOC_CRM_SPCTL0 - SOC_CRM_BASE)]
+
+ // enable/restart SPLL/MPLL
+ ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+#ifdef PLL_REF_CLK_32768HZ
+ // Make sure to use CKIL
+ bic r1, r1, #(3 << 16)
+#else
+ orr r1, r1, #(3 << 16) // select 26MHz
+#endif
+ orr r1, r1, #0x000C0000
+ orr r1, r1, #0x00000003
+ str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+
+ // add some delay here
+ mov r1, #0x1000
+ 1: subs r1, r1, #0x1
+ bne 1b
+
+ //Check The chip version TO1 or TO2
+ ldr r1, SOC_SI_ID_REG_W
+ ldr r1, [r1]
+ ands r1, r1, #0xF0000000
+
+ ldreq r2, SOC_CRM_CSCR_W
+ ldrne r2, SOC_CRM_CSCR2_W
+ str r2, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+
+ //for i.MX27 TO2, Set divider of H264_CLK to zero, NFC to 3.
+ ldrne r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
+ bicne r2, r2, #0x0000FC00
+ strne r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
+
+ /* Configure PCDR */
+ /* Configure PCDR1 */
+ ldr r1, SOC_CRM_PCDR1_W
+ str r1, [r0, #(SOC_CRM_PCDR1 - SOC_CRM_BASE)]
+
+ // Configure PCCR0 and PCCR1
+ ldr r1, SOC_CRM_PCCR0_W
+ str r1, [r0, #(SOC_CRM_PCCR0 - SOC_CRM_BASE)]
+
+ ldr r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
+ orr r1, r1, #0x0780
+ str r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
+ // make default CLKO to be FCLK
+ ldr r1, [r0, #(SOC_CRM_CCSR - SOC_CRM_BASE)]
+ and r1, r1, #0xFFFFFFE0
+ orr r1, r1, #0x7
+ str r1, [r0, #(SOC_CRM_CCSR - SOC_CRM_BASE)]
+ .endm //init_clock
+
+ /* CS0 sync mode setup */
+ .macro init_cs0_sync
+ /*
+ * Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz):
+ */
+ /* Flash reset command */
+ ldr r0, CS0_BASE_ADDR_W
+ mov r1, #0x00F0
+ strh r1, [r0]
+ /* 1st command */
+ ldr r2, CS0_CMD_0xAAA
+ add r2, r2, r0
+ mov r1, #0x00AA
+ strh r1, [r2]
+ /* 2nd command */
+ ldr r2, CS0_CMD_0x554
+ add r2, r2, r0
+ mov r1, #0x0055
+ strh r1, [r2]
+ /* 3rd command */
+ ldr r2, CS0_CMD_0xAAA
+ add r2, r2, r0
+ mov r1, #0x00D0
+ strh r1, [r2]
+ /* Write flash config register */
+ ldr r1, CS0_CFG_0x66CA
+ strh r1, [r2]
+ /* Flash reset command */
+ mov r1, #0x00F0
+ strh r1, [r0]
+
+ ldr r0, =SOC_CS0_CTL_BASE
+ ldr r1, CS0_0x23524E80
+ str r1, [r0, #CSCRU_OFFSET]
+ ldr r1, CS0_0x10000D03
+ str r1, [r0, #CSCRL_OFFSET]
+ ldr r1, CS0_0x00720900
+ str r1, [r0, #CSCRA_OFFSET]
+ .endm /* init_cs0_sync */
+
+ .macro init_cs5 /* 3-Stack board expanded IOs */
+ ldr r1, SOC_CS5_CTL_BASE_W
+ ldr r2, CS5_CSCRU_0x0000DCF6
+ str r2, [r1, #CSCRU_OFFSET]
+ ldr r2, CS5_CSCRL_0x444A4541
+ str r2, [r1, #CSCRL_OFFSET]
+ ldr r2, CS5_CSCRA_0x44443302
+ str r2, [r1, #CSCRA_OFFSET]
+ .endm /* init_cs5 */
+
+ .macro init_aipi
+ // setup AIPI1 and AIPI2
+ mov r0, #SOC_AIPI1_BASE
+ ldr r1, AIPI1_0x20040304
+ str r1, [r0] /* PSR0 */
+ ldr r2, AIPI1_0xDFFBFCFB
+ str r2, [r0, #4] /* PSR1 */
+ // set r0 = AIPI2 base
+ add r0, r0, #0x20000
+ mov r1, #0x0
+ str r1, [r0] /* PSR0 */
+ mov r2, #0xFFFFFFFF
+ str r2, [r0, #4] /* PSR1 */
+ .endm // init_aipi
+
+ .macro init_max
+ ldr r0, SOC_MAX_BASE_W
+ add r1, r0, #MAX_SLAVE_PORT1_OFFSET
+ add r2, r0, #MAX_SLAVE_PORT2_OFFSET
+ add r0, r0, #MAX_SLAVE_PORT0_OFFSET
+
+ /* MPR and AMPR */
+ ldr r6, SOC_MAX_0x00302145 /* Priority SLCD>EMMA>DMA>Codec>DAHB>IAHB */
+ str r6, [r0, #MAX_SLAVE_MPR_OFFSET] /* same for all slave ports */
+ str r6, [r0, #MAX_SLAVE_AMPR_OFFSET]
+ str r6, [r1, #MAX_SLAVE_MPR_OFFSET]
+ str r6, [r1, #MAX_SLAVE_AMPR_OFFSET]
+ str r6, [r2, #MAX_SLAVE_MPR_OFFSET]
+ str r6, [r2, #MAX_SLAVE_AMPR_OFFSET]
+ .endm //init_max
+
+ .macro init_drive_strength
+ ldr r0, SOC_SYSCTRL_BASE_W
+ ldr r1, DS_0x55555555
+ str r1, [r0, #(SOC_SYSCTRL_DSCR3 - SOC_SYSCTRL_BASE)]
+ str r1, [r0, #(SOC_SYSCTRL_DSCR5 - SOC_SYSCTRL_BASE)]
+ str r1, [r0, #(SOC_SYSCTRL_DSCR6 - SOC_SYSCTRL_BASE)]
+ ldr r1, DS_0x00005005
+ str r1, [r0, #(SOC_SYSCTRL_DSCR7 - SOC_SYSCTRL_BASE)]
+ ldr r1, DS_0x15555555
+ str r1, [r0, #(SOC_SYSCTRL_DSCR8 - SOC_SYSCTRL_BASE)]
+ .endm // init_drive_strength
+
+ .macro setup_sdram_ddr
+ ldr r0, SOC_ESDCTL_BASE_W
+ mov r2, #SOC_CSD0_BASE
+ mov r1, #0x8 // initial reset
+ str r1, [r0, #0x10]
+ // Hold for more than 200ns
+ ldr r1, =0x10000
+ 1:
+ subs r1, r1, #0x1
+ bne 1b
+
+ mov r1, #0x4
+ str r1, [r0, #0x10]
+
+ //Check The chip version TO1 or TO2
+ ldr r1, SOC_SI_ID_REG_W
+ ldr r1, [r1]
+ ands r1, r1, #0xF0000000
+ // add Latency on CAS only for TO2
+ ldreq r1, SDRAM_0x00795729
+ ldrne r1, SDRAM_0x00795429
+
+ str r1, [r0, #0x4]
+ ldr r1, SDRAM_0x92200000
+ str r1, [r0, #0x0]
+ ldr r1, [r2, #0xF00]
+ ldr r1, SDRAM_0xA2200000
+ str r1, [r0, #0x0]
+ ldr r1, [r2, #0xF00]
+ ldr r1, [r2, #0xF00]
+ ldr r1, SDRAM_0xB2200000
+ str r1, [r0, #0x0]
+ ldrb r1, [r2, #0x33]
+ add r3, r2, #0x1000000
+ ldrb r1, [r3]
+ ldr r1, SDRAM_0x82228485
+ str r1, [r0, #0x0]
+ .endm // setup_sdram_ddr
+
+ .macro nfc_cmd_input
+ strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
+ mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
+ strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ bl do_wait_op_done
+ .endm // nfc_cmd_input
+
+ .macro do_addr_input
+ and r3, r3, #0xFF
+ strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
+ mov r3, #NAND_FLASH_CONFIG2_FADD_EN
+ strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ bl do_wait_op_done
+ .endm // do_addr_input
+
+#define PLATFORM_VECTORS _platform_vectors
+ .macro _platform_vectors
+ .globl _board_BCR, _board_CFG
+_board_BCR: .long 0 // Board Control register shadow
+_board_CFG: .long 0 // Board Configuration (read at RESET)
+ .endm
+
+MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
+CONST_0xFFF: .word 0xFFF
+AVIC_VECTOR0_ADDR_W: .word MXCBOOT_FLAG_REG
+AVIC_VECTOR1_ADDR_W: .word MXCFIS_FLAG_REG
+SOC_SYSCTRL_BASE_W: .word SOC_SYSCTRL_BASE
+SOC_MAX_BASE_W: .word SOC_MAX_BASE
+SOC_MAX_0x00302145: .word 0x00302145
+SOC_CRM_BASE_W: .word SOC_CRM_BASE
+CRM_MPCTL0_VAL_W: .word CRM_MPCTL0_VAL
+CRM_SPCTL0_VAL_W: .word CRM_SPCTL0_VAL
+SOC_CRM_CSCR_W: .word CRM_CSCR_VAL
+CRM_MPCTL0_VAL2_W: .word CRM_MPCTL0_VAL2
+CRM_SPCTL0_VAL2_W: .word CRM_SPCTL0_VAL2
+SOC_CRM_CSCR2_W: .word CRM_CSCR_VAL2
+SOC_CRM_PCDR1_W: .word 0x09030913 // p1=20 p2=10 p3=4 p4=10
+SOC_CRM_PCCR0_W: .word 0x3108480F
+SOC_CS5_CTL_BASE_W: .word SOC_CS5_CTL_BASE
+CS5_CSCRU_0x0000DCF6: .word 0x0000DCF6
+CS5_CSCRL_0x444A4541: .word 0x444A4541
+CS5_CSCRA_0x44443302: .word 0x44443302
+NFC_BASE_W: .word NFC_BASE
+SOC_ESDCTL_BASE_W: .word SOC_ESDCTL_BASE
+SDRAM_0x00795429: .word 0x00795429
+SDRAM_0x00795729: .word 0x00795729
+SDRAM_0x92200000: .word 0x92200000
+SDRAM_0xA2200000: .word 0xA2200000
+SDRAM_0xB2200000: .word 0xB2200000
+SDRAM_0x82228485: .word 0x82228485
+CS0_0x0000CC03: .word 0x0000CC03
+CS0_0xA0330D01: .word 0xA0330D01
+CS0_0x00220800: .word 0x00220800
+CS0_0x23524E80: .word 0x23524E80
+CS0_0x10000D03: .word 0x10000D03
+CS0_0x00720900: .word 0x00720900
+CS0_CMD_0xAAA: .word 0x0AAA
+CS0_CMD_0x554: .word 0x0554
+CS0_CFG_0x66CA: .word 0x66CA
+CS0_BASE_ADDR_W: .word CS0_BASE_ADDR
+SOC_CS0_CTL_BASE_W: .word SOC_CS0_CTL_BASE
+DS_0x55555555: .word 0x55555555
+DS_0x00005005: .word 0x00005005
+DS_0x15555555: .word 0x15555555
+AIPI1_0x20040304: .word 0x20040304
+AIPI1_0xDFFBFCFB: .word 0xDFFBFCFB
+PBC_BASE_W: .word PBC_BASE
+SOC_SI_ID_REG_W: .word SOC_SI_ID_REG
+
+/*---------------------------------------------------------------------------*/
+/* end of hal_platform_setup.h */
+#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x00000000)
+#define CYGMEM_REGION_ram_SIZE (0x7F00000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0xA7F00000)
+#define CYGMEM_REGION_rom_SIZE (0x100000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ ram : ORIGIN = 0, LENGTH = 0x7F00000
+ rom : ORIGIN = 0xA7F00000, LENGTH = 0x100000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_rom_vectors (rom, 0xA7F00000, LMA_EQ_VMA)
+ SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
+ SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table))
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
--- /dev/null
+version 0
+region ram 0 7F00000 0 !
+region rom A7F00000 100000 1 !
+section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
+section data 0 1 1 1 1 1 0 0 8000 bss !
+section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
+section heap1 0 8 0 0 0 0 0 0 !
+section rom_vectors 0 1 0 1 1 1 1 1 A7F00000 A7F00000 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata rodata !
+section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 4 0 1 0 0 0 1 data !
--- /dev/null
+#ifndef CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+#define CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+
+//=============================================================================
+//
+// plf_io.h
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/hal/fsl_board.h>
+#include <cyg/hal/hal_soc.h>
+
+#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \
+ CYG_MACRO_START \
+ { \
+ extern unsigned int system_rev; \
+ /* Next ATAG_MEM. */ \
+ _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_MEM; \
+ /* Round up so there's only one bit set in the memory size. \
+ * Don't double it if it's already a power of two, though. \
+ */ \
+ _p_->u.mem.size = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE); \
+ if (_p_->u.mem.size < CYGMEM_REGION_ram_SIZE) \
+ _p_->u.mem.size <<= 1; \
+ _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram); \
+ _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size); \
+ _p_->hdr.size = ((sizeof(struct tag_revision)) + sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_REVISION; \
+ _p_->u.revision.rev = system_rev; \
+ } \
+ CYG_MACRO_END
+
+#endif // CYGONCE_HAL_ARM_BOARD_PLF_IO_H
--- /dev/null
+#ifndef CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+#define CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+//=============================================================================
+//
+// plf_mmap.h
+//
+// Platform specific memory map support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_misc.h>
+
+// Get the pagesize for a particular virtual address:
+
+// This does not depend on the vaddr.
+#define HAL_MM_PAGESIZE( vaddr, pagesize ) CYG_MACRO_START \
+ (pagesize) = SZ_1M; \
+CYG_MACRO_END
+
+// Get the physical address from a virtual address:
+
+#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START \
+ cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
+ if ( _v_ < 128 * SZ_1M ) /* SDRAM */ \
+ _v_ += 0xA00u * SZ_1M; \
+ else if ( _v_ < 0xF00u * SZ_1M ) \
+ /* no change */ ; \
+ else if ( _v_ < 0xF01u * SZ_1M ) /* Boot ROM */ \
+ _v_ -= 0xF00u * SZ_1M; \
+ else /* Rest of it */ \
+ /* no change */ ; \
+ (paddr) = _v_; \
+CYG_MACRO_END
+
+//---------------------------------------------------------------------------
+#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
--- /dev/null
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware mx27_3stack ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM current ;
+ package -hardware CYGPKG_HAL_ARM_MX27 current ;
+ package -hardware CYGPKG_HAL_ARM_MX27_3STACK current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ;
+ package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ;
+ package -hardware CYGPKG_DEVS_ETH_FEC current ;
+ package -hardware CYGPKG_COMPRESS_ZLIB current ;
+ package -hardware CYGPKG_IO_FLASH current ;
+ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+ package -hardware CYGPKG_DEVS_MXC_SPI current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package CYGPKG_MEMALLOC current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FSL_SPI_VER_XX {
+ inferred_value 1
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
+ user_value 10
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ inferred_value 0x00040000
+};
+
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+ inferred_value 0xA0008000
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_component CYG_HAL_STARTUP {
+ user_value ROMRAM
+};
+
+cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+ inferred_value 1
+};
+
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+ user_value 1 "FSL 200904"
+};
--- /dev/null
+/*=============================================================================
+//
+// board_diag.c
+//
+// HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_arch.h> // basic machine info
+#include <cyg/hal/hal_intr.h> // interrupt macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_if.h> // Calling-if API
+#include <cyg/hal/drv_api.h> // driver API
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/fsl_board.h> // Platform specifics
+
+static void cyg_hal_plf_duart_init(void);
+extern void cyg_hal_plf_serial_init(void);
+
+void cyg_hal_plf_comms_init(void)
+{
+ static int initialized = 0;
+
+ if (initialized)
+ return;
+
+ initialized = 1;
+ cyg_hal_plf_duart_init();
+ cyg_hal_plf_serial_init();
+}
+
+//=============================================================================
+// ST16552 DUART driver
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// Only one external UART.
+#define CYG_DEV_SERIAL_BASE_A (BOARD_CS_UART_BASE + 0x00)
+
+//-----------------------------------------------------------------------------
+// Based on 3.6864 MHz xtal
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x18
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x0C
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x06
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x04
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x02
+#endif
+
+#ifndef CYG_DEV_SERIAL_BAUD_MSB
+#error Missing/incorrect serial baud rate defined - CDL error?
+#endif
+
+//-----------------------------------------------------------------------------
+// Define the serial registers. The board is equipped with a 16552
+// serial chip.
+
+#if defined (EXT_UART_x16)
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT16
+#define HAL_READ_UINT_UART HAL_READ_UINT16
+typedef cyg_uint16 uart_width;
+#elif defined (EXT_UART_x32)
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT32
+#define HAL_READ_UINT_UART HAL_READ_UINT32
+typedef cyg_uint32 uart_width;
+#else //_x8
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT8
+#define HAL_READ_UINT_UART HAL_READ_UINT8
+typedef cyg_uint8 uart_width;
+#endif
+
+#define CYG_DEV_SERIAL_RHR 0x00 // receiver buffer register, read, dlab = 0
+#define CYG_DEV_SERIAL_THR 0x00 // transmitter holding register, write, dlab = 0
+#define CYG_DEV_SERIAL_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IER 0x01 // interrupt enable register, read/write, dlab = 0
+#define CYG_DEV_SERIAL_DLM 0x01 // divisor latch (MS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IIR 0x02 // interrupt identification register, read, dlab = 0
+#define CYG_DEV_SERIAL_FCR 0x02 // fifo control register, write, dlab = 0
+#define CYG_DEV_SERIAL_AFR 0x02 // alternate function register, read/write, dlab = 1
+#define CYG_DEV_SERIAL_LCR 0x03 // line control register, read/write
+#define CYG_DEV_SERIAL_MCR 0x04
+#define CYG_DEV_SERIAL_MCR_A 0x04
+#define CYG_DEV_SERIAL_MCR_B 0x04
+#define CYG_DEV_SERIAL_LSR 0x05 // line status register, read
+#define CYG_DEV_SERIAL_MSR 0x06 // modem status register, read
+#define CYG_DEV_SERIAL_SCR 0x07 // scratch pad register
+
+// The interrupt enable register bits.
+#define SIO_IER_ERDAI 0x01 // enable received data available irq
+#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
+#define SIO_IER_ELSI 0x04 // enable receiver line status irq
+#define SIO_IER_EMSI 0x08 // enable modem status interrupt
+
+// The interrupt identification register bits.
+#define SIO_IIR_IP 0x01 // 0 if interrupt pending
+#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
+#define ISR_Tx 0x02
+#define ISR_Rx 0x04
+
+// The line status register bits.
+#define SIO_LSR_DR 0x01 // data ready
+#define SIO_LSR_OE 0x02 // overrun error
+#define SIO_LSR_PE 0x04 // parity error
+#define SIO_LSR_FE 0x08 // framing error
+#define SIO_LSR_BI 0x10 // break interrupt
+#define SIO_LSR_THRE 0x20 // transmitter holding register empty
+#define SIO_LSR_TEMT 0x40 // transmitter register empty
+#define SIO_LSR_ERR 0x80 // any error condition
+
+// The modem status register bits.
+#define SIO_MSR_DCTS 0x01 // delta clear to send
+#define SIO_MSR_DDSR 0x02 // delta data set ready
+#define SIO_MSR_TERI 0x04 // trailing edge ring indicator
+#define SIO_MSR_DDCD 0x08 // delta data carrier detect
+#define SIO_MSR_CTS 0x10 // clear to send
+#define SIO_MSR_DSR 0x20 // data set ready
+#define SIO_MSR_RI 0x40 // ring indicator
+#define SIO_MSR_DCD 0x80 // data carrier detect
+
+// The line control register bits.
+#define SIO_LCR_WLS0 0x01 // word length select bit 0
+#define SIO_LCR_WLS1 0x02 // word length select bit 1
+#define SIO_LCR_STB 0x04 // number of stop bits
+#define SIO_LCR_PEN 0x08 // parity enable
+#define SIO_LCR_EPS 0x10 // even parity select
+#define SIO_LCR_SP 0x20 // stick parity
+#define SIO_LCR_SB 0x40 // set break
+#define SIO_LCR_DLAB 0x80 // divisor latch access bit
+
+// The FIFO control register
+#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
+#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
+#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
+
+//-----------------------------------------------------------------------------
+
+typedef struct {
+ uart_width* base;
+ cyg_int32 msec_timeout;
+ int isr_vector;
+} channel_data_t;
+
+static channel_data_t channels[] = {
+#if CYGHWR_HAL_ARM_DUART_UARTA != 0
+ {(uart_width*)CYG_DEV_SERIAL_BASE_A, 1000, 0},
+#endif
+#if CYGHWR_HAL_ARM_DUART_UARTB != 0
+ {(uart_width*)CYG_DEV_SERIAL_BASE_B, 1000, 0}
+#endif
+};
+
+//-----------------------------------------------------------------------------
+
+static void init_duart_channel(channel_data_t* __ch_data)
+{
+ uart_width* base = __ch_data->base;
+ uart_width lcr;
+
+ // 8-1-no parity.
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR,
+ SIO_LCR_WLS0 | SIO_LCR_WLS1);
+
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ lcr |= SIO_LCR_DLAB;
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLL, CYG_DEV_SERIAL_BAUD_LSB);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLM, CYG_DEV_SERIAL_BAUD_MSB);
+ lcr &= ~SIO_LCR_DLAB;
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_FCR, 0x07); // Enable & clear FIFO
+}
+
+//#define x_debug_uart_log_buf
+#ifdef x_debug_uart_log_buf
+#define x_DIAG_BUFSIZE 2048
+static char __x_log_buf[x_DIAG_BUFSIZE];
+static int x_diag_bp = 0;
+#endif
+
+extern unsigned int g_board_type;
+
+void cyg_hal_plf_duart_putc(void* __ch_data, cyg_uint8 c)
+{
+ uart_width* base = ((channel_data_t*)__ch_data)->base;
+ uart_width lsr;
+
+#ifdef x_debug_uart_log_buf
+ __x_log_buf[x_diag_bp++] = c;
+#endif
+ CYGARC_HAL_SAVE_GP();
+
+ do {
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ } while ((lsr & SIO_LSR_THRE) == 0);
+
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_THR, c);
+
+ // Hang around until the character has been safely sent.
+ do {
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ } while ((lsr & SIO_LSR_THRE) == 0);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool cyg_hal_plf_duart_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+ uart_width* base = ((channel_data_t*)__ch_data)->base;
+ uart_width lsr, ch16;
+
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ if ((lsr & SIO_LSR_DR) == 0)
+ return false;
+
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_RHR, ch16);
+
+ *ch = (cyg_uint8) (ch16 & 0x00FF);
+
+ return true;
+}
+
+cyg_uint8 cyg_hal_plf_duart_getc(void* __ch_data)
+{
+ cyg_uint8 ch;
+
+ CYGARC_HAL_SAVE_GP();
+
+ while (!cyg_hal_plf_duart_getc_nonblock(__ch_data, &ch));
+
+ CYGARC_HAL_RESTORE_GP();
+ return ch;
+}
+
+static void cyg_hal_plf_duart_write(void* __ch_data, const cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while (__len-- > 0)
+ cyg_hal_plf_duart_putc(__ch_data, *__buf++);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static void cyg_hal_plf_duart_read(void* __ch_data, cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while (__len-- > 0)
+ *__buf++ = cyg_hal_plf_duart_getc(__ch_data);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool cyg_hal_plf_duart_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+ int delay_count;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_bool res;
+
+ CYGARC_HAL_SAVE_GP();
+
+ delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+ for (;;) {
+ res = cyg_hal_plf_duart_getc_nonblock(__ch_data, ch);
+ if (res || 0 == delay_count--)
+ break;
+
+ CYGACC_CALL_IF_DELAY_US(100);
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static int cyg_hal_plf_duart_control(void *__ch_data,
+ __comm_control_cmd_t __func, ...)
+{
+ static int irq_state = 0;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ uart_width ier;
+ int ret = 0;
+
+ CYGARC_HAL_SAVE_GP();
+
+ switch (__func) {
+ case __COMMCTL_IRQ_ENABLE:
+ HAL_INTERRUPT_UNMASK(chan->isr_vector);
+ HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ ier |= SIO_IER_ERDAI;
+ HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ irq_state = 1;
+ break;
+ case __COMMCTL_IRQ_DISABLE:
+ ret = irq_state;
+ irq_state = 0;
+ HAL_INTERRUPT_MASK(chan->isr_vector);
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ ier &= ~SIO_IER_ERDAI;
+ HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ break;
+ case __COMMCTL_DBG_ISR_VECTOR:
+ ret = chan->isr_vector;
+ break;
+ case __COMMCTL_SET_TIMEOUT:
+ {
+ va_list ap;
+
+ va_start(ap, __func);
+
+ ret = chan->msec_timeout;
+ chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+ va_end(ap);
+ }
+ break;
+ default:
+ break;
+ }
+ CYGARC_HAL_RESTORE_GP();
+ return ret;
+}
+
+static int cyg_hal_plf_duart_isr(void *__ch_data, int* __ctrlc,
+ CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ uart_width _iir;
+ int res = 0;
+ CYGARC_HAL_SAVE_GP();
+
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IIR, _iir);
+ _iir &= SIO_IIR_ID_MASK;
+
+ *__ctrlc = 0;
+ if ( ISR_Rx == _iir ) {
+ uart_width c, lsr;
+ cyg_uint8 c8;
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_LSR, lsr);
+ if (lsr & SIO_LSR_DR) {
+
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_RHR, c);
+
+ c8 = (cyg_uint8) (c & 0x00FF);
+
+ if (cyg_hal_is_break( &c8 , 1 ))
+ *__ctrlc = 1;
+ }
+
+ // Acknowledge the interrupt
+ HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+ res = CYG_ISR_HANDLED;
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static void cyg_hal_plf_duart_init(void)
+{
+ hal_virtual_comm_table_t* comm;
+ int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ int i;
+
+ // Init channels
+#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
+ for (i = 0; i < NUMOF(channels); i++) {
+ HAL_INTERRUPT_MASK(channels[i].isr_vector);
+ init_duart_channel(&channels[i]);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_duart_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_duart_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_duart_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_duart_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_duart_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_duart_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_duart_getc_timeout);
+ }
+
+ // Restore original console
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
+
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
+#define __BASE CMA101_DUARTA
+#define _INT CYGNUM_HAL_INTERRUPT_SERIAL_A
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1)
+#define __BASE CMA101_DUARTB
+#define _INT CYGNUM_HAL_INTERRUPT_SERIAL_B
+#endif
+
+#ifdef __BASE
+
+#ifdef CYGSEM_HAL_ROM_MONITOR
+#define CYG_HAL_STARTUP_ROM
+#define CYG_HAL_STARTUP_ROMRAM
+#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#endif
+
+#if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define HAL_DIAG_USES_HARDWARE
+#elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
+#define HAL_DIAG_USES_HARDWARE
+#elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+#define HAL_DIAG_USES_HARDWARE
+#endif
+
+static channel_data_t channel = {
+ (uart_width*) _BASE, 0, 0
+};
+
+#ifdef HAL_DIAG_USES_HARDWARE
+
+void hal_diag_init(void)
+{
+ static int init = 0;
+ char *msg = "\n\rARM eCos\n\r";
+ uart_width lcr;
+
+ if (init++) return;
+
+ init_duart_channel(&channel);
+
+ while (*msg) hal_diag_write_char(*msg++);
+}
+
+#ifdef DEBUG_DIAG
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define DIAG_BUFSIZE 32
+#else
+#define DIAG_BUFSIZE 2048
+#endif
+static char diag_buffer[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+
+void hal_diag_write_char(char c)
+{
+ uart_width lsr;
+
+ hal_diag_init();
+
+ cyg_hal_plf_duart_putc(&channel, c)
+
+#ifdef DEBUG_DIAG
+ diag_buffer[diag_bp++] = c;
+ if (diag_bp == DIAG_BUFSIZE) {
+ while (1) ;
+ diag_bp = 0;
+ }
+#endif
+}
+
+void hal_diag_read_char(char *c)
+{
+ *c = cyg_hal_plf_duart_getc(&channel);
+}
+
+#else // HAL_DIAG relies on GDB
+
+// Initialize diag port - assume GDB channel is already set up
+void hal_diag_init(void)
+{
+ if (0) init_duart_channel(&channel); // avoid warning
+}
+
+// Actually send character down the wire
+static void hal_diag_write_char_serial(char c)
+{
+ cyg_hal_plf_duart_putc(&channel, c);
+}
+
+static bool hal_diag_read_serial(char *c)
+{
+ long timeout = 1000000000; // A long time...
+
+ while (!cyg_hal_plf_duart_getc_nonblock(&channel, c))
+ if (0 == --timeout) return false;
+
+ return true;
+}
+
+void hal_diag_read_char(char *c)
+{
+ while (!hal_diag_read_serial(c)) ;
+}
+
+void hal_diag_write_char(char c)
+{
+ static char line[100];
+ static int pos = 0;
+
+ // No need to send CRs
+ if (c == '\r') return;
+
+ line[pos++] = c;
+
+ if (c == '\n' || pos == sizeof(line)) {
+ CYG_INTERRUPT_STATE old;
+
+ // Disable interrupts. This prevents GDB trying to interrupt us
+ // while we are in the middle of sending a packet. The serial
+ // receive interrupt will be seen when we re-enable interrupts
+ // later.
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+#else
+ HAL_DISABLE_INTERRUPTS(old);
+#endif
+
+ while (1) {
+ static char hex[] = "0123456789ABCDEF";
+ cyg_uint8 csum = 0;
+ int i;
+ char c1;
+
+ hal_diag_write_char_serial('$');
+ hal_diag_write_char_serial('O');
+ csum += 'O';
+ for (i = 0; i < pos; i++) {
+ char ch = line[i];
+ char h = hex[(ch>>4)&0xF];
+ char l = hex[ch&0xF];
+ hal_diag_write_char_serial(h);
+ hal_diag_write_char_serial(l);
+ csum += h;
+ csum += l;
+ }
+ hal_diag_write_char_serial('#');
+ hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
+ hal_diag_write_char_serial(hex[csum&0xF]);
+
+ // Wait for the ACK character '+' from GDB here and handle
+ // receiving a ^C instead. This is the reason for this clause
+ // being a loop.
+ if (!hal_diag_read_serial(&c1))
+ continue; // No response - try sending packet again
+
+ if ( c1 == '+' )
+ break; // a good acknowledge
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
+ if ( c1 == 3 ) {
+ // Ctrl-C: breakpoint.
+ cyg_hal_gdb_interrupt (__builtin_return_address(0));
+ break;
+ }
+#endif
+ // otherwise, loop round again
+ }
+
+ pos = 0;
+
+ // And re-enable interrupts
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+#else
+ HAL_RESTORE_INTERRUPTS(old);
+#endif
+
+ }
+}
+#endif
+
+#endif // __BASE
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
--- /dev/null
+//==========================================================================
+//
+// board_misc.c
+//
+// HAL misc board support code for the board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#include <redboot.h>
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h> // Interrupt names
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/fsl_board.h> // Platform specifics
+
+#include <cyg/infra/diag.h> // diag_printf
+
+// All the MM table layout is here:
+#include <cyg/hal/hal_mm.h>
+#include <cyg/io/mxc_spi.h>
+
+externC void* memset(void *, int, size_t);
+
+void hal_mmu_init(void)
+{
+ unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
+ unsigned long i;
+
+ /*
+ * Set the TTB register
+ */
+ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
+
+ /*
+ * Set the Domain Access Control Register
+ */
+ i = ARM_ACCESS_DACR_DEFAULT;
+ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+
+ /*
+ * First clear all TT entries - ie Set them to Faulting
+ */
+ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+
+ /* Actual Virtual Size Attributes Function */
+ /* Base Base MB cached? buffered? access permissions */
+ /* xxx00000 xxx00000 */
+ X_ARM_MMU_SECTION(0x000, 0xF00, 0x001, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Boot Rom */
+ X_ARM_MMU_SECTION(0x100, 0x100, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Internal Regsisters */
+ X_ARM_MMU_SECTION(0x800, 0x800, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CSI/ATA Regsisters */
+ X_ARM_MMU_SECTION(0xA00, 0x000, 0x080, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0xA00, 0xA00, 0x080, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0xA00, 0xA80, 0x080, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0xC00, 0xC00, 0x020, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Flash */
+ X_ARM_MMU_SECTION(0xD60, 0xD60, 0x020, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS5 for External I/0 */
+ X_ARM_MMU_SECTION(0xD80, 0xD80, 0x100, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* EMI control/PCMCIA */
+ X_ARM_MMU_SECTION(0xFFF, 0xFFF, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* VRAM */
+}
+
+//
+// Platform specific initialization
+//
+static void fec_gpio_init(void)
+{
+ unsigned long addr , val;
+
+ /* PF23 PF10*/
+ addr = SOC_GPIOF_BASE;
+ /* OCR2: AIN=0x00 */
+ HAL_READ_UINT32(addr+GPIO_OCR2, val);
+ val = val & (~(0x00000003<<(13)));
+ HAL_WRITE_UINT32(addr+GPIO_OCR2, val);
+
+ /* OCR1: DR */
+ HAL_READ_UINT32(addr+GPIO_OCR1, val);
+ val = val | ((0x00000003<<(20)));
+ HAL_WRITE_UINT32(addr+GPIO_OCR1, val);
+
+ /* DDR: OUTPUT */
+ HAL_READ_UINT32(addr+GPIO_DDIR, val);
+ val = val | (0x00000001<<(23)) | (1<<10);
+ HAL_WRITE_UINT32(addr+GPIO_DDIR, val);
+
+ /* GIUS: GPIO */
+ HAL_READ_UINT32(addr+GPIO_GIUS, val);
+ val = val | (0x00000001<<23) | (1<<10);
+ HAL_WRITE_UINT32(addr+GPIO_GIUS, val);
+
+ /* DR: DATA */
+ HAL_READ_UINT32(addr+GPIO_DR, val);
+ val = val & (~(1<<10));
+ HAL_WRITE_UINT32(addr+GPIO_DR, val);
+
+
+ /* PD16-0*/
+ addr = SOC_GPIOD_BASE;
+ /* PD16 OCR2: AIN=0x00 */
+ HAL_READ_UINT32(addr+GPIO_OCR2, val);
+ val = val & ~0x00000003;
+ HAL_WRITE_UINT32(addr+GPIO_OCR2, val);
+
+ /* PD9, 3-0 OCR1: AIN=0x00 */
+ HAL_READ_UINT32(addr+GPIO_OCR1, val);
+ val = val & ~(0x000C00FF);
+ HAL_WRITE_UINT32(addr+GPIO_OCR1, val);
+
+ /* PD15~10, P7~4 ICONFIGA1: AOUT=0x00 */
+ HAL_READ_UINT32(addr+GPIO_ICONFA1, val);
+ val = val & ~(0xFFF0FF00);
+ HAL_WRITE_UINT32(addr+GPIO_ICONFA1, val);
+
+ /* PD8 GPR: ALT */
+ HAL_READ_UINT32(addr+GPIO_GPR, val);
+ val = val | 0x00000100;
+ HAL_WRITE_UINT32(addr+GPIO_GPR, val);
+
+ /* DDR: OUTPUT */
+ HAL_READ_UINT32(addr+GPIO_DDIR, val);
+ val = (val & 0xFFFE0000) | 0x0001020F;
+ HAL_WRITE_UINT32(addr+GPIO_DDIR, val);
+
+ /* GIUS: GPIO */
+ HAL_READ_UINT32(addr+GPIO_GIUS, val);
+ val = (val & 0xFFFE0000) | 0x0001FEFF;
+ HAL_WRITE_UINT32(addr+GPIO_GIUS, val);
+
+ /* PB24: */
+ addr = SOC_GPIOB_BASE;
+
+ HAL_READ_UINT32(addr+GPIO_DDIR, val);
+ val = val | (1<<24);
+ HAL_WRITE_UINT32(addr+GPIO_DDIR, val);
+
+ HAL_READ_UINT32(addr+GPIO_OCR2, val);
+ val = val | (3<<16);
+ HAL_WRITE_UINT32(addr+GPIO_OCR2, val);
+
+ HAL_READ_UINT32(addr+GPIO_GIUS, val);
+ val = val | (1<<24);
+ HAL_WRITE_UINT32(addr+GPIO_GIUS, val);
+
+ HAL_READ_UINT32(addr+GPIO_DR, val);
+ val = val | (1<<24);
+ HAL_WRITE_UINT32(addr+GPIO_DR, val);
+}
+
+static void fec_power_init(void)
+{
+ unsigned long addr , val;
+
+ /* Turn on the power of PHY*/
+ val = pmic_reg(34, val, 0);
+ val |= (1<<6) | (1<< 10) | (1<<12);
+ pmic_reg(34, val, 1);
+
+ /* Wait until the power is stable*/
+ for(val = 0; val< 5000; val++)
+ hal_delay_us(5);
+
+ /*Issue the reset signal*/
+ addr = SOC_GPIOF_BASE;
+
+ HAL_READ_UINT32(addr+GPIO_DR, val);
+ val = val & (~(1<<10));
+ HAL_WRITE_UINT32(addr+GPIO_DR, val);
+
+ for(val = 0; val< 300; val++)
+ hal_delay_us(2);
+
+ HAL_READ_UINT32(addr+GPIO_DR, val);
+ val = val | (1<<10);
+ HAL_WRITE_UINT32(addr+GPIO_DR, val);
+
+ for(val = 0; val< 5000; val++)
+ hal_delay_us(5);
+}
+
+RedBoot_init(fec_power_init, 9000);
+
+//
+// Platform specific initialization
+//
+
+unsigned int g_clock_src;
+unsigned int g_board_type = BOARD_TYPE_UNKNOWN;
+
+void plf_hardware_init(void)
+{
+ unsigned long val = readl(SOC_CRM_CSCR);
+
+ if ((val & (1 << 16)) != 0) {
+ g_clock_src = FREQ_26MHZ;
+ } else {
+ g_clock_src = FREQ_32768HZ;
+ }
+
+ g_board_type = BOARD_TYPE_3STACK;
+
+ fec_gpio_init();
+}
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+typedef void code_fun(void);
+
+void board_program_new_stack(void *func)
+{
+ register CYG_ADDRESS stack_ptr asm("sp");
+ register CYG_ADDRESS old_stack asm("r4");
+ register code_fun *new_func asm("r0");
+ old_stack = stack_ptr;
+ stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
+ new_func = (code_fun*)func;
+ new_func();
+ stack_ptr = old_stack;
+}
+
+static void display_clock_src(void)
+{
+ if (g_clock_src == FREQ_26MHZ) {
+ diag_printf("Clock input: 26 MHz");
+ } else if (g_clock_src == FREQ_32768HZ) {
+ diag_printf("Clock input: 32KHz");
+ } else {
+ diag_printf("Unknown clock input source. Something is wrong!");
+ }
+}
+
+static void display_board_type(void)
+{
+ if (g_board_type == BOARD_TYPE_3STACK) {
+ diag_printf("\nBoard Type: 3-Stack\n");
+ } else {
+ diag_printf("\nBoard Type: Unknown val %d\n", g_board_type);
+ }
+}
+
+static void display_board_info(void)
+{
+ display_board_type();
+ display_clock_src();
+}
+
+RedBoot_init(display_board_info, RedBoot_INIT_LAST);
+// ------------------------------------------------------------------------
--- /dev/null
+//==========================================================================
+//
+// redboot_cmds.c
+//
+// Board [platform] specific RedBoot commands
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+#include <redboot.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/plf_mmap.h>
+#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <flash_config.h>
+
+#if (REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE)
+#error REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE
+#endif
+
+RedBoot_config_option("Board specifics",
+ brd_specs,
+ ALWAYS_ENABLED,
+ true,
+ CONFIG_INT,
+ 0
+ );
+#endif //CYGSEM_REDBOOT_FLASH_CONFIG
+
+static void runImg(int argc, char *argv[]);
+
+RedBoot_cmd("run",
+ "Run an image at a location with MMU off",
+ "[<virtual addr>]",
+ runImg
+ );
+
+void launchRunImg(unsigned long addr)
+{
+ asm volatile ("mov r1, r0;");
+ HAL_MMU_OFF();
+ asm volatile (
+ "mov r11, #0;"
+ "mov r12, #0;"
+ "mrs r10, cpsr;"
+ "bic r10, r10, #0xF0000000;"
+ "msr cpsr_f, r10;"
+ "mov pc, r1"
+ );
+}
+
+extern unsigned long entry_address;
+
+static void runImg(int argc,char *argv[])
+{
+ unsigned int virt_addr, phys_addr;
+
+ // Default physical entry point for Symbian
+ if (entry_address == 0xFFFFFFFF)
+ virt_addr = 0x800000;
+ else
+ virt_addr = entry_address;
+
+ if (!scan_opts(argc,argv,1,0,0,(void*)&virt_addr,
+ OPTION_ARG_TYPE_NUM, "virtual address"))
+ return;
+
+ if (entry_address != 0xFFFFFFFF)
+ diag_printf("load entry_address=0x%lx\n", entry_address);
+ HAL_VIRT_TO_PHYS_ADDRESS(virt_addr, phys_addr);
+
+ diag_printf("virt_addr=0x%x\n",virt_addr);
+ diag_printf("phys_addr=0x%x\n",phys_addr);
+
+ launchRunImg(phys_addr);
+}
+
+#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYG_HAL_STARTUP_ROMRAM)
+
+RedBoot_cmd("romupdate",
+ "Update Redboot with currently running image",
+ "",
+ romupdate
+ );
+
+extern int flash_program(void *_addr, void *_data, int len, void **err_addr);
+extern int flash_erase(void *addr, int len, void **err_addr);
+extern char *flash_errmsg(int err);
+extern unsigned char *ram_end; //ram end is where the redboot starts FIXME: use PC value
+
+#ifdef CYGPKG_IO_FLASH
+void romupdate(int argc, char *argv[])
+{
+ void *err_addr, *base_addr;
+ int stat;
+
+ if (IS_FIS_FROM_NAND()) {
+ base_addr = (void*)0;
+ diag_printf("Updating ROM in NAND flash\n");
+ } else if (IS_FIS_FROM_NOR()) {
+ base_addr = (void*)BOARD_FLASH_START;
+ diag_printf("Updating ROM in NOR flash\n");
+ } else {
+ diag_printf("romupdate not supported\n");
+ diag_printf("Use \"factive [NOR|NAND]\" to select either NOR or NAND flash\n");
+ return;
+ }
+ // Erase area to be programmed
+ if ((stat = flash_erase((void *)base_addr,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ (void **)&err_addr)) != 0) {
+ diag_printf("Can't erase region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ return;
+ }
+ // Now program it
+ if ((stat = flash_program((void *)base_addr, (void *)ram_end,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ (void **)&err_addr)) != 0) {
+ diag_printf("Can't program region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ }
+}
+RedBoot_cmd("factive",
+ "Enable one flash media for Redboot",
+ "[NOR | NAND]",
+ factive
+ );
+
+void factive(int argc, char *argv[])
+{
+ unsigned long phys_addr;
+
+ if (argc != 2) {
+ diag_printf("Invalid factive cmd\n");
+ return;
+ }
+
+ if (strcasecmp(argv[1], "NOR") == 0) {
+#ifndef MXCFLASH_SELECT_NOR
+ diag_printf("Not supported\n");
+ return;
+#else
+ MXC_ASSERT_NOR_BOOT();
+#endif
+ } else if (strcasecmp(argv[1], "NAND") == 0) {
+#ifndef MXCFLASH_SELECT_NAND
+ diag_printf("Not supported\n");
+ return;
+#else
+ MXC_ASSERT_NAND_BOOT();
+#endif
+ } else {
+ diag_printf("Invalid command: %s\n", argv[1]);
+ return;
+ }
+ HAL_VIRT_TO_PHYS_ADDRESS(ram_end, phys_addr);
+
+ launchRunImg(phys_addr);
+}
+#endif //CYGPKG_IO_FLASH
+#endif /* CYG_HAL_STARTUP_ROMRAM */
--- /dev/null
+# ====================================================================
+#
+# hal_arm_board.cdl
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+
+cdl_package CYGPKG_HAL_ARM_MX31_3STACK {
+ display "Freescale board"
+ parent CYGPKG_HAL_ARM_MX31
+ hardware
+ include_dir cyg/hal
+ define_header hal_arm_board.h
+ description "
+ This HAL platform package provides generic
+ support for the Freescale MX31 3-Stack Board."
+
+ compile board_misc.c board_diag.c
+ implements CYGINT_HAL_DEBUG_GDB_STUBS
+ implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+ implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+
+ #implements CYGHWR_HAL_ARM_DUART_UARTB
+ implements CYGHWR_HAL_ARM_SOC_UART1
+ #implements CYGHWR_HAL_ARM_SOC_UART2
+ #implements CYGHWR_HAL_ARM_SOC_UART3
+
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_soc.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_board.h>"
+ puts $::cdl_header "#define HAL_PLATFORM_CPU \"i.MX\""
+ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Freescale\""
+ puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 1511"
+ puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK board_program_new_stack"
+ }
+
+ cdl_component CYG_HAL_STARTUP {
+ display "Startup type"
+ flavor data
+ default_value {"ROM"}
+ legal_values {"RAM" "ROM" "ROMRAM"}
+ no_define
+ define -file system.h CYG_HAL_STARTUP
+ description "
+ When targetting the eval board it is possible to build
+ the system for either RAM bootstrap or ROM bootstrap(s). Select
+ 'ram' when building programs to load into RAM using eCos GDB
+ stubs. Select 'rom' when building a stand-alone application
+ which will be put into ROM, or for the special case of
+ building the eCos GDB stubs themselves. Using ROMRAM will allow
+ the program to exist in ROM, but be copied to RAM during startup."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_DUART_UARTA {
+ display "ST16552 UARTA available as diagnostic/debug channel"
+ description "
+ The board has a ST16552 DUART chip. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_DUART_UARTB {
+ display "ST16552 UARTB available as diagnostic/debug channel"
+ description "
+ The board has a ST16552 DUART chip. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ display "Diagnostic serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the console port.
+ Note: this should match the value chosen for the GDB port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ display "GDB serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the GDB port.
+ Note: this should match the value chosen for the console port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the board"
+ flavor data
+ calculated 6
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ The board has three serial ports. This option
+ chooses which port will be used to connect to a host
+ running GDB."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+ display "Default console channel."
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ calculated 0
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Console serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ description "
+ The board has only three serial ports. This option
+ chooses which port will be used for console output."
+ }
+
+ cdl_component CYGBLD_GLOBAL_OPTIONS {
+ display "Global build options"
+ flavor none
+ no_define
+ description "
+ Global build options including control over
+ compiler flags, linker flags and choice of toolchain."
+
+
+ parent CYGPKG_NONE
+
+ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ display "Global command prefix"
+ flavor data
+ no_define
+ default_value { "arm-none-eabi" }
+ description "
+ This option specifies the command prefix used when
+ invoking the build tools."
+ }
+
+ cdl_option CYGBLD_GLOBAL_CFLAGS {
+ display "Global compiler flags"
+ flavor data
+ no_define
+ default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ description "
+ This option controls the global compiler flags which are used to
+ compile all packages by default. Individual packages may define
+ options which override these global flags."
+ }
+
+ cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ display "Global linker flags"
+ flavor data
+ no_define
+ default_value { "-Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" }
+ description "
+ This option controls the global linker flags. Individual
+ packages may define options which override these global flags."
+ }
+
+ cdl_option CYGBLD_BUILD_GDB_STUBS {
+ display "Build GDB stub ROM image"
+ default_value 0
+ requires { CYG_HAL_STARTUP == "ROM" }
+ requires CYGSEM_HAL_ROM_MONITOR
+ requires CYGBLD_BUILD_COMMON_GDB_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ no_define
+ description "
+ This option enables the building of the GDB stubs for the
+ board. The common HAL controls takes care of most of the
+ build process, but the final conversion from ELF image to
+ binary data is handled by the platform CDL, allowing
+ relocation of the data if necessary."
+
+ make -priority 320 {
+ <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
+ $(OBJCOPY) --remove-section=.fixed_vectors -O binary $< $@
+ }
+ }
+ }
+
+ cdl_component CYGPKG_HAL_ARM_BOARD_OPTIONS {
+ display "Freescale MXC Board build options"
+ flavor none
+ no_define
+ description "
+ Package specific build options including control over
+ compiler flags used only in building this package,
+ and details of which tests are built."
+
+ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the board HAL. These flags are used in addition
+ to the set of global flags."
+ }
+
+ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_REMOVE {
+ display "Suppressed compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the board HAL. These flags are removed from
+ the set of global flags if present."
+ }
+
+ }
+
+ cdl_component CYGHWR_MEMORY_LAYOUT {
+ display "Memory layout"
+ flavor data
+ no_define
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_board_ram" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" :
+ "arm_board_rom" }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ display "Memory layout linker script fragment"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.ldi>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.ldi>" :
+ "<pkgconf/mlt_arm_board_rom.ldi>" }
+ }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ display "Memory layout header file"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_H
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.h>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.h>" :
+ "<pkgconf/mlt_arm_board_rom.h>" }
+ }
+ }
+
+ cdl_option CYGSEM_HAL_ROM_MONITOR {
+ display "Behave as a ROM monitor"
+ flavor bool
+ default_value 0
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+ description "
+ Enable this option if this program is to be used as a ROM monitor,
+ i.e. applications will be loaded into RAM on the board, and this
+ ROM monitor may process exceptions or interrupts generated from the
+ application. This enables features such as utilizing a separate
+ interrupt stack when exceptions are generated."
+ }
+
+ cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ display "Work with a ROM monitor"
+ flavor booldata
+ legal_values { "Generic" "GDB_stubs" }
+ default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "RAM" }
+ description "
+ Support can be enabled for different varieties of ROM monitor.
+ This support changes various eCos semantics such as the encoding
+ of diagnostic output, or the overriding of hardware interrupt
+ vectors.
+ Firstly there is \"Generic\" support which prevents the HAL
+ from overriding the hardware vectors that it does not use, to
+ instead allow an installed ROM monitor to handle them. This is
+ the most basic support which is likely to be common to most
+ implementations of ROM monitor.
+ \"GDB_stubs\" provides support when GDB stubs are included in
+ the ROM monitor or boot ROM."
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ display "Redboot HAL options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+ description "
+ This option lists the target's requirements for a valid Redboot
+ configuration."
+
+ compile -library=libextras.a redboot_cmds.c
+
+ cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ display "Build Redboot ROM binary image"
+ active_if CYGBLD_BUILD_REDBOOT
+ default_value 1
+ no_define
+ description "This option enables the conversion of the Redboot ELF
+ image to a binary image suitable for ROM programming."
+
+ make -priority 325 {
+ <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+ $(OBJCOPY) -O binary $< $@
+ }
+ }
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_BOARD_OPTIONS {
+ display "Redboot HAL variant options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+
+ # RedBoot details
+ requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x80008000 }
+ define_proc {
+ puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00"
+ }
+ }
+}
--- /dev/null
+#ifndef CYGONCE_FSL_BOARD_H
+#define CYGONCE_FSL_BOARD_H
+
+//=============================================================================
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+
+#define PMIC_SPI_BASE CSPI2_BASE_ADDR
+#define PMIC_SPI_CHIP_SELECT_NO SPI_CTRL_CS2
+
+#define PBC_BASE CS5_BASE_ADDR /* Peripheral Bus Controller */
+#define PBC_LED_CTRL (PBC_BASE + 0x20000)
+#define PBC_SB_STAT (PBC_BASE + 0x20008)
+#define PBC_ID_AAAA (PBC_BASE + 0x20040)
+#define PBC_ID_5555 (PBC_BASE + 0x20048)
+#define PBC_VERSION (PBC_BASE + 0x20050)
+#define PBC_ID_CAFE (PBC_BASE + 0x20058)
+#define PBC_INT_STAT (PBC_BASE + 0x20010)
+#define PBC_INT_MASK (PBC_BASE + 0x20038)
+#define PBC_INT_REST (PBC_BASE + 0x20020)
+#define PBC_SW_RESET (PBC_BASE + 0x20060)
+#define BOARD_CS_LAN_BASE (PBC_BASE + 0x300)
+#define BOARD_CS_UART_BASE (PBC_BASE + 0x8000)
+
+#define REDBOOT_IMAGE_SIZE 0x40000
+
+#define EXT_UART_x16
+/* MX31 ADS SDRAM is from 0x80000000, 128M */
+#define SDRAM_BASE_ADDR CSD0_BASE_ADDR
+#define SDRAM_SIZE 0x08000000
+#define RAM_BANK0_BASE SDRAM_BASE_ADDR
+
+#define LED_MAX_NUM 8
+#define LED_IS_ON(n) ((readw(PBC_LED_CTRL) & (1<<(n))) != 0)
+#define TURN_LED_ON(n) writew((readw(PBC_LED_CTRL)|(1<<(n))), PBC_LED_CTRL)
+#define TURN_LED_OFF(n) writew((readw(PBC_LED_CTRL)&(~(1<<(n)))), PBC_LED_CTRL)
+
+#define BOARD_DEBUG_LED(n) \
+ CYG_MACRO_START \
+ if (n >= 0 && n < LED_MAX_NUM) { \
+ if (LED_IS_ON(n)) \
+ TURN_LED_OFF(n); \
+ else \
+ TURN_LED_ON(n); \
+ } \
+ CYG_MACRO_END
+
+#endif /* CYGONCE_FSL_BOARD_H */
--- /dev/null
+#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
+#define CYGONCE_HAL_PLATFORM_SETUP_H
+
+//=============================================================================
+//
+// hal_platform_setup.h
+//
+// Platform specific support for HAL (assembly code)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <pkgconf/system.h> // System-wide configuration info
+#include CYGBLD_HAL_VARIANT_H // Variant specific configuration
+#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
+#include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
+#include <cyg/hal/hal_mmu.h> // MMU definitions
+#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+
+//#define BOOT_FROM_MMC
+
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1 _platform_setup1
+#if defined(BOOT_FROM_MMC)
+#define PLATFORM_PREAMBLE flash_header
+#endif
+#define CYGHWR_HAL_ARM_HAS_MMU
+
+#ifdef CYG_HAL_STARTUP_ROMRAM
+#define CYGSEM_HAL_ROM_RESET_USES_JUMP
+#endif
+
+//#define ARM_399MHZ
+#define ARM_532MHZ
+
+//#define NFC_2K_BI_SWAP
+#define SDRAM_FULL_PAGE_BIT 0x100
+#define SDRAM_FULL_PAGE_MODE 0x37
+#define SDRAM_BURST_MODE 0x33
+
+#define MMC_BLK_LEN 0x200
+#define MMC_START_ADDR 0x0
+#define MMC_LOAD_SIZE 0x30000
+#define CYGHWR_HAL_ROM_VADDR 0x0
+
+#if 0
+#define UNALIGNED_ACCESS_ENABLE
+#define SET_T_BIT_DISABLE
+#define BRANCH_PREDICTION_ENABLE
+#endif
+
+//#define TURN_OFF_IMPRECISE_ABORT
+
+ .macro flash_header
+ b 1f
+ //Start code from offset 1K, gap left for MBR
+
+ .org 0x400
+ .long 0
+ .long 0
+ MMC_SDHC1_BASE_ADDR_W: .word MMC_SDHC1_BASE_ADDR
+ ESDHC_INTERRUPT_ENABLE_W: .word ESDHC_INTERRUPT_ENABLE
+ ESDHC_CLEAR_INTERRUPT_W: .word ESDHC_CLEAR_INTERRUPT
+ MXC_REDBOOT_ROM_ST_ADDR: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
+ REDBOOT_RESET_VECTOR: .word reset_vector
+1:
+ /* Check if booting from IRAM for MMC boot */
+ mov r0, #SDRAM_BASE_ADDR
+ cmp pc, r0
+ bhs 100f
+ setup_sdram ddr X32 DDR 0
+ mmcsd_read
+ mov r12, #MMC_BOOT
+100:
+ ldr r0, REDBOOT_RESET_VECTOR
+ mov pc, r0
+
+
+ .endm
+
+ .macro mmcsd_read
+ //Configure interface block and number of blocks 1 block and size is 512 Bytes
+ mov r2, #MMC_BLK_LEN
+ ldr r3, MMC_SDHC1_BASE_ADDR_W
+ str r2, [r3, #ESDHC_REG_BLK_LEN]
+ mov r2, #1
+ str r2, [r3, #ESDHC_REG_NOB]
+ //set block size and number of blocks of card
+ mov r1, #MMC_START_ADDR
+ mov r2, #MMC_BLK_LEN
+ sub r10, r1, r2
+ ldr r11, MXC_REDBOOT_ROM_ST_ADDR
+ mov r12, #MMC_LOAD_SIZE
+ add r12, r11, r12
+
+ //set read data length, Comfigure command CMD16 for single block read
+ mov r0, #MMC_BLK_LEN
+ mov r1, #0x10
+ mov r2, #0x1
+ send_cmd_wait_resp
+
+read_a_blk:
+ //set read data address
+ //CMD17 data_present Y
+ mov r2, #MMC_BLK_LEN
+ add r10, r10, r2
+ mov r0, r10
+ mov r1, #0x11
+ mov r2, #0x9
+ send_cmd_wait_resp
+ mov r5, #MMC_BLK_LEN
+ add r5, r11, r5
+
+ //enable interrupt
+ ldr r4, ESDHC_INTERRUPT_ENABLE_W
+ str r4, [r3, #ESDHC_REG_INT_STATUS_ENABLE]
+read_from_buffer:
+ ldr r4, [r3, #ESDHC_REG_INT_STATUS]
+ mov r2, #0x80 //ESDHC_STATUS_BUF_READ_RDY_MSK
+ ands r4, r4, r2
+ beq read_from_buffer
+
+four_times: //transfer data from SDHC buffer to ddr(4 words once)
+ ldr r4, [r3, #ESDHC_REG_BUFFER_DATA]
+ str r4, [r11]
+ add r11, r11, #0x4
+ ldr r4, [r3, #ESDHC_REG_BUFFER_DATA]
+ str r4, [r11]
+ add r11, r11, #0x4
+ ldr r4, [r3, #ESDHC_REG_BUFFER_DATA]
+ str r4, [r11]
+ add r11, r11, #0x4
+ ldr r4, [r3, #ESDHC_REG_BUFFER_DATA]
+ str r4, [r11]
+ add r11, r11, #0x4
+ cmp r11, r5
+ blo read_from_buffer
+
+check_tran_done: //check if the transfer is over
+ ldr r4, [r3, #ESDHC_REG_INT_STATUS]
+ mov r2, #0x800 //ESDHC_STATUS_TRANSFER_COMPLETE_MSK
+ ands r2, r4, r2
+ beq check_tran_done
+ ands r2, r2, #0x8
+ bne check_tran_done
+ cmp r11, r12
+ blo read_a_blk
+ .endm
+
+ //r0~r2 are reserved
+ .macro send_cmd_wait_resp
+ //start clk
+ ldr r3, MMC_SDHC1_BASE_ADDR_W
+ mov r4, #0x2
+ str r4, [r3, #ESDHC_REG_CLK]
+
+ //wait until the clk has started
+1:
+ ldr r4, [r3, #ESDHC_REG_INT_STATUS]
+ mov r5, #0x100
+ ands r4, r4, r5
+ beq 1b
+
+ //Clear Interrupt status register
+ ldr r4, ESDHC_CLEAR_INTERRUPT_W
+ str r4, [r3, #ESDHC_REG_INT_STATUS]
+ /* Enable Interrupt */
+ ldr r4, [r3, #ESDHC_REG_INT_STATUS_ENABLE]
+ ldr r5, ESDHC_INTERRUPT_ENABLE_W
+ orr r4, r4, r5
+ str r4, [r3, #ESDHC_REG_INT_STATUS_ENABLE]
+
+ /* Write Command Argument in Command Argument Register */
+ str r1, [r3, #ESDHC_REG_COMMAND]
+ str r0, [r3, #ESDHC_REG_COMMAND_TRANS_TYPE]
+ str r2, [r3, #ESDHC_REG_COMMAND_DAT_CONT]
+
+2: //wait for responds
+ mov r0, #0
+ mov r1, #0x1000
+3:
+ add r0,r0,#1
+ cmp r0,r1
+ bne 3b
+
+ ldr r0, [r3, #ESDHC_REG_INT_STATUS]
+ mov r1, #0x2000
+ ands r1, r0, r1
+ beq 2b
+
+ //mask all int
+ mov r4, #0
+ str r4, [r3, #ESDHC_REG_INT_STATUS_ENABLE]
+ .endm
+
+// This macro represents the initial startup code for the platform
+// r11 is reserved to contain chip rev info in this file
+ .macro _platform_setup1
+FSL_BOARD_SETUP_START:
+/*
+ * ARM1136 init
+ * - invalidate I/D cache/TLB and drain write buffer;
+ * - invalidate L2 cache
+ * - unaligned access
+ * - branch predictions
+ */
+#ifdef TURN_OFF_IMPRECISE_ABORT
+ mrs r0, cpsr
+ bic r0, r0, #0x100
+ msr cpsr, r0
+#endif
+
+ mov r0, #0
+ mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
+ mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+ mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
+
+ /* Also setup the Peripheral Port Remap register inside the core */
+ ldr r0, ARM_PPMRR /* start from AIPS 2GB region */
+ mcr p15, 0, r0, c15, c2, 4
+
+ /* Reload data from spare area to 0x400 of main area if booting from NAND */
+ mov r0, #NFC_BASE
+ add r1, r0, #0x400
+ cmp pc, r0
+ blo 1f
+ cmp pc, r1
+ bhi 1f
+#ifdef NFC_2K_BI_SWAP
+ ldr r3, [r0, #0x7D0] // load word at addr 464 of last 512 RAM buffer
+ and r3, r3, #0xFFFFFF00 // mask off the LSB
+ ldr r4, [r0, #0x834] // load word at addr 4 of the 3rd spare area buffer
+ mov r4, r4, lsr #8 // shift it to get the byte at addr 5
+ and r4, r4, #0xFF // throw away upper 3 bytes
+ add r3, r4, r3 // construct the word
+ str r3, [r0, #0x7D0] // write back
+#endif
+
+1:
+ /*** L2 Cache setup/invalidation/disable ***/
+ /* Disable L2 cache first */
+ mov r0, #L2CC_BASE_ADDR
+ ldr r2, [r0, #L2_CACHE_CTL_REG]
+ bic r2, r2, #0x1
+ str r2, [r0, #L2_CACHE_CTL_REG]
+ /*
+ * Configure L2 Cache:
+ * - 128k size(16k way)
+ * - 8-way associativity
+ * - 0 ws TAG/VALID/DIRTY
+ * - 4 ws DATA R/W
+ */
+ ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
+ and r1, r1, #0xFE000000
+ ldr r2, L2CACHE_PARAM
+ orr r1, r1, r2
+ str r1, [r0, #L2_CACHE_AUX_CTL_REG]
+
+ /* Invalidate L2 */
+ mov r1, #0x000000FF
+ str r1, [r0, #L2_CACHE_INV_WAY_REG]
+L2_loop:
+ /* Poll Invalidate By Way register */
+ ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
+ cmp r2, #0
+ bne L2_loop
+ /*** End of L2 operations ***/
+
+ mov r0, #SDRAM_NON_FLASH_BOOT
+ ldr r1, AVIC_VECTOR0_ADDR_W
+ str r0, [r1] // for checking boot source from nand or sdram
+/*
+ * End of ARM1136 init
+ */
+init_spba_start:
+ init_spba
+init_aips_start:
+ init_aips
+init_max_start:
+ init_max
+init_m3if_start:
+ init_m3if
+
+ ldr r11, =CHIP_REV_1_0
+ ldr r0, IIM_SREV_REG_VAL
+ ldr r1, [r0, #0x0]
+ cmp r1, #0x0
+ ldrne r11, =CHIP_REV_1_1
+ init_drive_strength
+
+ /* If SDRAM has been setup, bypass clock/WEIM setup */
+ cmp r12, #MMC_BOOT
+ ldreq r1, AVIC_VECTOR0_ADDR_W
+ streq r12, [r1]
+ beq init_cs5_start
+
+ cmp pc, #SDRAM_BASE_ADDR
+ blo init_clock_start
+ cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
+ blo HWInitialise_skip_SDRAM_setup
+
+ mov r0, #NOR_FLASH_BOOT
+ ldr r1, AVIC_VECTOR0_ADDR_W
+ str r0, [r1]
+
+init_cs5_start:
+ init_cs5
+
+init_clock_start:
+ init_clock
+
+ cmp r12, #MMC_BOOT
+ beq HWInitialise_skip_SDRAM_setup
+
+ /* Based on chip rev, setup params for SDRAM controller */
+ ldr r10, =0
+ mov r4, #SDRAM_BURST_MODE
+
+init_sdram_start:
+#ifndef BOOT_FROM_MMC
+ /* Assuming DDR memory first */
+ setup_sdram ddr X32 DDR 0
+#endif
+
+HWInitialise_skip_SDRAM_setup:
+
+ mov r0, #NFC_BASE
+ add r2, r0, #0x800 // 2K window
+ cmp pc, r0
+ blo Normal_Boot_Continue
+ cmp pc, r2
+ bhi Normal_Boot_Continue
+NAND_Boot_Start:
+ /* Copy image from flash to SDRAM first */
+ ldr r1, MXC_REDBOOT_ROM_START
+
+1: ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ blo 1b
+ /* Jump to SDRAM */
+ ldr r1, CONST_0x0FFF
+ and r0, pc, r1 /* offset of pc */
+ ldr r1, MXC_REDBOOT_ROM_START
+ add r1, r1, #0x10
+ add pc, r0, r1
+ nop
+ nop
+ nop
+ nop
+NAND_Copy_Main:
+ // Check if x16/2kb page
+ ldr r7, CCM_BASE_ADDR_W
+ ldr r7, [r7, #0xC]
+ ands r7, r7, #(1 << 30)
+
+ mov r0, #NAND_FLASH_BOOT
+ ldr r1, AVIC_VECTOR0_ADDR_W
+ str r0, [r1]
+ mov r0, #MXCFIS_NAND
+ ldr r1, AVIC_VECTOR1_ADDR_W
+ str r0, [r1]
+
+ mov r0, #NFC_BASE; //r0: nfc base. Reloaded after each page copying
+ mov r1, #0x800 //r1: starting flash addr to be copied. Updated constantly
+ add r2, r0, #0x800 //r2: end of 3rd RAM buf. Doesn't change
+ addeq r2, r0, #0x200 //r2: end of 1st RAM buf. Doesn't change
+ add r12, r0, #0xE00 //r12: NFC register base. Doesn't change
+ ldr r11, MXC_REDBOOT_ROM_START
+ add r13, r11, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
+ add r11, r11, r1 //r11: starting SDRAM address for copying. Updated constantly
+
+ //unlock internal buffer
+ mov r3, #0x2
+ strh r3, [r12, #0xA]
+
+Nfc_Read_Page:
+// NFC_CMD_INPUT(FLASH_Read_Mode1);
+ mov r3, #0x0
+ nfc_cmd_input
+
+ // Check if x16/2kb page
+ ldr r7, CCM_BASE_ADDR_W
+ ldr r7, [r7, #0xC]
+ ands r7, r7, #(1 << 30)
+ bne nfc_addr_ops_2kb
+// start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
+ mov r3, r1
+ do_addr_input //1st addr cycle
+ mov r3, r1, lsr #9
+ do_addr_input //2nd addr cycle
+ mov r3, r1, lsr #17
+ do_addr_input //3rd addr cycle
+ mov r3, r1, lsr #25
+ do_addr_input //4th addr cycle
+ b end_of_nfc_addr_ops
+
+nfc_addr_ops_2kb:
+// start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
+ mov r3, #0
+ do_addr_input //1st addr cycle
+ mov r3, #0
+ do_addr_input //2nd addr cycle
+ mov r3, r1, lsr #11
+ do_addr_input //3rd addr cycle
+ mov r3, r1, lsr #19
+ do_addr_input //4th addr cycle
+ mov r3, r1, lsr #27
+ do_addr_input //5th addr cycle
+
+// NFC_CMD_INPUT(FLASH_Read_Mode1_2K);
+ mov r3, #0x30
+ nfc_cmd_input
+
+end_of_nfc_addr_ops:
+// NFC_DATA_OUTPUT(buf, FDO_PAGE_SPARE_VAL);
+// writew(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN,
+// NAND_FLASH_CONFIG1_REG);
+ mov r8, #0
+ bl nfc_data_output
+ bl do_wait_op_done
+ // Check if x16/2kb page
+ ldr r7, CCM_BASE_ADDR_W
+ ldr r7, [r7, #0xC]
+ ands r7, r7, #(1 << 30)
+ beq nfc_addr_data_output_done_512
+
+// For 2K page - 2nd 512
+ mov r8, #1
+ bl nfc_data_output
+ bl do_wait_op_done
+
+// 3rd 512
+ mov r8, #2
+ bl nfc_data_output
+ bl do_wait_op_done
+
+// 4th 512
+ mov r8, #3
+ bl nfc_data_output
+ bl do_wait_op_done
+// end of 4th
+#ifdef NFC_2K_BI_SWAP
+ ldr r3, [r0, #0x7D0] // load word at addr 464 of last 512 RAM buffer
+ and r3, r3, #0xFFFFFF00 // mask off the LSB
+ ldr r4, [r0, #0x834] // load word at addr 4 of the 3rd spare area buffer
+ mov r4, r4, lsr #8 // shift it to get the byte at addr 5
+ and r4, r4, #0xFF // throw away upper 3 bytes
+ add r3, r4, r3 // construct the word
+ str r3, [r0, #0x7D0] // write back
+#endif
+ // check for bad block
+ mov r3, r1, lsl #(32-17) // get rid of block number
+ cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
+ b nfc_addr_data_output_done
+
+nfc_addr_data_output_done_512:
+ // check for bad block
+ mov r3, r1, lsl #(32-5-9) // get rid of block number
+ cmp r3, #(512 << (32-5-9)) // check if not page 0 or 1
+
+nfc_addr_data_output_done:
+ bhi Copy_Good_Blk
+ add r4, r0, #0x800 //r3 -> spare area buf 0
+ ldrh r4, [r4, #0x4]
+ and r4, r4, #0xFF00
+ cmp r4, #0xFF00
+ beq Copy_Good_Blk
+ // really sucks. Bad block!!!!
+ cmp r3, #0x0
+ beq Skip_bad_block
+ // even suckier since we already read the first page!
+ // Check if x16/2kb page
+ ldr r7, CCM_BASE_ADDR_W
+ ldr r7, [r7, #0xC]
+ ands r7, r7, #(1 << 30)
+
+ subeq r11, r11, #512 //rewind 1 page for the sdram pointer
+ subeq r1, r1, #512 //rewind 1 page for the flash pointer
+
+ // for 2k page
+ subne r11, r11, #0x800 //rewind 1 page for the sdram pointer
+ subne r1, r1, #0x800 //rewind 1 page for the flash pointer
+
+Skip_bad_block:
+ // Check if x16/2kb page
+ ldr r7, CCM_BASE_ADDR_W
+ ldr r7, [r7, #0xC]
+ ands r7, r7, #(1 << 30)
+
+ addeq r1, r1, #(32*512)
+ addne r1, r1, #(64*2048)
+
+ b Nfc_Read_Page
+Copy_Good_Blk:
+ //copying page
+1: ldmia r0!, {r3-r10}
+ stmia r11!, {r3-r10}
+ cmp r0, r2
+ blo 1b
+ cmp r11, r13
+ bge NAND_Copy_Main_done
+ // Check if x16/2kb page
+ ldr r7, CCM_BASE_ADDR_W
+ ldr r7, [r7, #0xC]
+ ands r7, r7, #(1 << 30)
+ addeq r1, r1, #0x200
+ addne r1, r1, #0x800
+ mov r0, #NFC_BASE
+ b Nfc_Read_Page
+
+NAND_Copy_Main_done:
+
+Normal_Boot_Continue:
+
+#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
+ /* Copy image from flash to SDRAM first */
+ ldr r0, =0xFFFFF000
+ and r0, r0, pc
+ ldr r1, MXC_REDBOOT_ROM_START
+ cmp r0, r1
+ beq HWInitialise_skip_SDRAM_copy
+
+ add r2, r0, #REDBOOT_IMAGE_SIZE
+
+1: ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ ble 1b
+ /* Jump to SDRAM */
+ ldr r1, =0xFFFF
+ and r0, pc, r1 /* offset of pc */
+ ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
+ add pc, r0, r1
+ nop
+ nop
+ nop
+ nop
+#endif /* CYG_HAL_STARTUP_ROMRAM */
+
+HWInitialise_skip_SDRAM_copy:
+
+NAND_ClockSetup:
+
+/*
+ * Note:
+ * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
+ */
+
+STACK_Setup:
+ // Set up a stack [for calling C code]
+ ldr r1, =__startup_stack
+ ldr r2, =RAM_BANK0_BASE
+ orr sp, r1, r2
+
+ // Create MMU tables
+ bl hal_mmu_init
+
+ // Enable MMU
+ ldr r2, =10f
+ mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
+ orr r1, r1, #7 // enable MMU bit
+ orr r1, r1, #0x800 // enable z bit
+ mcr MMU_CP, 0, r1, MMU_Control, c0
+ mov pc,r2 /* Change address spaces */
+ nop
+ nop
+ nop
+10:
+
+ // Save shadow copy of BCR, also hardware configuration
+ ldr r1, =_board_BCR
+ str r2, [r1]
+ ldr r1, =_board_CFG
+ str r9, [r1] // Saved far above...
+
+ .endm // _platform_setup1
+
+do_wait_op_done:
+ 1:
+ ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
+ beq 1b
+ bx lr // do_wait_op_done
+
+nfc_data_output:
+ mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
+ strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+
+ // writew(buf_no, RAM_BUFFER_ADDRESS_REG);
+ strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
+ // writew(FDO_PAGE_SPARE_VAL & 0xFF, NAND_FLASH_CONFIG2_REG);
+ mov r3, #FDO_PAGE_SPARE_VAL
+ strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ bx lr
+
+#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1
+#endif
+
+ /* Do nothing */
+ .macro init_spba
+ .endm /* init_spba */
+
+ /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
+ .macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, AIPS1_CTRL_BASE_ADDR_W
+ ldr r1, AIPS1_PARAM_W
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ ldr r0, AIPS2_CTRL_BASE_ADDR_W
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+
+ /*
+ * Clear the on and off peripheral modules Supervisor Protect bit
+ * for SDMA to access them. Did not change the AIPS control registers
+ * (offset 0x20) access type
+ */
+ ldr r0, AIPS1_CTRL_BASE_ADDR_W
+ ldr r1, =0x0
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ ldr r1, [r0, #0x50]
+ and r1, r1, #0x00FFFFFF
+ str r1, [r0, #0x50]
+
+ ldr r0, AIPS2_CTRL_BASE_ADDR_W
+ ldr r1, =0x0
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ ldr r1, [r0, #0x50]
+ and r1, r1, #0x00FFFFFF
+ str r1, [r0, #0x50]
+ .endm /* init_aips */
+
+ /* MAX (Multi-Layer AHB Crossbar Switch) setup */
+ .macro init_max
+ ldr r0, MAX_BASE_ADDR_W
+ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+ ldr r1, MAX_PARAM1
+ str r1, [r0, #0x000] /* for S0 */
+ str r1, [r0, #0x100] /* for S1 */
+ str r1, [r0, #0x200] /* for S2 */
+ str r1, [r0, #0x300] /* for S3 */
+ str r1, [r0, #0x400] /* for S4 */
+ /* SGPCR - always park on last master */
+ ldr r1, =0x10
+ str r1, [r0, #0x010] /* for S0 */
+ str r1, [r0, #0x110] /* for S1 */
+ str r1, [r0, #0x210] /* for S2 */
+ str r1, [r0, #0x310] /* for S3 */
+ str r1, [r0, #0x410] /* for S4 */
+ /* MGPCR - restore default values */
+ ldr r1, =0x0
+ str r1, [r0, #0x800] /* for M0 */
+ str r1, [r0, #0x900] /* for M1 */
+ str r1, [r0, #0xA00] /* for M2 */
+ str r1, [r0, #0xB00] /* for M3 */
+ str r1, [r0, #0xC00] /* for M4 */
+ str r1, [r0, #0xD00] /* for M5 */
+ .endm /* init_max */
+
+ /* Clock setup */
+ .macro init_clock
+ ldr r0, IPU_CTRL_BASE_ADDR_W
+ ldr r1, =0x40
+ str r1, [r0]
+
+ ldr r0, CCM_BASE_ADDR_W
+ ldr r2, CCM_CCMR_0x074B0BF5
+ ldr r3, CCM_CCMR_0x074B0BFD
+ ldr r4, CCM_CCMR_0x074B0B7D
+
+ // Make sure to use CKIH
+ ldr r1, [r0, #CLKCTL_CCMR]
+ bic r1, r1, #0x8 // disable PLL first
+ str r1, [r0, #CLKCTL_CCMR]
+ str r2, [r0, #CLKCTL_CCMR] // select CKIH (26MHz) as PLL ref clock
+ ldr r1, =0x1000
+ 1:
+ subs r1, r1, #0x1
+ bne 1b
+ str r3, [r0, #CLKCTL_CCMR] // enable PLL
+ str r4, [r0, #CLKCTL_CCMR] // switch to PLL (SPLL for FIR)
+
+ // 532-133-66.5
+ ldr r1, CCM_PDR0_W
+ str r1, [r0, #CLKCTL_PDR0]
+ ldr r1, MPCTL_PARAM_W
+ str r1, [r0, #CLKCTL_MPCTL]
+
+ /* Set UPLL=240MHz, USB=60MHz */
+ ldr r1, CCM_PDR1_0x49FCFE7F
+ str r1, [r0, #CLKCTL_PDR1]
+ ldr r1, CCM_UPCTL_PARAM_240
+ str r1, [r0, #CLKCTL_UPCTL]
+ // default CLKO to 1/8 of the ARM core
+ mov r1, #0x000002C0
+ add r1, r1, #0x00000006
+ str r1, [r0, #CLKCTL_COSR]
+ .endm /* init_clock */
+
+ /* M3IF setup */
+ .macro init_m3if
+ /* Configure M3IF registers */
+ ldr r1, M3IF_BASE_W
+ /*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+ ldr r0, =0x00000040
+ str r0, [r1] /* M3IF control reg */
+ .endm /* init_m3if */
+
+ /* CPLD on CS5 setup */
+ .macro init_cs5
+ ldr r0, WEIM_CTRL_CS5_W
+ ldr r1, CS5_0x0000D843
+ str r1, [r0, #CSCRU]
+ ldr r1, CS5_0x22252521
+ str r1, [r0, #CSCRL]
+ ldr r1, CS5_0x22220A00
+ str r1, [r0, #CSCRA]
+ .endm /* init_cs5 */
+
+ .macro setup_sdram, name, bus_width, mode, full_page
+ b 1f
+ ESDCTL_BASE_W: .word ESDCTL_BASE
+ SDRAM_PARAM1_DDR: .word 0x4
+ SDRAM_PARAM1_SDR: .word 0x0
+ SDRAM_PARAM2_DDR: .word 0x80000F00
+ SDRAM_PARAM2_SDR: .word 0x80000400
+ SDRAM_PARAM3_DDR: .word 0x00100000
+ SDRAM_PARAM3_SDR: .word 0x0
+ SDRAM_PARAM4_X32: .word 0x00010000
+ SDRAM_PARAM4_X16: .word 0x0
+ SDRAM_0x55555555: .word 0x55555555
+ SDRAM_0xAAAAAAAA: .word 0xAAAAAAAA
+ SDRAM_0x92100000: .word 0x92100000
+ SDRAM_0xA2100000: .word 0xA2100000
+ SDRAM_0xB2100000: .word 0xB2100000
+ SDRAM_0x82116080: .word 0x82116080
+ SDRAM_0x0075E73A: .word 0x0075E73A
+1:
+ /* It sets the "Z" flag in the CPSR at the end of the macro */
+ ldr r0, ESDCTL_BASE_W
+ mov r2, #SDRAM_BASE_ADDR
+ ldr r1, SDRAM_0x0075E73A
+ str r1, [r0, #0x4]
+ ldr r1, =0x2 // reset
+ str r1, [r0, #0x10]
+ ldr r1, SDRAM_PARAM1_\mode
+ str r1, [r0, #0x10]
+ // Hold for more than 200ns
+ ldr r1, =0x10000
+1:
+ subs r1, r1, #0x1
+ bne 1b
+
+ ldr r1, SDRAM_0x92100000
+ str r1, [r0]
+ ldr r1, =0x0
+ ldr r12, SDRAM_PARAM2_\mode
+ str r1, [r12]
+ ldr r1, SDRAM_0xA2100000
+ str r1, [r0]
+ ldr r1, =0x0
+ str r1, [r2]
+ ldr r1, SDRAM_0xB2100000
+ str r1, [r0]
+
+ ldr r1, =0x0
+ .if \full_page
+ strb r1, [r2, #SDRAM_FULL_PAGE_MODE]
+ .else
+ strb r1, [r2, #SDRAM_BURST_MODE]
+ .endif
+
+ ldr r1, =0xFF
+ ldr r12, =0x81000000
+ strb r1, [r12]
+ ldr r3, SDRAM_0x82116080
+ ldr r4, SDRAM_PARAM3_\mode
+ add r3, r3, r4
+ ldr r4, SDRAM_PARAM4_\bus_width
+ add r3, r3, r4
+ .if \full_page
+ add r3, r3, #0x100 /* Force to full page mode */
+ .endif
+
+ str r3, [r0]
+ ldr r1, =0x0
+ str r1, [r2]
+ /* Below only for DDR */
+ ldr r1, [r0, #0x10]
+ ands r1, r1, #0x4
+ ldrne r1, =0x0000000C
+ strne r1, [r0, #0x10]
+ /* Testing if it is truly DDR */
+ ldr r1, SDRAM_0x55555555
+ ldr r0, =SDRAM_BASE_ADDR
+ str r1, [r0]
+ ldr r2, SDRAM_0xAAAAAAAA
+ str r2, [r0, #0x4]
+ ldr r2, [r0]
+ cmp r1, r2
+ .endm
+
+ .macro nfc_cmd_input
+ strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
+ mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
+ strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ bl do_wait_op_done
+ .endm // nfc_cmd_input
+
+ .macro do_addr_input
+ and r3, r3, #0xFF
+ strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
+ mov r3, #NAND_FLASH_CONFIG2_FADD_EN
+ strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ bl do_wait_op_done
+ .endm // do_addr_input
+
+ /* To support 133MHz DDR */
+ .macro init_drive_strength
+ /*
+ * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
+ * in SW_PAD_CTL registers
+ */
+
+ // SDCLK
+ ldr r1, IOMUXC_BASE_ADDR_W
+ add r1, r1, #0x200
+ // Now r1 = (IOMUX_BASE_ADDR + 0x200)
+ ldr r0, [r1, #0x6C]
+ bic r0, r0, #(1 << 12)
+ str r0, [r1, #0x6C]
+
+ // CAS
+ ldr r0, [r1, #0x70]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x70]
+
+ // RAS
+ ldr r0, [r1, #0x74]
+ bic r0, r0, #(1 << 2)
+ str r0, [r1, #0x74]
+
+ // CS2 (CSD0)
+ ldr r0, [r1, #0x7C]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x7C]
+
+ // DQM3
+ ldr r0, [r1, #0x84]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x84]
+
+ // DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
+ ldr r2, =22 // (0x2E0 - 0x288) / 4 = 22
+pad_loop:
+ ldr r0, [r1, #0x88]
+ bic r0, r0, #(1 << 22)
+ bic r0, r0, #(1 << 12)
+ bic r0, r0, #(1 << 2)
+ str r0, [r1, #0x88]
+ add r1, r1, #4
+ subs r2, r2, #0x1
+ bne pad_loop
+ .endm /* init_drive_strength */
+
+#define PLATFORM_VECTORS _platform_vectors
+ .macro _platform_vectors
+ .globl _board_BCR, _board_CFG
+_board_BCR: .long 0 // Board Control register shadow
+_board_CFG: .long 0 // Board Configuration (read at RESET)
+ .endm
+
+ARM_PPMRR: .word 0x40000015
+L2CACHE_PARAM: .word 0x00030024
+IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
+AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
+AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
+AIPS1_PARAM_W: .word 0x77777777
+MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
+MAX_PARAM1: .word 0x00302154
+CLKCTL_BASE_ADDR_W: .word CLKCTL_BASE_ADDR
+M3IF_BASE_W: .word M3IF_BASE
+IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
+#ifdef ARM_399MHZ
+CCM_PDR0_W: .word PDR0_399_133_66
+MPCTL_PARAM_W: .word MPCTL_PARAM_399
+#endif
+#ifdef ARM_532MHZ
+CCM_PDR0_W: .word PDR0_532_133_66
+MPCTL_PARAM_W: .word MPCTL_PARAM_532
+#endif
+
+MPCTL_PARAM_532_27_W: .word MPCTL_PARAM_532_27
+CCM_PDR1_0x49FCFE7F: .word 0x49FCFE7F
+CCM_UPCTL_PARAM_240: .word UPCTL_PARAM_240
+CCM_UPCTL_PARAM_240_27: .word UPCTL_PARAM_240_27
+AVIC_VECTOR0_ADDR_W: .word MXCBOOT_FLAG_REG
+AVIC_VECTOR1_ADDR_W: .word MXCFIS_FLAG_REG
+MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
+CONST_0x0FFF: .word 0x0FFF
+CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
+IPU_CTRL_BASE_ADDR_W: .word IPU_CTRL_BASE_ADDR
+CCM_CCMR_0x074B0BF5: .word 0x074B0BF5
+CCM_CCMR_0x074B0BFD: .word 0x074B0BFD
+CCM_CCMR_0x074B0B7D: .word 0x074B0B7D
+WEIM_CTRL_CS5_W: .word WEIM_CTRL_CS5
+CS5_0x0000D843: .word 0x0000D843
+CS5_0x22252521: .word 0x22252521
+CS5_0x22220A00: .word 0x22220A00
+
+/*---------------------------------------------------------------------------*/
+/* end of hal_platform_setup.h */
+#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x00000000)
+#define CYGMEM_REGION_ram_SIZE (0x7F00000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0x87F00000)
+#define CYGMEM_REGION_rom_SIZE (0x100000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ ram : ORIGIN = 0, LENGTH = 0x7F00000
+ rom : ORIGIN = 0x87F00000, LENGTH = 0x100000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_rom_vectors (rom, 0x87F00000, LMA_EQ_VMA)
+ SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
+ SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table))
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
--- /dev/null
+version 0
+region ram 0 7F00000 0 !
+region rom 87F00000 100000 1 !
+section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
+section data 0 1 1 1 1 1 0 0 8000 bss !
+section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
+section heap1 0 8 0 0 0 0 0 0 !
+section rom_vectors 0 1 0 1 1 1 1 1 87F00000 87F00000 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata rodata !
+section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 4 0 1 0 0 0 1 data !
--- /dev/null
+#ifndef CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+#define CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+
+//=============================================================================
+//
+// plf_io.h
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/hal/fsl_board.h>
+#include <cyg/hal/hal_soc.h>
+
+#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \
+ CYG_MACRO_START \
+ { \
+ extern unsigned int system_rev; \
+ /* Next ATAG_MEM. */ \
+ _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_MEM; \
+ /* Round up so there's only one bit set in the memory size. \
+ * Don't double it if it's already a power of two, though. \
+ */ \
+ _p_->u.mem.size = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE); \
+ if (_p_->u.mem.size < CYGMEM_REGION_ram_SIZE) \
+ _p_->u.mem.size <<= 1; \
+ _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram); \
+ _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size); \
+ _p_->hdr.size = ((sizeof(struct tag_revision)) + sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_REVISION; \
+ _p_->u.revision.rev = system_rev; \
+ } \
+ CYG_MACRO_END
+
+#endif // CYGONCE_HAL_ARM_BOARD_PLF_IO_H
--- /dev/null
+#ifndef CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+#define CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+//=============================================================================
+//
+// plf_mmap.h
+//
+// Platform specific memory map support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_misc.h>
+
+// Get the pagesize for a particular virtual address:
+
+// This does not depend on the vaddr.
+#define HAL_MM_PAGESIZE(vaddr, pagesize) CYG_MACRO_START \
+ (pagesize) = SZ_1M; \
+CYG_MACRO_END
+
+// Get the physical address from a virtual address:
+
+#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START \
+ cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
+ if ( _v_ < 128 * SZ_1M ) /* SDRAM */ \
+ _v_ += 0x800u * SZ_1M; \
+ else /* Rest of it */ \
+ /* no change */ ; \
+ (paddr) = _v_; \
+CYG_MACRO_END
+
+//---------------------------------------------------------------------------
+#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
--- /dev/null
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware mx31_3stack ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM current ;
+ package -hardware CYGPKG_HAL_ARM_MX31 current ;
+ package -hardware CYGPKG_HAL_ARM_MX31_3STACK current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ;
+ package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ;
+ package -hardware CYGPKG_COMPRESS_ZLIB current ;
+ package -hardware CYGPKG_DIAGNOSIS current ;
+ package -hardware CYGPKG_IO_FLASH current ;
+ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+ package -hardware CYGPKG_DEVS_MXC_SPI current ;
+ package -hardware CYGPKG_DEVS_MXC_I2C current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package CYGPKG_MEMALLOC current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FSL_SPI_VER_0_4 {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MMC {
+ inferred_value 1
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
+ user_value 50
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ inferred_value 0x00040000
+};
+
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+ inferred_value 0x80008000
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_component CYG_HAL_STARTUP {
+ user_value ROMRAM
+};
+
+cdl_component CYGPKG_MEMORY_DIAGNOSIS {
+ user_value 1
+};
+
+cdl_option CYGSEM_RAM_PM_DIAGNOSIS {
+ user_value 0
+};
+
+#cdl_component CYGPKG_WDT_DIAGNOSIS {
+# user_value 1
+#};
+
+cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+ inferred_value 1
+};
+
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+ user_value 1 "FSL 200904"
+};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+ inferred_value 4
+};
--- /dev/null
+/*=============================================================================
+//
+// board_diag.c
+//
+// HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_arch.h> // basic machine info
+#include <cyg/hal/hal_intr.h> // interrupt macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_if.h> // Calling-if API
+#include <cyg/hal/drv_api.h> // driver API
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/fsl_board.h> // Platform specifics
+
+static void cyg_hal_plf_duart_init(void);
+extern void cyg_hal_plf_serial_init(void);
+
+#define DUART_WORKAROUND_DELAY(a) hal_delay_us(a);
+
+
+void cyg_hal_plf_comms_init(void)
+{
+ static int initialized = 0;
+
+ if (initialized)
+ return;
+
+ initialized = 1;
+
+ /* Setup GPIO and enable transceiver for UARTs */
+ cyg_hal_plf_duart_init();
+ cyg_hal_plf_serial_init();
+}
+
+//=============================================================================
+// ST16552 DUART driver
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// There are two serial ports.
+#define CYG_DEV_SERIAL_BASE_A (BOARD_CS_UART_BASE + 0x0000) // port A
+#define CYG_DEV_SERIAL_BASE_B (BOARD_CS_UART_BASE + 0x8000) // port B
+
+//-----------------------------------------------------------------------------
+// Based on 14.7456 MHz xtal
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x60
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x30
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x18
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x10
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x08
+#endif
+
+#ifndef CYG_DEV_SERIAL_BAUD_MSB
+#error Missing/incorrect serial baud rate defined - CDL error?
+#endif
+
+//-----------------------------------------------------------------------------
+// Define the serial registers. The board is equipped with a 16552
+// serial chip.
+
+#ifdef EXT_UART_x16
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT16
+#define HAL_READ_UINT_UART HAL_READ_UINT16
+typedef cyg_uint16 uart_width;
+#else //_x8
+typedef cyg_uint8 uart_width;
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT8
+#define HAL_READ_UINT_UART HAL_READ_UINT8
+#endif
+
+#define CYG_DEV_SERIAL_RHR 0x00 // receiver buffer register, read, dlab = 0
+#define CYG_DEV_SERIAL_THR 0x00 // transmitter holding register, write, dlab = 0
+#define CYG_DEV_SERIAL_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IER 0x01 // interrupt enable register, read/write, dlab = 0
+#define CYG_DEV_SERIAL_DLM 0x01 // divisor latch (MS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IIR 0x02 // interrupt identification register, read, dlab = 0
+#define CYG_DEV_SERIAL_FCR 0x02 // fifo control register, write, dlab = 0
+#define CYG_DEV_SERIAL_AFR 0x02 // alternate function register, read/write, dlab = 1
+#define CYG_DEV_SERIAL_LCR 0x03 // line control register, read/write
+#define CYG_DEV_SERIAL_MCR 0x04
+#define CYG_DEV_SERIAL_MCR_A 0x04
+#define CYG_DEV_SERIAL_MCR_B 0x04
+#define CYG_DEV_SERIAL_LSR 0x05 // line status register, read
+#define CYG_DEV_SERIAL_MSR 0x06 // modem status register, read
+#define CYG_DEV_SERIAL_SCR 0x07 // scratch pad register
+
+// The interrupt enable register bits.
+#define SIO_IER_ERDAI 0x01 // enable received data available irq
+#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
+#define SIO_IER_ELSI 0x04 // enable receiver line status irq
+#define SIO_IER_EMSI 0x08 // enable modem status interrupt
+
+// The interrupt identification register bits.
+#define SIO_IIR_IP 0x01 // 0 if interrupt pending
+#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
+#define ISR_Tx 0x02
+#define ISR_Rx 0x04
+
+// The line status register bits.
+#define SIO_LSR_DR 0x01 // data ready
+#define SIO_LSR_OE 0x02 // overrun error
+#define SIO_LSR_PE 0x04 // parity error
+#define SIO_LSR_FE 0x08 // framing error
+#define SIO_LSR_BI 0x10 // break interrupt
+#define SIO_LSR_THRE 0x20 // transmitter holding register empty
+#define SIO_LSR_TEMT 0x40 // transmitter register empty
+#define SIO_LSR_ERR 0x80 // any error condition
+
+// The modem status register bits.
+#define SIO_MSR_DCTS 0x01 // delta clear to send
+#define SIO_MSR_DDSR 0x02 // delta data set ready
+#define SIO_MSR_TERI 0x04 // trailing edge ring indicator
+#define SIO_MSR_DDCD 0x08 // delta data carrier detect
+#define SIO_MSR_CTS 0x10 // clear to send
+#define SIO_MSR_DSR 0x20 // data set ready
+#define SIO_MSR_RI 0x40 // ring indicator
+#define SIO_MSR_DCD 0x80 // data carrier detect
+
+// The line control register bits.
+#define SIO_LCR_WLS0 0x01 // word length select bit 0
+#define SIO_LCR_WLS1 0x02 // word length select bit 1
+#define SIO_LCR_STB 0x04 // number of stop bits
+#define SIO_LCR_PEN 0x08 // parity enable
+#define SIO_LCR_EPS 0x10 // even parity select
+#define SIO_LCR_SP 0x20 // stick parity
+#define SIO_LCR_SB 0x40 // set break
+#define SIO_LCR_DLAB 0x80 // divisor latch access bit
+
+// The FIFO control register
+#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
+#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
+#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
+
+//-----------------------------------------------------------------------------
+
+typedef struct {
+ uart_width* base;
+ cyg_int32 msec_timeout;
+ int isr_vector;
+} channel_data_t;
+
+static channel_data_t channels[] = {
+#if CYGHWR_HAL_ARM_DUART_UARTA != 0
+ {(uart_width*)CYG_DEV_SERIAL_BASE_A, 1000, 0},
+#endif
+#if CYGHWR_HAL_ARM_DUART_UARTB != 0
+ {(uart_width*)CYG_DEV_SERIAL_BASE_B, 1000, 0}
+#endif
+};
+
+//-----------------------------------------------------------------------------
+
+static void init_duart_channel(channel_data_t* __ch_data)
+{
+ uart_width* base = __ch_data->base;
+ uart_width lcr;
+
+ // 8-1-no parity.
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR,
+ SIO_LCR_WLS0 | SIO_LCR_WLS1);
+ DUART_WORKAROUND_DELAY(50);
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ lcr |= SIO_LCR_DLAB;
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLL, CYG_DEV_SERIAL_BAUD_LSB);
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLM, CYG_DEV_SERIAL_BAUD_MSB);
+ lcr &= ~SIO_LCR_DLAB;
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_FCR, 0x07); // Enable & clear FIFO
+}
+
+//#define x_debug_uart_log_buf
+#ifdef x_debug_uart_log_buf
+#define x_DIAG_BUFSIZE 2048
+static char __x_log_buf[x_DIAG_BUFSIZE];
+static int x_diag_bp = 0;
+#endif
+
+void cyg_hal_plf_duart_putc(void* __ch_data, cyg_uint8 c)
+{
+ uart_width* base = ((channel_data_t*)__ch_data)->base;
+ uart_width lsr;
+
+#ifdef x_debug_uart_log_buf
+ __x_log_buf[x_diag_bp++] = c;
+#endif
+ CYGARC_HAL_SAVE_GP();
+
+ do {
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ } while ((lsr & SIO_LSR_THRE) == 0);
+
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_THR, c);
+
+ // Hang around until the character has been safely sent.
+ do {
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ } while ((lsr & SIO_LSR_THRE) == 0);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool cyg_hal_plf_duart_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+ uart_width* base = ((channel_data_t*)__ch_data)->base;
+ uart_width lsr, ch16;
+
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ if ((lsr & SIO_LSR_DR) == 0)
+ return false;
+
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_RHR, ch16);
+
+ *ch = (cyg_uint8) (ch16 & 0x00FF);
+
+ return true;
+}
+
+cyg_uint8 cyg_hal_plf_duart_getc(void* __ch_data)
+{
+ cyg_uint8 ch;
+
+ CYGARC_HAL_SAVE_GP();
+
+ while (!cyg_hal_plf_duart_getc_nonblock(__ch_data, &ch));
+
+ CYGARC_HAL_RESTORE_GP();
+ return ch;
+}
+
+static void cyg_hal_plf_duart_write(void* __ch_data, const cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while (__len-- > 0)
+ cyg_hal_plf_duart_putc(__ch_data, *__buf++);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static void cyg_hal_plf_duart_read(void* __ch_data, cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while (__len-- > 0)
+ *__buf++ = cyg_hal_plf_duart_getc(__ch_data);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool cyg_hal_plf_duart_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+ int delay_count;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_bool res;
+
+ CYGARC_HAL_SAVE_GP();
+
+ delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+ for (;;) {
+ res = cyg_hal_plf_duart_getc_nonblock(__ch_data, ch);
+ if (res || 0 == delay_count--)
+ break;
+
+ CYGACC_CALL_IF_DELAY_US(100);
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static int cyg_hal_plf_duart_control(void *__ch_data,
+ __comm_control_cmd_t __func, ...)
+{
+ static int irq_state = 0;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ uart_width ier;
+ int ret = 0;
+
+ CYGARC_HAL_SAVE_GP();
+
+ switch (__func) {
+ case __COMMCTL_IRQ_ENABLE:
+ HAL_INTERRUPT_UNMASK(chan->isr_vector);
+ HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ ier |= SIO_IER_ERDAI;
+ HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ irq_state = 1;
+ break;
+ case __COMMCTL_IRQ_DISABLE:
+ ret = irq_state;
+ irq_state = 0;
+ HAL_INTERRUPT_MASK(chan->isr_vector);
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ ier &= ~SIO_IER_ERDAI;
+ HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ break;
+ case __COMMCTL_DBG_ISR_VECTOR:
+ ret = chan->isr_vector;
+ break;
+ case __COMMCTL_SET_TIMEOUT:
+ {
+ va_list ap;
+
+ va_start(ap, __func);
+
+ ret = chan->msec_timeout;
+ chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+ va_end(ap);
+ }
+ break;
+ default:
+ break;
+ }
+ CYGARC_HAL_RESTORE_GP();
+ return ret;
+}
+
+static int cyg_hal_plf_duart_isr(void *__ch_data, int* __ctrlc,
+ CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ uart_width _iir;
+ int res = 0;
+ CYGARC_HAL_SAVE_GP();
+
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IIR, _iir);
+ _iir &= SIO_IIR_ID_MASK;
+
+ *__ctrlc = 0;
+ if ( ISR_Rx == _iir ) {
+ uart_width c, lsr;
+ cyg_uint8 c8;
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_LSR, lsr);
+ if (lsr & SIO_LSR_DR) {
+
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_RHR, c);
+
+ c8 = (cyg_uint8) (c & 0x00FF);
+
+ if (cyg_hal_is_break( &c8 , 1 ))
+ *__ctrlc = 1;
+ }
+
+ // Acknowledge the interrupt
+ HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+ res = CYG_ISR_HANDLED;
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static void cyg_hal_plf_duart_init(void)
+{
+ hal_virtual_comm_table_t* comm;
+ int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ int i;
+
+ // Init channels
+#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
+ for (i = 0; i < NUMOF(channels); i++) {
+ HAL_INTERRUPT_MASK(channels[i].isr_vector);
+ init_duart_channel(&channels[i]);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_duart_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_duart_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_duart_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_duart_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_duart_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_duart_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_duart_getc_timeout);
+ }
+
+ // Restore original console
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
+
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
+#define __BASE CMA101_DUARTA
+#define _INT CYGNUM_HAL_INTERRUPT_SERIAL_A
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1)
+#define __BASE CMA101_DUARTB
+#define _INT CYGNUM_HAL_INTERRUPT_SERIAL_B
+#endif
+
+#ifdef __BASE
+
+#ifdef CYGSEM_HAL_ROM_MONITOR
+#define CYG_HAL_STARTUP_ROM
+#define CYG_HAL_STARTUP_ROMRAM
+#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#endif
+
+#if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define HAL_DIAG_USES_HARDWARE
+#elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
+#define HAL_DIAG_USES_HARDWARE
+#elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+#define HAL_DIAG_USES_HARDWARE
+#endif
+
+static channel_data_t channel = {
+ (uart_width*) _BASE, 0, 0
+};
+
+#ifdef HAL_DIAG_USES_HARDWARE
+
+void hal_diag_init(void)
+{
+ static int init = 0;
+ char *msg = "\n\rARM eCos\n\r";
+ uart_width lcr;
+
+ if (init++) return;
+
+ init_duart_channel(&channel);
+
+ while (*msg) hal_diag_write_char(*msg++);
+}
+
+#ifdef DEBUG_DIAG
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define DIAG_BUFSIZE 32
+#else
+#define DIAG_BUFSIZE 2048
+#endif
+static char diag_buffer[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+
+void hal_diag_write_char(char c)
+{
+ uart_width lsr;
+
+ hal_diag_init();
+
+ cyg_hal_plf_duart_putc(&channel, c)
+
+#ifdef DEBUG_DIAG
+ diag_buffer[diag_bp++] = c;
+ if (diag_bp == DIAG_BUFSIZE) {
+ while (1) ;
+ diag_bp = 0;
+ }
+#endif
+}
+
+void hal_diag_read_char(char *c)
+{
+ *c = cyg_hal_plf_duart_getc(&channel);
+}
+
+#else // HAL_DIAG relies on GDB
+
+// Initialize diag port - assume GDB channel is already set up
+void hal_diag_init(void)
+{
+ if (0) init_duart_channel(&channel); // avoid warning
+}
+
+// Actually send character down the wire
+static void hal_diag_write_char_serial(char c)
+{
+ cyg_hal_plf_duart_putc(&channel, c);
+}
+
+static bool hal_diag_read_serial(char *c)
+{
+ long timeout = 1000000000; // A long time...
+
+ while (!cyg_hal_plf_duart_getc_nonblock(&channel, c))
+ if (0 == --timeout) return false;
+
+ return true;
+}
+
+void hal_diag_read_char(char *c)
+{
+ while (!hal_diag_read_serial(c)) ;
+}
+
+void hal_diag_write_char(char c)
+{
+ static char line[100];
+ static int pos = 0;
+
+ // No need to send CRs
+ if (c == '\r') return;
+
+ line[pos++] = c;
+
+ if (c == '\n' || pos == sizeof(line)) {
+ CYG_INTERRUPT_STATE old;
+
+ // Disable interrupts. This prevents GDB trying to interrupt us
+ // while we are in the middle of sending a packet. The serial
+ // receive interrupt will be seen when we re-enable interrupts
+ // later.
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+#else
+ HAL_DISABLE_INTERRUPTS(old);
+#endif
+
+ while (1) {
+ static char hex[] = "0123456789ABCDEF";
+ cyg_uint8 csum = 0;
+ int i;
+ char c1;
+
+ hal_diag_write_char_serial('$');
+ hal_diag_write_char_serial('O');
+ csum += 'O';
+ for (i = 0; i < pos; i++) {
+ char ch = line[i];
+ char h = hex[(ch>>4)&0xF];
+ char l = hex[ch&0xF];
+ hal_diag_write_char_serial(h);
+ hal_diag_write_char_serial(l);
+ csum += h;
+ csum += l;
+ }
+ hal_diag_write_char_serial('#');
+ hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
+ hal_diag_write_char_serial(hex[csum&0xF]);
+
+ // Wait for the ACK character '+' from GDB here and handle
+ // receiving a ^C instead. This is the reason for this clause
+ // being a loop.
+ if (!hal_diag_read_serial(&c1))
+ continue; // No response - try sending packet again
+
+ if ( c1 == '+' )
+ break; // a good acknowledge
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
+ if ( c1 == 3 ) {
+ // Ctrl-C: breakpoint.
+ cyg_hal_gdb_interrupt (__builtin_return_address(0));
+ break;
+ }
+#endif
+ // otherwise, loop round again
+ }
+
+ pos = 0;
+
+ // And re-enable interrupts
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+#else
+ HAL_RESTORE_INTERRUPTS(old);
+#endif
+
+ }
+}
+#endif
+
+#endif // __BASE
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
--- /dev/null
+//==========================================================================
+//
+// board_misc.c
+//
+// HAL misc board support code for the board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include <redboot.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h> // Interrupt names
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/fsl_board.h> // Platform specifics
+
+#include <cyg/infra/diag.h> // diag_printf
+
+// All the MM table layout is here:
+#include <cyg/hal/hal_mm.h>
+
+externC void* memset(void *, int, size_t);
+
+void hal_mmu_init(void)
+{
+ unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
+ unsigned long i;
+
+ /*
+ * Set the TTB register
+ */
+ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
+
+ /*
+ * Set the Domain Access Control Register
+ */
+ i = ARM_ACCESS_DACR_DEFAULT;
+ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+
+ /*
+ * First clear all TT entries - ie Set them to Faulting
+ */
+ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+
+ /* Actual Virtual Size Attributes Function */
+ /* Base Base MB cached? buffered? access permissions */
+ /* xxx00000 xxx00000 */
+ X_ARM_MMU_SECTION(0x000, 0xF00, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */
+ X_ARM_MMU_SECTION(0x300, 0x300, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* L2CC */
+ X_ARM_MMU_SECTION(0x43F, 0x43F, 0x3C1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Internal Regsisters upto SDRAM*/
+ X_ARM_MMU_SECTION(0x800, 0x000, 0x80, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0x800, 0x800, 0x80, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0xA00, 0xA00, 0x20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Flash */
+ X_ARM_MMU_SECTION(0xB40, 0xB40, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* External I/O */
+ X_ARM_MMU_SECTION(0xB50, 0xB50, 0x8, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PSRAM */
+ X_ARM_MMU_SECTION(0xB60, 0xB60, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* External I/O */
+ X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* EIM control*/
+}
+
+//
+// Platform specific initialization
+//
+
+unsigned int g_clock_src;
+extern int g_board_type;
+
+void plf_hardware_init(void)
+{
+ unsigned long val = readl(CCM_BASE_ADDR + CLKCTL_CCMR);
+ unsigned long reg;
+
+ if ((val & 0x6) == 0x4) {
+ g_clock_src = FREQ_26MHZ;
+ } else if ((val & 0x6) == 0x2) {
+ g_clock_src = FREQ_32768HZ;
+ }
+
+ /* Reset interrupt status reg */
+ writew(0x1F, PBC_INT_REST);
+ writew(0x00, PBC_INT_REST);
+ writew(0xFFFF, PBC_INT_MASK);
+ // UART1
+ writel(0x1210, IOMUXC_BASE_ADDR + 0x80);
+ // Enable the MMC
+ writel(0x01220100, IOMUXC_BASE_ADDR + 0x148);
+ reg = readl(GPIO3_BASE_ADDR + 0x4);
+ reg |= 0x1;
+ writel(reg, GPIO3_BASE_ADDR + 0x4);
+ reg = readl(GPIO3_BASE_ADDR);
+ reg |= 0x1;
+ writel(reg, GPIO3_BASE_ADDR);
+
+ g_board_type = BOARD_TYPE_3STACK;
+}
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+typedef void code_fun(void);
+
+void board_program_new_stack(void *func)
+{
+ register CYG_ADDRESS stack_ptr asm("sp");
+ register CYG_ADDRESS old_stack asm("r4");
+ register code_fun *new_func asm("r0");
+ old_stack = stack_ptr;
+ stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
+ new_func = (code_fun*)func;
+ new_func();
+ stack_ptr = old_stack;
+}
+
+static void display_clock_src(void)
+{
+ diag_printf("\n");
+ if (g_clock_src == FREQ_27MHZ) {
+ diag_printf("Clock input is 27 MHz");
+ } else if (g_clock_src == FREQ_26MHZ) {
+ diag_printf("Clock input is 26 MHz");
+ } else if (g_clock_src == FREQ_32768HZ) {
+ diag_printf("Clock input is 32KHz");
+ } else {
+ diag_printf("Unknown clock input source. Something is wrong!");
+ }
+}
+RedBoot_init(display_clock_src, RedBoot_INIT_LAST);
+
+// ------------------------------------------------------------------------
--- /dev/null
+//==========================================================================
+//
+// redboot_cmds.c
+//
+// Board [platform] specific RedBoot commands
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+#include <redboot.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/plf_mmap.h>
+#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <flash_config.h>
+
+#if (REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE)
+#error REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE
+#endif
+
+RedBoot_config_option("Board specifics",
+ brd_specs,
+ ALWAYS_ENABLED,
+ true,
+ CONFIG_INT,
+ 0
+ );
+#endif //CYGSEM_REDBOOT_FLASH_CONFIG
+
+char HAL_PLATFORM_EXTRA[60] = "MX31 3-Stack (Freescale i.MX31 based) PASS 1.0 [x32 DDR]";
+
+static void runImg(int argc, char *argv[]);
+
+RedBoot_cmd("run",
+ "Run an image at a location with MMU off",
+ "[<virtual addr>]",
+ runImg
+ );
+
+void launchRunImg(unsigned long addr)
+{
+ asm volatile ("mov r12, r0;");
+ HAL_CLEAN_INVALIDATE_L2();
+ HAL_DISABLE_L2();
+ HAL_MMU_OFF();
+ asm volatile (
+ "mov r0, #0;"
+ "mov r1, r12;"
+ "mov r11, #0;"
+ "mov r12, #0;"
+ "mrs r10, cpsr;"
+ "bic r10, r10, #0xF0000000;"
+ "msr cpsr_f, r10;"
+ "mov pc, r1"
+ );
+}
+
+extern unsigned long entry_address;
+
+static void runImg(int argc,char *argv[])
+{
+ unsigned int virt_addr, phys_addr;
+
+ // Default physical entry point for Symbian
+ if (entry_address == 0xFFFFFFFF)
+ virt_addr = 0x800000;
+ else
+ virt_addr = entry_address;
+
+ if (!scan_opts(argc,argv,1,0,0,(void*)&virt_addr,
+ OPTION_ARG_TYPE_NUM, "virtual address"))
+ return;
+
+ if (entry_address != 0xFFFFFFFF)
+ diag_printf("load entry_address=0x%lx\n", entry_address);
+ HAL_VIRT_TO_PHYS_ADDRESS(virt_addr, phys_addr);
+
+ diag_printf("virt_addr=0x%x\n",virt_addr);
+ diag_printf("phys_addr=0x%x\n",phys_addr);
+
+ launchRunImg(phys_addr);
+}
+
+#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYG_HAL_STARTUP_ROMRAM)
+
+RedBoot_cmd("romupdate",
+ "Update Redboot with currently running image",
+ "",
+ romupdate
+ );
+
+extern int flash_program(void *_addr, void *_data, int len, void **err_addr);
+extern int flash_erase(void *addr, int len, void **err_addr);
+extern char *flash_errmsg(int err);
+extern unsigned char *ram_end; //ram end is where the redboot starts FIXME: use PC value
+
+#ifdef CYGPKG_IO_FLASH
+void romupdate(int argc, char *argv[])
+{
+ void *err_addr, *base_addr;
+ int stat;
+
+ if (IS_FIS_FROM_MMC()) {
+ diag_printf("Updating ROM in MMC/SD flash\n");
+ base_addr = (void*)MXC_MMC_BASE_DUMMY;
+ /* Read the MBR from the card to RAM */
+ mmc_data_read((cyg_uint32*)(ram_end + 0x4), 0x3FC, base_addr);
+ diag_printf("Programming Redboot to MMC/SD flash\n");
+ mmc_data_write((cyg_uint32*)ram_end, CYGBLD_REDBOOT_MIN_IMAGE_SIZE, (cyg_uint32)base_addr);
+ return;
+ } else if (IS_FIS_FROM_NAND()) {
+ base_addr = (void*)0;
+ diag_printf("Updating ROM in NAND flash\n");
+ } else {
+ diag_printf("romupdate not supported\n");
+ diag_printf("Use \"factive [NAND|MMC]\" to select either MMC or NAND flash\n");
+ return;
+ }
+
+ // Erase area to be programmed
+ if ((stat = flash_erase((void *)base_addr,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ (void **)&err_addr)) != 0) {
+ diag_printf("Can't erase region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ return;
+ }
+ // Now program it
+ if ((stat = flash_program((void *)base_addr, (void *)ram_end,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ (void **)&err_addr)) != 0) {
+ diag_printf("Can't program region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ }
+}
+RedBoot_cmd("factive",
+ "Enable one flash media for Redboot",
+ "[NOR | NAND | MMC]",
+ factive
+ );
+
+void factive(int argc, char *argv[])
+{
+ unsigned long phys_addr;
+
+ if (argc != 2) {
+ diag_printf("Invalid factive cmd\n");
+ return;
+ }
+
+ if (strcasecmp(argv[1], "NOR") == 0) {
+#ifndef MXCFLASH_SELECT_NOR
+ diag_printf("Not supported\n");
+ return;
+#else
+ MXC_ASSERT_NOR_BOOT();
+#endif
+ } else if (strcasecmp(argv[1], "NAND") == 0) {
+#ifndef MXCFLASH_SELECT_NAND
+ diag_printf("Not supported\n");
+ return;
+#else
+ MXC_ASSERT_NAND_BOOT();
+#endif
+ } else if (strcasecmp(argv[1], "MMC") == 0) {
+#ifndef MXCFLASH_SELECT_MMC
+ diag_printf("Not supported\n");
+ return;
+#else
+ MXC_ASSERT_MMC_BOOT();
+#endif
+ } else {
+ diag_printf("Invalid command: %s\n", argv[1]);
+ return;
+ }
+ HAL_VIRT_TO_PHYS_ADDRESS(ram_end, phys_addr);
+
+ launchRunImg(phys_addr);
+}
+#endif //CYGPKG_IO_FLASH
+#endif /* CYG_HAL_STARTUP_ROMRAM */
--- /dev/null
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware mx31ads ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM current ;
+ package -hardware CYGPKG_HAL_ARM_MX31 current ;
+ package -hardware CYGPKG_HAL_ARM_MX31ADS current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_MX31ADS current ;
+ package -hardware CYGPKG_DEVS_ETH_CL_CS8900A current ;
+ package -hardware CYGPKG_COMPRESS_ZLIB current ;
+ package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ;
+ package -hardware CYGPKG_IO_FLASH current ;
+ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+ package -hardware CYGPKG_DEVS_FLASH_MX31ADS_SPANSION current ;
+ package -hardware CYGPKG_DEVS_MXC_SPI current ;
+ package -hardware CYGPKG_DEVS_MXC_I2C current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package CYGPKG_MEMALLOC current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_S29WS256N {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FSL_SPI_VER_0_4 {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MMC {
+ inferred_value 1
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
+ user_value 50
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ inferred_value 0x00040000
+};
+
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+ inferred_value 0x80008000
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_component CYG_HAL_STARTUP {
+ user_value ROMRAM
+};
+
+cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+ inferred_value 1
+};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+ inferred_value 4
+};
+
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+ user_value 1 "FSL 200904"
+};
--- /dev/null
+# ====================================================================
+#
+# hal_arm_board.cdl
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+
+cdl_package CYGPKG_HAL_ARM_MX35_3STACK {
+ display "Freescale board"
+ parent CYGPKG_HAL_ARM_MX35
+ hardware
+ include_dir cyg/hal
+ define_header hal_arm_board.h
+ description "
+ This HAL platform package provides generic
+ support for the Freescale MX35 3STACK Board."
+
+ compile board_misc.c board_diag.c
+ implements CYGINT_HAL_DEBUG_GDB_STUBS
+ implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+ implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+
+ #implements CYGHWR_HAL_ARM_DUART_UARTB
+ implements CYGHWR_HAL_ARM_SOC_UART1
+
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_soc.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_board.h>"
+ puts $::cdl_header "#define HAL_PLATFORM_CPU \"i.MX35 \""
+ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Freescale\""
+ puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 1645"
+ puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK board_program_new_stack"
+ }
+
+ cdl_component CYG_HAL_STARTUP {
+ display "Startup type"
+ flavor data
+ default_value {"ROM"}
+ legal_values {"RAM" "ROM" "ROMRAM"}
+ no_define
+ define -file system.h CYG_HAL_STARTUP
+ description "
+ When targetting the eval board it is possible to build
+ the system for either RAM bootstrap or ROM bootstrap(s). Select
+ 'ram' when building programs to load into RAM using eCos GDB
+ stubs. Select 'rom' when building a stand-alone application
+ which will be put into ROM, or for the special case of
+ building the eCos GDB stubs themselves. Using ROMRAM will allow
+ the program to exist in ROM, but be copied to RAM during startup."
+ }
+
+ cdl_interface CYGINT_DEVS_ETH_FEC_REQUIRED {
+ display "FEC ethernet driver required"
+ }
+
+ implements CYGINT_DEVS_ETH_FEC_REQUIRED
+
+ cdl_interface CYGHWR_HAL_ARM_DUART_UARTA {
+ display "ST16552 UARTA available as diagnostic/debug channel"
+ description "
+ The board has a ST16552 DUART chip. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_DUART_UARTB {
+ display "ST16552 UARTB available as diagnostic/debug channel"
+ description "
+ The board has a ST16552 DUART chip. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ display "Diagnostic serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the console port.
+ Note: this should match the value chosen for the GDB port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ display "GDB serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the GDB port.
+ Note: this should match the value chosen for the console port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the board"
+ flavor data
+ calculated 3
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ The board has three serial ports. This option
+ chooses which port will be used to connect to a host
+ running GDB."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+ display "Default console channel."
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ calculated 0
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Console serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ description "
+ The board has only three serial ports. This option
+ chooses which port will be used for console output."
+ }
+
+ cdl_component CYGBLD_GLOBAL_OPTIONS {
+ display "Global build options"
+ flavor none
+ no_define
+ description "
+ Global build options including control over
+ compiler flags, linker flags and choice of toolchain."
+
+
+ parent CYGPKG_NONE
+
+ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ display "Global command prefix"
+ flavor data
+ no_define
+ default_value { "arm-none-eabi" }
+ description "
+ This option specifies the command prefix used when
+ invoking the build tools."
+ }
+
+ cdl_option CYGBLD_GLOBAL_CFLAGS {
+ display "Global compiler flags"
+ flavor data
+ no_define
+ default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ description "
+ This option controls the global compiler flags which are used to
+ compile all packages by default. Individual packages may define
+ options which override these global flags."
+ }
+
+ cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ display "Global linker flags"
+ flavor data
+ no_define
+ default_value { "-Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" }
+ description "
+ This option controls the global linker flags. Individual
+ packages may define options which override these global flags."
+ }
+
+ cdl_option CYGBLD_BUILD_GDB_STUBS {
+ display "Build GDB stub ROM image"
+ default_value 0
+ requires { CYG_HAL_STARTUP == "ROM" }
+ requires CYGSEM_HAL_ROM_MONITOR
+ requires CYGBLD_BUILD_COMMON_GDB_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ no_define
+ description "
+ This option enables the building of the GDB stubs for the
+ board. The common HAL controls takes care of most of the
+ build process, but the final conversion from ELF image to
+ binary data is handled by the platform CDL, allowing
+ relocation of the data if necessary."
+
+ make -priority 320 {
+ <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
+ $(OBJCOPY) --remove-section=.fixed_vectors -O binary $< $@
+ }
+ }
+ }
+
+ cdl_component CYGPKG_HAL_ARM_BOARD_OPTIONS {
+ display "Freescale MXC Board build options"
+ flavor none
+ no_define
+ description "
+ Package specific build options including control over
+ compiler flags used only in building this package,
+ and details of which tests are built."
+
+ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the board HAL. These flags are used in addition
+ to the set of global flags."
+ }
+
+ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_REMOVE {
+ display "Suppressed compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the board HAL. These flags are removed from
+ the set of global flags if present."
+ }
+
+ }
+
+ cdl_component CYGHWR_MEMORY_LAYOUT {
+ display "Memory layout"
+ flavor data
+ no_define
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_board_ram" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" :
+ "arm_board_rom" }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ display "Memory layout linker script fragment"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.ldi>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.ldi>" :
+ "<pkgconf/mlt_arm_board_rom.ldi>" }
+ }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ display "Memory layout header file"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_H
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.h>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.h>" :
+ "<pkgconf/mlt_arm_board_rom.h>" }
+ }
+ }
+
+ cdl_option CYGSEM_HAL_ROM_MONITOR {
+ display "Behave as a ROM monitor"
+ flavor bool
+ default_value 0
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+ description "
+ Enable this option if this program is to be used as a ROM monitor,
+ i.e. applications will be loaded into RAM on the board, and this
+ ROM monitor may process exceptions or interrupts generated from the
+ application. This enables features such as utilizing a separate
+ interrupt stack when exceptions are generated."
+ }
+
+ cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ display "Work with a ROM monitor"
+ flavor booldata
+ legal_values { "Generic" "GDB_stubs" }
+ default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "RAM" }
+ description "
+ Support can be enabled for different varieties of ROM monitor.
+ This support changes various eCos semantics such as the encoding
+ of diagnostic output, or the overriding of hardware interrupt
+ vectors.
+ Firstly there is \"Generic\" support which prevents the HAL
+ from overriding the hardware vectors that it does not use, to
+ instead allow an installed ROM monitor to handle them. This is
+ the most basic support which is likely to be common to most
+ implementations of ROM monitor.
+ \"GDB_stubs\" provides support when GDB stubs are included in
+ the ROM monitor or boot ROM."
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ display "Redboot HAL options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+ description "
+ This option lists the target's requirements for a valid Redboot
+ configuration."
+
+ compile -library=libextras.a redboot_cmds.c
+
+ cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ display "Build Redboot ROM binary image"
+ active_if CYGBLD_BUILD_REDBOOT
+ default_value 1
+ no_define
+ description "This option enables the conversion of the Redboot ELF
+ image to a binary image suitable for ROM programming."
+
+ make -priority 325 {
+ <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+ $(OBJCOPY) -O binary $< $@
+ }
+ }
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_BOARD_OPTIONS {
+ display "Redboot HAL variant options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+
+ # RedBoot details
+ requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x80008000 }
+ define_proc {
+ puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00"
+ }
+ }
+}
--- /dev/null
+#ifndef CYGONCE_FSL_BOARD_H
+#define CYGONCE_FSL_BOARD_H
+
+//=============================================================================
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+
+#define CPLD_SPI_BASE CSPI1_BASE_ADDR
+#define CPLD_SPI_CHIP_SELECT_NO SPI_CTRL_CS1
+#define CPLD_SPI_CTRL_MODE_MASTER SPI_CTRL_MODE_MASTER
+
+#define PBC_BASE CS5_BASE_ADDR /* Peripheral Bus Controller */
+#define PBC_LED_CTRL (PBC_BASE + 0x20000)
+#define PBC_SB_STAT (PBC_BASE + 0x20008)
+#define PBC_ID_AAAA (PBC_BASE + 0x20040)
+#define PBC_ID_5555 (PBC_BASE + 0x20048)
+#define PBC_VERSION (PBC_BASE + 0x20050)
+#define PBC_ID_CAFE (PBC_BASE + 0x20058)
+#define PBC_INT_STAT (PBC_BASE + 0x20010)
+#define PBC_INT_MASK (PBC_BASE + 0x20038)
+#define PBC_INT_REST (PBC_BASE + 0x20020)
+#define PBC_SW_RESET (PBC_BASE + 0x20060)
+#define BOARD_CS_LAN_BASE (PBC_BASE + 0x300)
+#define BOARD_CS_UART_BASE (PBC_BASE + 0x8000)
+
+#define BOARD_FLASH_START CS0_BASE_ADDR
+#define REDBOOT_IMAGE_SIZE 0x40000
+
+#define EXT_UART_x16
+
+/* MX35 3-Stack SDRAM is from 0x90000000, 64M */
+#define SDRAM_BASE_ADDR CSD0_BASE_ADDR
+#define SDRAM_SIZE 0x08000000
+#define RAM_BANK0_BASE CSD0_BASE_ADDR
+#define RAM_BANK1_BASE CSD1_BASE_ADDR
+
+#ifdef CYGPKG_DEVS_MXC_SPI
+#define LAN92XX_REG_READ(reg_offset) \
+ ((cpld_reg_xfer(reg_offset, 0x0, 1)) | \
+ ((cpld_reg_xfer(reg_offset + 0x2, 0x0, 1) << 16)))
+
+#define LAN92XX_REG_WRITE(reg_offset, val) \
+ (cpld_reg_xfer(reg_offset, val, 0)); \
+ (cpld_reg_xfer(reg_offset + 0x2, (val >> 16), 0));
+#endif
+
+#define FEC_PHY_ADDR 0x1F
+
+#define LED_MAX_NUM 8
+#define LED_IS_ON(n) ((readw(PBC_LED_CTRL) & (1<<(n))) != 0)
+#define TURN_LED_ON(n) writew((readw(PBC_LED_CTRL)|(1<<(n))), PBC_LED_CTRL)
+#define TURN_LED_OFF(n) writew((readw(PBC_LED_CTRL)&(~(1<<(n)))), PBC_LED_CTRL)
+
+#define BOARD_DEBUG_LED(n) \
+ CYG_MACRO_START \
+ if (n >= 0 && n < LED_MAX_NUM) { \
+ if (LED_IS_ON(n)) \
+ TURN_LED_OFF(n); \
+ else \
+ TURN_LED_ON(n); \
+ } \
+ CYG_MACRO_END
+
+#endif /* CYGONCE_FSL_BOARD_H */
--- /dev/null
+#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
+#define CYGONCE_HAL_PLATFORM_SETUP_H
+
+//=============================================================================
+//
+// hal_platform_setup.h
+//
+// Platform specific support for HAL (assembly code)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <pkgconf/system.h> // System-wide configuration info
+#include CYGBLD_HAL_VARIANT_H // Variant specific configuration
+#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
+#include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
+#include <cyg/hal/hal_mmu.h> // MMU definitions
+#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1 _platform_setup1
+
+//#define BOOT_FROM_MMC
+
+#if defined(BOOT_FROM_MMC)
+#define PLATFORM_PREAMBLE setup_flash_header
+//#define MEMORY_MDDR_ENABLE
+#endif
+
+#define CYGHWR_HAL_ARM_HAS_MMU
+
+#ifdef CYG_HAL_STARTUP_ROMRAM
+#define CYGSEM_HAL_ROM_RESET_USES_JUMP
+#endif
+
+#define CYGHWR_HAL_ROM_VADDR 0x0
+
+#if 0
+#define UNALIGNED_ACCESS_ENABLE
+#define SET_T_BIT_DISABLE
+#define LOW_INT_LATENCY_ENABLE
+#define BRANCH_PREDICTION_ENABLE
+#endif
+
+#define UNALIGNED_ACCESS_ENABLE
+#define LOW_INT_LATENCY_ENABLE
+#define BRANCH_PREDICTION_ENABLE
+
+//#define TURN_OFF_IMPRECISE_ABORT
+
+// This macro represents the initial startup code for the platform
+// r11 is reserved to contain chip rev info in this file
+ .macro _platform_setup1
+FSL_BOARD_SETUP_START:
+/*
+ * ARM1136 init
+ * - invalidate I/D cache/TLB and drain write buffer;
+ * - invalidate L2 cache
+ * - unaligned access
+ * - branch predictions
+ */
+#ifdef TURN_OFF_IMPRECISE_ABORT
+ mrs r0, cpsr
+ bic r0, r0, #0x100
+ msr cpsr, r0
+#endif
+
+ mrc 15, 0, r1, c1, c0, 0
+ bic r1, r1, #(0x3<<21)
+ bic r1, r1, #(0x3<<11)
+ bic r1, r1, #0x5
+
+#ifndef BRANCH_PREDICTION_ENABLE
+ mrc 15, 0, r0, c1, c0, 1
+ bic r0, r0, #7
+ mcr 15, 0, r0, c1, c0, 1
+#else
+ mrc 15, 0, r0, c1, c0, 1
+ orr r0, r0, #7
+ mcr 15, 0, r0, c1, c0, 1
+ orr r1, r1, #(1<<11)
+#endif
+
+#ifdef UNALIGNED_ACCESS_ENABLE
+ orr r1, r1, #(1<<22)
+#endif
+
+#ifdef LOW_INT_LATENCY_ENABLE
+ orr r1, r1, #(1<<21)
+#endif
+ mcr 15, 0, r1, c1, c0, 0
+
+#ifdef BRANCH_PREDICTION_ENABLE
+ mov r0, #0
+ mcr 15, 0, r0, c15, c2, 4
+#endif
+
+ mov r0, #0
+ mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
+ mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+ mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
+
+ /* Also setup the Peripheral Port Remap register inside the core */
+ ldr r0, ARM_PPMRR /* start from AIPS 2GB region */
+ mcr p15, 0, r0, c15, c2, 4
+
+ /*** L2 Cache setup/invalidation/disable ***/
+ /* Disable L2 cache first */
+ mov r0, #L2CC_BASE_ADDR
+ ldr r2, [r0, #L2_CACHE_CTL_REG]
+ bic r2, r2, #0x1
+ str r2, [r0, #L2_CACHE_CTL_REG]
+ /*
+ * Configure L2 Cache:
+ * - 128k size(16k way)
+ * - 8-way associativity
+ * - 0 ws TAG/VALID/DIRTY
+ * - 4 ws DATA R/W
+ */
+ ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
+ and r1, r1, #0xFE000000
+ ldr r2, L2CACHE_PARAM
+ orr r1, r1, r2
+ str r1, [r0, #L2_CACHE_AUX_CTL_REG]
+ ldr r1, ROM_VER_ADDR_W
+ ldr r2, [r1]
+ cmp r2, #0x1
+ /* Workaournd for DDR issue:WT*/
+ ldreq r1, [r0, #L2_CACHE_DBG_CTL_REG]
+ orreq r1, r1, #2
+ streq r1, [r0, #L2_CACHE_DBG_CTL_REG]
+
+ /* Invalidate L2 */
+ mov r1, #0x000000FF
+ str r1, [r0, #L2_CACHE_INV_WAY_REG]
+L2_loop:
+ /* Poll Invalidate By Way register */
+ ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
+ cmp r2, #0
+ bne L2_loop
+ /*** End of L2 operations ***/
+
+#if defined(BOOT_FROM_MMC)
+ mov r0, #MMC_FLASH_BOOT
+ ldr r1, AVIC_VECTOR0_ADDR_W
+ str r0, [r1] // if MMC is selected, set MXCFIS_FLAG_REG
+#else
+ mov r0, #SDRAM_NON_FLASH_BOOT
+ ldr r1, AVIC_VECTOR0_ADDR_W
+ str r0, [r1] // for checking boot source from nand or sdram
+#endif
+/*
+ * End of ARM1136 init
+ */
+init_spba_start:
+ init_spba
+init_aips_start:
+ init_aips
+init_max_start:
+ init_max
+init_m3if_start:
+ init_m3if
+
+/* TODO::
+ * Use default setting is more stable then the settinig from IC team for EINCE
+ */
+ /*init_iomuxc */
+#ifndef BOOT_FROM_MMC
+ /* If SDRAM has been setup, bypass clock/WEIM setup */
+ cmp pc, #SDRAM_BASE_ADDR
+ blo init_clock_start
+ cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
+ blo HWInitialise_skip_SDRAM_setup
+
+ mov r0, #NOR_FLASH_BOOT
+ ldr r1, AVIC_VECTOR0_ADDR_W
+ str r0, [r1]
+#endif
+init_clock_start:
+ init_clock
+#ifndef BOOT_FROM_MMC
+init_cs5_start:
+ init_cs5
+
+init_sdram_start:
+ /* Assuming DDR memory first */
+ setup_sdram
+#endif
+HWInitialise_skip_SDRAM_setup:
+
+ mov r0, #NFC_BASE
+ add r2, r0, #0x1000 // 4K window
+ cmp pc, r0
+ blo Normal_Boot_Continue
+ cmp pc, r2
+ bhi Normal_Boot_Continue
+NAND_Boot_Start:
+ /* Copy image from flash to SDRAM first */
+ ldr r1, MXC_REDBOOT_ROM_START
+
+1: ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ blo 1b
+ /* Jump to SDRAM */
+ ldr r1, CONST_0x0FFF
+ and r0, pc, r1 /* offset of pc */
+ ldr r1, MXC_REDBOOT_ROM_START
+ add r1, r1, #0x10
+ add pc, r0, r1
+ nop
+ nop
+ nop
+ nop
+NAND_Copy_Main:
+ mov r0, #NAND_FLASH_BOOT
+ ldr r1, AVIC_VECTOR0_ADDR_W
+ str r0, [r1]
+ mov r0, #MXCFIS_NAND
+ ldr r1, AVIC_VECTOR1_ADDR_W
+ str r0, [r1]
+
+ mov r0, #NFC_BASE; //r0: nfc base. Reloaded after each page copying
+ add r12, r0, #0x1E00 //r12: NFC register base. Doesn't change
+ ldrh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+ orr r3, r3, #0x1
+
+ /* Setting NFC */
+ ldr r7, CCM_BASE_ADDR_W
+ ldr r1, [r7, #CLKCTL_RCSR]
+ /*BUS WIDTH setting*/
+ tst r1, #0x20000000
+ orrne r1, r1, #0x4000
+ biceq r1, r1, #0x4000
+
+ /*4K PAGE*/
+ tst r1, #0x10000000
+ orrne r1, r1, #0x200
+ bne 1f
+ /*2K PAGE*/
+ bic r1, r1, #0x200
+ tst r1, #0x08000000
+ orrne r1, r1, #0x100 /*2KB page size*/
+ biceq r1, r1, #0x100 /*512B page size*/
+ movne r2, #32 /*64 bytes*/
+ moveq r2, #8 /*16 bytes*/
+ b NAND_setup
+1:
+ tst r1, #0x08000000
+ bicne r3, r3, #1 /*Enable 8bit ECC mode*/
+ movne r2, #109 /*218 bytes*/
+ moveq r2, #64 /*128 bytes*/
+NAND_setup:
+ str r1, [r7, #CLKCTL_RCSR]
+ strh r2, [r12, #ECC_RSLT_SPARE_AREA_REG_OFF]
+ strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+
+ //unlock internal buffer
+ mov r3, #0x2
+ strh r3, [r12, #NFC_CONFIGURATION_REG_OFF]
+ //unlock nand device
+ mov r3, #0
+ strh r3, [r12, #UNLOCK_START_BLK_ADD_REG_OFF]
+ sub r3, r3, #1
+ strh r3, [r12, #UNLOCK_END_BLK_ADD_REG_OFF]
+ mov r3, #4
+ strh r3, [r12, #NF_WR_PROT_REG_OFF]
+
+ /* r0: NFC base address. RAM buffer base address. [constantly]
+ * r1: starting flash address to be copied. [constantly]
+ * r2: page size. [Doesn't change]
+ * r3: used as argument.
+ * r11: starting SDRAM address for copying. [Updated constantly].
+ * r12: NFC register base address. [constantly].
+ * r13: end of SDRAM address for copying. [Doesn't change].
+ */
+
+ mov r1, #0x1000
+ ldr r3, [r7, #CLKCTL_RCSR]
+ tst r3, #0x200
+ movne r2, #0x1000
+ bne 1f
+ tst r3, #0x100
+ mov r1, #0x800 /*Strang Why is not 4K offset*/
+ movne r2, #0x800
+ moveq r2, #0x200
+1: /*Update the indicator of copy area */
+ ldr r11, MXC_REDBOOT_ROM_START
+ add r13, r11, #REDBOOT_IMAGE_SIZE
+ add r11, r11, r1
+
+Nfc_Read_Page:
+ mov r3, #0x0
+ nfc_cmd_input
+
+ cmp r2, #0x800
+ bhi nfc_addr_ops_4kb
+ beq nfc_addr_ops_2kb
+
+ mov r3, r1
+ do_addr_input //1st addr cycle
+ mov r3, r1, lsr #9
+ do_addr_input //2nd addr cycle
+ mov r3, r1, lsr #17
+ do_addr_input //3rd addr cycle
+ mov r3, r1, lsr #25
+ do_addr_input //4th addr cycle
+ b end_of_nfc_addr_ops
+
+nfc_addr_ops_2kb:
+ mov r3, #0
+ do_addr_input //1st addr cycle
+ mov r3, #0
+ do_addr_input //2nd addr cycle
+ mov r3, r1, lsr #11
+ do_addr_input //3rd addr cycle
+ mov r3, r1, lsr #19
+ do_addr_input //4th addr cycle
+ mov r3, r1, lsr #27
+ do_addr_input //5th addr cycle
+
+ mov r3, #0x30
+ nfc_cmd_input
+ b end_of_nfc_addr_ops
+
+nfc_addr_ops_4kb:
+ mov r3, #0
+ do_addr_input //1st addr cycle
+ mov r3, #0
+ do_addr_input //2nd addr cycle
+ mov r3, r1, lsr #12
+ do_addr_input //3rd addr cycle
+ mov r3, r1, lsr #20
+ do_addr_input //4th addr cycle
+ mov r3, r1, lsr #27
+ do_addr_input //5th addr cycle
+
+ mov r3, #0x30
+ nfc_cmd_input
+
+end_of_nfc_addr_ops:
+ mov r8, #0
+ bl nfc_data_output
+ bl do_wait_op_done
+ // Check if x16/2kb page
+ cmp r2, #0x800
+ bhi nfc_addr_data_output_done_4k
+ beq nfc_addr_data_output_done_2k
+ beq nfc_addr_data_output_done_512
+
+ // check for bad block
+// mov r3, r1, lsl #(32-17) // get rid of block number
+// cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
+ b nfc_addr_data_output_done
+
+nfc_addr_data_output_done_4k:
+//TODO
+ b nfc_addr_data_output_done
+
+nfc_addr_data_output_done_2k:
+// end of 4th
+ // check for bad block
+//TODO mov r3, r1, lsl #(32-17) // get rid of block number
+// cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
+ b nfc_addr_data_output_done
+
+nfc_addr_data_output_done_512:
+ // check for bad block
+// TODO mov r3, r1, lsl #(32-5-9) // get rid of block number
+// TODO cmp r3, #(512 << (32-5-9)) // check if not page 0 or 1
+
+nfc_addr_data_output_done:
+#if 0
+ bhi Copy_Good_Blk
+ add r4, r0, #0x1000 //r3 -> spare area buf 0
+ ldrh r4, [r4, #0x4]
+ and r4, r4, #0xFF00
+ cmp r4, #0xFF00
+ beq Copy_Good_Blk
+ // really sucks. Bad block!!!!
+ cmp r3, #0x0
+ beq Skip_bad_block
+ // even suckier since we already read the first page!
+ // Check if x16/2kb page
+ cmp r2, #0x800
+ // for 4k page
+ subhi r11, r11, #0x1000 //rewind 1 page for the sdram pointer
+ subhi r1, r1, #0x1000 //rewind 1 page for the flash pointer
+ // for 2k page
+ subeq r11, r11, #0x800 //rewind 1 page for the sdram pointer
+ subeq r1, r1, #0x800 //rewind 1 page for the flash pointer
+ // for 512 page
+ sublo r11, r11, #512 //rewind 1 page for the sdram pointer
+ sublo r1, r1, #512 //rewind 1 page for the flash pointer
+Skip_bad_block:
+ // Check if x16/2kb page
+ ldr r7, CCM_BASE_ADDR_W
+ ldr r7, [r7, #CLKCTL_RCSR]
+ tst r7, #0x200
+ addne r1, r1, #(128*4096)
+ bne Skip_bad_block_done
+ tst r7, #0x100
+ addeq r1, r1, #(32*512)
+ addne r1, r1, #(64*2048)
+Skip_bad_block_done:
+ b Nfc_Read_Page
+#endif
+Copy_Good_Blk:
+ //copying page
+ add r2, r2, #NFC_BASE
+1: ldmia r0!, {r3-r10}
+ stmia r11!, {r3-r10}
+ cmp r0, r2
+ blo 1b
+ sub r2, r2, #NFC_BASE
+
+ cmp r11, r13
+ bge NAND_Copy_Main_done
+ // Check if x16/2kb page
+ add r1, r1, r2
+ mov r0, #NFC_BASE
+ b Nfc_Read_Page
+
+NAND_Copy_Main_done:
+
+Normal_Boot_Continue:
+
+#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
+ /* Copy image from flash to SDRAM first */
+ ldr r0, =0xFFFFF000
+ and r0, r0, pc
+ ldr r1, MXC_REDBOOT_ROM_START
+ cmp r0, r1
+ beq HWInitialise_skip_SDRAM_copy
+
+ add r2, r0, #REDBOOT_IMAGE_SIZE
+
+1: ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ ble 1b
+ /* Jump to SDRAM */
+ ldr r1, =0xFFFF
+ and r0, pc, r1 /* offset of pc */
+ ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
+ add pc, r0, r1
+ nop
+ nop
+ nop
+ nop
+#endif /* CYG_HAL_STARTUP_ROMRAM */
+
+HWInitialise_skip_SDRAM_copy:
+ init_cs0
+
+/*
+ * Note:
+ * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
+ */
+
+STACK_Setup:
+ // Set up a stack [for calling C code]
+ ldr r1, =__startup_stack
+ ldr r2, =RAM_BANK0_BASE
+ orr sp, r1, r2
+
+ // Create MMU tables
+ bl hal_mmu_init
+
+ // Enable MMU
+ ldr r2, =10f
+ mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
+ orr r1, r1, #7 // enable MMU bit
+ orr r1, r1, #0x800 // enable z bit
+ mcr MMU_CP, 0, r1, MMU_Control, c0
+ mov pc,r2 /* Change address spaces */
+ nop
+ nop
+ nop
+10:
+
+ // Save shadow copy of BCR, also hardware configuration
+ ldr r1, =_board_BCR
+ str r2, [r1]
+ ldr r1, =_board_CFG
+ str r9, [r1] // Saved far above...
+
+ .endm // _platform_setup1
+
+do_wait_op_done:
+ 1:
+ ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
+ beq 1b
+ bx lr // do_wait_op_done
+
+nfc_data_output:
+ ldrh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+ orr r3, r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
+ strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+
+ strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
+
+ mov r3, #FDO_PAGE_SPARE_VAL
+ strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ bx lr
+
+#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1
+#endif
+
+ /* Do nothing */
+ .macro init_spba
+ .endm /* init_spba */
+
+ /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
+ .macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, AIPS1_CTRL_BASE_ADDR_W
+ ldr r1, AIPS1_PARAM_W
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ ldr r0, AIPS2_CTRL_BASE_ADDR_W
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+
+ /*
+ * Clear the on and off peripheral modules Supervisor Protect bit
+ * for SDMA to access them. Did not change the AIPS control registers
+ * (offset 0x20) access type
+ */
+ ldr r0, AIPS1_CTRL_BASE_ADDR_W
+ ldr r1, =0x0
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ ldr r1, [r0, #0x50]
+ and r1, r1, #0x00FFFFFF
+ str r1, [r0, #0x50]
+
+ ldr r0, AIPS2_CTRL_BASE_ADDR_W
+ ldr r1, =0x0
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ ldr r1, [r0, #0x50]
+ and r1, r1, #0x00FFFFFF
+ str r1, [r0, #0x50]
+ .endm /* init_aips */
+
+ /* MAX (Multi-Layer AHB Crossbar Switch) setup */
+ .macro init_max
+ ldr r0, MAX_BASE_ADDR_W
+ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+ ldr r1, MAX_PARAM1
+ str r1, [r0, #0x000] /* for S0 */
+ str r1, [r0, #0x100] /* for S1 */
+ str r1, [r0, #0x200] /* for S2 */
+ str r1, [r0, #0x300] /* for S3 */
+ str r1, [r0, #0x400] /* for S4 */
+ /* SGPCR - always park on last master */
+ ldr r1, =0x10
+ str r1, [r0, #0x010] /* for S0 */
+ str r1, [r0, #0x110] /* for S1 */
+ str r1, [r0, #0x210] /* for S2 */
+ str r1, [r0, #0x310] /* for S3 */
+ str r1, [r0, #0x410] /* for S4 */
+ /* MGPCR - restore default values */
+ ldr r1, =0x0
+ str r1, [r0, #0x800] /* for M0 */
+ str r1, [r0, #0x900] /* for M1 */
+ str r1, [r0, #0xA00] /* for M2 */
+ str r1, [r0, #0xB00] /* for M3 */
+ str r1, [r0, #0xC00] /* for M4 */
+ str r1, [r0, #0xD00] /* for M5 */
+ .endm /* init_max */
+
+ /* Clock setup */
+ .macro init_clock
+ ldr r0, CCM_BASE_ADDR_W
+
+ /* default CLKO to 1/32 of the ARM core*/
+ ldr r1, [r0, #CLKCTL_COSR]
+ bic r1, r1, #0x00000FF00
+ bic r1, r1, #0x0000000FF
+ mov r2, #0x00006C00
+ add r2, r2, #0x67
+ orr r1, r1, r2
+ str r1, [r0, #CLKCTL_COSR]
+
+ ldr r2, CCM_CCMR_W
+ str r2, [r0, #CLKCTL_CCMR]
+
+ /*check clock path*/
+ ldr r3, ROM_VER_ADDR_W
+ ldr r4, [r3]
+ cmp r4, #0x1
+ ldreq r2, [r0, #CLKCTL_PDR0]
+ movne r2, #0x1
+ tst r2, #0x1
+ ldrne r3, MPCTL_PARAM_532_W /* consumer path*/
+ ldreq r3, MPCTL_PARAM_399_W /* auto path*/
+
+ /*Set MPLL , arm clock and ahb clock*/
+ str r3, [r0, #CLKCTL_MPCTL]
+
+ ldr r1, PPCTL_PARAM_W
+ str r1, [r0, #CLKCTL_PPCTL]
+
+ cmp r4, #0x1
+ ldreq r1, [r0, #CLKCTL_PDR0]
+ orreq r1, r1, #0x800000
+ streq r1, [r0, #CLKCTL_PDR0]
+
+ ldr r1, CCM_PDR0_W
+ bicne r1, r1, #0x800000
+ str r1, [r0, #CLKCTL_PDR0]
+
+ ldr r1, [r0, #CLKCTL_CGR0]
+ orr r1, r1, #0x00300000
+ str r1, [r0, #CLKCTL_CGR0]
+
+ ldr r1, [r0, #CLKCTL_CGR1]
+ orr r1, r1, #0x00000C00
+ orr r1, r1, #0x00000003
+ str r1, [r0, #CLKCTL_CGR1]
+
+ .endm /* init_clock */
+
+ /* M3IF setup */
+ .macro init_m3if
+ /* Configure M3IF registers */
+ ldr r1, M3IF_BASE_W
+ /*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = USB not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = GPU not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+ ldr r0, =0x00000040
+ str r0, [r1] /* M3IF control reg */
+ .endm /* init_m3if */
+
+ .macro init_cs0
+ ldr r0, WEIM_CTRL_CS0_W
+ ldr r1, CS0_CSCRU_0x0000CC03
+ str r1, [r0, #CSCRU]
+ ldr r1, CS0_CSCRL_0xA0330D01
+ str r1, [r0, #CSCRL]
+ ldr r1, CS0_CSCRA_0x00220800
+ str r1, [r0, #CSCRA]
+ .endm
+
+ /* CPLD on CS5 setup */
+ .macro init_cs5
+ ldr r0, WEIM_CTRL_CS5_W
+ ldr r1, CS5_CSCRU_0x0000D843
+ str r1, [r0, #CSCRU]
+ ldr r1, CS5_CSCRL_0x22252521
+ str r1, [r0, #CSCRL]
+ ldr r1, CS5_CSCRA_0x22220A00
+ str r1, [r0, #CSCRA]
+ .endm /* init_cs5 */
+
+ .macro setup_sdram
+ ldr r0, ESDCTL_BASE_W
+ mov r3, #0x2000
+ str r3, [r0, #0x0]
+ ldr r2, ROM_VER_ADDR_W
+ ldr r4, [r2]
+ cmp r4, #0x1
+ streq r3, [r0, #0x8]
+
+ mov r12, #0x00
+ mov r2, #0x00
+ mov r1, #RAM_BANK0_BASE
+ bl setup_sdram_bank
+ cmp r3, #0x0
+ orreq r12, r12, #1
+ eorne r2, r2, #0x1
+ blne setup_sdram_bank
+#if 0
+ /* CSD1 */
+ mov r1, #RAM_BANK1_BASE
+ bl setup_sdram_bank
+ cmp r3, #0x0
+ beq 1b
+ eorne r2, r2, #0x1
+ blne setup_sdram_bank
+ orr r12, r12, #1
+1:
+#endif
+ cmp r12, #0
+ movne r3, #L2CC_BASE_ADDR
+ ldrne r4, [r3, #L2_CACHE_AUX_CTL_REG]
+ orrne r4, r4, #0x1000
+ strne r4, [r3, #L2_CACHE_AUX_CTL_REG]
+
+ ldr r3, ESDCTL_DELAY5
+ str r3, [r0, #0x30]
+ .endm
+
+ .macro nfc_cmd_input
+ strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
+ mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
+ strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ bl do_wait_op_done
+ .endm // nfc_cmd_input
+
+ .macro do_addr_input
+ and r3, r3, #0xFF
+ strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
+ mov r3, #NAND_FLASH_CONFIG2_FADD_EN
+ strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ bl do_wait_op_done
+ .endm // do_addr_input
+
+ /* To support 133MHz DDR */
+ .macro init_iomuxc
+ mov r0, #0x2
+ ldr r1, IOMUXC_BASE_ADDR_W
+ add r1, r1, #0x368
+ add r2, r1, #0x4C8 - 0x368
+1: str r0, [r1], #4
+ cmp r1, r2
+ ble 1b
+ .endm /* init_iomuxc */
+
+/*
+ * r0: control base, r1: ram bank base
+ * r2: ddr type(0:DDR2, 1:MDDR) r3, r4: working
+ */
+setup_sdram_bank:
+ mov r3, #0xE /*0xA + 0x4*/
+ tst r2, #0x1
+ orreq r3, r3, #0x300 /*DDR2*/
+ str r3, [r0, #0x10]
+ bic r3, r3, #0x00A
+ str r3, [r0, #0x10]
+ beq 2f
+
+ mov r3, #0x20000
+1: subs r3, r3, #1
+ bne 1b
+
+2: adr r4, ESDCTL_CONFIG
+ tst r2, #0x1
+ ldreq r3, [r4, #0x0]
+ ldrne r3, [r4, #0x4]
+ cmp r1, #RAM_BANK1_BASE
+ strlo r3, [r0, #0x4]
+ strhs r3, [r0, #0xC]
+
+ ldr r3, ESDCTL_0x92220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ mov r3, #0xDA
+ ldr r4, RAM_PARAM1_MDDR
+ strb r3, [r1, r4]
+
+ tst r2, #0x1
+ bne skip_set_mode
+
+ cmp r1, #RAM_BANK1_BASE
+ ldr r3, ESDCTL_0xB2220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ mov r3, #0xDA
+ ldr r4, RAM_PARAM4_MDDR
+ strb r3, [r1, r4]
+ ldr r4, RAM_PARAM5_MDDR
+ strb r3, [r1, r4]
+ ldr r4, RAM_PARAM3_MDDR
+ strb r3, [r1, r4]
+ ldr r4, RAM_PARAM2_MDDR
+ strb r3, [r1, r4]
+
+ ldr r3, ESDCTL_0x92220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ mov r3, #0xDA
+ ldr r4, RAM_PARAM1_MDDR
+ strb r3, [r1, r4]
+
+skip_set_mode:
+ cmp r1, #RAM_BANK1_BASE
+ ldr r3, ESDCTL_0xA2220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ mov r3, #0xDA
+ strb r3, [r1]
+ strb r3, [r1]
+
+ ldr r3, ESDCTL_0xB2220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ adr r4, RAM_PARAM6_MDDR
+ tst r2, #0x1
+ ldreq r4, [r4, #0x0]
+ ldrne r4, [r4, #0x4]
+ mov r3, #0xDA
+ strb r3, [r1, r4]
+ ldreq r4, RAM_PARAM7_MDDR
+ streqb r3, [r1, r4]
+ adr r4, RAM_PARAM3_MDDR
+ ldreq r4, [r4, #0x0]
+ ldrne r4, [r4, #0x4]
+ strb r3, [r1, r4]
+
+ cmp r1, #RAM_BANK1_BASE
+ ldr r3, ESDCTL_0x82226080
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+
+ tst r2, #0x1
+ moveq r4, #0x20000
+ movne r4, #0x200
+1: subs r4, r4, #1
+ bne 1b
+
+ str r3, [r1, #0x100]
+ ldr r4, [r1, #0x100]
+ cmp r3, r4
+ movne r3, #1
+ moveq r3, #0
+
+ mov pc, lr
+
+#define PLATFORM_VECTORS _platform_vectors
+ .macro _platform_vectors
+ .globl _board_BCR, _board_CFG
+_board_BCR: .long 0 // Board Control register shadow
+_board_CFG: .long 0 // Board Configuration (read at RESET)
+ .endm
+
+//Internal Boot, from MMC/SD cards
+#ifdef MXCFLASH_SELECT_MMC
+#define DCDGEN(i,type, addr, data) \
+dcd_##i: ;\
+ .long type ;\
+ .long addr ;\
+ .long data
+
+#define FHEADER_OFFSET 0x400
+#if 0
+#define GEN_FHEADERADDR(x) ((x) + FHEADER_OFFSET)
+#else
+#define GEN_FHEADERADDR(x) (x)
+#endif
+
+ .macro setup_flash_header
+ b reset_vector
+ // .org 0x400
+#if defined(FHEADER_OFFSET)
+ .org FHEADER_OFFSET
+#endif
+app_code_jump_v: .long GEN_FHEADERADDR(reset_vector)
+app_code_barker: .long 0xB1
+app_code_csf: .long 0
+hwcfg_ptr_ptr: .long GEN_FHEADERADDR(hwcfg_ptr)
+super_root_key: .long 0
+hwcfg_ptr: .long GEN_FHEADERADDR(dcd_data)
+app_dest_ptr: .long SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
+dcd_data: .long 0xB17219E9
+#ifdef MEMORY_MDDR_ENABLE
+ .long 228
+//real dcd data
+
+//arm clock is 266Mhz and ahb clock is 133Mhz
+//DCDGEN(1, 4, 0x53F80004, 0x00821000)
+
+//WEIM config-CS5 init
+DCDGEN(1, 4, 0xB8002054, 0x444a4541)
+DCDGEN(1_1, 4, 0xB8002050, 0x0000dcf6)
+DCDGEN(1_2, 4, 0xB8002058, 0x44443302)
+//MDDR init
+//enable mDDR
+DCDGEN(2, 4, 0xB8001010, 0x00000004)
+//reset delay time
+DCDGEN(3, 4, 0xB8001010, 0x0000000C)
+DCDGEN(4, 4, 0xB800100C, 0x007ffc3f)
+DCDGEN(5, 4, 0xB800100C, 0x007ffc3f)
+DCDGEN(6, 4, 0xB8001004, 0x007ffc3f)
+DCDGEN(7, 4, 0xB8001000, 0x92220000)
+DCDGEN(8, 1, 0x80000400, 0xda)
+DCDGEN(9, 4, 0xB8001000, 0xA2220000)
+DCDGEN(10, 4, 0x80000000, 0x87654321)
+DCDGEN(11, 4, 0x80000000, 0x87654321)
+DCDGEN(12, 4, 0xB8001000, 0xB2220000)
+DCDGEN(13, 1, 0x80000033, 0xda)
+DCDGEN(14, 1, 0x82000000, 0xda)
+DCDGEN(15, 4, 0xB8001000, 0x82226080)
+DCDGEN(16, 4, 0xB8001010, 0x00000004)
+DCDGEN(17, 4, 0xB8001008, 0x00002000)
+
+//add MMC FLASH BOOT mode in MXCFIS_FLAG_REG
+//DCDGEN(18, 4, 0x68000100, 0x40000000)
+
+#else
+ .long 240
+
+//arm clock is 266Mhz and ahb clock is 133Mhz
+//DCDGEN(1, 4, 0x53F80004, 0x00821000)
+
+//WEIM config-CS5 init
+DCDGEN(1, 4, 0xB8002050, 0x0000d843)
+DCDGEN(1_1, 4, 0xB8002054, 0x22252521)
+DCDGEN(1_2, 4, 0xB8002058, 0x22220a00)
+
+//DDR2 init
+DCDGEN(2, 4, 0xB8001010, 0x00000304)
+DCDGEN(3, 4, 0xB8001010, 0x0000030C)
+DCDGEN(4, 4, 0xB8001004, 0x007ffc3f)
+DCDGEN(5, 4, 0xB8001000, 0x92220000)
+DCDGEN(6, 4, 0x80000400, 0x12345678)
+DCDGEN(7, 4, 0xB8001000, 0xA2220000)
+DCDGEN(8, 4, 0x80000000, 0x87654321)
+DCDGEN(9, 4, 0x80000000, 0x87654321)
+DCDGEN(10, 4, 0xB8001000, 0xB2220000)
+DCDGEN(11, 1, 0x80000233, 0xda)
+DCDGEN(12, 1, 0x82000780, 0xda)
+DCDGEN(13, 1, 0x82000400, 0xda)
+DCDGEN(14, 4, 0xB8001000, 0x82226080)
+DCDGEN(15, 4, 0xB8001004, 0x007ffc3f)
+DCDGEN(16, 4, 0xB800100C, 0x007ffc3f)
+DCDGEN(17, 4, 0xB8001010, 0x00000304)
+DCDGEN(18, 4, 0xB8001008, 0x00002000)
+
+//add MMC FLASH BOOT mode in MXCFIS_FLAG_REG
+//DCDGEN(17, 4, #MMC_FLASH_BOOT, #MXCBOOT_FLAG_REG)
+//DCDGEN(19, 4, 0x68000100, 0x40000000)
+#endif
+
+//CARD_FLASH_CFG_PARMS_T---length
+card_cfg: .long REDBOOT_IMAGE_SIZE
+ .endm
+#endif
+
+ARM_PPMRR: .word 0x40000015
+L2CACHE_PARAM: .word 0x00030024
+IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
+AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
+AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
+AIPS1_PARAM_W: .word 0x77777777
+MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
+MAX_PARAM1: .word 0x00302154
+CLKCTL_BASE_ADDR_W: .word CLKCTL_BASE_ADDR
+ESDCTL_BASE_W: .word ESDCTL_BASE
+M3IF_BASE_W: .word M3IF_BASE
+RAM_PARAM1_MDDR: .word 0x00000400
+RAM_PARAM2_MDDR: .word 0x00000333
+RAM_PARAM3_MDDR: .word 0x02000400
+ .word 0x02000000
+RAM_PARAM4_MDDR: .word 0x04000000
+RAM_PARAM5_MDDR: .word 0x06000000
+RAM_PARAM6_MDDR: .word 0x00000233
+ .word 0x00000033
+RAM_PARAM7_MDDR: .word 0x02000780
+ESDCTL_0x92220000: .word 0x92220000
+ESDCTL_0xA2220000: .word 0xA2220000
+ESDCTL_0xB2220000: .word 0xB2220000
+ESDCTL_0x82226080: .word 0x82226080
+ESDCTL_CONFIG: .word 0x007FFC3F //DDR2
+ .word 0x00295729 //MDDR
+ESDCTL_DELAY5: .word 0x00F49F00
+IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
+CCM_CCMR_W: .word 0x003F4208
+CCM_PDR0_W: .word 0x00801000
+MPCTL_PARAM_399_W: .word MPCTL_PARAM_399
+MPCTL_PARAM_532_W: .word MPCTL_PARAM_532
+PPCTL_PARAM_W: .word PPCTL_PARAM_300
+AVIC_VECTOR0_ADDR_W: .word MXCBOOT_FLAG_REG
+AVIC_VECTOR1_ADDR_W: .word MXCFIS_FLAG_REG
+MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
+CONST_0x0FFF: .word 0x0FFF
+CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
+IPU_CTRL_BASE_ADDR_W: .word IPU_CTRL_BASE_ADDR
+WEIM_CTRL_CS5_W: .word WEIM_CTRL_CS5
+WEIM_CTRL_CS0_W: .word WEIM_CTRL_CS0
+CS0_CSCRU_0x0000CC03: .word 0x0000DCF6
+CS0_CSCRL_0xA0330D01: .word 0x444A4541
+CS0_CSCRA_0x00220800: .word 0x44443302
+CS5_CSCRU_0x0000D843: .word 0x0000D843
+CS5_CSCRL_0x22252521: .word 0x22252521
+CS5_CSCRA_0x22220A00: .word 0x22220A00
+ROM_VER_ADDR_W: .word ROM_BASE_ADDR + ROM_SI_REV_OFFSET
+/*---------------------------------------------------------------------------*/
+/* end of hal_platform_setup.h */
+#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x00000000)
+#define CYGMEM_REGION_ram_SIZE (0x7F00000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0x87F00000)
+#define CYGMEM_REGION_rom_SIZE (0x100000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ ram : ORIGIN = 0, LENGTH = 0x7F00000
+ rom : ORIGIN = 0x87F00000, LENGTH = 0x100000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_rom_vectors (rom, 0x87F00000, LMA_EQ_VMA)
+ SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
+ SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table))
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
--- /dev/null
+version 0
+region ram 0 7F00000 0 !
+region rom 87F00000 100000 1 !
+section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
+section data 0 1 1 1 1 1 0 0 8000 bss !
+section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
+section heap1 0 8 0 0 0 0 0 0 !
+section rom_vectors 0 1 0 1 1 1 1 1 87F00000 87F00000 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata rodata !
+section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 4 0 1 0 0 0 1 data !
--- /dev/null
+#ifndef CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+#define CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+
+//=============================================================================
+//
+// plf_io.h
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/hal/fsl_board.h>
+#include <cyg/hal/hal_soc.h>
+
+#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \
+ CYG_MACRO_START \
+ { \
+ extern unsigned int system_rev; \
+ /* Next ATAG_MEM. */ \
+ _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_MEM; \
+ /* Round up so there's only one bit set in the memory size. \
+ * Don't double it if it's already a power of two, though. \
+ */ \
+ _p_->u.mem.size = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE); \
+ if (_p_->u.mem.size < (CYGMEM_REGION_ram_SIZE)) \
+ _p_->u.mem.size <<= 1; \
+ _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram); \
+ _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size); \
+ _p_->hdr.size = ((sizeof(struct tag_revision)) + sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_REVISION; \
+ _p_->u.revision.rev = system_rev; \
+ } \
+ CYG_MACRO_END
+#endif // CYGONCE_HAL_ARM_BOARD_PLF_IO_H
--- /dev/null
+#ifndef CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+#define CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+//=============================================================================
+//
+// plf_mmap.h
+//
+// Platform specific memory map support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_misc.h>
+
+// Get the pagesize for a particular virtual address:
+
+// This does not depend on the vaddr.
+#define HAL_MM_PAGESIZE(vaddr, pagesize) CYG_MACRO_START \
+ (pagesize) = SZ_1M; \
+CYG_MACRO_END
+
+// Get the physical address from a virtual address:
+
+#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START \
+ cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
+ if ( _v_ < 128 * SZ_1M ) /* SDRAM */ \
+ _v_ += SDRAM_BASE_ADDR; \
+ else /* Rest of it */ \
+ /* no change */ ; \
+ (paddr) = _v_; \
+CYG_MACRO_END
+
+/*
+ * translate the virtual address of ram space to physical address
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
+{
+ if(virt < 0x08000000) {
+ return virt|0x80000000;
+ }
+ if((virt & 0xF0000000) == 0x80000000) {
+ return virt&(~0x08000000);
+ }
+ return virt;
+}
+
+/*
+ * remap the physical address of ram space to uncacheable virtual address space
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
+{
+ /* 0x88000000~0x87FFFFFF is uncacheable meory space which is mapped to SDRAM*/
+ if((phy & 0xF0000000) == 0x80000000) {
+ phy |= 0x08000000;
+ }
+ return phy;
+}
+
+//---------------------------------------------------------------------------
+#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
--- /dev/null
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware mx35_3stack ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM current ;
+ package -hardware CYGPKG_HAL_ARM_MX35 current ;
+ package -hardware CYGPKG_HAL_ARM_MX35_3STACK current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ;
+ package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ;
+ package -hardware CYGPKG_DEVS_ETH_FEC current ;
+ package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ;
+ package -hardware CYGPKG_COMPRESS_ZLIB current ;
+ package -hardware CYGPKG_DIAGNOSIS current ;
+ package -hardware CYGPKG_IO_FLASH current ;
+ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+ package -hardware CYGPKG_DEVS_FLASH_IMX_3STACK_SPANSION current ;
+# package -hardware CYGPKG_DEVS_MXC_SPI current ;
+ package -hardware CYGPKG_DEVS_MXC_I2C current ;
+ package -hardware CYGPKG_DEVS_PMIC_ARM_IMX35_3STACK current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package CYGPKG_MEMALLOC current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL512N {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+ inferred_value 1
+};
+
+#cdl_option CYGHWR_DEVS_FSL_SPI_VER_0_7 {
+# inferred_value 1
+#};
+
+cdl_option CYGHWR_DEVS_PMIC_I2C {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_PMIC_I2C_PORT {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_PMIC_I2C_ADDR {
+ inferred_value 0x69
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MMC {
+ inferred_value 1
+};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+ inferred_value 3
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
+ user_value 50
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ inferred_value 0x00040000
+};
+
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+ inferred_value 0x80008000
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_component CYG_HAL_STARTUP {
+ user_value ROMRAM
+};
+
+cdl_component CYGPKG_MEMORY_DIAGNOSIS {
+ user_value 1
+};
+
+cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+ inferred_value 1
+};
+
+
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+ user_value 1 "FSL 200904"
+};
--- /dev/null
+/*=============================================================================
+//
+// board_diag.c
+//
+// HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_arch.h> // basic machine info
+#include <cyg/hal/hal_intr.h> // interrupt macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_if.h> // Calling-if API
+#include <cyg/hal/drv_api.h> // driver API
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/fsl_board.h> // Platform specifics
+
+static void cyg_hal_plf_duart_init(void);
+extern void cyg_hal_plf_serial_init(void);
+
+#define DUART_WORKAROUND_DELAY(a) hal_delay_us(a);
+
+
+void cyg_hal_plf_comms_init(void)
+{
+ static int initialized = 0;
+
+ if (initialized)
+ return;
+
+ initialized = 1;
+
+ /* Setup GPIO and enable transceiver for UARTs */
+// cyg_hal_plf_duart_init();
+ cyg_hal_plf_serial_init();
+}
+
+//=============================================================================
+// ST16552 DUART driver
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// There are two serial ports.
+#define CYG_DEV_SERIAL_BASE_A (BOARD_CS_UART_BASE + 0x0000) // port A
+#define CYG_DEV_SERIAL_BASE_B (BOARD_CS_UART_BASE + 0x8000) // port B
+
+//-----------------------------------------------------------------------------
+// Based on 14.7456 MHz xtal
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x60
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x30
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x18
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x10
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x08
+#endif
+
+#ifndef CYG_DEV_SERIAL_BAUD_MSB
+#error Missing/incorrect serial baud rate defined - CDL error?
+#endif
+
+//-----------------------------------------------------------------------------
+// Define the serial registers. The board is equipped with a 16552
+// serial chip.
+
+#ifdef EXT_UART_x16
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT16
+#define HAL_READ_UINT_UART HAL_READ_UINT16
+typedef cyg_uint16 uart_width;
+#else //_x8
+typedef cyg_uint8 uart_width;
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT8
+#define HAL_READ_UINT_UART HAL_READ_UINT8
+#endif
+
+#define CYG_DEV_SERIAL_RHR 0x00 // receiver buffer register, read, dlab = 0
+#define CYG_DEV_SERIAL_THR 0x00 // transmitter holding register, write, dlab = 0
+#define CYG_DEV_SERIAL_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IER 0x01 // interrupt enable register, read/write, dlab = 0
+#define CYG_DEV_SERIAL_DLM 0x01 // divisor latch (MS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IIR 0x02 // interrupt identification register, read, dlab = 0
+#define CYG_DEV_SERIAL_FCR 0x02 // fifo control register, write, dlab = 0
+#define CYG_DEV_SERIAL_AFR 0x02 // alternate function register, read/write, dlab = 1
+#define CYG_DEV_SERIAL_LCR 0x03 // line control register, read/write
+#define CYG_DEV_SERIAL_MCR 0x04
+#define CYG_DEV_SERIAL_MCR_A 0x04
+#define CYG_DEV_SERIAL_MCR_B 0x04
+#define CYG_DEV_SERIAL_LSR 0x05 // line status register, read
+#define CYG_DEV_SERIAL_MSR 0x06 // modem status register, read
+#define CYG_DEV_SERIAL_SCR 0x07 // scratch pad register
+
+// The interrupt enable register bits.
+#define SIO_IER_ERDAI 0x01 // enable received data available irq
+#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
+#define SIO_IER_ELSI 0x04 // enable receiver line status irq
+#define SIO_IER_EMSI 0x08 // enable modem status interrupt
+
+// The interrupt identification register bits.
+#define SIO_IIR_IP 0x01 // 0 if interrupt pending
+#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
+#define ISR_Tx 0x02
+#define ISR_Rx 0x04
+
+// The line status register bits.
+#define SIO_LSR_DR 0x01 // data ready
+#define SIO_LSR_OE 0x02 // overrun error
+#define SIO_LSR_PE 0x04 // parity error
+#define SIO_LSR_FE 0x08 // framing error
+#define SIO_LSR_BI 0x10 // break interrupt
+#define SIO_LSR_THRE 0x20 // transmitter holding register empty
+#define SIO_LSR_TEMT 0x40 // transmitter register empty
+#define SIO_LSR_ERR 0x80 // any error condition
+
+// The modem status register bits.
+#define SIO_MSR_DCTS 0x01 // delta clear to send
+#define SIO_MSR_DDSR 0x02 // delta data set ready
+#define SIO_MSR_TERI 0x04 // trailing edge ring indicator
+#define SIO_MSR_DDCD 0x08 // delta data carrier detect
+#define SIO_MSR_CTS 0x10 // clear to send
+#define SIO_MSR_DSR 0x20 // data set ready
+#define SIO_MSR_RI 0x40 // ring indicator
+#define SIO_MSR_DCD 0x80 // data carrier detect
+
+// The line control register bits.
+#define SIO_LCR_WLS0 0x01 // word length select bit 0
+#define SIO_LCR_WLS1 0x02 // word length select bit 1
+#define SIO_LCR_STB 0x04 // number of stop bits
+#define SIO_LCR_PEN 0x08 // parity enable
+#define SIO_LCR_EPS 0x10 // even parity select
+#define SIO_LCR_SP 0x20 // stick parity
+#define SIO_LCR_SB 0x40 // set break
+#define SIO_LCR_DLAB 0x80 // divisor latch access bit
+
+// The FIFO control register
+#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
+#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
+#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
+
+//-----------------------------------------------------------------------------
+
+typedef struct {
+ uart_width* base;
+ cyg_int32 msec_timeout;
+ int isr_vector;
+} channel_data_t;
+
+static channel_data_t channels[] = {
+#if CYGHWR_HAL_ARM_DUART_UARTA != 0
+ {(uart_width*)CYG_DEV_SERIAL_BASE_A, 1000, 0},
+#endif
+#if CYGHWR_HAL_ARM_DUART_UARTB != 0
+ {(uart_width*)CYG_DEV_SERIAL_BASE_B, 1000, 0}
+#endif
+};
+
+//-----------------------------------------------------------------------------
+
+static void init_duart_channel(channel_data_t* __ch_data)
+{
+ uart_width* base = __ch_data->base;
+ uart_width lcr;
+
+ // 8-1-no parity.
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR,
+ SIO_LCR_WLS0 | SIO_LCR_WLS1);
+ DUART_WORKAROUND_DELAY(50);
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ lcr |= SIO_LCR_DLAB;
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLL, CYG_DEV_SERIAL_BAUD_LSB);
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLM, CYG_DEV_SERIAL_BAUD_MSB);
+ lcr &= ~SIO_LCR_DLAB;
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_FCR, 0x07); // Enable & clear FIFO
+}
+
+//#define x_debug_uart_log_buf
+#ifdef x_debug_uart_log_buf
+#define x_DIAG_BUFSIZE 2048
+static char __x_log_buf[x_DIAG_BUFSIZE];
+static int x_diag_bp = 0;
+#endif
+
+void cyg_hal_plf_duart_putc(void* __ch_data, cyg_uint8 c)
+{
+ uart_width* base = ((channel_data_t*)__ch_data)->base;
+ uart_width lsr;
+
+#ifdef x_debug_uart_log_buf
+ __x_log_buf[x_diag_bp++] = c;
+#endif
+ CYGARC_HAL_SAVE_GP();
+
+ do {
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ } while ((lsr & SIO_LSR_THRE) == 0);
+
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_THR, c);
+
+ // Hang around until the character has been safely sent.
+ do {
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ } while ((lsr & SIO_LSR_THRE) == 0);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool cyg_hal_plf_duart_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+ uart_width* base = ((channel_data_t*)__ch_data)->base;
+ uart_width lsr, ch16;
+
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ if ((lsr & SIO_LSR_DR) == 0)
+ return false;
+
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_RHR, ch16);
+
+ *ch = (cyg_uint8) (ch16 & 0x00FF);
+
+ return true;
+}
+
+cyg_uint8 cyg_hal_plf_duart_getc(void* __ch_data)
+{
+ cyg_uint8 ch;
+
+ CYGARC_HAL_SAVE_GP();
+
+ while (!cyg_hal_plf_duart_getc_nonblock(__ch_data, &ch));
+
+ CYGARC_HAL_RESTORE_GP();
+ return ch;
+}
+
+static void cyg_hal_plf_duart_write(void* __ch_data, const cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while (__len-- > 0)
+ cyg_hal_plf_duart_putc(__ch_data, *__buf++);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static void cyg_hal_plf_duart_read(void* __ch_data, cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while (__len-- > 0)
+ *__buf++ = cyg_hal_plf_duart_getc(__ch_data);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool cyg_hal_plf_duart_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+ int delay_count;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_bool res;
+
+ CYGARC_HAL_SAVE_GP();
+
+ delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+ for (;;) {
+ res = cyg_hal_plf_duart_getc_nonblock(__ch_data, ch);
+ if (res || 0 == delay_count--)
+ break;
+
+ CYGACC_CALL_IF_DELAY_US(100);
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static int cyg_hal_plf_duart_control(void *__ch_data,
+ __comm_control_cmd_t __func, ...)
+{
+ static int irq_state = 0;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ uart_width ier;
+ int ret = 0;
+
+ CYGARC_HAL_SAVE_GP();
+
+ switch (__func) {
+ case __COMMCTL_IRQ_ENABLE:
+ HAL_INTERRUPT_UNMASK(chan->isr_vector);
+ HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ ier |= SIO_IER_ERDAI;
+ HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ irq_state = 1;
+ break;
+ case __COMMCTL_IRQ_DISABLE:
+ ret = irq_state;
+ irq_state = 0;
+ HAL_INTERRUPT_MASK(chan->isr_vector);
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ ier &= ~SIO_IER_ERDAI;
+ HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ break;
+ case __COMMCTL_DBG_ISR_VECTOR:
+ ret = chan->isr_vector;
+ break;
+ case __COMMCTL_SET_TIMEOUT:
+ {
+ va_list ap;
+
+ va_start(ap, __func);
+
+ ret = chan->msec_timeout;
+ chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+ va_end(ap);
+ }
+ break;
+ default:
+ break;
+ }
+ CYGARC_HAL_RESTORE_GP();
+ return ret;
+}
+
+static int cyg_hal_plf_duart_isr(void *__ch_data, int* __ctrlc,
+ CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ uart_width _iir;
+ int res = 0;
+ CYGARC_HAL_SAVE_GP();
+
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IIR, _iir);
+ _iir &= SIO_IIR_ID_MASK;
+
+ *__ctrlc = 0;
+ if ( ISR_Rx == _iir ) {
+ uart_width c, lsr;
+ cyg_uint8 c8;
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_LSR, lsr);
+ if (lsr & SIO_LSR_DR) {
+
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_RHR, c);
+
+ c8 = (cyg_uint8) (c & 0x00FF);
+
+ if (cyg_hal_is_break( &c8 , 1 ))
+ *__ctrlc = 1;
+ }
+
+ // Acknowledge the interrupt
+ HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+ res = CYG_ISR_HANDLED;
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static void cyg_hal_plf_duart_init(void)
+{
+ hal_virtual_comm_table_t* comm;
+ int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ int i;
+
+ // Init channels
+#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
+ for (i = 0; i < NUMOF(channels); i++) {
+ HAL_INTERRUPT_MASK(channels[i].isr_vector);
+ init_duart_channel(&channels[i]);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_duart_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_duart_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_duart_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_duart_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_duart_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_duart_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_duart_getc_timeout);
+ }
+
+ // Restore original console
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
+
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
+#define __BASE CMA101_DUARTA
+#define _INT CYGNUM_HAL_INTERRUPT_SERIAL_A
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1)
+#define __BASE CMA101_DUARTB
+#define _INT CYGNUM_HAL_INTERRUPT_SERIAL_B
+#endif
+
+#ifdef __BASE
+
+#ifdef CYGSEM_HAL_ROM_MONITOR
+#define CYG_HAL_STARTUP_ROM
+#define CYG_HAL_STARTUP_ROMRAM
+#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#endif
+
+#if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define HAL_DIAG_USES_HARDWARE
+#elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
+#define HAL_DIAG_USES_HARDWARE
+#elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+#define HAL_DIAG_USES_HARDWARE
+#endif
+
+static channel_data_t channel = {
+ (uart_width*) _BASE, 0, 0
+};
+
+#ifdef HAL_DIAG_USES_HARDWARE
+
+void hal_diag_init(void)
+{
+ static int init = 0;
+ char *msg = "\n\rARM eCos\n\r";
+ uart_width lcr;
+
+ if (init++) return;
+
+ init_duart_channel(&channel);
+
+ while (*msg) hal_diag_write_char(*msg++);
+}
+
+#ifdef DEBUG_DIAG
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define DIAG_BUFSIZE 32
+#else
+#define DIAG_BUFSIZE 2048
+#endif
+static char diag_buffer[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+
+void hal_diag_write_char(char c)
+{
+ uart_width lsr;
+
+ hal_diag_init();
+
+ cyg_hal_plf_duart_putc(&channel, c)
+
+#ifdef DEBUG_DIAG
+ diag_buffer[diag_bp++] = c;
+ if (diag_bp == DIAG_BUFSIZE) {
+ while (1) ;
+ diag_bp = 0;
+ }
+#endif
+}
+
+void hal_diag_read_char(char *c)
+{
+ *c = cyg_hal_plf_duart_getc(&channel);
+}
+
+#else // HAL_DIAG relies on GDB
+
+// Initialize diag port - assume GDB channel is already set up
+void hal_diag_init(void)
+{
+ if (0) init_duart_channel(&channel); // avoid warning
+}
+
+// Actually send character down the wire
+static void hal_diag_write_char_serial(char c)
+{
+ cyg_hal_plf_duart_putc(&channel, c);
+}
+
+static bool hal_diag_read_serial(char *c)
+{
+ long timeout = 1000000000; // A long time...
+
+ while (!cyg_hal_plf_duart_getc_nonblock(&channel, c))
+ if (0 == --timeout) return false;
+
+ return true;
+}
+
+void hal_diag_read_char(char *c)
+{
+ while (!hal_diag_read_serial(c)) ;
+}
+
+void hal_diag_write_char(char c)
+{
+ static char line[100];
+ static int pos = 0;
+
+ // No need to send CRs
+ if (c == '\r') return;
+
+ line[pos++] = c;
+
+ if (c == '\n' || pos == sizeof(line)) {
+ CYG_INTERRUPT_STATE old;
+
+ // Disable interrupts. This prevents GDB trying to interrupt us
+ // while we are in the middle of sending a packet. The serial
+ // receive interrupt will be seen when we re-enable interrupts
+ // later.
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+#else
+ HAL_DISABLE_INTERRUPTS(old);
+#endif
+
+ while (1) {
+ static char hex[] = "0123456789ABCDEF";
+ cyg_uint8 csum = 0;
+ int i;
+ char c1;
+
+ hal_diag_write_char_serial('$');
+ hal_diag_write_char_serial('O');
+ csum += 'O';
+ for (i = 0; i < pos; i++) {
+ char ch = line[i];
+ char h = hex[(ch>>4)&0xF];
+ char l = hex[ch&0xF];
+ hal_diag_write_char_serial(h);
+ hal_diag_write_char_serial(l);
+ csum += h;
+ csum += l;
+ }
+ hal_diag_write_char_serial('#');
+ hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
+ hal_diag_write_char_serial(hex[csum&0xF]);
+
+ // Wait for the ACK character '+' from GDB here and handle
+ // receiving a ^C instead. This is the reason for this clause
+ // being a loop.
+ if (!hal_diag_read_serial(&c1))
+ continue; // No response - try sending packet again
+
+ if ( c1 == '+' )
+ break; // a good acknowledge
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
+ if ( c1 == 3 ) {
+ // Ctrl-C: breakpoint.
+ cyg_hal_gdb_interrupt (__builtin_return_address(0));
+ break;
+ }
+#endif
+ // otherwise, loop round again
+ }
+
+ pos = 0;
+
+ // And re-enable interrupts
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+#else
+ HAL_RESTORE_INTERRUPTS(old);
+#endif
+
+ }
+}
+#endif
+
+#endif // __BASE
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
--- /dev/null
+//==========================================================================
+//
+// board_misc.c
+//
+// HAL misc board support code for the board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include <redboot.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h> // Interrupt names
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/fsl_board.h> // Platform specifics
+
+#include <cyg/infra/diag.h> // diag_printf
+
+// All the MM table layout is here:
+#include <cyg/hal/hal_mm.h>
+
+externC void* memset(void *, int, size_t);
+static void mxc_fec_setup(void);
+static void mxc_serial_setup(void);
+
+void hal_mmu_init(void)
+{
+ unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
+ unsigned long i;
+
+ /*
+ * Set the TTB register
+ */
+ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
+
+ /*
+ * Set the Domain Access Control Register
+ */
+ i = ARM_ACCESS_DACR_DEFAULT;
+ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+
+ /*
+ * First clear all TT entries - ie Set them to Faulting
+ */
+ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+
+ /* Actual Virtual Size Attributes Function */
+ /* Base Base MB cached? buffered? access permissions */
+ /* xxx00000 xxx00000 */
+ X_ARM_MMU_SECTION(0x000, 0xF00, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */
+ X_ARM_MMU_SECTION(0x300, 0x300, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* L2CC */
+ X_ARM_MMU_SECTION(0x400, 0x400, 0x400, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Internal Regsisters upto SDRAM*/
+ X_ARM_MMU_SECTION(0x800, 0x000, 0x80, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
+ X_ARM_MMU_SECTION(0x800, 0x800, 0x80, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
+ X_ARM_MMU_SECTION(0x800, 0x880, 0x80, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
+ X_ARM_MMU_SECTION(0xA00, 0xA00, 0x100, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Flash */
+ X_ARM_MMU_SECTION(0xB00, 0xB00, 0x20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PSRAM */
+ X_ARM_MMU_SECTION(0xB20, 0xB20, 0x1E0, ARM_UNCACHEABLE, ARM_UNBUFFERABLE,ARM_ACCESS_PERM_RW_RW); /* ESDCTL, WEIM, M3IF, EMI, NFC, External I/O */
+}
+
+//
+// Platform specific initialization
+//
+
+unsigned int g_clock_src;
+
+void plf_hardware_init(void)
+{
+ unsigned long val = readl(CCM_BASE_ADDR + CLKCTL_CCMR);
+
+ g_clock_src = FREQ_24MHZ;
+ /* PBC setup */
+ /* Reset interrupt status reg */
+ writew(0x1F, PBC_INT_REST);
+ writew(0x00, PBC_INT_REST);
+ writew(0xFFFF, PBC_INT_MASK);
+
+ mxc_serial_setup();
+ mxc_fec_setup();
+}
+
+static void mxc_serial_setup(void)
+{
+ // UART1
+ /*RXD1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x188);
+ writel(0x1E0, IOMUXC_BASE_ADDR + 0x55C);
+
+ /*TXD1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x18C);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x560);
+
+ /*RTS1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x190);
+ writel(0x1E0, IOMUXC_BASE_ADDR + 0x564);
+
+ /*CTS1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x194);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x568);
+
+ // UART2
+ //writel(0x13131300, IOMUXC_BASE_ADDR + 0x70);
+ //writel(0x00001313, IOMUXC_BASE_ADDR + 0x74);
+ //writel(0x00000040, IOMUXC_BASE_ADDR + 0x7C);
+ //writel(0x40400000, IOMUXC_BASE_ADDR + 0x78);
+}
+
+static void mxc_fec_setup(void)
+{
+ unsigned long val;
+
+ /*FEC_TX_CLK*/
+ writel(0, IOMUXC_BASE_ADDR + 0x02E0);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x0744);
+
+ /*FEC_RX_CLK*/
+ writel(0, IOMUXC_BASE_ADDR + 0x02E4);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x0748);
+
+ /*FEC_RX_DV*/
+ writel(0, IOMUXC_BASE_ADDR + 0x02E8);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x074C);
+
+ /*FEC_COL*/
+ writel(0, IOMUXC_BASE_ADDR + 0x02EC);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x0750);
+
+ /*FEC_RDATA0*/
+ writel(0, IOMUXC_BASE_ADDR + 0x02F0);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x0754);
+
+ /*FEC_TDATA0*/
+ writel(0, IOMUXC_BASE_ADDR + 0x02F4);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x0758);
+
+ /*FEC_TX_EN*/
+ writel(0, IOMUXC_BASE_ADDR + 0x02F8);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x075C);
+
+ /*FEC_MDC*/
+ writel(0, IOMUXC_BASE_ADDR + 0x02FC);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x0760);
+
+ /*FEC_MDIO*/
+ writel(0, IOMUXC_BASE_ADDR + 0x0300);
+ writel(0x1F0, IOMUXC_BASE_ADDR + 0x0764);
+
+ /*FEC_TX_ERR*/
+ writel(0, IOMUXC_BASE_ADDR + 0x0304);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x0768);
+
+ /*FEC_RX_ERR*/
+ writel(0, IOMUXC_BASE_ADDR + 0x0308);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x076C);
+
+ /*FEC_CRS*/
+ writel(0, IOMUXC_BASE_ADDR + 0x030C);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x0770);
+
+ /*FEC_RDATA1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x0310);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x0774);
+
+ /*FEC_TDATA1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x0314);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x0778);
+
+ /*FEC_RDATA2*/
+ writel(0, IOMUXC_BASE_ADDR + 0x0318);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x077C);
+
+ /*FEC_TDATA2*/
+ writel(0, IOMUXC_BASE_ADDR + 0x031C);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x0780);
+
+ /*FEC_RDATA3*/
+ writel(0, IOMUXC_BASE_ADDR + 0x0320);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x0784);
+
+ /*FEC_TDATA3*/
+ writel(0, IOMUXC_BASE_ADDR + 0x0324);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x0788);
+
+ /*FEC/UART3 MUX, enable GPIO1_5 output */
+ writel(0, IOMUXC_BASE_ADDR + 0x032C);
+ writel(0x5 , IOMUXC_BASE_ADDR + 0x08);
+ val = readl(GPIO1_BASE_ADDR + 0x04);
+ writel(val | (1 << 5), GPIO1_BASE_ADDR + 0x04);
+ val = readl(GPIO1_BASE_ADDR);
+ writel(val | (1 << 5), GPIO1_BASE_ADDR);
+}
+
+static void mxc_cspi_setup(void)
+{
+ /*CSPI1*/
+ /*SCLK*/
+ writel(0, IOMUXC_BASE_ADDR + 0x180);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x5c4);
+ /*SPI_RDY*/
+ writel(0, IOMUXC_BASE_ADDR + 0x184);
+ writel(0x1E0, IOMUXC_BASE_ADDR + 0x5c8);
+ /*MOSI*/
+ writel(0, IOMUXC_BASE_ADDR + 0x170);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x5b4);
+ /*MISO*/
+ writel(0, IOMUXC_BASE_ADDR + 0x174);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x5b8);
+ /*SS1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x17C);
+ writel(0x1E0, IOMUXC_BASE_ADDR + 0x5C0);
+}
+
+void mxc_i2c_init(unsigned int module_base)
+{
+ switch(module_base) {
+ case I2C_BASE_ADDR:
+ writel(0x10, IOMUXC_BASE_ADDR + 0x110);
+ writel(0x10, IOMUXC_BASE_ADDR + 0x114);
+ writel(0x1E4, IOMUXC_BASE_ADDR + 0x554);
+ writel(0x1E4, IOMUXC_BASE_ADDR + 0x558);
+ break;
+ case I2C2_BASE_ADDR:
+ case I2C3_BASE_ADDR:
+ default:
+ break;
+ }
+}
+
+void mxc_mmc_init(base_address)
+{
+ switch(base_address) {
+ case MMC_SDHC1_BASE_ADDR:
+ writel (0x1E3, IOMUXC_BASE_ADDR + 0x328 + 224 * 4);
+ break;
+ default:
+ break;
+ }
+}
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+typedef void code_fun(void);
+
+void board_program_new_stack(void *func)
+{
+ register CYG_ADDRESS stack_ptr asm("sp");
+ register CYG_ADDRESS old_stack asm("r4");
+ register code_fun *new_func asm("r0");
+ old_stack = stack_ptr;
+ stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
+ new_func = (code_fun*)func;
+ new_func();
+ stack_ptr = old_stack;
+}
+
+static void display_clock_src(void)
+{
+ diag_printf("\n");
+ diag_printf("Clock input is 24 MHz");
+}
+RedBoot_init(display_clock_src, RedBoot_INIT_LAST);
+
+extern unsigned int pmic_reg(unsigned int reg, unsigned int val, unsigned int write);
+static void fec_power_init(void)
+{
+ unsigned int val;
+ val = pmic_reg(0x20, 0, 0);
+ hal_delay_us(25);
+ pmic_reg(0x20, val | 0x4, 1);
+}
+
+RedBoot_init(fec_power_init, RedBoot_INIT_PRIO(900));
+// ------------------------------------------------------------------------
--- /dev/null
+//==========================================================================
+//
+// redboot_cmds.c
+//
+// Board [platform] specific RedBoot commands
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+#include <redboot.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/plf_mmap.h>
+#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <flash_config.h>
+
+#if (REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE)
+#error REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE
+#endif
+
+RedBoot_config_option("Board specifics",
+ brd_specs,
+ ALWAYS_ENABLED,
+ true,
+ CONFIG_INT,
+ 0
+ );
+#endif //CYGSEM_REDBOOT_FLASH_CONFIG
+
+char HAL_PLATFORM_EXTRA[55] = "PASS x.x [x32 DDR]";
+
+static void runImg(int argc, char *argv[]);
+
+RedBoot_cmd("run",
+ "Run an image at a location with MMU off",
+ "[<virtual addr>]",
+ runImg
+ );
+
+void launchRunImg(unsigned long addr)
+{
+ asm volatile ("mov r12, r0;");
+ HAL_CLEAN_INVALIDATE_L2();
+ HAL_DISABLE_L2();
+ HAL_MMU_OFF();
+ asm volatile (
+ "mov r0, #0;"
+ "mov r1, r12;"
+ "mov r11, #0;"
+ "mov r12, #0;"
+ "mrs r10, cpsr;"
+ "bic r10, r10, #0xF0000000;"
+ "msr cpsr_f, r10;"
+ "mov pc, r1"
+ );
+}
+
+extern unsigned long entry_address;
+
+static void runImg(int argc,char *argv[])
+{
+ unsigned int virt_addr, phys_addr;
+
+ // Default physical entry point for Symbian
+ if (entry_address == 0xFFFFFFFF)
+ virt_addr = 0x800000;
+ else
+ virt_addr = entry_address;
+
+ if (!scan_opts(argc,argv,1,0,0,(void*)&virt_addr,
+ OPTION_ARG_TYPE_NUM, "virtual address"))
+ return;
+
+ if (entry_address != 0xFFFFFFFF)
+ diag_printf("load entry_address=0x%lx\n", entry_address);
+ HAL_VIRT_TO_PHYS_ADDRESS(virt_addr, phys_addr);
+
+ diag_printf("virt_addr=0x%x\n",virt_addr);
+ diag_printf("phys_addr=0x%x\n",phys_addr);
+
+ launchRunImg(phys_addr);
+}
+
+#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYG_HAL_STARTUP_ROMRAM)
+
+RedBoot_cmd("romupdate",
+ "Update Redboot with currently running image",
+ "",
+ romupdate
+ );
+
+extern int flash_program(void *_addr, void *_data, int len, void **err_addr);
+extern int flash_erase(void *addr, int len, void **err_addr);
+extern char *flash_errmsg(int err);
+extern unsigned char *ram_end; //ram end is where the redboot starts FIXME: use PC value
+
+#ifdef CYGPKG_IO_FLASH
+void romupdate(int argc, char *argv[])
+{
+ void *err_addr, *base_addr;
+ int stat;
+
+ if (IS_FIS_FROM_MMC()) {
+ diag_printf("Updating ROM in MMC/SD flash\n");
+ base_addr = (void*)0;
+ /* Read the first 1K from the card */
+ mmc_data_read((cyg_uint32*)ram_end, 0x400, base_addr);
+ diag_printf("Programming Redboot to MMC/SD flash\n");
+ mmc_data_write((cyg_uint32*)ram_end, CYGBLD_REDBOOT_MIN_IMAGE_SIZE, (cyg_uint32)base_addr);
+ return;
+ } else if (IS_FIS_FROM_NAND()) {
+ base_addr = (void*)MXC_NAND_BASE_DUMMY;
+ diag_printf("Updating ROM in NAND flash\n");
+ } else if (IS_FIS_FROM_NOR()) {
+ base_addr = (void*)BOARD_FLASH_START;
+ diag_printf("Updating ROM in NOR flash\n");
+ } else {
+ diag_printf("romupdate not supported\n");
+ diag_printf("Use \"factive [NOR|NAND|MMC]\" to select either NOR, NAND or MMC flash\n");
+ }
+
+ // Erase area to be programmed
+ if ((stat = flash_erase((void *)base_addr,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ (void **)&err_addr)) != 0) {
+ diag_printf("Can't erase region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ return;
+ }
+ // Now program it
+ if ((stat = flash_program((void *)base_addr, (void *)ram_end,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ (void **)&err_addr)) != 0) {
+ diag_printf("Can't program region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ }
+}
+
+RedBoot_cmd("factive",
+ "Enable one flash media for Redboot",
+ "[NOR | NAND | MMC]",
+ factive
+ );
+
+void factive(int argc, char *argv[])
+{
+ unsigned long phys_addr;
+
+ if (argc != 2) {
+ diag_printf("Invalid factive cmd\n");
+ return;
+ }
+
+ if (strcasecmp(argv[1], "NOR") == 0) {
+#ifndef MXCFLASH_SELECT_NOR
+ diag_printf("Not supported\n");
+ return;
+#else
+ MXC_ASSERT_NOR_BOOT();
+#endif
+ } else if (strcasecmp(argv[1], "NAND") == 0) {
+#ifndef MXCFLASH_SELECT_NAND
+ diag_printf("Not supported\n");
+ return;
+#else
+ MXC_ASSERT_NAND_BOOT();
+#endif
+ } else if (strcasecmp(argv[1], "MMC") == 0) {
+#ifndef MXCFLASH_SELECT_MMC
+ diag_printf("Not supported\n");
+ return;
+#else
+ MXC_ASSERT_MMC_BOOT();
+#endif
+ } else {
+ diag_printf("Invalid command: %s\n", argv[1]);
+ return;
+ }
+ HAL_VIRT_TO_PHYS_ADDRESS(ram_end, phys_addr);
+
+ launchRunImg(phys_addr);
+}
+#endif //CYGPKG_IO_FLASH
+#endif /* CYG_HAL_STARTUP_ROMRAM */
--- /dev/null
+# ====================================================================
+#
+# hal_arm_board.cdl
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+
+cdl_package CYGPKG_HAL_ARM_MX35EVB {
+ display "Freescale board"
+ parent CYGPKG_HAL_ARM_MX35
+ hardware
+ include_dir cyg/hal
+ define_header hal_arm_board.h
+ description "
+ This HAL platform package provides generic
+ support for the Freescale MX35 EVB Board."
+
+ compile board_misc.c board_diag.c
+ implements CYGINT_HAL_DEBUG_GDB_STUBS
+ implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+ implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+
+ #implements CYGHWR_HAL_ARM_DUART_UARTB
+ implements CYGHWR_HAL_ARM_SOC_UART1
+
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_soc.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_board.h>"
+ puts $::cdl_header "#define HAL_PLATFORM_CPU \"Freescale i.MX35 based\""
+ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"MX35 EVB\""
+ puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 1643"
+ puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK board_program_new_stack"
+ }
+
+ cdl_component CYG_HAL_STARTUP {
+ display "Startup type"
+ flavor data
+ default_value {"ROM"}
+ legal_values {"RAM" "ROM" "ROMRAM"}
+ no_define
+ define -file system.h CYG_HAL_STARTUP
+ description "
+ When targetting the eval board it is possible to build
+ the system for either RAM bootstrap or ROM bootstrap(s). Select
+ 'ram' when building programs to load into RAM using eCos GDB
+ stubs. Select 'rom' when building a stand-alone application
+ which will be put into ROM, or for the special case of
+ building the eCos GDB stubs themselves. Using ROMRAM will allow
+ the program to exist in ROM, but be copied to RAM during startup."
+ }
+
+ cdl_interface CYGINT_DEVS_ETH_FEC_REQUIRED {
+ display "FEC ethernet driver required"
+ }
+
+ implements CYGINT_DEVS_ETH_FEC_REQUIRED
+
+ cdl_interface CYGHWR_HAL_ARM_DUART_UARTA {
+ display "ST16552 UARTA available as diagnostic/debug channel"
+ description "
+ The board has a ST16552 DUART chip. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_DUART_UARTB {
+ display "ST16552 UARTB available as diagnostic/debug channel"
+ description "
+ The board has a ST16552 DUART chip. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ display "Diagnostic serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the console port.
+ Note: this should match the value chosen for the GDB port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ display "GDB serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the GDB port.
+ Note: this should match the value chosen for the console port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the board"
+ flavor data
+ calculated 3
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ The board has three serial ports. This option
+ chooses which port will be used to connect to a host
+ running GDB."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+ display "Default console channel."
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ calculated 0
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Console serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ description "
+ The board has only three serial ports. This option
+ chooses which port will be used for console output."
+ }
+
+ cdl_component CYGBLD_GLOBAL_OPTIONS {
+ display "Global build options"
+ flavor none
+ no_define
+ description "
+ Global build options including control over
+ compiler flags, linker flags and choice of toolchain."
+
+
+ parent CYGPKG_NONE
+
+ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ display "Global command prefix"
+ flavor data
+ no_define
+ default_value { "arm-none-eabi" }
+ description "
+ This option specifies the command prefix used when
+ invoking the build tools."
+ }
+
+ cdl_option CYGBLD_GLOBAL_CFLAGS {
+ display "Global compiler flags"
+ flavor data
+ no_define
+ default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ description "
+ This option controls the global compiler flags which are used to
+ compile all packages by default. Individual packages may define
+ options which override these global flags."
+ }
+
+ cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ display "Global linker flags"
+ flavor data
+ no_define
+ default_value { "-Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" }
+ description "
+ This option controls the global linker flags. Individual
+ packages may define options which override these global flags."
+ }
+
+ cdl_option CYGBLD_BUILD_GDB_STUBS {
+ display "Build GDB stub ROM image"
+ default_value 0
+ requires { CYG_HAL_STARTUP == "ROM" }
+ requires CYGSEM_HAL_ROM_MONITOR
+ requires CYGBLD_BUILD_COMMON_GDB_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ no_define
+ description "
+ This option enables the building of the GDB stubs for the
+ board. The common HAL controls takes care of most of the
+ build process, but the final conversion from ELF image to
+ binary data is handled by the platform CDL, allowing
+ relocation of the data if necessary."
+
+ make -priority 320 {
+ <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
+ $(OBJCOPY) --remove-section=.fixed_vectors -O binary $< $@
+ }
+ }
+ }
+
+ cdl_component CYGPKG_HAL_ARM_BOARD_OPTIONS {
+ display "Freescale MXC Board build options"
+ flavor none
+ no_define
+ description "
+ Package specific build options including control over
+ compiler flags used only in building this package,
+ and details of which tests are built."
+
+ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the board HAL. These flags are used in addition
+ to the set of global flags."
+ }
+
+ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_REMOVE {
+ display "Suppressed compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the board HAL. These flags are removed from
+ the set of global flags if present."
+ }
+
+ }
+
+ cdl_component CYGHWR_MEMORY_LAYOUT {
+ display "Memory layout"
+ flavor data
+ no_define
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_board_ram" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" :
+ "arm_board_rom" }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ display "Memory layout linker script fragment"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.ldi>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.ldi>" :
+ "<pkgconf/mlt_arm_board_rom.ldi>" }
+ }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ display "Memory layout header file"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_H
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.h>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.h>" :
+ "<pkgconf/mlt_arm_board_rom.h>" }
+ }
+ }
+
+ cdl_option CYGSEM_HAL_ROM_MONITOR {
+ display "Behave as a ROM monitor"
+ flavor bool
+ default_value 0
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+ description "
+ Enable this option if this program is to be used as a ROM monitor,
+ i.e. applications will be loaded into RAM on the board, and this
+ ROM monitor may process exceptions or interrupts generated from the
+ application. This enables features such as utilizing a separate
+ interrupt stack when exceptions are generated."
+ }
+
+ cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ display "Work with a ROM monitor"
+ flavor booldata
+ legal_values { "Generic" "GDB_stubs" }
+ default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "RAM" }
+ description "
+ Support can be enabled for different varieties of ROM monitor.
+ This support changes various eCos semantics such as the encoding
+ of diagnostic output, or the overriding of hardware interrupt
+ vectors.
+ Firstly there is \"Generic\" support which prevents the HAL
+ from overriding the hardware vectors that it does not use, to
+ instead allow an installed ROM monitor to handle them. This is
+ the most basic support which is likely to be common to most
+ implementations of ROM monitor.
+ \"GDB_stubs\" provides support when GDB stubs are included in
+ the ROM monitor or boot ROM."
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ display "Redboot HAL options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+ description "
+ This option lists the target's requirements for a valid Redboot
+ configuration."
+
+ compile -library=libextras.a redboot_cmds.c
+
+ cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ display "Build Redboot ROM binary image"
+ active_if CYGBLD_BUILD_REDBOOT
+ default_value 1
+ no_define
+ description "This option enables the conversion of the Redboot ELF
+ image to a binary image suitable for ROM programming."
+
+ make -priority 325 {
+ <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+ $(OBJCOPY) -O binary $< $@
+ }
+ }
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_BOARD_OPTIONS {
+ display "Redboot HAL variant options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+
+ # RedBoot details
+ requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x90008000 }
+ define_proc {
+ puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00"
+ }
+ }
+}
--- /dev/null
+#ifndef CYGONCE_FSL_BOARD_H
+#define CYGONCE_FSL_BOARD_H
+
+//=============================================================================
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+
+#define PMIC_SPI_BASE CSPI2_BASE_ADDR
+#define PMIC_SPI_CHIP_SELECT_NO SPI_CTRL_CS2
+
+#define PBC_BASE CS4_BASE_ADDR /* Peripheral Bus Controller */
+#define PBC_VERSION (PBC_BASE + 0x00000)
+#define PBC_CTRL1_SET (PBC_BASE + 0x00008)
+#define PBC_CTRL1_CLR (PBC_BASE + 0x0000C)
+#define PBC_CTRL2_SET (PBC_BASE + 0x00010)
+#define PBC_CTRL2_CLR (PBC_BASE + 0x00014)
+#define PBC_IMASK1_SET (PBC_BASE + 0x00018)
+#define PBC_IMASK1_CLR (PBC_BASE + 0x0001C)
+#define PBC_IMASK2_SET (PBC_BASE + 0x00020)
+#define PBC_IMASK2_CLR (PBC_BASE + 0x00024)
+#define PBC_STAT (PBC_BASE + 0x00028)
+#define PBC_INT_STAT (PBC_BASE + 0x0002C)
+
+#define BOARD_CS_UART_BASE (PBC_BASE + 0x20000)
+#define BOARD_CS_LAN_BASE (PBC_BASE + 0x40000)
+
+#define LAN92XX_REG_BASE BOARD_CS_LAN_BASE
+
+#define REDBOOT_IMAGE_SIZE 0x40000
+
+#define EXT_UART_x16
+/* MX31 ADS SDRAM is from 0x80000000, 128M */
+#define BOARD_FLASH_START CS0_BASE_ADDR
+#define SDRAM_BASE_ADDR CSD1_BASE_ADDR
+#define SDRAM_SIZE 0x08000000
+#define RAM_BANK0_BASE CSD0_BASE_ADDR
+#define RAM_BANK1_BASE CSD1_BASE_ADDR
+
+#define FEC_PHY_ADDR 0
+
+#define LED_MAX_NUM 8
+//#define LED_IS_ON(n) ((readw(PBC_LED_CTRL) & (1<<(n))) != 0)
+//#define TURN_LED_ON(n) writew((readw(PBC_LED_CTRL)|(1<<(n))), PBC_LED_CTRL)
+//#define TURN_LED_OFF(n) writew((readw(PBC_LED_CTRL)&(~(1<<(n)))), PBC_LED_CTRL)
+
+#define BOARD_DEBUG_LED(n)
+#if 0
+#define BOARD_DEBUG_LED(n) \
+ CYG_MACRO_START \
+ if (n >= 0 && n < LED_MAX_NUM) { \
+ if (LED_IS_ON(n)) \
+ TURN_LED_OFF(n); \
+ else \
+ TURN_LED_ON(n); \
+ } \
+ CYG_MACRO_END
+#endif
+#endif /* CYGONCE_FSL_BOARD_H */
--- /dev/null
+#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
+#define CYGONCE_HAL_PLATFORM_SETUP_H
+
+//=============================================================================
+//
+// hal_platform_setup.h
+//
+// Platform specific support for HAL (assembly code)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <pkgconf/system.h> // System-wide configuration info
+#include CYGBLD_HAL_VARIANT_H // Variant specific configuration
+#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
+#include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
+#include <cyg/hal/hal_mmu.h> // MMU definitions
+#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1 _platform_setup1
+#define CYGHWR_HAL_ARM_HAS_MMU
+
+#ifdef CYG_HAL_STARTUP_ROMRAM
+#define CYGSEM_HAL_ROM_RESET_USES_JUMP
+#endif
+
+//#define NFC_2K_BI_SWAP
+
+//#define SDRAM_FULL_PAGE_BIT 0x100
+//#define SDRAM_FULL_PAGE_MODE 0x37
+//#define SDRAM_BURST_MODE 0x33
+
+#define CYGHWR_HAL_ROM_VADDR 0x0
+
+#if 0
+#define UNALIGNED_ACCESS_ENABLE
+#define SET_T_BIT_DISABLE
+#define LOW_INT_LATENCY_ENABLE
+#define BRANCH_PREDICTION_ENABLE
+#endif
+
+#define UNALIGNED_ACCESS_ENABLE
+#define LOW_INT_LATENCY_ENABLE
+#define BRANCH_PREDICTION_ENABLE
+
+//#define TURN_OFF_IMPRECISE_ABORT
+
+// This macro represents the initial startup code for the platform
+// r11 is reserved to contain chip rev info in this file
+ .macro _platform_setup1
+FSL_BOARD_SETUP_START:
+/*
+ * ARM1136 init
+ * - invalidate I/D cache/TLB and drain write buffer;
+ * - invalidate L2 cache
+ * - unaligned access
+ * - branch predictions
+ */
+#ifdef TURN_OFF_IMPRECISE_ABORT
+ mrs r0, cpsr
+ bic r0, r0, #0x100
+ msr cpsr, r0
+#endif
+
+ mrc 15, 0, r1, c1, c0, 0
+ bic r1, r1, #(0x3<<21)
+ bic r1, r1, #(0x3<<11)
+ bic r1, r1, #0x5
+
+#ifndef BRANCH_PREDICTION_ENABLE
+ mrc 15, 0, r0, c1, c0, 1
+ bic r0, r0, #7
+ mcr 15, 0, r0, c1, c0, 1
+#else
+ mrc 15, 0, r0, c1, c0, 1
+ orr r0, r0, #7
+ mcr 15, 0, r0, c1, c0, 1
+ orr r1, r1, #(1<<11)
+#endif
+
+#ifdef UNALIGNED_ACCESS_ENABLE
+ orr r1, r1, #(1<<22)
+#endif
+
+#ifdef LOW_INT_LATENCY_ENABLE
+ orr r1, r1, #(1<<21)
+#endif
+ mcr 15, 0, r1, c1, c0, 0
+
+#ifdef BRANCH_PREDICTION_ENABLE
+ mov r0, #0
+ mcr 15, 0, r0, c15, c2, 4
+#endif
+
+ mov r0, #0
+ mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
+ mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+ mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
+
+ /* Also setup the Peripheral Port Remap register inside the core */
+ ldr r0, ARM_PPMRR /* start from AIPS 2GB region */
+ mcr p15, 0, r0, c15, c2, 4
+
+ /* Reload data from spare area to 0x1000 of main area if booting from NAND */
+ mov r0, #NFC_BASE
+ add r1, r0, #0x1000
+ cmp pc, r0
+ blo 1f
+ cmp pc, r1
+ bhi 1f
+
+#define MXC_NAND_BOOT_LOAD_AT_0x404
+#ifdef MXC_NAND_BOOT_LOAD_AT_0x404
+ // Recover the word at 0x404 offset using the one stored in the spare area
+ ldr r2, [r0, #0x820]
+ str r2, [r1]
+#endif
+
+#ifdef NFC_2K_BI_SWAP
+ ldr r3, [r0, #0x7D0] // load word at addr 464 of last 512 RAM buffer
+ and r3, r3, #0xFFFFFF00 // mask off the LSB
+ ldr r4, [r0, #0x834] // load word at addr 4 of the 3rd spare area buffer
+ mov r4, r4, lsr #8 // shift it to get the byte at addr 5
+ and r4, r4, #0xFF // throw away upper 3 bytes
+ add r3, r4, r3 // construct the word
+ str r3, [r0, #0x7D0] // write back
+#endif
+
+1:
+ /*** L2 Cache setup/invalidation/disable ***/
+ /* Disable L2 cache first */
+ mov r0, #L2CC_BASE_ADDR
+ ldr r2, [r0, #L2_CACHE_CTL_REG]
+ bic r2, r2, #0x1
+ str r2, [r0, #L2_CACHE_CTL_REG]
+ /*
+ * Configure L2 Cache:
+ * - 128k size(16k way)
+ * - 8-way associativity
+ * - 0 ws TAG/VALID/DIRTY
+ * - 4 ws DATA R/W
+ */
+ ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
+ and r1, r1, #0xFE000000
+ ldr r2, L2CACHE_PARAM
+ orr r1, r1, r2
+ str r1, [r0, #L2_CACHE_AUX_CTL_REG]
+/* Workaournd for DDR issue:WT*/
+ ldr r1, [r0, #L2_CACHE_DBG_CTL_REG]
+ orr r1, r1, #2
+ str r1, [r0, #L2_CACHE_DBG_CTL_REG]
+
+ /* Invalidate L2 */
+ mov r1, #0x000000FF
+ str r1, [r0, #L2_CACHE_INV_WAY_REG]
+L2_loop:
+ /* Poll Invalidate By Way register */
+ ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
+ cmp r2, #0
+ bne L2_loop
+ /*** End of L2 operations ***/
+
+ mov r0, #SDRAM_NON_FLASH_BOOT
+ ldr r1, AVIC_VECTOR0_ADDR_W
+ str r0, [r1] // for checking boot source from nand or sdram
+/*
+ * End of ARM1136 init
+ */
+init_spba_start:
+ init_spba
+init_aips_start:
+ init_aips
+init_max_start:
+ init_max
+init_m3if_start:
+ init_m3if
+
+ init_iomuxc
+
+ /* If SDRAM has been setup, bypass clock/WEIM setup */
+ cmp pc, #SDRAM_BASE_ADDR
+ blo init_clock_start
+ cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
+ blo HWInitialise_skip_SDRAM_setup
+
+ mov r0, #NOR_FLASH_BOOT
+ ldr r1, AVIC_VECTOR0_ADDR_W
+ str r0, [r1]
+
+init_clock_start:
+ init_clock
+
+init_cs4_start:
+ init_cs4
+ init_cs5
+
+ /* Based on chip rev, setup params for SDRAM controller */
+init_sdram_start:
+
+ /* Assuming DDR memory first */
+ setup_sdram
+
+HWInitialise_skip_SDRAM_setup:
+
+ mov r0, #NFC_BASE
+ add r2, r0, #0x1000 // 4K window
+ cmp pc, r0
+ blo Normal_Boot_Continue
+ cmp pc, r2
+ bhi Normal_Boot_Continue
+NAND_Boot_Start:
+ /* Copy image from flash to SDRAM first */
+ ldr r1, MXC_REDBOOT_ROM_START
+
+1: ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ blo 1b
+ /* Jump to SDRAM */
+ ldr r1, CONST_0x0FFF
+ and r0, pc, r1 /* offset of pc */
+ ldr r1, MXC_REDBOOT_ROM_START
+ add r1, r1, #0x10
+ add pc, r0, r1
+ nop
+ nop
+ nop
+ nop
+NAND_Copy_Main:
+ /* Setting NFC */
+ ldr r7, CCM_BASE_ADDR_W
+ ldr r7, [r7, #CLKCTL_RCSR]
+ /*BUS WIDTH*/
+ tst r7, #0x20000000
+ orrne r7, r7, #0x4000
+ biceq r7, r7, #0x4000
+ /*4K PAGE*/
+ tst r7, #0x10000000
+ orrne r7, r7, #0x200
+ bne 1f
+ /*2K PAGE*/
+ bic r7, r7, #0x200
+ tst r7, #0x08000000
+ orrne r7, r7, #0x100
+ biceq r7, r7, #0x100
+1:
+ mov r0, #NAND_FLASH_BOOT
+ ldr r1, AVIC_VECTOR0_ADDR_W
+ str r0, [r1]
+ mov r0, #MXCFIS_NAND
+ ldr r1, AVIC_VECTOR1_ADDR_W
+ str r0, [r1]
+
+ mov r0, #NFC_BASE; //r0: nfc base. Reloaded after each page copying
+ mov r1, #0x1000 //r1: starting flash addr to be copied. Updated constantly
+ add r2, r0, #0x1000 //r2: end of 3rd RAM buf. Doesn't change
+ ldr r7, CCM_BASE_ADDR_W
+ ldr r7, [r7, #CLKCTL_RCSR]
+ tst r7, #0x200
+ bne 1f
+ tst r7, #0x100
+ addne r2, r0, #0x800
+ addeq r2, r0, #0x200
+1:
+ ldr r11, MXC_REDBOOT_ROM_START
+ add r12, r0, #0x1E00 //r12: NFC register base. Doesn't change
+ add r13, r11, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
+ add r11, r11, r1 //r11: starting SDRAM address for copying. Updated constantly
+
+ //unlock internal buffer
+ mov r3, #0x2
+ strh r3, [r12, #NFC_CONFIGURATION_REG_OFF]
+
+Nfc_Read_Page:
+ mov r3, #0x0
+ nfc_cmd_input
+
+ // Check if x16/2kb page
+ ldr r7, CCM_BASE_ADDR_W
+ ldr r7, [r7, #CLKCTL_RCSR]
+ tst r7, #0x200
+ bne nfc_addr_ops_4kb
+ tst r7, #0x100
+
+ bne nfc_addr_ops_2kb
+ mov r3, r1
+ do_addr_input //1st addr cycle
+ mov r3, r1, lsr #9
+ do_addr_input //2nd addr cycle
+ mov r3, r1, lsr #17
+ do_addr_input //3rd addr cycle
+ mov r3, r1, lsr #25
+ do_addr_input //4th addr cycle
+ b end_of_nfc_addr_ops
+
+nfc_addr_ops_2kb:
+ mov r3, #0
+ do_addr_input //1st addr cycle
+ mov r3, #0
+ do_addr_input //2nd addr cycle
+ mov r3, r1, lsr #11
+ do_addr_input //3rd addr cycle
+ mov r3, r1, lsr #19
+ do_addr_input //4th addr cycle
+ mov r3, r1, lsr #27
+ do_addr_input //5th addr cycle
+
+ mov r3, #0x30
+ nfc_cmd_input
+ b end_of_nfc_addr_ops
+
+nfc_addr_ops_4kb:
+ mov r3, #0
+ do_addr_input //1st addr cycle
+ mov r3, #0
+ do_addr_input //2nd addr cycle
+ mov r3, r1, lsr #12
+ do_addr_input //3rd addr cycle
+ mov r3, r1, lsr #19
+ do_addr_input //4th addr cycle
+ mov r3, r1, lsr #27
+ do_addr_input //5th addr cycle
+
+ mov r3, #0x30
+ nfc_cmd_input
+
+end_of_nfc_addr_ops:
+ mov r8, #0
+ bl nfc_data_output
+ bl do_wait_op_done
+ // Check if x16/2kb page
+ ldr r7, CCM_BASE_ADDR_W
+ ldr r7, [r7, #CLKCTL_RCSR]
+ tst r7, #0x300
+ beq nfc_addr_data_output_done_512
+// For 4K page - 2nd 512
+ mov r8, #1
+ bl nfc_data_output
+ bl do_wait_op_done
+
+// 3rd 512
+ mov r8, #2
+ bl nfc_data_output
+ bl do_wait_op_done
+
+// 4th 512
+ mov r8, #3
+ bl nfc_data_output
+ bl do_wait_op_done
+
+ tst r7, #0x200
+ beq nfc_addr_data_output_done_2k
+
+ mov r8, #4
+ bl nfc_data_output
+ bl do_wait_op_done
+
+ mov r8, #5
+ bl nfc_data_output
+ bl do_wait_op_done
+
+ mov r8, #6
+ bl nfc_data_output
+ bl do_wait_op_done
+#ifdef NFC_4K_BI_SWAP
+ ldr r3, [r0, #0x7D0] // load word at addr 464 of last 512 RAM buffer
+ and r3, r3, #0xFFFFFF00 // mask off the LSB
+ ldr r4, [r0, #0x834] // load word at addr 4 of the 3rd spare area buffer
+ mov r4, r4, lsr #8 // shift it to get the byte at addr 5
+ and r4, r4, #0xFF // throw away upper 3 bytes
+ add r3, r4, r3 // construct the word
+ str r3, [r0, #0x7D0] // write back
+#endif
+ // check for bad block
+ mov r3, r1, lsl #(32-17) // get rid of block number
+ cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
+ b nfc_addr_data_output_done
+
+nfc_addr_data_output_done_2k:
+// end of 4th
+#ifdef NFC_2K_BI_SWAP
+ ldr r3, [r0, #0x7D0] // load word at addr 464 of last 512 RAM buffer
+ and r3, r3, #0xFFFFFF00 // mask off the LSB
+ ldr r4, [r0, #0x834] // load word at addr 4 of the 3rd spare area buffer
+ mov r4, r4, lsr #8 // shift it to get the byte at addr 5
+ and r4, r4, #0xFF // throw away upper 3 bytes
+ add r3, r4, r3 // construct the word
+ str r3, [r0, #0x7D0] // write back
+#endif
+ // check for bad block
+ mov r3, r1, lsl #(32-17) // get rid of block number
+ cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
+ b nfc_addr_data_output_done
+
+nfc_addr_data_output_done_512:
+ // check for bad block
+ mov r3, r1, lsl #(32-5-9) // get rid of block number
+ cmp r3, #(512 << (32-5-9)) // check if not page 0 or 1
+
+nfc_addr_data_output_done:
+ bhi Copy_Good_Blk
+ add r4, r0, #0x1000 //r3 -> spare area buf 0
+ ldrh r4, [r4, #0x4]
+ and r4, r4, #0xFF00
+ cmp r4, #0xFF00
+ beq Copy_Good_Blk
+ // really sucks. Bad block!!!!
+ cmp r3, #0x0
+ beq Skip_bad_block
+ // even suckier since we already read the first page!
+ // Check if x16/2kb page
+ ldr r7, CCM_BASE_ADDR_W
+ ldr r7, [r7, #CLKCTL_RCSR]
+ tst r7, #0x200
+ // for 4k page
+ subne r11, r11, #0x1000 //rewind 1 page for the sdram pointer
+ subne r1, r1, #0x1000 //rewind 1 page for the flash pointer
+ bne Skip_bad_block
+ tst r7, #0x100
+ subeq r11, r11, #512 //rewind 1 page for the sdram pointer
+ subeq r1, r1, #512 //rewind 1 page for the flash pointer
+
+ // for 2k page
+ subne r11, r11, #0x800 //rewind 1 page for the sdram pointer
+ subne r1, r1, #0x800 //rewind 1 page for the flash pointer
+
+Skip_bad_block:
+ // Check if x16/2kb page
+ ldr r7, CCM_BASE_ADDR_W
+ ldr r7, [r7, #CLKCTL_RCSR]
+ tst r7, #0x200
+ addne r1, r1, #(128*4096)
+ bne Skip_bad_block_done
+ tst r7, #0x100
+ addeq r1, r1, #(32*512)
+ addne r1, r1, #(64*2048)
+Skip_bad_block_done:
+ b Nfc_Read_Page
+Copy_Good_Blk:
+ //copying page
+1: ldmia r0!, {r3-r10}
+ stmia r11!, {r3-r10}
+ cmp r0, r2
+ blo 1b
+ cmp r11, r13
+ bge NAND_Copy_Main_done
+ // Check if x16/2kb page
+ ldr r7, CCM_BASE_ADDR_W
+ ldr r7, [r7, #CLKCTL_RCSR]
+ tst r7, #0x200
+ addne r1, r1, #0x1000
+ bne 1f
+ tst r7, #0x100
+ addne r1, r1, #0x800
+ addeq r1, r1, #0x200
+1:
+ mov r0, #NFC_BASE
+ b Nfc_Read_Page
+
+NAND_Copy_Main_done:
+
+Normal_Boot_Continue:
+
+#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
+ /* Copy image from flash to SDRAM first */
+ ldr r0, =0xFFFFF000
+ and r0, r0, pc
+ ldr r1, MXC_REDBOOT_ROM_START
+ cmp r0, r1
+ beq HWInitialise_skip_SDRAM_copy
+
+ add r2, r0, #REDBOOT_IMAGE_SIZE
+
+1: ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ ble 1b
+ /* Jump to SDRAM */
+ ldr r1, =0xFFFF
+ and r0, pc, r1 /* offset of pc */
+ ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
+ add pc, r0, r1
+ nop
+ nop
+ nop
+ nop
+#endif /* CYG_HAL_STARTUP_ROMRAM */
+
+HWInitialise_skip_SDRAM_copy:
+ init_cs0
+
+/*
+ * Note:
+ * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
+ */
+
+STACK_Setup:
+ // Set up a stack [for calling C code]
+ ldr r1, =__startup_stack
+ ldr r2, =SDRAM_BASE_ADDR
+ orr sp, r1, r2
+
+ // Create MMU tables
+ bl hal_mmu_init
+
+ // Enable MMU
+ ldr r2, =10f
+ mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
+ orr r1, r1, #7 // enable MMU bit
+ orr r1, r1, #0x800 // enable z bit
+ mcr MMU_CP, 0, r1, MMU_Control, c0
+ mov pc,r2 /* Change address spaces */
+ nop
+ nop
+ nop
+10:
+
+ // Save shadow copy of BCR, also hardware configuration
+ ldr r1, =_board_BCR
+ str r2, [r1]
+ ldr r1, =_board_CFG
+ str r9, [r1] // Saved far above...
+
+ .endm // _platform_setup1
+
+do_wait_op_done:
+ 1:
+ ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
+ beq 1b
+ bx lr // do_wait_op_done
+
+nfc_data_output:
+ mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
+ strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+
+ // writew(buf_no, RAM_BUFFER_ADDRESS_REG);
+ strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
+ // writew(FDO_PAGE_SPARE_VAL & 0xFF, NAND_FLASH_CONFIG2_REG);
+ mov r3, #FDO_PAGE_SPARE_VAL
+ strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ bx lr
+
+#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1
+#endif
+
+ /* Do nothing */
+ .macro init_spba
+ .endm /* init_spba */
+
+ /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
+ .macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, AIPS1_CTRL_BASE_ADDR_W
+ ldr r1, AIPS1_PARAM_W
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ ldr r0, AIPS2_CTRL_BASE_ADDR_W
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+
+ /*
+ * Clear the on and off peripheral modules Supervisor Protect bit
+ * for SDMA to access them. Did not change the AIPS control registers
+ * (offset 0x20) access type
+ */
+ ldr r0, AIPS1_CTRL_BASE_ADDR_W
+ ldr r1, =0x0
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ ldr r1, [r0, #0x50]
+ and r1, r1, #0x00FFFFFF
+ str r1, [r0, #0x50]
+
+ ldr r0, AIPS2_CTRL_BASE_ADDR_W
+ ldr r1, =0x0
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ ldr r1, [r0, #0x50]
+ and r1, r1, #0x00FFFFFF
+ str r1, [r0, #0x50]
+ .endm /* init_aips */
+
+ /* MAX (Multi-Layer AHB Crossbar Switch) setup */
+ .macro init_max
+ ldr r0, MAX_BASE_ADDR_W
+ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+ ldr r1, MAX_PARAM1
+ str r1, [r0, #0x000] /* for S0 */
+ str r1, [r0, #0x100] /* for S1 */
+ str r1, [r0, #0x200] /* for S2 */
+ str r1, [r0, #0x300] /* for S3 */
+ str r1, [r0, #0x400] /* for S4 */
+ /* SGPCR - always park on last master */
+ ldr r1, =0x10
+ str r1, [r0, #0x010] /* for S0 */
+ str r1, [r0, #0x110] /* for S1 */
+ str r1, [r0, #0x210] /* for S2 */
+ str r1, [r0, #0x310] /* for S3 */
+ str r1, [r0, #0x410] /* for S4 */
+ /* MGPCR - restore default values */
+ ldr r1, =0x0
+ str r1, [r0, #0x800] /* for M0 */
+ str r1, [r0, #0x900] /* for M1 */
+ str r1, [r0, #0xA00] /* for M2 */
+ str r1, [r0, #0xB00] /* for M3 */
+ str r1, [r0, #0xC00] /* for M4 */
+ str r1, [r0, #0xD00] /* for M5 */
+ .endm /* init_max */
+
+ /* Clock setup */
+ .macro init_clock
+ ldr r0, CCM_BASE_ADDR_W
+
+ /* default CLKO to 1/32 of the ARM core*/
+ ldr r1, [r0, #CLKCTL_COSR]
+ bic r1, r1, #0x00000FF00
+ bic r1, r1, #0x0000000FF
+ mov r2, #0x00006C00
+ add r2, r2, #0x67
+ orr r1, r1, r2
+ str r1, [r0, #CLKCTL_COSR]
+
+ ldr r2, CCM_CCMR_W
+ str r2, [r0, #CLKCTL_CCMR]
+
+ /*check clock path*/
+ ldr r2, [r0, #CLKCTL_PDR0]
+ tst r2, #0x1
+ ldrne r3, MPCTL_PARAM_532_W /* consumer path*/
+ ldreq r3, MPCTL_PARAM_399_W /* auto path*/
+
+ /*Set MPLL , arm clock and ahb clock*/
+ str r3, [r0, #CLKCTL_MPCTL]
+
+ ldr r1, PPCTL_PARAM_W
+ str r1, [r0, #CLKCTL_PPCTL]
+
+ ldr r1, [r0, #CLKCTL_PDR0]
+ orr r1, r1, #0x800000
+ str r1, [r0, #CLKCTL_PDR0]
+
+ ldr r1, CCM_PDR0_W
+ str r1, [r0, #CLKCTL_PDR0]
+ .endm /* init_clock */
+
+ /* M3IF setup */
+ .macro init_m3if
+ /* Configure M3IF registers */
+ ldr r1, M3IF_BASE_W
+ /*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+ ldr r0, =0x00000040
+ str r0, [r1] /* M3IF control reg */
+ .endm /* init_m3if */
+
+ .macro init_cs0
+ ldr r0, WEIM_CTRL_CS0_W
+ ldr r1, CS0_CSCRU_0x0000CC03
+ str r1, [r0, #CSCRU]
+ ldr r1, CS0_CSCRL_0xA0330D01
+ str r1, [r0, #CSCRL]
+ ldr r1, CS0_CSCRA_0x00220800
+ str r1, [r0, #CSCRA]
+ .endm
+
+ /* CPLD on CS5 setup */
+ .macro init_cs4
+ ldr r0, WEIM_CTRL_CS4_W
+ ldr r1, CS4_CSCRU_0x0000DCF6
+ str r1, [r0, #CSCRU]
+ ldr r1, CS4_CSCRL_0x444A4541
+ str r1, [r0, #CSCRL]
+ ldr r1, CS4_CSCRA_0x44443302
+ str r1, [r0, #CSCRA]
+ .endm /* init_cs4 */
+
+ /* CPLD on CS5 setup */
+ .macro init_cs5
+ ldr r0, WEIM_CTRL_CS5_W
+ ldr r1, CS5_CSCRU_0x0000DCF6
+ str r1, [r0, #CSCRU]
+ ldr r1, CS5_CSCRL_0x444A4541
+ str r1, [r0, #CSCRL]
+ ldr r1, CS5_CSCRA_0x44443302
+ str r1, [r0, #CSCRA]
+ .endm /* init_cs5 */
+
+ .macro setup_sdram
+ ldr r0, ESDCTL_BASE_W
+// mov r1, #0x204
+ mov r1, #0x4
+ str r1, [r0, #0x10]
+// mov r2, #RAM_BANK0_BASE
+// bl setup_sdram_bank
+ add r0, r0, #8
+ mov r2, #RAM_BANK1_BASE
+ bl setup_sdram_bank
+ .endm
+
+ .macro nfc_cmd_input
+ strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
+ mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
+ strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ bl do_wait_op_done
+ .endm // nfc_cmd_input
+
+ .macro do_addr_input
+ and r3, r3, #0xFF
+ strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
+ mov r3, #NAND_FLASH_CONFIG2_FADD_EN
+ strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ bl do_wait_op_done
+ .endm // do_addr_input
+
+ /* To support 133MHz DDR */
+ .macro init_iomuxc
+ mov r0, #0x2
+ ldr r1, IOMUXC_BASE_ADDR_W
+ add r1, r1, #0x368
+ add r2, r1, #0x4C8 -0x368
+1: str r0, [r1]
+ add r1, r1, #4
+ cmp r1, r2
+ ble 1b
+ .endm /* init_iomuxc */
+
+/*
+ * r0: control base, r1: working, r2: sdram bank base
+ */
+setup_sdram_bank:
+ ldr r1, SDRAM_0x00795429
+ str r1, [r0, #0x4]
+ ldr r1, SDRAM_0x92220000
+ str r1, [r0, #0x0]
+ mov r1, #0
+ ldr r12, SDRAM_PARAM1_MDDR
+ str r1, [r12, r2]
+
+ ldr r1, SDRAM_0xA2220000
+ str r1, [r0, #0x0]
+ mov r1, #0
+ ldr r12, SDRAM_PARAM1_MDDR
+ str r1, [r12, r2]
+ str r1, [r12, r2]
+
+ ldr r1, SDRAM_0xB2220000
+ str r1, [r0, #0x0]
+ mov r1, #0xda
+ ldr r12, SDRAM_PARAM2_MDDR
+ strb r1, [r12, r2]
+ mov r1, #0xFF
+ ldr r12, SDRAM_PARAM3_MDDR
+ strb r1, [r12, r2]
+
+ ldr r1, SDRAM_0x82228C80
+ str r1, [r0, #0x0]
+ mov pc, lr
+
+#define PLATFORM_VECTORS _platform_vectors
+ .macro _platform_vectors
+ .globl _board_BCR, _board_CFG
+_board_BCR: .long 0 // Board Control register shadow
+_board_CFG: .long 0 // Board Configuration (read at RESET)
+ .endm
+
+ARM_PPMRR: .word 0x40000015
+L2CACHE_PARAM: .word 0x00030024
+IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
+AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
+AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
+AIPS1_PARAM_W: .word 0x77777777
+MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
+MAX_PARAM1: .word 0x00302154
+CLKCTL_BASE_ADDR_W: .word CLKCTL_BASE_ADDR
+ESDCTL_BASE_W: .word ESDCTL_BASE
+M3IF_BASE_W: .word M3IF_BASE
+SDRAM_PARAM1_MDDR: .word 0x00000400
+SDRAM_PARAM2_MDDR: .word 0x00000033
+SDRAM_PARAM3_MDDR: .word 0x01000000
+SDRAM_0x92220000: .word 0x92200000
+SDRAM_0xA2220000: .word 0xA2200000
+SDRAM_0xB2220000: .word 0xB2200000
+SDRAM_0x82228C80: .word 0x82228C80
+SDRAM_0x00795429: .word 0x00795429
+IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
+CCM_CCMR_W: .word 0x003F4208
+CCM_PDR0_W: .word 0x00881800
+//MPCTL_PARAM_399_W: .word MPCTL_PARAM_399
+MPCTL_PARAM_399_W: .word 0x000F2005
+MPCTL_PARAM_532_W: .word MPCTL_PARAM_532
+//PPCTL_PARAM_W: .word PPCTL_PARAM_300
+PPCTL_PARAM_W: .word 0x00031801
+AVIC_VECTOR0_ADDR_W: .word MXCBOOT_FLAG_REG
+AVIC_VECTOR1_ADDR_W: .word MXCFIS_FLAG_REG
+MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
+CONST_0x0FFF: .word 0x0FFF
+CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
+IPU_CTRL_BASE_ADDR_W: .word IPU_CTRL_BASE_ADDR
+WEIM_CTRL_CS4_W: .word WEIM_CTRL_CS4
+WEIM_CTRL_CS5_W: .word WEIM_CTRL_CS5
+WEIM_CTRL_CS0_W: .word WEIM_CTRL_CS0
+CS0_CSCRU_0x0000CC03: .word 0x0000CC03
+CS0_CSCRL_0xA0330D01: .word 0xA0330D01
+CS0_CSCRA_0x00220800: .word 0x00220800
+#if 0
+CS5_CSCRU_0x0000DCF6: .word 0x0000DCF6
+CS5_CSCRL_0x444A4541: .word 0x444A4541
+CS5_CSCRA_0x44443302: .word 0x44443302
+#else
+CS4_CSCRU_0x0000DCF6: .word 0x0000DCF6
+CS4_CSCRL_0x444A4541: .word 0x444A4541
+CS4_CSCRA_0x44443302: .word 0x44443302
+CS5_CSCRU_0x0000DCF6: .word 0x0000DCF6
+CS5_CSCRL_0x444A4541: .word 0x444A4541
+CS5_CSCRA_0x44443302: .word 0x44443302
+#endif
+/*---------------------------------------------------------------------------*/
+/* end of hal_platform_setup.h */
+#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x00000000)
+#define CYGMEM_REGION_ram_SIZE (0x7F00000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0x97F00000)
+#define CYGMEM_REGION_rom_SIZE (0x100000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ ram : ORIGIN = 0, LENGTH = 0x7F00000
+ rom : ORIGIN = 0x97F00000, LENGTH = 0x100000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_rom_vectors (rom, 0x97F00000, LMA_EQ_VMA)
+ SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
+ SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table))
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
--- /dev/null
+version 0
+region ram 0 7F00000 0 !
+region rom 97F00000 100000 1 !
+section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
+section data 0 1 1 1 1 1 0 0 8000 bss !
+section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
+section heap1 0 8 0 0 0 0 0 0 !
+section rom_vectors 0 1 0 1 1 1 1 1 97F00000 97F00000 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata rodata !
+section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 4 0 1 0 0 0 1 data !
--- /dev/null
+#ifndef CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+#define CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+
+//=============================================================================
+//
+// plf_io.h
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/hal/fsl_board.h>
+#include <cyg/hal/hal_soc.h>
+
+#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \
+ CYG_MACRO_START \
+ { \
+ extern unsigned int system_rev; \
+ /* Next ATAG_MEM. */ \
+ _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_MEM; \
+ /* Round up so there's only one bit set in the memory size. \
+ * Don't double it if it's already a power of two, though. \
+ */ \
+ _p_->u.mem.size = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE); \
+ if (_p_->u.mem.size < CYGMEM_REGION_ram_SIZE) \
+ _p_->u.mem.size <<= 1; \
+ _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram); \
+ _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size); \
+ _p_->hdr.size = ((sizeof(struct tag_revision)) + sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_REVISION; \
+ _p_->u.revision.rev = system_rev; \
+ } \
+ CYG_MACRO_END
+
+#endif // CYGONCE_HAL_ARM_BOARD_PLF_IO_H
--- /dev/null
+#ifndef CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+#define CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+//=============================================================================
+//
+// plf_mmap.h
+//
+// Platform specific memory map support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_misc.h>
+
+// Get the pagesize for a particular virtual address:
+
+// This does not depend on the vaddr.
+#define HAL_MM_PAGESIZE(vaddr, pagesize) CYG_MACRO_START \
+ (pagesize) = SZ_1M; \
+CYG_MACRO_END
+
+// Get the physical address from a virtual address:
+
+#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START \
+ cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
+ if ( _v_ < 128 * SZ_1M ) /* SDRAM */ \
+ _v_ += SDRAM_BASE_ADDR; \
+ else /* Rest of it */ \
+ /* no change */ ; \
+ (paddr) = _v_; \
+CYG_MACRO_END
+
+/*
+ * translate the virtual address of ram space to physical address
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
+{
+ if(virt < 0x08000000) {
+ return virt|0x90000000;
+ }
+ if((virt & 0xF0000000) == 0x90000000) {
+ return virt&(~0x08000000);
+ }
+ return virt;
+}
+
+/*
+ * remap the physical address of ram space to uncacheable virtual address space
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
+{
+ /* 0x98000000~0x98FFFFFF is uncacheable meory space which is mapped to SDRAM*/
+ if((phy & 0xF0000000) == 0x90000000) {
+ phy |= 0x08000000;
+ }
+ return phy;
+}
+
+//---------------------------------------------------------------------------
+#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
--- /dev/null
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware mx35evb ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM current ;
+ package -hardware CYGPKG_HAL_ARM_MX35 current ;
+ package -hardware CYGPKG_HAL_ARM_MX35EVB current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ;
+ package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ;
+ package -hardware CYGPKG_DEVS_ETH_FEC current ;
+ package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ;
+ package -hardware CYGPKG_COMPRESS_ZLIB current ;
+ package -hardware CYGPKG_DIAGNOSIS current ;
+ package -hardware CYGPKG_IO_FLASH current ;
+ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+ package -hardware CYGPKG_DEVS_FLASH_MX35EVB_SPANSION current ;
+# package -hardware CYGPKG_DEVS_MXC_SPI current ;
+# package -hardware CYGPKG_DEVS_MXC_I2C current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package CYGPKG_MEMALLOC current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_S29WS256N {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+ inferred_value 1
+};
+
+#cdl_option CYGHWR_DEVS_FSL_SPI_VER_0_4 {
+# inferred_value 1
+#};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+ inferred_value 1
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
+ user_value 50
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ inferred_value 0x00040000
+};
+
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+ inferred_value 0x90008000
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_component CYG_HAL_STARTUP {
+ user_value ROMRAM
+};
+
+cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+ inferred_value 1
+};
+
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+ user_value 1 "FSL 200904"
+};
--- /dev/null
+/*=============================================================================
+//
+// board_diag.c
+//
+// HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_arch.h> // basic machine info
+#include <cyg/hal/hal_intr.h> // interrupt macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_if.h> // Calling-if API
+#include <cyg/hal/drv_api.h> // driver API
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/fsl_board.h> // Platform specifics
+
+static void cyg_hal_plf_duart_init(void);
+extern void cyg_hal_plf_serial_init(void);
+
+#define DUART_WORKAROUND_DELAY(a) hal_delay_us(a);
+
+
+void cyg_hal_plf_comms_init(void)
+{
+ static int initialized = 0;
+
+ if (initialized)
+ return;
+
+ initialized = 1;
+
+ /* Setup GPIO and enable transceiver for UARTs */
+// cyg_hal_plf_duart_init();
+ cyg_hal_plf_serial_init();
+}
+
+//=============================================================================
+// ST16552 DUART driver
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// There are two serial ports.
+#define CYG_DEV_SERIAL_BASE_A (BOARD_CS_UART_BASE + 0x0000) // port A
+#define CYG_DEV_SERIAL_BASE_B (BOARD_CS_UART_BASE + 0x8000) // port B
+
+//-----------------------------------------------------------------------------
+// Based on 14.7456 MHz xtal
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x60
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x30
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x18
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x10
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x08
+#endif
+
+#ifndef CYG_DEV_SERIAL_BAUD_MSB
+#error Missing/incorrect serial baud rate defined - CDL error?
+#endif
+
+//-----------------------------------------------------------------------------
+// Define the serial registers. The board is equipped with a 16552
+// serial chip.
+
+#ifdef EXT_UART_x16
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT16
+#define HAL_READ_UINT_UART HAL_READ_UINT16
+typedef cyg_uint16 uart_width;
+#else //_x8
+typedef cyg_uint8 uart_width;
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT8
+#define HAL_READ_UINT_UART HAL_READ_UINT8
+#endif
+
+#define CYG_DEV_SERIAL_RHR 0x00 // receiver buffer register, read, dlab = 0
+#define CYG_DEV_SERIAL_THR 0x00 // transmitter holding register, write, dlab = 0
+#define CYG_DEV_SERIAL_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IER 0x01 // interrupt enable register, read/write, dlab = 0
+#define CYG_DEV_SERIAL_DLM 0x01 // divisor latch (MS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IIR 0x02 // interrupt identification register, read, dlab = 0
+#define CYG_DEV_SERIAL_FCR 0x02 // fifo control register, write, dlab = 0
+#define CYG_DEV_SERIAL_AFR 0x02 // alternate function register, read/write, dlab = 1
+#define CYG_DEV_SERIAL_LCR 0x03 // line control register, read/write
+#define CYG_DEV_SERIAL_MCR 0x04
+#define CYG_DEV_SERIAL_MCR_A 0x04
+#define CYG_DEV_SERIAL_MCR_B 0x04
+#define CYG_DEV_SERIAL_LSR 0x05 // line status register, read
+#define CYG_DEV_SERIAL_MSR 0x06 // modem status register, read
+#define CYG_DEV_SERIAL_SCR 0x07 // scratch pad register
+
+// The interrupt enable register bits.
+#define SIO_IER_ERDAI 0x01 // enable received data available irq
+#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
+#define SIO_IER_ELSI 0x04 // enable receiver line status irq
+#define SIO_IER_EMSI 0x08 // enable modem status interrupt
+
+// The interrupt identification register bits.
+#define SIO_IIR_IP 0x01 // 0 if interrupt pending
+#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
+#define ISR_Tx 0x02
+#define ISR_Rx 0x04
+
+// The line status register bits.
+#define SIO_LSR_DR 0x01 // data ready
+#define SIO_LSR_OE 0x02 // overrun error
+#define SIO_LSR_PE 0x04 // parity error
+#define SIO_LSR_FE 0x08 // framing error
+#define SIO_LSR_BI 0x10 // break interrupt
+#define SIO_LSR_THRE 0x20 // transmitter holding register empty
+#define SIO_LSR_TEMT 0x40 // transmitter register empty
+#define SIO_LSR_ERR 0x80 // any error condition
+
+// The modem status register bits.
+#define SIO_MSR_DCTS 0x01 // delta clear to send
+#define SIO_MSR_DDSR 0x02 // delta data set ready
+#define SIO_MSR_TERI 0x04 // trailing edge ring indicator
+#define SIO_MSR_DDCD 0x08 // delta data carrier detect
+#define SIO_MSR_CTS 0x10 // clear to send
+#define SIO_MSR_DSR 0x20 // data set ready
+#define SIO_MSR_RI 0x40 // ring indicator
+#define SIO_MSR_DCD 0x80 // data carrier detect
+
+// The line control register bits.
+#define SIO_LCR_WLS0 0x01 // word length select bit 0
+#define SIO_LCR_WLS1 0x02 // word length select bit 1
+#define SIO_LCR_STB 0x04 // number of stop bits
+#define SIO_LCR_PEN 0x08 // parity enable
+#define SIO_LCR_EPS 0x10 // even parity select
+#define SIO_LCR_SP 0x20 // stick parity
+#define SIO_LCR_SB 0x40 // set break
+#define SIO_LCR_DLAB 0x80 // divisor latch access bit
+
+// The FIFO control register
+#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
+#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
+#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
+
+//-----------------------------------------------------------------------------
+
+typedef struct {
+ uart_width* base;
+ cyg_int32 msec_timeout;
+ int isr_vector;
+} channel_data_t;
+
+static channel_data_t channels[] = {
+#if CYGHWR_HAL_ARM_DUART_UARTA != 0
+ {(uart_width*)CYG_DEV_SERIAL_BASE_A, 1000, 0},
+#endif
+#if CYGHWR_HAL_ARM_DUART_UARTB != 0
+ {(uart_width*)CYG_DEV_SERIAL_BASE_B, 1000, 0}
+#endif
+};
+
+//-----------------------------------------------------------------------------
+
+static void init_duart_channel(channel_data_t* __ch_data)
+{
+ uart_width* base = __ch_data->base;
+ uart_width lcr;
+
+ // 8-1-no parity.
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR,
+ SIO_LCR_WLS0 | SIO_LCR_WLS1);
+ DUART_WORKAROUND_DELAY(50);
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ lcr |= SIO_LCR_DLAB;
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLL, CYG_DEV_SERIAL_BAUD_LSB);
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLM, CYG_DEV_SERIAL_BAUD_MSB);
+ lcr &= ~SIO_LCR_DLAB;
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_FCR, 0x07); // Enable & clear FIFO
+}
+
+//#define x_debug_uart_log_buf
+#ifdef x_debug_uart_log_buf
+#define x_DIAG_BUFSIZE 2048
+static char __x_log_buf[x_DIAG_BUFSIZE];
+static int x_diag_bp = 0;
+#endif
+
+void cyg_hal_plf_duart_putc(void* __ch_data, cyg_uint8 c)
+{
+ uart_width* base = ((channel_data_t*)__ch_data)->base;
+ uart_width lsr;
+
+#ifdef x_debug_uart_log_buf
+ __x_log_buf[x_diag_bp++] = c;
+#endif
+ CYGARC_HAL_SAVE_GP();
+
+ do {
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ } while ((lsr & SIO_LSR_THRE) == 0);
+
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_THR, c);
+
+ // Hang around until the character has been safely sent.
+ do {
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ } while ((lsr & SIO_LSR_THRE) == 0);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool cyg_hal_plf_duart_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+ uart_width* base = ((channel_data_t*)__ch_data)->base;
+ uart_width lsr, ch16;
+
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ if ((lsr & SIO_LSR_DR) == 0)
+ return false;
+
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_RHR, ch16);
+
+ *ch = (cyg_uint8) (ch16 & 0x00FF);
+
+ return true;
+}
+
+cyg_uint8 cyg_hal_plf_duart_getc(void* __ch_data)
+{
+ cyg_uint8 ch;
+
+ CYGARC_HAL_SAVE_GP();
+
+ while (!cyg_hal_plf_duart_getc_nonblock(__ch_data, &ch));
+
+ CYGARC_HAL_RESTORE_GP();
+ return ch;
+}
+
+static void cyg_hal_plf_duart_write(void* __ch_data, const cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while (__len-- > 0)
+ cyg_hal_plf_duart_putc(__ch_data, *__buf++);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static void cyg_hal_plf_duart_read(void* __ch_data, cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while (__len-- > 0)
+ *__buf++ = cyg_hal_plf_duart_getc(__ch_data);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool cyg_hal_plf_duart_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+ int delay_count;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_bool res;
+
+ CYGARC_HAL_SAVE_GP();
+
+ delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+ for (;;) {
+ res = cyg_hal_plf_duart_getc_nonblock(__ch_data, ch);
+ if (res || 0 == delay_count--)
+ break;
+
+ CYGACC_CALL_IF_DELAY_US(100);
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static int cyg_hal_plf_duart_control(void *__ch_data,
+ __comm_control_cmd_t __func, ...)
+{
+ static int irq_state = 0;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ uart_width ier;
+ int ret = 0;
+
+ CYGARC_HAL_SAVE_GP();
+
+ switch (__func) {
+ case __COMMCTL_IRQ_ENABLE:
+ HAL_INTERRUPT_UNMASK(chan->isr_vector);
+ HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ ier |= SIO_IER_ERDAI;
+ HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ irq_state = 1;
+ break;
+ case __COMMCTL_IRQ_DISABLE:
+ ret = irq_state;
+ irq_state = 0;
+ HAL_INTERRUPT_MASK(chan->isr_vector);
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ ier &= ~SIO_IER_ERDAI;
+ HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ break;
+ case __COMMCTL_DBG_ISR_VECTOR:
+ ret = chan->isr_vector;
+ break;
+ case __COMMCTL_SET_TIMEOUT:
+ {
+ va_list ap;
+
+ va_start(ap, __func);
+
+ ret = chan->msec_timeout;
+ chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+ va_end(ap);
+ }
+ break;
+ default:
+ break;
+ }
+ CYGARC_HAL_RESTORE_GP();
+ return ret;
+}
+
+static int cyg_hal_plf_duart_isr(void *__ch_data, int* __ctrlc,
+ CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ uart_width _iir;
+ int res = 0;
+ CYGARC_HAL_SAVE_GP();
+
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IIR, _iir);
+ _iir &= SIO_IIR_ID_MASK;
+
+ *__ctrlc = 0;
+ if ( ISR_Rx == _iir ) {
+ uart_width c, lsr;
+ cyg_uint8 c8;
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_LSR, lsr);
+ if (lsr & SIO_LSR_DR) {
+
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_RHR, c);
+
+ c8 = (cyg_uint8) (c & 0x00FF);
+
+ if (cyg_hal_is_break( &c8 , 1 ))
+ *__ctrlc = 1;
+ }
+
+ // Acknowledge the interrupt
+ HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+ res = CYG_ISR_HANDLED;
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static void cyg_hal_plf_duart_init(void)
+{
+ hal_virtual_comm_table_t* comm;
+ int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ int i;
+
+ // Init channels
+#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
+ for (i = 0; i < NUMOF(channels); i++) {
+ HAL_INTERRUPT_MASK(channels[i].isr_vector);
+ init_duart_channel(&channels[i]);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_duart_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_duart_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_duart_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_duart_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_duart_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_duart_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_duart_getc_timeout);
+ }
+
+ // Restore original console
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
+
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
+#define __BASE CMA101_DUARTA
+#define _INT CYGNUM_HAL_INTERRUPT_SERIAL_A
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1)
+#define __BASE CMA101_DUARTB
+#define _INT CYGNUM_HAL_INTERRUPT_SERIAL_B
+#endif
+
+#ifdef __BASE
+
+#ifdef CYGSEM_HAL_ROM_MONITOR
+#define CYG_HAL_STARTUP_ROM
+#define CYG_HAL_STARTUP_ROMRAM
+#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#endif
+
+#if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define HAL_DIAG_USES_HARDWARE
+#elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
+#define HAL_DIAG_USES_HARDWARE
+#elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+#define HAL_DIAG_USES_HARDWARE
+#endif
+
+static channel_data_t channel = {
+ (uart_width*) _BASE, 0, 0
+};
+
+#ifdef HAL_DIAG_USES_HARDWARE
+
+void hal_diag_init(void)
+{
+ static int init = 0;
+ char *msg = "\n\rARM eCos\n\r";
+ uart_width lcr;
+
+ if (init++) return;
+
+ init_duart_channel(&channel);
+
+ while (*msg) hal_diag_write_char(*msg++);
+}
+
+#ifdef DEBUG_DIAG
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define DIAG_BUFSIZE 32
+#else
+#define DIAG_BUFSIZE 2048
+#endif
+static char diag_buffer[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+
+void hal_diag_write_char(char c)
+{
+ uart_width lsr;
+
+ hal_diag_init();
+
+ cyg_hal_plf_duart_putc(&channel, c)
+
+#ifdef DEBUG_DIAG
+ diag_buffer[diag_bp++] = c;
+ if (diag_bp == DIAG_BUFSIZE) {
+ while (1) ;
+ diag_bp = 0;
+ }
+#endif
+}
+
+void hal_diag_read_char(char *c)
+{
+ *c = cyg_hal_plf_duart_getc(&channel);
+}
+
+#else // HAL_DIAG relies on GDB
+
+// Initialize diag port - assume GDB channel is already set up
+void hal_diag_init(void)
+{
+ if (0) init_duart_channel(&channel); // avoid warning
+}
+
+// Actually send character down the wire
+static void hal_diag_write_char_serial(char c)
+{
+ cyg_hal_plf_duart_putc(&channel, c);
+}
+
+static bool hal_diag_read_serial(char *c)
+{
+ long timeout = 1000000000; // A long time...
+
+ while (!cyg_hal_plf_duart_getc_nonblock(&channel, c))
+ if (0 == --timeout) return false;
+
+ return true;
+}
+
+void hal_diag_read_char(char *c)
+{
+ while (!hal_diag_read_serial(c)) ;
+}
+
+void hal_diag_write_char(char c)
+{
+ static char line[100];
+ static int pos = 0;
+
+ // No need to send CRs
+ if (c == '\r') return;
+
+ line[pos++] = c;
+
+ if (c == '\n' || pos == sizeof(line)) {
+ CYG_INTERRUPT_STATE old;
+
+ // Disable interrupts. This prevents GDB trying to interrupt us
+ // while we are in the middle of sending a packet. The serial
+ // receive interrupt will be seen when we re-enable interrupts
+ // later.
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+#else
+ HAL_DISABLE_INTERRUPTS(old);
+#endif
+
+ while (1) {
+ static char hex[] = "0123456789ABCDEF";
+ cyg_uint8 csum = 0;
+ int i;
+ char c1;
+
+ hal_diag_write_char_serial('$');
+ hal_diag_write_char_serial('O');
+ csum += 'O';
+ for (i = 0; i < pos; i++) {
+ char ch = line[i];
+ char h = hex[(ch>>4)&0xF];
+ char l = hex[ch&0xF];
+ hal_diag_write_char_serial(h);
+ hal_diag_write_char_serial(l);
+ csum += h;
+ csum += l;
+ }
+ hal_diag_write_char_serial('#');
+ hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
+ hal_diag_write_char_serial(hex[csum&0xF]);
+
+ // Wait for the ACK character '+' from GDB here and handle
+ // receiving a ^C instead. This is the reason for this clause
+ // being a loop.
+ if (!hal_diag_read_serial(&c1))
+ continue; // No response - try sending packet again
+
+ if ( c1 == '+' )
+ break; // a good acknowledge
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
+ if ( c1 == 3 ) {
+ // Ctrl-C: breakpoint.
+ cyg_hal_gdb_interrupt (__builtin_return_address(0));
+ break;
+ }
+#endif
+ // otherwise, loop round again
+ }
+
+ pos = 0;
+
+ // And re-enable interrupts
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+#else
+ HAL_RESTORE_INTERRUPTS(old);
+#endif
+
+ }
+}
+#endif
+
+#endif // __BASE
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
--- /dev/null
+//==========================================================================
+//
+// board_misc.c
+//
+// HAL misc board support code for the board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include <redboot.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h> // Interrupt names
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/fsl_board.h> // Platform specifics
+
+#include <cyg/infra/diag.h> // diag_printf
+
+// All the MM table layout is here:
+#include <cyg/hal/hal_mm.h>
+
+externC void* memset(void *, int, size_t);
+static void plf_setup_uart(void);
+static void plf_setup_fec(void);
+
+void hal_mmu_init(void)
+{
+ unsigned long ttb_base = RAM_BANK1_BASE + 0x4000;
+ unsigned long i;
+
+ /*
+ * Set the TTB register
+ */
+ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
+
+ /*
+ * Set the Domain Access Control Register
+ */
+ i = ARM_ACCESS_DACR_DEFAULT;
+ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+
+ /*
+ * First clear all TT entries - ie Set them to Faulting
+ */
+ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+
+ /* Actual Virtual Size Attributes Function */
+ /* Base Base MB cached? buffered? access permissions */
+ /* xxx00000 xxx00000 */
+ X_ARM_MMU_SECTION(0x000, 0xF00, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */
+ X_ARM_MMU_SECTION(0x300, 0x300, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* L2CC */
+ X_ARM_MMU_SECTION(0x400, 0x400, 0x400, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Internal Regsisters upto SDRAM*/
+ X_ARM_MMU_SECTION(0x900, 0x000, 0x80, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 1:128M*/
+ X_ARM_MMU_SECTION(0x900, 0x900, 0x80, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 1:128M*/
+ X_ARM_MMU_SECTION(0x900, 0x980, 0x80, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 1:128M*/
+ X_ARM_MMU_SECTION(0xA00, 0xA00, 0x200, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Flash */
+ X_ARM_MMU_SECTION(0xB00, 0xB00, 0x20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PSRAM */
+ X_ARM_MMU_SECTION(0xB20, 0xB20, 0x1E0, ARM_UNCACHEABLE, ARM_UNBUFFERABLE,ARM_ACCESS_PERM_RW_RW); /* ESDCTL, WEIM, M3IF, EMI, NFC, External I/O */
+}
+
+//
+// Platform specific initialization
+//
+
+unsigned int g_clock_src;
+
+void plf_hardware_init(void)
+{
+ int i;
+ unsigned long val = readl(CCM_BASE_ADDR + CLKCTL_CCMR);
+
+ g_clock_src = FREQ_24MHZ;
+ /* PBC setup */
+ /* Reset interrupt status reg */
+#if 0
+ writel(0x0000007, PBC_CTRL1_SET);
+ for(i=0; i<10000; i++);
+ writel(0x0000007, PBC_CTRL1_CLR);
+#endif
+ plf_setup_uart();
+ plf_setup_fec();
+#if 0
+ // UART1
+ /*RXD1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x188);
+ writel(0x1E0, IOMUXC_BASE_ADDR + 0x55C);
+
+ /*TXD1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x18C);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x560);
+
+ /*RTS1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x190);
+ writel(0x1E0, IOMUXC_BASE_ADDR + 0x564);
+
+ /*CTS1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x194);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x568);
+
+ // UART2
+ //writel(0x13131300, IOMUXC_BASE_ADDR + 0x70);
+ //writel(0x00001313, IOMUXC_BASE_ADDR + 0x74);
+ //writel(0x00000040, IOMUXC_BASE_ADDR + 0x7C);
+ //writel(0x40400000, IOMUXC_BASE_ADDR + 0x78);
+#endif
+}
+
+static void plf_setup_uart(void)
+{
+ // UART1
+ /*RXD1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x188);
+ writel(0x1E0, IOMUXC_BASE_ADDR + 0x55C);
+
+ /*TXD1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x18C);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x560);
+
+ /*RTS1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x190);
+ writel(0x1E0, IOMUXC_BASE_ADDR + 0x564);
+
+ /*CTS1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x194);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x568);
+
+ // UART2
+}
+
+static void plf_setup_fec(void)
+{
+ /*FEC_TX_CLK*/
+ writel(0, IOMUXC_BASE_ADDR + 0x02E0);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x0744);
+
+ /*FEC_RX_CLK*/
+ writel(0, IOMUXC_BASE_ADDR + 0x02E4);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x0748);
+
+ /*FEC_RX_DV*/
+ writel(0, IOMUXC_BASE_ADDR + 0x02E8);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x074C);
+
+ /*FEC_COL*/
+ writel(0, IOMUXC_BASE_ADDR + 0x02EC);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x0750);
+
+ /*FEC_RDATA0*/
+ writel(0, IOMUXC_BASE_ADDR + 0x02F0);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x0754);
+
+ /*FEC_TDATA0*/
+ writel(0, IOMUXC_BASE_ADDR + 0x02F4);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x0758);
+
+ /*FEC_TX_EN*/
+ writel(0, IOMUXC_BASE_ADDR + 0x02F8);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x075C);
+
+ /*FEC_MDC*/
+ writel(0, IOMUXC_BASE_ADDR + 0x02FC);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x0760);
+
+ /*FEC_MDIO*/
+ writel(0, IOMUXC_BASE_ADDR + 0x0300);
+ writel(0x1F0, IOMUXC_BASE_ADDR + 0x0764);
+
+ /*FEC_TX_ERR*/
+ writel(0, IOMUXC_BASE_ADDR + 0x0304);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x0768);
+
+ /*FEC_RX_ERR*/
+ writel(0, IOMUXC_BASE_ADDR + 0x0308);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x076C);
+
+ /*FEC_CRS*/
+ writel(0, IOMUXC_BASE_ADDR + 0x030C);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x0770);
+
+ /*FEC_RDATA1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x0310);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x0774);
+
+ /*FEC_TDATA1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x0314);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x0778);
+
+ /*FEC_RDATA2*/
+ writel(0, IOMUXC_BASE_ADDR + 0x0318);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x077C);
+
+ /*FEC_TDATA2*/
+ writel(0, IOMUXC_BASE_ADDR + 0x031C);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x0780);
+
+ /*FEC_RDATA3*/
+ writel(0, IOMUXC_BASE_ADDR + 0x0320);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x0784);
+
+ /*FEC_TDATA3*/
+ writel(0, IOMUXC_BASE_ADDR + 0x0324);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x0788);
+}
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+typedef void code_fun(void);
+
+void board_program_new_stack(void *func)
+{
+ register CYG_ADDRESS stack_ptr asm("sp");
+ register CYG_ADDRESS old_stack asm("r4");
+ register code_fun *new_func asm("r0");
+ old_stack = stack_ptr;
+ stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
+ new_func = (code_fun*)func;
+ new_func();
+ stack_ptr = old_stack;
+}
+
+static void display_clock_src(void)
+{
+ diag_printf("\n");
+ diag_printf("Clock input is 24 MHz");
+}
+RedBoot_init(display_clock_src, RedBoot_INIT_LAST);
+
+// ------------------------------------------------------------------------
--- /dev/null
+//==========================================================================
+//
+// redboot_cmds.c
+//
+// Board [platform] specific RedBoot commands
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+#include <redboot.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/plf_mmap.h>
+#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <flash_config.h>
+
+#if (REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE)
+#error REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE
+#endif
+
+RedBoot_config_option("Board specifics",
+ brd_specs,
+ ALWAYS_ENABLED,
+ true,
+ CONFIG_INT,
+ 0
+ );
+#endif //CYGSEM_REDBOOT_FLASH_CONFIG
+
+char HAL_PLATFORM_EXTRA[55] = " PASS 1.0 [x32 DDR]";
+
+static void runImg(int argc, char *argv[]);
+
+RedBoot_cmd("run",
+ "Run an image at a location with MMU off",
+ "[<virtual addr>]",
+ runImg
+ );
+
+void launchRunImg(unsigned long addr)
+{
+ asm volatile ("mov r12, r0;");
+ HAL_CLEAN_INVALIDATE_L2();
+ HAL_DISABLE_L2();
+ HAL_MMU_OFF();
+ asm volatile (
+ "mov r0, #0;"
+ "mov r1, r12;"
+ "mov r11, #0;"
+ "mov r12, #0;"
+ "mrs r10, cpsr;"
+ "bic r10, r10, #0xF0000000;"
+ "msr cpsr_f, r10;"
+ "mov pc, r1"
+ );
+}
+
+extern unsigned long entry_address;
+
+static void runImg(int argc,char *argv[])
+{
+ unsigned int virt_addr, phys_addr;
+
+ // Default physical entry point for Symbian
+ if (entry_address == 0xFFFFFFFF)
+ virt_addr = 0x800000;
+ else
+ virt_addr = entry_address;
+
+ if (!scan_opts(argc,argv,1,0,0,(void*)&virt_addr,
+ OPTION_ARG_TYPE_NUM, "virtual address"))
+ return;
+
+ if (entry_address != 0xFFFFFFFF)
+ diag_printf("load entry_address=0x%lx\n", entry_address);
+ HAL_VIRT_TO_PHYS_ADDRESS(virt_addr, phys_addr);
+
+ diag_printf("virt_addr=0x%x\n",virt_addr);
+ diag_printf("phys_addr=0x%x\n",phys_addr);
+
+ launchRunImg(phys_addr);
+}
+
+#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYG_HAL_STARTUP_ROMRAM)
+
+RedBoot_cmd("romupdate",
+ "Update Redboot with currently running image",
+ "",
+ romupdate
+ );
+
+extern int flash_program(void *_addr, void *_data, int len, void **err_addr);
+extern int flash_erase(void *addr, int len, void **err_addr);
+extern char *flash_errmsg(int err);
+extern unsigned char *ram_end; //ram end is where the redboot starts FIXME: use PC value
+
+#ifdef CYGPKG_IO_FLASH
+void romupdate(int argc, char *argv[])
+{
+ void *err_addr, *base_addr;
+ int stat;
+
+ if (IS_FIS_FROM_NAND()) {
+ base_addr = (void*)MXC_NAND_BASE_DUMMY;
+ diag_printf("Updating ROM in NAND flash\n");
+ } else if (IS_FIS_FROM_NOR()) {
+ base_addr = (void*)BOARD_FLASH_START;
+ diag_printf("Updating ROM in NOR flash\n");
+ } else {
+ diag_printf("romupdate not supported\n");
+ diag_printf("Use \"factive [NOR|NAND]\" to select either NOR or NAND flash\n");
+ }
+
+ // Erase area to be programmed
+ if ((stat = flash_erase((void *)base_addr,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ (void **)&err_addr)) != 0) {
+ diag_printf("Can't erase region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ return;
+ }
+ // Now program it
+ if ((stat = flash_program((void *)base_addr, (void *)ram_end,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ (void **)&err_addr)) != 0) {
+ diag_printf("Can't program region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ }
+}
+RedBoot_cmd("factive",
+ "Enable one flash media for Redboot",
+ "[NOR | NAND]",
+ factive
+ );
+
+void factive(int argc, char *argv[])
+{
+ unsigned long phys_addr;
+
+ if (argc != 2) {
+ diag_printf("Invalid factive cmd\n");
+ return;
+ }
+
+ if (strcasecmp(argv[1], "NOR") == 0) {
+#ifndef MXCFLASH_SELECT_NOR
+ diag_printf("Not supported\n");
+ return;
+#else
+ MXC_ASSERT_NOR_BOOT();
+#endif
+ } else if (strcasecmp(argv[1], "NAND") == 0) {
+#ifndef MXCFLASH_SELECT_NAND
+ diag_printf("Not supported\n");
+ return;
+#else
+ MXC_ASSERT_NAND_BOOT();
+#endif
+ } else {
+ diag_printf("Invalid command: %s\n", argv[1]);
+ return;
+ }
+ HAL_VIRT_TO_PHYS_ADDRESS(ram_end, phys_addr);
+
+ launchRunImg(phys_addr);
+}
+#endif //CYGPKG_IO_FLASH
+#endif /* CYG_HAL_STARTUP_ROMRAM */
--- /dev/null
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): gthomas
+# Original data: gthomas
+# Contributors:
+# Date: 2000-05-08
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+cdl_package CYGPKG_HAL_ARM_MX35 {
+ display "Freescale SoC architecture"
+ parent CYGPKG_HAL_ARM
+ hardware
+ include_dir cyg/hal
+ define_header hal_arm_soc.h
+ description "
+ This HAL variant package provides generic
+ support for the Freescale SoC. It is also
+ necessary to select a specific target platform HAL
+ package."
+
+ implements CYGINT_HAL_ARM_ARCH_ARM9
+ implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+
+ # Let the architectural HAL see this variant's interrupts file -
+ # the SoC has no variation between targets here.
+ define_proc {
+ puts $::cdl_header "#define CYGBLD_HAL_VAR_INTS_H <cyg/hal/hal_var_ints.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H"
+
+ puts $::cdl_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 1000000"
+ }
+
+ compile soc_diag.c soc_misc.c
+ compile -library=libextras.a cmds.c
+
+ cdl_option CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK {
+ display "Processor clock rate"
+ active_if { CYG_HAL_STARTUP == "ROM" }
+ flavor data
+ legal_values 150000 200000
+ default_value { CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT ?
+ CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT : 150000}
+ description "
+ The processor can run at various frequencies.
+ These values are expressed in KHz. Note that there are
+ several steppings of the rated to run at different
+ maximum frequencies. Check the specs to make sure that your
+ particular processor can run at the rate you select here."
+ }
+
+ # Real-time clock/counter specifics
+ cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+ display "Real-time clock constants"
+ flavor none
+ no_define
+
+ cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+ display "Real-time clock numerator"
+ flavor data
+ calculated 1000000000
+ }
+ cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+ display "Real-time clock denominator"
+ flavor data
+ default_value 100
+ description "
+ This option selects the heartbeat rate for the real-time clock.
+ The rate is specified in ticks per second. Change this value
+ with caution - too high and your system will become saturated
+ just handling clock interrupts, too low and some operations
+ such as thread scheduling may become sluggish."
+ }
+ cdl_option CYGNUM_HAL_RTC_PERIOD {
+ display "Real-time clock period"
+ flavor data
+ calculated (3686400/CYGNUM_HAL_RTC_DENOMINATOR) ;# Clock for OS Timer is 3.6864MHz
+ }
+ }
+
+ # Control over hardware layout.
+ cdl_interface CYGHWR_HAL_ARM_SOC_UART1 {
+ display "UART1 available as diagnostic/debug channel"
+ description "
+ The chip has multiple serial channels which may be
+ used for different things on different platforms. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_SOC_UART2 {
+ display "UART2 available as diagnostic/debug channel"
+ description "
+ The chip has multiple serial channels which may be
+ used for different things on different platforms. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_SOC_UART3 {
+ display "UART3 available as diagnostic/debug channel"
+ description "
+ The chip has multiple serial channels which may be
+ used for different things on different platforms. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+}
--- /dev/null
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+
+//=============================================================================
+//
+// hal_cache.h
+//
+// HAL cache control API
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
+
+//-----------------------------------------------------------------------------
+// Cache dimensions
+
+// Data cache
+#define HAL_DCACHE_SIZE 0x4000 // 16KB Size of data cache in bytes
+#define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
+#define HAL_DCACHE_WAYS 64 // Associativity of the cache
+
+// Instruction cache
+#define HAL_ICACHE_SIZE 0x4000 // Size of cache in bytes
+#define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
+#define HAL_ICACHE_WAYS 64 // Associativity of the cache
+
+#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE / (HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
+#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE / (HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
+
+#define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
+#define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x20
+#define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x100
+//-----------------------------------------------------------------------------
+// Global control of data cache
+#ifdef L1CC_ENABLED
+// Enable the data cache
+#define HAL_DCACHE_ENABLE_L1() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mrc p15, 0, r1, c1, c0, 0;" \
+ "orr r1, r1, #0x0007;" /* enable DCache (also ensures */ \
+ /* the MMU, alignment faults, and */ \
+ "mcr p15, 0, r1, c1, c0, 0" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE_L1() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mov r1, #0;" \
+ "mcr p15, 0, r1, c7, c6, 0;" /* clear data cache */ \
+ "mrc p15, 0, r1, c1, c0, 0;" \
+ "bic r1, r1, #0x0004;" /* disable DCache */ \
+ /* but not MMU and alignment faults */ \
+ "mcr p15, 0, r1, c1, c0, 0" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL_L1() \
+CYG_MACRO_START /* this macro can discard dirty cache lines. */ \
+ asm volatile ( \
+ "mov r0, #0;" \
+ "mcr p15, 0, r0, c7, c6, 0;" /* flush d-cache */ \
+ "mcr p15, 0, r0, c8, c7, 0;" /* flush i+d-TLBs */ \
+ : \
+ : \
+ : "r0","memory" /* clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Synchronize the contents of the cache with memory.
+// using ARM9's defined(CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX)
+#define HAL_DCACHE_SYNC_L1() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "mov r0, #0x0;" \
+ "mcr p15, 0, r0, c7, c14, 0;" /* clean, invalidate Dcache*/ \
+ "mcr p15, 0, r0, c7, c10, 4;" /* drain the write buffer */ \
+ "mcr p15, 0, r0, c7, c10, 5;" /* data memory barrier */ \
+ : \
+ : \
+ : "r0" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Query the state of the data cache
+#define HAL_DCACHE_IS_ENABLED(_state_) \
+CYG_MACRO_START \
+ register int reg; \
+ asm volatile ( \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "mrc p15, 0, %0, c1, c0, 0;" \
+ : "=r"(reg) \
+ : \
+ ); \
+ (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \
+CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE_L1() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mrc p15, 0, r1, c1, c0, 0;" \
+ "orr r1, r1, #0x1000;" \
+ "orr r1, r1, #0x0003;" /* enable ICache (also ensures */ \
+ /* that MMU and alignment faults */ \
+ /* are enabled) */ \
+ "mcr p15, 0, r1, c1, c0, 0" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Query the state of the instruction cache
+#define HAL_ICACHE_IS_ENABLED(_state_) \
+CYG_MACRO_START \
+ register cyg_uint32 reg; \
+ asm volatile ( \
+ "mrc p15, 0, %0, c1, c0, 0" \
+ : "=r"(reg) \
+ : \
+ ); \
+ \
+ (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \
+CYG_MACRO_END
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE_L1() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mrc p15, 0, r1, c1, c0, 0;" \
+ "bic r1, r1, #0x1000;" /* disable ICache (but not MMU, etc) */ \
+ "mcr p15, 0, r1, c1, c0, 0;" \
+ "mov r1, #0;" \
+ "mcr p15, 0, r1, c7, c5, 0;" /* flush ICache */ \
+ "mcr p15, 0, r1, c7, c5, 4;" /* flush prefetch buffer */ \
+ "nop;" /* next few instructions may be via cache */ \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL_L1() \
+CYG_MACRO_START \
+ /* this macro can discard dirty cache lines (N/A for ICache) */ \
+ asm volatile ( \
+ "mov r1, #0;" \
+ "mcr p15, 0, r1, c7, c5, 0;" /* flush ICache */ \
+ "mcr p15, 0, r1, c8, c5, 0;" /* flush ITLB only */ \
+ "mcr p15, 0, r1, c7, c5, 4;" /* flush prefetch buffer */ \
+ "nop;" /* next few instructions may be via cache */ \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Synchronize the contents of the cache with memory.
+// (which includes flushing out pending writes)
+#define HAL_ICACHE_SYNC() \
+CYG_MACRO_START \
+ HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
+ HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
+CYG_MACRO_END
+#else
+
+#define HAL_DCACHE_ENABLE_L1()
+#define HAL_DCACHE_DISABLE_L1()
+#define HAL_DCACHE_INVALIDATE_ALL_L1()
+#define HAL_DCACHE_SYNC_L1()
+
+#define HAL_DCACHE_IS_ENABLED(_state_) \
+CYG_MACRO_START \
+ register int reg; \
+ asm volatile ( \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "mrc p15, 0, %0, c1, c0, 0;" \
+ : "=r"(reg) \
+ : \
+ ); \
+ (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \
+CYG_MACRO_END
+
+#define HAL_ICACHE_ENABLE_L1()
+
+#define HAL_ICACHE_IS_ENABLED(_state_) \
+CYG_MACRO_START \
+ register cyg_uint32 reg; \
+ asm volatile ( \
+ "mrc p15, 0, %0, c1, c0, 0" \
+ : "=r"(reg) \
+ : \
+ ); \
+ \
+ (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \
+CYG_MACRO_END
+
+#define HAL_ICACHE_DISABLE_L1()
+#define HAL_ICACHE_INVALIDATE_ALL_L1()
+#define HAL_ICACHE_SYNC()
+#endif
+
+// Query the state of the L2 cache
+#define HAL_L2CACHE_IS_ENABLED(_state_) \
+CYG_MACRO_START \
+ _state_ = (*(unsigned long *)(0x30000100)) & 0x1; \
+CYG_MACRO_END
+
+#ifdef L2CC_ENABLED
+
+#define HAL_ENABLE_L2() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "ldr r0, =0x30000100;" \
+ "ldr r1, [r0];" \
+ "orr r1, r1, #0x1;" \
+ "str r1, [r0];" \
+ : \
+ : \
+ : "r0", "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+#define HAL_DISABLE_L2() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "ldr r0, =0x30000000;" \
+ "ldr r1, [r0, #0x100];" \
+ "bic r1, r1, #0x1;" \
+ "str r1, [r0, #0x100];" \
+ : \
+ : \
+ : "r0", "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+#define HAL_SYNC_L2() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "ldr r0, =0x30000000;" \
+ "ldr r1, =0x0;" \
+ "str r1, [r0, #0x730];" \
+ : \
+ : \
+ : "r0", "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+#define HAL_INVALIDATE_L2() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "ldr r0, =0x30000000;" \
+ "ldr r1, =0xFF;" \
+ "str r1, [r0, #0x77C];" \
+ "2: " \
+ "ldr r1, [r0, #0x77C];" \
+ "cmp r1, #0x0;" \
+ "bne 2b;" \
+ : \
+ : \
+ : "r0", "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+#define HAL_CLEAN_INVALIDATE_L2() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "ldr r0, =0x30000000;" \
+ "ldr r1, =0xFF;" \
+ "str r1, [r0, #0x7FC];" \
+ "2: " \
+ "ldr r1, [r0, #0x7FC];" \
+ "cmp r1, #0x0;" \
+ "bne 2b;" \
+ : \
+ : \
+ : "r0", "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+#else //L2CC_ENABLED
+
+#define HAL_ENABLE_L2()
+#define HAL_DISABLE_L2()
+#define HAL_INVALIDATE_L2()
+#define HAL_CLEAN_INVALIDATE_L2()
+#define HAL_SYNC_L2()
+#endif //L2CC_ENABLED
+
+/*********************** Exported macros *******************/
+
+#define HAL_DCACHE_ENABLE() { \
+ HAL_DCACHE_ENABLE_L1(); \
+ HAL_ENABLE_L2(); \
+}
+
+#define HAL_DCACHE_DISABLE() { \
+ HAL_DCACHE_DISABLE_L1(); \
+ HAL_DISABLE_L2(); \
+}
+
+#define HAL_DCACHE_INVALIDATE_ALL() { \
+ HAL_DCACHE_INVALIDATE_ALL_L1(); \
+ HAL_CLEAN_INVALIDATE_L2(); \
+}
+
+#define HAL_DCACHE_SYNC() { \
+ HAL_DCACHE_SYNC_L1(); \
+ HAL_SYNC_L2(); \
+}
+
+#define HAL_ICACHE_INVALIDATE_ALL() { \
+ HAL_ICACHE_INVALIDATE_ALL_L1(); \
+ HAL_CLEAN_INVALIDATE_L2(); \
+}
+
+#define HAL_ICACHE_DISABLE() { \
+ HAL_ICACHE_DISABLE_L1(); \
+}
+
+#define HAL_ICACHE_ENABLE() { \
+ HAL_ICACHE_ENABLE_L1(); \
+}
+
+#define CYGARC_HAL_EXEC_FIXUP() \
+ "tst %7, #0x20;\n" \
+ "moveq r0, #0x30000000;\n" \
+ "moveq r1, #0x1;\n" \
+ "streq r1, [r0, #0x100];\n" \
+
+#endif // ifndef CYGONCE_HAL_CACHE_H
+// End of hal_cache.h
--- /dev/null
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+
+/*=============================================================================
+//
+// hal_diag.h
+//
+// HAL Support for Kernel Diagnostic Routines
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+#include <cyg/hal/hal_if.h>
+
+#define HAL_DIAG_INIT() hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
+
+#else // everything by steam
+
+/*---------------------------------------------------------------------------*/
+/* functions implemented in hal_diag.c */
+
+externC void hal_diag_init(void);
+externC void hal_diag_write_char(char c);
+externC void hal_diag_read_char(char *c);
+
+/*---------------------------------------------------------------------------*/
+
+#define HAL_DIAG_INIT() hal_diag_init()
+
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_)
+
+#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_)
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
+// LED
+
+externC void hal_diag_led(int n);
+
+/*---------------------------------------------------------------------------*/
+/* end of hal_diag.h */
+#endif /* CYGONCE_HAL_DIAG_H */
--- /dev/null
+#ifndef CYGONCE_HAL_MM_H
+#define CYGONCE_HAL_MM_H
+
+//=============================================================================
+//
+// hal_mm.h
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+// -------------------------------------------------------------------------
+// MMU initialization:
+//
+// These structures are laid down in memory to define the translation
+// table.
+//
+
+/*
+ * Translation Table Base Bit Masks
+ */
+#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
+
+/*
+ * Domain Access Control Bit Masks
+ */
+#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2)
+
+struct ARM_MMU_FIRST_LEVEL_FAULT {
+ unsigned int id : 2;
+ unsigned int sbz : 30;
+};
+
+#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
+
+struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
+ unsigned int id : 2;
+ unsigned int imp : 2;
+ unsigned int domain : 4;
+ unsigned int sbz : 1;
+ unsigned int base_address : 23;
+};
+
+#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
+
+struct ARM_MMU_FIRST_LEVEL_SECTION {
+ unsigned int id : 2;
+ unsigned int b : 1;
+ unsigned int c : 1;
+ unsigned int imp : 1;
+ unsigned int domain : 4;
+ unsigned int sbz0 : 1;
+ unsigned int ap : 2;
+ unsigned int sbz1 : 8;
+ unsigned int base_address : 12;
+};
+
+#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
+
+struct ARM_MMU_FIRST_LEVEL_RESERVED {
+ unsigned int id : 2;
+ unsigned int sbz : 30;
+};
+
+#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
+
+#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
+ (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
+
+#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
+
+#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
+ cacheable, bufferable, perm) \
+ CYG_MACRO_START \
+ register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
+ \
+ desc.word = 0; \
+ desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
+ desc.section.domain = 0; \
+ desc.section.c = (cacheable); \
+ desc.section.b = (bufferable); \
+ desc.section.ap = (perm); \
+ desc.section.base_address = (actual_base); \
+ *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
+ = desc.word; \
+ CYG_MACRO_END
+
+#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \
+ { \
+ int i; int j = abase; int k = vbase; \
+ for (i = size; i > 0 ; i--,j++,k++) { \
+ ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
+ } \
+ }
+
+union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
+ unsigned long word;
+ struct ARM_MMU_FIRST_LEVEL_FAULT fault;
+ struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
+ struct ARM_MMU_FIRST_LEVEL_SECTION section;
+ struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
+};
+
+#define ARM_UNCACHEABLE 0
+#define ARM_CACHEABLE 1
+#define ARM_UNBUFFERABLE 0
+#define ARM_BUFFERABLE 1
+
+#define ARM_ACCESS_PERM_NONE_NONE 0
+#define ARM_ACCESS_PERM_RO_NONE 0
+#define ARM_ACCESS_PERM_RO_RO 0
+#define ARM_ACCESS_PERM_RW_NONE 1
+#define ARM_ACCESS_PERM_RW_RO 2
+#define ARM_ACCESS_PERM_RW_RW 3
+
+/*
+ * Initialization for the Domain Access Control Register
+ */
+#define ARM_ACCESS_DACR_DEFAULT ( \
+ ARM_ACCESS_TYPE_MANAGER(0) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(1) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(2) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(3) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(4) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(5) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(6) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(7) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(8) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(9) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(10) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(11) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(12) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(13) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(14) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(15) )
+
+// ------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_MM_H
+// End of hal_mm.h
+
+
+
+
+
--- /dev/null
+//==========================================================================
+//
+// hal_soc.h
+//
+// SoC chip definitions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#ifndef __HAL_SOC_H__
+#define __HAL_SOC_H__
+
+#ifdef __ASSEMBLER__
+
+#define REG8_VAL(a) (a)
+#define REG16_VAL(a) (a)
+#define REG32_VAL(a) (a)
+
+#define REG8_PTR(a) (a)
+#define REG16_PTR(a) (a)
+#define REG32_PTR(a) (a)
+
+#else /* __ASSEMBLER__ */
+
+extern char HAL_PLATFORM_EXTRA[];
+#define REG8_VAL(a) ((unsigned char)(a))
+#define REG16_VAL(a) ((unsigned short)(a))
+#define REG32_VAL(a) ((unsigned int)(a))
+
+#define REG8_PTR(a) ((volatile unsigned char *)(a))
+#define REG16_PTR(a) ((volatile unsigned short *)(a))
+#define REG32_PTR(a) ((volatile unsigned int *)(a))
+#define readb(a) (*(volatile unsigned char *)(a))
+#define readw(a) (*(volatile unsigned short *)(a))
+#define readl(a) (*(volatile unsigned int *)(a))
+#define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
+#define writew(v,a) (*(volatile unsigned short *)(a) = (v))
+#define writel(v,a) (*(volatile unsigned int *)(a) = (v))
+
+#endif /* __ASSEMBLER__ */
+
+/*
+ * Default Memory Layout Definitions
+ */
+
+#define L2CC_BASE_ADDR 0x30000000
+
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR 0x43F00000
+#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
+#define MAX_BASE_ADDR 0x43F04000
+#define EVTMON_BASE_ADDR 0x43F08000
+#define CLKCTL_BASE_ADDR 0x43F0C000
+#define ETB_SLOT4_BASE_ADDR 0x43F10000
+#define ETB_SLOT5_BASE_ADDR 0x43F14000
+#define ECT_CTIO_BASE_ADDR 0x43F18000
+#define I2C_BASE_ADDR 0x43F80000
+#define I2C3_BASE_ADDR 0x43F84000
+//#define OTG_BASE_ADDR 0x43F88000
+#define ATA_BASE_ADDR 0x43F8C000
+#define UART1_BASE_ADDR 0x43F90000
+#define UART2_BASE_ADDR 0x43F94000
+#define I2C2_BASE_ADDR 0x43F98000
+#define OWIRE_BASE_ADDR 0x43F9C000
+#define SSI1_BASE_ADDR 0x43FA0000
+#define CSPI1_BASE_ADDR 0x43FA4000
+#define KPP_BASE_ADDR 0x43FA8000
+#define IOMUXC_BASE_ADDR 0x43FAC000
+//#define UART4_BASE_ADDR 0x43FB0000
+//#define UART5_BASE_ADDR 0x43FB4000
+#define ECT_IP1_BASE_ADDR 0x43FB8000
+#define ECT_IP2_BASE_ADDR 0x43FBC000
+
+/*
+ * SPBA
+ */
+#define SPBA_BASE_ADDR 0x50000000
+#define MMC_SDHC1_BASE_ADDR 0x53FB4000
+#define MMC_SDHC2_BASE_ADDR 0x53FB8000
+#define ESDHC1_REG_BASE MMC_SDHC1_BASE_ADDR
+#define UART3_BASE_ADDR 0x5000C000
+#define CSPI2_BASE_ADDR 0x50010000
+#define SSI2_BASE_ADDR 0x50014000
+//#define SIM_BASE_ADDR 0x50018000
+#define ATA_DMA_BASE_ADDR 0x50020000
+#define FEC_BASE_ADDR 0x50038000
+#define SOC_FEC_BASE FEC_BASE_ADDR
+#define SPBA_CTRL_BASE_ADDR 0x5003C000
+
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR 0x53F00000
+#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
+#define CCM_BASE_ADDR 0x53F80000
+//#define FIRI_BASE_ADDR 0x53F8C000
+#define GPT1_BASE_ADDR 0x53F90000
+#define EPIT1_BASE_ADDR 0x53F94000
+#define EPIT2_BASE_ADDR 0x53F98000
+#define GPIO3_BASE_ADDR 0x53FA4000
+#define SCC_BASE 0x53FAC000
+//#define SCM_BASE 0x53FAE000
+//#define SMN_BASE 0x53FAF000
+#define RNGA_BASE_ADDR 0x53FB0000
+#define IPU_CTRL_BASE_ADDR 0x53FC0000
+#define AUDMUX_BASE 0x53FC4000
+//#define MPEG4_ENC_BASE 0x53FC8000
+#define GPIO1_BASE_ADDR 0x53FCC000
+#define GPIO2_BASE_ADDR 0x53FD0000
+#define SDMA_BASE_ADDR 0x53FD4000
+#define RTC_BASE_ADDR 0x53FD8000
+#define WDOG_BASE_ADDR 0x53FDC000
+#define PWM_BASE_ADDR 0x53FE0000
+#define RTIC_BASE_ADDR 0x53FEC000
+#define IIM_BASE_ADDR 0x53FF0000
+
+/*
+ * ROMPATCH and AVIC
+ */
+#define ROMPATCH_BASE_ADDR 0x60000000
+#define AVIC_BASE_ADDR 0x68000000
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define EXT_MEM_CTRL_BASE 0xB8000000
+#define ESDCTL_BASE 0xB8001000
+#define WEIM_BASE_ADDR 0xB8002000
+#define WEIM_CTRL_CS0 WEIM_BASE_ADDR
+#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10)
+#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20)
+#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30)
+#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40)
+#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50)
+#define M3IF_BASE 0xB8003000
+#define EMI_BASE 0xB8004000
+
+#define NFC_BASE 0xBB000000
+
+#define ROM_BASE_ADDR 0x0
+#define ROM_BASE_ADDR_VIRT 0xF0000000
+#define ROM_SI_REV_OFFSET 0x40
+
+/*
+ * Memory regions and CS
+ */
+#define IPU_MEM_BASE_ADDR 0x70000000
+#define CSD0_BASE_ADDR 0x80000000
+#define CSD1_BASE_ADDR 0x90000000
+#define CS0_BASE_ADDR 0xA0000000
+#define CS1_BASE_ADDR 0xA8000000
+#define CS2_BASE_ADDR 0xB0000000
+#define CS3_BASE_ADDR 0xB2000000
+#define CS4_BASE_ADDR 0xB4000000
+#define CS4_BASE_PSRAM 0xB5000000
+#define CS5_BASE_ADDR 0xB6000000
+
+#define INTERNAL_ROM_VA 0xF0000000
+
+/*
+ * IRQ Controller Register Definitions.
+ */
+#define AVIC_NIMASK REG32_PTR(AVIC_BASE_ADDR + (0x04))
+#define AVIC_INTTYPEH REG32_PTR(AVIC_BASE_ADDR + (0x18))
+#define AVIC_INTTYPEL REG32_PTR(AVIC_BASE_ADDR + (0x1C))
+
+/* L210 */
+#define L2CC_BASE_ADDR 0x30000000
+#define L2_CACHE_LINE_SIZE 32
+#define L2_CACHE_CTL_REG 0x100
+#define L2_CACHE_AUX_CTL_REG 0x104
+#define L2_CACHE_SYNC_REG 0x730
+#define L2_CACHE_INV_LINE_REG 0x770
+#define L2_CACHE_INV_WAY_REG 0x77C
+#define L2_CACHE_CLEAN_LINE_REG 0x7B0
+#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
+#define L2_CACHE_DBG_CTL_REG 0xF40
+
+/* CCM */
+#define CLKCTL_CCMR 0x00
+#define CLKCTL_PDR0 0x04
+#define CLKCTL_PDR1 0x08
+#define CLKCTL_PDR2 0x0C
+#define CLKCTL_PDR3 0x10
+#define CLKCTL_PDR4 0x14
+#define CLKCTL_RCSR 0x18
+#define CLKCTL_MPCTL 0x1C
+#define CLKCTL_PPCTL 0x20
+#define CLKCTL_ACMR 0x24
+#define CLKCTL_COSR 0x28
+#define CLKCTL_CGR0 0x2C
+#define CLKCTL_CGR1 0x30
+#define CLKCTL_CGR2 0x34
+#define CLKCTL_CGR3 0x38
+
+
+#define FREQ_24MHZ 24000000
+#define PLL_REF_CLK FREQ_24MHZ
+
+#define CLKMODE_AUTO 0
+#define CLKMODE_CONSUMER 1
+
+/* WEIM - CS0 */
+#define CSCRU 0x00
+#define CSCRL 0x04
+#define CSCRA 0x08
+
+#define CHIP_REV_1_0 0x0 /* PASS 1.0 */
+#define CHIP_REV_1_1 0x1 /* PASS 1.1 */
+#define CHIP_REV_2_0 0x2 /* PASS 2.0 */
+#define CHIP_LATEST CHIP_REV_1_1
+
+#define IIM_STAT_OFF 0x00
+#define IIM_STAT_BUSY (1 << 7)
+#define IIM_STAT_PRGD (1 << 1)
+#define IIM_STAT_SNSD (1 << 0)
+#define IIM_STATM_OFF 0x04
+#define IIM_ERR_OFF 0x08
+#define IIM_ERR_PRGE (1 << 7)
+#define IIM_ERR_WPE (1 << 6)
+#define IIM_ERR_OPE (1 << 5)
+#define IIM_ERR_RPE (1 << 4)
+#define IIM_ERR_WLRE (1 << 3)
+#define IIM_ERR_SNSE (1 << 2)
+#define IIM_ERR_PARITYE (1 << 1)
+#define IIM_EMASK_OFF 0x0C
+#define IIM_FCTL_OFF 0x10
+#define IIM_UA_OFF 0x14
+#define IIM_LA_OFF 0x18
+#define IIM_SDAT_OFF 0x1C
+#define IIM_PREV_OFF 0x20
+#define IIM_SREV_OFF 0x24
+#define IIM_PREG_P_OFF 0x28
+#define IIM_SCS0_OFF 0x2C
+#define IIM_SCS1_P_OFF 0x30
+#define IIM_SCS2_OFF 0x34
+#define IIM_SCS3_P_OFF 0x38
+
+#define EPIT_BASE_ADDR EPIT1_BASE_ADDR
+#define EPITCR 0x00
+#define EPITSR 0x04
+#define EPITLR 0x08
+#define EPITCMPR 0x0C
+#define EPITCNR 0x10
+
+#define GPT_BASE_ADDR GPT1_BASE_ADDR
+#define GPTCR 0x00
+#define GPTPR 0x04
+#define GPTSR 0x08
+#define GPTIR 0x0C
+#define GPTOCR1 0x10
+#define GPTOCR2 0x14
+#define GPTOCR3 0x18
+#define GPTICR1 0x1C
+#define GPTICR2 0x20
+#define GPTCNT 0x24
+
+/* ESDCTL */
+#define ESDCTL_ESDCTL0 0x00
+#define ESDCTL_ESDCFG0 0x04
+#define ESDCTL_ESDCTL1 0x08
+#define ESDCTL_ESDCFG1 0x0C
+#define ESDCTL_ESDMISC 0x10
+
+#if (PLL_REF_CLK != 24000000)
+#error Wrong PLL reference clock! The following macros will not work.
+#endif
+
+/* Assuming 24MHz input clock */
+/* PD MFD MFI MFN */
+#define MPCTL_PARAM_399 (((1-1) << 26) + ((16-1) << 16) + (8 << 10) + (5 << 0))
+#define MPCTL_PARAM_532 ((1 << 31) + ((1-1) << 26) + ((12-1) << 16) + (11 << 10) + (1 << 0))
+#define MPCTL_PARAM_665 (((1-1) << 26) + ((48-1) << 16) + (13 << 10) + (41 << 0))
+
+/* UPCTL PD MFD MFI MFN */
+#define PPCTL_PARAM_300 (((1-1) << 26) + ((4-1) << 16) + (6 << 10) + (1 << 0))
+
+#define NFC_V1_1
+
+#define NAND_REG_BASE (NFC_BASE + 0x1E00)
+#define NFC_BUFSIZE_REG_OFF (0 + 0x00)
+#define RAM_BUFFER_ADDRESS_REG_OFF (0 + 0x04)
+#define NAND_FLASH_ADD_REG_OFF (0 + 0x06)
+#define NAND_FLASH_CMD_REG_OFF (0 + 0x08)
+#define NFC_CONFIGURATION_REG_OFF (0 + 0x0A)
+#define ECC_STATUS_RESULT_REG_OFF (0 + 0x0C)
+#define ECC_RSLT_MAIN_AREA_REG_OFF (0 + 0x0E)
+#define ECC_RSLT_SPARE_AREA_REG_OFF (0 + 0x10)
+#define NF_WR_PROT_REG_OFF (0 + 0x12)
+#define NAND_FLASH_WR_PR_ST_REG_OFF (0 + 0x18)
+#define NAND_FLASH_CONFIG1_REG_OFF (0 + 0x1A)
+#define NAND_FLASH_CONFIG2_REG_OFF (0 + 0x1C)
+#define UNLOCK_START_BLK_ADD_REG_OFF (0 + 0x20)
+#define UNLOCK_END_BLK_ADD_REG_OFF (0 + 0x22)
+#define RAM_BUFFER_ADDRESS_RBA_3 0x3
+#define NFC_BUFSIZE_1KB 0x0
+#define NFC_BUFSIZE_2KB 0x1
+#define NFC_CONFIGURATION_UNLOCKED 0x2
+#define ECC_STATUS_RESULT_NO_ERR 0x0
+#define ECC_STATUS_RESULT_1BIT_ERR 0x1
+#define ECC_STATUS_RESULT_2BIT_ERR 0x2
+#define NF_WR_PROT_UNLOCK 0x4
+#define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7)
+#define NAND_FLASH_CONFIG1_RST (1 << 6)
+#define NAND_FLASH_CONFIG1_BIG (1 << 5)
+#define NAND_FLASH_CONFIG1_INT_MSK (1 << 4)
+#define NAND_FLASH_CONFIG1_ECC_EN (1 << 3)
+#define NAND_FLASH_CONFIG1_SP_EN (1 << 2)
+#define NAND_FLASH_CONFIG2_INT_DONE (1 << 15)
+#define NAND_FLASH_CONFIG2_FDO_PAGE (0 << 3)
+#define NAND_FLASH_CONFIG2_FDO_ID (2 << 3)
+#define NAND_FLASH_CONFIG2_FDO_STATUS (4 << 3)
+#define NAND_FLASH_CONFIG2_FDI_EN (1 << 2)
+#define NAND_FLASH_CONFIG2_FADD_EN (1 << 1)
+#define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0)
+#define FDO_PAGE_SPARE_VAL 0x8
+#define NAND_BUF_NUM 8
+
+#define MXC_NAND_BASE_DUMMY 0x00000000
+#define MXC_MMC_BASE_DUMMY 0x00000000
+#define NOR_FLASH_BOOT 0
+#define NAND_FLASH_BOOT 0x10000000
+#define SDRAM_NON_FLASH_BOOT 0x20000000
+#define MMC_FLASH_BOOT 0x40000000
+#define MXCBOOT_FLAG_REG (AVIC_BASE_ADDR + 0x100)
+#define MXCFIS_NOTHING 0x00000000
+#define MXCFIS_NAND 0x10000000
+#define MXCFIS_NOR 0x20000000
+#define MXCFIS_MMC 0x40000000
+#define MXCFIS_FLAG_REG (AVIC_BASE_ADDR + 0x104)
+
+#define IS_BOOTING_FROM_NAND() (readl(MXCBOOT_FLAG_REG) == NAND_FLASH_BOOT)
+#define IS_BOOTING_FROM_NOR() (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
+#define IS_BOOTING_FROM_SDRAM() (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
+#define IS_BOOTING_FROM_MMC() (readl(MXCBOOT_FLAG_REG) == MMC_FLASH_BOOT)
+
+#ifndef MXCFLASH_SELECT_NAND
+#define IS_FIS_FROM_NAND() 0
+#else
+#define IS_FIS_FROM_NAND() (readl(MXCFIS_FLAG_REG) == MXCFIS_NAND)
+#endif
+
+#ifndef MXCFLASH_SELECT_MMC
+#define IS_FIS_FROM_MMC() 0
+#else
+#define IS_FIS_FROM_MMC() (readl(MXCFIS_FLAG_REG) == MXCFIS_MMC)
+#endif
+
+#ifndef MXCFLASH_SELECT_NOR
+#define IS_FIS_FROM_NOR() 0
+#else
+#define IS_FIS_FROM_NOR() (readl(MXCFIS_FLAG_REG) == MXCFIS_NOR)
+#endif
+
+#define MXC_ASSERT_NOR_BOOT() writel(MXCFIS_NOR, MXCFIS_FLAG_REG)
+#define MXC_ASSERT_NAND_BOOT() writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
+#define MXC_ASSERT_MMC_BOOT() writel(MXCFIS_MMC, MXCFIS_FLAG_REG)
+
+/*
+ * This macro is used to get certain bit field from a number
+ */
+#define MXC_GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1))
+
+/*
+ * This macro is used to set certain bit field inside a number
+ */
+#define MXC_SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
+
+#define L1CC_ENABLED
+#define L2CC_ENABLED
+
+#define UART_WIDTH_32 /* internal UART is 32bit access only */
+
+#if !defined(__ASSEMBLER__)
+void cyg_hal_plf_serial_init(void);
+void cyg_hal_plf_serial_stop(void);
+void hal_delay_us(unsigned int usecs);
+#define HAL_DELAY_US(n) hal_delay_us(n)
+
+enum plls {
+ MCU_PLL = CCM_BASE_ADDR + CLKCTL_MPCTL,
+ PER_PLL = CCM_BASE_ADDR + CLKCTL_PPCTL,
+};
+
+enum main_clocks {
+ CPU_CLK,
+ AHB_CLK,
+ IPG_CLK,
+ IPG_PER_CLK,
+ NFC_CLK,
+ USB_CLK,
+ HSP_CLK,
+};
+
+enum peri_clocks {
+ UART1_BAUD,
+ UART2_BAUD,
+ UART3_BAUD,
+ SSI1_BAUD,
+ SSI2_BAUD,
+ CSI_BAUD,
+ MSHC_CLK,
+ ESDHC1_CLK,
+ ESDHC2_CLK,
+ ESDHC3_CLK,
+ SPDIF_CLK,
+ SPI1_CLK = CSPI1_BASE_ADDR,
+ SPI2_CLK = CSPI2_BASE_ADDR,
+};
+
+unsigned int pll_clock(enum plls pll);
+
+unsigned int get_main_clock(enum main_clocks clk);
+
+unsigned int get_peri_clock(enum peri_clocks clk);
+
+typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
+
+#endif //#if !defined(__ASSEMBLER__)
+
+#define HAL_MMU_OFF() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mcr p15, 0, r0, c7, c14, 0;" \
+ "mcr p15, 0, r0, c7, c10, 4;" /* drain the write buffer */ \
+ "mcr p15, 0, r0, c7, c5, 0;" /* invalidate I cache */ \
+ "mrc p15, 0, r0, c1, c0, 0;" /* read c1 */ \
+ "bic r0, r0, #0x7;" /* disable DCache and MMU */ \
+ "bic r0, r0, #0x1000;" /* disable ICache */ \
+ "mcr p15, 0, r0, c1, c0, 0;" /* */ \
+ "nop;" /* flush i+d-TLBs */ \
+ "nop;" /* flush i+d-TLBs */ \
+ "nop;" /* flush i+d-TLBs */ \
+ : \
+ : \
+ : "r0","memory" /* clobber list */); \
+CYG_MACRO_END
+
+#endif /* __HAL_SOC_H__ */
--- /dev/null
+#ifndef CYGONCE_HAL_VAR_INTS_H
+#define CYGONCE_HAL_VAR_INTS_H
+//==========================================================================
+//
+// hal_var_ints.h
+//
+// HAL Interrupt and clock support
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+
+#include <cyg/hal/hal_soc.h> // registers
+
+#define CYGNUM_HAL_INTERRUPT_GPIO0 0
+#define CYGNUM_HAL_INTERRUPT_GPIO1 1
+#define CYGNUM_HAL_INTERRUPT_GPIO2 2
+#define CYGNUM_HAL_INTERRUPT_GPIO3 3
+#define CYGNUM_HAL_INTERRUPT_GPIO4 4
+#define CYGNUM_HAL_INTERRUPT_GPIO5 5
+#define CYGNUM_HAL_INTERRUPT_GPIO6 6
+#define CYGNUM_HAL_INTERRUPT_GPIO7 7
+#define CYGNUM_HAL_INTERRUPT_GPIO8 8
+#define CYGNUM_HAL_INTERRUPT_GPIO9 9
+#define CYGNUM_HAL_INTERRUPT_GPIO10 10
+#define CYGNUM_HAL_INTERRUPT_GPIO 11 // Don't use directly!
+#define CYGNUM_HAL_INTERRUPT_LCD 12
+#define CYGNUM_HAL_INTERRUPT_UDC 13
+#define CYGNUM_HAL_INTERRUPT_UART1 15
+#define CYGNUM_HAL_INTERRUPT_UART2 16
+#define CYGNUM_HAL_INTERRUPT_UART3 17
+#define CYGNUM_HAL_INTERRUPT_UART4 17
+#define CYGNUM_HAL_INTERRUPT_MCP 18
+#define CYGNUM_HAL_INTERRUPT_SSP 19
+#define CYGNUM_HAL_INTERRUPT_TIMER0 26
+#define CYGNUM_HAL_INTERRUPT_TIMER1 27
+#define CYGNUM_HAL_INTERRUPT_TIMER2 28
+#define CYGNUM_HAL_INTERRUPT_TIMER3 29
+#define CYGNUM_HAL_INTERRUPT_HZ 30
+#define CYGNUM_HAL_INTERRUPT_ALARM 31
+
+// GPIO bits 31..11 can generate interrupts as well, but they all
+// end up clumped into interrupt signal #11. Using the symbols
+// below allow for detection of these separately.
+
+#define CYGNUM_HAL_INTERRUPT_GPIO11 (32+11)
+#define CYGNUM_HAL_INTERRUPT_GPIO12 (32+12)
+#define CYGNUM_HAL_INTERRUPT_GPIO13 (32+13)
+#define CYGNUM_HAL_INTERRUPT_GPIO14 (32+14)
+#define CYGNUM_HAL_INTERRUPT_GPIO15 (32+15)
+#define CYGNUM_HAL_INTERRUPT_GPIO16 (32+16)
+#define CYGNUM_HAL_INTERRUPT_GPIO17 (32+17)
+#define CYGNUM_HAL_INTERRUPT_GPIO18 (32+18)
+#define CYGNUM_HAL_INTERRUPT_GPIO19 (32+19)
+#define CYGNUM_HAL_INTERRUPT_GPIO20 (32+20)
+#define CYGNUM_HAL_INTERRUPT_GPIO21 (32+21)
+#define CYGNUM_HAL_INTERRUPT_GPIO22 (32+22)
+#define CYGNUM_HAL_INTERRUPT_GPIO23 (32+23)
+#define CYGNUM_HAL_INTERRUPT_GPIO24 (32+24)
+#define CYGNUM_HAL_INTERRUPT_GPIO25 (32+25)
+#define CYGNUM_HAL_INTERRUPT_GPIO26 (32+26)
+#define CYGNUM_HAL_INTERRUPT_GPIO27 (32+27)
+
+#define CYGNUM_HAL_INTERRUPT_NONE -1
+
+#define CYGNUM_HAL_ISR_MIN 0
+#define CYGNUM_HAL_ISR_MAX (27+32)
+
+#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1)
+
+// The vector used by the Real time clock
+#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0
+
+// The vector used by the Ethernet
+#define CYGNUM_HAL_INTERRUPT_ETH CYGNUM_HAL_INTERRUPT_GPIO0
+
+// method for reading clock interrupt latency
+#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
+externC void hal_clock_latency(cyg_uint32 *);
+# define HAL_CLOCK_LATENCY( _pvalue_ ) \
+ hal_clock_latency( (cyg_uint32 *)(_pvalue_) )
+#endif
+
+//----------------------------------------------------------------------------
+// Reset.
+#define HAL_PLATFORM_RESET() \
+ CYG_MACRO_START \
+ *(volatile unsigned short *)WDOG_BASE_ADDR |= 0x4; \
+ /* hang here forever if reset fails */ \
+ while (1){} \
+ CYG_MACRO_END
+
+// Fallback (never really used)
+#define HAL_PLATFORM_RESET_ENTRY 0x00000000
+
+#endif // CYGONCE_HAL_VAR_INTS_H
--- /dev/null
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+// plf_stub.h
+//
+// Platform header for GDB stub support.
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM
+
+#include <cyg/hal/hal_soc.h> // registers
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_intr.h> // Interrupt macros
+#include <cyg/hal/arm_stub.h> // architecture stub support
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init()
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
--- /dev/null
+#ifndef CYGONCE_VAR_IO_H
+#define CYGONCE_VAR_IO_H
+
+//=============================================================================
+//
+// var_io.h
+//
+// Variant specific IO support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/hal/plf_io.h> // Platform specifics
+
+//-----------------------------------------------------------------------------
+
+// Memory mapping details
+#ifndef CYGARC_PHYSICAL_ADDRESS
+#ifdef SRAM_BASE_ADDR
+#if (SDRAM_BASE_ADDR==SRAM_BASE_ADDR)
+#define CYGARC_PHYSICAL_ADDRESS(x) \
+ (((unsigned long)(x) & 0x00FFFFFF) + SRAM_BASE_ADDR)
+/*#elif (SDRAM_BASE_ADDR == RAM_BANK0_BASE)
+ #define CYGARC_PHYSICAL_ADDRESS(x) \
+ (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK0_BASE)*/
+#else
+#define CYGARC_PHYSICAL_ADDRESS(x) \
+ ((((unsigned long)x & 0x1FFFFFFF) > 0x0FFFFFFF)? \
+ (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK1_BASE): \
+ (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK0_BASE))
+#endif
+#else //SRAM_BASE_ADDR
+#if (SDRAM_BASE_ADDR == RAM_BANK0_BASE)
+#define CYGARC_PHYSICAL_ADDRESS(x) \
+ ((((unsigned long)x & 0x1FFFFFFF) > 0x0FFFFFFF)? \
+ (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK1_BASE): \
+ (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK0_BASE))
+#else
+#define CYGARC_PHYSICAL_ADDRESS(x) \
+ ((((unsigned long)x & 0x1FFFFFFF) > 0x0FFFFFFF)? \
+ (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK0_BASE): \
+ (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK1_BASE))
+#endif
+#endif //SRAM_BASE_ADDr
+#endif
+
+//-----------------------------------------------------------------------------
+// end of var_io.h
+#endif // CYGONCE_VAR_IO_H
--- /dev/null
+//==========================================================================
+//
+// cmds.c
+//
+// SoC [platform] specific RedBoot commands
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+#include <redboot.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/plf_mmap.h>
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/hal_cache.h>
+
+typedef unsigned long long u64;
+typedef unsigned int u32;
+typedef unsigned short u16;
+typedef unsigned char u8;
+
+#define SZ_DEC_1M 1000000
+#define PLL_PD_MAX 16 //actual pd+1
+#define PLL_MFI_MAX 15
+#define PLL_MFI_MIN 5
+#define PLL_MFD_MAX 1024 //actual mfd+1
+#define PLL_MFN_MAX 511
+#define NFC_PODF_MAX 16
+#define PRESC_MAX 4
+
+#define PLL_FREQ_MAX (2 * PLL_REF_CLK * PLL_MFI_MAX)
+#define PLL_FREQ_MIN ((2 * PLL_REF_CLK * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
+#define AHB_CLK_MAX 133333333
+#define IPG_CLK_MAX (AHB_CLK_MAX / 2)
+#define NFC_CLK_MAX 25000000
+// IPU-HSP clock is independent of the HCLK and can go up to 177MHz but requires
+// higher voltage support. For simplicity, limit it to 133MHz
+#define HSP_CLK_MAX 178000000
+
+#define ERR_WRONG_CLK -1
+#define ERR_NO_MFI -2
+#define ERR_NO_MFN -3
+#define ERR_NO_PD -4
+#define ERR_NO_PRESC -5
+#define ERR_NO_AHB_DIV -6
+
+#define ARM_DIV_OFF 16
+#define AHB_DIV_OFF 8
+#define ARM_SEL_OFF 0
+
+#define CLOCK_PATH_FIELD(arm, ahb, sel) \
+ (((arm) << ARM_DIV_OFF) + ((ahb) << AHB_DIV_OFF) + ((sel) << ARM_SEL_OFF))
+
+static unsigned int clock_auto_path[8] =
+{
+ CLOCK_PATH_FIELD(1, 3, 0), CLOCK_PATH_FIELD(1, 2, 1),
+ CLOCK_PATH_FIELD(2, 1, 1), -1,
+ CLOCK_PATH_FIELD(1, 6, 0), CLOCK_PATH_FIELD(1, 4, 1),
+ CLOCK_PATH_FIELD(2, 2, 1), -1,
+};
+
+static unsigned int clock_consumer_path[16] =
+{
+ CLOCK_PATH_FIELD(1, 4, 0), CLOCK_PATH_FIELD(1, 3, 1),
+ CLOCK_PATH_FIELD(2, 2, 0), -1,
+ -1, -1,
+ CLOCK_PATH_FIELD(4, 1, 0), CLOCK_PATH_FIELD(1, 5, 0),
+ CLOCK_PATH_FIELD(1, 8, 0), CLOCK_PATH_FIELD(1, 6, 1),
+ CLOCK_PATH_FIELD(2, 4, 0), -1,
+ -1, -1,
+ CLOCK_PATH_FIELD(4, 2, 0), -1,
+};
+
+static int hsp_div_table[3][16] =
+{
+ {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
+ {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
+ {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
+};
+
+u32 pll_clock(enum plls pll);
+u32 get_main_clock(enum main_clocks clk);
+u32 get_peri_clock(enum peri_clocks clk);
+
+static u32 pll_mfd_fixed;
+
+static void clock_setup(int argc, char *argv[]);
+static void clko(int argc, char *argv[]);
+extern unsigned int g_clock_src;
+extern unsigned int system_rev;
+
+RedBoot_cmd("clock",
+ "Setup/Display clock (max AHB=133MHz, max IPG=66.5MHz)\nSyntax:",
+ "[<ARM core clock in MHz> [:<ARM-AHB-IPG clock selection>[:<HSP selection>]]] \n\n\
+If a selection is zero or no selectin is specified, the optimal divider values \n\
+will be chosen. Examples:\n\
+ [clock] -> Show various clocks\n\
+ [clock 532] -> Core=532 AHB=133 IPG=66.5 HSP=133\n\
+ [clock 399] -> Core=399 AHB=133 IPG=66.5 HSP=133\n\
+ [clock 532:?] -> show ARM-AHB-IPG clock selections\n\
+ [clock 532:8] -> Core=532 AHB=66.5 IPG=33.25 HSP=133\n\
+ [clock 532:8:?] -> show HSP selection\n\
+ [clock 532:8:2] -> Core=532 AHB=66.5 IPG=33.25 HSP=178\n",
+ clock_setup
+ );
+
+static char consume_core_clocks[] =
+ " selection of consumer path ARM clock source\n\
+ ========ARM\t AHB \t IPG ========\n\
+ <01> - 532\t 133 \t 66.5\n\
+ <02> - 399\t 133 \t 66.5\n\
+ <03> - 266\t 133 \t 66.5\n\
+ <07> - 133\t 133 \t 66.5\n\
+ <08> - 665\t 133 \t 66.5\n\
+ <09> - 532\t 66.5\t33.25\n\
+ <10> - 399\t 66.5\t33.25\n\
+ <11> - 266\t 66.5\t33.25\n\
+ <15> - 133\t 66.5\t33.25\n\
+ Other selection value can't be configured";
+
+static char auto_core_clocks[] =
+ " selection of auto path ARM clock source\n\
+ ========ARM\t AHB \t IPG ========\n\
+ <1> - 399\t 133 \t 66.5\n\
+ <2> - 266\t 133 \t 66.5\n\
+ <3> - 133\t 133 \t 66.5\n\
+ <5> - 399\t 66.5\t33.25\n\
+ <6> - 266\t 66.5\t33.25\n\
+ <7> - 133\t 66.5\t33.25\n\
+ Other selection value can't be configured";
+
+static char consume_hsp_clocks[] =
+ " selection of consumer path hsp clock source\n\
+ ========HSP ========\n\
+ <1> - 133\n\
+ <2> - 66.5\n\
+ <3> - 178\n\
+ Other selection value can't be configured";
+
+static inline unsigned long decode_root_clocks(int mode, int pll, int index, int arm)
+{
+ unsigned int * p, max, arm_div, ahb_div = 1;
+ if(mode) {
+ p = clock_consumer_path;
+ max = sizeof(clock_consumer_path)/sizeof(clock_consumer_path[0]);
+ } else {
+ p = clock_auto_path;
+ max = sizeof(clock_auto_path)/sizeof(clock_auto_path[0]);
+ }
+ if(index >= max || p[index] == -1) return 0;
+
+ arm_div = (p[index] >> 16)&0xFF;
+ if(!arm) {
+ ahb_div = (p[index] >> 8)&0xFF;
+ }
+ if(!(p[index]&0xFF)) {
+ return pll/(arm_div*ahb_div);
+ }
+ if(mode) {
+ return (pll*3)/(arm_div*ahb_div*4);
+ }
+ return (pll*2)/(arm_div*ahb_div*3);
+}
+
+static inline unsigned long calc_pll_base_core(unsigned long core, unsigned int pdr0)
+{
+ unsigned int * p, arm_div, index;
+ if(pdr0 & CLKMODE_CONSUMER) {
+ p = clock_consumer_path;
+ index = (pdr0 >> 16) & 0xF;
+ } else {
+ p = clock_auto_path;
+ index = (pdr0 >> 9) & 7;
+ }
+
+ arm_div = (p[index] >> 16)&0xFF;
+ if(!(p[index]&0xFF)) {
+ return core*arm_div;
+ }
+ if(pdr0 & CLKMODE_CONSUMER) {
+ return (core*arm_div*4)/3;
+ }
+ return (core*arm_div*3)/2;
+}
+
+static unsigned long get_arm_ahb_clock(int arm, unsigned long pdr0)
+{
+ int mode = pdr0 & CLKMODE_CONSUMER, cfg;
+ unsigned long pll;
+ if(mode) {
+ cfg = (pdr0 >> 16) & 0xF;
+ } else {
+ cfg = (pdr0 >> 9) & 0x7;
+ }
+ pll = pll_clock(MCU_PLL);
+ return decode_root_clocks(mode, pll, cfg, arm);
+}
+
+/*!
+ * This is to calculate various parameters based on reference clock and
+ * targeted clock based on the equation:
+ * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
+ * This calculation is based on a fixed MFD value for simplicity.
+ *
+ * @param ref reference clock freq
+ * @param target targeted clock in HZ
+ * @param p_pd calculated pd value (pd value from register + 1) upon return
+ * @param p_mfi calculated actual mfi value upon return
+ * @param p_mfn calculated actual mfn value upon return
+ * @param p_mfd fixed mfd value (mfd value from register + 1) upon return
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+int calc_pll_params(u32 ref, u32 target, u32 *p_pd,
+ u32 *p_mfi, u32 *p_mfn, u32 *p_mfd)
+{
+ u64 pd, mfi, mfn, n_target = (u64)target, n_ref = (u64)ref;
+
+ pll_mfd_fixed = 24 * 16;
+
+ // Make sure targeted freq is in the valid range. Otherwise the
+ // following calculation might be wrong!!!
+ if (target < PLL_FREQ_MIN || target > PLL_FREQ_MAX) {
+ return ERR_WRONG_CLK;
+ }
+ // Use n_target and n_ref to avoid overflow
+ for (pd = 1; pd <= PLL_PD_MAX; pd++) {
+ mfi = (n_target * pd) / (2 * n_ref);
+ if (mfi > PLL_MFI_MAX) {
+ return ERR_NO_MFI;
+ } else if (mfi < 5) {
+ continue;
+ }
+ break;
+ }
+ // Now got pd and mfi already
+ mfn = (((n_target * pd) / 2 - n_ref * mfi) * pll_mfd_fixed) / n_ref;
+ // Check mfn within limit and mfn < denominator
+ if (mfn > PLL_MFN_MAX || mfn >= pll_mfd_fixed) {
+ return ERR_NO_MFN;
+ }
+
+ if (pd > PLL_PD_MAX) {
+ return ERR_NO_PD;
+ }
+ *p_pd = (u32)pd;
+ *p_mfi = (u32)mfi;
+ *p_mfn = (u32)mfn;
+ *p_mfd = pll_mfd_fixed;
+ return 0;
+}
+
+/*!
+ * This function assumes the expected core clock has to be changed by
+ * modifying the PLL. This is NOT true always but for most of the times,
+ * it is. So it assumes the PLL output freq is the same as the expected
+ * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
+ * In the latter case, it will try to increase the presc value until
+ * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
+ * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
+ * on the targeted PLL and reference input clock to the PLL. Lastly,
+ * it sets the register based on these values along with the dividers.
+ * Note 1) There is no value checking for the passed-in divider values
+ * so the caller has to make sure those values are sensible.
+ * 2) Also adjust the NFC divider such that the NFC clock doesn't
+ * exceed NFC_CLK_MAX.
+ * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
+ * 177MHz for higher voltage, this function fixes the max to 133MHz.
+ * 4) This function should not have allowed diag_printf() calls since
+ * the serial driver has been stoped. But leave then here to allow
+ * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
+ *
+ * @param ref pll input reference clock (32KHz or 26MHz)
+ * @param core_clk core clock in Hz
+ * @param ahb_div ahb divider to divide the core clock to get ahb clock
+ * (ahb_div - 1) needs to be set in the register
+ * @param ipg_div ipg divider to divide the ahb clock to get ipg clock
+ * (ipg_div - 1) needs to be set in the register
+ # @return 0 if successful; non-zero otherwise
+ */
+int configure_clock(u32 ref, u32 core_clk, u32 ahb_clk, u32 pdr0)
+{
+ u32 pll, pd, mfi, mfn, mfd, brmo = 0, mpctl0;
+ u32 pdr4, nfc_div;
+ int ret, i;
+
+ pll = calc_pll_base_core(core_clk, pdr0);
+
+ if((pll < PLL_FREQ_MIN ) || (pll > PLL_FREQ_MAX)) {
+ return ERR_WRONG_CLK;
+ }
+ // get nfc_div - make sure optimal NFC clock but less than NFC_CLK_MAX
+ for (nfc_div = 1; nfc_div <= NFC_PODF_MAX; nfc_div++) {
+ if ((ahb_clk/ nfc_div) <= NFC_CLK_MAX) {
+ break;
+ }
+ }
+
+ // pll is now the targeted pll output. Use it along with ref input clock
+ // to get pd, mfi, mfn, mfd
+ if ((ret = calc_pll_params(ref, pll, &pd, &mfi, &mfn, &mfd)) != 0) {
+ diag_printf("can't find pll(%d) parameters: %d\n", pll, ret);
+ return ret;
+ }
+#ifdef CMD_CLOCK_DEBUG
+ diag_printf("ref=%d, pll=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
+ ref, pll, pd, mfi, mfn, mfd);
+#endif
+
+ // blindly increase divider first to avoid too fast ahbclk and ipgclk
+ // in case the core clock increases too much
+ pdr4 = readl(CCM_BASE_ADDR + CLKCTL_PDR4);
+ pdr4 &= ~0xF0000000;
+ // increase the dividers. should work even when core clock is 832 (26*2*16)MHz
+ // which is unlikely true.
+ pdr4 |= (nfc_div -1) << 28;
+
+ // update PLL register
+ if ((mfd >= (10 * mfn)) || ((10 * mfn) >= (9 * mfd)))
+ brmo = 1;
+
+ mpctl0 = readl(CCM_BASE_ADDR + CLKCTL_MPCTL);
+ mpctl0 = (mpctl0 & 0x4000C000) |
+ (brmo << 31) |
+ ((pd - 1) << 26) |
+ ((mfd - 1) << 16) |
+ (mfi << 10) |
+ mfn;
+ writel(mpctl0, CCM_BASE_ADDR + CLKCTL_MPCTL);
+ writel(pdr0, CCM_BASE_ADDR + CLKCTL_PDR0);
+ writel(pdr4, CCM_BASE_ADDR + CLKCTL_PDR4);
+ // add some delay for new values to take effect
+ for (i = 0; i < 10000; i++);
+ return 0;
+}
+
+static int clock_setup_polling(u32 * params, u32 * ahb_clk, u32 * hsp_clk, u32 * pdr0)
+{
+ u32 ahb_div, hsp_div;
+ diag_printf("data[0]=%d, data[1]=%d, data[2]=%d\n", params[0], params[1], params[2]);
+ if(!params[1]) {
+ goto polling;
+ } else {
+ if((*pdr0) & CLKMODE_CONSUMER) {
+ if((params[1] > 16) || (clock_consumer_path[params[1] - 1] == -1)) {
+ diag_printf("Error: Invalid arm source selection in consumer path\n");
+ return -1;
+ }
+ ahb_div = (clock_consumer_path[params[1] - 1] >> AHB_DIV_OFF) & 0xFF;
+ } else {
+ if((params[1] > 8) || (clock_auto_path[params[1] -1 ] == -1)) {
+ diag_printf("Error: Invalid arm source selection in auto path\n");
+ return -1;
+ }
+ ahb_div = (clock_auto_path[params[1] - 1] >> AHB_DIV_OFF) & 0xFF;
+ }
+ }
+ if(((*pdr0) & CLKMODE_CONSUMER)){
+ if(!params[2]) params[2] = ((*pdr0 >> 20) & 0x3) + 1;
+ if((params[2] > 3) || (hsp_div_table[params[2] - 1][params[1] -1] == -1)) {
+ diag_printf("Error: current hsp source selection[%d] in current core path is invalid\n", params[2]);
+ return -1;
+ }
+ }
+
+ if (params[0] < (PLL_FREQ_MIN / PRESC_MAX) || params[0] > PLL_FREQ_MAX) {
+ diag_printf("Targeted core clock should be within [%d - %d]\n",
+ PLL_FREQ_MIN / PRESC_MAX, PLL_FREQ_MAX);
+ return -1;
+ }
+
+ if ((params[0] / ahb_div) > AHB_CLK_MAX) {
+ diag_printf("Can't make AHB=%d since max=%d\n",
+ params[0] / ahb_div, AHB_CLK_MAX);
+ return -1;
+ }
+
+//output:
+ *ahb_clk = params[0] / ahb_div;
+ if((*pdr0) & CLKMODE_CONSUMER) {
+ *hsp_clk = params[0] /hsp_div_table[params[2] - 1][params[1] -1];
+ *pdr0 &= ~((0x3<<20) | (0xF<<16));
+ *pdr0 |= ((params[2] - 1)<< 20) | (params[1] -1) << 16;
+ } else {
+ *hsp_clk = *ahb_clk;
+ *pdr0 &= ~(0x7 << 9);
+ *pdr0 |= (params[1] -1) << 9;
+ }
+ return 0;
+polling:
+ return -1;
+ //goto output;
+}
+
+static void clock_setup(int argc,char *argv[])
+{
+ int ret;
+ u32 pdr0 = readl(CCM_BASE_ADDR + CLKCTL_PDR0);
+ u32 i, data[3], temp, ahb_clk, hsp_clk;
+
+ if (system_rev & (0x2 << 4)) /* consumer path only in TO2.0 */
+ pdr0 |= 0x1;
+
+ if (argc == 1)
+ goto print_clock;
+
+ memset(data, 0, sizeof(u32)*3);
+ for (i = 0; i < 3; i++) {
+ if (!parse_num(*(&argv[1]), (unsigned long *)&temp, &argv[1], ":")) {
+ if(*argv[1] == '?') {
+ switch(i) {
+ case 1:
+ diag_printf("ARM-AHB-IPG clock selections:\n");
+ if(pdr0 & CLKMODE_CONSUMER) {
+ diag_printf("%s\n", consume_core_clocks);
+ } else {
+ diag_printf("%s\n", auto_core_clocks);
+ }
+ return;
+ case 2:
+ diag_printf("HSP clock selections:\n");
+ if(pdr0 & CLKMODE_CONSUMER) {
+ diag_printf("%s\n", consume_hsp_clocks);
+ } else {
+ diag_printf("In auto path, HSP clock always is same as AHB clock.\n");
+ }
+ return;
+ }
+ }
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ data[i] = temp;
+ }
+
+ data[0] = data[0] * SZ_DEC_1M;
+
+ if(clock_setup_polling(data, &ahb_clk, &hsp_clk, &pdr0)) return;
+ diag_printf("Trying to set core=%d ahb=%d ipg=%d hsp=%d...\n",
+ data[0], ahb_clk, ahb_clk/2, hsp_clk);
+ diag_printf("Current pdr0=%x\n", pdr0);
+ // stop the serial to be ready to adjust the clock
+ hal_delay_us(100000);
+ cyg_hal_plf_serial_stop();
+ // adjust the clock
+ ret = configure_clock(PLL_REF_CLK, data[0], ahb_clk, pdr0);
+ // restart the serial driver
+ cyg_hal_plf_serial_init();
+ hal_delay_us(100000);
+
+ if (ret != 0) {
+ diag_printf("Failed to setup clock: %d\n", ret);
+ return;
+ }
+ diag_printf("\n<<<New clock setting>>>\n");
+ // Now printing clocks
+print_clock:
+ diag_printf("\nMPLL\t\tPPLL\n");
+ diag_printf("========================================\n");
+ diag_printf("%-16d%-16d\n\n", pll_clock(MCU_PLL), pll_clock(PER_PLL));
+ diag_printf("CPU\t\tAHB\t\tIPG\t\tIPG_PER\n");
+ diag_printf("========================================================\n");
+ diag_printf("%-16d%-16d%-16d%-16d\n\n",
+ get_main_clock(CPU_CLK),
+ get_main_clock(AHB_CLK),
+ get_main_clock(IPG_CLK),
+ get_main_clock(IPG_PER_CLK));
+
+ diag_printf("NFC\t\tUSB\t\tIPU-HSP\n");
+ diag_printf("========================================\n");
+ diag_printf("%-16d%-16d%-16d\n\n",
+ get_main_clock(NFC_CLK),
+ get_main_clock(USB_CLK),
+ get_main_clock(HSP_CLK));
+
+ diag_printf("UART1-3\t\tSSI1\t\tSSI2\t\tCSI\n");
+ diag_printf("===========================================");
+ diag_printf("=============\n");
+
+ diag_printf("%-16d%-16d%-16d%-16d\n\n",
+ get_peri_clock(UART1_BAUD),
+ get_peri_clock(SSI1_BAUD),
+ get_peri_clock(SSI2_BAUD),
+ get_peri_clock(CSI_BAUD));
+
+ diag_printf("MSHC\t\tESDHC1\t\tESDHC2\t\tESDHC3\n");
+ diag_printf("===========================================");
+ diag_printf("=============\n");
+
+ diag_printf("%-16d%-16d%-16d%-16d\n\n",
+ get_peri_clock(MSHC_CLK),
+ get_peri_clock(ESDHC1_CLK),
+ get_peri_clock(ESDHC2_CLK),
+ get_peri_clock(ESDHC3_CLK));
+
+ diag_printf("SPDIF\t\t\n");
+ diag_printf("===========================================");
+ diag_printf("=============\n");
+
+ diag_printf("%-16d\n\n",
+ get_peri_clock(SPDIF_CLK));
+ diag_printf("IPG_PERCLK as baud clock for: UART1-5, I2C, SIM, OWIRE");
+ if (((readl(EPIT1_BASE_ADDR) >> 24) & 0x3) == 0x2) {
+ diag_printf(", EPIT");
+ }
+ if (((readl(GPT1_BASE_ADDR) >> 6) & 0x7) == 0x2) {
+ diag_printf("GPT,");
+ }
+ if (((readl(PWM_BASE_ADDR) >> 16) & 0x3) == 0x2) {
+ diag_printf("PWM,");
+ }
+ diag_printf("\n");
+}
+
+/*!
+ * This function returns the PLL output value in Hz based on pll.
+ */
+u32 pll_clock(enum plls pll)
+{
+ u64 mfi, mfn, mfd, pdf, ref_clk, pll_out, sign;
+ u64 reg = readl(pll);
+
+ pdf = (reg >> 26) & 0xF;
+ mfd = (reg >> 16) & 0x3FF;
+ mfi = (reg >> 10) & 0xF;
+ mfi = (mfi <= 5) ? 5: mfi;
+ mfn = reg & 0x3FF;
+ sign = (mfn < 512) ? 0: 1;
+ mfn = (mfn < 512) ? mfn: (1024 - mfn);
+
+ ref_clk = g_clock_src;
+
+ if (sign == 0) {
+ pll_out = (2 * ref_clk * mfi + ((2 * ref_clk * mfn) / (mfd + 1))) /
+ (pdf + 1);
+ } else {
+ pll_out = (2 * ref_clk * mfi - ((2 * ref_clk * mfn) / (mfd + 1))) /
+ (pdf + 1);
+ }
+
+ return (u32)pll_out;
+}
+
+/*!
+ * This function returns the main clock value in Hz.
+ */
+u32 get_main_clock(enum main_clocks clk)
+{
+ u32 ipg_pdf, nfc_pdf, hsp_podf;
+ u32 pll, ret_val = 0, usb_prdf, usb_podf, pdf;
+
+ u32 reg = readl(CCM_BASE_ADDR + CLKCTL_PDR0);
+ u32 reg4 = readl(CCM_BASE_ADDR + CLKCTL_PDR4);
+
+ if (system_rev & (0x2 << 4)) /* consumer path only in TO2.0 */
+ reg |= 0x1;
+
+ switch (clk) {
+ case CPU_CLK:
+ ret_val = get_arm_ahb_clock(1, reg);
+ break;
+ case AHB_CLK:
+ ret_val = get_arm_ahb_clock(0, reg);
+ break;
+ case HSP_CLK:
+ if( reg & CLKMODE_CONSUMER) {
+ hsp_podf = (reg >> 20) & 0x3;
+ pll = get_arm_ahb_clock(1, reg);
+ hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
+ if(hsp_podf > 0 ) {
+ ret_val = pll / hsp_podf;
+ } else {
+ diag_printf("mismatch HSP with ARM clock setting\n");
+ ret_val = 0;
+ }
+ } else {
+ ret_val = get_arm_ahb_clock(0, reg);
+ }
+ break;
+ case IPG_CLK:
+ ret_val = get_arm_ahb_clock(0, reg) / 2;
+ break;
+ case IPG_PER_CLK:
+ if(reg & 0x04000000) {
+ ipg_pdf = (reg >> 12) & 0x7;
+ ret_val = get_arm_ahb_clock(0, reg)/ (ipg_pdf + 1);
+ } else {
+ pdf = (((reg4 >> 16) & 0x7) + 1);
+ ipg_pdf = (((reg4 >> 19) & 0x7) + 1);
+ ret_val = get_arm_ahb_clock(1, reg)/(pdf * ipg_pdf);
+ }
+ break;
+ case NFC_CLK:
+ nfc_pdf = (reg4 >> 28) & 0xF;
+ pll = get_arm_ahb_clock(0, reg);
+ /* AHB/nfc_pdf */
+ ret_val = pll / (nfc_pdf + 1);
+ break;
+ case USB_CLK:
+ usb_prdf = (reg4 >> 25) & 0x7;
+ usb_podf = (reg4 >> 22) & 0x7;
+ if(reg4 & 0x200) {
+ pll = get_arm_ahb_clock(1, reg);
+ } else {
+ pll = pll_clock(PER_PLL);
+ }
+ ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1));
+ break;
+ default:
+ diag_printf("Unknown clock: %d\n", clk);
+ break;
+ }
+
+ return ret_val;
+}
+
+/*!
+ * This function returns the peripheral clock value in Hz.
+ */
+u32 get_peri_clock(enum peri_clocks clk)
+{
+ u32 ret_val = 0, pdf, pre_pdf, clk_sel;
+ u32 mpdr2 = readl(CCM_BASE_ADDR + CLKCTL_PDR2);
+ u32 mpdr3 = readl(CCM_BASE_ADDR + CLKCTL_PDR3);
+ u32 mpdr4 = readl(CCM_BASE_ADDR + CLKCTL_PDR4);
+
+ switch (clk) {
+ case UART1_BAUD:
+ case UART2_BAUD:
+ case UART3_BAUD:
+ clk_sel = mpdr3 & (1 << 14);
+ pre_pdf = (mpdr4 >> 13) & 0x7;
+ pdf = (mpdr4 >> 10) & 0x7;
+ ret_val = ((clk_sel != 0) ? get_main_clock(CPU_CLK) :
+ pll_clock(PER_PLL)) / ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case SSI1_BAUD:
+ pre_pdf = (mpdr2 >> 24) & 0x7;
+ pdf = mpdr2 & 0x3F;
+ clk_sel = mpdr2 & ( 1 << 6);
+ ret_val = ((clk_sel != 0) ? get_main_clock(CPU_CLK) :
+ pll_clock(PER_PLL)) / ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case SSI2_BAUD:
+ pre_pdf = (mpdr2 >> 27) & 0x7;
+ pdf = (mpdr2 >> 8)& 0x3F;
+ clk_sel = mpdr2 & ( 1 << 6);
+ ret_val = ((clk_sel != 0) ? get_main_clock(CPU_CLK) :
+ pll_clock(PER_PLL)) / ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case CSI_BAUD:
+ clk_sel = mpdr2 & (1 << 7);
+ pre_pdf = (mpdr2 >> 16) & 0x7;
+ pdf = (mpdr2 >> 19) & 0x7;
+ ret_val = ((clk_sel != 0) ? get_main_clock(CPU_CLK) :
+ pll_clock(PER_PLL)) / ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case MSHC_CLK:
+
+ pre_pdf = readl(CCM_BASE_ADDR + CLKCTL_PDR1);
+ clk_sel = (pre_pdf & 0x80);
+ pdf = (pre_pdf >> 22) & 0x3F;
+ pre_pdf = (pre_pdf >> 28) & 0x7;
+ ret_val = ((clk_sel != 0)? get_main_clock(CPU_CLK) :
+ pll_clock(PER_PLL)) / ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case ESDHC1_CLK:
+ clk_sel = mpdr3 & 0x40;
+ pre_pdf = mpdr3&0x7;
+ pdf = (mpdr3>>3)&0x7;
+ ret_val = ((clk_sel != 0)? get_main_clock(CPU_CLK) :
+ pll_clock(PER_PLL)) / ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case ESDHC2_CLK:
+ clk_sel = mpdr3 & 0x40;
+ pre_pdf = (mpdr3 >> 8)&0x7;
+ pdf = (mpdr3 >> 11)&0x7;
+ ret_val = ((clk_sel != 0)? get_main_clock(CPU_CLK) :
+ pll_clock(PER_PLL)) / ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case ESDHC3_CLK:
+ clk_sel = mpdr3 & 0x40;
+ pre_pdf = (mpdr3 >> 16)&0x7;
+ pdf = (mpdr3 >> 19)&0x7;
+ ret_val = ((clk_sel != 0)? get_main_clock(CPU_CLK) :
+ pll_clock(PER_PLL)) / ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case SPDIF_CLK:
+ clk_sel = mpdr3 & 0x400000;
+ pre_pdf = (mpdr3 >> 29)&0x7;
+ pdf = (mpdr3 >> 23)&0x3F;
+ ret_val = ((clk_sel != 0)? get_main_clock(CPU_CLK) :
+ pll_clock(PER_PLL)) / ((pre_pdf + 1) * (pdf + 1));
+ break;
+ default:
+ diag_printf("%s(): This clock: %d not supported yet \n",
+ __FUNCTION__, clk);
+ break;
+ }
+ return ret_val;
+}
+
+RedBoot_cmd("clko",
+ "Select clock source for CLKO (J11 on the CPU daughter card)",
+ " Default is 1/32 of ARM core\n\
+ <00> - display current clko selection \n\
+ <01> - async 32K clock \n\
+ <02> - input 24Mhz clock for pll ref(PLL_REF_CLK)\n\
+ <03> - input 24.576Mhz osc audio clk(AUDIO_REF_CLK) \n\
+ <04> - 1/32 mpll_divgen output 2x(MPLL_OUTPUT_2) \n\
+ <05> - 1/32 ppll_divgen output 0.75x(PPLL_OUTPUT_1) \n\
+ <06> - 1/32 mpll_divgen output 1x(MPLL_OUTPUT_1) \n\
+ <07> - 1/32 ppll output clock(PPLL) \n\
+ <08> - 1/32 arm clock(ARM_CLK) \n\
+ <09> - hclk always(AHB_CLK) \n\
+ <10> - ipg clock always(IPG_CLK) \n\
+ <11> - synched per clock root(PER_CLK) \n\
+ <12> - usb clock(USB_CLK) \n\
+ <13> - esdhc1 clock root (ESDHC_CLK) \n\
+ <14> - ssi clock root (SSI_CLK) \n\
+ <15> - mlb memory clock (MLB_CLK) \n\
+ <16> - csi clock root (ESDHC_CLK) \n\
+ <17> - spdif clock root (ESDHC_CLK) \n\
+ <18> - uart clock root (ESDHC_CLK) \n\
+ <19> - asrc autio input clock(ASRC_CLK) \n\
+ <20> - dptc reference clock 1 from ref cir(DPTC_REF_CLK)",
+ clko
+ );
+
+static u8* clko_name[] ={
+ "NULL",
+ "async 32K clock",
+ "input 24Mhz clock for pll ref(PLL_REF_CLK)",
+ "input 24.576Mhz osc audio clk(AUDIO_REF_CLK)",
+ "1/32 mpll_divgen output 2x(MPLL_OUTPUT_2)",
+ "1/32 ppll_divgen output 0.75x(PPLL_OUTPUT_1)",
+ "1/32 mpll_divgen output 1x(MPLL_OUTPUT_1)",
+ "1/32 ppll output clock(PPLL)",
+ "1/32 arm clock(ARM_CLK)",
+ "hclk always(AHB_CLK)",
+ "ipg clock always(IPG_CLK)",
+ "synched per clock root(PER_CLK)",
+ "usb clock(USB_CLK)",
+ "esdhc1 clock root (ESDHC_CLK)",
+ "ssi clock root (SSI_CLK)" ,
+ "mlb memory clock (MLB_CLK)" ,
+ "mpll lock flag" ,
+ "csi clock root (ESDHC_CLK)" ,
+ "spdif clock root (ESDHC_CLK)",
+ "uart clock root (ESDHC_CLK)" ,
+ "asrc autio input clock(ASRC_CLK)",
+ "dptc reference clock 1 from ref cir(DPTC_REF_CLK)",
+};
+
+#define CLKO_MAX_INDEX (sizeof(clko_name) / sizeof(u8*))
+
+static void clko(int argc,char *argv[])
+{
+ u32 action = 0, cosr;
+
+ if (!scan_opts(argc, argv, 1, 0, 0, (void*) &action,
+ OPTION_ARG_TYPE_NUM, "action"))
+ return;
+
+ if (action >= (CLKO_MAX_INDEX -1)) {
+ diag_printf("%d is not supported\n\n", action);
+ return;
+ }
+
+ cosr = readl(CCM_BASE_ADDR + CLKCTL_COSR);
+ if (action != 0) {
+ cosr = (cosr & 0xFFFF0020) + ((action<16)?(action - 1):action);
+ if (action > 3 && action < 9) {
+ cosr |= 0x6C40; // make it divided by 32
+ }
+ writel(cosr, CCM_BASE_ADDR + CLKCTL_COSR);
+ diag_printf("Set clko to ");
+ }
+
+ cosr = readl(CCM_BASE_ADDR + CLKCTL_COSR);
+ if((cosr&0x1F) > 0x14) {
+ diag_printf("reserved selections\n");
+ } else {
+ diag_printf("%s\n", clko_name[(cosr&0x1F)+1]);
+ }
+ diag_printf("COSR register[0x%x] = 0x%x\n",
+ (CCM_BASE_ADDR + CLKCTL_COSR), cosr);
+}
+
+#ifdef L2CC_ENABLED
+/*
+ * This command is added for some simple testing only. It turns on/off
+ * L2 cache regardless of L1 cache state. The side effect of this is
+ * when doing any flash operations such as "fis init", the L2
+ * will be turned back on along with L1 caches even though it is off
+ * by using this command.
+ */
+RedBoot_cmd("L2",
+ "L2 cache",
+ "[ON | OFF]",
+ do_L2_caches
+ );
+
+void do_L2_caches(int argc, char *argv[])
+{
+ u32 oldints;
+ int L2cache_on=0;
+
+ if (argc == 2) {
+ if (strcasecmp(argv[1], "on") == 0) {
+ HAL_DISABLE_INTERRUPTS(oldints);
+ HAL_ENABLE_L2();
+ HAL_RESTORE_INTERRUPTS(oldints);
+ } else if (strcasecmp(argv[1], "off") == 0) {
+ HAL_DISABLE_INTERRUPTS(oldints);
+ HAL_CLEAN_INVALIDATE_L2();
+ HAL_DISABLE_L2();
+ HAL_RESTORE_INTERRUPTS(oldints);
+ } else {
+ diag_printf("Invalid L2 cache mode: %s\n", argv[1]);
+ }
+ } else {
+ HAL_L2CACHE_IS_ENABLED(L2cache_on);
+ diag_printf("L2 cache: %s\n", L2cache_on?"On":"Off");
+ }
+}
+#endif //L2CC_ENABLED
+
+#define IIM_ERR_SHIFT 8
+#define POLL_FUSE_PRGD (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT))
+#define POLL_FUSE_SNSD (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT))
+
+static void fuse_op_start(void)
+{
+ /* Do not generate interrupt */
+ writel(0, IIM_BASE_ADDR + IIM_STATM_OFF);
+ // clear the status bits and error bits
+ writel(0x3, IIM_BASE_ADDR + IIM_STAT_OFF);
+ writel(0xFE, IIM_BASE_ADDR + IIM_ERR_OFF);
+}
+
+/*
+ * The action should be either:
+ * POLL_FUSE_PRGD
+ * or:
+ * POLL_FUSE_SNSD
+ */
+static int poll_fuse_op_done(int action)
+{
+
+ u32 status, error;
+
+ if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) {
+ diag_printf("%s(%d) invalid operation\n", __FUNCTION__, action);
+ return -1;
+ }
+
+ /* Poll busy bit till it is NOT set */
+ while ((readl(IIM_BASE_ADDR + IIM_STAT_OFF) & IIM_STAT_BUSY) != 0 ) {
+ }
+
+ /* Test for successful write */
+ status = readl(IIM_BASE_ADDR + IIM_STAT_OFF);
+ error = readl(IIM_BASE_ADDR + IIM_ERR_OFF);
+
+ if ((status & action) != 0 && (error & (action >> IIM_ERR_SHIFT)) == 0) {
+ if (error) {
+ diag_printf("Even though the operation seems successful...\n");
+ diag_printf("There are some error(s) at addr=0x%x: 0x%x\n",
+ (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+ }
+ return 0;
+ }
+ diag_printf("%s(%d) failed\n", __FUNCTION__, action);
+ diag_printf("status address=0x%x, value=0x%x\n",
+ (IIM_BASE_ADDR + IIM_STAT_OFF), status);
+ diag_printf("There are some error(s) at addr=0x%x: 0x%x\n",
+ (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+ return -1;
+}
+
+static void sense_fuse(int bank, int row, int bit)
+{
+ int addr, addr_l, addr_h, reg_addr;
+
+ fuse_op_start();
+
+ addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+ /* Set IIM Program Upper Address */
+ addr_h = (addr >> 8) & 0x000000FF;
+ /* Set IIM Program Lower Address */
+ addr_l = (addr & 0x000000FF);
+
+#ifdef IIM_FUSE_DEBUG
+ diag_printf("%s: addr_h=0x%x, addr_l=0x%x\n",
+ __FUNCTION__, addr_h, addr_l);
+#endif
+ writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
+ writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
+ /* Start sensing */
+ writel(0x8, IIM_BASE_ADDR + IIM_FCTL_OFF);
+ if (poll_fuse_op_done(POLL_FUSE_SNSD) != 0) {
+ diag_printf("%s(bank: %d, row: %d, bit: %d failed\n",
+ __FUNCTION__, bank, row, bit);
+ }
+ reg_addr = IIM_BASE_ADDR + IIM_SDAT_OFF;
+ diag_printf("fuses at (bank:%d, row:%d) = 0x%x\n", bank, row, readl(reg_addr));
+}
+
+void do_fuse_read(int argc, char *argv[])
+{
+ int bank, row;
+
+ if (argc == 1) {
+ diag_printf("Useage: fuse_read <bank> <row>\n");
+ return;
+ } else if (argc == 3) {
+ if (!parse_num(*(&argv[1]), (unsigned long *)&bank, &argv[1], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(*(&argv[2]), (unsigned long *)&row, &argv[2], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+
+ diag_printf("Read fuse at bank:%d row:%d\n", bank, row);
+ sense_fuse(bank, row, 0);
+
+ } else {
+ diag_printf("Passing in wrong arguments: %d\n", argc);
+ diag_printf("Useage: fuse_read <bank> <row>\n");
+ }
+}
+
+/* Blow fuses based on the bank, row and bit positions (all 0-based)
+*/
+static int fuse_blow(int bank,int row,int bit)
+{
+ int addr, addr_l, addr_h, ret = -1;
+
+ fuse_op_start();
+
+ /* Disable IIM Program Protect */
+ writel(0xAA, IIM_BASE_ADDR + IIM_PREG_P_OFF);
+
+ addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+ /* Set IIM Program Upper Address */
+ addr_h = (addr >> 8) & 0x000000FF;
+ /* Set IIM Program Lower Address */
+ addr_l = (addr & 0x000000FF);
+
+#ifdef IIM_FUSE_DEBUG
+ diag_printf("blowing addr_h=0x%x, addr_l=0x%x\n", addr_h, addr_l);
+#endif
+
+ writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
+ writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
+ /* Start Programming */
+ writel(0x31, IIM_BASE_ADDR + IIM_FCTL_OFF);
+ if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) {
+ ret = 0;
+ }
+
+ /* Enable IIM Program Protect */
+ writel(0x0, IIM_BASE_ADDR + IIM_PREG_P_OFF);
+ return ret;
+}
+
+/*
+ * This command is added for burning IIM fuses
+ */
+RedBoot_cmd("fuse_read",
+ "read some fuses",
+ "<bank> <row>",
+ do_fuse_read
+ );
+
+RedBoot_cmd("fuse_blow",
+ "blow some fuses",
+ "<bank> <row> <value>",
+ do_fuse_blow
+ );
+
+#define INIT_STRING "12345678"
+static char ready_to_blow[] = INIT_STRING;
+
+void quick_itoa(u32 num, char *a)
+{
+ int i, j, k;
+ for (i = 0; i <= 7; i++) {
+ j = (num >> (4 * i)) & 0xF;
+ k = (j < 10) ? '0' : ('a' - 0xa);
+ a[i] = j + k;
+ }
+}
+
+void do_fuse_blow(int argc, char *argv[])
+{
+ int bank, row, value, i;
+
+ if (argc == 1) {
+ diag_printf("It is too dangeous for you to use this command.\n");
+ return;
+ } else if (argc == 2) {
+ if (strcasecmp(argv[1], "nandboot") == 0) {
+ quick_itoa(readl(EPIT_BASE_ADDR + EPITCNR), ready_to_blow);
+ diag_printf("%s\n", ready_to_blow);
+ }
+ return;
+ } else if (argc == 3) {
+ if (strcasecmp(argv[1], "nandboot") == 0 &&
+ strcasecmp(argv[2], ready_to_blow) == 0) {
+#if defined(CYGPKG_HAL_ARM_MXC91131) || defined(CYGPKG_HAL_ARM_MX21) || defined(CYGPKG_HAL_ARM_MX27) || defined(CYGPKG_HAL_ARM_MX31) ||defined(CYGPKG_HAL_ARM_MX35)
+ diag_printf("No need to blow any fuses for NAND boot on this platform\n\n");
+#else
+ diag_printf("Ready to burn NAND boot fuses\n");
+ if (fuse_blow(0, 16, 1) != 0 || fuse_blow(0, 16, 7) != 0) {
+ diag_printf("NAND BOOT fuse blown failed miserably ...\n");
+ } else {
+ diag_printf("NAND BOOT fuse blown successfully ...\n");
+ }
+ } else {
+ diag_printf("Not ready: %s, %s\n", argv[1], argv[2]);
+#endif
+ }
+ } else if (argc == 4) {
+ if (!parse_num(*(&argv[1]), (unsigned long *)&bank, &argv[1], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(*(&argv[2]), (unsigned long *)&row, &argv[2], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(*(&argv[3]), (unsigned long *)&value, &argv[3], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+
+ diag_printf("Blowing fuse at bank:%d row:%d value:%d\n",
+ bank, row, value);
+ for (i = 0; i < 8; i++) {
+ if (((value >> i) & 0x1) == 0) {
+ continue;
+ }
+ if (fuse_blow(bank, row, i) != 0) {
+ diag_printf("fuse_blow(bank: %d, row: %d, bit: %d failed\n",
+ bank, row, i);
+ } else {
+ diag_printf("fuse_blow(bank: %d, row: %d, bit: %d successful\n",
+ bank, row, i);
+ }
+ }
+ sense_fuse(bank, row, 0);
+
+ } else {
+ diag_printf("Passing in wrong arguments: %d\n", argc);
+ }
+ /* Reset to default string */
+ strcpy(ready_to_blow, INIT_STRING);;
+}
+
+/* precondition: m>0 and n>0. Let g=gcd(m,n). */
+int gcd(int m, int n)
+{
+ int t;
+ while(m > 0) {
+ if(n > m) {t = m; m = n; n = t;} /* swap */
+ m -= n;
+ }
+ return n;
+}
+
+#define CLOCK_SRC_DETECT_MS 100
+#define CLOCK_SRC_DETECT_MARGIN 500000
+void mxc_show_clk_input(void)
+{
+
+ u32 c1, c2, diff, ipg_real, ipg_clk = get_main_clock(IPG_CLK);
+ u32 reg = readl(CCM_BASE_ADDR + CLKCTL_PDR0);
+
+ if (system_rev & (0x2 << 4)) /* consumer path only in TO2.0 */
+ reg |= 0x1;
+
+ diag_printf("Chip is working in %s mode\n", (reg&CLKMODE_CONSUMER)?"consumer":"auto");
+
+ // enable GPT with IPG clock input
+ writel(0x241, GPT_BASE_ADDR + GPTCR);
+ // prescaler = 1
+ writel(0, GPT_BASE_ADDR + GPTPR);
+
+ c1 = readl(GPT_BASE_ADDR + GPTCNT);
+ // use 32KHz input clock to get the delay
+ hal_delay_us(CLOCK_SRC_DETECT_MS * 1000);
+ c2 = readl(GPT_BASE_ADDR + GPTCNT);
+ diff = (c2 > c1) ? (c2 - c1) : (0xFFFFFFFF - c1 + c2);
+ ipg_real = diff * 10;
+
+ if (ipg_real > (ipg_clk + CLOCK_SRC_DETECT_MARGIN)) {
+ goto warning;
+ } else if (ipg_real < (ipg_clk - CLOCK_SRC_DETECT_MARGIN)) {
+ goto warning;
+ }
+ return;
+warning:
+ diag_printf("Error: Actural ipg clock input is %d Hz\n", ipg_real);
+ diag_printf(" ipg_clk=%d difference=%d\n\n",
+ ipg_clk, (ipg_clk > ipg_real) ? (ipg_clk-ipg_real) : (ipg_real-ipg_clk));
+ hal_delay_us(2000000);
+}
+
+RedBoot_init(mxc_show_clk_input, RedBoot_INIT_LAST);
--- /dev/null
+/*=============================================================================
+//
+// hal_diag.c
+//
+// HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_arch.h> // basic machine info
+#include <cyg/hal/hal_intr.h> // interrupt macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_if.h> // Calling interface definitions
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/drv_api.h> // cyg_drv_interrupt_acknowledge
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+
+/*
+ * UART Control Register 0 Bit Fields.
+ */
+#define EUartUCR1_ADEN (1 << 15) // Auto dectect interrupt
+#define EUartUCR1_ADBR (1 << 14) // Auto detect baud rate
+#define EUartUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable
+#define EUartUCR1_IDEN (1 << 12) // Idle condition interrupt
+#define EUartUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable
+#define EUartUCR1_RDMAEN (1 << 8) // Recv ready DMA enable
+#define EUartUCR1_IREN (1 << 7) // Infrared interface enable
+#define EUartUCR1_TXMPTYEN (1 << 6) // Transimitter empty interrupt enable
+#define EUartUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable
+#define EUartUCR1_SNDBRK (1 << 4) // Send break
+#define EUartUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable
+#define EUartUCR1_DOZE (1 << 1) // Doze
+#define EUartUCR1_UARTEN (1 << 0) // UART enabled
+#define EUartUCR2_ESCI (1 << 15) // Escape seq interrupt enable
+#define EUartUCR2_IRTS (1 << 14) // Ignore RTS pin
+#define EUartUCR2_CTSC (1 << 13) // CTS pin control
+#define EUartUCR2_CTS (1 << 12) // Clear to send
+#define EUartUCR2_ESCEN (1 << 11) // Escape enable
+#define EUartUCR2_PREN (1 << 8) // Parity enable
+#define EUartUCR2_PROE (1 << 7) // Parity odd/even
+#define EUartUCR2_STPB (1 << 6) // Stop
+#define EUartUCR2_WS (1 << 5) // Word size
+#define EUartUCR2_RTSEN (1 << 4) // Request to send interrupt enable
+#define EUartUCR2_ATEN (1 << 3) // Aging timer enable
+#define EUartUCR2_TXEN (1 << 2) // Transmitter enabled
+#define EUartUCR2_RXEN (1 << 1) // Receiver enabled
+#define EUartUCR2_SRST_ (1 << 0) // SW reset
+#define EUartUCR3_PARERREN (1 << 12) // Parity enable
+#define EUartUCR3_FRAERREN (1 << 11) // Frame error interrupt enable
+#define EUartUCR3_ADNIMP (1 << 7) // Autobaud detection not improved
+#define EUartUCR3_RXDSEN (1 << 6) // Receive status interrupt enable
+#define EUartUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable
+#define EUartUCR3_AWAKEN (1 << 4) // Async wake interrupt enable
+#define EUartUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected
+#define EUartUCR3_INVT (1 << 1) // Inverted Infrared transmission
+#define EUartUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable
+#define EUartUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars)
+#define EUartUCR4_INVR (1 << 9) // Inverted infrared reception
+#define EUartUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable
+#define EUartUCR4_WKEN (1 << 7) // Wake interrupt enable
+#define EUartUCR4_IRSC (1 << 5) // IR special case
+#define EUartUCR4_LPBYP (1 << 4) // Low power bypass
+#define EUartUCR4_TCEN (1 << 3) // Transmit complete interrupt enable
+#define EUartUCR4_BKEN (1 << 2) // Break condition interrupt enable
+#define EUartUCR4_OREN (1 << 1) // Receiver overrun interrupt enable
+#define EUartUCR4_DREN (1 << 0) // Recv data ready interrupt enable
+#define EUartUFCR_RXTL_SHF 0 // Receiver trigger level shift
+#define EUartUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div 1)
+#define EUartUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div 2)
+#define EUartUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3)
+#define EUartUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4)
+#define EUartUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5)
+#define EUartUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6)
+#define EUartUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7)
+#define EUartUFCR_TXTL_SHF 10 // Transmitter trigger level shift
+#define EUartUSR1_PARITYERR (1 << 15) // Parity error interrupt flag
+#define EUartUSR1_RTSS (1 << 14) // RTS pin status
+#define EUartUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag
+#define EUartUSR1_RTSD (1 << 12) // RTS delta
+#define EUartUSR1_ESCF (1 << 11) // Escape seq interrupt flag
+#define EUartUSR1_FRAMERR (1 << 10) // Frame error interrupt flag
+#define EUartUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag
+#define EUartUSR1_AGTIM (1 << 8) // Aging timeout interrupt status
+#define EUartUSR1_RXDS (1 << 6) // Receiver idle interrupt flag
+#define EUartUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag
+#define EUartUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag
+#define EUartUSR2_ADET (1 << 15) // Auto baud rate detect complete
+#define EUartUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty
+#define EUartUSR2_IDLE (1 << 12) // Idle condition
+#define EUartUSR2_ACST (1 << 11) // Autobaud counter stopped
+#define EUartUSR2_IRINT (1 << 8) // Serial infrared interrupt flag
+#define EUartUSR2_WAKE (1 << 7) // Wake
+#define EUartUSR2_RTSF (1 << 4) // RTS edge interrupt flag
+#define EUartUSR2_TXDC (1 << 3) // Transmitter complete
+#define EUartUSR2_BRCD (1 << 2) // Break condition
+#define EUartUSR2_ORE (1 << 1) // Overrun error
+#define EUartUSR2_RDR (1 << 0) // Recv data ready
+#define EUartUTS_FRCPERR (1 << 13) // Force parity error
+#define EUartUTS_LOOP (1 << 12) // Loop tx and rx
+#define EUartUTS_TXEMPTY (1 << 6) // TxFIFO empty
+#define EUartUTS_RXEMPTY (1 << 5) // RxFIFO empty
+#define EUartUTS_TXFULL (1 << 4) // TxFIFO full
+#define EUartUTS_RXFULL (1 << 3) // RxFIFO full
+#define EUartUTS_SOFTRST (1 << 0) // Software reset
+
+#define EUartUFCR_RFDIV EUartUFCR_RFDIV_2
+//#define EUartUFCR_RFDIV EUartUFCR_RFDIV_4
+
+#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_2)
+#define MXC_UART_REFFREQ (get_peri_clock(UART1_BAUD) / 2)
+#endif
+
+#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_4)
+#define MXC_UART_REFFREQ (get_peri_clock(UART1_BAUD) / 4)
+#endif
+
+#if 0
+void
+cyg_hal_plf_comms_init(void)
+{
+ static int initialized = 0;
+
+ if (initialized)
+ return;
+
+ initialized = 1;
+
+ cyg_hal_plf_serial_init();
+}
+#endif
+
+//=============================================================================
+// MXC Serial Port (UARTx) for Debug
+//=============================================================================
+#ifdef UART_WIDTH_32
+struct mxc_serial {
+ volatile cyg_uint32 urxd[16];
+ volatile cyg_uint32 utxd[16];
+ volatile cyg_uint32 ucr1;
+ volatile cyg_uint32 ucr2;
+ volatile cyg_uint32 ucr3;
+ volatile cyg_uint32 ucr4;
+ volatile cyg_uint32 ufcr;
+ volatile cyg_uint32 usr1;
+ volatile cyg_uint32 usr2;
+ volatile cyg_uint32 uesc;
+ volatile cyg_uint32 utim;
+ volatile cyg_uint32 ubir;
+ volatile cyg_uint32 ubmr;
+ volatile cyg_uint32 ubrc;
+ volatile cyg_uint32 onems;
+ volatile cyg_uint32 uts;
+};
+#else
+struct mxc_serial {
+ volatile cyg_uint16 urxd[1];
+ volatile cyg_uint16 resv0[31];
+
+ volatile cyg_uint16 utxd[1];
+ volatile cyg_uint16 resv1[31];
+ volatile cyg_uint16 ucr1;
+ volatile cyg_uint16 resv2;
+ volatile cyg_uint16 ucr2;
+ volatile cyg_uint16 resv3;
+ volatile cyg_uint16 ucr3;
+ volatile cyg_uint16 resv4;
+ volatile cyg_uint16 ucr4;
+ volatile cyg_uint16 resv5;
+ volatile cyg_uint16 ufcr;
+ volatile cyg_uint16 resv6;
+ volatile cyg_uint16 usr1;
+ volatile cyg_uint16 resv7;
+ volatile cyg_uint16 usr2;
+ volatile cyg_uint16 resv8;
+ volatile cyg_uint16 uesc;
+ volatile cyg_uint16 resv9;
+ volatile cyg_uint16 utim;
+ volatile cyg_uint16 resv10;
+ volatile cyg_uint16 ubir;
+ volatile cyg_uint16 resv11;
+ volatile cyg_uint16 ubmr;
+ volatile cyg_uint16 resv12;
+ volatile cyg_uint16 ubrc;
+ volatile cyg_uint16 resv13;
+ volatile cyg_uint16 onems;
+ volatile cyg_uint16 resv14;
+ volatile cyg_uint16 uts;
+ volatile cyg_uint16 resv15;
+};
+#endif
+
+typedef struct {
+ volatile struct mxc_serial* base;
+ cyg_int32 msec_timeout;
+ int isr_vector;
+ int baud_rate;
+} channel_data_t;
+
+static channel_data_t channels[] = {
+#if CYGHWR_HAL_ARM_SOC_UART1 != 0
+ {(volatile struct mxc_serial*)UART1_BASE_ADDR, 1000,
+ CYGNUM_HAL_INTERRUPT_UART1, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#endif
+#if CYGHWR_HAL_ARM_SOC_UART2 != 0
+ {(volatile struct mxc_serial*)UART2_BASE_ADDR, 1000,
+ CYGNUM_HAL_INTERRUPT_UART2, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#endif
+#if CYGHWR_HAL_ARM_SOC_UART3 != 0
+ {(volatile struct mxc_serial*)UART3_BASE_ADDR, 1000,
+ CYGNUM_HAL_INTERRUPT_UART3, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#endif
+};
+
+/*---------------------------------------------------------------------------*/
+
+static void init_serial_channel(channel_data_t* __ch_data)
+{
+ volatile struct mxc_serial* base = __ch_data->base;
+
+ /* Wait for UART to finish transmitting */
+ while (!(base->uts & EUartUTS_TXEMPTY));
+
+ /* Disable UART */
+ base->ucr1 &= ~EUartUCR1_UARTEN;
+
+ /* Set to default POR state */
+ base->ucr1 = 0x00000000;
+ base->ucr2 = 0x00000000;
+
+ while (!(base->ucr2 & EUartUCR2_SRST_));
+
+ base->ucr3 = 0x00000704;
+ base->ucr4 = 0x00008000;
+ base->ufcr = 0x00000801;
+ base->uesc = 0x0000002B;
+ base->utim = 0x00000000;
+ base->ubir = 0x00000000;
+ base->ubmr = 0x00000000;
+ base->onems = 0x00000000;
+ base->uts = 0x00000000;
+
+ /* Configure FIFOs */
+ base->ufcr = (1 << EUartUFCR_RXTL_SHF) | EUartUFCR_RFDIV
+ | (2 << EUartUFCR_TXTL_SHF);
+
+ /* Setup One MS timer */
+ base->onems = (MXC_UART_REFFREQ / 1000);
+
+ /* Set to 8N1 */
+ base->ucr2 &= ~EUartUCR2_PREN;
+ base->ucr2 |= EUartUCR2_WS;
+ base->ucr2 &= ~EUartUCR2_STPB;
+
+ /* Ignore RTS */
+ base->ucr2 |= EUartUCR2_IRTS;
+
+ /* Enable UART */
+ base->ucr1 |= EUartUCR1_UARTEN;
+
+ /* Enable FIFOs */
+ base->ucr2 |= EUartUCR2_SRST_ | EUartUCR2_RXEN | EUartUCR2_TXEN;
+
+ /* Clear status flags */
+ base->usr2 |= EUartUSR2_ADET |
+ EUartUSR2_IDLE |
+ EUartUSR2_IRINT |
+ EUartUSR2_WAKE |
+ EUartUSR2_RTSF |
+ EUartUSR2_BRCD |
+ EUartUSR2_ORE |
+ EUartUSR2_RDR;
+
+ /* Clear status flags */
+ base->usr1 |= EUartUSR1_PARITYERR |
+ EUartUSR1_RTSD |
+ EUartUSR1_ESCF |
+ EUartUSR1_FRAMERR |
+ EUartUSR1_AIRINT |
+ EUartUSR1_AWAKE;
+
+ /* Set the numerator value minus one of the BRM ratio */
+ base->ubir = (__ch_data->baud_rate / 100) - 1;
+
+ /* Set the denominator value minus one of the BRM ratio */
+ base->ubmr = ((MXC_UART_REFFREQ / 1600) - 1);
+
+}
+
+static void stop_serial_channel(channel_data_t* __ch_data)
+{
+ volatile struct mxc_serial* base = __ch_data->base;
+
+ /* Wait for UART to finish transmitting */
+ while (!(base->uts & EUartUTS_TXEMPTY));
+
+ /* Disable UART */
+ base->ucr1 &= ~EUartUCR1_UARTEN;
+}
+
+//#define debug_uart_log_buf
+#ifdef debug_uart_log_buf
+#define DIAG_BUFSIZE 2048
+static char __log_buf[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+
+void cyg_hal_plf_serial_putc(void *__ch_data, char c)
+{
+ volatile struct mxc_serial* base = ((channel_data_t*)__ch_data)->base;
+
+#ifdef debug_uart_log_buf
+ __log_buf[diag_bp++] = c;
+#endif
+
+ CYGARC_HAL_SAVE_GP();
+
+ // Wait for Tx FIFO not full
+ while (base->uts & EUartUTS_TXFULL)
+ ;
+ base->utxd[0] = c;
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool cyg_hal_plf_serial_getc_nonblock(void* __ch_data,
+ cyg_uint8* ch)
+{
+ volatile struct mxc_serial* base = ((channel_data_t*)__ch_data)->base;
+
+ // If receive fifo is empty, return false
+ if (base->uts & EUartUTS_RXEMPTY)
+ return false;
+
+ *ch = (char)base->urxd[0];
+
+ return true;
+}
+
+cyg_uint8 cyg_hal_plf_serial_getc(void* __ch_data)
+{
+ cyg_uint8 ch;
+ CYGARC_HAL_SAVE_GP();
+
+ while (!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
+
+ CYGARC_HAL_RESTORE_GP();
+ return ch;
+}
+
+static void cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while(__len-- > 0)
+ cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static void cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while (__len-- > 0)
+ *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool cyg_hal_plf_serial_getc_timeout(void* __ch_data,
+ cyg_uint8* ch)
+{
+ int delay_count;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_bool res;
+ CYGARC_HAL_SAVE_GP();
+
+ delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+
+ for(;;) {
+ res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
+ if (res || 0 == delay_count--)
+ break;
+
+ CYGACC_CALL_IF_DELAY_US(100);
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static int cyg_hal_plf_serial_control(void *__ch_data,
+ __comm_control_cmd_t __func, ...)
+{
+ static int irq_state = 0;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ int ret = -1;
+ va_list ap;
+
+ CYGARC_HAL_SAVE_GP();
+ va_start(ap, __func);
+
+ switch (__func) {
+ case __COMMCTL_GETBAUD:
+ ret = chan->baud_rate;
+ break;
+ case __COMMCTL_SETBAUD:
+ chan->baud_rate = va_arg(ap, cyg_int32);
+ // Should we verify this value here?
+ init_serial_channel(chan);
+ ret = 0;
+ break;
+ case __COMMCTL_IRQ_ENABLE:
+ irq_state = 1;
+
+ chan->base->ucr1 |= EUartUCR1_RRDYEN;
+
+ HAL_INTERRUPT_UNMASK(chan->isr_vector);
+ break;
+ case __COMMCTL_IRQ_DISABLE:
+ ret = irq_state;
+ irq_state = 0;
+
+ chan->base->ucr1 &= ~EUartUCR1_RRDYEN;
+
+ HAL_INTERRUPT_MASK(chan->isr_vector);
+ break;
+ case __COMMCTL_DBG_ISR_VECTOR:
+ ret = chan->isr_vector;
+ break;
+ case __COMMCTL_SET_TIMEOUT:
+ ret = chan->msec_timeout;
+ chan->msec_timeout = va_arg(ap, cyg_uint32);
+ break;
+ default:
+ break;
+ }
+ va_end(ap);
+ CYGARC_HAL_RESTORE_GP();
+ return ret;
+}
+
+static int cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
+ CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+ int res = 0;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ char c;
+
+ CYGARC_HAL_SAVE_GP();
+
+ cyg_drv_interrupt_acknowledge(chan->isr_vector);
+
+ *__ctrlc = 0;
+ if (!(chan->base->uts & EUartUTS_RXEMPTY)) {
+ c = (char)chan->base->urxd[0];
+
+ if (cyg_hal_is_break( &c , 1 ))
+ *__ctrlc = 1;
+
+ res = CYG_ISR_HANDLED;
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+void cyg_hal_plf_serial_init(void)
+{
+ hal_virtual_comm_table_t* comm;
+ int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ int i;
+ static int jjj = 0;
+
+ // Init channels
+#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
+ for (i = 0; i < NUMOF(channels); i++) {
+ init_serial_channel(&channels[i]);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(i+2);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+ if (jjj == 0) {
+ cyg_hal_plf_serial_putc(&channels[i], '+');
+ jjj++;
+ }
+ cyg_hal_plf_serial_putc(&channels[i], '+');
+ }
+
+ // Restore original console
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+void cyg_hal_plf_serial_stop(void)
+{
+ int i;
+
+ // Init channels
+#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
+ for (i = 0; i < NUMOF(channels); i++) {
+ stop_serial_channel(&channels[i]);
+ }
+}
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
+
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 2)
+#define __BASE ((void*)UART1_BASE_ADDR)
+#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART1
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 3)
+#define __BASE ((void*)UART2_BASE_ADDR)
+#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART2
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 4)
+#define __BASE ((void*)UART3_BASE_ADDR)
+#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART3
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 5)
+#define __BASE ((void*)UART4_BASE_ADDR)
+#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART4
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 6)
+#define __BASE ((void*)UART5_BASE_ADDR)
+#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART5
+#endif
+
+#ifdef __BASE
+
+#ifdef CYGSEM_HAL_ROM_MONITOR
+#define CYG_HAL_STARTUP_ROM
+#define CYG_HAL_STARTUP_ROMRAM
+#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#endif
+
+#if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define HAL_DIAG_USES_HARDWARE
+#elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
+#define HAL_DIAG_USES_HARDWARE
+#elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+#define HAL_DIAG_USES_HARDWARE
+#endif
+
+static channel_data_t channel = {
+ (volatile struct mxc_serial*)__BASE, 0, CYGHWR_HAL_GDB_PORT_VECTOR
+};
+
+#ifdef HAL_DIAG_USES_HARDWARE
+
+void hal_diag_init(void)
+{
+ static int init = 0;
+ char *msg = "\n\rARM eCos\n\r";
+ cyg_uint8 lcr;
+
+ if (init++) return;
+
+ init_serial_channel(&channel);
+
+ while (*msg) hal_diag_write_char(*msg++);
+}
+
+#ifdef DEBUG_DIAG
+#ifndef CYG_HAL_STARTUP_ROM
+#define DIAG_BUFSIZE 2048
+static char diag_buffer[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+#endif
+
+void hal_diag_write_char(char c)
+{
+#ifdef DEBUG_DIAG
+#ifndef CYG_HAL_STARTUP_ROM
+ diag_buffer[diag_bp++] = c;
+ if (diag_bp == sizeof(diag_buffer)) diag_bp = 0;
+#endif
+#endif
+ cyg_hal_plf_serial_putc(&channel, c);
+}
+
+void hal_diag_read_char(char *c)
+{
+ *c = cyg_hal_plf_serial_getc(&channel);
+}
+
+#else // not HAL_DIAG_USES_HARDWARE - it uses GDB protocol
+
+void hal_diag_read_char(char *c)
+{
+ *c = cyg_hal_plf_serial_getc(&channel);
+}
+
+void hal_diag_write_char(char c)
+{
+ static char line[100];
+ static int pos = 0;
+
+ // FIXME: Some LED blinking might be nice right here.
+
+ // No need to send CRs
+ if( c == '\r' ) return;
+
+ line[pos++] = c;
+
+ if (c == '\n' || pos == sizeof(line)) {
+ CYG_INTERRUPT_STATE old;
+
+ // Disable interrupts. This prevents GDB trying to interrupt us
+ // while we are in the middle of sending a packet. The serial
+ // receive interrupt will be seen when we re-enable interrupts
+ // later.
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+#else
+ HAL_DISABLE_INTERRUPTS(old);
+#endif
+
+ while (1) {
+ static char hex[] = "0123456789ABCDEF";
+ cyg_uint8 csum = 0;
+ int i;
+#ifndef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ char c1;
+#endif
+ cyg_hal_plf_serial_putc(&channel, '$');
+ cyg_hal_plf_serial_putc(&channel, 'O');
+ csum += 'O';
+ for(i = 0; i < pos; i++) {
+ char ch = line[i];
+ char h = hex[(ch>>4)&0xF];
+ char l = hex[ch&0xF];
+ cyg_hal_plf_serial_putc(&channel, h);
+ cyg_hal_plf_serial_putc(&channel, l);
+ csum += h;
+ csum += l;
+ }
+ cyg_hal_plf_serial_putc(&channel, '#');
+ cyg_hal_plf_serial_putc(&channel, hex[(csum>>4)&0xF]);
+ cyg_hal_plf_serial_putc(&channel, hex[csum&0xF]);
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+
+ break; // regardless
+
+#else // not CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT Ie. usually...
+
+ // Wait for the ACK character '+' from GDB here and handle
+ // receiving a ^C instead. This is the reason for this clause
+ // being a loop.
+ c1 = cyg_hal_plf_serial_getc(&channel);
+
+ if( c1 == '+' )
+ break; // a good acknowledge
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ cyg_drv_interrupt_acknowledge(CYGHWR_HAL_GDB_PORT_VECTOR);
+ if( c1 == 3 ) {
+ // Ctrl-C: breakpoint.
+ cyg_hal_gdb_interrupt(
+ (target_register_t)__builtin_return_address(0) );
+ break;
+ }
+#endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+
+#endif // ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ // otherwise, loop round again
+ }
+
+ pos = 0;
+
+ // And re-enable interrupts
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+#else
+ HAL_RESTORE_INTERRUPTS(old);
+#endif
+
+ }
+}
+#endif
+
+#endif // __BASE
+
+#endif // !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
+/* End of hal_diag.c */
--- /dev/null
+//==========================================================================
+//
+// soc_misc.c
+//
+// HAL misc board support code
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#include <redboot.h>
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_misc.h> // Size constants
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h> // Interrupt names
+#include <cyg/hal/hal_cache.h> // Cache control
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/hal_mm.h> // MMap table definitions
+
+#include <cyg/infra/diag.h> // diag_printf
+
+// Most initialization has already been done before we get here.
+// All we do here is set up the interrupt environment.
+// FIXME: some of the stuff in hal_platform_setup could be moved here.
+
+externC void plf_hardware_init(void);
+
+#define IIM_PROD_REV_SH 3
+#define IIM_PROD_REV_LEN 5
+#define IIM_SREV_REV_SH 4
+#define IIM_SREV_REV_LEN 4
+
+#define PROD_SIGNATURE_MX35 0x1
+
+#define PROD_SIGNATURE_SUPPORTED_1 PROD_SIGNATURE_MX35
+
+#define CHIP_VERSION_NONE 0xFFFFFFFF // invalid product ID
+#define CHIP_VERSION_UNKNOWN 0xDEADBEEF // invalid chip rev
+
+#define PART_NUMBER_OFFSET (12)
+#define MAJOR_NUMBER_OFFSET (4)
+#define MINOR_NUMBER_OFFSET (0)
+
+/*
+ * System_rev will have the following format
+ * 31-12 = part # (0x31, 0x32, 0x27, 0x91131, 0x91321, 0x35, etc)
+ * 11-8 = unused
+ * 7-4 = major (1.y)
+ * 3-0 = minor (x.0)
+ */
+unsigned int system_rev = CHIP_REV_1_0;
+static int find_correct_chip;
+extern char HAL_PLATFORM_EXTRA[55];
+
+/*
+ * This functions reads the IIM module and returns the system revision number.
+ * It returns the IIM silicon revision reg value if valid product rev is found.
+ . Otherwise, it returns -1.
+ */
+static int read_system_rev(void)
+{
+ int val;
+
+ system_rev = 0x35 << PART_NUMBER_OFFSET; /* For MX35 Platform*/
+
+ /* get silicon id */
+ val = readl(ROM_BASE_ADDR_VIRT + ROM_SI_REV_OFFSET) & 0xF;
+ system_rev |= val << 4;
+
+ /* Now trying to retrieve the silicon rev from IIM's SREV register */
+ return val;
+}
+
+extern nfc_setup_func_t *nfc_setup;
+unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz,
+ unsigned int is_mlc, unsigned int num_of_chips);
+void hal_hardware_init(void)
+{
+ int ver = read_system_rev();
+ find_correct_chip = ver;
+
+ if (ver != CHIP_VERSION_NONE) {
+ /* use the version from the ROM code. */
+ if (ver == 0x1) {
+ HAL_PLATFORM_EXTRA[5] = '1';
+ HAL_PLATFORM_EXTRA[7] = '0';
+ } else if (ver == 0x2) {
+ HAL_PLATFORM_EXTRA[5] = '2';
+ HAL_PLATFORM_EXTRA[7] = '0';
+ } else {
+ find_correct_chip = CHIP_VERSION_UNKNOWN;
+ }
+ }
+
+ // Mask all interrupts
+ writel(0xFFFFFFFF, AVIC_NIMASK);
+
+ // Make all interrupts do IRQ and not FIQ
+ // FIXME: Change this if you use FIQs.
+ writel(0, AVIC_INTTYPEH);
+ writel(0, AVIC_INTTYPEL);
+
+ // Enable caches
+ HAL_ICACHE_ENABLE();
+ HAL_DCACHE_ENABLE();
+
+ // enable EPIT and start it with 32KHz input clock
+ writel(0x00010000, EPIT_BASE_ADDR + EPITCR);
+
+ // make sure reset is complete
+ while ((readl(EPIT_BASE_ADDR + EPITCR) & 0x10000) != 0) {
+ }
+
+ writel(0x030E0002, EPIT_BASE_ADDR + EPITCR);
+ writel(0x030E0003, EPIT_BASE_ADDR + EPITCR);
+
+ writel(0, EPIT_BASE_ADDR + EPITCMPR); // always compare with 0
+
+ if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
+ // increase the WDOG timeout value to the max
+ writew(readw(WDOG_BASE_ADDR) | 0xFF00, WDOG_BASE_ADDR);
+ }
+
+ // Perform any platform specific initializations
+ plf_hardware_init();
+
+ // Set up eCos/ROM interfaces
+ hal_if_init();
+
+#if CYGHWR_DEVS_FLASH_MXC_NAND
+ nfc_setup = (nfc_setup_func_t*)mxc_nfc_soc_setup;
+#endif
+}
+
+// -------------------------------------------------------------------------
+void hal_clock_initialize(cyg_uint32 period)
+{
+}
+
+// This routine is called during a clock interrupt.
+
+// Define this if you want to ensure that the clock is perfect (i.e. does
+// not drift). One reason to leave it turned off is that it costs some
+// us per system clock interrupt for this maintenance.
+#undef COMPENSATE_FOR_CLOCK_DRIFT
+
+void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
+{
+}
+
+// Read the current value of the clock, returning the number of hardware
+// "ticks" that have occurred (i.e. how far away the current value is from
+// the start)
+
+// Note: The "contract" for this function is that the value is the number
+// of hardware clocks that have happened since the last interrupt (i.e.
+// when it was reset). This value is used to measure interrupt latencies.
+// However, since the hardware counter runs freely, this routine computes
+// the difference between the current clock period and the number of hardware
+// ticks left before the next timer interrupt.
+void hal_clock_read(cyg_uint32 *pvalue)
+{
+}
+
+// This is to cope with the test read used by tm_basic with
+// CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY defined; we read the count ASAP
+// in the ISR, *before* resetting the clock. Which returns 1tick +
+// latency if we just use plain hal_clock_read().
+void hal_clock_latency(cyg_uint32 *pvalue)
+{
+}
+
+unsigned int hal_timer_count(void)
+{
+ return (0xFFFFFFFF - readl(EPIT_BASE_ADDR + EPITCNR));
+}
+
+#define WDT_MAGIC_1 0x5555
+#define WDT_MAGIC_2 0xAAAA
+#define MXC_WDT_WSR 0x2
+
+unsigned int i2c_base_addr[] = {
+ I2C_BASE_ADDR,
+ I2C2_BASE_ADDR,
+ I2C3_BASE_ADDR
+};
+unsigned int i2c_num = 3;
+
+static unsigned int led_on = 0;
+//
+// Delay for some number of micro-seconds
+//
+void hal_delay_us(unsigned int usecs)
+{
+ /*
+ * This causes overflow.
+ * unsigned int delayCount = (usecs * 32000) / 1000000;
+ * So use the following one instead
+ */
+ unsigned int delayCount = (usecs*4 + 124) / 125;
+
+ if (delayCount == 0) {
+ return;
+ }
+
+ // issue the service sequence instructions
+ if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
+ writew(WDT_MAGIC_1, WDOG_BASE_ADDR + MXC_WDT_WSR);
+ writew(WDT_MAGIC_2, WDOG_BASE_ADDR + MXC_WDT_WSR);
+ }
+
+ writel(0x01, EPIT_BASE_ADDR + EPITSR); // clear the compare status bit
+
+ writel(delayCount, EPIT_BASE_ADDR + EPITLR);
+
+ while ((0x1 & readl(EPIT_BASE_ADDR + EPITSR)) == 0); // return until compare bit is set
+ if ((++led_on % 2000) == 0)
+ BOARD_DEBUG_LED(0);
+}
+
+// -------------------------------------------------------------------------
+
+// This routine is called to respond to a hardware interrupt (IRQ). It
+// should interrogate the hardware and return the IRQ vector number.
+int hal_IRQ_handler(void)
+{
+#ifdef HAL_EXTENDED_IRQ_HANDLER
+ cyg_uint32 index;
+
+ // Use platform specific IRQ handler, if defined
+ // Note: this macro should do a 'return' with the appropriate
+ // interrupt number if such an extended interrupt exists. The
+ // assumption is that the line after the macro starts 'normal' processing.
+ HAL_EXTENDED_IRQ_HANDLER(index);
+#endif
+
+ return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
+}
+
+//
+// Interrupt control
+//
+
+void hal_interrupt_mask(int vector)
+{
+// diag_printf("6hal_interrupt_mask(vector=%d) \n", vector);
+#ifdef HAL_EXTENDED_INTERRUPT_MASK
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_MASK(vector);
+#endif
+}
+
+void hal_interrupt_unmask(int vector)
+{
+// diag_printf("7hal_interrupt_unmask(vector=%d) \n", vector);
+
+#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_UNMASK(vector);
+#endif
+}
+
+void hal_interrupt_acknowledge(int vector)
+{
+
+// diag_printf("8hal_interrupt_acknowledge(vector=%d) \n", vector);
+#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector);
+#endif
+}
+
+void hal_interrupt_configure(int vector, int level, int up)
+{
+
+#ifdef HAL_EXTENDED_INTERRUPT_CONFIGURE
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_CONFIGURE(vector, level, up);
+#endif
+}
+
+void hal_interrupt_set_level(int vector, int level)
+{
+
+#ifdef HAL_EXTENDED_INTERRUPT_SET_LEVEL
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_SET_LEVEL(vector, level);
+#endif
+
+ // Interrupt priorities are not configurable.
+}
+
+unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz, unsigned int is_mlc, unsigned int num_of_chips)
+{
+ unsigned int tmp ;
+ if (is_mlc) {
+ tmp = readw(NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF) | (1 << 8);
+ } else {
+ tmp = readw(NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF) & (~(1 << 8));
+ }
+
+ writew(tmp, NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF);
+ tmp = readl(CCM_BASE_ADDR + CLKCTL_RCSR);
+ if (io_sz == 16) {
+ tmp |= (1 << 14);
+ } else {
+ tmp &= (~(1 << 14));
+ }
+
+ tmp &= ~(3<<8);
+ switch(pg_sz = 2048){
+ case 2048:
+ tmp |= (1<<8);
+ break;
+ case 4096:
+ tmp |= (1<<9);
+ break;
+ }
+
+ writel(tmp, CCM_BASE_ADDR + CLKCTL_RCSR);
+ diag_printf("NAND: RCSR=%x\n", tmp);
+ return 0x10;
+}
+
+static void check_reset_source(void)
+{
+ unsigned int source=readl(CCM_BASE_ADDR + CLKCTL_RCSR);
+ switch(source & 0xF) {
+ case 0x0:
+ diag_printf("hardware reset by POR\n");
+ break;
+ case 0x2:
+ diag_printf("hardware reset by JTAG\n");
+ break;
+ case 0x4:
+ diag_printf("hardware reset by qualified external reset\n");
+ break;
+ case 0x8:
+ diag_printf("hardware reset by watchdog\n");
+ break;
+ default:
+ diag_printf("hardware reset by unknow source\n");
+ }
+}
+
+RedBoot_init(check_reset_source, RedBoot_INIT_LAST);
+
+static void check_correct_chip(void)
+{
+ if (find_correct_chip == CHIP_VERSION_UNKNOWN) {
+ diag_printf("Unrecognized chip version: 0x%x!!!\n", read_system_rev());
+ diag_printf("Assuming chip version=0x%x\n", system_rev);
+ } else if (find_correct_chip == CHIP_VERSION_NONE) {
+ diag_printf("Unrecognized chip: 0x%x!!!\n", readl(IIM_BASE_ADDR + IIM_PREV_OFF));
+ }
+}
+
+RedBoot_init(check_correct_chip, RedBoot_INIT_LAST);
--- /dev/null
+# ====================================================================
+#
+# hal_arm_board.cdl
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+
+cdl_package CYGPKG_HAL_ARM_MX37_3STACK {
+ display "Freescale board"
+ parent CYGPKG_HAL_ARM_MX37
+ hardware
+ include_dir cyg/hal
+ define_header hal_arm_board.h
+ description "
+ This HAL platform package provides generic
+ support for the Freescale MX37 3-Stack Board."
+
+ compile board_misc.c board_diag.c
+ implements CYGINT_HAL_DEBUG_GDB_STUBS
+ implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+ implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+
+ #implements CYGHWR_HAL_ARM_DUART_UARTB
+ implements CYGHWR_HAL_ARM_SOC_UART1
+ #implements CYGHWR_HAL_ARM_SOC_UART2
+ #implements CYGHWR_HAL_ARM_SOC_UART3
+
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_soc.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_board.h>"
+ puts $::cdl_header "#define HAL_PLATFORM_CPU \"Freescale i.MX37 based\""
+ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"MX37 3-Stack\""
+ puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 1575"
+ puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK board_program_new_stack"
+ }
+
+ cdl_component CYG_HAL_STARTUP {
+ display "Startup type"
+ flavor data
+ default_value {"ROM"}
+ legal_values {"RAM" "ROM" "ROMRAM"}
+ no_define
+ define -file system.h CYG_HAL_STARTUP
+ description "
+ When targetting the eval board it is possible to build
+ the system for either RAM bootstrap or ROM bootstrap(s). Select
+ 'ram' when building programs to load into RAM using eCos GDB
+ stubs. Select 'rom' when building a stand-alone application
+ which will be put into ROM, or for the special case of
+ building the eCos GDB stubs themselves. Using ROMRAM will allow
+ the program to exist in ROM, but be copied to RAM during startup."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_DUART_UARTA {
+ display "ST16552 UARTA available as diagnostic/debug channel"
+ description "
+ The board has a ST16552 DUART chip. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_DUART_UARTB {
+ display "ST16552 UARTB available as diagnostic/debug channel"
+ description "
+ The board has a ST16552 DUART chip. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ display "Diagnostic serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the console port.
+ Note: this should match the value chosen for the GDB port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ display "GDB serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the GDB port.
+ Note: this should match the value chosen for the console port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the board"
+ flavor data
+ calculated 6
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ The board has three serial ports. This option
+ chooses which port will be used to connect to a host
+ running GDB."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+ display "Default console channel."
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ calculated 0
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Console serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ description "
+ The board has only three serial ports. This option
+ chooses which port will be used for console output."
+ }
+
+ cdl_component CYGBLD_GLOBAL_OPTIONS {
+ display "Global build options"
+ flavor none
+ no_define
+ description "
+ Global build options including control over
+ compiler flags, linker flags and choice of toolchain."
+
+
+ parent CYGPKG_NONE
+
+ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ display "Global command prefix"
+ flavor data
+ no_define
+ default_value { "arm-none-eabi" }
+ description "
+ This option specifies the command prefix used when
+ invoking the build tools."
+ }
+
+ cdl_option CYGBLD_GLOBAL_CFLAGS {
+ display "Global compiler flags"
+ flavor data
+ no_define
+ default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ description "
+ This option controls the global compiler flags which are used to
+ compile all packages by default. Individual packages may define
+ options which override these global flags."
+ }
+
+ cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ display "Global linker flags"
+ flavor data
+ no_define
+ default_value { "-Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" }
+ description "
+ This option controls the global linker flags. Individual
+ packages may define options which override these global flags."
+ }
+
+ cdl_option CYGBLD_BUILD_GDB_STUBS {
+ display "Build GDB stub ROM image"
+ default_value 0
+ requires { CYG_HAL_STARTUP == "ROM" }
+ requires CYGSEM_HAL_ROM_MONITOR
+ requires CYGBLD_BUILD_COMMON_GDB_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ no_define
+ description "
+ This option enables the building of the GDB stubs for the
+ board. The common HAL controls takes care of most of the
+ build process, but the final conversion from ELF image to
+ binary data is handled by the platform CDL, allowing
+ relocation of the data if necessary."
+
+ make -priority 320 {
+ <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
+ $(OBJCOPY) --remove-section=.fixed_vectors -O binary $< $@
+ }
+ }
+ }
+
+ cdl_component CYGPKG_HAL_ARM_BOARD_OPTIONS {
+ display "Freescale MXC Board build options"
+ flavor none
+ no_define
+ description "
+ Package specific build options including control over
+ compiler flags used only in building this package,
+ and details of which tests are built."
+
+ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the board HAL. These flags are used in addition
+ to the set of global flags."
+ }
+
+ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_REMOVE {
+ display "Suppressed compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the board HAL. These flags are removed from
+ the set of global flags if present."
+ }
+
+ }
+
+ cdl_component CYGHWR_MEMORY_LAYOUT {
+ display "Memory layout"
+ flavor data
+ no_define
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_board_ram" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" :
+ "arm_board_rom" }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ display "Memory layout linker script fragment"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.ldi>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.ldi>" :
+ "<pkgconf/mlt_arm_board_rom.ldi>" }
+ }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ display "Memory layout header file"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_H
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.h>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.h>" :
+ "<pkgconf/mlt_arm_board_rom.h>" }
+ }
+ }
+
+ cdl_option CYGSEM_HAL_ROM_MONITOR {
+ display "Behave as a ROM monitor"
+ flavor bool
+ default_value 0
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+ description "
+ Enable this option if this program is to be used as a ROM monitor,
+ i.e. applications will be loaded into RAM on the board, and this
+ ROM monitor may process exceptions or interrupts generated from the
+ application. This enables features such as utilizing a separate
+ interrupt stack when exceptions are generated."
+ }
+
+ cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ display "Work with a ROM monitor"
+ flavor booldata
+ legal_values { "Generic" "GDB_stubs" }
+ default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "RAM" }
+ description "
+ Support can be enabled for different varieties of ROM monitor.
+ This support changes various eCos semantics such as the encoding
+ of diagnostic output, or the overriding of hardware interrupt
+ vectors.
+ Firstly there is \"Generic\" support which prevents the HAL
+ from overriding the hardware vectors that it does not use, to
+ instead allow an installed ROM monitor to handle them. This is
+ the most basic support which is likely to be common to most
+ implementations of ROM monitor.
+ \"GDB_stubs\" provides support when GDB stubs are included in
+ the ROM monitor or boot ROM."
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ display "Redboot HAL options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+ description "
+ This option lists the target's requirements for a valid Redboot
+ configuration."
+
+ compile -library=libextras.a redboot_cmds.c
+
+ cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ display "Build Redboot ROM binary image"
+ active_if CYGBLD_BUILD_REDBOOT
+ default_value 1
+ no_define
+ description "This option enables the conversion of the Redboot ELF
+ image to a binary image suitable for ROM programming."
+
+ make -priority 325 {
+ <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+ $(OBJCOPY) -O binary $< $@
+ }
+ }
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_BOARD_OPTIONS {
+ display "Redboot HAL variant options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+
+ # RedBoot details
+ requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x40008000 }
+ define_proc {
+ puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00"
+ }
+ }
+}
--- /dev/null
+#ifndef CYGONCE_FSL_BOARD_H
+#define CYGONCE_FSL_BOARD_H
+
+//=============================================================================
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+
+#define CPLD_SPI_BASE CSPI2_BASE_ADDR
+#define CPLD_SPI_CHIP_SELECT_NO SPI_CTRL_CS0
+#define CPLD_SPI_CTRL_MODE_MASTER SPI_CTRL_MODE_MASTER_0
+
+/* CPLD offsets */
+#define PBC_LED_CTRL 0x20000
+#define PBC_SB_STAT 0x20008
+#define PBC_ID_AAAA 0x20040
+#define PBC_ID_5555 0x20048
+#define PBC_VERSION 0x20050
+#define PBC_ID_CAFE 0x20058
+#define PBC_INT_STAT 0x20010
+#define PBC_INT_MASK 0x20038
+#define PBC_INT_REST 0x20020
+#define PBC_SW_RESET 0x20060
+#define BOARD_CS_UART_BASE 0x8000
+
+#define REDBOOT_IMAGE_SIZE 0x40000
+
+#define LAN92XX_REG_READ(reg_offset) \
+ ((cpld_reg_xfer(reg_offset, 0x0, 1)) | ((cpld_reg_xfer(reg_offset + 0x2, 0x0, 1) << 16)))
+
+#define LAN92XX_REG_WRITE(reg_offset, val) \
+ (cpld_reg_xfer(reg_offset, val, 0)); \
+ (cpld_reg_xfer(reg_offset + 0x2, (val >> 16), 0));
+
+#define EXT_UART_x16
+/* MX31 3-Stack SDRAM is from 0x40000000, 128M */
+#define SDRAM_BASE_ADDR CSD0_BASE_ADDR
+#define SDRAM_SIZE 0x08000000
+#define RAM_BANK0_BASE SDRAM_BASE_ADDR
+
+#define LED_MAX_NUM 8
+#define LED_IS_ON(n) ((readw(PBC_LED_CTRL) & (1<<(n))) != 0)
+#define TURN_LED_ON(n) writew((readw(PBC_LED_CTRL)|(1<<(n))), PBC_LED_CTRL)
+#define TURN_LED_OFF(n) writew((readw(PBC_LED_CTRL)&(~(1<<(n)))), PBC_LED_CTRL)
+
+#define BOARD_DEBUG_LED(n) 0
+/*
+#define BOARD_DEBUG_LED(n) \
+ CYG_MACRO_START \
+ if (n >= 0 && n < LED_MAX_NUM) { \
+ if (LED_IS_ON(n)) \
+ TURN_LED_OFF(n); \
+ else \
+ TURN_LED_ON(n); \
+ } \
+ CYG_MACRO_END
+*/
+#endif /* CYGONCE_FSL_BOARD_H */
--- /dev/null
+#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
+#define CYGONCE_HAL_PLATFORM_SETUP_H
+
+//=============================================================================
+//
+// hal_platform_setup.h
+//
+// Platform specific support for HAL (assembly code)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <pkgconf/system.h> // System-wide configuration info
+#include CYGBLD_HAL_VARIANT_H // Variant specific configuration
+#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
+#include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
+#include <cyg/hal/hal_mmu.h> // MMU definitions
+#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1 _platform_setup1
+#define CYGHWR_HAL_ARM_HAS_MMU
+
+#ifdef CYG_HAL_STARTUP_ROMRAM
+#define CYGSEM_HAL_ROM_RESET_USES_JUMP
+#endif
+
+//#define NFC_2K_BI_SWAP
+#define SDRAM_FULL_PAGE_BIT 0x100
+#define SDRAM_FULL_PAGE_MODE 0x37
+#define SDRAM_BURST_MODE 0x33
+
+#define CYGHWR_HAL_ROM_VADDR 0x0
+
+#if 0
+#define UNALIGNED_ACCESS_ENABLE
+#define SET_T_BIT_DISABLE
+#define BRANCH_PREDICTION_ENABLE
+#endif
+
+//#define ENABLE_IMPRECISE_ABORT
+
+#define PLATFORM_PREAMBLE flash_header
+
+//flash header & DCD @ 0x400
+.macro flash_header
+ b reset_vector
+.org 0x400
+app_code_jump_v: .long reset_vector
+app_code_barker: .long 0xB1
+app_code_csf: .long 0
+dcd_ptr_ptr: .long dcd_ptr
+super_root_key: .long 0
+dcd_ptr: .long dcd_data
+app_dest_ptr: .long 0x47f00000
+
+dcd_data: .long 0xB17219E9
+dcd_len: .long (49*12)
+
+//DCD
+//iomux 1
+.long 4
+.long 0xc3fa8008
+.long 0x1
+// 2
+.long 4
+.long 0xc3fa800c
+.long 0x1
+// 3
+.long 4
+.long 0xc3fa8010
+.long 0x1
+// 4
+.long 4
+.long 0xc3fa8014
+.long 0x1
+//5
+.long 4
+.long 0xc3fa8018
+.long 0x1
+//6
+.long 4
+.long 0xc3fa801c
+.long 0x1
+// 7
+.long 4
+.long 0xc3fa8020
+.long 0x1
+// 8
+.long 4
+.long 0xc3fa8024
+.long 0x1
+// 9
+.long 4
+.long 0xc3fa8028
+.long 0x1
+//10
+.long 4
+.long 0xc3fa802c
+.long 0x1
+// 11
+.long 4
+.long 0xc3fa8030
+.long 0x1
+// 12
+.long 4
+.long 0xc3fa8034
+.long 0x1
+// 13
+.long 4
+.long 0xc3fa8038
+.long 0x1
+// 14
+.long 4
+.long 0xc3fa803c
+.long 0x1
+// 15
+.long 4
+.long 0xc3fa8040
+.long 0x1
+// 16
+.long 4
+.long 0xc3fa8044
+.long 0x1
+// 17
+.long 4
+.long 0xc3fa8048
+.long 0x1
+// 18
+.long 4
+.long 0xc3fa804c
+.long 0x1
+// 19
+.long 4
+.long 0xc3fa805c
+.long 0x1
+// 20
+.long 4
+.long 0xc3fa82bc
+.long 0x02c4
+// 21
+.long 4
+.long 0xc3fa8060
+.long 0x1
+// 22
+.long 4
+.long 0xc3fa82c0
+.long 0x02c4
+// 23
+.long 4
+.long 0xc3fa84a8
+.long 0x2
+// 24
+.long 4
+.long 0xc3fa84b0
+.long 0x2
+// 25
+.long 4
+.long 0xc3fa84b4
+.long 0x2
+// 26
+.long 4
+.long 0xc3fa84e0
+.long 0x2
+// 27
+.long 4
+.long 0xc3fa8278
+.long 0x2
+// 28
+.long 4
+.long 0xc3fa827c
+.long 0x2
+// 29
+.long 4
+.long 0xc3fa8298
+.long 0x2
+// 30
+.long 4
+.long 0xc3fa829c
+.long 0x2
+// 31
+.long 4
+.long 0xc3fa84fc
+.long 0x2
+// 32
+.long 4
+.long 0xc3fa8504
+.long 0x2
+// 33
+.long 4
+.long 0xc3fa848c
+.long 0x2
+// 34
+.long 4
+.long 0xc3fa849c
+.long 0x2
+// 35
+.long 4
+.long 0xc3fa8294
+.long 0x2
+// 36
+.long 4
+.long 0xc3fa8280
+.long 0x2
+// 37
+.long 4
+.long 0xc3fa8284
+.long 0x2
+// 38
+.long 4
+.long 0xc3fa8288
+.long 0x2
+// 39
+.long 4
+.long 0xc3fa828c
+.long 0x2
+// 40
+.long 4
+.long 0xc3fa8290
+.long 0x2
+
+// set CSD0 1
+// 41
+.long 4
+.long 0xe3fd9000
+.long 0x80000000
+
+// Precharge command 2
+// 42
+.long 4
+.long 0xe3fd9014
+.long 0x04008008
+// refresh commands 3
+// 43
+.long 4
+.long 0xe3fd9014
+.long 0x00008010
+
+// 44
+.long 4
+.long 0xe3fd9014
+.long 0x00008010
+// LMR with CAS=3 BL=3 5
+// 45
+.long 4
+.long 0xe3fd9014
+.long 0x00338018
+
+// 13row 10 col 32 bit sref=4 micro model 6
+// 46
+.long 4
+.long 0xe3fd9000
+.long 0xb2220000
+
+// timing parameter 7
+// 47
+.long 4
+.long 0xe3fd9004
+.long 0x899f6bba
+
+// mddr enable RLAT=2 8
+// 48
+.long 4
+.long 0xe3fd9010
+.long 0x000a1104
+
+// Normal mode 9
+// 49
+.long 4
+.long 0xe3fd9014
+.long 0x00000000
+
+image_len: .long REDBOOT_IMAGE_SIZE
+
+.endm
+
+
+
+
+// This macro represents the initial startup code for the platform
+ .macro _platform_setup1
+FSL_BOARD_SETUP_START:
+
+/*
+ * ARM1136 init
+ * - invalidate I/D cache/TLB and drain write buffer;
+ * - invalidate L2 cache
+ * - unaligned access
+ * - branch predictions
+ */
+ // mrc p15, 0, r0, c1, c1, 0 // Read Secure Configuration Register data. Why doesn't work???
+ // mcr p15, 0, <Rd>, c1, c1, 0 ; Write Secure Configuration Register data
+#ifdef ENABLE_IMPRECISE_ABORT
+ mrs r1, spsr // save old spsr
+ mrs r0, cpsr // read out the cpsr
+ bic r0, r0, #0x100 // clear the A bit
+ msr spsr, r0 // update spsr
+ add lr, pc, #0x8 // update lr
+ movs pc, lr // update cpsr
+ nop
+ nop
+ nop
+ nop
+ msr spsr, r1 // restore old spsr
+#endif
+
+ mov r0, #0
+ mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
+ mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+ mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
+
+ /* Also setup the Peripheral Port Remap register inside the core */
+ ldr r0, ARM_PPMRR /* start from AIPS 2GB region */
+ mcr p15, 0, r0, c15, c2, 4
+
+ /* Reload data from spare area to 0x400 of main area if booting from NAND */
+ ldr r0, NFC_BASE_W
+ cmp pc, r0
+ blo 1f
+ cmp pc, r1
+ bhi 1f
+#ifdef BARKER_CODE_SWAP_LOC
+#if BARKER_CODE_SWAP_LOC != 0x404
+#error FIXME: the following depends on barker code to be 0x404
+#endif
+ // Recover the word at 0x404 offset using the one stored in the spare area 0
+ add r1, r0, #0x400
+ add r1, r1, #0x4
+ mov r3, #0x1000
+ ldr r2, [r0, r3]
+ str r2, [r1]
+#endif
+1:
+#ifdef L2CC_ENABLED
+ /*** L2 Cache setup/invalidation/disable ***/
+ /* Disable L2 cache first */
+ mov r0, #L2CC_BASE_ADDR
+ mov r2, #0
+ str r2, [r0, #L2_CACHE_CTL_REG]
+ /*
+ * Configure L2 Cache:
+ * - 128k size(16k way)
+ * - 8-way associativity
+ * - 0 ws TAG/VALID/DIRTY
+ * - 4 ws DATA R/W
+ */
+ mov r2, #0xFF000000
+ add r2, r2, #0x00F00000
+ ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
+ and r1, r1, r2
+ ldr r2, L2CACHE_PARAM
+ orr r1, r1, r2
+ str r1, [r0, #L2_CACHE_AUX_CTL_REG]
+
+ /* Invalidate L2 */
+ mov r1, #0xFF
+ str r1, [r0, #L2_CACHE_INV_WAY_REG]
+L2_loop:
+ /* Poll Invalidate By Way register */
+ ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
+ ands r2, r2, #0xFF
+ bne L2_loop
+ /*** End of L2 operations ***/
+#endif
+
+/*
+ * End of ARM1136 init
+ */
+init_spba_start:
+ init_spba
+init_aips_start:
+ init_aips
+init_max_start:
+ init_max
+init_m4if_start:
+ init_m4if
+init_iomux_start:
+ init_iomux
+
+ // disable wdog
+ ldr r0, =0x30
+ ldr r1, WDOG1_BASE_W
+ strh r0, [r1]
+
+ /* If SDRAM has been setup, bypass clock/WEIM setup */
+ cmp pc, #SDRAM_BASE_ADDR
+ blo external_boot_cont
+ cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
+ blo internal_boot_cont
+
+external_boot_cont:
+init_sdram_start:
+ setup_sdram
+
+internal_boot_cont:
+init_clock_start:
+ init_clock
+
+
+HWInitialise_skip_SDRAM_setup:
+ ldr r0, NFC_BASE_W
+ add r2, r0, #0x1000 // 4K window
+ cmp pc, r0
+ blo Normal_Boot_Continue
+ cmp pc, r2
+ bhi Normal_Boot_Continue
+
+NAND_Boot_Start:
+ /* Copy image from flash to SDRAM first */
+ ldr r1, MXC_REDBOOT_ROM_START
+1: ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ blo 1b
+
+ /* Jump to SDRAM */
+ ldr r1, CONST_0x0FFF
+ and r0, pc, r1 /* offset of pc */
+ ldr r1, MXC_REDBOOT_ROM_START
+ add r1, r1, #0x10
+ add pc, r0, r1
+ nop
+ nop
+ nop
+ nop
+ nop
+
+NAND_Copy_Main:
+ // Check if x16/2kb page
+// ldr r7, CCM_BASE_ADDR_W
+// ldr r7, [r7, #0xC]
+// ands r7, r7, #(1 << 30)
+ ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
+ mov r1, #0x1000 //r1: starting flash addr to be copied. Updated constantly
+ // ???? should be dynamic based on the page size kevin todo
+ add r2, r0, #0x1000 //r2: end of 3rd RAM buf. Doesn't change ?? dynamic
+
+ ldr r11, NFC_IP_BASE_W //r11: NFC IP register base. Doesn't change
+ add r12, r0, #0x1E00 //r12: NFC AXI register base. Doesn't change
+ ldr r14, MXC_REDBOOT_ROM_START
+ add r13, r14, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
+ add r14, r14, r1 //r14: starting SDRAM address for copying. Updated constantly
+
+ //unlock internal buffer
+ mov r3, #0xFF000000
+ add r3, r3, #0x00FF0000
+ str r3, [r11, #0x4]
+ str r3, [r11, #0x8]
+ str r3, [r11, #0xC]
+ str r3, [r11, #0x10]
+ mov r3, #0x20000
+ add r3, r3, #0x4
+ str r3, [r11, #0x0] // kevin - revist for multiple CS ??
+ mov r3, #0
+ str r3, [r11, #0x18]
+
+Nfc_Read_Page:
+// writew(FLASH_Read_Mode1, NAND_ADD_CMD_REG);
+ mov r3, #0x0;
+ str r3, [r12, #0x0]
+ mov r3, #NAND_LAUNCH_FCMD
+ str r3, [r12, #0xC]
+
+ do_wait_op_done
+// start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
+ mov r4, r1, lsl #1
+ and r3, r4, #0xFF
+ mov r3, r3, lsl #16
+ do_addr_input //1st addr cycle
+ mov r3, r4, lsr #8
+ and r3, r3, #0x1F
+ mov r3, r3, lsl #16
+ do_addr_input //2nd addr cycle
+ mov r3, r4, lsr #13
+ and r3, r3, #0xFF
+ mov r3, r3, lsl #16
+ do_addr_input //3rd addr cycle
+ mov r3, r4, lsr #21
+ and r3, r3, #0xFF
+ mov r3, r3, lsl #16
+ do_addr_input //4th addr cycle
+ mov r3, r4, lsr #29
+ and r3, r3, #0xF
+ mov r3, r3, lsl #16
+ do_addr_input //5th addr cycle TODO
+
+// writew(FLASH_Read_Mode1_2K, NAND_ADD_CMD_REG);
+ mov r3, #0x30;
+ str r3, [r12, #0x0]
+ mov r3, #NAND_LAUNCH_FCMD
+ str r3, [r12, #0xC]
+ do_wait_op_done
+
+// write RBA=0 to NFC_CONFIGURATION1
+ mov r3, #0
+ str r3, [r12, #0x4]
+
+// writel(mode & 0xFF, NAND_LAUNCH_REG);
+ mov r3, #0x8
+ str r3, [r12, #0xC]
+// wait_op_done();
+ do_wait_op_done
+
+
+Copy_Good_Blk:
+ //copying page
+1: ldmia r0!, {r3-r10}
+ stmia r14!, {r3-r10}
+ cmp r0, r2
+ blo 1b
+ cmp r14, r13
+ bge NAND_Copy_Main_done
+ add r1, r1, #0x1000
+ ldr r0, NFC_BASE_W
+ b Nfc_Read_Page
+
+NAND_Copy_Main_done:
+
+Normal_Boot_Continue:
+
+#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
+ /* Copy image from flash to SDRAM first */
+ ldr r0, =0xFFFFF000
+ and r0, r0, pc
+ ldr r1, MXC_REDBOOT_ROM_START
+ cmp r0, r1
+ beq HWInitialise_skip_SDRAM_copy
+
+ add r2, r0, #REDBOOT_IMAGE_SIZE
+
+1: ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ ble 1b
+ /* Jump to SDRAM */
+ ldr r1, =0xFFFF
+ and r0, pc, r1 /* offset of pc */
+ ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
+ add pc, r0, r1
+ nop
+ nop
+ nop
+ nop
+#endif /* CYG_HAL_STARTUP_ROMRAM */
+
+HWInitialise_skip_SDRAM_copy:
+
+/*
+ * Note:
+ * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
+ */
+
+STACK_Setup:
+ // Set up a stack [for calling C code]
+ ldr r1, =__startup_stack
+ ldr r2, =RAM_BANK0_BASE
+ orr sp, r1, r2
+
+ // Create MMU tables
+ bl hal_mmu_init
+
+ // Enable MMU
+ ldr r2, =10f
+ mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
+ orr r1, r1, #7 // enable MMU bit
+ orr r1, r1, #0x800 // enable z bit
+ mcr MMU_CP, 0, r1, MMU_Control, c0
+ mov pc,r2 /* Change address spaces */
+ nop
+ nop
+ nop
+10:
+
+ // Save shadow copy of BCR, also hardware configuration
+ ldr r1, =_board_BCR
+ str r2, [r1]
+ ldr r1, =_board_CFG
+ str r9, [r1] // Saved far above...
+
+ .endm // _platform_setup1
+
+#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1
+#endif
+
+ /* Do nothing */
+ .macro init_spba
+ .endm /* init_spba */
+
+ /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
+ .macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, AIPS1_CTRL_BASE_ADDR_W
+ ldr r1, AIPS1_PARAM_W
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ ldr r0, AIPS2_CTRL_BASE_ADDR_W
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+
+ .endm /* init_aips */
+
+ /* MAX (Multi-Layer AHB Crossbar Switch) setup */
+ .macro init_max
+ ldr r0, MAX_BASE_ADDR_W
+#if 0
+ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+ ldr r1, MAX_PARAM1
+ str r1, [r0, #0x000] /* for S0 */
+ str r1, [r0, #0x100] /* for S1 */
+ str r1, [r0, #0x200] /* for S2 */
+ str r1, [r0, #0x300] /* for S3 */
+ str r1, [r0, #0x400] /* for S4 */
+ /* SGPCR - always park on last master */
+ ldr r1, =0x10
+ str r1, [r0, #0x010] /* for S0 */
+ str r1, [r0, #0x110] /* for S1 */
+ str r1, [r0, #0x210] /* for S2 */
+ str r1, [r0, #0x310] /* for S3 */
+ str r1, [r0, #0x410] /* for S4 */
+ /* MGPCR - restore default values */
+ ldr r1, =0x0
+ str r1, [r0, #0x800] /* for M0 */
+ str r1, [r0, #0x900] /* for M1 */
+ str r1, [r0, #0xA00] /* for M2 */
+ str r1, [r0, #0xB00] /* for M3 */
+ str r1, [r0, #0xC00] /* for M4 */
+ str r1, [r0, #0xD00] /* for M5 */
+#endif
+ .endm /* init_max */
+
+ .macro init_clock
+ /*
+ * Clock setup
+ * After this step,
+
+ Module Freq (MHz)
+ ===========================
+ ARM core 532 ap_clk
+ AHB 133 ahb_clk
+ IP 66.5 ipg_clk
+ EMI 133 ddr_clk
+
+ * All other clocks can be figured out based on this.
+ */
+ /*
+ * Step 1: Switch to step clock
+ */
+ ldr r0, CCM_BASE_ADDR_W
+ mov r1, #0x00000104
+ str r1, [r0, #CLKCTL_CCSR]
+
+ /* Step 2: Setup PLL's */
+ /* Set PLL1 to be 532MHz */
+ ldr r0, PLL1_BASE_ADDR_W
+
+ mov r1, #0x1200
+ add r1, r1, #0x22
+ str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
+ ldr r1, =0x2
+ str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+
+ ldr r1, =0x50
+ str r1, [r0, #PLL_DP_OP]
+ ldr r1, =23
+ str r1, [r0, #PLL_DP_MFD]
+ ldr r1, =13
+ str r1, [r0, #PLL_DP_MFN]
+
+ ldr r1, =0x50
+ str r1, [r0, #PLL_DP_HFS_OP]
+ ldr r1, =23
+ str r1, [r0, #PLL_DP_HFS_MFD]
+ ldr r1, =13
+ str r1, [r0, #PLL_DP_HFS_MFN]
+
+ /* Now restart PLL 1 */
+ ldr r1, PLL_VAL_0x1232
+ str r1, [r0, #PLL_DP_CTL]
+ 1:
+ ldr r1, [r0, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+ beq 1b
+
+ /*
+ * Step 2: Setup PLL2 to 665 MHz.
+ */
+ ldr r0, PLL2_BASE_ADDR_W
+
+ ldr r1, =0x1200
+ add r1, r1, #0x22
+ str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
+ ldr r1, =0x2
+ str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+
+ ldr r1, =0x60
+ str r1, [r0, #PLL_DP_OP]
+ ldr r1, =95
+ str r1, [r0, #PLL_DP_MFD]
+ ldr r1, =89
+ str r1, [r0, #PLL_DP_MFN]
+
+ ldr r1, =0x60
+ str r1, [r0, #PLL_DP_HFS_OP]
+ ldr r1, =95
+ str r1, [r0, #PLL_DP_HFS_MFD]
+ ldr r1, =89
+ str r1, [r0, #PLL_DP_HFS_MFN]
+
+ /* Now restart PLL 2 */
+ ldr r1, PLL_VAL_0x1232
+ str r1, [r0, #PLL_DP_CTL]
+ 1:
+ ldr r1, [r0, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+ beq 1b
+
+ /*
+ * Set PLL 3 to 216MHz
+ */
+ ldr r0, PLL3_BASE_ADDR_W
+
+ ldr r1, PLL_VAL_0x222
+ str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
+ ldr r1, =0x2
+ str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+
+ ldr r1, =0x91
+ str r1, [r0, #PLL_DP_OP]
+ ldr r1, =0x0
+ str r1, [r0, #PLL_DP_MFD]
+ ldr r1, =0x0
+ str r1, [r0, #PLL_DP_MFN]
+
+ ldr r1, =0x91
+ str r1, [r0, #PLL_DP_HFS_OP]
+ ldr r1, =0x0
+ str r1, [r0, #PLL_DP_HFS_MFD]
+ ldr r1, =0x0
+ str r1, [r0, #PLL_DP_HFS_MFN]
+
+ /* Now restart PLL 3 */
+ ldr r1, PLL_VAL_0x232
+ str r1, [r0, #PLL_DP_CTL]
+
+ 1:
+ ldr r1, [r0, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+ beq 1b
+ /* End of PLL 3 setup */
+
+ /* Setup the ARM platform clock dividers */
+ ldr r0, PLATFORM_BASE_ADDR_W
+ ldr r1, PLATFORM_CLOCK_DIV_W
+ str r1, [r0, #0x18]
+
+ /*
+ * Step 3: switching to PLL 1 and restore default register values.
+ */
+ ldr r0, CCM_BASE_ADDR_W
+ mov r1, #0x00000100
+ str r1, [r0, #CLKCTL_CCSR]
+
+ mov r1, #0x000A0000
+ add r1, r1, #0x00000F0
+ str r1, [r0, #CLKCTL_CCOSR]
+ /* Use 133MHz for DDR clock */
+ mov r1, #0x1C00
+ str r1, [r0, #CLKCTL_CAMR]
+ /* Use PLL 2 for UART's, get 66.5MHz from it */
+ ldr r1, CCM_VAL_0xA5A6A020
+ str r1, [r0, #CLKCTL_CSCMR1]
+ ldr r1, CCM_VAL_0x01450B21
+ str r1, [r0, #CLKCTL_CSCDR1]
+
+ mov r1, #0x1C
+ str r1, [r0, #CLKCTL_CBCDR7]
+ mov r1, #1
+ str r1, [r0, #4]
+ .endm /* init_clock */
+
+ /* M4IF setup */
+ .macro init_m4if
+ /* Configure M4IF registers, VPU and IPU given higher priority (=0x4)
+ IPU accesses with ID=0x1 given highest priority (=0xA) */
+ ldr r1, M4IF_BASE_W
+ ldr r0, M4IF_0x00000a01
+ str r0, [r1, #M4IF_FIDBP]
+
+ ldr r0, M4IF_0x00000404
+ str r0, [r1, #M4IF_FBPM0]
+ .endm /* init_m4if */
+
+ .macro setup_sdram
+ ldr r0, ESDCTL_BASE_W
+ /* Set CSD0 */
+ ldr r1, =0x80000000
+ str r1, [r0, #ESDCTL_ESDCTL0]
+ /* Precharge command */
+ ldr r1, SDRAM_0x04008008
+ str r1, [r0, #ESDCTL_ESDSCR]
+ /* 2 refresh commands */
+ ldr r1, SDRAM_0x00008010
+ str r1, [r0, #ESDCTL_ESDSCR]
+ str r1, [r0, #ESDCTL_ESDSCR]
+ /* LMR with CAS=3 and BL=3 */
+ ldr r1, SDRAM_0x00338018
+ str r1, [r0, #ESDCTL_ESDSCR]
+ /* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
+ ldr r1, SDRAM_0xB2220000
+ str r1, [r0, #ESDCTL_ESDCTL0]
+ /* Timing parameters */
+ ldr r1, SDRAM_0x899F6BBA
+ str r1, [r0, #ESDCTL_ESDCFG0]
+ /* MDDR enable, RLAT=2 */
+ ldr r1, SDRAM_0x000A1104
+ str r1, [r0, #ESDCTL_ESDMISC]
+ /* Normal mode */
+ ldr r1, =0x00000000
+ str r1, [r0, #ESDCTL_ESDSCR]
+ .endm
+
+ .macro do_wait_op_done
+ 1:
+ ldr r3, [r11, #0x18]
+ ands r3, r3, #NFC_IPC_INT
+ beq 1b
+ mov r3, #0x0
+ str r3, [r11, #0x18]
+ .endm // do_wait_op_done
+
+ .macro do_addr_input
+ str r3, [r12, #0x0]
+ mov r3, #NAND_LAUNCH_FADD
+ str r3, [r12, #0xC]
+ do_wait_op_done
+ .endm // do_addr_input
+
+ /* To support 133MHz DDR */
+ .macro init_iomux
+ ldr r0, IOMUXC_BASE_ADDR_W
+
+ // DDR signal setup for D16-D31 and drive strength
+ ldr r8, =0x1
+ add r1, r0, #8
+ add r2, r0, #0x4C
+ 1:
+ stmia r1!, {r8}
+ cmp r1, r2
+ bls 1b
+
+ str r8, [r0, #0x5C]
+ str r8, [r0, #0x60]
+
+ add r2, r0, #0x200
+ mov r8, #0x2C4
+ str r8, [r2, #0xBC]
+ str r8, [r2, #0xC0]
+
+ ldr r8, =0x2
+ str r8, [r0, #0x4A8]
+ str r8, [r0, #0x4B0]
+ str r8, [r0, #0x4B4]
+ str r8, [r0, #0x4E0]
+ str r8, [r0, #0x4FC]
+ str r8, [r0, #0x504]
+ str r8, [r0, #0x48C]
+ str r8, [r0, #0x49C]
+
+ add r1, r0, #0x278
+ add r2, r0, #0x29C
+ 2:
+ stmia r1!, {r8}
+ cmp r1, r2
+ bls 2b
+ .endm /* init_iomux */
+
+#define PLATFORM_VECTORS _platform_vectors
+ .macro _platform_vectors
+ .globl _board_BCR, _board_CFG
+_board_BCR: .long 0 // Board Control register shadow
+_board_CFG: .long 0 // Board Configuration (read at RESET)
+ .endm
+
+ARM_PPMRR: .word 0x80000016
+L2CACHE_PARAM: .word 0x0003001B
+WDOG1_BASE_W: .word WDOG1_BASE_ADDR
+IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
+AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
+AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
+AIPS1_PARAM_W: .word 0x77777777
+MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
+MAX_PARAM1: .word 0x00302154
+ESDCTL_BASE_W: .word ESDCTL_BASE
+M4IF_BASE_W: .word M4IF_BASE
+M4IF_0x00000a01: .word 0x00000a01
+M4IF_0x00000404: .word 0x00000404
+NFC_BASE_W: .word NFC_BASE
+NFC_IP_BASE_W: .word NFC_IP_BASE
+SDRAM_0x04008008: .word 0x04008008
+SDRAM_0x00008010: .word 0x00008010
+SDRAM_0x00338018: .word 0x00338018
+SDRAM_0xB2220000: .word 0xB2220000
+SDRAM_0x899F6BBA: .word 0x899F6BBA
+SDRAM_0x000A1104: .word 0x000A1104
+IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
+MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
+CONST_0x0FFF: .word 0x0FFF
+CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
+PLATFORM_BASE_ADDR_W: .word PLATFORM_BASE_ADDR
+PLATFORM_CLOCK_DIV_W: .word 0x00077713
+CCM_VAL_0x01450B21: .word 0x01450B21
+CCM_VAL_0xA5A6A020: .word 0xA5A6A020
+PLL_VAL_0x222: .word 0x222
+PLL_VAL_0x232: .word 0x232
+PLL1_BASE_ADDR_W: .word PLL1_BASE_ADDR
+PLL2_BASE_ADDR_W: .word PLL2_BASE_ADDR
+PLL3_BASE_ADDR_W: .word PLL3_BASE_ADDR
+PLL_VAL_0x1232: .word 0x1232
+
+/*---------------------------------------------------------------------------*/
+/* end of hal_platform_setup.h */
+#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x00000000)
+#define CYGMEM_REGION_ram_SIZE (0x7F00000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0x47F00000)
+#define CYGMEM_REGION_rom_SIZE (0x100000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ ram : ORIGIN = 0, LENGTH = 0x7F00000
+ rom : ORIGIN = 0x47F00000, LENGTH = 0x100000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_rom_vectors (rom, 0x47F00000, LMA_EQ_VMA)
+ SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
+ SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table))
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
--- /dev/null
+version 0
+region ram 0 7F00000 0 !
+region rom 47F00000 100000 1 !
+section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
+section data 0 1 1 1 1 1 0 0 8000 bss !
+section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
+section heap1 0 8 0 0 0 0 0 0 !
+section rom_vectors 0 1 0 1 1 1 1 1 47F00000 47F00000 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata rodata !
+section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 4 0 1 0 0 0 1 data !
--- /dev/null
+#ifndef CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+#define CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+
+//=============================================================================
+//
+// plf_io.h
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/hal/fsl_board.h>
+#include <cyg/hal/hal_soc.h>
+
+#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \
+ CYG_MACRO_START \
+ { \
+ extern unsigned int system_rev; \
+ /* Next ATAG_MEM. */ \
+ _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_MEM; \
+ /* Round up so there's only one bit set in the memory size. \
+ * Don't double it if it's already a power of two, though. \
+ */ \
+ _p_->u.mem.size = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE); \
+ if (_p_->u.mem.size < CYGMEM_REGION_ram_SIZE) \
+ _p_->u.mem.size <<= 1; \
+ _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram); \
+ _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size); \
+ _p_->hdr.size = ((sizeof(struct tag_revision)) + sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_REVISION; \
+ _p_->u.revision.rev = system_rev; \
+ } \
+ CYG_MACRO_END
+
+#endif // CYGONCE_HAL_ARM_BOARD_PLF_IO_H
--- /dev/null
+#ifndef CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+#define CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+//=============================================================================
+//
+// plf_mmap.h
+//
+// Platform specific memory map support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_misc.h>
+
+// Get the pagesize for a particular virtual address:
+
+// This does not depend on the vaddr.
+#define HAL_MM_PAGESIZE(vaddr, pagesize) CYG_MACRO_START \
+ (pagesize) = SZ_1M; \
+CYG_MACRO_END
+
+// Get the physical address from a virtual address:
+
+#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START \
+ cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
+ if ( _v_ < 128 * SZ_1M ) /* SDRAM */ \
+ _v_ += SDRAM_BASE_ADDR; \
+ else /* Rest of it */ \
+ /* no change */ ; \
+ (paddr) = _v_; \
+CYG_MACRO_END
+
+//---------------------------------------------------------------------------
+#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
--- /dev/null
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware mx37_3stack ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM current ;
+ package -hardware CYGPKG_HAL_ARM_MX37 current ;
+ package -hardware CYGPKG_HAL_ARM_MX37_3STACK current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ;
+ package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ;
+ package -hardware CYGPKG_COMPRESS_ZLIB current ;
+ package -hardware CYGPKG_IO_FLASH current ;
+ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+ package -hardware CYGPKG_DEVS_MXC_SPI current ;
+ package -hardware CYGPKG_DEVS_MXC_I2C current ;
+
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package CYGPKG_MEMALLOC current ;
+
+ package -hardware CYGPKG_DEVS_USB_IMX_OTG current ;
+ package -hardware CYGPKG_IO_USB current ;
+ package -hardware CYGPKG_IO_USB_SLAVE current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FSL_SPI_VER_2_3 {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MMC {
+ inferred_value 1
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
+ user_value 50
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ inferred_value 0x00040000
+};
+
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+ inferred_value 0x40008000
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_component CYG_HAL_STARTUP {
+ user_value ROMRAM
+};
+
+cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+ inferred_value 1
+};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+ inferred_value 2
+};
+
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+ user_value 1 "FSL 200904"
+};
+
+cdl_option CYGHWR_USB_DEVS_MX37_OTG {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_MXC_USB_BUFFER_USE_IRAM {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_IMX_USB_DOWNLOAD_SUPPORT {
+ inferred_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_IMXOTG {
+ inferred_value 1
+};
--- /dev/null
+/*=============================================================================
+//
+// board_diag.c
+//
+// HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_arch.h> // basic machine info
+#include <cyg/hal/hal_intr.h> // interrupt macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_if.h> // Calling-if API
+#include <cyg/hal/drv_api.h> // driver API
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/fsl_board.h> // Platform specifics
+
+static void cyg_hal_plf_duart_init(void);
+extern void cyg_hal_plf_serial_init(void);
+
+#define DUART_WORKAROUND_DELAY(a) hal_delay_us(a);
+
+
+void cyg_hal_plf_comms_init(void)
+{
+ static int initialized = 0;
+
+ if (initialized)
+ return;
+
+ initialized = 1;
+
+ /* Setup GPIO and enable transceiver for UARTs */
+ cyg_hal_plf_duart_init();
+ cyg_hal_plf_serial_init();
+}
+
+//=============================================================================
+// ST16552 DUART driver
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// There are two serial ports.
+#define CYG_DEV_SERIAL_BASE_A (BOARD_CS_UART_BASE + 0x0000) // port A
+#define CYG_DEV_SERIAL_BASE_B (BOARD_CS_UART_BASE + 0x8000) // port B
+
+//-----------------------------------------------------------------------------
+// Based on 14.7456 MHz xtal
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x60
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x30
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x18
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x10
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x08
+#endif
+
+#ifndef CYG_DEV_SERIAL_BAUD_MSB
+#error Missing/incorrect serial baud rate defined - CDL error?
+#endif
+
+//-----------------------------------------------------------------------------
+// Define the serial registers. The board is equipped with a 16552
+// serial chip.
+
+#ifdef EXT_UART_x16
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT16
+#define HAL_READ_UINT_UART HAL_READ_UINT16
+typedef cyg_uint16 uart_width;
+#else //_x8
+typedef cyg_uint8 uart_width;
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT8
+#define HAL_READ_UINT_UART HAL_READ_UINT8
+#endif
+
+#define CYG_DEV_SERIAL_RHR 0x00 // receiver buffer register, read, dlab = 0
+#define CYG_DEV_SERIAL_THR 0x00 // transmitter holding register, write, dlab = 0
+#define CYG_DEV_SERIAL_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IER 0x01 // interrupt enable register, read/write, dlab = 0
+#define CYG_DEV_SERIAL_DLM 0x01 // divisor latch (MS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IIR 0x02 // interrupt identification register, read, dlab = 0
+#define CYG_DEV_SERIAL_FCR 0x02 // fifo control register, write, dlab = 0
+#define CYG_DEV_SERIAL_AFR 0x02 // alternate function register, read/write, dlab = 1
+#define CYG_DEV_SERIAL_LCR 0x03 // line control register, read/write
+#define CYG_DEV_SERIAL_MCR 0x04
+#define CYG_DEV_SERIAL_MCR_A 0x04
+#define CYG_DEV_SERIAL_MCR_B 0x04
+#define CYG_DEV_SERIAL_LSR 0x05 // line status register, read
+#define CYG_DEV_SERIAL_MSR 0x06 // modem status register, read
+#define CYG_DEV_SERIAL_SCR 0x07 // scratch pad register
+
+// The interrupt enable register bits.
+#define SIO_IER_ERDAI 0x01 // enable received data available irq
+#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
+#define SIO_IER_ELSI 0x04 // enable receiver line status irq
+#define SIO_IER_EMSI 0x08 // enable modem status interrupt
+
+// The interrupt identification register bits.
+#define SIO_IIR_IP 0x01 // 0 if interrupt pending
+#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
+#define ISR_Tx 0x02
+#define ISR_Rx 0x04
+
+// The line status register bits.
+#define SIO_LSR_DR 0x01 // data ready
+#define SIO_LSR_OE 0x02 // overrun error
+#define SIO_LSR_PE 0x04 // parity error
+#define SIO_LSR_FE 0x08 // framing error
+#define SIO_LSR_BI 0x10 // break interrupt
+#define SIO_LSR_THRE 0x20 // transmitter holding register empty
+#define SIO_LSR_TEMT 0x40 // transmitter register empty
+#define SIO_LSR_ERR 0x80 // any error condition
+
+// The modem status register bits.
+#define SIO_MSR_DCTS 0x01 // delta clear to send
+#define SIO_MSR_DDSR 0x02 // delta data set ready
+#define SIO_MSR_TERI 0x04 // trailing edge ring indicator
+#define SIO_MSR_DDCD 0x08 // delta data carrier detect
+#define SIO_MSR_CTS 0x10 // clear to send
+#define SIO_MSR_DSR 0x20 // data set ready
+#define SIO_MSR_RI 0x40 // ring indicator
+#define SIO_MSR_DCD 0x80 // data carrier detect
+
+// The line control register bits.
+#define SIO_LCR_WLS0 0x01 // word length select bit 0
+#define SIO_LCR_WLS1 0x02 // word length select bit 1
+#define SIO_LCR_STB 0x04 // number of stop bits
+#define SIO_LCR_PEN 0x08 // parity enable
+#define SIO_LCR_EPS 0x10 // even parity select
+#define SIO_LCR_SP 0x20 // stick parity
+#define SIO_LCR_SB 0x40 // set break
+#define SIO_LCR_DLAB 0x80 // divisor latch access bit
+
+// The FIFO control register
+#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
+#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
+#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
+
+//-----------------------------------------------------------------------------
+
+typedef struct {
+ uart_width* base;
+ cyg_int32 msec_timeout;
+ int isr_vector;
+} channel_data_t;
+
+static channel_data_t channels[] = {
+#if CYGHWR_HAL_ARM_DUART_UARTA != 0
+ {(uart_width*)CYG_DEV_SERIAL_BASE_A, 1000, 0},
+#endif
+#if CYGHWR_HAL_ARM_DUART_UARTB != 0
+ {(uart_width*)CYG_DEV_SERIAL_BASE_B, 1000, 0}
+#endif
+};
+
+//-----------------------------------------------------------------------------
+
+static void init_duart_channel(channel_data_t* __ch_data)
+{
+ uart_width* base = __ch_data->base;
+ uart_width lcr;
+
+ // 8-1-no parity.
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR,
+ SIO_LCR_WLS0 | SIO_LCR_WLS1);
+ DUART_WORKAROUND_DELAY(50);
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ lcr |= SIO_LCR_DLAB;
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLL, CYG_DEV_SERIAL_BAUD_LSB);
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLM, CYG_DEV_SERIAL_BAUD_MSB);
+ lcr &= ~SIO_LCR_DLAB;
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_FCR, 0x07); // Enable & clear FIFO
+}
+
+//#define x_debug_uart_log_buf
+#ifdef x_debug_uart_log_buf
+#define x_DIAG_BUFSIZE 2048
+static char __x_log_buf[x_DIAG_BUFSIZE];
+static int x_diag_bp = 0;
+#endif
+
+void cyg_hal_plf_duart_putc(void* __ch_data, cyg_uint8 c)
+{
+ uart_width* base = ((channel_data_t*)__ch_data)->base;
+ uart_width lsr;
+
+#ifdef x_debug_uart_log_buf
+ __x_log_buf[x_diag_bp++] = c;
+#endif
+ CYGARC_HAL_SAVE_GP();
+
+ do {
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ } while ((lsr & SIO_LSR_THRE) == 0);
+
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_THR, c);
+
+ // Hang around until the character has been safely sent.
+ do {
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ } while ((lsr & SIO_LSR_THRE) == 0);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool cyg_hal_plf_duart_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+ uart_width* base = ((channel_data_t*)__ch_data)->base;
+ uart_width lsr, ch16;
+
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ if ((lsr & SIO_LSR_DR) == 0)
+ return false;
+
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_RHR, ch16);
+
+ *ch = (cyg_uint8) (ch16 & 0x00FF);
+
+ return true;
+}
+
+cyg_uint8 cyg_hal_plf_duart_getc(void* __ch_data)
+{
+ cyg_uint8 ch;
+
+ CYGARC_HAL_SAVE_GP();
+
+ while (!cyg_hal_plf_duart_getc_nonblock(__ch_data, &ch));
+
+ CYGARC_HAL_RESTORE_GP();
+ return ch;
+}
+
+static void cyg_hal_plf_duart_write(void* __ch_data, const cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while (__len-- > 0)
+ cyg_hal_plf_duart_putc(__ch_data, *__buf++);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static void cyg_hal_plf_duart_read(void* __ch_data, cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while (__len-- > 0)
+ *__buf++ = cyg_hal_plf_duart_getc(__ch_data);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool cyg_hal_plf_duart_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+ int delay_count;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_bool res;
+
+ CYGARC_HAL_SAVE_GP();
+
+ delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+ for (;;) {
+ res = cyg_hal_plf_duart_getc_nonblock(__ch_data, ch);
+ if (res || 0 == delay_count--)
+ break;
+
+ CYGACC_CALL_IF_DELAY_US(100);
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static int cyg_hal_plf_duart_control(void *__ch_data,
+ __comm_control_cmd_t __func, ...)
+{
+ static int irq_state = 0;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ uart_width ier;
+ int ret = 0;
+
+ CYGARC_HAL_SAVE_GP();
+
+ switch (__func) {
+ case __COMMCTL_IRQ_ENABLE:
+ HAL_INTERRUPT_UNMASK(chan->isr_vector);
+ HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ ier |= SIO_IER_ERDAI;
+ HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ irq_state = 1;
+ break;
+ case __COMMCTL_IRQ_DISABLE:
+ ret = irq_state;
+ irq_state = 0;
+ HAL_INTERRUPT_MASK(chan->isr_vector);
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ ier &= ~SIO_IER_ERDAI;
+ HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ break;
+ case __COMMCTL_DBG_ISR_VECTOR:
+ ret = chan->isr_vector;
+ break;
+ case __COMMCTL_SET_TIMEOUT:
+ {
+ va_list ap;
+
+ va_start(ap, __func);
+
+ ret = chan->msec_timeout;
+ chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+ va_end(ap);
+ }
+ break;
+ default:
+ break;
+ }
+ CYGARC_HAL_RESTORE_GP();
+ return ret;
+}
+
+static int cyg_hal_plf_duart_isr(void *__ch_data, int* __ctrlc,
+ CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ uart_width _iir;
+ int res = 0;
+ CYGARC_HAL_SAVE_GP();
+
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IIR, _iir);
+ _iir &= SIO_IIR_ID_MASK;
+
+ *__ctrlc = 0;
+ if ( ISR_Rx == _iir ) {
+ uart_width c, lsr;
+ cyg_uint8 c8;
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_LSR, lsr);
+ if (lsr & SIO_LSR_DR) {
+
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_RHR, c);
+
+ c8 = (cyg_uint8) (c & 0x00FF);
+
+ if (cyg_hal_is_break( &c8 , 1 ))
+ *__ctrlc = 1;
+ }
+
+ // Acknowledge the interrupt
+ HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+ res = CYG_ISR_HANDLED;
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static void cyg_hal_plf_duart_init(void)
+{
+ hal_virtual_comm_table_t* comm;
+ int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ int i;
+
+ // Init channels
+#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
+ for (i = 0; i < NUMOF(channels); i++) {
+ HAL_INTERRUPT_MASK(channels[i].isr_vector);
+ init_duart_channel(&channels[i]);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_duart_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_duart_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_duart_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_duart_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_duart_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_duart_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_duart_getc_timeout);
+ }
+
+ // Restore original console
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
+
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
+#define __BASE CMA101_DUARTA
+#define _INT CYGNUM_HAL_INTERRUPT_SERIAL_A
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1)
+#define __BASE CMA101_DUARTB
+#define _INT CYGNUM_HAL_INTERRUPT_SERIAL_B
+#endif
+
+#ifdef __BASE
+
+#ifdef CYGSEM_HAL_ROM_MONITOR
+#define CYG_HAL_STARTUP_ROM
+#define CYG_HAL_STARTUP_ROMRAM
+#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#endif
+
+#if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define HAL_DIAG_USES_HARDWARE
+#elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
+#define HAL_DIAG_USES_HARDWARE
+#elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+#define HAL_DIAG_USES_HARDWARE
+#endif
+
+static channel_data_t channel = {
+ (uart_width*) _BASE, 0, 0
+};
+
+#ifdef HAL_DIAG_USES_HARDWARE
+
+void hal_diag_init(void)
+{
+ static int init = 0;
+ char *msg = "\n\rARM eCos\n\r";
+ uart_width lcr;
+
+ if (init++) return;
+
+ init_duart_channel(&channel);
+
+ while (*msg) hal_diag_write_char(*msg++);
+}
+
+#ifdef DEBUG_DIAG
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define DIAG_BUFSIZE 32
+#else
+#define DIAG_BUFSIZE 2048
+#endif
+static char diag_buffer[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+
+void hal_diag_write_char(char c)
+{
+ uart_width lsr;
+
+ hal_diag_init();
+
+ cyg_hal_plf_duart_putc(&channel, c)
+
+#ifdef DEBUG_DIAG
+ diag_buffer[diag_bp++] = c;
+ if (diag_bp == DIAG_BUFSIZE) {
+ while (1) ;
+ diag_bp = 0;
+ }
+#endif
+}
+
+void hal_diag_read_char(char *c)
+{
+ *c = cyg_hal_plf_duart_getc(&channel);
+}
+
+#else // HAL_DIAG relies on GDB
+
+// Initialize diag port - assume GDB channel is already set up
+void hal_diag_init(void)
+{
+ if (0) init_duart_channel(&channel); // avoid warning
+}
+
+// Actually send character down the wire
+static void hal_diag_write_char_serial(char c)
+{
+ cyg_hal_plf_duart_putc(&channel, c);
+}
+
+static bool hal_diag_read_serial(char *c)
+{
+ long timeout = 1000000000; // A long time...
+
+ while (!cyg_hal_plf_duart_getc_nonblock(&channel, c))
+ if (0 == --timeout) return false;
+
+ return true;
+}
+
+void hal_diag_read_char(char *c)
+{
+ while (!hal_diag_read_serial(c)) ;
+}
+
+void hal_diag_write_char(char c)
+{
+ static char line[100];
+ static int pos = 0;
+
+ // No need to send CRs
+ if (c == '\r') return;
+
+ line[pos++] = c;
+
+ if (c == '\n' || pos == sizeof(line)) {
+ CYG_INTERRUPT_STATE old;
+
+ // Disable interrupts. This prevents GDB trying to interrupt us
+ // while we are in the middle of sending a packet. The serial
+ // receive interrupt will be seen when we re-enable interrupts
+ // later.
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+#else
+ HAL_DISABLE_INTERRUPTS(old);
+#endif
+
+ while (1) {
+ static char hex[] = "0123456789ABCDEF";
+ cyg_uint8 csum = 0;
+ int i;
+ char c1;
+
+ hal_diag_write_char_serial('$');
+ hal_diag_write_char_serial('O');
+ csum += 'O';
+ for (i = 0; i < pos; i++) {
+ char ch = line[i];
+ char h = hex[(ch>>4)&0xF];
+ char l = hex[ch&0xF];
+ hal_diag_write_char_serial(h);
+ hal_diag_write_char_serial(l);
+ csum += h;
+ csum += l;
+ }
+ hal_diag_write_char_serial('#');
+ hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
+ hal_diag_write_char_serial(hex[csum&0xF]);
+
+ // Wait for the ACK character '+' from GDB here and handle
+ // receiving a ^C instead. This is the reason for this clause
+ // being a loop.
+ if (!hal_diag_read_serial(&c1))
+ continue; // No response - try sending packet again
+
+ if ( c1 == '+' )
+ break; // a good acknowledge
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
+ if ( c1 == 3 ) {
+ // Ctrl-C: breakpoint.
+ cyg_hal_gdb_interrupt (__builtin_return_address(0));
+ break;
+ }
+#endif
+ // otherwise, loop round again
+ }
+
+ pos = 0;
+
+ // And re-enable interrupts
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+#else
+ HAL_RESTORE_INTERRUPTS(old);
+#endif
+
+ }
+}
+#endif
+
+#endif // __BASE
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
--- /dev/null
+//==========================================================================
+//
+// board_misc.c
+//
+// HAL misc board support code for the board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include <redboot.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h> // Interrupt names
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/fsl_board.h> // Platform specifics
+#include <cyg/io/mxc_i2c.h>
+#include <cyg/infra/diag.h> // diag_printf
+
+// All the MM table layout is here:
+#include <cyg/hal/hal_mm.h>
+
+externC void* memset(void *, int, size_t);
+
+volatile void *gpio_mcu1 = (volatile void *)GPIO1_BASE_ADDR;
+volatile void *gpio_mcu2 = (volatile void *)GPIO2_BASE_ADDR;
+volatile void *gpio_mcu3 = (volatile void *)GPIO3_BASE_ADDR;
+volatile void *iomux = (volatile void *)IOMUXC_BASE_ADDR;
+
+/* point to Data Direction Registers (DDIR) of all GPIO ports */
+static volatile cyg_uint32 *const data_dir_reg_ptr_array[3] = {
+ (cyg_uint32 *) ((cyg_uint32) GPIO1_BASE_ADDR + 4),
+ (cyg_uint32 *) ((cyg_uint32) GPIO1_BASE_ADDR + 4),
+ (cyg_uint32 *) ((cyg_uint32) GPIO1_BASE_ADDR + 4)
+};
+
+/* point to Data Registers (DR) of all GPIO ports */
+static volatile unsigned int *const data_reg_ptr_array[3] = {
+ (cyg_uint32 *) GPIO1_BASE_ADDR,
+ (cyg_uint32 *) GPIO2_BASE_ADDR,
+ (cyg_uint32 *) GPIO3_BASE_ADDR
+};
+
+/* point to Pad Status Registers (PSR) of all GPIO ports */
+static volatile unsigned int *const pad_status_reg_ptr_array[3] = {
+ (cyg_uint32 *) ((cyg_uint32) GPIO1_BASE_ADDR + 4 * 2),
+ (cyg_uint32 *) ((cyg_uint32) GPIO2_BASE_ADDR + 4 * 2),
+ (cyg_uint32 *) ((cyg_uint32) GPIO3_BASE_ADDR + 4 * 2)
+};
+
+/* point to IOMUX SW MUX Control Registers*/
+static volatile unsigned int *const iomux_sw_mux_ctrl_reg_array[3] = {
+ (cyg_uint32 *) ((cyg_uint32) IOMUXC_BASE_ADDR + 0x0008), //the offset of sw_mux_ctrl_reg_array is 0x0004
+ (cyg_uint32 *) ((cyg_uint32) IOMUXC_BASE_ADDR + 0x0230), //the offset of sw_pad_ctrl_reg_array is 0x0328
+ (cyg_uint32 *) ((cyg_uint32) IOMUXC_BASE_ADDR + 0x0508), //the offset of daisy_sel_in_reg_array is 0x07AC
+};
+
+void hal_mmu_init(void)
+{
+ unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
+ unsigned long i;
+
+ /*
+ * Set the TTB register
+ */
+ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
+
+ /*
+ * Set the Domain Access Control Register
+ */
+ i = ARM_ACCESS_DACR_DEFAULT;
+ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+
+ /*
+ * First clear all TT entries - ie Set them to Faulting
+ */
+ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+
+ /* Actual Virtual Size Attributes Function */
+ /* Base Base MB cached? buffered? access permissions */
+ /* xxx00000 xxx00000 */
+ X_ARM_MMU_SECTION(0x000, 0x200, 0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */
+ X_ARM_MMU_SECTION(0x100, 0x100, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IRAM */
+ X_ARM_MMU_SECTION(0x400, 0x000, 0x080, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0x400, 0x400, 0x080, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0x7ff, 0x7ff, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* NAND Flash buffer */
+ X_ARM_MMU_SECTION(0x800, 0x800, 0x020, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IPUv3D */
+ X_ARM_MMU_SECTION(0xB00, 0xB00, 0x400, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* periperals */
+}
+
+//
+// Platform specific initialization
+//
+
+void plf_hardware_init(void)
+{
+ unsigned int v;
+
+ v = 0x0040174A; // modified
+ writel(v, NFC_FLASH_CONFIG2_REG);
+
+ writel(0xFFFF0000, UNLOCK_BLK_ADD0_REG);
+ writel(0xFFFF0000, UNLOCK_BLK_ADD1_REG);
+ writel(0xFFFF0000, UNLOCK_BLK_ADD2_REG);
+ writel(0xFFFF0000, UNLOCK_BLK_ADD3_REG);
+
+ v = NFC_WR_PROT_CS0 | NFC_WR_PROT_BLS_UNLOCK | NFC_WR_PROT_WPC;
+ writel(v, NFC_WR_PROT_REG);
+
+ writel(0, NFC_IPC_REG);
+
+#if 0
+ /* PBC setup */
+ //Enable UART transceivers also reset the Ethernet/external UART
+ temp = readw(PBC_BASE + PBC_BCTRL1);
+
+ writew(0x8023, PBC_BASE + PBC_BCTRL1);
+
+ for (i = 0; i < 100000; i++) {
+ }
+
+ // clear the reset, toggle the LEDs
+ writew(0xDF, PBC_BASE + PBC_BCTRL1_CLR);
+
+ for (i = 0; i < 100000; i++) {
+ }
+
+ dummy = readb(0xB4000008);
+ dummy = readb(0xB4000007);
+ dummy = readb(0xB4000008);
+ dummy = readb(0xB4000007);
+#endif
+
+#if 0
+ /* Reset interrupt status reg */
+ writew(0x1F, PBC_INT_REST);
+ writew(0x00, PBC_INT_REST);
+ writew(0xFFFF, PBC_INT_MASK);
+#endif
+ // UART1
+ //RXD
+ writel(0x0, IOMUXC_BASE_ADDR + 0x15C);
+ writel(0x4, IOMUXC_BASE_ADDR + 0x604);
+ writel(0x1C5, IOMUXC_BASE_ADDR + 0x3BC);
+
+ //TXD
+ writel(0x0, IOMUXC_BASE_ADDR + 0x160);
+ writel(0x1C5, IOMUXC_BASE_ADDR + 0x3C0);
+
+ //RTS
+ writel(0x0, IOMUXC_BASE_ADDR + 0x164);
+ writel(0x4, IOMUXC_BASE_ADDR + 0x600);
+ writel(0x1C4, IOMUXC_BASE_ADDR + 0x3C4);
+
+ //CTS
+ writel(0x0, IOMUXC_BASE_ADDR + 0x168);
+ writel(0x1C4, IOMUXC_BASE_ADDR + 0x3C8);
+}
+
+static void configure_gpio(cyg_uint32 port, cyg_uint32 pin,
+ cyg_uint32 io_select, cyg_uint32 dir)
+{
+ cyg_uint32 tmp, rnum, roffset, cfg_val;
+
+ if ((io_select & 0x200) == 0x200) {
+ rnum = (io_select >> 12) & 0xff;
+ roffset = (io_select >> 10) & 0x3;
+ cfg_val = (io_select & 0xff);
+ tmp = iomux_sw_mux_ctrl_reg_array[port][rnum];
+ tmp &= ~(0xff << (roffset * 8));
+ tmp |= (cfg_val << (roffset * 8));
+ iomux_sw_mux_ctrl_reg_array[port][rnum] = tmp;
+ }
+ if ((io_select & 0x100) == 0x100) {
+ /* Configure the direction of GPIO */
+ if (dir) {
+ *data_dir_reg_ptr_array[port] |= (1 << pin);
+ } else {
+ *data_dir_reg_ptr_array[port] &= ~(1 << pin);
+ }
+ }
+}
+
+static void configure_pad(cyg_uint32 port, cyg_uint32 reg_index, cyg_uint32 val)
+{
+ iomux_sw_mux_ctrl_reg_array[port][reg_index] = val;
+}
+
+void mxc_mmc_init(base_address)
+{
+ configure_gpio(IOMUX_SD1_CMD_PORT, IOMUX_SD1_CMD_PIN,
+ IOMUX_SD1_CMD_SEL, IOMUX_SD1_CMD_DIR);
+ configure_gpio(IOMUX_SD1_CLK_PORT, IOMUX_SD1_CLK_PIN,
+ IOMUX_SD1_CLK_SEL, IOMUX_SD1_CLK_DIR);
+ configure_gpio(IOMUX_SD1_DATA0_PORT,
+ IOMUX_SD1_DATA0_PIN, IOMUX_SD1_DATA0_SEL,
+ IOMUX_SD1_DATA0_DIR);
+ configure_gpio(IOMUX_SD1_DATA1_PORT,
+ IOMUX_SD1_DATA1_PIN, IOMUX_SD1_DATA1_SEL,
+ IOMUX_SD1_DATA1_DIR);
+ configure_gpio(IOMUX_SD1_DATA2_PORT,
+ IOMUX_SD1_DATA2_PIN, IOMUX_SD1_DATA2_SEL,
+ IOMUX_SD1_DATA2_DIR);
+ configure_gpio(IOMUX_SD1_DATA3_PORT,
+ IOMUX_SD1_DATA3_PIN, IOMUX_SD1_DATA3_SEL,
+ IOMUX_SD1_DATA3_DIR);
+
+ configure_gpio(IOMUX_SD2_DATA0_PORT,
+ IOMUX_SD2_DATA0_PIN, IOMUX_SD2_DATA0_SEL,
+ IOMUX_SD2_DATA0_DIR);
+ configure_gpio(IOMUX_SD2_DATA1_PORT,
+ IOMUX_SD2_DATA1_PIN, IOMUX_SD2_DATA1_SEL,
+ IOMUX_SD2_DATA1_DIR);
+ configure_gpio(IOMUX_SD2_DATA2_PORT,
+ IOMUX_SD2_DATA2_PIN, IOMUX_SD2_DATA2_SEL,
+ IOMUX_SD2_DATA2_DIR);
+ configure_gpio(IOMUX_SD2_DATA3_PORT,
+ IOMUX_SD2_DATA3_PIN, IOMUX_SD2_DATA3_SEL,
+ IOMUX_SD2_DATA3_DIR);
+
+ if((system_rev & 0xf) == 0x1) {
+ /* for Marley TO1.1.1, WP is not supported because of IC bug */
+ /* use default value */
+ configure_gpio(IOMUX_PAD_GPIO1_4_PORT,
+ IOMUX_PAD_GPIO1_4_PIN,
+ IOMUX_PAD_GPIO1_4_SEL_1,
+ IOMUX_PAD_GPIO1_4_DIR);
+ } else { /* for TO 1.0 */
+ configure_gpio(IOMUX_PAD_GPIO1_4_PORT,
+ IOMUX_PAD_GPIO1_4_PIN,
+ IOMUX_PAD_GPIO1_4_SEL,
+ IOMUX_PAD_GPIO1_4_DIR);
+ }
+
+ configure_gpio(IOMUX_PAD_GPIO1_5_PORT,
+ IOMUX_PAD_GPIO1_5_PIN,
+ IOMUX_PAD_GPIO1_5_SEL,
+ IOMUX_PAD_GPIO1_5_DIR);
+ configure_gpio(IOMUX_PAD_GPIO1_6_PORT,
+ IOMUX_PAD_GPIO1_6_PIN,
+ IOMUX_PAD_GPIO1_6_SEL,
+ IOMUX_PAD_GPIO1_6_DIR);
+
+ /* Configure PAD setting for MMC/SD */
+ configure_pad(1, 65, 0x0190);
+ configure_pad(1, 66, 0x00d0);
+ configure_pad(1, 67, 0x01d0);
+ configure_pad(1, 68, 0x01d0);
+ configure_pad(1, 69, 0x01d0);
+ configure_pad(1, 70, 0x01A0);
+ configure_pad(1, 73, 0x0190);
+ configure_pad(1, 74, 0x0190);
+ configure_pad(1, 75, 0x0190);
+ configure_pad(1, 76, 0x0190);
+ configure_pad(1, 146, 0x01e0);
+ configure_pad(1, 147, 0x01e0);
+ configure_pad(1, 148, 0x0005);
+}
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+typedef void code_fun(void);
+
+void board_program_new_stack(void *func)
+{
+ register CYG_ADDRESS stack_ptr asm("sp");
+ register CYG_ADDRESS old_stack asm("r4");
+ register code_fun *new_func asm("r0");
+ old_stack = stack_ptr;
+ stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
+ new_func = (code_fun*)func;
+ new_func();
+ stack_ptr = old_stack;
+}
+
+static void mx37_3stack_read_pmic_id()
+{
+ struct mxc_i2c_request rq;
+ unsigned char buf[4];
+
+ if (i2c_init(I2C2_BASE_ADDR, 170000) == 0) {
+ rq.dev_addr = 0x8;
+ rq.reg_addr = 0x7;
+ rq.reg_addr_sz = 1;
+ rq.buffer_sz = 3;
+ rq.buffer = buf;
+ i2c_xfer(1, &rq, 1);
+ if ((buf[1] == 0x41) && (buf[2] == 0xc8 || buf[2] == 0xc9)) {
+ diag_printf("PMIC is Atlas AP Lite\n");
+ system_rev |= 0x1 << PMIC_ID_OFFSET;
+ } else {
+ /* Reinitialize I2C */
+ i2c_init(I2C2_BASE_ADDR, 170000);
+ rq.dev_addr = (0x34 >> 1);
+ rq.reg_addr = 0x0;
+ rq.reg_addr_sz = 1;
+ rq.buffer_sz = 2;
+ rq.buffer = buf;
+ i2c_xfer(1, &rq, 1);
+ if ((buf[0] == 0x61) && (buf[1] == 0x43)) {
+ diag_printf("PMIC is WM8350\n");
+ } else {
+ diag_printf("Unable to read the PMIC ID, assuming Atlas AP Lite\n");
+ system_rev |= 0x1 << PMIC_ID_OFFSET;
+ }
+ }
+ } else {
+ diag_printf("Error Initializing I2C2, assuming PMIC to be Atlas AP Lite\n");
+ system_rev |= 0x1 << PMIC_ID_OFFSET;
+ }
+
+}
+
+RedBoot_init(mx37_3stack_read_pmic_id, RedBoot_INIT_PRIO(900));
--- /dev/null
+//==========================================================================
+//
+// redboot_cmds.c
+//
+// Board [platform] specific RedBoot commands
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+#include <redboot.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/plf_mmap.h>
+#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <flash_config.h>
+
+#if (REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE)
+#error REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE
+#endif
+
+RedBoot_config_option("Board specifics",
+ brd_specs,
+ ALWAYS_ENABLED,
+ true,
+ CONFIG_INT,
+ 0
+ );
+#endif //CYGSEM_REDBOOT_FLASH_CONFIG
+
+char HAL_PLATFORM_EXTRA[20] = "PASS x.x [x32 DDR]";
+
+static void runImg(int argc, char *argv[]);
+
+RedBoot_cmd("run",
+ "Run an image at a location with MMU off",
+ "[<virtual addr>]",
+ runImg
+ );
+
+void launchRunImg(unsigned long addr)
+{
+ asm volatile ("mov r12, r0;");
+ HAL_CLEAN_INVALIDATE_L2();
+ HAL_DISABLE_L2();
+ HAL_MMU_OFF();
+ asm volatile (
+ "mov r0, #0;"
+ "mov r1, r12;"
+ "mov r11, #0;"
+ "mov r12, #0;"
+ "mrs r10, cpsr;"
+ "bic r10, r10, #0xF0000000;"
+ "msr cpsr_f, r10;"
+ "mov pc, r1"
+ );
+}
+
+extern unsigned long entry_address;
+
+static void runImg(int argc,char *argv[])
+{
+ unsigned int virt_addr, phys_addr;
+
+ // Default physical entry point for Symbian
+ if (entry_address == 0xFFFFFFFF)
+ virt_addr = 0x800000;
+ else
+ virt_addr = entry_address;
+
+ if (!scan_opts(argc,argv,1,0,0,(void*)&virt_addr,
+ OPTION_ARG_TYPE_NUM, "virtual address"))
+ return;
+
+ if (entry_address != 0xFFFFFFFF)
+ diag_printf("load entry_address=0x%lx\n", entry_address);
+ HAL_VIRT_TO_PHYS_ADDRESS(virt_addr, phys_addr);
+
+ diag_printf("virt_addr=0x%x\n",virt_addr);
+ diag_printf("phys_addr=0x%x\n",phys_addr);
+
+ launchRunImg(phys_addr);
+}
+
+#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYG_HAL_STARTUP_ROMRAM)
+
+RedBoot_cmd("romupdate",
+ "Update Redboot with currently running image",
+ "",
+ romupdate
+ );
+
+extern int flash_program(void *_addr, void *_data, int len, void **err_addr);
+extern int flash_erase(void *addr, int len, void **err_addr);
+extern char *flash_errmsg(int err);
+extern unsigned char *ram_end; //ram end is where the redboot starts FIXME: use PC value
+
+#ifdef CYGPKG_IO_FLASH
+void romupdate(int argc, char *argv[])
+{
+ void *err_addr, *base_addr;
+ int stat;
+
+ if (IS_FIS_FROM_MMC() || IS_BOOTING_FROM_MMC()) {
+ diag_printf("Updating ROM in MMC/SD flash\n");
+ /* eMMC 4.3 and eSD 2.1 supported only on TO 1.1 */
+ if ((system_rev & 0xf) == 0x1) {
+ if(!emmc_set_boot_partition((cyg_uint32*)ram_end, CYGBLD_REDBOOT_MIN_IMAGE_SIZE)) {
+ /* eMMC 4.3 */
+ diag_printf("Card supports MMC-4.3, programming for boot operation.\n");
+ return;
+ } else if(!esd_set_boot_partition((cyg_uint32*)ram_end, CYGBLD_REDBOOT_MIN_IMAGE_SIZE)) {
+ /* eSD 2.1 */
+ diag_printf("Card supports SD-2.1, programming for boot operation.\n");
+ return;
+ }
+ }
+ base_addr = (void*)0;
+ /* Read the first 1K from the card */
+ mmc_data_read((cyg_uint32*)ram_end, 0x400, base_addr);
+ diag_printf("Programming Redboot to MMC/SD flash\n");
+ mmc_data_write((cyg_uint32*)ram_end, CYGBLD_REDBOOT_MIN_IMAGE_SIZE, (cyg_uint32)base_addr);
+ return;
+ } else if (IS_FIS_FROM_NAND() || IS_BOOTING_FROM_NAND()) {
+ base_addr = (void*)MXC_NAND_BASE_DUMMY;
+ diag_printf("Updating ROM in NAND flash\n");
+ } else {
+ diag_printf("romupdate not supported\n");
+ diag_printf("Use \"factive [NAND|MMC]\" to select either NAND or MMC flash\n");
+ }
+
+ // Erase area to be programmed
+ if ((stat = flash_erase((void *)base_addr,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ (void **)&err_addr)) != 0) {
+ diag_printf("Can't erase region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ return;
+ }
+ // Now program it
+ if ((stat = flash_program((void *)base_addr, (void *)ram_end,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ (void **)&err_addr)) != 0) {
+ diag_printf("Can't program region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ }
+}
+RedBoot_cmd("factive",
+ "Enable one flash media for Redboot",
+ "[NAND | MMC]",
+ factive
+ );
+
+typedef void reset_func_t(void);
+
+extern reset_func_t reset_vector;
+
+void factive(int argc, char *argv[])
+{
+ unsigned long phys_addr;
+ unsigned int *fis_addr = IRAM_BASE_ADDR;
+
+ if (argc != 2) {
+ diag_printf("Invalid factive cmd\n");
+ return;
+ }
+
+ if (strcasecmp(argv[1], "NOR") == 0) {
+ diag_printf("Not supported\n");
+ return;
+ } else if (strcasecmp(argv[1], "NAND") == 0) {
+#ifndef MXCFLASH_SELECT_NAND
+ diag_printf("Not supported\n");
+ return;
+#endif
+ *fis_addr = FROM_NAND_FLASH;
+ _mxc_boot = FROM_SDRAM;
+ } else if (strcasecmp(argv[1], "MMC") == 0) {
+#ifndef MXCFLASH_SELECT_MMC
+ diag_printf("Not supported\n");
+ return;
+#else
+ *fis_addr = FROM_MMC_FLASH;
+ _mxc_boot = FROM_SDRAM;
+#endif
+ } else {
+ diag_printf("Invalid command: %s\n", argv[1]);
+ return;
+ }
+ //HAL_VIRT_TO_PHYS_ADDRESS(ram_end, phys_addr);
+
+ launchRunImg(reset_vector);
+}
+#endif //CYGPKG_IO_FLASH
+#endif /* CYG_HAL_STARTUP_ROMRAM */
--- /dev/null
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): gthomas
+# Original data: gthomas
+# Contributors:
+# Date: 2000-05-08
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+cdl_package CYGPKG_HAL_ARM_MX37 {
+ display "Freescale SoC architecture"
+ parent CYGPKG_HAL_ARM
+ hardware
+ include_dir cyg/hal
+ define_header hal_arm_soc.h
+ description "
+ This HAL variant package provides generic
+ support for the Freescale SoC. It is also
+ necessary to select a specific target platform HAL
+ package."
+
+ implements CYGINT_HAL_ARM_ARCH_ARM9
+ implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+
+ # Let the architectural HAL see this variant's interrupts file -
+ # the SoC has no variation between targets here.
+ define_proc {
+ puts $::cdl_header "#define CYGBLD_HAL_VAR_INTS_H <cyg/hal/hal_var_ints.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H"
+
+ puts $::cdl_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 1000000"
+ }
+
+ compile soc_diag.c soc_misc.c
+ compile -library=libextras.a cmds.c
+
+ cdl_option CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK {
+ display "Processor clock rate"
+ active_if { CYG_HAL_STARTUP == "ROM" }
+ flavor data
+ legal_values 150000 200000
+ default_value { CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT ?
+ CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT : 150000}
+ description "
+ The processor can run at various frequencies.
+ These values are expressed in KHz. Note that there are
+ several steppings of the rated to run at different
+ maximum frequencies. Check the specs to make sure that your
+ particular processor can run at the rate you select here."
+ }
+
+ # Real-time clock/counter specifics
+ cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+ display "Real-time clock constants"
+ flavor none
+ no_define
+
+ cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+ display "Real-time clock numerator"
+ flavor data
+ calculated 1000000000
+ }
+ cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+ display "Real-time clock denominator"
+ flavor data
+ default_value 100
+ description "
+ This option selects the heartbeat rate for the real-time clock.
+ The rate is specified in ticks per second. Change this value
+ with caution - too high and your system will become saturated
+ just handling clock interrupts, too low and some operations
+ such as thread scheduling may become sluggish."
+ }
+ cdl_option CYGNUM_HAL_RTC_PERIOD {
+ display "Real-time clock period"
+ flavor data
+ calculated (3686400/CYGNUM_HAL_RTC_DENOMINATOR) ;# Clock for OS Timer is 3.6864MHz
+ }
+ }
+
+ # Control over hardware layout.
+ cdl_interface CYGHWR_HAL_ARM_SOC_UART1 {
+ display "UART1 available as diagnostic/debug channel"
+ description "
+ The chip has multiple serial channels which may be
+ used for different things on different platforms. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_SOC_UART2 {
+ display "UART2 available as diagnostic/debug channel"
+ description "
+ The chip has multiple serial channels which may be
+ used for different things on different platforms. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_SOC_UART3 {
+ display "UART3 available as diagnostic/debug channel"
+ description "
+ The chip has multiple serial channels which may be
+ used for different things on different platforms. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_SOC_UART4 {
+ display "UART4 available as diagnostic/debug channel"
+ description "
+ The chip has multiple serial channels which may be
+ used for different things on different platforms. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_SOC_UART5 {
+ display "UART5 available as diagnostic/debug channel"
+ description "
+ The chip has multiple serial channels which may be
+ used for different things on different platforms. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+}
--- /dev/null
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+
+//=============================================================================
+//
+// hal_cache.h
+//
+// HAL cache control API
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
+
+//-----------------------------------------------------------------------------
+// Cache dimensions
+
+// Data cache
+#define HAL_DCACHE_SIZE 0x4000 // 16KB Size of data cache in bytes
+#define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
+#define HAL_DCACHE_WAYS 64 // Associativity of the cache
+
+// Instruction cache
+#define HAL_ICACHE_SIZE 0x4000 // Size of cache in bytes
+#define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
+#define HAL_ICACHE_WAYS 64 // Associativity of the cache
+
+#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE / (HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
+#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE / (HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
+
+#define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
+#define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x20
+#define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x100
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE_L1() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mrc p15, 0, r1, c1, c0, 0;" \
+ "orr r1, r1, #0x0007;" /* enable DCache (also ensures */ \
+ /* the MMU, alignment faults, and */ \
+ "mcr p15, 0, r1, c1, c0, 0" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE_L1() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mov r1, #0;" \
+ "mcr p15, 0, r1, c7, c6, 0;" /* clear data cache */ \
+ "mrc p15, 0, r1, c1, c0, 0;" \
+ "bic r1, r1, #0x0004;" /* disable DCache */ \
+ /* but not MMU and alignment faults */ \
+ "mcr p15, 0, r1, c1, c0, 0" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL_L1() \
+CYG_MACRO_START /* this macro can discard dirty cache lines. */ \
+ asm volatile ( \
+ "mov r0, #0;" \
+ "mcr p15, 0, r0, c7, c6, 0;" /* flush d-cache */ \
+ "mcr p15, 0, r0, c8, c7, 0;" /* flush i+d-TLBs */ \
+ : \
+ : \
+ : "r0","memory" /* clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Synchronize the contents of the cache with memory.
+// using ARM9's defined(CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX)
+#define HAL_DCACHE_SYNC_L1() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "mov r0, #0x0;" \
+ "mcr p15, 0, r0, c7, c14, 0;" /* clean, invalidate Dcache*/ \
+ "mcr p15, 0, r0, c7, c10, 4;" /* drain the write buffer */ \
+ "mcr p15, 0, r0, c7, c10, 5;" /* data memory barrier */ \
+ : \
+ : \
+ : "r0" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Query the state of the data cache
+#define HAL_DCACHE_IS_ENABLED(_state_) \
+CYG_MACRO_START \
+ register int reg; \
+ asm volatile ( \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "mrc p15, 0, %0, c1, c0, 0;" \
+ : "=r"(reg) \
+ : \
+ ); \
+ (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \
+CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE_L1() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mrc p15, 0, r1, c1, c0, 0;" \
+ "orr r1, r1, #0x1000;" \
+ "orr r1, r1, #0x0003;" /* enable ICache (also ensures */ \
+ /* that MMU and alignment faults */ \
+ /* are enabled) */ \
+ "mcr p15, 0, r1, c1, c0, 0" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Query the state of the instruction cache
+#define HAL_ICACHE_IS_ENABLED(_state_) \
+CYG_MACRO_START \
+ register cyg_uint32 reg; \
+ asm volatile ( \
+ "mrc p15, 0, %0, c1, c0, 0" \
+ : "=r"(reg) \
+ : \
+ ); \
+ \
+ (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \
+CYG_MACRO_END
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE_L1() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mrc p15, 0, r1, c1, c0, 0;" \
+ "bic r1, r1, #0x1000;" /* disable ICache (but not MMU, etc) */ \
+ "mcr p15, 0, r1, c1, c0, 0;" \
+ "mov r1, #0;" \
+ "mcr p15, 0, r1, c7, c5, 0;" /* flush ICache */ \
+ "mcr p15, 0, r1, c7, c5, 4;" /* flush prefetch buffer */ \
+ "nop;" /* next few instructions may be via cache */ \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL_L1() \
+CYG_MACRO_START \
+ /* this macro can discard dirty cache lines (N/A for ICache) */ \
+ asm volatile ( \
+ "mov r1, #0;" \
+ "mcr p15, 0, r1, c7, c5, 0;" /* flush ICache */ \
+ "mcr p15, 0, r1, c8, c5, 0;" /* flush ITLB only */ \
+ "mcr p15, 0, r1, c7, c5, 4;" /* flush prefetch buffer */ \
+ "nop;" /* next few instructions may be via cache */ \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Synchronize the contents of the cache with memory.
+// (which includes flushing out pending writes)
+#define HAL_ICACHE_SYNC() \
+CYG_MACRO_START \
+ HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
+ HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
+CYG_MACRO_END
+
+// Query the state of the L2 cache
+#define HAL_L2CACHE_IS_ENABLED(_state_) \
+ (_state_ = readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1)
+
+#ifdef L2CC_ENABLED
+
+#define HAL_ENABLE_L2() \
+{ \
+ writel(1, L2CC_BASE_ADDR + L2_CACHE_CTL_REG); \
+}
+
+#define HAL_DISABLE_L2() \
+{ \
+ writel(0, L2CC_BASE_ADDR + L2_CACHE_CTL_REG); \
+}
+
+#define HAL_SYNC_L2() \
+{ \
+ if ((readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1) != 0) { \
+ writel(0, L2CC_BASE_ADDR + L2_CACHE_SYNC_REG); \
+ while ((readl(L2CC_BASE_ADDR + L2_CACHE_SYNC_REG) & 1) == 1); \
+ } \
+}
+
+#define HAL_INVALIDATE_L2() \
+{ \
+ if ((readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1) != 0) { \
+ writel(0xFF, L2CC_BASE_ADDR + L2_CACHE_INV_WAY_REG); \
+ while ((readl(L2CC_BASE_ADDR + L2_CACHE_INV_WAY_REG) & 0xFF) != 0); \
+ HAL_SYNC_L2(); \
+ } \
+}
+ \
+#define HAL_CLEAN_INVALIDATE_L2() \
+{ \
+ if ((readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1) != 0) { \
+ writel(0xFF, L2CC_BASE_ADDR + L2_CACHE_CLEAN_INV_WAY_REG); \
+ while ((readl(L2CC_BASE_ADDR + L2_CACHE_CLEAN_INV_WAY_REG) & 0xFF) != 0);\
+ HAL_SYNC_L2(); \
+ } \
+}
+
+#else //L2CC_ENABLED
+
+#define HAL_ENABLE_L2()
+#define HAL_DISABLE_L2()
+#define HAL_INVALIDATE_L2()
+#define HAL_CLEAN_INVALIDATE_L2()
+#define HAL_SYNC_L2()
+#endif //L2CC_ENABLED
+
+/*********************** Exported macros *******************/
+
+#define HAL_DCACHE_ENABLE() { \
+ HAL_DCACHE_ENABLE_L1(); \
+ HAL_ENABLE_L2(); \
+}
+
+#define HAL_DCACHE_DISABLE() { \
+ HAL_DCACHE_DISABLE_L1(); \
+ HAL_DISABLE_L2(); \
+}
+
+#define HAL_DCACHE_INVALIDATE_ALL() { \
+ HAL_DCACHE_INVALIDATE_ALL_L1(); \
+ HAL_CLEAN_INVALIDATE_L2(); \
+}
+
+#define HAL_DCACHE_SYNC() { \
+ HAL_DCACHE_SYNC_L1(); \
+ /* don't just call HAL_SYNC_L2() */ \
+ HAL_CLEAN_INVALIDATE_L2(); \
+}
+
+#define HAL_ICACHE_INVALIDATE_ALL() { \
+ HAL_ICACHE_INVALIDATE_ALL_L1(); \
+ HAL_CLEAN_INVALIDATE_L2(); \
+}
+
+#define HAL_ICACHE_DISABLE() { \
+ HAL_ICACHE_DISABLE_L1(); \
+}
+
+#define HAL_ICACHE_ENABLE() { \
+ HAL_ICACHE_ENABLE_L1(); \
+}
+
+#endif // ifndef CYGONCE_HAL_CACHE_H
+// End of hal_cache.h
--- /dev/null
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+
+/*=============================================================================
+//
+// hal_diag.h
+//
+// HAL Support for Kernel Diagnostic Routines
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+#include <cyg/hal/hal_if.h>
+
+#define HAL_DIAG_INIT() hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
+
+#else // everything by steam
+
+/*---------------------------------------------------------------------------*/
+/* functions implemented in hal_diag.c */
+
+externC void hal_diag_init(void);
+externC void hal_diag_write_char(char c);
+externC void hal_diag_read_char(char *c);
+
+/*---------------------------------------------------------------------------*/
+
+#define HAL_DIAG_INIT() hal_diag_init()
+
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_)
+
+#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_)
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
+// LED
+
+externC void hal_diag_led(int n);
+
+/*---------------------------------------------------------------------------*/
+/* end of hal_diag.h */
+#endif /* CYGONCE_HAL_DIAG_H */
--- /dev/null
+#ifndef CYGONCE_HAL_MM_H
+#define CYGONCE_HAL_MM_H
+
+//=============================================================================
+//
+// hal_mm.h
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+// -------------------------------------------------------------------------
+// MMU initialization:
+//
+// These structures are laid down in memory to define the translation
+// table.
+//
+
+/*
+ * Translation Table Base Bit Masks
+ */
+#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
+
+/*
+ * Domain Access Control Bit Masks
+ */
+#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2)
+
+struct ARM_MMU_FIRST_LEVEL_FAULT {
+ unsigned int id : 2;
+ unsigned int sbz : 30;
+};
+
+#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
+
+struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
+ unsigned int id : 2;
+ unsigned int imp : 2;
+ unsigned int domain : 4;
+ unsigned int sbz : 1;
+ unsigned int base_address : 23;
+};
+
+#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
+
+struct ARM_MMU_FIRST_LEVEL_SECTION {
+ unsigned int id : 2;
+ unsigned int b : 1;
+ unsigned int c : 1;
+ unsigned int imp : 1;
+ unsigned int domain : 4;
+ unsigned int sbz0 : 1;
+ unsigned int ap : 2;
+ unsigned int sbz1 : 8;
+ unsigned int base_address : 12;
+};
+
+#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
+
+struct ARM_MMU_FIRST_LEVEL_RESERVED {
+ unsigned int id : 2;
+ unsigned int sbz : 30;
+};
+
+#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
+
+#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
+ (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
+
+#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
+
+#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
+ cacheable, bufferable, perm) \
+ CYG_MACRO_START \
+ register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
+ \
+ desc.word = 0; \
+ desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
+ desc.section.domain = 0; \
+ desc.section.c = (cacheable); \
+ desc.section.b = (bufferable); \
+ desc.section.ap = (perm); \
+ desc.section.base_address = (actual_base); \
+ *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
+ = desc.word; \
+ CYG_MACRO_END
+
+#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \
+ { \
+ int i; int j = abase; int k = vbase; \
+ for (i = size; i > 0 ; i--,j++,k++) { \
+ ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
+ } \
+ }
+
+union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
+ unsigned long word;
+ struct ARM_MMU_FIRST_LEVEL_FAULT fault;
+ struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
+ struct ARM_MMU_FIRST_LEVEL_SECTION section;
+ struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
+};
+
+#define ARM_UNCACHEABLE 0
+#define ARM_CACHEABLE 1
+#define ARM_UNBUFFERABLE 0
+#define ARM_BUFFERABLE 1
+
+#define ARM_ACCESS_PERM_NONE_NONE 0
+#define ARM_ACCESS_PERM_RO_NONE 0
+#define ARM_ACCESS_PERM_RO_RO 0
+#define ARM_ACCESS_PERM_RW_NONE 1
+#define ARM_ACCESS_PERM_RW_RO 2
+#define ARM_ACCESS_PERM_RW_RW 3
+
+/*
+ * Initialization for the Domain Access Control Register
+ */
+#define ARM_ACCESS_DACR_DEFAULT ( \
+ ARM_ACCESS_TYPE_MANAGER(0) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(1) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(2) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(3) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(4) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(5) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(6) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(7) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(8) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(9) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(10) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(11) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(12) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(13) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(14) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(15) )
+
+// ------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_MM_H
+// End of hal_mm.h
+
+
+
+
+
--- /dev/null
+//==========================================================================
+//
+// hal_soc.h
+//
+// SoC chip definitions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#ifndef __HAL_SOC_H__
+#define __HAL_SOC_H__
+
+#ifdef __ASSEMBLER__
+
+#define REG8_VAL(a) (a)
+#define REG16_VAL(a) (a)
+#define REG32_VAL(a) (a)
+
+#define REG8_PTR(a) (a)
+#define REG16_PTR(a) (a)
+#define REG32_PTR(a) (a)
+
+#else /* __ASSEMBLER__ */
+
+extern char HAL_PLATFORM_EXTRA[];
+#define REG8_VAL(a) ((unsigned char)(a))
+#define REG16_VAL(a) ((unsigned short)(a))
+#define REG32_VAL(a) ((unsigned int)(a))
+
+#define REG8_PTR(a) ((volatile unsigned char *)(a))
+#define REG16_PTR(a) ((volatile unsigned short *)(a))
+#define REG32_PTR(a) ((volatile unsigned int *)(a))
+#define readb(a) (*(volatile unsigned char *)(a))
+#define readw(a) (*(volatile unsigned short *)(a))
+#define readl(a) (*(volatile unsigned int *)(a))
+#define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
+#define writew(v,a) (*(volatile unsigned short *)(a) = (v))
+#define writel(v,a) (*(volatile unsigned int *)(a) = (v))
+
+#endif /* __ASSEMBLER__ */
+
+/*
+ * Default Memory Layout Definitions
+ */
+
+#define L2CC_BASE_ADDR 0xB0000000
+
+#define IRAM_BASE_ADDR 0x10000000
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR 0xC3F00000
+#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
+#define MAX_BASE_ADDR 0xC3F80000
+#define GPIO1_BASE_ADDR 0xC3F84000
+#define GPIO2_BASE_ADDR 0xC3F88000
+#define GPIO3_BASE_ADDR 0xC3F8C000
+#define KPP_BASE_ADDR 0xC3F94000
+#define WDOG1_BASE_ADDR 0xC3F98000
+#define WDOG_BASE_ADDR WDOG1_BASE_ADDR
+#define WDOG2_BASE_ADDR 0xC3F9C000
+#define GPT1_BASE_ADDR 0xC3FA0000
+#define RTC_BASE_ADDR 0xC3FA4000
+#define IOMUXC_BASE_ADDR 0xC3FA8000
+#define IIM_BASE_ADDR 0xC3FAC000
+#define FEC_BASE_ADDR 0xC3FE8000
+
+/*
+ * SPBA
+ */
+#define MMC_SDHC1_BASE_ADDR 0xC0004000
+#define ESDHC1_REG_BASE MMC_SDHC1_BASE_ADDR
+#define MMC_SDHC2_BASE_ADDR 0xC0008000
+#define UART3_BASE_ADDR 0xC000C000
+#define CSPI2_BASE_ADDR 0xC0010000
+#define SSI2_BASE_ADDR 0xC0014000
+#define ATA_DMA_BASE_ADDR 0xC0034000
+#define SPBA_CTRL_BASE_ADDR 0xC003C000
+
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR 0xE3F00000
+#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
+#define PLL1_BASE_ADDR 0xE3F80000
+#define PLL2_BASE_ADDR 0xE3F84000
+#define PLL3_BASE_ADDR 0xE3F88000
+#define CCM_BASE_ADDR 0xE3F8C000
+#define SRC_BASE_ADDR 0xE3F94000
+#define EPIT1_BASE_ADDR 0xE3F98000
+#define EPIT2_BASE_ADDR 0xE3F9C000
+#define CSPI3_BASE_ADDR 0xE3FA8000
+#define CSPI1_BASE_ADDR 0xE3FAC000
+#define UART1_BASE_ADDR 0xE3FB0000
+#define UART2_BASE_ADDR 0xE3FBC000
+#define I2C3_BASE_ADDR 0xE3FC0000
+#define I2C2_BASE_ADDR 0xE3FC4000
+#define I2C_BASE_ADDR 0xE3FC8000
+#define SSI1_BASE_ADDR 0xE3FCC000
+#define AUDMUX_BASE 0xE3FD0000
+
+#define GPC_BASE_ADDR 0xE3F90000
+#define GPC_CNTR_REG (GPC_BASE_ADDR + 0)
+#define GPC_PGR_REG (GPC_BASE_ADDR + 4)
+#define GPC_VCR_REG (GPC_BASE_ADDR + 8)
+
+#define PGC_BASE_VPU (GPC_BASE_ADDR + 0x0240)
+#define PGC_BASE_IPU (GPC_BASE_ADDR + 0x0220)
+#define GPC_PGR (GPC_BASE_ADDR + 0x000)
+#define SRPGCR_ARM (GPC_BASE_ADDR + 0x02A0 + 0x0000)
+#define SRPGCR_EMI (GPC_BASE_ADDR + 0x0280 + 0x0000)
+#define PGC_PGCR_VPU (PGC_BASE_VPU + 0x0000)
+#define PGC_PGCR_IPU (PGC_BASE_IPU + 0x0000)
+
+#define PLATFORM_BASE_ADDR 0xB0404000
+#define PLATFORM_LPC_REG (PLATFORM_BASE_ADDR + 0x14)
+
+/*
+ * Interrupt controller
+ */
+#define INTC_BASE_ADDR 0xB0800000
+
+/*
+ * NAND, SDRAM, WEIM, M4IF, EMI controllers
+ */
+#define NFC_IP_BASE 0xE3FDB000
+#define ESDCTL_BASE 0xE3FD9000
+#define WEIM_BASE_ADDR 0xE3FDA000
+
+#define WEIM_CTRL_CS0 WEIM_BASE_ADDR
+#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x18)
+#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x30)
+#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x48)
+#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x60)
+#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x78)
+#define M4IF_BASE 0xE3FD8000
+
+/*
+ * Memory regions and CS
+ */
+#define CSD0_BASE_ADDR 0x40000000
+#define CSD1_BASE_ADDR 0x50000000
+#define CS0_BASE_ADDR 0x60000000
+#define CS1_BASE_ADDR 0x68000000
+#define CS2_BASE_ADDR 0x70000000
+
+/*
+ * IRQ Controller Register Definitions.
+ */
+#define INTC_NIMASK REG32_PTR(INTC_BASE_ADDR + (0x04))
+#define INTC_INTTYPEH REG32_PTR(INTC_BASE_ADDR + (0x18))
+#define INTC_INTTYPEL REG32_PTR(INTC_BASE_ADDR + (0x1C))
+
+/* M4IF */
+#define M4IF_FBPM0 0x40
+#define M4IF_FIDBP 0x48
+
+/* L210 */
+#define L2_CACHE_LINE_SIZE 32
+#define L2_CACHE_CTL_REG 0x100
+#define L2_CACHE_AUX_CTL_REG 0x104
+#define L2_CACHE_SYNC_REG 0x730
+#define L2_CACHE_INV_LINE_REG 0x770
+#define L2_CACHE_INV_WAY_REG 0x77C
+#define L2_CACHE_CLEAN_LINE_PA_REG 0x7B0
+#define L2_CACHE_CLEAN_LINE_WAY_REG 0x7B8
+#define L2_CACHE_CLEAN_WAY_REG 0x7BC
+#define L2_CACHE_CLEAN_INV_LINE_PA_REG 0x7F0
+#define L2_CACHE_CLEAN_INV_LINE_WAY_REG 0x7F8
+#define L2_CACHE_CLEAN_INV_WAY_REG 0x7FC
+
+/* CCM */
+#define CLKCTL_CCMR 0x00
+#define CLKCTL_PDR0 0x04
+#define CLKCTL_PDR1 0x08
+
+#define CLKCTL_CCSR 0x0C
+#define CLKCTL_CACRR 0x10
+#define CLKCTL_CBCDR2 0x18
+#define CLKCTL_CBCDR3 0x1C
+#define CLKCTL_CBCDR4 0x20
+#define CLKCTL_CBCDR5 0x24
+#define CLKCTL_CBCDR6 0x28
+#define CLKCTL_CBCDR7 0x2C
+#define CLKCTL_CAMR 0x30
+#define CLKCTL_PDR2 0x64
+#define CLKCTL_RCSR 0x0C
+#define CLKCTL_MPCTL 0x10
+#define CLKCTL_UPCTL 0x14
+#define CLKCTL_SPCTL 0x18
+#define CLKCTL_COSR 0x1C
+#define CLKCTL_CSCMR1 0x34
+#define CLKCTL_CSCDR1 0x3C
+#define CLKCTL_CS1CDR 0x40
+#define CLKCTL_CS2CDR 0x44
+#define CLKCTL_CSCDR2 0x60
+#define CLKCTL_CDCR 0x6C
+#define CLKCTL_CCOSR 0x80
+
+#define FREQ_24MHZ 24000000
+#define FREQ_32768HZ (32768 * 1024)
+#define FREQ_38400HZ (38400 * 1024)
+#define FREQ_32000HZ (32000 * 1024)
+#define PLL_REF_CLK FREQ_24MHZ
+//#define PLL_REF_CLK FREQ_32768HZ
+//#define PLL_REF_CLK FREQ_32000HZ
+
+/* WEIM registers */
+#define CSGCR1 0x00
+#define CSGCR2 0x04
+#define CSRCR1 0x08
+#define CSRCR2 0x0C
+#define CSWCR1 0x10
+
+/* ESDCTL */
+#define ESDCTL_ESDCTL0 0x00
+#define ESDCTL_ESDCFG0 0x04
+#define ESDCTL_ESDCTL1 0x08
+#define ESDCTL_ESDCFG1 0x0C
+#define ESDCTL_ESDMISC 0x10
+#define ESDCTL_ESDSCR 0x14
+#define ESDCTL_ESDCDLY1 0x20
+#define ESDCTL_ESDCDLY2 0x24
+#define ESDCTL_ESDCDLY3 0x28
+#define ESDCTL_ESDCDLY4 0x2C
+#define ESDCTL_ESDCDLY5 0x30
+#define ESDCTL_ESDCDLYGD 0x34
+
+/* DPLL */
+#define PLL_DP_CTL 0x00
+#define PLL_DP_CONFIG 0x04
+#define PLL_DP_OP 0x08
+#define PLL_DP_MFD 0x0C
+#define PLL_DP_MFN 0x10
+#define PLL_DP_MFNMINUS 0x14
+#define PLL_DP_MFNPLUS 0x18
+#define PLL_DP_HFS_OP 0x1C
+#define PLL_DP_HFS_MFD 0x20
+#define PLL_DP_HFS_MFN 0x24
+#define PLL_DP_TOGC 0x28
+#define PLL_DP_DESTAT 0x2C
+
+#define CHIP_REV_1_0 0x0 /* PASS 1.0 */
+#define CHIP_REV_1_1 0x1 /* PASS 1.1 */
+#define CHIP_REV_2_0 0x2 /* PASS 2.0 */
+#define CHIP_LATEST CHIP_REV_1_1
+
+#define IIM_STAT_OFF 0x00
+#define IIM_STAT_BUSY (1 << 7)
+#define IIM_STAT_PRGD (1 << 1)
+#define IIM_STAT_SNSD (1 << 0)
+#define IIM_STATM_OFF 0x04
+#define IIM_ERR_OFF 0x08
+#define IIM_ERR_PRGE (1 << 7)
+#define IIM_ERR_WPE (1 << 6)
+#define IIM_ERR_OPE (1 << 5)
+#define IIM_ERR_RPE (1 << 4)
+#define IIM_ERR_WLRE (1 << 3)
+#define IIM_ERR_SNSE (1 << 2)
+#define IIM_ERR_PARITYE (1 << 1)
+#define IIM_EMASK_OFF 0x0C
+#define IIM_FCTL_OFF 0x10
+#define IIM_UA_OFF 0x14
+#define IIM_LA_OFF 0x18
+#define IIM_SDAT_OFF 0x1C
+#define IIM_PREV_OFF 0x20
+#define IIM_SREV_OFF 0x24
+#define IIM_PREG_P_OFF 0x28
+#define IIM_SCS0_OFF 0x2C
+#define IIM_SCS1_P_OFF 0x30
+#define IIM_SCS2_OFF 0x34
+#define IIM_SCS3_P_OFF 0x38
+
+#define EPIT_BASE_ADDR EPIT1_BASE_ADDR
+#define EPITCR 0x00
+#define EPITSR 0x04
+#define EPITLR 0x08
+#define EPITCMPR 0x0C
+#define EPITCNR 0x10
+
+/*defines iomux for mx37*/
+#define IOMUX_SD1_CMD_PORT 0
+#define IOMUX_SD1_CMD_PIN 32
+#define IOMUX_SD1_CMD_SEL (0x200 | 0x10 | (51<<12))
+#define IOMUX_SD1_CMD_DIR (0xFF)
+
+#define IOMUX_SD1_CLK_PORT 0
+#define IOMUX_SD1_CLK_PIN 32
+#define IOMUX_SD1_CLK_SEL (0x200 |(52<<12))
+#define IOMUX_SD1_CLK_DIR (0xFF)
+
+#define IOMUX_SD1_DATA0_PORT 0
+#define IOMUX_SD1_DATA0_PIN 32
+#define IOMUX_SD1_DATA0_SEL (0x200 | (53<<12))
+#define IOMUX_SD1_DATA0_DIR (0xFF)
+
+#define IOMUX_SD1_DATA1_PORT 0
+#define IOMUX_SD1_DATA1_PIN 32
+#define IOMUX_SD1_DATA1_SEL (0x200 | (54<<12))
+#define IOMUX_SD1_DATA1_DIR (0xFF)
+
+#define IOMUX_SD1_DATA2_PORT 0
+#define IOMUX_SD1_DATA2_PIN 32
+#define IOMUX_SD1_DATA2_SEL (0x200 | (55<<12))
+#define IOMUX_SD1_DATA2_DIR (0xFF)
+
+#define IOMUX_SD1_DATA3_PORT 0
+#define IOMUX_SD1_DATA3_PIN 32
+#define IOMUX_SD1_DATA3_SEL (0x200 | (56<<12))
+#define IOMUX_SD1_DATA3_DIR (0xFF)
+
+#define IOMUX_SD2_DATA0_PORT 0
+#define IOMUX_SD2_DATA0_PIN 32
+#define IOMUX_SD2_DATA0_SEL (0x200 | 0x4 | (59<<12))
+#define IOMUX_SD2_DATA0_DIR (0xFF)
+#define IOMUX_SD2_DATA1_PORT 0
+#define IOMUX_SD2_DATA1_PIN 32
+#define IOMUX_SD2_DATA1_SEL (0x200 | 0x4 | (60<<12))
+#define IOMUX_SD2_DATA1_DIR (0xFF)
+#define IOMUX_SD2_DATA2_PORT 0
+#define IOMUX_SD2_DATA2_PIN 32
+#define IOMUX_SD2_DATA2_SEL (0x200 | 0x4 | (61<<12))
+#define IOMUX_SD2_DATA2_DIR (0xFF)
+#define IOMUX_SD2_DATA3_PORT 0
+#define IOMUX_SD2_DATA3_PIN 32
+#define IOMUX_SD2_DATA3_SEL (0x200 | 0x4 | (62<<12))
+#define IOMUX_SD2_DATA3_DIR (0xFF)
+
+#define IOMUX_PAD_GPIO1_4_PORT 0
+#define IOMUX_PAD_GPIO1_4_PIN 32
+#define IOMUX_PAD_GPIO1_4_SEL (0x200 | 0x6 | (134<<12))
+#define IOMUX_PAD_GPIO1_4_SEL_1 (0x200 | 0x0 | (134<<12))
+#define IOMUX_PAD_GPIO1_4_DIR (0xFF)
+
+#define IOMUX_PAD_GPIO1_5_PORT 0
+#define IOMUX_PAD_GPIO1_5_PIN 32
+#define IOMUX_PAD_GPIO1_5_SEL (0x200 | 0x6 | (135<<12))
+#define IOMUX_PAD_GPIO1_5_DIR (0xFF)
+
+#define IOMUX_PAD_GPIO1_6_PORT 0
+#define IOMUX_PAD_GPIO1_6_PIN 32
+#define IOMUX_PAD_GPIO1_6_SEL (0x200 | 0x6 | (136<<12))
+#define IOMUX_PAD_GPIO1_6_DIR (0xFF)
+
+#define GPT_BASE_ADDR GPT1_BASE_ADDR
+#define GPTCR 0x00
+#define GPTPR 0x04
+#define GPTSR 0x08
+#define GPTIR 0x0C
+#define GPTOCR1 0x10
+#define GPTOCR2 0x14
+#define GPTOCR3 0x18
+#define GPTICR1 0x1C
+#define GPTICR2 0x20
+#define GPTCNT 0x24
+
+/* Assuming 26MHz input clock */
+/* PD MFD MFI MFN */
+#define MPCTL_PARAM_208 (((2-1) << 26) + ((1 -1) << 16) + (8 << 10) + (0 << 0))
+#define MPCTL_PARAM_399 (((1-1) << 26) + ((52-1) << 16) + (7 << 10) + (35 << 0))
+#define MPCTL_PARAM_532 (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
+#define MPCTL_PARAM_665 (((1-1) << 26) + ((52-1) << 16) + (12 << 10) + (41 << 0))
+#define MPCTL_PARAM_532_27 (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0))
+
+/* UPCTL PD MFD MFI MFN */
+#define UPCTL_PARAM_288 (((1-1) << 26) + ((13-1) << 16) + (5 << 10) + (7 << 0))
+#define UPCTL_PARAM_240 (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
+#define UPCTL_PARAM_240_27 (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0))
+
+/* PDR0 */
+#define PDR0_208_104_52 0xFF870D48 /* ARM=208MHz, HCLK=104MHz, IPG=52MHz */
+#define PDR0_399_66_66 0xFF872B28 /* ARM=399MHz, HCLK=IPG=66.5MHz */
+#define PDR0_399_133_66 0xFF871650 /* ARM=399MHz, HCLK=133MHz, IPG=66.5MHz */
+#define PDR0_532_133_66 0xFF871D58 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
+#define PDR0_665_83_42 0xFF873B78 /* ARM=665MHz, HCLK=83MHz, IPG=42MHz */
+#define PDR0_665_133_66 0xFF872560 /* ARM=665MHz, HCLK=133MHz, IPG=66MHz */
+
+//#define BARKER_CODE_SWAP_LOC 0x404
+#define BARKER_CODE_VAL 0xB1
+#define NFC_V2_1
+#define NFC_BASE 0x7FFF0000
+#define NAND_REG_BASE (NFC_BASE + 0x1E00)
+
+#define NAND_ADD_CMD_REG (NAND_REG_BASE + 0x00)
+
+#define NAND_CONFIGURATION1_REG (NAND_REG_BASE + 0x04)
+ #define NAND_CONFIGURATION1_NFC_RST (1 << 2)
+ #define NAND_CONFIGURATION1_NF_CE (1 << 1)
+ #define NAND_CONFIGURATION1_SP_EN (1 << 0)
+
+#define NAND_ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x08)
+
+#define NAND_LAUNCH_REG (NAND_REG_BASE + 0x0C)
+ #define NAND_LAUNCH_FCMD (1 << 0)
+ #define NAND_LAUNCH_FADD (1 << 1)
+ #define NAND_LAUNCH_FDI (1 << 2)
+
+
+#define NFC_WR_PROT_REG (NFC_IP_BASE + 0x00)
+ #define NFC_WR_PROT_CS0 (0 << 20)
+ #define NFC_WR_PROT_BLS_UNLOCK (2 << 16)
+ #define NFC_WR_PROT_WPC (4 << 0)
+
+#define UNLOCK_BLK_ADD0_REG (NFC_IP_BASE + 0x04)
+
+#define UNLOCK_BLK_ADD1_REG (NFC_IP_BASE + 0x08)
+
+#define UNLOCK_BLK_ADD2_REG (NFC_IP_BASE + 0x0C)
+
+#define UNLOCK_BLK_ADD3_REG (NFC_IP_BASE + 0x10)
+
+#define NFC_FLASH_CONFIG2_REG (NFC_IP_BASE + 0x14)
+ #define NFC_FLASH_CONFIG2_EDC0 (0 << 9)
+ #define NFC_FLASH_CONFIG2_EDC1 (1 << 9)
+ #define NFC_FLASH_CONFIG2_EDC2 (2 << 9)
+ #define NFC_FLASH_CONFIG2_EDC3 (3 << 9)
+ #define NFC_FLASH_CONFIG2_EDC4 (4 << 9)
+ #define NFC_FLASH_CONFIG2_EDC5 (5 << 9)
+ #define NFC_FLASH_CONFIG2_EDC6 (6 << 9)
+ #define NFC_FLASH_CONFIG2_EDC7 (7 << 9)
+ #define NFC_FLASH_CONFIG2_PPB_32 (0 << 7)
+ #define NFC_FLASH_CONFIG2_PPB_64 (1 << 7)
+ #define NFC_FLASH_CONFIG2_PPB_128 (2 << 7)
+ #define NFC_FLASH_CONFIG2_PPB_256 (3 << 7)
+ #define NFC_FLASH_CONFIG2_INT_MSK (1 << 4)
+ #define NFC_FLASH_CONFIG2_ECC_EN (1 << 3)
+ #define NFC_FLASH_CONFIG2_SYM (1 << 2)
+
+#define NFC_IPC_REG (NFC_IP_BASE + 0x18)
+ #define NFC_IPC_INT (1 << 31)
+ #define NFC_IPC_LPS (1 << 30)
+ #define NFC_IPC_RB_B (1 << 29)
+ #define NFC_IPC_CACK (1 << 1)
+ #define NFC_IPC_CREQ (1 << 0)
+#define NFC_AXI_ERR_ADD_REG (NFC_IP_BASE + 0x1C)
+
+#define MXC_NAND_BASE_DUMMY 0x00000000
+#define MXC_MMC_BASE_DUMMY 0x00000000
+
+#define FROM_SDRAM 0x00000000
+#define FROM_NAND_FLASH 0x10000000
+#define FROM_NOR_FLASH 0x20000000
+#define FROM_MMC_FLASH 0x40000000
+#define FROM_SPI_NOR_FLASH 0x80000000
+
+#define IS_BOOTING_FROM_NAND() (_mxc_boot == FROM_NAND_FLASH)
+// No NOR flash is supported under MX37 for booting
+#define IS_BOOTING_FROM_NOR() (0)
+#define IS_BOOTING_FROM_SPI_NOR() (0)
+#define IS_BOOTING_FROM_SDRAM() (_mxc_boot == FROM_SDRAM)
+#define IS_BOOTING_FROM_MMC() (_mxc_boot == FROM_MMC_FLASH)
+
+#ifndef MXCFLASH_SELECT_NAND
+#define IS_FIS_FROM_NAND() 0
+#else
+#define IS_FIS_FROM_NAND() (_mxc_fis == FROM_NAND_FLASH)
+#endif
+
+#ifndef MXCFLASH_SELECT_MMC
+#define IS_FIS_FROM_MMC() 0
+#else
+#define IS_FIS_FROM_MMC() (_mxc_fis == FROM_MMC_FLASH)
+#endif
+
+#define IS_FIS_FROM_NOR() 0
+
+/*
+ * This macro is used to get certain bit field from a number
+ */
+#define MXC_GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1))
+
+/*
+ * This macro is used to set certain bit field inside a number
+ */
+#define MXC_SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
+
+#define L2CC_ENABLED
+#define UART_WIDTH_32 /* internal UART is 32bit access only */
+
+/* Offsets for system_rev */
+#define PART_NUMBER_OFFSET (12)
+#define PMIC_ID_OFFSET (8)
+#define MAJOR_NUMBER_OFFSET (4)
+#define MINOR_NUMBER_OFFSET (0)
+
+#if !defined(__ASSEMBLER__)
+void cyg_hal_plf_serial_init(void);
+void cyg_hal_plf_serial_stop(void);
+void hal_delay_us(unsigned int usecs);
+#define HAL_DELAY_US(n) hal_delay_us(n)
+extern int _mxc_fis;
+extern int _mxc_boot;
+extern unsigned int system_rev;
+
+enum plls {
+ PLL1,
+ PLL2,
+ PLL3,
+};
+
+enum main_clocks {
+ CPU_CLK,
+ AHB_CLK,
+ IPG_CLK,
+ IPG_PER_CLK,
+ DDR_CLK,
+ NFC_CLK,
+ USB_CLK,
+};
+
+enum peri_clocks {
+ UART1_BAUD,
+ UART2_BAUD,
+ UART3_BAUD,
+ SSI1_BAUD,
+ SSI2_BAUD,
+ CSI_BAUD,
+ MSTICK1_CLK,
+ MSTICK2_CLK,
+ SPI1_CLK = CSPI1_BASE_ADDR,
+ SPI2_CLK = CSPI2_BASE_ADDR,
+};
+
+unsigned int pll_clock(enum plls pll);
+
+unsigned int get_main_clock(enum main_clocks clk);
+
+unsigned int get_peri_clock(enum peri_clocks clk);
+
+typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
+
+#endif //#if !defined(__ASSEMBLER__)
+
+#define HAL_MMU_OFF() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mcr p15, 0, r0, c7, c14, 0;" \
+ "mcr p15, 0, r0, c7, c10, 4;" /* drain the write buffer */ \
+ "mcr p15, 0, r0, c7, c5, 0;" /* invalidate I cache */ \
+ "mrc p15, 0, r0, c1, c0, 0;" /* read c1 */ \
+ "bic r0, r0, #0x7;" /* disable DCache and MMU */ \
+ "bic r0, r0, #0x1000;" /* disable ICache */ \
+ "mcr p15, 0, r0, c1, c0, 0;" /* */ \
+ "nop;" /* flush i+d-TLBs */ \
+ "nop;" /* flush i+d-TLBs */ \
+ "nop;" /* flush i+d-TLBs */ \
+ : \
+ : \
+ : "r0","memory" /* clobber list */); \
+CYG_MACRO_END
+
+#endif /* __HAL_SOC_H__ */
--- /dev/null
+#ifndef CYGONCE_HAL_VAR_INTS_H
+#define CYGONCE_HAL_VAR_INTS_H
+//==========================================================================
+//
+// hal_var_ints.h
+//
+// HAL Interrupt and clock support
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+
+#include <cyg/hal/hal_soc.h> // registers
+
+#define CYGNUM_HAL_INTERRUPT_GPIO0 0
+#define CYGNUM_HAL_INTERRUPT_GPIO1 1
+#define CYGNUM_HAL_INTERRUPT_GPIO2 2
+#define CYGNUM_HAL_INTERRUPT_GPIO3 3
+#define CYGNUM_HAL_INTERRUPT_GPIO4 4
+#define CYGNUM_HAL_INTERRUPT_GPIO5 5
+#define CYGNUM_HAL_INTERRUPT_GPIO6 6
+#define CYGNUM_HAL_INTERRUPT_GPIO7 7
+#define CYGNUM_HAL_INTERRUPT_GPIO8 8
+#define CYGNUM_HAL_INTERRUPT_GPIO9 9
+#define CYGNUM_HAL_INTERRUPT_GPIO10 10
+#define CYGNUM_HAL_INTERRUPT_GPIO 11 // Don't use directly!
+#define CYGNUM_HAL_INTERRUPT_LCD 12
+#define CYGNUM_HAL_INTERRUPT_UDC 13
+#define CYGNUM_HAL_INTERRUPT_UART1 15
+#define CYGNUM_HAL_INTERRUPT_UART2 16
+#define CYGNUM_HAL_INTERRUPT_UART3 17
+#define CYGNUM_HAL_INTERRUPT_UART4 17
+#define CYGNUM_HAL_INTERRUPT_MCP 18
+#define CYGNUM_HAL_INTERRUPT_SSP 19
+#define CYGNUM_HAL_INTERRUPT_TIMER0 26
+#define CYGNUM_HAL_INTERRUPT_TIMER1 27
+#define CYGNUM_HAL_INTERRUPT_TIMER2 28
+#define CYGNUM_HAL_INTERRUPT_TIMER3 29
+#define CYGNUM_HAL_INTERRUPT_HZ 30
+#define CYGNUM_HAL_INTERRUPT_ALARM 31
+
+// GPIO bits 31..11 can generate interrupts as well, but they all
+// end up clumped into interrupt signal #11. Using the symbols
+// below allow for detection of these separately.
+
+#define CYGNUM_HAL_INTERRUPT_GPIO11 (32+11)
+#define CYGNUM_HAL_INTERRUPT_GPIO12 (32+12)
+#define CYGNUM_HAL_INTERRUPT_GPIO13 (32+13)
+#define CYGNUM_HAL_INTERRUPT_GPIO14 (32+14)
+#define CYGNUM_HAL_INTERRUPT_GPIO15 (32+15)
+#define CYGNUM_HAL_INTERRUPT_GPIO16 (32+16)
+#define CYGNUM_HAL_INTERRUPT_GPIO17 (32+17)
+#define CYGNUM_HAL_INTERRUPT_GPIO18 (32+18)
+#define CYGNUM_HAL_INTERRUPT_GPIO19 (32+19)
+#define CYGNUM_HAL_INTERRUPT_GPIO20 (32+20)
+#define CYGNUM_HAL_INTERRUPT_GPIO21 (32+21)
+#define CYGNUM_HAL_INTERRUPT_GPIO22 (32+22)
+#define CYGNUM_HAL_INTERRUPT_GPIO23 (32+23)
+#define CYGNUM_HAL_INTERRUPT_GPIO24 (32+24)
+#define CYGNUM_HAL_INTERRUPT_GPIO25 (32+25)
+#define CYGNUM_HAL_INTERRUPT_GPIO26 (32+26)
+#define CYGNUM_HAL_INTERRUPT_GPIO27 (32+27)
+
+#define CYGNUM_HAL_INTERRUPT_NONE -1
+
+#define CYGNUM_HAL_ISR_MIN 0
+#define CYGNUM_HAL_ISR_MAX (27+32)
+
+#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1)
+
+// The vector used by the Real time clock
+#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0
+
+// The vector used by the Ethernet
+#define CYGNUM_HAL_INTERRUPT_ETH CYGNUM_HAL_INTERRUPT_GPIO0
+
+// method for reading clock interrupt latency
+#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
+externC void hal_clock_latency(cyg_uint32 *);
+# define HAL_CLOCK_LATENCY( _pvalue_ ) \
+ hal_clock_latency( (cyg_uint32 *)(_pvalue_) )
+#endif
+
+//----------------------------------------------------------------------------
+// Reset.
+#define HAL_PLATFORM_RESET() \
+ CYG_MACRO_START \
+ *(volatile unsigned short *)WDOG_BASE_ADDR |= 0x4; \
+ /* hang here forever if reset fails */ \
+ while (1){} \
+ CYG_MACRO_END
+
+// Fallback (never really used)
+#define HAL_PLATFORM_RESET_ENTRY 0x00000000
+
+#endif // CYGONCE_HAL_VAR_INTS_H
--- /dev/null
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+// plf_stub.h
+//
+// Platform header for GDB stub support.
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM
+
+#include <cyg/hal/hal_soc.h> // registers
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_intr.h> // Interrupt macros
+#include <cyg/hal/arm_stub.h> // architecture stub support
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init()
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
--- /dev/null
+#ifndef CYGONCE_VAR_IO_H
+#define CYGONCE_VAR_IO_H
+
+//=============================================================================
+//
+// var_io.h
+//
+// Variant specific IO support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/hal/plf_io.h> // Platform specifics
+
+//-----------------------------------------------------------------------------
+
+// Memory mapping details
+#ifndef CYGARC_PHYSICAL_ADDRESS
+#define CYGARC_PHYSICAL_ADDRESS(x) (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK0_BASE)
+#endif
+
+//-----------------------------------------------------------------------------
+// end of var_io.h
+#endif // CYGONCE_VAR_IO_H
--- /dev/null
+//==========================================================================
+//
+// cmds.c
+//
+// SoC [platform] specific RedBoot commands
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+#include <redboot.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/plf_mmap.h>
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/hal_cache.h>
+
+int gcd(int m, int n);
+
+typedef unsigned long long u64;
+typedef unsigned int u32;
+typedef unsigned short u16;
+typedef unsigned char u8;
+
+#define SZ_DEC_1M 1000000
+#define PLL_PD_MAX 16 //actual pd+1
+#define PLL_MFI_MAX 15
+#define PLL_MFI_MIN 5
+#define ARM_DIV_MAX 8
+#define IPG_DIV_MAX 4
+#define AHB_DIV_MAX 8
+#define EMI_DIV_MAX 8
+#define NFC_DIV_MAX 8
+
+#define REF_IN_CLK_NUM 4
+struct fixed_pll_mfd {
+ u32 ref_clk_hz;
+ u32 mfd;
+};
+const struct fixed_pll_mfd fixed_mfd[REF_IN_CLK_NUM] = {
+ {0, 0}, // reserved
+ {0, 0}, // reserved
+ {FREQ_24MHZ, 24 * 16}, // 384
+ {0, 0}, // reserved
+};
+
+struct pll_param {
+ u32 pd;
+ u32 mfi;
+ u32 mfn;
+ u32 mfd;
+};
+
+#define PLL_FREQ_MAX(_ref_clk_) (2 * _ref_clk_ * PLL_MFI_MAX)
+#define PLL_FREQ_MIN(_ref_clk_) ((2 * _ref_clk_ * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
+#define AHB_CLK_MAX 133333333
+#define IPG_CLK_MAX (AHB_CLK_MAX / 2)
+#define NFC_CLK_MAX 25000000
+// IPU-HSP clock is independent of the HCLK and can go up to 177MHz but requires
+// higher voltage support. For simplicity, limit it to 133MHz
+#define HSP_CLK_MAX 133333333
+
+#define ERR_WRONG_CLK -1
+#define ERR_NO_MFI -2
+#define ERR_NO_MFN -3
+#define ERR_NO_PD -4
+#define ERR_NO_PRESC -5
+#define ERR_NO_AHB_DIV -6
+
+u32 pll_clock(enum plls pll);
+u32 get_main_clock(enum main_clocks clk);
+u32 get_peri_clock(enum peri_clocks clk);
+
+static volatile u32 *pll_base[] =
+{
+ REG32_PTR(PLL1_BASE_ADDR),
+ REG32_PTR(PLL2_BASE_ADDR),
+ REG32_PTR(PLL3_BASE_ADDR),
+};
+
+#define NOT_ON_VAL 0xDEADBEEF
+
+static void clock_setup(int argc, char *argv[]);
+static void clko(int argc, char *argv[]);
+
+RedBoot_cmd("clock",
+ "Setup/Display clock (max AHB=133MHz, max IPG=66.5MHz)\nSyntax:",
+ "[<core clock in MHz> [:<AHB-to-core divider>[:<IPG-to-AHB divider>]]] \n\n\
+If a divider is zero or no divider is specified, the optimal divider values \n\
+will be chosen. Examples:\n\
+ [clock] -> Show various clocks\n\
+ [clock 532] -> Core=532 AHB=133 IPG=66.5\n\
+ [clock 399] -> Core=399 AHB=133 IPG=66.5\n\
+ [clock 532:8] -> Core=532 AHB=66.5(Core/8) IPG=66.5\n\
+ [clock 532:8:2] -> Core=532 AHB=66.5(Core/8) IPG=33.25(AHB/2)\n",
+ clock_setup
+ );
+
+/*!
+ * This is to calculate various parameters based on reference clock and
+ * targeted clock based on the equation:
+ * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
+ * This calculation is based on a fixed MFD value for simplicity.
+ *
+ * @param ref reference clock freq in Hz
+ * @param target targeted clock in Hz
+ * @param p_pd calculated pd value (pd value from register + 1) upon return
+ * @param p_mfi calculated actual mfi value upon return
+ * @param p_mfn calculated actual mfn value upon return
+ * @param p_mfd fixed mfd value (mfd value from register + 1) upon return
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
+{
+ u64 pd, mfi = 1, mfn, mfd, n_target = target, n_ref = ref, i;
+
+ // make sure targeted freq is in the valid range. Otherwise the
+ // following calculation might be wrong!!!
+ if (n_target < PLL_FREQ_MIN(ref) || n_target > PLL_FREQ_MAX(ref))
+ return ERR_WRONG_CLK;
+ for (i = 0; ; i++) {
+ if (i == REF_IN_CLK_NUM)
+ return ERR_WRONG_CLK;
+ if (fixed_mfd[i].ref_clk_hz == ref) {
+ mfd = fixed_mfd[i].mfd;
+ break;
+ }
+ }
+ // Use n_target and n_ref to avoid overflow
+ for (pd = 1; pd <= PLL_PD_MAX; pd++) {
+ mfi = (n_target * pd) / (2 * n_ref);
+ if (mfi > PLL_MFI_MAX) {
+ return ERR_NO_MFI;
+ } else if (mfi < 5) {
+ continue;
+ }
+ break;
+ }
+ // Now got pd and mfi already
+ mfn = (((n_target * pd) / 2 - n_ref * mfi) * mfd) / n_ref;
+#ifdef CMD_CLOCK_DEBUG
+ diag_printf("%d: ref=%d, target=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
+ __LINE__, ref, (u32)n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
+#endif
+ i = 1;
+ if (mfn != 0)
+ i = gcd(mfd, mfn);
+ pll->pd = (u32)pd;
+ pll->mfi = (u32)mfi;
+ pll->mfn = (u32)(mfn / i);
+ pll->mfd = (u32)(mfd / i);
+ return 0;
+}
+
+/*!
+ * This function assumes the expected core clock has to be changed by
+ * modifying the PLL. This is NOT true always but for most of the times,
+ * it is. So it assumes the PLL output freq is the same as the expected
+ * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
+ * In the latter case, it will try to increase the presc value until
+ * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
+ * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
+ * on the targeted PLL and reference input clock to the PLL. Lastly,
+ * it sets the register based on these values along with the dividers.
+ * Note 1) There is no value checking for the passed-in divider values
+ * so the caller has to make sure those values are sensible.
+ * 2) Also adjust the NFC divider such that the NFC clock doesn't
+ * exceed NFC_CLK_MAX.
+ * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
+ * 177MHz for higher voltage, this function fixes the max to 133MHz.
+ * 4) This function should not have allowed diag_printf() calls since
+ * the serial driver has been stoped. But leave then here to allow
+ * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
+ *
+ * @param ref pll input reference clock (32KHz or 26MHz)
+ * @param core_clk core clock in Hz
+ * @param emi_clk emi clock in Hz
+ * @param ahb_div ahb divider to divide the core clock to get ahb clock
+ * (ahb_div - 1) needs to be set in the register
+ * @param ipg_div ipg divider to divide the core clock to get ipg clock
+ * (ipg_div - 1) needs to be set in the register
+ # @return 0 if successful; non-zero otherwise
+ */
+int configure_clock(u32 ref, u32 core_clk, u32 emi_clk, u32 ahb_div, u32 ipg_div)
+{
+#if 0
+ u32 pll, arm_div = 1, emi_div = 0, nfc_div, ascsr, acdr, acder2;
+ struct pll_param pll_param;
+ int ret;
+
+ // assume pll default to core clock first
+ pll = core_clk;
+ // when core_clk >= PLL_FREQ_MIN, the presc can be 1.
+ // Otherwise, need to calculate presc value below and adjust the targeted pll
+ if (core_clk < PLL_FREQ_MIN) {
+ for (presc = 1; presc <= PRESC_MAX; presc++) {
+ if ((core_clk * presc) > PLL_FREQ_MIN) {
+ break;
+ }
+ }
+ if (presc == (PRESC_MAX + 1)) {
+ diag_printf("can't make presc=%d\n", presc);
+ return ERR_NO_PRESC;
+ }
+ pll = core_clk * presc;
+ }
+ // get hsp_div
+ for (hsp_div = 1; hsp_div <= HSP_PODF_MAX; hsp_div++) {
+ if ((pll / hsp_div) <= HSP_CLK_MAX) {
+ break;
+ }
+ }
+ if (hsp_div == (HSP_PODF_MAX + 1)) {
+ diag_printf("can't make hsp_div=%d\n", hsp_div);
+ return ERR_NO_PRESC;
+ }
+
+ // get nfc_div - make sure optimal NFC clock but less than NFC_CLK_MAX
+ for (nfc_div = 1; nfc_div <= NFC_PODF_MAX; nfc_div++) {
+ if ((pll / (ahb_div * nfc_div)) <= NFC_CLK_MAX) {
+ break;
+ }
+ }
+
+ // pll is now the targeted pll output. Use it along with ref input clock
+ // to get pd, mfi, mfn, mfd
+ if ((ret = calc_pll_params(ref, pll, &pd, &mfi, &mfn, &mfd)) != 0) {
+ diag_printf("can't find pll parameters: %d\n", ret);
+ return ret;
+ }
+#ifdef CMD_CLOCK_DEBUG
+ diag_printf("ref=%d, pll=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
+ ref, pll, pd, mfi, mfn, mfd);
+#endif
+
+ // blindly increase divider first to avoid too fast ahbclk and ipgclk
+ // in case the core clock increases too much
+ pdr0 = readl(CCM_BASE_ADDR + CLKCTL_PDR0);
+ pdr0 &= ~0x000000FF;
+ // increase the dividers. should work even when core clock is 832 (26*2*16)MHz
+ // which is unlikely true.
+ pdr0 |= (1 << 6) | (6 << 3) | (0 << 0);
+ writel(pdr0, CCM_BASE_ADDR + CLKCTL_PDR0);
+ // calculate new pdr0
+ pdr0 &= ~0x00003FFF;
+ pdr0 |= ((hsp_div - 1) << 11) | ((nfc_div - 1) << 8) | ((ipg_div - 1) << 6) |
+ ((ahb_div - 1) << 3) | ((presc - 1) << 0);
+
+ // update PLL register
+ if ((mfd >= (10 * mfn)) || ((10 * mfn) >= (9 * mfd)))
+ brmo = 1;
+
+ mpctl0 = readl(CCM_BASE_ADDR + CLKCTL_MPCTL);
+ mpctl0 = (mpctl0 & 0x4000C000) |
+ (brmo << 31) |
+ ((pd - 1) << 26) |
+ ((mfd - 1) << 16) |
+ (mfi << 10) |
+ mfn;
+ writel(mpctl0, CCM_BASE_ADDR + CLKCTL_MPCTL);
+ writel(pdr0, CCM_BASE_ADDR + CLKCTL_PDR0);
+ // add some delay for new values to take effect
+ for (i = 0; i < 10000; i++);
+#endif
+ return 0;
+}
+
+static void clock_setup(int argc,char *argv[])
+{
+#if 0
+ u32 i, core_clk, ipg_div, data[3], temp, ahb_div, ahb_clk, ipg_clk;
+ int ret;
+
+ if (argc == 1)
+ goto print_clock;
+
+ for (i = 0; i < 3; i++) {
+ if (!parse_num(*(&argv[1]), (unsigned long *)&temp, &argv[1], ":")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ data[i] = temp;
+ }
+
+ core_clk = data[0] * SZ_DEC_1M;
+ ahb_div = data[1]; // actual register field + 1
+ ipg_div = data[2]; // actual register field + 1
+
+ if (core_clk < (PLL_FREQ_MIN / PRESC_MAX) || core_clk > PLL_FREQ_MAX) {
+ diag_printf("Targeted core clock should be within [%d - %d]\n",
+ PLL_FREQ_MIN / PRESC_MAX, PLL_FREQ_MAX);
+ return;
+ }
+
+ // find the ahb divider
+ if (ahb_div > AHB_DIV_MAX) {
+ diag_printf("Invalid AHB divider: %d. Maximum value is %d\n",
+ ahb_div, AHB_DIV_MAX);
+ return;
+ }
+ if (ahb_div == 0) {
+ // no HCLK divider specified
+ for (ahb_div = 1; ; ahb_div++) {
+ if ((core_clk / ahb_div) <= AHB_CLK_MAX) {
+ break;
+ }
+ }
+ }
+ if (ahb_div > AHB_DIV_MAX || (core_clk / ahb_div) > AHB_CLK_MAX) {
+ diag_printf("Can't make AHB=%d since max=%d\n",
+ core_clk / ahb_div, AHB_CLK_MAX);
+ return;
+ }
+
+ // find the ipg divider
+ ahb_clk = core_clk / ahb_div;
+ if (ipg_div > IPG_DIV_MAX) {
+ diag_printf("Invalid IPG divider: %d. Maximum value is %d\n",
+ ipg_div, IPG_DIV_MAX);
+ return;
+ }
+ if (ipg_div == 0) {
+ ipg_div++; // At least =1
+ if (ahb_clk > IPG_CLK_MAX)
+ ipg_div++; // Make it =2
+ }
+ if (ipg_div > IPG_DIV_MAX || (ahb_clk / ipg_div) > IPG_CLK_MAX) {
+ diag_printf("Can't make IPG=%d since max=%d\n",
+ (ahb_clk / ipg_div), IPG_CLK_MAX);
+ return;
+ }
+ ipg_clk = ahb_clk / ipg_div;
+
+ diag_printf("Trying to set core=%d ahb=%d ipg=%d...\n",
+ core_clk, ahb_clk, ipg_clk);
+
+ // stop the serial to be ready to adjust the clock
+ hal_delay_us(100000);
+ cyg_hal_plf_serial_stop();
+ // adjust the clock
+ ret = configure_clock(PLL_REF_CLK, core_clk, ahb_div, ipg_div);
+ // restart the serial driver
+ cyg_hal_plf_serial_init();
+ hal_delay_us(100000);
+
+ if (ret != 0) {
+ diag_printf("Failed to setup clock: %d\n", ret);
+ return;
+ }
+ diag_printf("\n<<<New clock setting>>>\n");
+
+ // Now printing clocks
+print_clock:
+#endif
+ diag_printf("\nPLL1\t\tPLL2\t\tPLL3\n");
+ diag_printf("========================================\n");
+ diag_printf("%-16d%-16d%-16d\n\n", pll_clock(PLL1), pll_clock(PLL2),
+ pll_clock(PLL3));
+ diag_printf("CPU\t\tAHB\t\tIPG\t\tEMI_CLK\n");
+ diag_printf("========================================================\n");
+ diag_printf("%-16d%-16d%-16d%-16d\n\n",
+ get_main_clock(CPU_CLK),
+ get_main_clock(AHB_CLK),
+ get_main_clock(IPG_CLK),
+ get_main_clock(DDR_CLK));
+
+ diag_printf("NFC\t\tUSB\n");
+ diag_printf("========================================\n");
+ diag_printf("%-16d%-16d\n\n",
+ get_main_clock(NFC_CLK),
+ get_main_clock(USB_CLK));
+
+ diag_printf("UART1-3\t\tSSI1\t\tSSI2\t\tCSI\n");
+ diag_printf("===========================================");
+ diag_printf("=============\n");
+
+ diag_printf("%-16d%-16d%-16d%-16d\n\n",
+ get_peri_clock(UART1_BAUD),
+ get_peri_clock(SSI1_BAUD),
+ get_peri_clock(SSI2_BAUD),
+ get_peri_clock(CSI_BAUD));
+
+ diag_printf("MSTICK1\t\tMSTICK2\t\tSPI\n");
+ diag_printf("===========================================");
+ diag_printf("=============\n");
+
+ diag_printf("%-16d%-16d%-16d\n\n",
+ get_peri_clock(MSTICK1_CLK),
+ get_peri_clock(MSTICK2_CLK),
+ get_peri_clock(SPI1_CLK));
+#if 0
+ diag_printf("IPG_PERCLK as baud clock for: UART1-5, I2C, OWIRE, SDHC");
+ if (((readl(EPIT1_BASE_ADDR) >> 24) & 0x3) == 0x2) {
+ diag_printf(", EPIT");
+ }
+ if (((readl(GPT1_BASE_ADDR) >> 6) & 0x7) == 0x2) {
+ diag_printf("GPT,");
+ }
+#endif
+ diag_printf("\n");
+
+}
+
+/*!
+ * This function returns the PLL output value in Hz based on pll.
+ */
+u32 pll_clock(enum plls pll)
+{
+ u64 mfi, mfn, mfd, pdf, ref_clk, pll_out, sign;
+ u64 dp_ctrl, dp_op, dp_mfd, dp_mfn, clk_sel;
+ u8 dbl = 0;
+
+ dp_ctrl = pll_base[pll][PLL_DP_CTL >> 2];
+ clk_sel = MXC_GET_FIELD(dp_ctrl, 2, 8);
+ ref_clk = fixed_mfd[clk_sel].ref_clk_hz;
+
+ if ((pll_base[pll][PLL_DP_CTL >> 2] & 0x80) == 0) {
+ dp_op = pll_base[pll][PLL_DP_OP >> 2];
+ dp_mfd = pll_base[pll][PLL_DP_MFD >> 2];
+ dp_mfn = pll_base[pll][PLL_DP_MFN >> 2];
+ } else {
+ dp_op = pll_base[pll][PLL_DP_HFS_OP >> 2];
+ dp_mfd = pll_base[pll][PLL_DP_HFS_MFD >> 2];
+ dp_mfn = pll_base[pll][PLL_DP_HFS_MFN >> 2];
+ }
+ pdf = dp_op & 0xF;
+ mfi = (dp_op >> 4) & 0xF;
+ mfi = (mfi <= 5) ? 5: mfi;
+ mfd = dp_mfd & 0x07FFFFFF;
+ mfn = dp_mfn & 0x07FFFFFF;
+
+ sign = (mfn < 0x4000000) ? 0: 1;
+ mfn = (mfn <= 0x4000000) ? mfn: (0x8000000 - mfn);
+
+ dbl = ((dp_ctrl >> 12) & 0x1) + 1;
+
+ dbl = dbl * 2;
+ if (sign == 0) {
+ pll_out = (dbl * ref_clk * mfi + ((dbl * ref_clk * mfn) / (mfd + 1))) /
+ (pdf + 1);
+ } else {
+ pll_out = (dbl * ref_clk * mfi - ((dbl * ref_clk * mfn) / (mfd + 1))) /
+ (pdf + 1);
+ }
+
+ return (u32)pll_out;
+}
+
+// The clocks are on by default. But need to setup the IOMUX
+void clock_spi_enable(unsigned int spi_clk)
+{
+ // Take care of SPI2
+ writel(0x0, IOMUXC_BASE_ADDR + 0x14C);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x3AC);
+ writel(0x100, IOMUXC_BASE_ADDR + 0x494);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x148);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x3A8);
+ writel(0x3, IOMUXC_BASE_ADDR + 0x168);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x3C8);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x158);
+ writel(0x101, IOMUXC_BASE_ADDR + 0x3B8);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x150);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x3B0);
+ writel(0x100, IOMUXC_BASE_ADDR + 0x490);
+}
+
+/*!
+ * This function returns the low power audio clock.
+ */
+u32 get_lp_apm(void)
+{
+ u32 ret_val = 0;
+ u32 ccsr = readl(CCM_BASE_ADDR + CLKCTL_CCSR);
+
+ if (((ccsr >> 9) & 1) == 0) {
+ ret_val = FREQ_24MHZ;
+ } else {
+ ret_val = FREQ_32000HZ;
+ }
+ return ret_val;
+}
+
+/*!
+ * This function returns the periph_clk.
+ */
+u32 get_periph_clk(void)
+{
+ u32 cbcdr6 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR6);
+ u32 camr = readl(CCM_BASE_ADDR + CLKCTL_CAMR);
+ u32 ret_val = 0, clk_sel;
+
+ if (((cbcdr6 >> 4) & 1) == 0) {
+ ret_val = pll_clock(PLL2);
+ } else {
+ clk_sel = (camr >> 12) & 3;
+ if (clk_sel == 0) {
+ ret_val = pll_clock(PLL1);
+ } else if (clk_sel == 1) {
+ ret_val = pll_clock(PLL3);
+ } else if (clk_sel == 2) {
+ ret_val = get_lp_apm();
+ }
+ }
+
+ return ret_val;
+}
+
+/*!
+ * This function returns the emi_core_clk_root clock.
+ */
+u32 get_emi_core_clk(void)
+{
+ u32 cbcdr6 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR6);
+ u32 cbcdr2 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR2);
+ u32 clk_sel = 0, pdf = 0, max_pdf = 0, peri_clk = 0, ahb_clk = 0;
+ u32 ret_val = 0;
+
+ max_pdf = (cbcdr2 >> 10) & 0x7;
+ peri_clk = get_periph_clk();
+ ahb_clk = peri_clk / (max_pdf + 1);
+
+ pdf = cbcdr6 & 0x7;
+ clk_sel = (cbcdr6 >> 3) & 1;
+ if (clk_sel == 0) {
+ ret_val = peri_clk / (pdf + 1);
+ } else {
+ ret_val = ahb_clk / (pdf + 1);
+ }
+ return ret_val;
+}
+
+// The clocks are on by default. But need to setup the IOMUX
+void mxc_i2c_init(unsigned int module_base)
+{
+ unsigned int val, reg;
+
+ switch (module_base) {
+ case I2C_BASE_ADDR:
+ writel(0x0, IOMUXC_BASE_ADDR + 0x104);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x5C0);
+ writel(0xA8, IOMUXC_BASE_ADDR + 0x364);
+
+ writel(0x0, IOMUXC_BASE_ADDR + 0x108);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x5C4);
+ writel(0xA8, IOMUXC_BASE_ADDR + 0x368);
+
+ writel(0x100, IOMUXC_BASE_ADDR + 0x4D0);
+ break;
+ case I2C2_BASE_ADDR:
+ // i2c SCL
+ writel(0x2, IOMUXC_BASE_ADDR + 0x210);
+ writel(0x1EC, IOMUXC_BASE_ADDR + 0x468);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x5C8);
+ // i2c SDA
+ writel(0x2, IOMUXC_BASE_ADDR + 0x214);
+ writel(0x1EC, IOMUXC_BASE_ADDR + 0x46C);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x5CC);
+ break;
+ case I2C3_BASE_ADDR:
+ reg = IOMUXC_BASE_ADDR + 0x84;
+ val = (readl(reg) & 0xFFFFFF00) | 0x24; // alt mode 1
+ writel(val, reg);
+ reg = IOMUXC_BASE_ADDR + 0x80;
+ val = (readl(reg) & 0x00FFFFFF) | 0x24000000; // alt mode 1
+ writel(val, reg);
+ break;
+ default:
+ diag_printf("Invalid I2C base: 0x%x\n", module_base);
+ return;
+ }
+}
+
+/*!
+ * This function returns the main clock value in Hz.
+ */
+u32 get_main_clock(enum main_clocks clk)
+{
+ u32 mcu_podf, max_pdf, ipg_pdf, nfc_pdf, clk_sel;
+ u32 pll, ret_val = 0;
+ u32 cacrr = readl(CCM_BASE_ADDR + CLKCTL_CACRR);
+ u32 cbcdr2 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR2);
+ u32 cbcdr3 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR3);
+ u32 cbcdr4 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR4);
+ u32 cbcdr5 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR5);
+ u32 cbcdr7 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR7);
+ u32 camr = readl(CCM_BASE_ADDR + CLKCTL_CAMR);
+
+ switch (clk) {
+ case CPU_CLK:
+ mcu_podf = cacrr & 0x7;
+ pll = pll_clock(PLL1);
+ ret_val = pll / (mcu_podf + 1);
+ break;
+ case AHB_CLK:
+ max_pdf = (cbcdr2 >> 10) & 0x7;
+ pll = get_periph_clk();
+ ret_val = pll / (max_pdf + 1);
+ break;
+ case IPG_CLK:
+ max_pdf = (cbcdr2 >> 10) & 0x7;
+ ipg_pdf = (cbcdr2 >> 8) & 0x3;
+ pll = get_periph_clk();
+ ret_val = pll / ((max_pdf + 1) * (ipg_pdf + 1));
+ break;
+ case IPG_PER_CLK:
+#if 0
+ clk_sel = ccmr & (1 << 24);
+ pdf = (mpdr0 >> 16) & 0x1F;
+ if (clk_sel != 0) {
+ // get the ipg_clk
+ max_pdf = (reg >> 3) & 0x7;
+ ipg_pdf = (reg >> 6) & 0x3;
+ pll = pll_clock(PLL1);
+ ret_val = pll / ((max_pdf + 1) * (ipg_pdf + 1));
+ } else {
+ ret_val = pll_clock(PLL2) / (pdf + 1);
+ }
+#endif
+ break;
+ case DDR_CLK:
+ clk_sel = (camr >> 10) & 3;
+ if (clk_sel == 0) {
+ ret_val = get_periph_clk() / ((cbcdr3 & 7) + 1);
+ } else if (clk_sel == 1) {
+ ret_val = get_periph_clk() / ((cbcdr4 & 7) + 1);
+ } else if (clk_sel == 2) {
+ ret_val = get_periph_clk() / ((cbcdr5 & 7) + 1);
+ } else if (clk_sel == 3) {
+ ret_val = get_emi_core_clk();
+ }
+ break;
+ case NFC_CLK:
+ nfc_pdf = cbcdr7 & 0x7;
+ pll = get_emi_core_clk();
+ /* AHB/nfc_pdf */
+ ret_val = pll / (nfc_pdf + 1);
+ break;
+ case USB_CLK:
+#if 0
+ usb_prdf = reg1 >> 30;
+ usb_podf = (reg1 >> 27) & 0x7;
+ pll = pll_clock(PLL2);
+ ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1));
+#endif
+ break;
+ default:
+ diag_printf("Unknown clock: %d\n", clk);
+ break;
+ }
+
+ return ret_val;
+}
+
+/*!
+ * This function returns the peripheral clock value in Hz.
+ */
+u32 get_peri_clock(enum peri_clocks clk)
+{
+ u32 ret_val = 0, pdf, pre_pdf, clk_sel;
+ u32 cscmr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCMR1);
+ u32 cscdr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCDR1);
+ u32 cscdr2 = readl(CCM_BASE_ADDR + CLKCTL_CSCDR2);
+ u32 cs1cdr = readl(CCM_BASE_ADDR + CLKCTL_CS1CDR);
+ u32 cs2cdr = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);
+
+ switch (clk) {
+ case UART1_BAUD:
+ case UART2_BAUD:
+ case UART3_BAUD:
+ pre_pdf = (cscdr1 >> 3) & 0x7;
+ pdf = cscdr1 & 0x7;
+ clk_sel = (cscmr1 >> 24) & 3;
+ if (clk_sel == 0) {
+ ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 1) {
+ ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 2) {
+ ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
+ }
+ break;
+ case SSI1_BAUD:
+ pre_pdf = (cs1cdr >> 6) & 0x7;
+ pdf = cs1cdr & 0x3F;
+ clk_sel = (cscmr1 >> 14) & 3;
+ if (clk_sel == 0) {
+ ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 0x1) {
+ ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 0x2) {
+ ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
+ } else {
+ diag_printf("Error: Use reserved value for SSI1!\n");
+ ret_val = 0;
+ }
+ break;
+ case SSI2_BAUD:
+ pre_pdf = (cs2cdr >> 6) & 0x7;
+ pdf = cs2cdr & 0x3F;
+ clk_sel = (cscmr1 >> 12) & 3;
+ if (clk_sel == 0) {
+ ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 0x1) {
+ ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 0x2) {
+ ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
+ } else {
+ diag_printf("Error: Use reserved value for SSI2!\n");
+ ret_val = 0;
+ }
+ break;
+ case CSI_BAUD:
+#if 0
+ clk_sel = ccmr & (1 << 25);
+ pdf = (mpdr0 >> 23) & 0x1FF;
+ ret_val = (clk_sel != 0) ? (pll_clock(PLL3) / (pdf + 1)) :
+ (pll_clock(PLL2) / (pdf + 1));
+#endif
+ break;
+ case MSTICK1_CLK:
+#if 0
+ pdf = mpdr2 & 0x3F;
+ ret_val = pll_clock(PLL2) / (pdf + 1);
+#endif
+ break;
+ case MSTICK2_CLK:
+#if 0
+ pdf = (mpdr2 >> 7) & 0x3F;
+ ret_val = pll_clock(PLL2) / (pdf + 1);
+#endif
+ break;
+ case SPI1_CLK:
+ case SPI2_CLK:
+ pre_pdf = (cscdr2 >> 25) & 0x7;
+ pdf = (cscdr2 >> 19) & 0x3F;
+ clk_sel = (cscmr1 >> 4) & 3;
+ if (clk_sel == 0) {
+ ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 1) {
+ ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 2) {
+ ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
+ }
+ break;
+ default:
+ diag_printf("%s(): This clock: %d not supported yet \n",
+ __FUNCTION__, clk);
+ break;
+ }
+
+ return ret_val;
+}
+
+RedBoot_cmd("clko",
+ "Select clock source for CLKO (J11 on the CPU daughter card)",
+ " Default is 1/8 of ARM core\n\
+ <0> - display current clko selection \n\
+ <1> - mpl_dpdgck_clk (MPLL) \n\
+ <2> - ipg_clk_ccm (IPG) \n\
+ <3> - upl_dpdgck_clk (UPLL) \n\
+ <4> - pll_ref_clk \n\
+ <5> - fpm_ckil512_clk \n\
+ <6> - ipg_clk_ahb_arm (AHB) \n\
+ <7> - ipg_clk_arm (ARM) \n\
+ <8> - spl_dpdgck_clk (SPLL) \n\
+ <9> - ckih \n\
+ <10> - ipg_clk_ahb_emi_clk \n\
+ <11> - ipg_clk_ipu_hsp \n\
+ <12> - ipg_clk_nfc_20m \n\
+ <13> - ipg_clk_perclk_uart1 (IPG_PER)",
+ clko
+ );
+
+static u8* clko_name[] ={
+ "NULL",
+ "1/8 of mpl_dpdgck_clk (MPLL)",
+ "ipg_clk_ccm (IPG)",
+ "1/8 of upl_dpdgck_clk (UPLL)",
+ "pll_ref_clk",
+ "fpm_ckil512_clk",
+ "ipg_clk_ahb_arm (AHB)",
+ "1/8 of ipg_clk_arm (ARM)",
+ "1/8 of spl_dpdgck_clk (SPLL)",
+ "ckih",
+ "ipg_clk_ahb_emi_clk",
+ "ipg_clk_ipu_hsp",
+ "ipg_clk_nfc_20m",
+ "ipg_clk_perclk_uart1 (IPG_PER)",
+};
+
+#define CLKO_MAX_INDEX (sizeof(clko_name) / sizeof(u8*))
+
+static void clko(int argc,char *argv[])
+{
+ u32 action = 0, cosr;
+
+ if (!scan_opts(argc, argv, 1, 0, 0, (void*) &action,
+ OPTION_ARG_TYPE_NUM, "action"))
+ return;
+
+ if (action >= CLKO_MAX_INDEX) {
+ diag_printf("%d is not supported\n\n", action);
+ return;
+ }
+
+ cosr = readl(CCM_BASE_ADDR + CLKCTL_COSR);
+
+ if (action != 0) {
+ cosr = (cosr & (~0x1FF)) + action - 1;
+ if (action == 1 || action == 3 || action == 7 || action == 8) {
+ cosr |= (0x3 << 6); // make it divided by 8
+ }
+ writel(cosr, CCM_BASE_ADDR + CLKCTL_COSR);
+ diag_printf("Set clko to ");
+ }
+
+ cosr = readl(CCM_BASE_ADDR + CLKCTL_COSR);
+ diag_printf("%s\n", clko_name[(cosr & 0xF) + 1]);
+ diag_printf("COSR register[0x%x] = 0x%x\n",
+ (CCM_BASE_ADDR + CLKCTL_COSR), cosr);
+}
+
+#ifdef L2CC_ENABLED
+/*
+ * This command is added for some simple testing only. It turns on/off
+ * L2 cache regardless of L1 cache state. The side effect of this is
+ * when doing any flash operations such as "fis init", the L2
+ * will be turned back on along with L1 caches even though it is off
+ * by using this command.
+ */
+RedBoot_cmd("L2",
+ "L2 cache",
+ "[ON | OFF]",
+ do_L2_caches
+ );
+
+void do_L2_caches(int argc, char *argv[])
+{
+ u32 oldints;
+ int L2cache_on=0;
+
+ if (argc == 2) {
+ if (strcasecmp(argv[1], "on") == 0) {
+ HAL_DISABLE_INTERRUPTS(oldints);
+ HAL_ENABLE_L2();
+ HAL_RESTORE_INTERRUPTS(oldints);
+ } else if (strcasecmp(argv[1], "off") == 0) {
+ HAL_DISABLE_INTERRUPTS(oldints);
+ HAL_CLEAN_INVALIDATE_L2();
+ HAL_DISABLE_L2();
+ HAL_RESTORE_INTERRUPTS(oldints);
+ } else {
+ diag_printf("Invalid L2 cache mode: %s\n", argv[1]);
+ }
+ } else {
+ HAL_L2CACHE_IS_ENABLED(L2cache_on);
+ diag_printf("L2 cache: %s\n", L2cache_on?"On":"Off");
+ }
+}
+#endif //L2CC_ENABLED
+
+#define IIM_ERR_SHIFT 8
+#define POLL_FUSE_PRGD (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT))
+#define POLL_FUSE_SNSD (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT))
+
+static void fuse_op_start(void)
+{
+ /* Do not generate interrupt */
+ writel(0, IIM_BASE_ADDR + IIM_STATM_OFF);
+ // clear the status bits and error bits
+ writel(0x3, IIM_BASE_ADDR + IIM_STAT_OFF);
+ writel(0xFE, IIM_BASE_ADDR + IIM_ERR_OFF);
+}
+
+/*
+ * The action should be either:
+ * POLL_FUSE_PRGD
+ * or:
+ * POLL_FUSE_SNSD
+ */
+static int poll_fuse_op_done(int action)
+{
+
+ u32 status, error;
+
+ if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) {
+ diag_printf("%s(%d) invalid operation\n", __FUNCTION__, action);
+ return -1;
+ }
+
+ /* Poll busy bit till it is NOT set */
+ while ((readl(IIM_BASE_ADDR + IIM_STAT_OFF) & IIM_STAT_BUSY) != 0 ) {
+ }
+
+ /* Test for successful write */
+ status = readl(IIM_BASE_ADDR + IIM_STAT_OFF);
+ error = readl(IIM_BASE_ADDR + IIM_ERR_OFF);
+
+ if ((status & action) != 0 && (error & (action >> IIM_ERR_SHIFT)) == 0) {
+ if (error) {
+ diag_printf("Even though the operation seems successful...\n");
+ diag_printf("There are some error(s) at addr=0x%x: 0x%x\n",
+ (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+ }
+ return 0;
+ }
+ diag_printf("%s(%d) failed\n", __FUNCTION__, action);
+ diag_printf("status address=0x%x, value=0x%x\n",
+ (IIM_BASE_ADDR + IIM_STAT_OFF), status);
+ diag_printf("There are some error(s) at addr=0x%x: 0x%x\n",
+ (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+ return -1;
+}
+
+static void sense_fuse(int bank, int row, int bit)
+{
+ int addr, addr_l, addr_h, reg_addr;
+
+ fuse_op_start();
+
+ addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+ /* Set IIM Program Upper Address */
+ addr_h = (addr >> 8) & 0x000000FF;
+ /* Set IIM Program Lower Address */
+ addr_l = (addr & 0x000000FF);
+
+#ifdef IIM_FUSE_DEBUG
+ diag_printf("%s: addr_h=0x%x, addr_l=0x%x\n",
+ __FUNCTION__, addr_h, addr_l);
+#endif
+ writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
+ writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
+ /* Start sensing */
+ writel(0x8, IIM_BASE_ADDR + IIM_FCTL_OFF);
+ if (poll_fuse_op_done(POLL_FUSE_SNSD) != 0) {
+ diag_printf("%s(bank: %d, row: %d, bit: %d failed\n",
+ __FUNCTION__, bank, row, bit);
+ }
+ reg_addr = IIM_BASE_ADDR + IIM_SDAT_OFF;
+ diag_printf("fuses at (bank:%d, row:%d) = 0x%x\n", bank, row, readl(reg_addr));
+}
+
+void do_fuse_read(int argc, char *argv[])
+{
+ int bank, row;
+
+ if (argc == 1) {
+ diag_printf("Useage: fuse_read <bank> <row>\n");
+ return;
+ } else if (argc == 3) {
+ if (!parse_num(*(&argv[1]), (unsigned long *)&bank, &argv[1], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(*(&argv[2]), (unsigned long *)&row, &argv[2], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+
+ diag_printf("Read fuse at bank:%d row:%d\n", bank, row);
+ sense_fuse(bank, row, 0);
+
+ } else {
+ diag_printf("Passing in wrong arguments: %d\n", argc);
+ diag_printf("Useage: fuse_read <bank> <row>\n");
+ }
+}
+
+/* Blow fuses based on the bank, row and bit positions (all 0-based)
+*/
+static int fuse_blow(int bank,int row,int bit)
+{
+ int addr, addr_l, addr_h, ret = -1;
+
+ fuse_op_start();
+
+ /* Disable IIM Program Protect */
+ writel(0xAA, IIM_BASE_ADDR + IIM_PREG_P_OFF);
+
+ addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+ /* Set IIM Program Upper Address */
+ addr_h = (addr >> 8) & 0x000000FF;
+ /* Set IIM Program Lower Address */
+ addr_l = (addr & 0x000000FF);
+
+#ifdef IIM_FUSE_DEBUG
+ diag_printf("blowing addr_h=0x%x, addr_l=0x%x\n", addr_h, addr_l);
+#endif
+
+ writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
+ writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
+ /* Start Programming */
+ writel(0x31, IIM_BASE_ADDR + IIM_FCTL_OFF);
+ if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) {
+ ret = 0;
+ }
+
+ /* Enable IIM Program Protect */
+ writel(0x0, IIM_BASE_ADDR + IIM_PREG_P_OFF);
+ return ret;
+}
+
+/*
+ * This command is added for burning IIM fuses
+ */
+RedBoot_cmd("fuse_read",
+ "read some fuses",
+ "<bank> <row>",
+ do_fuse_read
+ );
+
+RedBoot_cmd("fuse_blow",
+ "blow some fuses",
+ "<bank> <row> <value>",
+ do_fuse_blow
+ );
+
+#define INIT_STRING "12345678"
+static char ready_to_blow[] = INIT_STRING;
+
+void quick_itoa(u32 num, char *a)
+{
+ int i, j, k;
+ for (i = 0; i <= 7; i++) {
+ j = (num >> (4 * i)) & 0xF;
+ k = (j < 10) ? '0' : ('a' - 0xa);
+ a[i] = j + k;
+ }
+}
+
+void do_fuse_blow(int argc, char *argv[])
+{
+ int bank, row, value, i;
+
+ if (argc == 1) {
+ diag_printf("It is too dangeous for you to use this command.\n");
+ return;
+ } else if (argc == 2) {
+ if (strcasecmp(argv[1], "nandboot") == 0) {
+ quick_itoa(readl(EPIT_BASE_ADDR + EPITCNR), ready_to_blow);
+ diag_printf("%s\n", ready_to_blow);
+ }
+ return;
+ } else if (argc == 3) {
+ if (strcasecmp(argv[1], "nandboot") == 0 &&
+ strcasecmp(argv[2], ready_to_blow) == 0) {
+#if defined(CYGPKG_HAL_ARM_MXC91131) || defined(CYGPKG_HAL_ARM_MX21) || defined(CYGPKG_HAL_ARM_MX27) || defined(CYGPKG_HAL_ARM_MX31)
+ diag_printf("No need to blow any fuses for NAND boot on this platform\n\n");
+#else
+ diag_printf("Ready to burn NAND boot fuses\n");
+ if (fuse_blow(0, 16, 1) != 0 || fuse_blow(0, 16, 7) != 0) {
+ diag_printf("NAND BOOT fuse blown failed miserably ...\n");
+ } else {
+ diag_printf("NAND BOOT fuse blown successfully ...\n");
+ }
+ } else {
+ diag_printf("Not ready: %s, %s\n", argv[1], argv[2]);
+#endif
+ }
+ } else if (argc == 4) {
+ if (!parse_num(*(&argv[1]), (unsigned long *)&bank, &argv[1], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(*(&argv[2]), (unsigned long *)&row, &argv[2], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(*(&argv[3]), (unsigned long *)&value, &argv[3], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+
+ diag_printf("Blowing fuse at bank:%d row:%d value:%d\n",
+ bank, row, value);
+ for (i = 0; i < 8; i++) {
+ if (((value >> i) & 0x1) == 0) {
+ continue;
+ }
+ if (fuse_blow(bank, row, i) != 0) {
+ diag_printf("fuse_blow(bank: %d, row: %d, bit: %d failed\n",
+ bank, row, i);
+ } else {
+ diag_printf("fuse_blow(bank: %d, row: %d, bit: %d successful\n",
+ bank, row, i);
+ }
+ }
+ sense_fuse(bank, row, 0);
+
+ } else {
+ diag_printf("Passing in wrong arguments: %d\n", argc);
+ }
+ /* Reset to default string */
+ strcpy(ready_to_blow, INIT_STRING);;
+}
+
+/* precondition: m>0 and n>0. Let g=gcd(m,n). */
+int gcd(int m, int n)
+{
+ int t;
+ while(m > 0) {
+ if(n > m) {t = m; m = n; n = t;} /* swap */
+ m -= n;
+ }
+ return n;
+}
+
+#define CLOCK_SRC_DETECT_MS 100
+#define CLOCK_IPG_DEFAULT 66500000
+#define CLOCK_SRC_DETECT_MARGIN 500000
+void mxc_show_clk_input(void)
+{
+// u32 c1, c2, diff, ipg_real, num = 0;
+
+ return; // FIXME
+#if 0
+ switch (prcs) {
+ case 0x01:
+ diag_printf("FPM enabled --> 32KHz input source\n");
+ return;
+ case 0x02:
+ break;
+ default:
+ diag_printf("Error %d: unknown clock source %d\n", __LINE__, prcs);
+ return;
+ }
+
+ // enable GPT with IPG clock input
+ writel(0x241, GPT_BASE_ADDR + GPTCR);
+ // prescaler = 1
+ writel(0, GPT_BASE_ADDR + GPTPR);
+
+ c1 = readl(GPT_BASE_ADDR + GPTCNT);
+ // use 32KHz input clock to get the delay
+ hal_delay_us(CLOCK_SRC_DETECT_MS * 1000);
+ c2 = readl(GPT_BASE_ADDR + GPTCNT);
+ diff = (c2 > c1) ? (c2 - c1) : (0xFFFFFFFF - c1 + c2);
+
+ ipg_real = diff * (1000 / CLOCK_SRC_DETECT_MS);
+
+ if (num != 0) {
+ diag_printf("Error: Actural clock input is %d MHz\n", num);
+ diag_printf(" ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n\n",
+ ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
+ hal_delay_us(2000000);
+ } else {
+ diag_printf("ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n\n",
+ ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
+ }
+#endif
+}
+
+RedBoot_init(mxc_show_clk_input, RedBoot_INIT_LAST);
+
+void imx_power_mode(int mode)
+{
+ volatile unsigned int val;
+ switch (mode) {
+ case 0:
+ diag_printf("WFI only\n");
+ break;
+ case 1:
+ diag_printf("Entering WAIT mode\n");
+ // wait mode - from validation code
+ // Set DSM_INT_HOLDOFF bit in TZIC
+ // If the TZIC didn't write the bit then there was interrupt pending
+ // It will be serviced while we're in the loop
+ // So we write to this bit again
+ while (readl(INTC_BASE_ADDR + 0x14) == 0) {
+ writel(1, INTC_BASE_ADDR + 0x14);
+ // Wait few cycles
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ }
+ val = readl(CCM_BASE_ADDR + 0x74);
+ val = (val & 0xfffffffc) | 0x1; // set WAIT mode
+ writel(val, CCM_BASE_ADDR + 0x74);
+ val = readl(PLATFORM_LPC_REG);
+ writel(val | (1 << 16), PLATFORM_LPC_REG);// ENABLE DSM in ELBOW submodule of ARM platform
+ val = readl(PLATFORM_LPC_REG);
+ writel(val | (1 << 17), PLATFORM_LPC_REG);// ENABLE DSM in ELBOW submodule of ARM platform
+ break;
+ case 2:
+ diag_printf("Entering stop mode\n");
+ hal_delay_us(100);
+ // stop mode - from validation code
+ // Set DSM_INT_HOLDOFF bit in TZIC
+ // If the TZIC didn't write the bit then there was interrupt pending
+ // It will be serviced while we're in the loop
+ // So we write to this bit again
+ while (readl(INTC_BASE_ADDR + 0x14) == 0) {
+ writel(1, INTC_BASE_ADDR + 0x14);
+ // Wait few cycles
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ }
+ val = readl(CCM_BASE_ADDR + 0x74);
+ val = (val & 0xfffffffc) | 0x2; // set STOP mode
+ writel(val, CCM_BASE_ADDR + 0x74);
+ val = readl(PLATFORM_LPC_REG);
+ writel(val | (3 << 16), PLATFORM_LPC_REG);// ENABLE DSM in ELBOW submodule of ARM platform
+
+ // power gating these peripherals
+ writel(0x0000030f, GPC_PGR);
+ writel(0x1, SRPGCR_EMI);
+ writel(0x1, SRPGCR_ARM);
+ writel(0x1, PGC_PGCR_VPU);
+ writel(0x1, PGC_PGCR_IPU);
+ break;
+ default:
+ diag_printf("Unknown low power mode: %d\n", mode);
+ return;
+ }
+
+ asm("mov r1, #0");
+ asm("mcr p15, 0, r1, c7, c0, 4");
+}
+
+void do_power_mode(int argc, char *argv[])
+{
+ int mode;
+
+ if (argc == 1) {
+ diag_printf("Useage: power_mode <mode>\n");
+ return;
+ } else if (argc == 2) {
+ if (!parse_num(*(&argv[1]), (unsigned long *)&mode, &argv[1], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ imx_power_mode(mode);
+
+ } else {
+ diag_printf("Passing in wrong arguments: %d\n", argc);
+ diag_printf("Useage: power_mode <mode>\n");
+ }
+}
+
+/*
+ * This command is added for burning IIM fuses
+ */
+RedBoot_cmd("power_mode",
+ "Enter various power modes:",
+ "\n\
+ <0> - WAIT\n\
+ <1> - SRPG\n\
+ <2> - STOP\n\
+ <3> - STOP with Power-Gating\n\
+ -- need reset after issuing the command",
+ do_power_mode
+ );
+
--- /dev/null
+/*=============================================================================
+//
+// hal_diag.c
+//
+// HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_arch.h> // basic machine info
+#include <cyg/hal/hal_intr.h> // interrupt macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_if.h> // Calling interface definitions
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/drv_api.h> // cyg_drv_interrupt_acknowledge
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+
+/*
+ * UART Control Register 0 Bit Fields.
+ */
+#define EUartUCR1_ADEN (1 << 15) // Auto dectect interrupt
+#define EUartUCR1_ADBR (1 << 14) // Auto detect baud rate
+#define EUartUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable
+#define EUartUCR1_IDEN (1 << 12) // Idle condition interrupt
+#define EUartUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable
+#define EUartUCR1_RDMAEN (1 << 8) // Recv ready DMA enable
+#define EUartUCR1_IREN (1 << 7) // Infrared interface enable
+#define EUartUCR1_TXMPTYEN (1 << 6) // Transimitter empty interrupt enable
+#define EUartUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable
+#define EUartUCR1_SNDBRK (1 << 4) // Send break
+#define EUartUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable
+#define EUartUCR1_DOZE (1 << 1) // Doze
+#define EUartUCR1_UARTEN (1 << 0) // UART enabled
+#define EUartUCR2_ESCI (1 << 15) // Escape seq interrupt enable
+#define EUartUCR2_IRTS (1 << 14) // Ignore RTS pin
+#define EUartUCR2_CTSC (1 << 13) // CTS pin control
+#define EUartUCR2_CTS (1 << 12) // Clear to send
+#define EUartUCR2_ESCEN (1 << 11) // Escape enable
+#define EUartUCR2_PREN (1 << 8) // Parity enable
+#define EUartUCR2_PROE (1 << 7) // Parity odd/even
+#define EUartUCR2_STPB (1 << 6) // Stop
+#define EUartUCR2_WS (1 << 5) // Word size
+#define EUartUCR2_RTSEN (1 << 4) // Request to send interrupt enable
+#define EUartUCR2_ATEN (1 << 3) // Aging timer enable
+#define EUartUCR2_TXEN (1 << 2) // Transmitter enabled
+#define EUartUCR2_RXEN (1 << 1) // Receiver enabled
+#define EUartUCR2_SRST_ (1 << 0) // SW reset
+#define EUartUCR3_PARERREN (1 << 12) // Parity enable
+#define EUartUCR3_FRAERREN (1 << 11) // Frame error interrupt enable
+#define EUartUCR3_ADNIMP (1 << 7) // Autobaud detection not improved
+#define EUartUCR3_RXDSEN (1 << 6) // Receive status interrupt enable
+#define EUartUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable
+#define EUartUCR3_AWAKEN (1 << 4) // Async wake interrupt enable
+#define EUartUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected
+#define EUartUCR3_INVT (1 << 1) // Inverted Infrared transmission
+#define EUartUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable
+#define EUartUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars)
+#define EUartUCR4_INVR (1 << 9) // Inverted infrared reception
+#define EUartUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable
+#define EUartUCR4_WKEN (1 << 7) // Wake interrupt enable
+#define EUartUCR4_IRSC (1 << 5) // IR special case
+#define EUartUCR4_LPBYP (1 << 4) // Low power bypass
+#define EUartUCR4_TCEN (1 << 3) // Transmit complete interrupt enable
+#define EUartUCR4_BKEN (1 << 2) // Break condition interrupt enable
+#define EUartUCR4_OREN (1 << 1) // Receiver overrun interrupt enable
+#define EUartUCR4_DREN (1 << 0) // Recv data ready interrupt enable
+#define EUartUFCR_RXTL_SHF 0 // Receiver trigger level shift
+#define EUartUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div 1)
+#define EUartUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div 2)
+#define EUartUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3)
+#define EUartUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4)
+#define EUartUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5)
+#define EUartUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6)
+#define EUartUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7)
+#define EUartUFCR_TXTL_SHF 10 // Transmitter trigger level shift
+#define EUartUSR1_PARITYERR (1 << 15) // Parity error interrupt flag
+#define EUartUSR1_RTSS (1 << 14) // RTS pin status
+#define EUartUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag
+#define EUartUSR1_RTSD (1 << 12) // RTS delta
+#define EUartUSR1_ESCF (1 << 11) // Escape seq interrupt flag
+#define EUartUSR1_FRAMERR (1 << 10) // Frame error interrupt flag
+#define EUartUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag
+#define EUartUSR1_AGTIM (1 << 8) // Aging timeout interrupt status
+#define EUartUSR1_RXDS (1 << 6) // Receiver idle interrupt flag
+#define EUartUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag
+#define EUartUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag
+#define EUartUSR2_ADET (1 << 15) // Auto baud rate detect complete
+#define EUartUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty
+#define EUartUSR2_IDLE (1 << 12) // Idle condition
+#define EUartUSR2_ACST (1 << 11) // Autobaud counter stopped
+#define EUartUSR2_IRINT (1 << 8) // Serial infrared interrupt flag
+#define EUartUSR2_WAKE (1 << 7) // Wake
+#define EUartUSR2_RTSF (1 << 4) // RTS edge interrupt flag
+#define EUartUSR2_TXDC (1 << 3) // Transmitter complete
+#define EUartUSR2_BRCD (1 << 2) // Break condition
+#define EUartUSR2_ORE (1 << 1) // Overrun error
+#define EUartUSR2_RDR (1 << 0) // Recv data ready
+#define EUartUTS_FRCPERR (1 << 13) // Force parity error
+#define EUartUTS_LOOP (1 << 12) // Loop tx and rx
+#define EUartUTS_TXEMPTY (1 << 6) // TxFIFO empty
+#define EUartUTS_RXEMPTY (1 << 5) // RxFIFO empty
+#define EUartUTS_TXFULL (1 << 4) // TxFIFO full
+#define EUartUTS_RXFULL (1 << 3) // RxFIFO full
+#define EUartUTS_SOFTRST (1 << 0) // Software reset
+
+#define EUartUFCR_RFDIV EUartUFCR_RFDIV_2
+//#define EUartUFCR_RFDIV EUartUFCR_RFDIV_4
+//#define EUartUFCR_RFDIV EUartUFCR_RFDIV_7
+
+#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_2)
+#define MXC_UART_REFFREQ (get_peri_clock(UART1_BAUD) / 2)
+#endif
+
+#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_4)
+#define MXC_UART_REFFREQ (get_peri_clock(UART1_BAUD) / 4)
+#endif
+
+#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_7)
+#define MXC_UART_REFFREQ (get_peri_clock(UART1_BAUD) / 7)
+#endif
+
+#if 0
+void
+cyg_hal_plf_comms_init(void)
+{
+ static int initialized = 0;
+
+ if (initialized)
+ return;
+
+ initialized = 1;
+
+ cyg_hal_plf_serial_init();
+}
+#endif
+
+//=============================================================================
+// MXC Serial Port (UARTx) for Debug
+//=============================================================================
+#ifdef UART_WIDTH_32
+struct mxc_serial {
+ volatile cyg_uint32 urxd[16];
+ volatile cyg_uint32 utxd[16];
+ volatile cyg_uint32 ucr1;
+ volatile cyg_uint32 ucr2;
+ volatile cyg_uint32 ucr3;
+ volatile cyg_uint32 ucr4;
+ volatile cyg_uint32 ufcr;
+ volatile cyg_uint32 usr1;
+ volatile cyg_uint32 usr2;
+ volatile cyg_uint32 uesc;
+ volatile cyg_uint32 utim;
+ volatile cyg_uint32 ubir;
+ volatile cyg_uint32 ubmr;
+ volatile cyg_uint32 ubrc;
+ volatile cyg_uint32 onems;
+ volatile cyg_uint32 uts;
+};
+#else
+struct mxc_serial {
+ volatile cyg_uint16 urxd[1];
+ volatile cyg_uint16 resv0[31];
+
+ volatile cyg_uint16 utxd[1];
+ volatile cyg_uint16 resv1[31];
+ volatile cyg_uint16 ucr1;
+ volatile cyg_uint16 resv2;
+ volatile cyg_uint16 ucr2;
+ volatile cyg_uint16 resv3;
+ volatile cyg_uint16 ucr3;
+ volatile cyg_uint16 resv4;
+ volatile cyg_uint16 ucr4;
+ volatile cyg_uint16 resv5;
+ volatile cyg_uint16 ufcr;
+ volatile cyg_uint16 resv6;
+ volatile cyg_uint16 usr1;
+ volatile cyg_uint16 resv7;
+ volatile cyg_uint16 usr2;
+ volatile cyg_uint16 resv8;
+ volatile cyg_uint16 uesc;
+ volatile cyg_uint16 resv9;
+ volatile cyg_uint16 utim;
+ volatile cyg_uint16 resv10;
+ volatile cyg_uint16 ubir;
+ volatile cyg_uint16 resv11;
+ volatile cyg_uint16 ubmr;
+ volatile cyg_uint16 resv12;
+ volatile cyg_uint16 ubrc;
+ volatile cyg_uint16 resv13;
+ volatile cyg_uint16 onems;
+ volatile cyg_uint16 resv14;
+ volatile cyg_uint16 uts;
+ volatile cyg_uint16 resv15;
+};
+#endif
+
+typedef struct {
+ volatile struct mxc_serial* base;
+ cyg_int32 msec_timeout;
+ int isr_vector;
+ int baud_rate;
+} channel_data_t;
+
+static channel_data_t channels[] = {
+#if CYGHWR_HAL_ARM_SOC_UART1 != 0
+ {(volatile struct mxc_serial*)UART1_BASE_ADDR, 1000,
+ CYGNUM_HAL_INTERRUPT_UART1, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#endif
+#if CYGHWR_HAL_ARM_SOC_UART2 != 0
+ {(volatile struct mxc_serial*)UART2_BASE_ADDR, 1000,
+ CYGNUM_HAL_INTERRUPT_UART2, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#endif
+#if CYGHWR_HAL_ARM_SOC_UART3 != 0
+ {(volatile struct mxc_serial*)UART3_BASE_ADDR, 1000,
+ CYGNUM_HAL_INTERRUPT_UART3, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#endif
+};
+
+/*---------------------------------------------------------------------------*/
+
+static void init_serial_channel(channel_data_t* __ch_data)
+{
+ volatile struct mxc_serial* base = __ch_data->base;
+
+ /* Wait for UART to finish transmitting */
+ while (!(base->uts & EUartUTS_TXEMPTY));
+
+ /* Disable UART */
+ base->ucr1 &= ~EUartUCR1_UARTEN;
+
+ /* Set to default POR state */
+ base->ucr1 = 0x00000000;
+ base->ucr2 = 0x00000000;
+
+ while (!(base->ucr2 & EUartUCR2_SRST_));
+
+ base->ucr3 = 0x00000704;
+ base->ucr4 = 0x00008000;
+ base->ufcr = 0x00000801;
+ base->uesc = 0x0000002B;
+ base->utim = 0x00000000;
+ base->ubir = 0x00000000;
+ base->ubmr = 0x00000000;
+ base->onems = 0x00000000;
+ base->uts = 0x00000000;
+
+ /* Configure FIFOs */
+ base->ufcr = (1 << EUartUFCR_RXTL_SHF) | EUartUFCR_RFDIV
+ | (2 << EUartUFCR_TXTL_SHF);
+
+ /* Setup One MS timer */
+ base->onems = (MXC_UART_REFFREQ / 1000);
+
+ /* Set to 8N1 */
+ base->ucr2 &= ~EUartUCR2_PREN;
+ base->ucr2 |= EUartUCR2_WS;
+ base->ucr2 &= ~EUartUCR2_STPB;
+
+ /* Ignore RTS */
+ base->ucr2 |= EUartUCR2_IRTS;
+
+ /* Enable UART */
+ base->ucr1 |= EUartUCR1_UARTEN;
+
+ /* Enable FIFOs */
+ base->ucr2 |= EUartUCR2_SRST_ | EUartUCR2_RXEN | EUartUCR2_TXEN;
+
+ /* Clear status flags */
+ base->usr2 |= EUartUSR2_ADET |
+ EUartUSR2_IDLE |
+ EUartUSR2_IRINT |
+ EUartUSR2_WAKE |
+ EUartUSR2_RTSF |
+ EUartUSR2_BRCD |
+ EUartUSR2_ORE |
+ EUartUSR2_RDR;
+
+ /* Clear status flags */
+ base->usr1 |= EUartUSR1_PARITYERR |
+ EUartUSR1_RTSD |
+ EUartUSR1_ESCF |
+ EUartUSR1_FRAMERR |
+ EUartUSR1_AIRINT |
+ EUartUSR1_AWAKE;
+
+ /* Set the numerator value minus one of the BRM ratio */
+ base->ubir = (__ch_data->baud_rate / 100) - 1;
+
+ /* Set the denominator value minus one of the BRM ratio */
+ base->ubmr = ((MXC_UART_REFFREQ / 1600) - 1);
+
+}
+
+static void stop_serial_channel(channel_data_t* __ch_data)
+{
+ volatile struct mxc_serial* base = __ch_data->base;
+
+ /* Wait for UART to finish transmitting */
+ while (!(base->uts & EUartUTS_TXEMPTY));
+
+ /* Disable UART */
+ base->ucr1 &= ~EUartUCR1_UARTEN;
+}
+
+//#define debug_uart_log_buf
+#ifdef debug_uart_log_buf
+#define DIAG_BUFSIZE 2048
+static char __log_buf[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+
+void cyg_hal_plf_serial_putc(void *__ch_data, char c)
+{
+ volatile struct mxc_serial* base = ((channel_data_t*)__ch_data)->base;
+
+#ifdef debug_uart_log_buf
+ __log_buf[diag_bp++] = c;
+ return;
+#endif
+
+ CYGARC_HAL_SAVE_GP();
+
+ // Wait for Tx FIFO not full
+ while (base->uts & EUartUTS_TXFULL)
+ ;
+ base->utxd[0] = c;
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool cyg_hal_plf_serial_getc_nonblock(void* __ch_data,
+ cyg_uint8* ch)
+{
+ volatile struct mxc_serial* base = ((channel_data_t*)__ch_data)->base;
+
+ // If receive fifo is empty, return false
+ if (base->uts & EUartUTS_RXEMPTY)
+ return false;
+
+ *ch = (char)base->urxd[0];
+
+ return true;
+}
+
+cyg_uint8 cyg_hal_plf_serial_getc(void* __ch_data)
+{
+ cyg_uint8 ch;
+ CYGARC_HAL_SAVE_GP();
+
+ while (!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
+
+ CYGARC_HAL_RESTORE_GP();
+ return ch;
+}
+
+static void cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while(__len-- > 0)
+ cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static void cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while (__len-- > 0)
+ *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool cyg_hal_plf_serial_getc_timeout(void* __ch_data,
+ cyg_uint8* ch)
+{
+ int delay_count;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_bool res;
+ CYGARC_HAL_SAVE_GP();
+
+ delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+
+ for(;;) {
+ res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
+ if (res || 0 == delay_count--)
+ break;
+
+ CYGACC_CALL_IF_DELAY_US(100);
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static int cyg_hal_plf_serial_control(void *__ch_data,
+ __comm_control_cmd_t __func, ...)
+{
+ static int irq_state = 0;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ int ret = -1;
+ va_list ap;
+
+ CYGARC_HAL_SAVE_GP();
+ va_start(ap, __func);
+
+ switch (__func) {
+ case __COMMCTL_GETBAUD:
+ ret = chan->baud_rate;
+ break;
+ case __COMMCTL_SETBAUD:
+ chan->baud_rate = va_arg(ap, cyg_int32);
+ // Should we verify this value here?
+ init_serial_channel(chan);
+ ret = 0;
+ break;
+ case __COMMCTL_IRQ_ENABLE:
+ irq_state = 1;
+
+ chan->base->ucr1 |= EUartUCR1_RRDYEN;
+
+ HAL_INTERRUPT_UNMASK(chan->isr_vector);
+ break;
+ case __COMMCTL_IRQ_DISABLE:
+ ret = irq_state;
+ irq_state = 0;
+
+ chan->base->ucr1 &= ~EUartUCR1_RRDYEN;
+
+ HAL_INTERRUPT_MASK(chan->isr_vector);
+ break;
+ case __COMMCTL_DBG_ISR_VECTOR:
+ ret = chan->isr_vector;
+ break;
+ case __COMMCTL_SET_TIMEOUT:
+ ret = chan->msec_timeout;
+ chan->msec_timeout = va_arg(ap, cyg_uint32);
+ break;
+ default:
+ break;
+ }
+ va_end(ap);
+ CYGARC_HAL_RESTORE_GP();
+ return ret;
+}
+
+static int cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
+ CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+ int res = 0;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ char c;
+
+ CYGARC_HAL_SAVE_GP();
+
+ cyg_drv_interrupt_acknowledge(chan->isr_vector);
+
+ *__ctrlc = 0;
+ if (!(chan->base->uts & EUartUTS_RXEMPTY)) {
+ c = (char)chan->base->urxd[0];
+
+ if (cyg_hal_is_break( &c , 1 ))
+ *__ctrlc = 1;
+
+ res = CYG_ISR_HANDLED;
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+void cyg_hal_plf_serial_init(void)
+{
+ hal_virtual_comm_table_t* comm;
+ int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ int i;
+ static int jjj = 0;
+
+ // Init channels
+#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
+ for (i = 0; i < NUMOF(channels); i++) {
+ init_serial_channel(&channels[i]);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+ if (jjj == 0) {
+ cyg_hal_plf_serial_putc(&channels[i], '+');
+ jjj++;
+ }
+ cyg_hal_plf_serial_putc(&channels[i], '+');
+ }
+
+ // Restore original console
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+void cyg_hal_plf_serial_stop(void)
+{
+ int i;
+
+ // Init channels
+#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
+ for (i = 0; i < NUMOF(channels); i++) {
+ stop_serial_channel(&channels[i]);
+ }
+}
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
+
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 2)
+#define __BASE ((void*)UART1_BASE_ADDR)
+#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART1
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 3)
+#define __BASE ((void*)UART2_BASE_ADDR)
+#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART2
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 4)
+#define __BASE ((void*)UART3_BASE_ADDR)
+#endif
+
+#ifdef __BASE
+
+#ifdef CYGSEM_HAL_ROM_MONITOR
+#define CYG_HAL_STARTUP_ROM
+#define CYG_HAL_STARTUP_ROMRAM
+#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#endif
+
+#if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define HAL_DIAG_USES_HARDWARE
+#elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
+#define HAL_DIAG_USES_HARDWARE
+#elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+#define HAL_DIAG_USES_HARDWARE
+#endif
+
+static channel_data_t channel = {
+ (volatile struct mxc_serial*)__BASE, 0, CYGHWR_HAL_GDB_PORT_VECTOR
+};
+
+#ifdef HAL_DIAG_USES_HARDWARE
+
+void hal_diag_init(void)
+{
+ static int init = 0;
+ char *msg = "\n\rARM eCos\n\r";
+ cyg_uint8 lcr;
+
+ if (init++) return;
+
+ init_serial_channel(&channel);
+
+ while (*msg) hal_diag_write_char(*msg++);
+}
+
+#ifdef DEBUG_DIAG
+#ifndef CYG_HAL_STARTUP_ROM
+#define DIAG_BUFSIZE 2048
+static char diag_buffer[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+#endif
+
+void hal_diag_write_char(char c)
+{
+#ifdef DEBUG_DIAG
+#ifndef CYG_HAL_STARTUP_ROM
+ diag_buffer[diag_bp++] = c;
+ if (diag_bp == sizeof(diag_buffer)) diag_bp = 0;
+#endif
+#endif
+ cyg_hal_plf_serial_putc(&channel, c);
+}
+
+void hal_diag_read_char(char *c)
+{
+ *c = cyg_hal_plf_serial_getc(&channel);
+}
+
+#else // not HAL_DIAG_USES_HARDWARE - it uses GDB protocol
+
+void hal_diag_read_char(char *c)
+{
+ *c = cyg_hal_plf_serial_getc(&channel);
+}
+
+void hal_diag_write_char(char c)
+{
+ static char line[100];
+ static int pos = 0;
+
+ // FIXME: Some LED blinking might be nice right here.
+
+ // No need to send CRs
+ if( c == '\r' ) return;
+
+ line[pos++] = c;
+
+ if (c == '\n' || pos == sizeof(line)) {
+ CYG_INTERRUPT_STATE old;
+
+ // Disable interrupts. This prevents GDB trying to interrupt us
+ // while we are in the middle of sending a packet. The serial
+ // receive interrupt will be seen when we re-enable interrupts
+ // later.
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+#else
+ HAL_DISABLE_INTERRUPTS(old);
+#endif
+
+ while (1) {
+ static char hex[] = "0123456789ABCDEF";
+ cyg_uint8 csum = 0;
+ int i;
+#ifndef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ char c1;
+#endif
+ cyg_hal_plf_serial_putc(&channel, '$');
+ cyg_hal_plf_serial_putc(&channel, 'O');
+ csum += 'O';
+ for(i = 0; i < pos; i++) {
+ char ch = line[i];
+ char h = hex[(ch>>4)&0xF];
+ char l = hex[ch&0xF];
+ cyg_hal_plf_serial_putc(&channel, h);
+ cyg_hal_plf_serial_putc(&channel, l);
+ csum += h;
+ csum += l;
+ }
+ cyg_hal_plf_serial_putc(&channel, '#');
+ cyg_hal_plf_serial_putc(&channel, hex[(csum>>4)&0xF]);
+ cyg_hal_plf_serial_putc(&channel, hex[csum&0xF]);
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+
+ break; // regardless
+
+#else // not CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT Ie. usually...
+
+ // Wait for the ACK character '+' from GDB here and handle
+ // receiving a ^C instead. This is the reason for this clause
+ // being a loop.
+ c1 = cyg_hal_plf_serial_getc(&channel);
+
+ if( c1 == '+' )
+ break; // a good acknowledge
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ cyg_drv_interrupt_acknowledge(CYGHWR_HAL_GDB_PORT_VECTOR);
+ if( c1 == 3 ) {
+ // Ctrl-C: breakpoint.
+ cyg_hal_gdb_interrupt(
+ (target_register_t)__builtin_return_address(0) );
+ break;
+ }
+#endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+
+#endif // ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ // otherwise, loop round again
+ }
+
+ pos = 0;
+
+ // And re-enable interrupts
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+#else
+ HAL_RESTORE_INTERRUPTS(old);
+#endif
+
+ }
+}
+#endif
+
+#endif // __BASE
+
+#endif // !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
+/* End of hal_diag.c */
--- /dev/null
+//==========================================================================
+//
+// soc_misc.c
+//
+// HAL misc board support code
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#include <redboot.h>
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_misc.h> // Size constants
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h> // Interrupt names
+#include <cyg/hal/hal_cache.h> // Cache control
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/hal_mm.h> // MMap table definitions
+
+#include <cyg/infra/diag.h> // diag_printf
+
+// Most initialization has already been done before we get here.
+// All we do here is set up the interrupt environment.
+// FIXME: some of the stuff in hal_platform_setup could be moved here.
+
+externC void plf_hardware_init(void);
+int _mxc_boot, _mxc_fis;
+
+#define IIM_PROD_REV_SH 3
+#define IIM_PROD_REV_LEN 5
+#define IIM_SREV_REV_SH 4
+#define IIM_SREV_REV_LEN 4
+#define PROD_SIGNATURE_MX37 0x1
+
+#define PROD_SIGNATURE_SUPPORTED PROD_SIGNATURE_MX37
+
+#define CHIP_VERSION_NONE 0xFFFFFFFF // invalid product ID
+#define CHIP_VERSION_UNKNOWN 0xDEADBEEF // invalid chip rev
+
+/*
+ * System_rev will have the following format
+ * 31-12 = part # (0x31, 0x32, 0x27, 0x91131, 0x91321, etc)
+ * 11-8 = PMIC ID
+ * 7-4 = major (1.y)
+ * 3-0 = minor (x.0)
+ */
+unsigned int system_rev = CHIP_REV_1_0;
+static int find_correct_chip;
+extern char HAL_PLATFORM_EXTRA[20];
+
+/*
+ * This functions reads the IIM module and returns the system revision number.
+ * It returns the IIM silicon revision reg value if valid product rev is found.
+ . Otherwise, it returns -1.
+ */
+static int read_system_rev(void)
+{
+ int val;
+
+ val = readl(IIM_BASE_ADDR + IIM_PREV_OFF);
+
+ system_rev = 0x37 << PART_NUMBER_OFFSET; /* For MX37 Platform*/
+
+ /* Now trying to retrieve the silicon rev from IIM's SREV register */
+ return readl(IIM_BASE_ADDR + IIM_SREV_OFF);
+}
+
+extern nfc_setup_func_t *nfc_setup;
+unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz,
+ unsigned int is_mlc, unsigned int num_of_chips);
+void hal_hardware_init(void)
+{
+ volatile unsigned int esdmisc = readl(ESDCTL_BASE + 0x10);
+ volatile unsigned int esdctl0 = readl(ESDCTL_BASE);
+ volatile unsigned int sbmr;
+ int bt_mem_type = 0, bt_mem_control = 0;
+ int ver = read_system_rev();
+ unsigned int *fis_addr = (unsigned int *)IRAM_BASE_ADDR;
+
+ switch (*fis_addr) {
+ case FROM_MMC_FLASH:
+ _mxc_fis = FROM_MMC_FLASH;
+ break;
+ case FROM_NAND_FLASH:
+ _mxc_fis = FROM_NAND_FLASH;
+ break;
+ default:
+ sbmr = readl(SRC_BASE_ADDR + 0x4);
+ bt_mem_control = sbmr & 0x3;
+ bt_mem_type = (sbmr & 0x180) >> 7;
+ if (bt_mem_control == 0x3) {
+ if (bt_mem_type == 0) {
+ _mxc_fis = FROM_MMC_FLASH;
+ _mxc_boot = FROM_MMC_FLASH;
+ } else if (bt_mem_type == 3) {
+ _mxc_fis = FROM_SPI_NOR_FLASH;
+ _mxc_boot = FROM_SPI_NOR_FLASH;
+ }
+ } else if (bt_mem_control == 0x1) {
+ _mxc_fis = FROM_NAND_FLASH;
+ _mxc_boot = FROM_NAND_FLASH;
+ }
+ }
+
+ find_correct_chip = ver;
+
+ if (ver != CHIP_VERSION_NONE) {
+ /* Valid product revision found. Check actual silicon rev and
+ * NOT use the version from the ROM code. */
+ if (((ver >> 4) & 0xF) == 0x0) {
+ HAL_PLATFORM_EXTRA[5] = '1';
+ HAL_PLATFORM_EXTRA[7] = '0';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ } else if (((ver >> 4) & 0xF) == 0x1) {
+ HAL_PLATFORM_EXTRA[5] = '1';
+ HAL_PLATFORM_EXTRA[7] = '1';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 1 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ } else {
+ HAL_PLATFORM_EXTRA[5] = 'x';
+ HAL_PLATFORM_EXTRA[7] = 'x';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 1 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ find_correct_chip = CHIP_VERSION_UNKNOWN;
+ }
+ }
+
+ if ((esdmisc & 0x4) == 0) {
+ HAL_PLATFORM_EXTRA[14] = 'S';
+ }
+ if ((esdctl0 & 0x30000) != 0x20000) {
+ HAL_PLATFORM_EXTRA[11] = '1';
+ HAL_PLATFORM_EXTRA[12] = '6';
+ }
+
+ // Enable caches
+ HAL_ICACHE_ENABLE();
+ HAL_DCACHE_ENABLE();
+
+ // enable EPIT and start it with 32KHz input clock
+ writel(0x00010000, EPIT_BASE_ADDR + EPITCR);
+
+ // make sure reset is complete
+ while ((readl(EPIT_BASE_ADDR + EPITCR) & 0x10000) != 0) {
+ }
+
+ writel(0x030E0002, EPIT_BASE_ADDR + EPITCR);
+ writel(0x030E0003, EPIT_BASE_ADDR + EPITCR);
+
+ writel(0, EPIT_BASE_ADDR + EPITCMPR); // always compare with 0
+
+ if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
+ // increase the WDOG timeout value to the max
+ writew(readw(WDOG_BASE_ADDR) | 0xFF00, WDOG_BASE_ADDR);
+ }
+
+ // Perform any platform specific initializations
+ plf_hardware_init();
+
+ // Set up eCos/ROM interfaces
+ hal_if_init();
+
+ nfc_setup = (nfc_setup_func_t*)mxc_nfc_soc_setup;
+}
+
+// -------------------------------------------------------------------------
+void hal_clock_initialize(cyg_uint32 period)
+{
+}
+
+// This routine is called during a clock interrupt.
+
+// Define this if you want to ensure that the clock is perfect (i.e. does
+// not drift). One reason to leave it turned off is that it costs some
+// us per system clock interrupt for this maintenance.
+#undef COMPENSATE_FOR_CLOCK_DRIFT
+
+void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
+{
+}
+
+// Read the current value of the clock, returning the number of hardware
+// "ticks" that have occurred (i.e. how far away the current value is from
+// the start)
+
+// Note: The "contract" for this function is that the value is the number
+// of hardware clocks that have happened since the last interrupt (i.e.
+// when it was reset). This value is used to measure interrupt latencies.
+// However, since the hardware counter runs freely, this routine computes
+// the difference between the current clock period and the number of hardware
+// ticks left before the next timer interrupt.
+void hal_clock_read(cyg_uint32 *pvalue)
+{
+}
+
+// This is to cope with the test read used by tm_basic with
+// CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY defined; we read the count ASAP
+// in the ISR, *before* resetting the clock. Which returns 1tick +
+// latency if we just use plain hal_clock_read().
+void hal_clock_latency(cyg_uint32 *pvalue)
+{
+}
+
+unsigned int hal_timer_count(void)
+{
+ return (0xFFFFFFFF - readl(EPIT_BASE_ADDR + EPITCNR));
+}
+
+#define WDT_MAGIC_1 0x5555
+#define WDT_MAGIC_2 0xAAAA
+#define MXC_WDT_WSR 0x2
+
+unsigned int i2c_base_addr[] = {
+ I2C_BASE_ADDR,
+ I2C2_BASE_ADDR,
+ I2C3_BASE_ADDR
+};
+unsigned int i2c_num = 3;
+
+//
+// Delay for some number of micro-seconds
+//
+void hal_delay_us(unsigned int usecs)
+{
+ /*
+ * This causes overflow.
+ * unsigned int delayCount = (usecs * 32768) / 1000000;
+ * So use the following one instead
+ */
+ unsigned int delayCount = (usecs * 512) / 15625;
+
+ if (delayCount == 0) {
+ return;
+ }
+
+ // issue the service sequence instructions
+ if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
+ writew(WDT_MAGIC_1, WDOG_BASE_ADDR + MXC_WDT_WSR);
+ writew(WDT_MAGIC_2, WDOG_BASE_ADDR + MXC_WDT_WSR);
+ }
+
+ writel(0x01, EPIT_BASE_ADDR + EPITSR); // clear the compare status bit
+
+ writel(delayCount, EPIT_BASE_ADDR + EPITLR);
+
+ while ((0x1 & readl(EPIT_BASE_ADDR + EPITSR)) == 0); // return until compare bit is set
+}
+
+// -------------------------------------------------------------------------
+
+// This routine is called to respond to a hardware interrupt (IRQ). It
+// should interrogate the hardware and return the IRQ vector number.
+int hal_IRQ_handler(void)
+{
+#ifdef HAL_EXTENDED_IRQ_HANDLER
+ cyg_uint32 index;
+
+ // Use platform specific IRQ handler, if defined
+ // Note: this macro should do a 'return' with the appropriate
+ // interrupt number if such an extended interrupt exists. The
+ // assumption is that the line after the macro starts 'normal' processing.
+ HAL_EXTENDED_IRQ_HANDLER(index);
+#endif
+
+ return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
+}
+
+//
+// Interrupt control
+//
+
+void hal_interrupt_mask(int vector)
+{
+// diag_printf("6hal_interrupt_mask(vector=%d) \n", vector);
+#ifdef HAL_EXTENDED_INTERRUPT_MASK
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_MASK(vector);
+#endif
+}
+
+void hal_interrupt_unmask(int vector)
+{
+// diag_printf("7hal_interrupt_unmask(vector=%d) \n", vector);
+
+#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_UNMASK(vector);
+#endif
+}
+
+void hal_interrupt_acknowledge(int vector)
+{
+
+// diag_printf("8hal_interrupt_acknowledge(vector=%d) \n", vector);
+#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector);
+#endif
+}
+
+void hal_interrupt_configure(int vector, int level, int up)
+{
+
+#ifdef HAL_EXTENDED_INTERRUPT_CONFIGURE
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_CONFIGURE(vector, level, up);
+#endif
+}
+
+void hal_interrupt_set_level(int vector, int level)
+{
+
+#ifdef HAL_EXTENDED_INTERRUPT_SET_LEVEL
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_SET_LEVEL(vector, level);
+#endif
+
+ // Interrupt priorities are not configurable.
+}
+
+unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz, unsigned int is_mlc, unsigned int num_of_chips)
+{
+ return 0x20; // NFC version 2
+}
+
+static void check_correct_chip(void)
+{
+ if (find_correct_chip == CHIP_VERSION_UNKNOWN) {
+ diag_printf("Unrecognized chip version: 0x%x!!!\n", read_system_rev());
+ diag_printf("Assuming chip version=0x%x\n", system_rev);
+ } else if (find_correct_chip == CHIP_VERSION_NONE) {
+ diag_printf("Unrecognized chip: 0x%x!!!\n", readl(IIM_BASE_ADDR + IIM_PREV_OFF));
+ }
+}
+
+RedBoot_init(check_correct_chip, RedBoot_INIT_LAST);
--- /dev/null
+# ====================================================================
+#
+# hal_arm_board.cdl
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+
+cdl_package CYGPKG_HAL_ARM_MX51_3STACK {
+ display "Freescale board"
+ parent CYGPKG_HAL_ARM_MX51
+ hardware
+ include_dir cyg/hal
+ define_header hal_arm_board.h
+ description "
+ This HAL platform package provides generic
+ support for the Freescale MX51 3-Stack Board."
+
+ compile board_misc.c board_diag.c
+ implements CYGINT_HAL_DEBUG_GDB_STUBS
+ implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+ implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+
+ #implements CYGHWR_HAL_ARM_DUART_UARTB
+ implements CYGHWR_HAL_ARM_SOC_UART1
+ #implements CYGHWR_HAL_ARM_SOC_UART2
+ #implements CYGHWR_HAL_ARM_SOC_UART3
+
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_soc.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_board.h>"
+ puts $::cdl_header "#define HAL_PLATFORM_CPU \"Freescale i.MX51 based\""
+ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"MX51 3-Stack\""
+ puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 1696"
+ puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK board_program_new_stack"
+ }
+
+ cdl_component CYG_HAL_STARTUP {
+ display "Startup type"
+ flavor data
+ default_value {"ROM"}
+ legal_values {"RAM" "ROM" "ROMRAM"}
+ no_define
+ define -file system.h CYG_HAL_STARTUP
+ description "
+ When targetting the eval board it is possible to build
+ the system for either RAM bootstrap or ROM bootstrap(s). Select
+ 'ram' when building programs to load into RAM using eCos GDB
+ stubs. Select 'rom' when building a stand-alone application
+ which will be put into ROM, or for the special case of
+ building the eCos GDB stubs themselves. Using ROMRAM will allow
+ the program to exist in ROM, but be copied to RAM during startup."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_DUART_UARTA {
+ display "ST16552 UARTA available as diagnostic/debug channel"
+ description "
+ The board has a ST16552 DUART chip. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_DUART_UARTB {
+ display "ST16552 UARTB available as diagnostic/debug channel"
+ description "
+ The board has a ST16552 DUART chip. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ display "Diagnostic serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the console port.
+ Note: this should match the value chosen for the GDB port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ display "GDB serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the GDB port.
+ Note: this should match the value chosen for the console port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the board"
+ flavor data
+ calculated 6
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ The board has three serial ports. This option
+ chooses which port will be used to connect to a host
+ running GDB."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+ display "Default console channel."
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ calculated 0
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Console serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ description "
+ The board has only three serial ports. This option
+ chooses which port will be used for console output."
+ }
+
+ cdl_component CYGBLD_GLOBAL_OPTIONS {
+ display "Global build options"
+ flavor none
+ no_define
+ description "
+ Global build options including control over
+ compiler flags, linker flags and choice of toolchain."
+
+
+ parent CYGPKG_NONE
+
+ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ display "Global command prefix"
+ flavor data
+ no_define
+ default_value { "arm-none-eabi" }
+ description "
+ This option specifies the command prefix used when
+ invoking the build tools."
+ }
+
+ cdl_option CYGBLD_GLOBAL_CFLAGS {
+ display "Global compiler flags"
+ flavor data
+ no_define
+ default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ description "
+ This option controls the global compiler flags which are used to
+ compile all packages by default. Individual packages may define
+ options which override these global flags."
+ }
+
+ cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ display "Global linker flags"
+ flavor data
+ no_define
+ default_value { "-Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" }
+ description "
+ This option controls the global linker flags. Individual
+ packages may define options which override these global flags."
+ }
+
+ cdl_option CYGBLD_BUILD_GDB_STUBS {
+ display "Build GDB stub ROM image"
+ default_value 0
+ requires { CYG_HAL_STARTUP == "ROM" }
+ requires CYGSEM_HAL_ROM_MONITOR
+ requires CYGBLD_BUILD_COMMON_GDB_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ no_define
+ description "
+ This option enables the building of the GDB stubs for the
+ board. The common HAL controls takes care of most of the
+ build process, but the final conversion from ELF image to
+ binary data is handled by the platform CDL, allowing
+ relocation of the data if necessary."
+
+ make -priority 320 {
+ <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
+ $(OBJCOPY) --remove-section=.fixed_vectors -O binary $< $@
+ }
+ }
+ }
+
+ cdl_component CYGPKG_HAL_ARM_BOARD_OPTIONS {
+ display "Freescale MXC Board build options"
+ flavor none
+ no_define
+ description "
+ Package specific build options including control over
+ compiler flags used only in building this package,
+ and details of which tests are built."
+
+ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the board HAL. These flags are used in addition
+ to the set of global flags."
+ }
+
+ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_REMOVE {
+ display "Suppressed compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the board HAL. These flags are removed from
+ the set of global flags if present."
+ }
+
+ }
+
+ cdl_component CYGHWR_MEMORY_LAYOUT {
+ display "Memory layout"
+ flavor data
+ no_define
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_board_ram" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" :
+ "arm_board_rom" }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ display "Memory layout linker script fragment"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.ldi>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.ldi>" :
+ "<pkgconf/mlt_arm_board_rom.ldi>" }
+ }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ display "Memory layout header file"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_H
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.h>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.h>" :
+ "<pkgconf/mlt_arm_board_rom.h>" }
+ }
+ }
+
+ cdl_option CYGSEM_HAL_ROM_MONITOR {
+ display "Behave as a ROM monitor"
+ flavor bool
+ default_value 0
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+ description "
+ Enable this option if this program is to be used as a ROM monitor,
+ i.e. applications will be loaded into RAM on the board, and this
+ ROM monitor may process exceptions or interrupts generated from the
+ application. This enables features such as utilizing a separate
+ interrupt stack when exceptions are generated."
+ }
+
+ cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ display "Work with a ROM monitor"
+ flavor booldata
+ legal_values { "Generic" "GDB_stubs" }
+ default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "RAM" }
+ description "
+ Support can be enabled for different varieties of ROM monitor.
+ This support changes various eCos semantics such as the encoding
+ of diagnostic output, or the overriding of hardware interrupt
+ vectors.
+ Firstly there is \"Generic\" support which prevents the HAL
+ from overriding the hardware vectors that it does not use, to
+ instead allow an installed ROM monitor to handle them. This is
+ the most basic support which is likely to be common to most
+ implementations of ROM monitor.
+ \"GDB_stubs\" provides support when GDB stubs are included in
+ the ROM monitor or boot ROM."
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ display "Redboot HAL options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+ description "
+ This option lists the target's requirements for a valid Redboot
+ configuration."
+
+ compile -library=libextras.a redboot_cmds.c
+
+ cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ display "Build Redboot ROM binary image"
+ active_if CYGBLD_BUILD_REDBOOT
+ default_value 1
+ no_define
+ description "This option enables the conversion of the Redboot ELF
+ image to a binary image suitable for ROM programming."
+
+ make -priority 325 {
+ <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+ $(OBJCOPY) -O binary $< $@
+ }
+ }
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_BOARD_OPTIONS {
+ display "Redboot HAL variant options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+
+ # RedBoot details
+ requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x90008000 }
+ define_proc {
+ puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00"
+ }
+ }
+}
--- /dev/null
+#ifndef CYGONCE_FSL_BOARD_H
+#define CYGONCE_FSL_BOARD_H
+
+//=============================================================================
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+
+/* CPLD offsets */
+#define PBC_LED_CTRL (0x20000)
+#define PBC_SB_STAT (0x20008)
+#define PBC_ID_AAAA (0x20040)
+#define PBC_ID_5555 (0x20048)
+#define PBC_VERSION (0x20050)
+#define PBC_ID_CAFE (0x20058)
+#define PBC_INT_STAT (0x20010)
+#define PBC_INT_MASK (0x20038)
+#define PBC_INT_REST (0x20020)
+#define PBC_SW_RESET (0x20060)
+#define BOARD_CS_UART_BASE (0x8000)
+
+#define FEC_PHY_ADDR 0x06
+#define REDBOOT_IMAGE_SIZE 0x40000
+
+#define EXT_UART_x16
+/* MX51 3-Stack SDRAM is from 0x40000000, 128M */
+#define SDRAM_BASE_ADDR CSD0_BASE_ADDR
+#define SDRAM_SIZE 0x08000000
+#define RAM_BANK0_BASE SDRAM_BASE_ADDR
+
+#define LED_MAX_NUM 8
+
+#endif /* CYGONCE_FSL_BOARD_H */
--- /dev/null
+#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
+#define CYGONCE_HAL_PLATFORM_SETUP_H
+
+//=============================================================================
+//
+// hal_platform_setup.h
+//
+// Platform specific support for HAL (assembly code)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <pkgconf/system.h> // System-wide configuration info
+#include CYGBLD_HAL_VARIANT_H // Variant specific configuration
+#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
+#include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
+#include <cyg/hal/hal_mmu.h> // MMU definitions
+#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1 _platform_setup1
+#define CYGHWR_HAL_ARM_HAS_MMU
+
+#ifdef CYG_HAL_STARTUP_ROMRAM
+#define CYGSEM_HAL_ROM_RESET_USES_JUMP
+#endif
+
+//#define NFC_2K_BI_SWAP
+#define SDRAM_FULL_PAGE_BIT 0x100
+#define SDRAM_FULL_PAGE_MODE 0x37
+#define SDRAM_BURST_MODE 0x33
+
+#define CYGHWR_HAL_ROM_VADDR 0x0
+
+#if 0
+#define UNALIGNED_ACCESS_ENABLE
+#define SET_T_BIT_DISABLE
+#define BRANCH_PREDICTION_ENABLE
+#endif
+
+#define DCDGEN(i,type, addr, data) \
+dcd_##i: ;\
+ .long type ;\
+ .long addr ;\
+ .long data
+
+#define PLATFORM_PREAMBLE flash_header
+//flash header & DCD @ 0x400
+.macro flash_header
+ b reset_vector
+ .org 0x400
+app_code_jump_v: .long reset_vector
+app_code_barker: .long 0xB1
+app_code_csf: .long 0
+dcd_ptr_ptr: .long dcd_ptr
+super_root_key: .long 0
+dcd_ptr: .long dcd_data
+app_dest_ptr: .long 0x97f00000
+
+dcd_data: .long 0xB17219E9 // Fixed. can't change.
+#ifdef IMX51_TO_2
+dcd_len: .long (56*12)
+
+//DCD
+//DDR2 IOMUX configuration
+DCDGEN(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200)
+DCDGEN(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5)
+DCDGEN(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5)
+DCDGEN(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2)
+DCDGEN(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2)
+DCDGEN(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7)
+DCDGEN(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45)
+DCDGEN(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45)
+DCDGEN(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45)
+DCDGEN(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45)
+DCDGEN(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0)
+DCDGEN(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3)
+DCDGEN(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3)
+DCDGEN(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3)
+DCDGEN(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3)
+DCDGEN(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3)
+DCDGEN(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3)
+DCDGEN(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2)
+//Set drive strength to MAX
+DCDGEN(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x6)
+DCDGEN(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x6)
+DCDGEN(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x6)
+DCDGEN(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x6)
+//13 ROW, 10 COL, 32Bit, SREF=4 Micron Model
+//CAS=3, BL=4
+DCDGEN(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000)
+DCDGEN(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000)
+DCDGEN(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0)
+DCDGEN(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333574aa)
+DCDGEN(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333574aa)
+// Init DRAM on CS0
+DCDGEN(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+DCDGEN(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a)
+DCDGEN(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b)
+DCDGEN(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00448019)
+DCDGEN(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018)
+DCDGEN(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+DCDGEN(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+DCDGEN(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+DCDGEN(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018)
+DCDGEN(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019)
+DCDGEN(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00408019)
+DCDGEN(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000)
+
+// Init DRAM on CS1
+DCDGEN(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
+DCDGEN(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e)
+DCDGEN(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f)
+DCDGEN(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d)
+DCDGEN(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c)
+DCDGEN(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
+DCDGEN(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
+DCDGEN(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
+DCDGEN(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c)
+DCDGEN(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d)
+DCDGEN(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0040801d)
+DCDGEN(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004)
+
+DCDGEN(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000)
+DCDGEN(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000)
+DCDGEN(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
+DCDGEN(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000)
+DCDGEN(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
+
+#else
+dcd_len: .long (9*12)
+
+//DCD
+ // ldr r0, ESDCTL_BASE_W
+ // /* Set CSD0 */
+ // ldr r1, =0x80000000
+ // str r1, [r0, #ESDCTL_ESDCTL0]
+DCDGEN(1, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x80000000)
+ // /* Precharge command */
+ // ldr r1, SDRAM_0x04008008
+ // str r1, [r0, #ESDCTL_ESDSCR]
+DCDGEN(2, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+ // /* 2 refresh commands */
+ // ldr r1, SDRAM_0x00008010
+ // str r1, [r0, #ESDCTL_ESDSCR]
+DCDGEN(3, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+ // str r1, [r0, #ESDCTL_ESDSCR]
+DCDGEN(4, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+ // /* LMR with CAS=3 and BL=3 */
+ // ldr r1, SDRAM_0x00338018
+ // str r1, [r0, #ESDCTL_ESDSCR]
+DCDGEN(5, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00338018)
+ // /* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
+ // ldr r1, SDRAM_0xB2220000
+ // str r1, [r0, #ESDCTL_ESDCTL0]
+DCDGEN(6, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xB2220000)
+ // /* Timing parameters */
+ // ldr r1, SDRAM_0xB02567A9
+ // str r1, [r0, #ESDCTL_ESDCFG0]
+DCDGEN(7, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0xB02567A9)
+ // /* MDDR enable, RLAT=2 */
+ // ldr r1, SDRAM_0x000A0104
+ // str r1, [r0, #ESDCTL_ESDMISC]
+DCDGEN(8, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000A0104)
+ // /* Normal mode */
+ // ldr r1, =0x00000000
+ // str r1, [r0, #ESDCTL_ESDSCR]
+DCDGEN(9, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0)
+#endif
+image_len: .long 256*1024
+
+.endm
+
+//#define ENABLE_IMPRECISE_ABORT
+
+// This macro represents the initial startup code for the platform
+ .macro _platform_setup1
+FSL_BOARD_SETUP_START:
+ // mrc p15, 0, r0, c1, c1, 0 // Read Secure Configuration Register data. Why doesn't work???
+ // mcr p15, 0, <Rd>, c1, c1, 0 ; Write Secure Configuration Register data
+#ifdef ENABLE_IMPRECISE_ABORT
+ mrs r1, spsr // save old spsr
+ mrs r0, cpsr // read out the cpsr
+ bic r0, r0, #0x100 // clear the A bit
+ msr spsr, r0 // update spsr
+ add lr, pc, #0x8 // update lr
+ movs pc, lr // update cpsr
+ nop
+ nop
+ nop
+ nop
+ msr spsr, r1 // restore old spsr
+#endif
+
+ // explicitly disable L2 cache
+ mrc 15, 0, r0, c1, c0, 1
+ bic r0, r0, #0x2
+ mcr 15, 0, r0, c1, c0, 1
+
+ // reconfigure L2 cache aux control reg
+ mov r0, #0xC0 // tag RAM
+ add r0, r0, #0x4 // data RAM
+ orr r0, r0, #(1 << 25) // disable write combine
+ orr r0, r0, #(1 << 24) // disable write allocate delay
+ orr r0, r0, #(1 << 23) // disable write allocate combine
+ orr r0, r0, #(1 << 22) // disable write allocate
+
+ mcr 15, 1, r0, c9, c0, 2
+
+ /* Reload data from spare area to 0x400 of main area if booting from NAND */
+ ldr r0, NFC_BASE_W
+ cmp pc, r0
+ blo 1f
+ cmp pc, r1
+ bhi 1f
+1:
+ /* Store the boot type, from NAND or SDRAM */
+ mov r11, #SDRAM_NON_FLASH_BOOT
+
+init_spba_start:
+ init_spba
+init_aips_start:
+ init_aips
+init_max_start:
+ init_max
+init_m4if_start:
+ init_m4if
+init_iomux_start:
+// init_iomux
+
+ // disable wdog
+ ldr r0, =0x30
+ ldr r1, WDOG1_BASE_W
+ strh r0, [r1]
+
+ /* If SDRAM has been setup, bypass clock/WEIM setup */
+ cmp pc, #SDRAM_BASE_ADDR
+ blo external_boot_cont
+ cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
+ blo internal_boot_cont
+
+external_boot_cont:
+
+init_sdram_start:
+ setup_sdram
+
+
+internal_boot_cont:
+init_clock_start:
+ init_clock
+
+HWInitialise_skip_SDRAM_setup:
+ ldr r0, NFC_BASE_W
+ add r2, r0, #0x1000 // 4K window
+ cmp pc, r0
+ blo Normal_Boot_Continue
+ cmp pc, r2
+ bhi Normal_Boot_Continue
+
+NAND_Boot_Start:
+ /* Copy image from flash to SDRAM first */
+ ldr r1, MXC_REDBOOT_ROM_START
+1: ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ blo 1b
+
+ /* Jump to SDRAM */
+ ldr r1, CONST_0x0FFF
+ and r0, pc, r1 /* offset of pc */
+ ldr r1, MXC_REDBOOT_ROM_START
+ add r1, r1, #0x10
+ add pc, r0, r1
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+NAND_Copy_Main:
+ ldr r11, NFC_IP_BASE_W //r11: NFC IP register base. Doesn't change
+ ldr r0, [r11, #0x24]
+ and r0, r0, #3
+ cmp r0, #1
+ mov r0, #4096
+ moveq r0, #2048
+ movlt r0, #512
+ ldr r1, =_nand_pg_sz // r1 -> _nand_pg_sz
+ str r0, [r1] // store the page size into the global variable _nand_pg_sz
+
+ ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
+ ldr r1, _nand_pg_sz //r1: starting flash addr to be copied. Updated constantly
+ add r2, r0, #0x800 //r2: end of 3rd RAM buf. Doesn't change ?? dynamic
+ cmp r1, #2048
+ addgt r2, r2, #2048 // for 4K page, copy 4K instead of 2K
+
+ add r12, r0, #0x1E00 //r12: NFC AXI register base. Doesn't change
+ ldr r14, MXC_REDBOOT_ROM_START
+ add r13, r14, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
+ add r14, r14, r1 //r14: starting SDRAM address for copying. Updated constantly
+
+ //unlock internal buffer
+ mov r3, #0xFF000000
+ add r3, r3, #0x00FF0000
+ str r3, [r11, #0x4]
+ str r3, [r11, #0x8]
+ str r3, [r11, #0xC]
+ str r3, [r11, #0x10]
+ str r3, [r11, #0x14]
+ str r3, [r11, #0x18]
+ str r3, [r11, #0x1C]
+ str r3, [r11, #0x20]
+ mov r4, #0x7
+ mov r3, #0x84
+1: add r5, r3, r4, lsr #3
+ str r5, [r11, #0x0]
+ subs r4, r4, #0x1
+ bne 1b
+
+ mov r3, #0
+ str r3, [r11, #0x2C]
+
+Nfc_Read_Page:
+ //start_nfc_addr_ops1(pg_no, pg_off);
+ ldr r3, _nand_pg_sz
+ cmp r3, #2048
+ // TODO: need to deal with 512B page
+ movgt r3, r1, lsr #12 // get the page number for 4K page nand
+ moveq r3, r1, lsr #11 // get the page number for 2K page nand
+ mov r3, r3, lsl #16
+ str r3, [r12, #0x4] // set the addr
+
+ // writel((FLASH_Read_Mode1_LG << 8) | FLASH_Read_Mode1, NAND_CMD_REG);
+ mov r3, #0x3000
+ str r3, [r12, #0x0]
+
+ // writel(0x00000000, NAND_CONFIGURATION1_REG);
+ mov r3, #0x0
+ str r3, [r12, #0x34]
+
+ // start auto-read
+ //writel(NAND_LAUNCH_AUTO_READ, NAND_LAUNCH_REG);
+ mov r3, #NAND_LAUNCH_AUTO_READ
+ str r3, [r12, #0x40]
+
+ do_wait_op_done
+
+Copy_Good_Blk:
+ //copying page
+1: ldmia r0!, {r3-r10}
+ stmia r14!, {r3-r10}
+ cmp r0, r2
+ blo 1b
+ cmp r14, r13
+ bge NAND_Copy_Main_done
+ ldr r3, _nand_pg_sz
+ add r1, r1, r3
+ ldr r0, NFC_BASE_W
+ b Nfc_Read_Page
+
+NAND_Copy_Main_done:
+
+Normal_Boot_Continue:
+
+#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
+ /* Copy image from flash to SDRAM first */
+ ldr r0, =0xFFFFF000
+ and r0, r0, pc
+ ldr r1, MXC_REDBOOT_ROM_START
+ cmp r0, r1
+ beq HWInitialise_skip_SDRAM_copy
+
+ add r2, r0, #REDBOOT_IMAGE_SIZE
+
+1: ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ ble 1b
+ /* Jump to SDRAM */
+ ldr r1, =0xFFFF
+ and r0, pc, r1 /* offset of pc */
+ ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
+ add pc, r0, r1
+ nop
+ nop
+ nop
+ nop
+#endif /* CYG_HAL_STARTUP_ROMRAM */
+
+HWInitialise_skip_SDRAM_copy:
+
+init_cs1_start:
+// init_cs1 -- moved to plf_hardware_init()
+
+/*
+ * Note:
+ * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
+ */
+STACK_Setup:
+ // Set up a stack [for calling C code]
+ ldr r1, =__startup_stack
+ ldr r2, =RAM_BANK0_BASE
+ orr sp, r1, r2
+
+ // Create MMU tables
+ bl hal_mmu_init
+
+ // Enable MMU
+ ldr r2, =10f
+ ldr r0, =ROM_BASE_ADDRESS
+ ldr r3, [r0, #ROM_SI_REV_OFFSET]
+ cmp r3, #0x1
+ bne skip_L1_workaround
+ // Workaround for L1 cache issue
+ mrc MMU_CP, 0, r1, c10, c2, 1 // Read normal memory remap register
+ bic r1, r1, #(3 << 14) // Remap inner attribute for TEX[0],C,B = b111 as noncacheable
+ bic r1, r1, #(3 << 6) // Remap inner attribute for TEX[0],C,B = b011 as noncacheable
+ bic r1, r1, #(3 << 4) // Remap inner attribute for TEX[0],C,B = b010 as noncacheable
+ mcr MMU_CP, 0, r1, c10, c2, 1 // Write normal memory remap register
+skip_L1_workaround:
+ mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
+ orr r1, r1, #7 // enable MMU bit
+ orr r1, r1, #0x800 // enable z bit
+ orrne r1, r1, #(1 << 28) // Enable TEX remap, workaround for L1 cache issue
+ mcr MMU_CP, 0, r1, MMU_Control, c0
+ mov pc,r2 /* Change address spaces */
+ nop
+ nop
+ nop
+10:
+
+ // Save shadow copy of BCR, also hardware configuration
+ ldr r1, =_board_BCR
+ str r2, [r1]
+ ldr r1, =_board_CFG
+ str r9, [r1] // Saved far above...
+
+ .endm // _platform_setup1
+
+#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1
+#endif
+
+ /* Do nothing */
+ .macro init_spba
+ .endm /* init_spba */
+
+ /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
+ .macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, AIPS1_CTRL_BASE_ADDR_W
+ ldr r1, AIPS1_PARAM_W
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ ldr r0, AIPS2_CTRL_BASE_ADDR_W
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+
+ .endm /* init_aips */
+
+ /* MAX (Multi-Layer AHB Crossbar Switch) setup */
+ .macro init_max
+ .endm /* init_max */
+
+ .macro init_clock
+ ldr r0, CCM_BASE_ADDR_W
+ /* Disable IPU and HSC dividers */
+ mov r1, #0x60000
+ str r1, [r0, #CLKCTL_CCDR]
+
+#ifdef IMX51_TO_2
+ /* Make sure to switch the DDR away from PLL 1 */
+ ldr r1, CCM_VAL_0x19239100
+ str r1, [r0, #CLKCTL_CBCDR]
+ /* make sure divider effective */
+ 1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+#endif
+ /* Switch ARM to step clock */
+ mov r1, #0x4
+ str r1, [r0, #CLKCTL_CCSR]
+ setup_pll PLL1, 800
+
+ setup_pll PLL3, 665
+ /* Switch peripheral to PLL 3 */
+ ldr r0, CCM_BASE_ADDR_W
+ ldr r1, CCM_VAL_0x0000D3C0
+ str r1, [r0, #CLKCTL_CBCMR]
+ ldr r1, CCM_VAL_0x033B9145
+ str r1, [r0, #CLKCTL_CBCDR]
+ setup_pll PLL2, 665
+ /* Switch peripheral to PLL 2 */
+ ldr r0, CCM_BASE_ADDR_W
+ ldr r1, CCM_VAL_0x013B9145
+ str r1, [r0, #CLKCTL_CBCDR]
+ ldr r1, CCM_VAL_0x0000E3C0
+ str r1, [r0, #CLKCTL_CBCMR]
+
+ setup_pll PLL3, 216
+
+ /* Set the platform clock dividers */
+ ldr r0, PLATFORM_BASE_ADDR_W
+ ldr r1, PLATFORM_CLOCK_DIV_W
+ str r1, [r0, #PLATFORM_ICGC]
+
+ /* Switch ARM back to PLL 1. */
+ ldr r0, CCM_BASE_ADDR_W
+ mov r1, #0x0
+ str r1, [r0, #CLKCTL_CCSR]
+
+ /* setup the rest */
+ mov r1, #0
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Use lp_apm (24MHz) source for perclk */
+#ifdef IMX51_TO_2
+ ldr r1, CCM_VAL_0x000020C2
+ str r1, [r0, #CLKCTL_CBCMR]
+ // ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
+ ldr r1, CCM_VAL_0x59239100
+ str r1, [r0, #CLKCTL_CBCDR]
+#else
+ ldr r1, CCM_VAL_0x0000E3C2
+ str r1, [r0, #CLKCTL_CBCMR]
+ // emi=ahb, all perclk dividers are 1 since using 24MHz
+ ldr r1, CCM_VAL_0x013B9100
+ str r1, [r0, #CLKCTL_CBCDR]
+#endif
+ /* Use PLL 2 for UART's, get 66.5MHz from it */
+ ldr r1, CCM_VAL_0xA5A2A020
+ str r1, [r0, #CLKCTL_CSCMR1]
+ ldr r1, CCM_VAL_0x00C30321
+ str r1, [r0, #CLKCTL_CSCDR1]
+
+ /* make sure divider effective */
+ 1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ mov r1, #0x00000
+ str r1, [r0, #CLKCTL_CCDR]
+
+ // for cko - for ARM div by 8
+ mov r1, #0x000A0000
+ add r1, r1, #0x00000F0
+ str r1, [r0, #CLKCTL_CCOSR]
+ .endm /* init_clock */
+
+ .macro setup_pll pll_nr, mhz
+ ldr r0, BASE_ADDR_W_\pll_nr
+ ldr r1, PLL_VAL_0x1232
+ str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
+ ldr r1, =0x2
+ str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+
+ ldr r1, W_DP_OP_\mhz
+ str r1, [r0, #PLL_DP_OP]
+ str r1, [r0, #PLL_DP_HFS_OP]
+
+ ldr r1, W_DP_MFD_\mhz
+ str r1, [r0, #PLL_DP_MFD]
+ str r1, [r0, #PLL_DP_HFS_MFD]
+
+ ldr r1, W_DP_MFN_\mhz
+ str r1, [r0, #PLL_DP_MFN]
+ str r1, [r0, #PLL_DP_HFS_MFN]
+
+ /* Now restart PLL */
+ ldr r1, PLL_VAL_0x1232
+ str r1, [r0, #PLL_DP_CTL]
+wait_pll_lock\pll_nr\mhz:
+ ldr r1, [r0, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+ beq wait_pll_lock\pll_nr\mhz
+ .endm
+
+ /* M3IF setup */
+ .macro init_m4if
+ ldr r1, M4IF_BASE_W
+#ifdef IMX51_TO_2
+ ldr r0, M4IF_0x00240180
+ str r0, [r1, #M4IF_MIF4]
+#else
+ /* IPU accesses with ID=0x1 given highest priority (=0xA) */
+ ldr r0, M4IF_0x00000a01
+ str r0, [r1, #M4IF_FIDBP]
+#endif
+ /* Configure M4IF registers, VPU and IPU given higher priority (=0x4) */
+ ldr r0, M4IF_0x00000404
+ str r0, [r1, #M4IF_FBPM0]
+ .endm /* init_m4if */
+
+ .macro setup_sdram
+ ldr r0, ESDCTL_BASE_W
+ /* Set CSD0 */
+ ldr r1, =0x80000000
+ str r1, [r0, #ESDCTL_ESDCTL0]
+ /* Precharge command */
+ ldr r1, SDRAM_0x04008008
+ str r1, [r0, #ESDCTL_ESDSCR]
+ /* 2 refresh commands */
+ ldr r1, SDRAM_0x00008010
+ str r1, [r0, #ESDCTL_ESDSCR]
+ str r1, [r0, #ESDCTL_ESDSCR]
+ /* LMR with CAS=3 and BL=3 */
+ ldr r1, SDRAM_0x00338018
+ str r1, [r0, #ESDCTL_ESDSCR]
+ /* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
+ ldr r1, SDRAM_0xB2220000
+ str r1, [r0, #ESDCTL_ESDCTL0]
+ /* Timing parameters */
+// ldr r1, SDRAM_0x899F6BBA
+ ldr r1, SDRAM_0xB02567A9
+ str r1, [r0, #ESDCTL_ESDCFG0]
+ /* MDDR enable, RLAT=2 */
+ ldr r1, SDRAM_0x000A0104
+ str r1, [r0, #ESDCTL_ESDMISC]
+ /* Normal mode */
+ ldr r1, =0x00000000
+ str r1, [r0, #ESDCTL_ESDSCR]
+ .endm
+
+ .macro do_wait_op_done
+ 1:
+ ldr r3, [r11, #0x2C]
+ ands r3, r3, #NFC_IPC_INT
+ beq 1b
+ mov r3, #0x0
+ str r3, [r11, #0x2C]
+ .endm // do_wait_op_done
+
+ .macro init_iomux
+ // do nothing
+ .endm /* init_iomux */
+
+#define PLATFORM_VECTORS _platform_vectors
+ .macro _platform_vectors
+ .globl _board_BCR, _board_CFG
+_board_BCR: .long 0 // Board Control register shadow
+_board_CFG: .long 0 // Board Configuration (read at RESET)
+ .endm
+
+WDOG1_BASE_W: .word WDOG1_BASE_ADDR
+IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
+AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
+AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
+AIPS1_PARAM_W: .word 0x77777777
+MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
+MAX_PARAM1: .word 0x00302154
+ESDCTL_BASE_W: .word ESDCTL_BASE_ADDR
+M4IF_BASE_W: .word M4IF_BASE_ADDR
+M4IF_0x00000a01: .word 0x00000a01
+M4IF_0x00240180: .word 0x00240180
+M4IF_0x00000404: .word 0x00000404
+NFC_BASE_W: .word NFC_BASE_ADDR_AXI
+NFC_IP_BASE_W: .word NFC_IP_BASE
+SDRAM_0x04008008: .word 0x04008008
+SDRAM_0x00008010: .word 0x00008010
+SDRAM_0x00338018: .word 0x00338018
+SDRAM_0xB2220000: .word 0xB2220000
+SDRAM_0x899F6BBA: .word 0x899F6BBA
+SDRAM_0xB02567A9: .word 0xB02567A9
+SDRAM_0x000A0104: .word 0x000A0104
+IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
+MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
+CONST_0x0FFF: .word 0x0FFF
+CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
+CCM_VAL_0x0000E3C2: .word 0x0000E3C2
+CCM_VAL_0x000020C2: .word 0x000020C2
+CCM_VAL_0x013B9100: .word 0x013B9100
+CCM_VAL_0x59239100: .word 0x59239100
+CCM_VAL_0x19239100: .word 0x19239100
+CCM_VAL_0xA5A2A020: .word 0xA5A2A020
+CCM_VAL_0x00C30321: .word 0x00C30321
+CCM_VAL_0x0000D3C0: .word 0x0000D3C0
+CCM_VAL_0x033B9145: .word 0x033B9145
+CCM_VAL_0x013B9145: .word 0x013B9145
+CCM_VAL_0x0000E3C0: .word 0x0000E3C0
+PLL_VAL_0x222: .word 0x222
+PLL_VAL_0x232: .word 0x232
+BASE_ADDR_W_PLL1: .word PLL1_BASE_ADDR
+BASE_ADDR_W_PLL2: .word PLL2_BASE_ADDR
+BASE_ADDR_W_PLL3: .word PLL3_BASE_ADDR
+PLL_VAL_0x1232: .word 0x1232
+W_DP_OP_800: .word DP_OP_800
+W_DP_MFD_800: .word DP_MFD_800
+W_DP_MFN_800: .word DP_MFN_800
+W_DP_OP_700: .word DP_OP_700
+W_DP_MFD_700: .word DP_MFD_700
+W_DP_MFN_700: .word DP_MFN_700
+W_DP_OP_400: .word DP_OP_400
+W_DP_MFD_400: .word DP_MFD_400
+W_DP_MFN_400: .word DP_MFN_400
+W_DP_OP_532: .word DP_OP_532
+W_DP_MFD_532: .word DP_MFD_532
+W_DP_MFN_532: .word DP_MFN_532
+W_DP_OP_665: .word DP_OP_665
+W_DP_MFD_665: .word DP_MFD_665
+W_DP_MFN_665: .word DP_MFN_665
+W_DP_OP_216: .word DP_OP_216
+W_DP_MFD_216: .word DP_MFD_216
+W_DP_MFN_216: .word DP_MFN_216
+PLATFORM_BASE_ADDR_W: .word PLATFORM_BASE_ADDR
+PLATFORM_CLOCK_DIV_W: .word 0x00000725
+_nand_pg_sz: .word 0
+
+/*---------------------------------------------------------------------------*/
+/* end of hal_platform_setup.h */
+#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x00000000)
+#define CYGMEM_REGION_ram_SIZE (0x7F00000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0x97F00000)
+#define CYGMEM_REGION_rom_SIZE (0x100000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ ram : ORIGIN = 0, LENGTH = 0x7F00000
+ rom : ORIGIN = 0x97F00000, LENGTH = 0x100000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_rom_vectors (rom, 0x97F00000, LMA_EQ_VMA)
+ SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
+ SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table))
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
--- /dev/null
+version 0
+region ram 0 7F00000 0 !
+region rom 97F00000 100000 1 !
+section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
+section data 0 1 1 1 1 1 0 0 8000 bss !
+section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
+section heap1 0 8 0 0 0 0 0 0 !
+section rom_vectors 0 1 0 1 1 1 1 1 97F00000 97F00000 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata rodata !
+section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 4 0 1 0 0 0 1 data !
--- /dev/null
+#ifndef CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+#define CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+
+//=============================================================================
+//
+// plf_io.h
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/hal/fsl_board.h>
+#include <cyg/hal/hal_soc.h>
+
+extern unsigned int cpld_base_addr;
+
+#define LAN92XX_REG_READ(reg_offset) \
+ (*(volatile unsigned int *)(cpld_base_addr + reg_offset))
+
+#define LAN92XX_REG_WRITE(reg_offset, val) \
+ (*(volatile unsigned int *)(cpld_base_addr + reg_offset) = (val))
+
+#define LED_IS_ON(n) ((readw(cpld_base_addr + PBC_LED_CTRL) & (1 << (n))) != 0)
+#define TURN_LED_ON(n) writew((readw(cpld_base_addr + PBC_LED_CTRL) | (1 << (n))), cpld_base_addr + PBC_LED_CTRL)
+#define TURN_LED_OFF(n) writew((readw(cpld_base_addr + PBC_LED_CTRL) & (~(1<<(n)))), cpld_base_addr + PBC_LED_CTRL)
+
+#define BOARD_DEBUG_LED(n) 0
+/*
+#define BOARD_DEBUG_LED(n) \
+ CYG_MACRO_START \
+ if (n >= 0 && n < LED_MAX_NUM) { \
+ if (LED_IS_ON(n)) \
+ TURN_LED_OFF(n); \
+ else \
+ TURN_LED_ON(n); \
+ } \
+ CYG_MACRO_END
+*/
+
+extern unsigned int system_rev;
+
+#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \
+ CYG_MACRO_START \
+ { \
+ extern unsigned int system_rev; \
+ /* Next ATAG_MEM. */ \
+ _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header)) / sizeof(long); \
+ _p_->hdr.tag = ATAG_MEM; \
+ /* Round up so there's only one bit set in the memory size. \
+ * Don't double it if it's already a power of two, though. \
+ */ \
+ _p_->u.mem.size = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE); \
+ if (_p_->u.mem.size < CYGMEM_REGION_ram_SIZE) \
+ _p_->u.mem.size <<= 1; \
+ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) \
+ _p_->u.mem.size = 512 * 0x100000; \
+ _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram); \
+ _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size); \
+ _p_->hdr.size = ((sizeof(struct tag_revision)) + sizeof(struct tag_header)) / sizeof(long); \
+ _p_->hdr.tag = ATAG_REVISION; \
+ _p_->u.revision.rev = system_rev; \
+ } \
+ CYG_MACRO_END
+
+#endif // CYGONCE_HAL_ARM_BOARD_PLF_IO_H
--- /dev/null
+#ifndef CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+#define CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+//=============================================================================
+//
+// plf_mmap.h
+//
+// Platform specific memory map support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_misc.h>
+
+// Get the pagesize for a particular virtual address:
+
+// This does not depend on the vaddr.
+#define HAL_MM_PAGESIZE(vaddr, pagesize) CYG_MACRO_START \
+ (pagesize) = SZ_1M; \
+CYG_MACRO_END
+
+// Get the physical address from a virtual address:
+
+#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START \
+ cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
+ if ( _v_ < 128 * SZ_1M ) /* SDRAM */ \
+ _v_ += SDRAM_BASE_ADDR; \
+ else /* Rest of it */ \
+ /* no change */ ; \
+ (paddr) = _v_; \
+CYG_MACRO_END
+
+//---------------------------------------------------------------------------
+
+/*
+ * translate the virtual address of ram space to physical address
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
+{
+ if(virt < 0x08000000) {
+ return virt|0x90000000;
+ }
+ if((virt & 0xF0000000) == 0x90000000) {
+ return virt&(~0x08000000);
+ }
+ return virt;
+}
+
+/*
+ * remap the physical address of ram space to uncacheable virtual address space
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
+{
+ /* 0x98000000~0x9FFFFFFF is uncacheable meory space which is mapped to SDRAM*/
+ if((phy & 0xF0000000) == 0x90000000) {
+ phy |= 0x08000000;
+ }
+ return phy;
+}
+
+#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
--- /dev/null
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware mx51_3stack ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM current ;
+ package -hardware CYGPKG_HAL_ARM_MX51 current ;
+ package -hardware CYGPKG_HAL_ARM_MX51_3STACK current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ;
+ package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ;
+ package -hardware CYGPKG_DEVS_ETH_FEC current ;
+ package -hardware CYGPKG_COMPRESS_ZLIB current ;
+ package -hardware CYGPKG_DIAGNOSIS current ;
+ package -hardware CYGPKG_IO_FLASH current ;
+ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+ package -hardware CYGPKG_DEVS_IMX_SPI current ;
+ package -hardware CYGPKG_DEVS_MXC_I2C current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package CYGPKG_MEMALLOC current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MMC {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_ATA {
+ inferred_value 1
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
+ user_value 50
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ inferred_value 0x00040000
+};
+
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+ inferred_value 0x90008000
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_component CYG_HAL_STARTUP {
+ user_value ROMRAM
+};
+
+cdl_component CYGPKG_MEMORY_DIAGNOSIS {
+ user_value 1
+};
+
+cdl_option CYGSEM_RAM_PM_DIAGNOSIS {
+ user_value 0
+};
+
+#cdl_component CYGPKG_WDT_DIAGNOSIS {
+# user_value 1
+#};
+
+cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+ inferred_value 1
+};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+ inferred_value 4
+};
+
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+ user_value 1 "FSL 200904"
+};
--- /dev/null
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware mx51_3stack ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM current ;
+ package -hardware CYGPKG_HAL_ARM_MX51 current ;
+ package -hardware CYGPKG_HAL_ARM_MX51_3STACK current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ;
+ package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ;
+ #package -hardware CYGPKG_DEVS_ETH_FEC current ;
+ package -hardware CYGPKG_COMPRESS_ZLIB current ;
+ package -hardware CYGPKG_DIAGNOSIS current ;
+ package -hardware CYGPKG_IO_FLASH current ;
+ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+ #package -hardware CYGPKG_DEVS_IMX_SPI current ;
+ package -hardware CYGPKG_DEVS_MXC_I2C current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package CYGPKG_MEMALLOC current ;
+};
+
+cdl_option CYGHWR_MX51_TO2 {
+ inferred_value 1
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MMC {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_ATA {
+ inferred_value 0
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
+ user_value 50
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ inferred_value 0x00040000
+};
+
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+ inferred_value 0x90008000
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_component CYG_HAL_STARTUP {
+ user_value ROMRAM
+};
+
+cdl_component CYGPKG_MEMORY_DIAGNOSIS {
+ user_value 1
+};
+
+cdl_option CYGSEM_RAM_PM_DIAGNOSIS {
+ user_value 0
+};
+
+#cdl_component CYGPKG_WDT_DIAGNOSIS {
+# user_value 1
+#};
+
+cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+ inferred_value 1
+};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+ inferred_value 4
+};
+
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+ user_value 1 "FSL 200904"
+};
--- /dev/null
+/*=============================================================================
+//
+// board_diag.c
+//
+// HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_arch.h> // basic machine info
+#include <cyg/hal/hal_intr.h> // interrupt macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_if.h> // Calling-if API
+#include <cyg/hal/drv_api.h> // driver API
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/fsl_board.h> // Platform specifics
+
+static void cyg_hal_plf_duart_init(void);
+extern void cyg_hal_plf_serial_init(void);
+
+#define DUART_WORKAROUND_DELAY(a) hal_delay_us(a);
+
+
+void cyg_hal_plf_comms_init(void)
+{
+ static int initialized = 0;
+
+ if (initialized)
+ return;
+
+ initialized = 1;
+
+ /* Setup GPIO and enable transceiver for UARTs */
+ cyg_hal_plf_duart_init();
+ cyg_hal_plf_serial_init();
+}
+
+//=============================================================================
+// ST16552 DUART driver
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// There are two serial ports.
+#define CYG_DEV_SERIAL_BASE_A (BOARD_CS_UART_BASE + 0x0000) // port A
+#define CYG_DEV_SERIAL_BASE_B (BOARD_CS_UART_BASE + 0x8000) // port B
+
+//-----------------------------------------------------------------------------
+// Based on 14.7456 MHz xtal
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x60
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x30
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x18
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x10
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x08
+#endif
+
+#ifndef CYG_DEV_SERIAL_BAUD_MSB
+#error Missing/incorrect serial baud rate defined - CDL error?
+#endif
+
+//-----------------------------------------------------------------------------
+// Define the serial registers. The board is equipped with a 16552
+// serial chip.
+
+#ifdef EXT_UART_x16
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT16
+#define HAL_READ_UINT_UART HAL_READ_UINT16
+typedef cyg_uint16 uart_width;
+#else //_x8
+typedef cyg_uint8 uart_width;
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT8
+#define HAL_READ_UINT_UART HAL_READ_UINT8
+#endif
+
+#define CYG_DEV_SERIAL_RHR 0x00 // receiver buffer register, read, dlab = 0
+#define CYG_DEV_SERIAL_THR 0x00 // transmitter holding register, write, dlab = 0
+#define CYG_DEV_SERIAL_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IER 0x01 // interrupt enable register, read/write, dlab = 0
+#define CYG_DEV_SERIAL_DLM 0x01 // divisor latch (MS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IIR 0x02 // interrupt identification register, read, dlab = 0
+#define CYG_DEV_SERIAL_FCR 0x02 // fifo control register, write, dlab = 0
+#define CYG_DEV_SERIAL_AFR 0x02 // alternate function register, read/write, dlab = 1
+#define CYG_DEV_SERIAL_LCR 0x03 // line control register, read/write
+#define CYG_DEV_SERIAL_MCR 0x04
+#define CYG_DEV_SERIAL_MCR_A 0x04
+#define CYG_DEV_SERIAL_MCR_B 0x04
+#define CYG_DEV_SERIAL_LSR 0x05 // line status register, read
+#define CYG_DEV_SERIAL_MSR 0x06 // modem status register, read
+#define CYG_DEV_SERIAL_SCR 0x07 // scratch pad register
+
+// The interrupt enable register bits.
+#define SIO_IER_ERDAI 0x01 // enable received data available irq
+#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
+#define SIO_IER_ELSI 0x04 // enable receiver line status irq
+#define SIO_IER_EMSI 0x08 // enable modem status interrupt
+
+// The interrupt identification register bits.
+#define SIO_IIR_IP 0x01 // 0 if interrupt pending
+#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
+#define ISR_Tx 0x02
+#define ISR_Rx 0x04
+
+// The line status register bits.
+#define SIO_LSR_DR 0x01 // data ready
+#define SIO_LSR_OE 0x02 // overrun error
+#define SIO_LSR_PE 0x04 // parity error
+#define SIO_LSR_FE 0x08 // framing error
+#define SIO_LSR_BI 0x10 // break interrupt
+#define SIO_LSR_THRE 0x20 // transmitter holding register empty
+#define SIO_LSR_TEMT 0x40 // transmitter register empty
+#define SIO_LSR_ERR 0x80 // any error condition
+
+// The modem status register bits.
+#define SIO_MSR_DCTS 0x01 // delta clear to send
+#define SIO_MSR_DDSR 0x02 // delta data set ready
+#define SIO_MSR_TERI 0x04 // trailing edge ring indicator
+#define SIO_MSR_DDCD 0x08 // delta data carrier detect
+#define SIO_MSR_CTS 0x10 // clear to send
+#define SIO_MSR_DSR 0x20 // data set ready
+#define SIO_MSR_RI 0x40 // ring indicator
+#define SIO_MSR_DCD 0x80 // data carrier detect
+
+// The line control register bits.
+#define SIO_LCR_WLS0 0x01 // word length select bit 0
+#define SIO_LCR_WLS1 0x02 // word length select bit 1
+#define SIO_LCR_STB 0x04 // number of stop bits
+#define SIO_LCR_PEN 0x08 // parity enable
+#define SIO_LCR_EPS 0x10 // even parity select
+#define SIO_LCR_SP 0x20 // stick parity
+#define SIO_LCR_SB 0x40 // set break
+#define SIO_LCR_DLAB 0x80 // divisor latch access bit
+
+// The FIFO control register
+#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
+#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
+#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
+
+//-----------------------------------------------------------------------------
+
+typedef struct {
+ uart_width* base;
+ cyg_int32 msec_timeout;
+ int isr_vector;
+} channel_data_t;
+
+static channel_data_t channels[] = {
+#if CYGHWR_HAL_ARM_DUART_UARTA != 0
+ {(uart_width*)CYG_DEV_SERIAL_BASE_A, 1000, 0},
+#endif
+#if CYGHWR_HAL_ARM_DUART_UARTB != 0
+ {(uart_width*)CYG_DEV_SERIAL_BASE_B, 1000, 0}
+#endif
+};
+
+//-----------------------------------------------------------------------------
+
+static void init_duart_channel(channel_data_t* __ch_data)
+{
+ uart_width* base = __ch_data->base;
+ uart_width lcr;
+
+ // 8-1-no parity.
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR,
+ SIO_LCR_WLS0 | SIO_LCR_WLS1);
+ DUART_WORKAROUND_DELAY(50);
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ lcr |= SIO_LCR_DLAB;
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLL, CYG_DEV_SERIAL_BAUD_LSB);
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLM, CYG_DEV_SERIAL_BAUD_MSB);
+ lcr &= ~SIO_LCR_DLAB;
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_FCR, 0x07); // Enable & clear FIFO
+}
+
+//#define x_debug_uart_log_buf
+#ifdef x_debug_uart_log_buf
+#define x_DIAG_BUFSIZE 2048
+static char __x_log_buf[x_DIAG_BUFSIZE];
+static int x_diag_bp = 0;
+#endif
+
+void cyg_hal_plf_duart_putc(void* __ch_data, cyg_uint8 c)
+{
+ uart_width* base = ((channel_data_t*)__ch_data)->base;
+ uart_width lsr;
+
+#ifdef x_debug_uart_log_buf
+ __x_log_buf[x_diag_bp++] = c;
+#endif
+ CYGARC_HAL_SAVE_GP();
+
+ do {
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ } while ((lsr & SIO_LSR_THRE) == 0);
+
+ DUART_WORKAROUND_DELAY(50);
+ HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_THR, c);
+
+ // Hang around until the character has been safely sent.
+ do {
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ } while ((lsr & SIO_LSR_THRE) == 0);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool cyg_hal_plf_duart_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+ uart_width* base = ((channel_data_t*)__ch_data)->base;
+ uart_width lsr, ch16;
+
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+ if ((lsr & SIO_LSR_DR) == 0)
+ return false;
+
+ HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_RHR, ch16);
+
+ *ch = (cyg_uint8) (ch16 & 0x00FF);
+
+ return true;
+}
+
+cyg_uint8 cyg_hal_plf_duart_getc(void* __ch_data)
+{
+ cyg_uint8 ch;
+
+ CYGARC_HAL_SAVE_GP();
+
+ while (!cyg_hal_plf_duart_getc_nonblock(__ch_data, &ch));
+
+ CYGARC_HAL_RESTORE_GP();
+ return ch;
+}
+
+static void cyg_hal_plf_duart_write(void* __ch_data, const cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while (__len-- > 0)
+ cyg_hal_plf_duart_putc(__ch_data, *__buf++);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static void cyg_hal_plf_duart_read(void* __ch_data, cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while (__len-- > 0)
+ *__buf++ = cyg_hal_plf_duart_getc(__ch_data);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool cyg_hal_plf_duart_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+ int delay_count;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_bool res;
+
+ CYGARC_HAL_SAVE_GP();
+
+ delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+ for (;;) {
+ res = cyg_hal_plf_duart_getc_nonblock(__ch_data, ch);
+ if (res || 0 == delay_count--)
+ break;
+
+ CYGACC_CALL_IF_DELAY_US(100);
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static int cyg_hal_plf_duart_control(void *__ch_data,
+ __comm_control_cmd_t __func, ...)
+{
+ static int irq_state = 0;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ uart_width ier;
+ int ret = 0;
+
+ CYGARC_HAL_SAVE_GP();
+
+ switch (__func) {
+ case __COMMCTL_IRQ_ENABLE:
+ HAL_INTERRUPT_UNMASK(chan->isr_vector);
+ HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ ier |= SIO_IER_ERDAI;
+ HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ irq_state = 1;
+ break;
+ case __COMMCTL_IRQ_DISABLE:
+ ret = irq_state;
+ irq_state = 0;
+ HAL_INTERRUPT_MASK(chan->isr_vector);
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ ier &= ~SIO_IER_ERDAI;
+ HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+ break;
+ case __COMMCTL_DBG_ISR_VECTOR:
+ ret = chan->isr_vector;
+ break;
+ case __COMMCTL_SET_TIMEOUT:
+ {
+ va_list ap;
+
+ va_start(ap, __func);
+
+ ret = chan->msec_timeout;
+ chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+ va_end(ap);
+ }
+ break;
+ default:
+ break;
+ }
+ CYGARC_HAL_RESTORE_GP();
+ return ret;
+}
+
+static int cyg_hal_plf_duart_isr(void *__ch_data, int* __ctrlc,
+ CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ uart_width _iir;
+ int res = 0;
+ CYGARC_HAL_SAVE_GP();
+
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IIR, _iir);
+ _iir &= SIO_IIR_ID_MASK;
+
+ *__ctrlc = 0;
+ if ( ISR_Rx == _iir ) {
+ uart_width c, lsr;
+ cyg_uint8 c8;
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_LSR, lsr);
+ if (lsr & SIO_LSR_DR) {
+
+ HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_RHR, c);
+
+ c8 = (cyg_uint8) (c & 0x00FF);
+
+ if (cyg_hal_is_break( &c8 , 1 ))
+ *__ctrlc = 1;
+ }
+
+ // Acknowledge the interrupt
+ HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+ res = CYG_ISR_HANDLED;
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static void cyg_hal_plf_duart_init(void)
+{
+ hal_virtual_comm_table_t* comm;
+ int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ int i;
+
+ // Init channels
+#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
+ for (i = 0; i < NUMOF(channels); i++) {
+ HAL_INTERRUPT_MASK(channels[i].isr_vector);
+ init_duart_channel(&channels[i]);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_duart_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_duart_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_duart_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_duart_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_duart_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_duart_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_duart_getc_timeout);
+ }
+
+ // Restore original console
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
+
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
+#define __BASE CMA101_DUARTA
+#define _INT CYGNUM_HAL_INTERRUPT_SERIAL_A
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1)
+#define __BASE CMA101_DUARTB
+#define _INT CYGNUM_HAL_INTERRUPT_SERIAL_B
+#endif
+
+#ifdef __BASE
+
+#ifdef CYGSEM_HAL_ROM_MONITOR
+#define CYG_HAL_STARTUP_ROM
+#define CYG_HAL_STARTUP_ROMRAM
+#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#endif
+
+#if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define HAL_DIAG_USES_HARDWARE
+#elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
+#define HAL_DIAG_USES_HARDWARE
+#elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+#define HAL_DIAG_USES_HARDWARE
+#endif
+
+static channel_data_t channel = {
+ (uart_width*) _BASE, 0, 0
+};
+
+#ifdef HAL_DIAG_USES_HARDWARE
+
+void hal_diag_init(void)
+{
+ static int init = 0;
+ char *msg = "\n\rARM eCos\n\r";
+ uart_width lcr;
+
+ if (init++) return;
+
+ init_duart_channel(&channel);
+
+ while (*msg) hal_diag_write_char(*msg++);
+}
+
+#ifdef DEBUG_DIAG
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define DIAG_BUFSIZE 32
+#else
+#define DIAG_BUFSIZE 2048
+#endif
+static char diag_buffer[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+
+void hal_diag_write_char(char c)
+{
+ uart_width lsr;
+
+ hal_diag_init();
+
+ cyg_hal_plf_duart_putc(&channel, c)
+
+#ifdef DEBUG_DIAG
+ diag_buffer[diag_bp++] = c;
+ if (diag_bp == DIAG_BUFSIZE) {
+ while (1) ;
+ diag_bp = 0;
+ }
+#endif
+}
+
+void hal_diag_read_char(char *c)
+{
+ *c = cyg_hal_plf_duart_getc(&channel);
+}
+
+#else // HAL_DIAG relies on GDB
+
+// Initialize diag port - assume GDB channel is already set up
+void hal_diag_init(void)
+{
+ if (0) init_duart_channel(&channel); // avoid warning
+}
+
+// Actually send character down the wire
+static void hal_diag_write_char_serial(char c)
+{
+ cyg_hal_plf_duart_putc(&channel, c);
+}
+
+static bool hal_diag_read_serial(char *c)
+{
+ long timeout = 1000000000; // A long time...
+
+ while (!cyg_hal_plf_duart_getc_nonblock(&channel, c))
+ if (0 == --timeout) return false;
+
+ return true;
+}
+
+void hal_diag_read_char(char *c)
+{
+ while (!hal_diag_read_serial(c)) ;
+}
+
+void hal_diag_write_char(char c)
+{
+ static char line[100];
+ static int pos = 0;
+
+ // No need to send CRs
+ if (c == '\r') return;
+
+ line[pos++] = c;
+
+ if (c == '\n' || pos == sizeof(line)) {
+ CYG_INTERRUPT_STATE old;
+
+ // Disable interrupts. This prevents GDB trying to interrupt us
+ // while we are in the middle of sending a packet. The serial
+ // receive interrupt will be seen when we re-enable interrupts
+ // later.
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+#else
+ HAL_DISABLE_INTERRUPTS(old);
+#endif
+
+ while (1) {
+ static char hex[] = "0123456789ABCDEF";
+ cyg_uint8 csum = 0;
+ int i;
+ char c1;
+
+ hal_diag_write_char_serial('$');
+ hal_diag_write_char_serial('O');
+ csum += 'O';
+ for (i = 0; i < pos; i++) {
+ char ch = line[i];
+ char h = hex[(ch>>4)&0xF];
+ char l = hex[ch&0xF];
+ hal_diag_write_char_serial(h);
+ hal_diag_write_char_serial(l);
+ csum += h;
+ csum += l;
+ }
+ hal_diag_write_char_serial('#');
+ hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
+ hal_diag_write_char_serial(hex[csum&0xF]);
+
+ // Wait for the ACK character '+' from GDB here and handle
+ // receiving a ^C instead. This is the reason for this clause
+ // being a loop.
+ if (!hal_diag_read_serial(&c1))
+ continue; // No response - try sending packet again
+
+ if ( c1 == '+' )
+ break; // a good acknowledge
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
+ if ( c1 == 3 ) {
+ // Ctrl-C: breakpoint.
+ cyg_hal_gdb_interrupt (__builtin_return_address(0));
+ break;
+ }
+#endif
+ // otherwise, loop round again
+ }
+
+ pos = 0;
+
+ // And re-enable interrupts
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+#else
+ HAL_RESTORE_INTERRUPTS(old);
+#endif
+
+ }
+}
+#endif
+
+#endif // __BASE
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
--- /dev/null
+//==========================================================================
+//
+// board_misc.c
+//
+// HAL misc board support code for the board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include <redboot.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h> // Interrupt names
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/fsl_board.h> // Platform specifics
+#include <cyg/io/mxc_i2c.h>
+#include <cyg/io/imx_nfc.h>
+#include <cyg/infra/diag.h> // diag_printf
+
+// All the MM table layout is here:
+#include <cyg/hal/hal_mm.h>
+
+externC void* memset(void *, int, size_t);
+extern nfc_iomuxsetup_func_t *nfc_iomux_setup;
+
+unsigned int cpld_base_addr;
+
+void hal_mmu_init(void)
+{
+ unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
+ unsigned long i;
+
+ /*
+ * Set the TTB register
+ */
+ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
+
+ /*
+ * Set the Domain Access Control Register
+ */
+ i = ARM_ACCESS_DACR_DEFAULT;
+ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+
+ /*
+ * First clear all TT entries - ie Set them to Faulting
+ */
+ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+
+ /* Actual Virtual Size Attributes Function */
+ /* Base Base MB cached? buffered? access permissions */
+ /* xxx00000 xxx00000 */
+ X_ARM_MMU_SECTION(0x000, 0x200, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */
+ X_ARM_MMU_SECTION(0x1FF, 0x1FF, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IRAM */
+ X_ARM_MMU_SECTION(0x300, 0x300, 0x100, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* GPU */
+ X_ARM_MMU_SECTION(0x400, 0x400, 0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IPUv3D */
+ X_ARM_MMU_SECTION(0x600, 0x600, 0x300, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* periperals */
+ X_ARM_MMU_SECTION(0x900, 0x000, 0x080, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0x900, 0x900, 0x080, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0x900, 0x980, 0x080, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
+ X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
+ X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */
+}
+
+void mxc_i2c_init(unsigned int module_base)
+{
+ unsigned int reg;
+
+ switch (module_base) {
+ case I2C_BASE_ADDR:
+ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
+ reg = IOMUXC_BASE_ADDR + 0x210; // i2c SDA
+ writel(0x11, reg);
+ reg = IOMUXC_BASE_ADDR + 0x600;
+ writel(0x1ad, reg);
+ reg = IOMUXC_BASE_ADDR + 0x9B4;
+ writel(0x1, reg);
+
+ reg = IOMUXC_BASE_ADDR + 0x224; // i2c SCL
+ writel(0x11, reg);
+ reg = IOMUXC_BASE_ADDR + 0x614;
+ writel(0x1ad, reg);
+ reg = IOMUXC_BASE_ADDR + 0x9B0;
+ writel(0x1, reg);
+ } else {
+ reg = IOMUXC_BASE_ADDR + 0x230; // i2c SCL
+ writel(0x11, reg);
+ reg = IOMUXC_BASE_ADDR + 0x6e0;
+ writel(0x1ad, reg);
+ reg = IOMUXC_BASE_ADDR + 0xA00;
+ writel(0x1, reg);
+
+ reg = IOMUXC_BASE_ADDR + 0x21C; // i2c SDA
+ writel(0x11, reg);
+ reg = IOMUXC_BASE_ADDR + 0x6cc;
+ writel(0x1ad, reg);
+ reg = IOMUXC_BASE_ADDR + 0xA04;
+ writel(0x1, reg);
+ }
+ break;
+ case I2C2_BASE_ADDR:
+ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
+ /* Workaround for Atlas Lite */
+ writel(0x0, IOMUXC_BASE_ADDR + 0x3CC); // i2c SCL
+ writel(0x0, IOMUXC_BASE_ADDR + 0x3D0); // i2c SDA
+ reg = readl(GPIO1_BASE_ADDR + 0x0);
+ reg |= 0xC; // write a 1 on the SCL and SDA lines
+ writel(reg, GPIO1_BASE_ADDR + 0x0);
+ reg = readl(GPIO1_BASE_ADDR + 0x4);
+ reg |= 0xC; // configure GPIO lines as output
+ writel(reg, GPIO1_BASE_ADDR + 0x4);
+ reg = readl(GPIO1_BASE_ADDR + 0x0);
+ reg &= ~0x4 ; // set SCL low for a few milliseconds
+ writel(reg, GPIO1_BASE_ADDR + 0x0);
+ hal_delay_us(20000);
+ reg |= 0x4;
+ writel(reg, GPIO1_BASE_ADDR + 0x0);
+ hal_delay_us(10);
+ reg = readl(GPIO1_BASE_ADDR + 0x4);
+ reg &= ~0xC; // configure GPIO lines back as input
+ writel(reg, GPIO1_BASE_ADDR + 0x4);
+
+ writel(0x12, IOMUXC_BASE_ADDR + 0x3CC); // i2c SCL
+ writel(0x3, IOMUXC_BASE_ADDR + 0x9B8);
+ writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D4);
+
+ writel(0x12, IOMUXC_BASE_ADDR + 0x3D0); // i2c SDA
+ writel(0x3, IOMUXC_BASE_ADDR + 0x9BC);
+ writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D8);
+ } else {
+ /* Workaround for Atlas Lite */
+ writel(0x0, IOMUXC_BASE_ADDR + 0x3D4); // i2c SCL
+ writel(0x0, IOMUXC_BASE_ADDR + 0x3D8); // i2c SDA
+ reg = readl(GPIO1_BASE_ADDR + 0x0);
+ reg |= 0xC; // write a 1 on the SCL and SDA lines
+ writel(reg, GPIO1_BASE_ADDR + 0x0);
+ reg = readl(GPIO1_BASE_ADDR + 0x4);
+ reg |= 0xC; // configure GPIO lines as output
+ writel(reg, GPIO1_BASE_ADDR + 0x4);
+ reg = readl(GPIO1_BASE_ADDR + 0x0);
+ reg &= ~0x4 ; // set SCL low for a few milliseconds
+ writel(reg, GPIO1_BASE_ADDR + 0x0);
+ hal_delay_us(20000);
+ reg |= 0x4;
+ writel(reg, GPIO1_BASE_ADDR + 0x0);
+ hal_delay_us(10);
+ reg = readl(GPIO1_BASE_ADDR + 0x4);
+ reg &= ~0xC; // configure GPIO lines back as input
+ writel(reg, GPIO1_BASE_ADDR + 0x4);
+
+ writel(0x12, IOMUXC_BASE_ADDR + 0x3D4); // i2c SCL
+ writel(0x3, IOMUXC_BASE_ADDR + 0xA08);
+ writel(0x1ed, IOMUXC_BASE_ADDR + 0x8A0);
+
+ writel(0x12, IOMUXC_BASE_ADDR + 0x3D8); // i2c SDA
+ writel(0x3, IOMUXC_BASE_ADDR + 0xA0C);
+ writel(0x1ed, IOMUXC_BASE_ADDR + 0x8A4);
+ }
+ break;
+ default:
+ diag_printf("Invalid I2C base: 0x%x\n", module_base);
+ return;
+ }
+}
+
+void mxc_ata_iomux_setup(void)
+{
+ // config NANDF_WE_B pad for pata instance DIOW port
+ // config_pad_mode(NANDF_WE_B, ALT1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull / Keep Select to Pull (Different from Module Level value: NA)
+ // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to Disabled
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_WE_B, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B);
+
+ // config NANDF_RE_B pad for pata instance DIOR port
+ // config_pad_mode(NANDF_RE_B, ALT1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull / Keep Select to Pull (Different from Module Level value: NA)
+ // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to Disabled
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_RE_B, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B);
+
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE);
+
+ // config NANDF_CLE pad for pata instance PATA_RESET_B port
+ // config_pad_mode(NANDF_CLE, ALT1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Hyst. Enable to Disabled
+ // Pull / Keep Select to Keep (Different from Module Level value: NA)
+ // Pull Up / Down Config. to 100Kohm PU (Different from Module Level value: NA)
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Pull / Keep Enable to Disabled
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_CLE, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE);
+
+ // config NANDF_WP_B pad for pata instance DMACK port
+ // config_pad_mode(NANDF_WP_B, ALT1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull / Keep Select to Pull (Different from Module Level value: NA)
+ // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to Disabled
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_WP_B, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B);
+
+ // config NANDF_RB0 pad for pata instance DMARQ port
+ // config_pad_mode(NANDF_RB0, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled (Different from Module Level value: NA)
+ // Drive Strength to NA (CFG in SoC Level however NA in Module Level)
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to CFG(360Kohm PD)
+ // config_pad_settings(NANDF_RB0, 0x20c0);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0);
+
+ // config NANDF_RB1 pad for pata instance IORDY port
+ // config_pad_mode(NANDF_RB1, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to NA (CFG in SoC Level however NA in Module Level)
+ // Drive Strength to NA (CFG in SoC Level however NA in Module Level)
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // config_pad_settings(NANDF_RB1, 0x20e0);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1);
+
+ // config NANDF_RB5 pad for pata instance INTRQ port
+ // config_pad_mode(NANDF_RB5, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RB5);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull Up / Down Config. to 100Kohm PU
+ // Open Drain Enable to Disabled (Different from Module Level value: NA)
+ // Drive Strength to NA (CFG in SoC Level however NA in Module Level)
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // config_pad_settings(NANDF_RB5, 0x20c0);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RB5);
+
+ // config NANDF_CS2 pad for pata instance CS_0 port
+ // config_pad_mode(NANDF_CS2, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull / Keep Select to NA (CFG in SoC Level however NA in Module Level)
+ // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to Disabled
+ // Open Drain Enable to Disabled
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_CS2, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2);
+
+ // config NANDF_CS3 pad for pata instance CS_1 port
+ // config_pad_mode(NANDF_CS3, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull / Keep Select to NA (CFG in SoC Level however NA in Module Level)
+ // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to Disabled
+ // Open Drain Enable to Disabled
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_CS3, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3);
+
+ // config NANDF_CS4 pad for pata instance DA_0 port
+ // config_pad_mode(NANDF_CS4, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull / Keep Select to NA (CFG in SoC Level however NA in Module Level)
+ // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to Disabled
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_CS4, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4);
+
+ // config NANDF_CS5 pad for pata instance DA_1 port
+ // config_pad_mode(NANDF_CS5, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull / Keep Select to NA (CFG in SoC Level however NA in Module Level)
+ // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to Disabled
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_CS5, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5);
+
+ // config NANDF_CS6 pad for pata instance DA_2 port
+ // config_pad_mode(NANDF_CS6, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull / Keep Select to Pull (Different from Module Level value: NA)
+ // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to Disabled
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_CS6, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6);
+
+ // config NANDF_D15 pad for pata instance PATA_DATA[15] port
+ // config_pad_mode(NANDF_D15, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D15);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D15, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D15);
+
+ // config NANDF_D14 pad for pata instance PATA_DATA[14] port
+ // config_pad_mode(NANDF_D14, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D14);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D14, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D14);
+
+ // config NANDF_D13 pad for pata instance PATA_DATA[13] port
+ // config_pad_mode(NANDF_D13, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D13);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D13, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D13);
+
+ // config NANDF_D12 pad for pata instance PATA_DATA[12] port
+ // config_pad_mode(NANDF_D12, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D12);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D12, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D12);
+
+ // config NANDF_D11 pad for pata instance PATA_DATA[11] port
+ // config_pad_mode(NANDF_D11, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D11);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D11, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D11);
+
+ // config NANDF_D10 pad for pata instance PATA_DATA[10] port
+ // config_pad_mode(NANDF_D10, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D10);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D10, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D10);
+
+ // config NANDF_D9 pad for pata instance PATA_DATA[9] port
+ // config_pad_mode(NANDF_D9, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D9);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D9, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D9);
+
+ // config NANDF_D8 pad for pata instance PATA_DATA[8] port
+ // config_pad_mode(NANDF_D8, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D8);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D8, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D8);
+
+ // config NANDF_D7 pad for pata instance PATA_DATA[7] port
+ // config_pad_mode(NANDF_D7, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D7);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull Up / Down Config. to 100Kohm PU
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D7, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D7);
+
+ // config NANDF_D6 pad for pata instance PATA_DATA[6] port
+ // config_pad_mode(NANDF_D6, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D6);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull Up / Down Config. to 100Kohm PU
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Open Drain Enable to Disabled
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D6, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D6);
+
+ // config NANDF_D5 pad for pata instance PATA_DATA[5] port
+ // config_pad_mode(NANDF_D5, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D5);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull Up / Down Config. to 100Kohm PU
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D5, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D5);
+
+ // config NANDF_D4 pad for pata instance PATA_DATA[4] port
+ // config_pad_mode(NANDF_D4, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D4);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull Up / Down Config. to 100Kohm PU
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D4, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D4);
+
+ // config NANDF_D3 pad for pata instance PATA_DATA[3] port
+ // config_pad_mode(NANDF_D3, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D3);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D3, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D3);
+
+ // config NANDF_D2 pad for pata instance PATA_DATA[2] port
+ // config_pad_mode(NANDF_D2, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D2);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D2, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D2);
+
+ // config NANDF_D1 pad for pata instance PATA_DATA[1] port
+ // config_pad_mode(NANDF_D1, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D1);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D1, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D1);
+
+ // config NANDF_D0 pad for pata instance PATA_DATA[0] port
+ // config_pad_mode(NANDF_D0, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D0);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D0, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D0);
+}
+
+static void mxc_fec_setup(void)
+{
+ volatile unsigned int reg;
+
+ /* No FEC support for TO 2.0 yet */
+ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2)
+ return;
+ /*FEC_TX_CLK*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0390);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x085C);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x09D0);
+
+ /*FEC_RX_CLK*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0388);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x0854);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x09C4);
+
+ /*FEC_RX_DV*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x038c);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x0858);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x09C8);
+
+ /*FEC_COL*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0384);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x0850);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x9A8);
+
+ /*FEC_RDATA0*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0394);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x0860);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x09B4);
+
+ /*FEC_TDATA0*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0398);
+ writel(0x5, IOMUXC_BASE_ADDR + 0x864);
+
+ /*FEC_TX_EN*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0380);
+ writel(0x5, IOMUXC_BASE_ADDR + 0x084C);
+
+ /*FEC_MDC*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x034C);
+ writel(0x5, IOMUXC_BASE_ADDR + 0x0818);
+
+ /*FEC_MDIO*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0350);
+ writel(0x1CD, IOMUXC_BASE_ADDR + 0x081C);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x09B0);
+
+ /*FEC_TX_ERR*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0344);
+ writel(0x5, IOMUXC_BASE_ADDR + 0x0810);
+
+ /*FEC_RX_ERR*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0360);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x082C);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x09CC);
+
+ /*FEC_CRS*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0348);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x0814);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x09AC);
+
+ /*FEC_RDATA1*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0354);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x0820);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x09B8);
+
+ /*FEC_TDATA1*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0374);
+ writel(0x5, IOMUXC_BASE_ADDR + 0x0840);
+
+ /*FEC_RDATA2*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0358);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x0824);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x09BC);
+
+ /*FEC_TDATA2*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0378);
+ writel(0x5, IOMUXC_BASE_ADDR + 0x0844);
+
+ /*FEC_RDATA3*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x035C);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x0828);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x09C0);
+
+ /*FEC_TDATA3*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x037C);
+ writel(0x5, IOMUXC_BASE_ADDR + 0x0848);
+
+ reg = readl(GPIO3_BASE_ADDR + 0x0);
+ reg &= ~0x40; // Lower reset line
+ writel(reg, GPIO3_BASE_ADDR + 0x0);
+
+ reg = readl(GPIO3_BASE_ADDR + 0x4);
+ reg |= 0x40; // configure GPIO lines as output
+ writel(reg, GPIO3_BASE_ADDR + 0x4);
+
+ /* Reset the ethernet controller over GPIO */
+ writel(0x4, IOMUXC_BASE_ADDR + 0x02CC);
+ writel(0xC5, IOMUXC_BASE_ADDR + 0x078C);
+
+ hal_delay_us(200);
+
+ reg = readl(GPIO3_BASE_ADDR + 0x0);
+ reg |= 0x40;
+ writel(reg, GPIO3_BASE_ADDR + 0x0);
+}
+
+static void mxc_nfc_iomux_setup(void)
+{
+ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
+ writel(0x0, IOMUXC_BASE_ADDR + 0x108);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x10C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x110);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x114);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x118);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x11C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x120);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x124);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x128);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x12C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x130);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x134);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x138);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x13C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x140);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x144);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x148);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x14C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x150);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x154);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x158);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x15C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x160);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x164);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x168);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x16C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x170);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x174);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x178);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x17C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x180);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x184);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x188);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x18C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x190);
+ } else {
+ writel(0x0, IOMUXC_BASE_ADDR + 0x108);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x10C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x110);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x114);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x118);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x11C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x120);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x124);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x128);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x12C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x130);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x134);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x138);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x13C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x140);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x144);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x148);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x14C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x150);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x154);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x158);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x15C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x160);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x164);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x168);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x16C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x170);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x174);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x178);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x17C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x180);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x184);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x188);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x18C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x190);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x194);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x198);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x19C);
+ }
+}
+
+//
+// Platform specific initialization
+//
+
+void plf_hardware_init(void)
+{
+ unsigned long sw_rest_reg, weim_base;
+ unsigned int reg;
+ unsigned char buf[4];
+ struct mxc_i2c_request rq;
+
+ /* Atlas Workaround needed only for TO 1.0 and 1.1 boards */
+ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) != 0x2) {
+ if (i2c_init(I2C2_BASE_ADDR, 170000) == 0) {
+ rq.dev_addr = 0x8;
+ rq.reg_addr = 0x7;
+ rq.reg_addr_sz = 1;
+ rq.buffer_sz = 3;
+ rq.buffer = buf;
+
+ i2c_xfer(1, &rq, 1);
+ /* Make sure we implement this workaround only for boards with Atlas-Lite to turn off the charger */
+ if ((buf[1] == 0x41) && (buf[2] == 0xc8 || buf[2] == 0xc9)) {
+ buf[0] = 0xb4;
+ buf[1] = 0x0;
+ buf[2] = 0x3;
+ rq.dev_addr = 0x8;
+ rq.reg_addr = 0x30;
+ rq.reg_addr_sz = 1;
+ rq.buffer_sz = 3;
+ rq.buffer = buf;
+
+ i2c_xfer(1, &rq, 0);
+ }
+ }
+ }
+ // CS5 setup
+ writel(0, IOMUXC_BASE_ADDR + 0xF4);
+ weim_base = WEIM_BASE_ADDR + 0x78;
+ writel(0x00410089, weim_base + CSGCR1);
+ writel(0x00000002, weim_base + CSGCR2);
+ // RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0
+ writel(0x32260000, weim_base + CSRCR1);
+ // APR=0
+ writel(0x00000000, weim_base + CSRCR2);
+ // WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, WCSA=0, WCSN=0
+ writel(0x72080F00, weim_base + CSWCR1);
+ cpld_base_addr = CS5_BASE_ADDR;
+
+ /* Reset interrupt status reg */
+ writew(0x1F, cpld_base_addr + PBC_INT_REST);
+ writew(0x00, cpld_base_addr + PBC_INT_REST);
+ writew(0xFFFF, cpld_base_addr + PBC_INT_MASK);
+
+ /* Reset the XUART and Ethernet controllers */
+ sw_rest_reg = readw(cpld_base_addr + PBC_SW_RESET);
+ sw_rest_reg |= 0x9;
+ writew(sw_rest_reg, cpld_base_addr + PBC_SW_RESET);
+ sw_rest_reg &= ~0x9;
+ writew(sw_rest_reg, cpld_base_addr + PBC_SW_RESET);
+
+ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
+ // UART1
+ //RXD
+ writel(0x0, IOMUXC_BASE_ADDR + 0x228);
+ writel(0x1C5, IOMUXC_BASE_ADDR + 0x618);
+ //TXD
+ writel(0x0, IOMUXC_BASE_ADDR + 0x22c);
+ writel(0x1C5, IOMUXC_BASE_ADDR + 0x61c);
+ //RTS
+ writel(0x0, IOMUXC_BASE_ADDR + 0x230);
+ writel(0x1C4, IOMUXC_BASE_ADDR + 0x620);
+ //CTS
+ writel(0x0, IOMUXC_BASE_ADDR + 0x234);
+ writel(0x1C4, IOMUXC_BASE_ADDR + 0x624);
+ // enable GPIO1_9 for CLKO and GPIO1_8 for CLKO2
+ writel(0x00000004, 0x73fa83E8);
+ writel(0x00000004, 0x73fa83Ec);
+ } else {
+ // UART1
+ //RXD
+ writel(0x0, IOMUXC_BASE_ADDR + 0x234);
+ writel(0x1C5, IOMUXC_BASE_ADDR + 0x6E4);
+ //TXD
+ writel(0x0, IOMUXC_BASE_ADDR + 0x238);
+ writel(0x1C5, IOMUXC_BASE_ADDR + 0x6E8);
+ //RTS
+ writel(0x0, IOMUXC_BASE_ADDR + 0x23C);
+ writel(0x1C4, IOMUXC_BASE_ADDR + 0x6EC);
+ //CTS
+ writel(0x0, IOMUXC_BASE_ADDR + 0x240);
+ writel(0x1C4, IOMUXC_BASE_ADDR + 0x6F0);
+ // enable GPIO1_9 for CLKO and GPIO1_8 for CLKO2
+ writel(0x00000004, 0x73fa83F4);
+ writel(0x00000004, 0x73fa83F0);
+ }
+
+ // enable ARM clock div by 8
+ writel(0x010900F0, CCM_BASE_ADDR + CLKCTL_CCOSR);
+#ifdef MXCFLASH_SELECT_NAND
+ nfc_iomux_setup = (nfc_iomuxsetup_func_t*)mxc_nfc_iomux_setup;
+#endif
+ mxc_fec_setup();
+}
+
+void mxc_mmc_init(unsigned int base_address)
+{
+ switch(base_address) {
+ case MMC_SDHC1_BASE_ADDR:
+ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
+ /* SD1 CMD, SION bit */
+ writel(0x10, IOMUXC_BASE_ADDR + 0x394);
+ /* Configure SW PAD */
+ /* SD1 CMD */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x79C);
+ /* SD1 CLK */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x7A0);
+ /* SD1 DAT0 */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x7A4);
+ /* SD1 DAT1 */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x7A8);
+ /* SD1 DAT2 */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x7AC);
+ /* SD1 DAT3 */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x7B0);
+ } else {
+ /* SD1 CMD, SION bit */
+ writel(0x10, IOMUXC_BASE_ADDR + 0x39c);
+ /* SD1 CD, as gpio1_0 */
+ writel(0x01, IOMUXC_BASE_ADDR + 0x3b4);
+ /* Configure SW PAD */
+ /* SD1 CMD */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x868);
+ /* SD1 CLK */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x86c);
+ /* SD1 DAT0 */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x870);
+ /* SD1 DAT1 */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x874);
+ /* SD1 DAT2 */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x878);
+ /* SD1 DAT3 */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x87c);
+ /* SD1 CD as gpio1_0 */
+ writel(0x1e2, IOMUXC_BASE_ADDR + 0x880);
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+void increase_core_voltage(bool i)
+{
+ unsigned char buf[4];
+ struct mxc_i2c_request rq;
+
+
+ rq.dev_addr = 0x8;
+ rq.reg_addr = 24;
+ rq.reg_addr_sz = 1;
+ rq.buffer_sz = 3;
+ rq.buffer = buf;
+
+ i2c_xfer(1, &rq, 1);
+
+ if (i) {
+ buf[2] = buf[2] & (~0x1F) | 0x17;
+ } else {
+ buf[2] = buf[2] & (~0x1F) | 0x12;
+ }
+ i2c_xfer(1, &rq, 0);
+}
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+typedef void code_fun(void);
+
+void board_program_new_stack(void *func)
+{
+ register CYG_ADDRESS stack_ptr asm("sp");
+ register CYG_ADDRESS old_stack asm("r4");
+ register code_fun *new_func asm("r0");
+ old_stack = stack_ptr;
+ stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
+ new_func = (code_fun*)func;
+ new_func();
+ stack_ptr = old_stack;
+}
+
--- /dev/null
+//==========================================================================
+//
+// redboot_cmds.c
+//
+// Board [platform] specific RedBoot commands
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+#include <redboot.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/plf_mmap.h>
+#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <flash_config.h>
+
+#if (REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE)
+#error REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE
+#endif
+
+RedBoot_config_option("Board specifics",
+ brd_specs,
+ ALWAYS_ENABLED,
+ true,
+ CONFIG_INT,
+ 0
+ );
+#endif //CYGSEM_REDBOOT_FLASH_CONFIG
+
+char HAL_PLATFORM_EXTRA[20] = "PASS x.x [x32 DDR]";
+
+static void runImg(int argc, char *argv[]);
+
+RedBoot_cmd("run",
+ "Run an image at a location with MMU off",
+ "[<virtual addr>]",
+ runImg
+ );
+
+void launchRunImg(unsigned long addr)
+{
+ asm volatile ("mov r12, r0;");
+ HAL_CACHE_FLUSH_ALL();
+ HAL_DISABLE_L2();
+ HAL_MMU_OFF();
+ asm volatile (
+ "mov r0, #0;"
+ "mov r1, r12;"
+ "mov r11, #0;"
+ "mov r12, #0;"
+ "mrs r10, cpsr;"
+ "bic r10, r10, #0xF0000000;"
+ "msr cpsr_f, r10;"
+ "mov pc, r1"
+ );
+}
+
+extern unsigned long entry_address;
+
+static void runImg(int argc,char *argv[])
+{
+ unsigned int virt_addr, phys_addr;
+
+ // Default physical entry point for Symbian
+ if (entry_address == 0xFFFFFFFF)
+ virt_addr = 0x800000;
+ else
+ virt_addr = entry_address;
+
+ if (!scan_opts(argc,argv,1,0,0,(void*)&virt_addr,
+ OPTION_ARG_TYPE_NUM, "virtual address"))
+ return;
+
+ if (entry_address != 0xFFFFFFFF)
+ diag_printf("load entry_address=0x%lx\n", entry_address);
+ HAL_VIRT_TO_PHYS_ADDRESS(virt_addr, phys_addr);
+
+ diag_printf("virt_addr=0x%x\n",virt_addr);
+ diag_printf("phys_addr=0x%x\n",phys_addr);
+
+ launchRunImg(phys_addr);
+}
+
+#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYG_HAL_STARTUP_ROMRAM)
+
+RedBoot_cmd("romupdate",
+ "Update Redboot with currently running image",
+ "",
+ romupdate
+ );
+
+extern int flash_program(void *_addr, void *_data, int len, void **err_addr);
+extern int flash_erase(void *addr, int len, void **err_addr);
+extern char *flash_errmsg(int err);
+extern unsigned char *ram_end; //ram end is where the redboot starts FIXME: use PC value
+
+#ifdef CYGPKG_IO_FLASH
+void romupdate(int argc, char *argv[])
+{
+ void *err_addr, *base_addr;
+ int stat;
+ unsigned int nfc_config3_reg, temp;
+
+ if (IS_FIS_FROM_MMC() || IS_BOOTING_FROM_MMC()) {
+ diag_printf("Updating ROM in MMC/SD flash\n");
+ /* eMMC 4.3 and eSD 2.1 supported only on TO 2.0 */
+ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
+ if(!emmc_set_boot_partition((cyg_uint32*)ram_end, CYGBLD_REDBOOT_MIN_IMAGE_SIZE)) {
+ /* eMMC 4.3 */
+ diag_printf("Card supports MMC-4.3, programming for boot operation.\n");
+ return;
+ } else if(!esd_set_boot_partition((cyg_uint32*)ram_end, CYGBLD_REDBOOT_MIN_IMAGE_SIZE)) {
+ /* eSD 2.1 */
+ diag_printf("Card supports SD-2.1, programming for boot operation.\n");
+ return;
+ }
+ }
+ base_addr = (void*)0;
+ /* Read the first 1K from the card */
+ mmc_data_read((cyg_uint32*)ram_end, 0x400, base_addr);
+ diag_printf("Programming Redboot to MMC/SD flash\n");
+ mmc_data_write((cyg_uint32*)ram_end, CYGBLD_REDBOOT_MIN_IMAGE_SIZE, (cyg_uint32)base_addr);
+
+ return;
+ } else if (IS_FIS_FROM_NAND() || IS_BOOTING_FROM_NAND()) {
+ diag_printf("Updating ROM in NAND flash\n");
+ base_addr = (void*)0;
+ nfc_config3_reg = readl(NFC_FLASH_CONFIG3_REG);
+ temp = nfc_config3_reg & (~ 0x7003);
+ writel(temp, NFC_FLASH_CONFIG3_REG);
+ } else {
+ diag_printf("romupdate not supported\n");
+ diag_printf("Use \"factive [NAND|MMC]\" to select either NAND or MMC flash\n");
+ }
+
+ // Erase area to be programmed
+ if ((stat = flash_erase((void *)base_addr,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ (void **)&err_addr)) != 0) {
+ diag_printf("Can't erase region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ return;
+ }
+ // Now program it
+ if ((stat = flash_program((void *)base_addr, (void *)ram_end,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ (void **)&err_addr)) != 0) {
+ diag_printf("Can't program region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ }
+ if (IS_FIS_FROM_NAND() || IS_BOOTING_FROM_NAND())
+ writel(nfc_config3_reg, NFC_FLASH_CONFIG3_REG);
+}
+RedBoot_cmd("factive",
+ "Enable one flash media for Redboot",
+ "[NAND | MMC]",
+ factive
+ );
+
+typedef void reset_func_t(void);
+
+extern reset_func_t reset_vector;
+
+void factive(int argc, char *argv[])
+{
+ unsigned long phys_addr;
+ unsigned int *fis_addr = IRAM_BASE_ADDR;
+
+ if (argc != 2) {
+ diag_printf("Invalid factive cmd\n");
+ return;
+ }
+
+ if (strcasecmp(argv[1], "NOR") == 0) {
+ diag_printf("Not supported\n");
+ return;
+ } else if (strcasecmp(argv[1], "NAND") == 0) {
+#ifndef MXCFLASH_SELECT_NAND
+ diag_printf("Not supported\n");
+ return;
+#endif
+ *fis_addr = FROM_NAND_FLASH;
+ } else if (strcasecmp(argv[1], "MMC") == 0) {
+#ifndef MXCFLASH_SELECT_MMC
+ diag_printf("Not supported\n");
+ return;
+#else
+ *fis_addr = FROM_MMC_FLASH;
+#endif
+ } else {
+ diag_printf("Invalid command: %s\n", argv[1]);
+ return;
+ }
+
+ //HAL_VIRT_TO_PHYS_ADDRESS(ram_end, phys_addr);
+ launchRunImg(reset_vector);
+}
+#endif //CYGPKG_IO_FLASH
+#endif /* CYG_HAL_STARTUP_ROMRAM */
--- /dev/null
+# ====================================================================
+#
+# hal_arm_board.cdl
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+
+cdl_package CYGPKG_HAL_ARM_MX51_BABBAGE {
+ display "Freescale board"
+ parent CYGPKG_HAL_ARM_MX51
+ hardware
+ include_dir cyg/hal
+ define_header hal_arm_board.h
+ description "
+ This HAL platform package provides generic
+ support for the Freescale MX51 Babbage Board."
+
+ compile board_misc.c board_diag.c
+ implements CYGINT_HAL_DEBUG_GDB_STUBS
+ implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+ implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+
+ #implements CYGHWR_HAL_ARM_DUART_UARTB
+ implements CYGHWR_HAL_ARM_SOC_UART1
+ #implements CYGHWR_HAL_ARM_SOC_UART2
+ #implements CYGHWR_HAL_ARM_SOC_UART3
+
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_soc.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_board.h>"
+ puts $::cdl_header "#define HAL_PLATFORM_CPU \"Freescale i.MX51 based\""
+ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"MX51 Babbage\""
+ puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 2000"
+ puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK board_program_new_stack"
+ }
+
+ cdl_component CYG_HAL_STARTUP {
+ display "Startup type"
+ flavor data
+ default_value {"ROM"}
+ legal_values {"RAM" "ROM" "ROMRAM"}
+ no_define
+ define -file system.h CYG_HAL_STARTUP
+ description "
+ When targetting the eval board it is possible to build
+ the system for either RAM bootstrap or ROM bootstrap(s). Select
+ 'ram' when building programs to load into RAM using eCos GDB
+ stubs. Select 'rom' when building a stand-alone application
+ which will be put into ROM, or for the special case of
+ building the eCos GDB stubs themselves. Using ROMRAM will allow
+ the program to exist in ROM, but be copied to RAM during startup."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_DUART_UARTA {
+ display "ST16552 UARTA available as diagnostic/debug channel"
+ description "
+ The board has a ST16552 DUART chip. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_DUART_UARTB {
+ display "ST16552 UARTB available as diagnostic/debug channel"
+ description "
+ The board has a ST16552 DUART chip. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ display "Diagnostic serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the console port.
+ Note: this should match the value chosen for the GDB port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ display "GDB serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the GDB port.
+ Note: this should match the value chosen for the console port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the board"
+ flavor data
+ calculated 6
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ The board has three serial ports. This option
+ chooses which port will be used to connect to a host
+ running GDB."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+ display "Default console channel."
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ calculated 0
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Console serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ description "
+ The board has only three serial ports. This option
+ chooses which port will be used for console output."
+ }
+
+ cdl_component CYGBLD_GLOBAL_OPTIONS {
+ display "Global build options"
+ flavor none
+ no_define
+ description "
+ Global build options including control over
+ compiler flags, linker flags and choice of toolchain."
+
+
+ parent CYGPKG_NONE
+
+ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ display "Global command prefix"
+ flavor data
+ no_define
+ default_value { "arm-none-eabi" }
+ description "
+ This option specifies the command prefix used when
+ invoking the build tools."
+ }
+
+ cdl_option CYGBLD_GLOBAL_CFLAGS {
+ display "Global compiler flags"
+ flavor data
+ no_define
+ default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ description "
+ This option controls the global compiler flags which are used to
+ compile all packages by default. Individual packages may define
+ options which override these global flags."
+ }
+
+ cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ display "Global linker flags"
+ flavor data
+ no_define
+ default_value { "-Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" }
+ description "
+ This option controls the global linker flags. Individual
+ packages may define options which override these global flags."
+ }
+
+ cdl_option CYGBLD_BUILD_GDB_STUBS {
+ display "Build GDB stub ROM image"
+ default_value 0
+ requires { CYG_HAL_STARTUP == "ROM" }
+ requires CYGSEM_HAL_ROM_MONITOR
+ requires CYGBLD_BUILD_COMMON_GDB_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ no_define
+ description "
+ This option enables the building of the GDB stubs for the
+ board. The common HAL controls takes care of most of the
+ build process, but the final conversion from ELF image to
+ binary data is handled by the platform CDL, allowing
+ relocation of the data if necessary."
+
+ make -priority 320 {
+ <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
+ $(OBJCOPY) --remove-section=.fixed_vectors -O binary $< $@
+ }
+ }
+ }
+
+ cdl_component CYGPKG_HAL_ARM_BOARD_OPTIONS {
+ display "Freescale MXC Board build options"
+ flavor none
+ no_define
+ description "
+ Package specific build options including control over
+ compiler flags used only in building this package,
+ and details of which tests are built."
+
+ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the board HAL. These flags are used in addition
+ to the set of global flags."
+ }
+
+ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_REMOVE {
+ display "Suppressed compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the board HAL. These flags are removed from
+ the set of global flags if present."
+ }
+
+ }
+
+ cdl_component CYGHWR_MEMORY_LAYOUT {
+ display "Memory layout"
+ flavor data
+ no_define
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_board_ram" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" :
+ "arm_board_rom" }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ display "Memory layout linker script fragment"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.ldi>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.ldi>" :
+ "<pkgconf/mlt_arm_board_rom.ldi>" }
+ }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ display "Memory layout header file"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_H
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.h>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.h>" :
+ "<pkgconf/mlt_arm_board_rom.h>" }
+ }
+ }
+
+ cdl_option CYGSEM_HAL_ROM_MONITOR {
+ display "Behave as a ROM monitor"
+ flavor bool
+ default_value 0
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+ description "
+ Enable this option if this program is to be used as a ROM monitor,
+ i.e. applications will be loaded into RAM on the board, and this
+ ROM monitor may process exceptions or interrupts generated from the
+ application. This enables features such as utilizing a separate
+ interrupt stack when exceptions are generated."
+ }
+
+ cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ display "Work with a ROM monitor"
+ flavor booldata
+ legal_values { "Generic" "GDB_stubs" }
+ default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "RAM" }
+ description "
+ Support can be enabled for different varieties of ROM monitor.
+ This support changes various eCos semantics such as the encoding
+ of diagnostic output, or the overriding of hardware interrupt
+ vectors.
+ Firstly there is \"Generic\" support which prevents the HAL
+ from overriding the hardware vectors that it does not use, to
+ instead allow an installed ROM monitor to handle them. This is
+ the most basic support which is likely to be common to most
+ implementations of ROM monitor.
+ \"GDB_stubs\" provides support when GDB stubs are included in
+ the ROM monitor or boot ROM."
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ display "Redboot HAL options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+ description "
+ This option lists the target's requirements for a valid Redboot
+ configuration."
+
+ compile -library=libextras.a redboot_cmds.c
+
+ cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ display "Build Redboot ROM binary image"
+ active_if CYGBLD_BUILD_REDBOOT
+ default_value 1
+ no_define
+ description "This option enables the conversion of the Redboot ELF
+ image to a binary image suitable for ROM programming."
+
+ make -priority 325 {
+ <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+ $(OBJCOPY) -O binary $< $@
+ }
+ }
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_BOARD_OPTIONS {
+ display "Redboot HAL variant options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+
+ # RedBoot details
+ requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x90008000 }
+ define_proc {
+ puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00"
+ }
+ }
+}
--- /dev/null
+#ifndef CYGONCE_FSL_BOARD_H
+#define CYGONCE_FSL_BOARD_H
+
+//=============================================================================
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+
+#define BOARD_CS_UART_BASE (0x8000)
+
+#define REDBOOT_IMAGE_SIZE 0x40000
+
+#define PMIC_SPI_BASE CSPI1_BASE_ADDR
+#define PMIC_SPI_CHIP_SELECT_NO SPI_CTRL_CS0
+#define PMIC_SPI_SS_POL SPI_CFG_SS0_POL_HIGH
+
+#define FEC_PHY_ADDR 0
+
+/* MX51 3-Stack SDRAM is from 0x40000000, 128M */
+#define SDRAM_BASE_ADDR CSD0_BASE_ADDR
+#define SDRAM_SIZE 0x20000000
+#define RAM_BANK0_BASE SDRAM_BASE_ADDR
+
+#endif /* CYGONCE_FSL_BOARD_H */
--- /dev/null
+#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
+#define CYGONCE_HAL_PLATFORM_SETUP_H
+
+//=============================================================================
+//
+// hal_platform_setup.h
+//
+// Platform specific support for HAL (assembly code)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <pkgconf/system.h> // System-wide configuration info
+#include CYGBLD_HAL_VARIANT_H // Variant specific configuration
+#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
+#include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
+#include <cyg/hal/hal_mmu.h> // MMU definitions
+#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1 _platform_setup1
+#define CYGHWR_HAL_ARM_HAS_MMU
+
+#ifdef CYG_HAL_STARTUP_ROMRAM
+#define CYGSEM_HAL_ROM_RESET_USES_JUMP
+#endif
+
+//#define NFC_2K_BI_SWAP
+#define SDRAM_FULL_PAGE_BIT 0x100
+#define SDRAM_FULL_PAGE_MODE 0x37
+#define SDRAM_BURST_MODE 0x33
+
+#define CYGHWR_HAL_ROM_VADDR 0x0
+
+#if 0
+#define UNALIGNED_ACCESS_ENABLE
+#define SET_T_BIT_DISABLE
+#define BRANCH_PREDICTION_ENABLE
+#endif
+
+#define DCDGEN(i,type, addr, data) \
+dcd_##i: ;\
+ .long type ;\
+ .long addr ;\
+ .long data
+
+#define PLATFORM_PREAMBLE flash_header
+//flash header & DCD @ 0x400
+.macro flash_header
+ b reset_vector
+ .org 0x400
+app_code_jump_v: .long reset_vector
+app_code_barker: .long 0xB1
+app_code_csf: .long 0
+dcd_ptr_ptr: .long dcd_ptr
+super_root_key: .long 0
+dcd_ptr: .long dcd_data
+app_dest_ptr: .long 0xAFF00000
+
+dcd_data: .long 0xB17219E9 // Fixed. can't change.
+dcd_len: .long (20*12)
+
+//DCD
+ // ldr r0, ESDCTL_BASE_W
+ // /* Set CSD0 */
+ // ldr r1, =0x80000000
+ // str r1, [r0, #ESDCTL_ESDCTL0]
+DCDGEN(1, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x80000000)
+ // /* Precharge command */
+ // ldr r1, SDRAM_0x04008008
+ // str r1, [r0, #ESDCTL_ESDSCR]
+DCDGEN(2, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+ // /* 2 refresh commands */
+ // ldr r1, SDRAM_0x00008010
+ // str r1, [r0, #ESDCTL_ESDSCR]
+DCDGEN(3, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+ // str r1, [r0, #ESDCTL_ESDSCR]
+DCDGEN(4, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+ // /* LMR with CAS=3 and BL=3 */
+ // ldr r1, SDRAM_0x00338018
+ // str r1, [r0, #ESDCTL_ESDSCR]
+DCDGEN(5, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00338018)
+ // /* 14 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
+ // ldr r1, SDRAM_0xB2220000
+ // str r1, [r0, #ESDCTL_ESDCTL0]
+DCDGEN(6, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xC3220000)
+ // /* Timing parameters */
+ // ldr r1, SDRAM_0xB02567A9
+ // str r1, [r0, #ESDCTL_ESDCFG0]
+DCDGEN(7, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0xB08567A9)
+ // /* MDDR enable, RLAT=2 */
+ // ldr r1, SDRAM_0x000A0104
+ // str r1, [r0, #ESDCTL_ESDMISC]
+DCDGEN(8, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000A0104)
+ // /* Normal mode */
+ // ldr r1, =0x00000000
+ // str r1, [r0, #ESDCTL_ESDSCR]
+DCDGEN(9, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0)
+
+//////////////////// csd1 //////////////////
+DCDGEN(10, 4, 0x83fd9008, 0x80000000)
+ //Precharge command
+ //setmem /32 0x83fd9014 = 0x0400800C // [MK]
+DCDGEN(11, 4, 0x83fd9014, 0x0400800C)
+ //2 Refresh commands
+ //setmem /32 0x83fd9014 = 0x00008014 // [MK]
+DCDGEN(12, 4, 0x83fd9014, 0x00008014)
+ //setmem /32 0x83fd9014 = 0x00008014 // [MK]
+DCDGEN(13, 4, 0x83fd9014, 0x00008014)
+ //LMR with CAS=3 and BL=3
+ //setmem /32 0x83fd9014 = 0x0033801C // [MK]
+DCDGEN(14, 4, 0x83fd9014, 0x0033801C)
+ //14 ROW, 10 COL, 32Bit, SREF=8 Micron Model
+ //setmem /32 0x83fd9008 = 0xC3220000
+DCDGEN(15, 4, 0x83fd9008, 0xC3220000)
+ //Timing parameters
+ //setmem /32 0x83fd900C = 0xB08567A9
+DCDGEN(16, 4, 0x83fd900C, 0xB08567A9)
+ //MDDR enable, RLAT=2
+ //setmem /32 0x83fd9010 = 0x000a0104
+DCDGEN(17, 4, 0x83fd9010, 0x000a0104)
+ //Normal mode
+ //setmem /32 0x83fd9014 = 0x00000004 // [DB]
+DCDGEN(18, 4, 0x83fd9014, 0x00000004)
+ //setmem /32 0x90000000 = 0x00000000
+DCDGEN(19, 4, 0x90000000, 0x00000000)
+ //setmem /32 0xA0000000 = 0x00000000
+DCDGEN(20, 4, 0xA0000000, 0x00000000)
+
+image_len: .long 256*1024
+
+.endm
+
+//#define ENABLE_IMPRECISE_ABORT
+
+// This macro represents the initial startup code for the platform
+ .macro _platform_setup1
+FSL_BOARD_SETUP_START:
+ // mrc p15, 0, r0, c1, c1, 0 // Read Secure Configuration Register data. Why doesn't work???
+ // mcr p15, 0, <Rd>, c1, c1, 0 ; Write Secure Configuration Register data
+#ifdef ENABLE_IMPRECISE_ABORT
+ mrs r1, spsr // save old spsr
+ mrs r0, cpsr // read out the cpsr
+ bic r0, r0, #0x100 // clear the A bit
+ msr spsr, r0 // update spsr
+ add lr, pc, #0x8 // update lr
+ movs pc, lr // update cpsr
+ nop
+ nop
+ nop
+ nop
+ msr spsr, r1 // restore old spsr
+#endif
+ // explicitly disable L2 cache
+ mrc 15, 0, r0, c1, c0, 1
+ bic r0, r0, #0x2
+ mcr 15, 0, r0, c1, c0, 1
+
+ // reconfigure L2 cache aux control reg
+ mov r0, #0xC0 // tag RAM
+ add r0, r0, #0x4 // data RAM
+ orr r0, r0, #(1 << 25) // disable write combine
+ orr r0, r0, #(1 << 24) // disable write allocate delay
+ orr r0, r0, #(1 << 23) // disable write allocate combine
+ orr r0, r0, #(1 << 22) // disable write allocate
+
+ mcr 15, 1, r0, c9, c0, 2
+
+init_spba_start:
+ init_spba
+init_aips_start:
+ init_aips
+init_max_start:
+ init_max
+init_m4if_start:
+ init_m4if
+init_iomux_start:
+// init_iomux
+
+ // disable wdog
+ ldr r0, =0x30
+ ldr r1, WDOG1_BASE_W
+ strh r0, [r1]
+
+init_clock_start:
+ init_clock
+
+#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
+ /* Copy image from flash to SDRAM first */
+ ldr r0, =0xFFFFF000
+ and r0, r0, pc
+ ldr r1, MXC_REDBOOT_ROM_START
+ cmp r0, r1
+ beq HWInitialise_skip_SDRAM_copy
+
+ add r2, r0, #REDBOOT_IMAGE_SIZE
+
+1: ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ ble 1b
+ /* Jump to SDRAM */
+ ldr r1, =0xFFFF
+ and r0, pc, r1 /* offset of pc */
+ ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
+ add pc, r0, r1
+ nop
+ nop
+ nop
+ nop
+#endif /* CYG_HAL_STARTUP_ROMRAM */
+
+HWInitialise_skip_SDRAM_copy:
+
+init_cs1_start:
+// init_cs1 -- moved to plf_hardware_init()
+
+/*
+ * Note:
+ * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
+ */
+STACK_Setup:
+ // Set up a stack [for calling C code]
+ ldr r1, =__startup_stack
+ ldr r2, =RAM_BANK0_BASE
+ orr sp, r1, r2
+
+ // Create MMU tables
+ bl hal_mmu_init
+
+ // Enable MMU
+ ldr r2, =10f
+ ldr r0, =ROM_BASE_ADDRESS
+ ldr r3, [r0, #ROM_SI_REV_OFFSET]
+ cmp r3, #0x1
+ bne skip_L1_workaround
+ // Workaround for L1 cache issue
+ mrc MMU_CP, 0, r1, c10, c2, 1 // Read normal memory remap register
+ bic r1, r1, #(3 << 14) // Remap inner attribute for TEX[0],C,B = b111 as noncacheable
+ bic r1, r1, #(3 << 6) // Remap inner attribute for TEX[0],C,B = b011 as noncacheable
+ bic r1, r1, #(3 << 4) // Remap inner attribute for TEX[0],C,B = b010 as noncacheable
+ mcr MMU_CP, 0, r1, c10, c2, 1 // Write normal memory remap register
+skip_L1_workaround:
+ mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
+ orr r1, r1, #7 // enable MMU bit
+ orr r1, r1, #0x800 // enable z bit
+ orrne r1, r1, #(1 << 28) // Enable TEX remap, workaround for L1 cache issue
+ mcr MMU_CP, 0, r1, MMU_Control, c0
+ mov pc,r2 /* Change address spaces */
+ nop
+ nop
+ nop
+10:
+
+ // Save shadow copy of BCR, also hardware configuration
+ ldr r1, =_board_BCR
+ str r2, [r1]
+ ldr r1, =_board_CFG
+ str r9, [r1] // Saved far above...
+
+ .endm // _platform_setup1
+
+#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1
+#endif
+
+ /* Do nothing */
+ .macro init_spba
+ .endm /* init_spba */
+
+ /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
+ .macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, AIPS1_CTRL_BASE_ADDR_W
+ ldr r1, AIPS1_PARAM_W
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ ldr r0, AIPS2_CTRL_BASE_ADDR_W
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+
+ .endm /* init_aips */
+
+ /* MAX (Multi-Layer AHB Crossbar Switch) setup */
+ .macro init_max
+ .endm /* init_max */
+
+ .macro init_clock
+ ldr r0, CCM_BASE_ADDR_W
+ /* Disable IPU and HSC dividers */
+ mov r1, #0x60000
+ str r1, [r0, #CLKCTL_CCDR]
+
+ /* Switch ARM to step clock */
+ mov r1, #0x4
+ str r1, [r0, #CLKCTL_CCSR]
+ setup_pll PLL1, 800
+
+ /* Switch peripheral to PLL 3 */
+ ldr r0, CCM_BASE_ADDR_W
+ ldr r1, CCM_VAL_0x0000D3C0
+ str r1, [r0, #CLKCTL_CBCMR]
+ ldr r1, CCM_VAL_0x033B9145
+ str r1, [r0, #CLKCTL_CBCDR]
+ setup_pll PLL2, 665
+ /* Switch peripheral to PLL 2 */
+ ldr r0, CCM_BASE_ADDR_W
+ ldr r1, CCM_VAL_0x013B9145
+ str r1, [r0, #CLKCTL_CBCDR]
+ ldr r1, CCM_VAL_0x0000E3C0
+ str r1, [r0, #CLKCTL_CBCMR]
+
+ setup_pll PLL3, 216
+
+ /* Set the platform clock dividers */
+ ldr r0, PLATFORM_BASE_ADDR_W
+ ldr r1, PLATFORM_CLOCK_DIV_W
+ str r1, [r0, #PLATFORM_ICGC]
+
+ /* Switch ARM back to PLL 1. */
+ ldr r0, CCM_BASE_ADDR_W
+ mov r1, #0x0
+ str r1, [r0, #CLKCTL_CCSR]
+
+ /* setup the rest */
+ mov r1, #0
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Use lp_apm (24MHz) source for perclk */
+ ldr r1, CCM_VAL_0x0000E3C2
+ str r1, [r0, #CLKCTL_CBCMR]
+ // emi=ahb, all perclk dividers are 1 since using 24MHz
+ // DDR divider=6 to have 665/6=110MHz
+ ldr r1, CCM_VAL_0x013D9100
+ str r1, [r0, #CLKCTL_CBCDR]
+
+ /* Use PLL 2 for UART's, get 66.5MHz from it */
+ ldr r1, CCM_VAL_0xA5A2A020
+ str r1, [r0, #CLKCTL_CSCMR1]
+ ldr r1, CCM_VAL_0x00C30321
+ str r1, [r0, #CLKCTL_CSCDR1]
+
+ /* make sure divider effective */
+ 1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ mov r1, #0x00000
+ str r1, [r0, #CLKCTL_CCDR]
+
+ // for cko - for ARM div by 8
+ mov r1, #0x000A0000
+ add r1, r1, #0x00000F0
+ str r1, [r0, #CLKCTL_CCOSR]
+ .endm /* init_clock */
+
+ .macro setup_pll pll_nr, mhz
+ ldr r0, BASE_ADDR_W_\pll_nr
+ ldr r1, PLL_VAL_0x1232
+ str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
+ ldr r1, =0x2
+ str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+
+ ldr r1, W_DP_OP_\mhz
+ str r1, [r0, #PLL_DP_OP]
+ str r1, [r0, #PLL_DP_HFS_OP]
+
+ ldr r1, W_DP_MFD_\mhz
+ str r1, [r0, #PLL_DP_MFD]
+ str r1, [r0, #PLL_DP_HFS_MFD]
+
+ ldr r1, W_DP_MFN_\mhz
+ str r1, [r0, #PLL_DP_MFN]
+ str r1, [r0, #PLL_DP_HFS_MFN]
+
+ /* Now restart PLL */
+ ldr r1, PLL_VAL_0x1232
+ str r1, [r0, #PLL_DP_CTL]
+wait_pll_lock\pll_nr:
+ ldr r1, [r0, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+ beq wait_pll_lock\pll_nr
+ .endm
+
+ /* M4IF setup */
+ .macro init_m4if
+ /* Configure M4IF registers, VPU and IPU given higher priority (=0x4)
+ IPU accesses with ID=0x1 given highest priority (=0xA) */
+ ldr r1, M4IF_BASE_W
+ ldr r0, M4IF_0x00000a01
+ str r0, [r1, #M4IF_FIDBP]
+
+ ldr r0, M4IF_0x00000404
+ str r0, [r1, #M4IF_FBPM0]
+ .endm /* init_m4if */
+
+ .macro init_iomux
+ // do nothing
+ .endm /* init_iomux */
+
+#define PLATFORM_VECTORS _platform_vectors
+ .macro _platform_vectors
+ .globl _board_BCR, _board_CFG
+_board_BCR: .long 0 // Board Control register shadow
+_board_CFG: .long 0 // Board Configuration (read at RESET)
+ .endm
+
+WDOG1_BASE_W: .word WDOG1_BASE_ADDR
+IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
+AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
+AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
+AIPS1_PARAM_W: .word 0x77777777
+MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
+MAX_PARAM1: .word 0x00302154
+ESDCTL_BASE_W: .word ESDCTL_BASE_ADDR
+M4IF_BASE_W: .word M4IF_BASE_ADDR
+M4IF_0x00000a01: .word 0x00000a01
+M4IF_0x00000404: .word 0x00000404
+NFC_BASE_W: .word NFC_BASE_ADDR_AXI
+NFC_IP_BASE_W: .word NFC_IP_BASE
+IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
+MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
+CONST_0x0FFF: .word 0x0FFF
+CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
+CCM_VAL_0x0000E3C2: .word 0x0000E3C2
+CCM_VAL_0x013D9100: .word 0x013D9100
+CCM_VAL_0xA5A2A020: .word 0xA5A2A020
+CCM_VAL_0x00C30321: .word 0x00C30321
+CCM_VAL_0x0000D3C0: .word 0x0000D3C0
+CCM_VAL_0x033B9145: .word 0x033B9145
+CCM_VAL_0x013B9145: .word 0x013B9145
+CCM_VAL_0x0000E3C0: .word 0x0000E3C0
+PLL_VAL_0x222: .word 0x222
+PLL_VAL_0x232: .word 0x232
+BASE_ADDR_W_PLL1: .word PLL1_BASE_ADDR
+BASE_ADDR_W_PLL2: .word PLL2_BASE_ADDR
+BASE_ADDR_W_PLL3: .word PLL3_BASE_ADDR
+PLL_VAL_0x1232: .word 0x1232
+W_DP_OP_800: .word DP_OP_800
+W_DP_MFD_800: .word DP_MFD_800
+W_DP_MFN_800: .word DP_MFN_800
+W_DP_OP_700: .word DP_OP_700
+W_DP_MFD_700: .word DP_MFD_700
+W_DP_MFN_700: .word DP_MFN_700
+W_DP_OP_400: .word DP_OP_400
+W_DP_MFD_400: .word DP_MFD_400
+W_DP_MFN_400: .word DP_MFN_400
+W_DP_OP_532: .word DP_OP_532
+W_DP_MFD_532: .word DP_MFD_532
+W_DP_MFN_532: .word DP_MFN_532
+W_DP_OP_665: .word DP_OP_665
+W_DP_MFD_665: .word DP_MFD_665
+W_DP_MFN_665: .word DP_MFN_665
+W_DP_OP_216: .word DP_OP_216
+W_DP_MFD_216: .word DP_MFD_216
+W_DP_MFN_216: .word DP_MFN_216
+PLATFORM_BASE_ADDR_W: .word PLATFORM_BASE_ADDR
+PLATFORM_CLOCK_DIV_W: .word 0x00000725
+_nand_pg_sz: .word 0
+
+/*---------------------------------------------------------------------------*/
+/* end of hal_platform_setup.h */
+#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x00000000)
+#define CYGMEM_REGION_ram_SIZE (0x1FF00000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0xAFF00000)
+#define CYGMEM_REGION_rom_SIZE (0x100000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ ram : ORIGIN = 0, LENGTH = 0x1FF00000
+ rom : ORIGIN = 0xAFF00000, LENGTH = 0x100000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_rom_vectors (rom, 0xAFF00000, LMA_EQ_VMA)
+ SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
+ SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table))
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
--- /dev/null
+version 0
+region ram 0 1FF00000 0 !
+region rom AFF00000 100000 1 !
+section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
+section data 0 1 1 1 1 1 0 0 8000 bss !
+section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
+section heap1 0 8 0 0 0 0 0 0 !
+section rom_vectors 0 1 0 1 1 1 1 1 AFF00000 AFF00000 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata rodata !
+section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 4 0 1 0 0 0 1 data !
--- /dev/null
+#ifndef CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+#define CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+
+//=============================================================================
+//
+// plf_io.h
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/hal/fsl_board.h>
+#include <cyg/hal/hal_soc.h>
+
+#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \
+ CYG_MACRO_START \
+ { \
+ extern unsigned int system_rev; \
+ /* Next ATAG_MEM. */ \
+ _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header)) / sizeof(long); \
+ _p_->hdr.tag = ATAG_MEM; \
+ /* Round up so there's only one bit set in the memory size. \
+ * Don't double it if it's already a power of two, though. \
+ */ \
+ _p_->u.mem.size = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE); \
+ if (_p_->u.mem.size < CYGMEM_REGION_ram_SIZE) \
+ _p_->u.mem.size <<= 1; \
+ _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram); \
+ _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size); \
+ _p_->hdr.size = ((sizeof(struct tag_revision)) + sizeof(struct tag_header)) / sizeof(long); \
+ _p_->hdr.tag = ATAG_REVISION; \
+ _p_->u.revision.rev = system_rev; \
+ } \
+ CYG_MACRO_END
+
+#endif // CYGONCE_HAL_ARM_BOARD_PLF_IO_H
--- /dev/null
+#ifndef CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+#define CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+//=============================================================================
+//
+// plf_mmap.h
+//
+// Platform specific memory map support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_misc.h>
+#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+
+// Get the pagesize for a particular virtual address:
+
+// This does not depend on the vaddr.
+#define HAL_MM_PAGESIZE(vaddr, pagesize) CYG_MACRO_START \
+ (pagesize) = SZ_1M; \
+CYG_MACRO_END
+
+// Get the physical address from a virtual address:
+
+#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START \
+ cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
+ if ( _v_ < SDRAM_SIZE ) /* SDRAM */ \
+ _v_ += SDRAM_BASE_ADDR; \
+ else /* Rest of it */ \
+ /* no change */ ; \
+ (paddr) = _v_; \
+CYG_MACRO_END
+
+/*
+ * translate the virtual address of ram space to physical address
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
+{
+ if(virt < (SDRAM_SIZE - 0x100000)) {
+ return (virt + SDRAM_BASE_ADDR);
+ }
+ if(virt >= 0xE0000000) {
+ return ((virt - 0xE0000000) + SDRAM_BASE_ADDR);
+ }
+ return virt;
+}
+
+/*
+ * remap the physical address of ram space to uncacheable virtual address space
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
+{
+ /* 0xE0000000~0xFFFFFFFF is uncacheable meory space which is mapped to SDRAM*/
+ if(phy >= SDRAM_BASE_ADDR && phy < (SDRAM_BASE_ADDR + SDRAM_SIZE)) {
+ phy = (phy - SDRAM_BASE_ADDR) + 0xE0000000;
+ }
+ return phy;
+}
+
+//---------------------------------------------------------------------------
+#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
--- /dev/null
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware mx51_babbage ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM current ;
+ package -hardware CYGPKG_HAL_ARM_MX51 current ;
+ package -hardware CYGPKG_HAL_ARM_MX51_BABBAGE current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_FEC current ;
+ package -hardware CYGPKG_COMPRESS_ZLIB current ;
+ package -hardware CYGPKG_IO_FLASH current ;
+ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+ package -hardware CYGPKG_DEVS_IMX_SPI current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package CYGPKG_MEMALLOC current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_IMX_SPI_NOR {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MMC {
+ inferred_value 1
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
+ user_value 50
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ inferred_value 0x00040000
+};
+
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+ inferred_value 0x90008000
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_component CYG_HAL_STARTUP {
+ user_value ROMRAM
+};
+
+cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+ inferred_value 1
+};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+ inferred_value 4
+};
+
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+ user_value 1 "FSL 200904"
+};
--- /dev/null
+/*=============================================================================
+//
+// board_diag.c
+//
+// HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_arch.h> // basic machine info
+#include <cyg/hal/hal_intr.h> // interrupt macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_if.h> // Calling-if API
+#include <cyg/hal/drv_api.h> // driver API
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/fsl_board.h> // Platform specifics
+
+extern void cyg_hal_plf_serial_init(void);
+
+void cyg_hal_plf_comms_init(void)
+{
+ static int initialized = 0;
+
+ if (initialized)
+ return;
+
+ initialized = 1;
+
+ /* Setup GPIO and enable transceiver for UARTs */
+ cyg_hal_plf_serial_init();
+}
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
+
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
+#define __BASE CMA101_DUARTA
+#define _INT CYGNUM_HAL_INTERRUPT_SERIAL_A
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1)
+#define __BASE CMA101_DUARTB
+#define _INT CYGNUM_HAL_INTERRUPT_SERIAL_B
+#endif
+
+#ifdef __BASE
+
+#ifdef CYGSEM_HAL_ROM_MONITOR
+#define CYG_HAL_STARTUP_ROM
+#define CYG_HAL_STARTUP_ROMRAM
+#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#endif
+
+#if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define HAL_DIAG_USES_HARDWARE
+#elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
+#define HAL_DIAG_USES_HARDWARE
+#elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+#define HAL_DIAG_USES_HARDWARE
+#endif
+
+static channel_data_t channel = {
+ (uart_width*) _BASE, 0, 0
+};
+
+#ifdef HAL_DIAG_USES_HARDWARE
+
+void hal_diag_init(void)
+{
+ static int init = 0;
+ char *msg = "\n\rARM eCos\n\r";
+ uart_width lcr;
+
+ if (init++) return;
+
+ init_duart_channel(&channel);
+
+ while (*msg) hal_diag_write_char(*msg++);
+}
+
+#ifdef DEBUG_DIAG
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define DIAG_BUFSIZE 32
+#else
+#define DIAG_BUFSIZE 2048
+#endif
+static char diag_buffer[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+
+void hal_diag_write_char(char c)
+{
+ uart_width lsr;
+
+ hal_diag_init();
+
+ cyg_hal_plf_duart_putc(&channel, c)
+
+#ifdef DEBUG_DIAG
+ diag_buffer[diag_bp++] = c;
+ if (diag_bp == DIAG_BUFSIZE) {
+ while (1) ;
+ diag_bp = 0;
+ }
+#endif
+}
+
+void hal_diag_read_char(char *c)
+{
+ *c = cyg_hal_plf_duart_getc(&channel);
+}
+
+#else // HAL_DIAG relies on GDB
+
+// Initialize diag port - assume GDB channel is already set up
+void hal_diag_init(void)
+{
+ if (0) init_duart_channel(&channel); // avoid warning
+}
+
+// Actually send character down the wire
+static void hal_diag_write_char_serial(char c)
+{
+ cyg_hal_plf_duart_putc(&channel, c);
+}
+
+static bool hal_diag_read_serial(char *c)
+{
+ long timeout = 1000000000; // A long time...
+
+ while (!cyg_hal_plf_duart_getc_nonblock(&channel, c))
+ if (0 == --timeout) return false;
+
+ return true;
+}
+
+void hal_diag_read_char(char *c)
+{
+ while (!hal_diag_read_serial(c)) ;
+}
+
+void hal_diag_write_char(char c)
+{
+ static char line[100];
+ static int pos = 0;
+
+ // No need to send CRs
+ if (c == '\r') return;
+
+ line[pos++] = c;
+
+ if (c == '\n' || pos == sizeof(line)) {
+ CYG_INTERRUPT_STATE old;
+
+ // Disable interrupts. This prevents GDB trying to interrupt us
+ // while we are in the middle of sending a packet. The serial
+ // receive interrupt will be seen when we re-enable interrupts
+ // later.
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+#else
+ HAL_DISABLE_INTERRUPTS(old);
+#endif
+
+ while (1) {
+ static char hex[] = "0123456789ABCDEF";
+ cyg_uint8 csum = 0;
+ int i;
+ char c1;
+
+ hal_diag_write_char_serial('$');
+ hal_diag_write_char_serial('O');
+ csum += 'O';
+ for (i = 0; i < pos; i++) {
+ char ch = line[i];
+ char h = hex[(ch>>4)&0xF];
+ char l = hex[ch&0xF];
+ hal_diag_write_char_serial(h);
+ hal_diag_write_char_serial(l);
+ csum += h;
+ csum += l;
+ }
+ hal_diag_write_char_serial('#');
+ hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
+ hal_diag_write_char_serial(hex[csum&0xF]);
+
+ // Wait for the ACK character '+' from GDB here and handle
+ // receiving a ^C instead. This is the reason for this clause
+ // being a loop.
+ if (!hal_diag_read_serial(&c1))
+ continue; // No response - try sending packet again
+
+ if ( c1 == '+' )
+ break; // a good acknowledge
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
+ if ( c1 == 3 ) {
+ // Ctrl-C: breakpoint.
+ cyg_hal_gdb_interrupt (__builtin_return_address(0));
+ break;
+ }
+#endif
+ // otherwise, loop round again
+ }
+
+ pos = 0;
+
+ // And re-enable interrupts
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+#else
+ HAL_RESTORE_INTERRUPTS(old);
+#endif
+
+ }
+}
+#endif
+
+#endif // __BASE
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
--- /dev/null
+//==========================================================================
+//
+// board_misc.c
+//
+// HAL misc board support code for the board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include <redboot.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h> // Interrupt names
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/fsl_board.h> // Platform specifics
+#include <cyg/infra/diag.h> // diag_printf
+
+// All the MM table layout is here:
+#include <cyg/hal/hal_mm.h>
+
+externC void* memset(void *, int, size_t);
+unsigned int cpld_base_addr;
+
+void hal_mmu_init(void)
+{
+ unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
+ unsigned long i;
+
+ /*
+ * Set the TTB register
+ */
+ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
+
+ /*
+ * Set the Domain Access Control Register
+ */
+ i = ARM_ACCESS_DACR_DEFAULT;
+ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+
+ /*
+ * First clear all TT entries - ie Set them to Faulting
+ */
+ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+
+ /* Actual Virtual Size Attributes Function */
+ /* Base Base MB cached? buffered? access permissions */
+ /* xxx00000 xxx00000 */
+ X_ARM_MMU_SECTION(0x000, 0x200, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */
+ X_ARM_MMU_SECTION(0x1FF, 0x1FF, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IRAM */
+ X_ARM_MMU_SECTION(0x300, 0x300, 0x100, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* GPU */
+ X_ARM_MMU_SECTION(0x400, 0x400, 0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IPUv3D */
+ X_ARM_MMU_SECTION(0x600, 0x600, 0x300, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* periperals */
+ X_ARM_MMU_SECTION(0x900, 0x000, 0x1FF, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0x900, 0x900, 0x200, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0x900, 0xE00, 0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
+ X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
+ X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */
+}
+
+static void mxc_fec_setup(void)
+{
+ volatile unsigned int reg;
+
+ /*FEC_MDIO*/
+ writel(0x3, IOMUXC_BASE_ADDR + 0x0D4);
+ writel(0x1FD, IOMUXC_BASE_ADDR + 0x0470);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x09B0);
+
+ /*FEC_RDATA1*/
+ writel(0x3, IOMUXC_BASE_ADDR + 0x0D8);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x0474);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x09B8);
+
+ /*FEC_RDATA2*/
+ writel(0x3, IOMUXC_BASE_ADDR + 0x0E8);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x0484);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x09BC);
+
+ /*FEC_RDATA3*/
+ writel(0x3, IOMUXC_BASE_ADDR + 0x0EC);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x0488);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x09C0);
+
+ /*FEC_RX_ERR*/
+ writel(0x3, IOMUXC_BASE_ADDR + 0x0F0);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x048C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x09CC);
+
+ /*FEC_CRS*/
+ writel(0x3, IOMUXC_BASE_ADDR + 0x0F4);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x0490);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x09AC);
+
+ /*FEC_COL*/
+ writel(0x1, IOMUXC_BASE_ADDR + 0x0124);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x05CC);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x9A8);
+
+ /*FEC_RX_CLK*/
+ writel(0x1, IOMUXC_BASE_ADDR + 0x0128);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x05D0);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x09C4);
+
+ /*FEC_RX_DV*/
+ writel(0x1, IOMUXC_BASE_ADDR + 0x012C);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x05D4);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x09C8);
+
+ /*FEC_RDATA0*/
+ writel(0x1, IOMUXC_BASE_ADDR + 0x0134);
+ writel(0x2180, IOMUXC_BASE_ADDR + 0x05DC);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x09B4);
+
+ /*FEC_TDATA0*/
+ writel(0x1, IOMUXC_BASE_ADDR + 0x0138);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x5E0);
+
+ /*FEC_TX_ERR*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0144);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x05EC);
+
+ /*FEC_MDC*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0148);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x05F0);
+
+ /*FEC_TDATA1*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x014C);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x05F4);
+
+ /*FEC_TDATA2*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0150);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x05F8);
+
+ /*FEC_TDATA3*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0154);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x05FC);
+
+ /*FEC_TX_EN*/
+ writel(0x1, IOMUXC_BASE_ADDR + 0x0158);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x0600);
+
+ /*FEC_TX_CLK*/
+ writel(0x1, IOMUXC_BASE_ADDR + 0x015C);
+ writel(0x2180, IOMUXC_BASE_ADDR + 0x0604);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x09D0);
+
+ reg = readl(GPIO2_BASE_ADDR + 0x0);
+ reg &= ~0x4000; // Lower reset line
+ writel(reg, GPIO2_BASE_ADDR + 0x0);
+
+ reg = readl(GPIO2_BASE_ADDR + 0x4);
+ reg |= 0x4000; // configure GPIO lines as output
+ writel(reg, GPIO2_BASE_ADDR + 0x4);
+
+ /* Reset the ethernet controller over GPIO */
+ writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
+
+ hal_delay_us(200);
+
+ reg = readl(GPIO2_BASE_ADDR + 0x0);
+ reg |= 0x4000;
+ writel(reg, GPIO2_BASE_ADDR + 0x0);
+}
+
+#include <cyg/io/imx_spi.h>
+struct spi_v2_3_reg spi_pmic_reg;
+
+struct imx_spi_dev imx_spi_pmic = {
+ base : CSPI1_BASE_ADDR,
+ freq : 25000000,
+ ss_pol : IMX_SPI_ACTIVE_HIGH,
+ ss : 0, // slave select 0
+ fifo_sz : 64 * 4,
+ reg : &spi_pmic_reg,
+};
+
+struct spi_v2_3_reg spi_nor_reg;
+
+struct imx_spi_dev imx_spi_nor = {
+ base : CSPI1_BASE_ADDR,
+ freq : 25000000,
+ ss_pol : IMX_SPI_ACTIVE_LOW,
+ ss : 1, // slave select 1
+ fifo_sz : 64 * 4,
+ us_delay: 0,
+ reg : &spi_nor_reg,
+};
+
+imx_spi_init_func_t *spi_nor_init;
+imx_spi_xfer_func_t *spi_nor_xfer;
+
+imx_spi_init_func_t *spi_pmic_init;
+imx_spi_xfer_func_t *spi_pmic_xfer;
+
+//
+// Platform specific initialization
+//
+
+void plf_hardware_init(void)
+{
+ unsigned int reg;
+
+ /* Disable IPU and HSC dividers */
+ writel(0x60000, CCM_BASE_ADDR + CLKCTL_CCDR);
+ /* Change the DDR divider to run at 166MHz on CPU 2 */
+ reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
+ reg = (reg & (~0x70000)) | 0x40000;
+ writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR);
+ /* make sure divider effective */
+ while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0);
+ writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
+
+ // UART1
+ //RXD
+ writel(0x0, IOMUXC_BASE_ADDR + 0x234);
+ writel(0x1C5, IOMUXC_BASE_ADDR + 0x6E4);
+
+ //TXD
+ writel(0x0, IOMUXC_BASE_ADDR + 0x238);
+ writel(0x1C5, IOMUXC_BASE_ADDR + 0x6E8);
+
+ //RTS
+ writel(0x0, IOMUXC_BASE_ADDR + 0x23C);
+ writel(0x1C4, IOMUXC_BASE_ADDR + 0x6EC);
+
+ //CTS
+ writel(0x0, IOMUXC_BASE_ADDR + 0x240);
+ writel(0x1C4, IOMUXC_BASE_ADDR + 0x6F0);
+
+ // enable GPIO1_9 for CLKO and GPIO1_8 for CLKO2
+ writel(0x00000004, 0x73fa83F4);
+ writel(0x00000004, 0x73fa83F0);
+ // enable ARM clock div by 8
+ writel(0x010900F0, CCM_BASE_ADDR + CLKCTL_CCOSR);
+
+ spi_nor_init = (imx_spi_init_func_t *)imx_spi_init_v2_3;
+ spi_nor_xfer = (imx_spi_xfer_func_t *)imx_spi_xfer_v2_3;
+
+ spi_pmic_init = (imx_spi_init_func_t *)imx_spi_init_v2_3;
+ spi_pmic_xfer = (imx_spi_xfer_func_t *)imx_spi_xfer_v2_3;
+}
+
+void mxc_mmc_init(unsigned int base_address)
+{
+ switch(base_address) {
+ case MMC_SDHC1_BASE_ADDR:
+ //diag_printf("Configure IOMUX of ESDHC1 on i.MX51\n");
+ /* SD1 CMD, SION bit */
+ writel(0x10, IOMUXC_BASE_ADDR + 0x39c);
+
+ /* SD1 CD, as gpio1_0 */
+ writel(0x01, IOMUXC_BASE_ADDR + 0x3b4);
+ /* Configure SW PAD */
+ /* SD1 CMD */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x868);
+ /* SD1 CLK */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x86c);
+ /* SD1 DAT0 */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x870);
+ /* SD1 DAT1 */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x874);
+ /* SD1 DAT2 */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x878);
+ /* SD1 DAT3 */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x87c);
+ /* SD1 CD as gpio1_0 */
+ writel(0x1e2, IOMUXC_BASE_ADDR + 0x880);
+ break;
+ default:
+ break;
+ }
+}
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+typedef void code_fun(void);
+
+void board_program_new_stack(void *func)
+{
+ register CYG_ADDRESS stack_ptr asm("sp");
+ register CYG_ADDRESS old_stack asm("r4");
+ register code_fun *new_func asm("r0");
+ old_stack = stack_ptr;
+ stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
+ new_func = (code_fun*)func;
+ new_func();
+ stack_ptr = old_stack;
+}
+
+void increase_core_voltage(bool i)
+{
+ unsigned int val;
+
+ val = pmic_reg(24, 0, 0);
+
+ if (i) {
+ /* Set core voltage to 1.175V */
+ val = val & (~0x1F) | 0x17;
+ } else {
+ /* Set core voltage to 1.05V */
+ val = val & (~0x1F) | 0x12;
+ }
+
+ pmic_reg(24, val, 1);
+}
+
+extern unsigned int pmic_reg(unsigned int reg, unsigned int val, unsigned int write);
+static void babbage_power_init(void)
+{
+ unsigned int val;
+
+ /* power up the system first */
+ pmic_reg(34, 0x00200000, 1);
+
+ if (pll_clock(PLL1) > 800000000) {
+ /* Set core voltage to 1.175V */
+ val = pmic_reg(24, 0, 0);
+ val = val & (~0x1F) | 0x17;
+ pmic_reg(24, val, 1);
+ }
+
+ /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */
+ val = pmic_reg(30, 0, 0);
+ val &= ~0x34030;
+ val |= 0x10020;
+ pmic_reg(30, val, 1);
+
+ /* Set VVIDEO to 2.775V, VAUDIO to 2.775V, VSD to 3.15V */
+ val = pmic_reg(31, 0, 0);
+ val &= ~0x1FC;
+ val |= 0x1F4;
+ pmic_reg(31, val, 1);
+
+ /* Configure VGEN3 and VCAM regulators to use external PNP */
+ val = 0x208;
+ pmic_reg(33, val, 1);
+ hal_delay_us(200);
+
+ /* Enable VGEN1 regulator */
+ val = pmic_reg(32, val, 0);
+ val |= 0x1;
+ pmic_reg(32, val, 1);
+
+ /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
+ val = 0x49249;
+ pmic_reg(33, val, 1);
+
+ hal_delay_us(200);
+
+ /* Setup the FEC after enabling the regulators */
+ mxc_fec_setup();
+}
+
+RedBoot_init(babbage_power_init, RedBoot_INIT_PRIO(900));
+
+void io_cfg_spi(struct imx_spi_dev *dev)
+{
+ switch (dev->base) {
+ case CSPI1_BASE_ADDR:
+ // 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1
+ writel(0x0, IOMUXC_BASE_ADDR + 0x21C);
+ writel(0x105, IOMUXC_BASE_ADDR + 0x6CC);
+
+ // 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1.
+ writel(0x0, IOMUXC_BASE_ADDR + 0x220);
+ writel(0x105, IOMUXC_BASE_ADDR + 0x6D0);
+ if (dev->ss == 0) {
+ // de-select SS1 of instance: ecspi1.
+ writel(0x3, IOMUXC_BASE_ADDR + 0x228);
+ writel(0x85, IOMUXC_BASE_ADDR + 0x6D8);
+ // 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1.
+ writel(0x0, IOMUXC_BASE_ADDR + 0x224);
+ writel(0x185, IOMUXC_BASE_ADDR + 0x6D4);
+ } else if (dev->ss == 1) {
+ // de-select SS0 of instance: ecspi1.
+ writel(0x3, IOMUXC_BASE_ADDR + 0x224);
+ writel(0x85, IOMUXC_BASE_ADDR + 0x6D4);
+ // 000: Select mux mode: ALT0 mux port: SS1 of instance: ecspi1.
+ writel(0x0, IOMUXC_BASE_ADDR + 0x228);
+ writel(0x105, IOMUXC_BASE_ADDR + 0x6D8);
+ }
+ // 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1.
+ writel(0x0, IOMUXC_BASE_ADDR + 0x22C);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x6DC);
+
+ // 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1.
+ writel(0x0, IOMUXC_BASE_ADDR + 0x230);
+ writel(0x105, IOMUXC_BASE_ADDR + 0x6E0);
+ break;
+ case CSPI2_BASE_ADDR:
+ default:
+ break;
+ }
+}
--- /dev/null
+//==========================================================================
+//
+// redboot_cmds.c
+//
+// Board [platform] specific RedBoot commands
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+#include <redboot.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/plf_mmap.h>
+#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <flash_config.h>
+
+#if (REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE)
+#error REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE
+#endif
+
+RedBoot_config_option("Board specifics",
+ brd_specs,
+ ALWAYS_ENABLED,
+ true,
+ CONFIG_INT,
+ 0
+ );
+#endif //CYGSEM_REDBOOT_FLASH_CONFIG
+
+char HAL_PLATFORM_EXTRA[20] = "PASS x.x [x32 DDR]";
+
+static void runImg(int argc, char *argv[]);
+
+RedBoot_cmd("run",
+ "Run an image at a location with MMU off",
+ "[<virtual addr>]",
+ runImg
+ );
+
+void launchRunImg(unsigned long addr)
+{
+ asm volatile ("mov r12, r0;");
+ HAL_CACHE_FLUSH_ALL();
+ HAL_DISABLE_L2();
+ HAL_MMU_OFF();
+ asm volatile (
+ "mov r0, #0;"
+ "mov r1, r12;"
+ "mov r11, #0;"
+ "mov r12, #0;"
+ "mrs r10, cpsr;"
+ "bic r10, r10, #0xF0000000;"
+ "msr cpsr_f, r10;"
+ "mov pc, r1"
+ );
+}
+
+extern unsigned long entry_address;
+
+static void runImg(int argc,char *argv[])
+{
+ unsigned int virt_addr, phys_addr;
+
+ // Default physical entry point for Symbian
+ if (entry_address == 0xFFFFFFFF)
+ virt_addr = 0x800000;
+ else
+ virt_addr = entry_address;
+
+ if (!scan_opts(argc,argv,1,0,0,(void*)&virt_addr,
+ OPTION_ARG_TYPE_NUM, "virtual address"))
+ return;
+
+ if (entry_address != 0xFFFFFFFF)
+ diag_printf("load entry_address=0x%lx\n", entry_address);
+ HAL_VIRT_TO_PHYS_ADDRESS(virt_addr, phys_addr);
+
+ diag_printf("virt_addr=0x%x\n",virt_addr);
+ diag_printf("phys_addr=0x%x\n",phys_addr);
+
+ launchRunImg(phys_addr);
+}
+
+#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYG_HAL_STARTUP_ROMRAM)
+
+RedBoot_cmd("romupdate",
+ "Update Redboot with currently running image",
+ "",
+ romupdate
+ );
+
+extern int flash_program(void *_addr, void *_data, int len, void **err_addr);
+extern int flash_erase(void *addr, int len, void **err_addr);
+extern char *flash_errmsg(int err);
+extern unsigned char *ram_end; //ram end is where the redboot starts FIXME: use PC value
+extern cyg_uint32 mmc_data_read (cyg_uint32 *,cyg_uint32 ,cyg_uint32);
+extern int spi_nor_erase_block(void* block_addr, unsigned int block_size);
+extern int spi_nor_program_buf(void *addr, void *data, int len);
+
+#ifdef CYGPKG_IO_FLASH
+void romupdate(int argc, char *argv[])
+{
+ void *err_addr, *base_addr;
+ int stat;
+ unsigned int nfc_config3_reg, temp;
+
+ if (IS_FIS_FROM_MMC() || IS_BOOTING_FROM_MMC()) {
+ diag_printf("Updating ROM in MMC/SD flash\n");
+ base_addr = (void*)0;
+ /* Read the first 1K from the card */
+ mmc_data_read((cyg_uint32*)(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000),
+ 0x400, base_addr);
+ diag_printf("Programming Redboot to MMC/SD flash\n");
+ mmc_data_write((cyg_uint32*)(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000),
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE, (cyg_uint32)base_addr);
+ return;
+ } else if (IS_BOOTING_FROM_SPI_NOR() || IS_FIS_FROM_SPI_NOR()) {
+ diag_printf("Updating ROM in SPI-NOR flash\n");
+ base_addr = (void*)0;
+ } else {
+ diag_printf("romupdate not supported\n");
+ diag_printf("Use \"factive [SPI|MMC]\" to select either NAND or MMC flash\n");
+ }
+
+ // Erase area to be programmed
+ if ((stat = flash_erase((void *)base_addr,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ (void **)&err_addr)) != 0) {
+ diag_printf("Can't erase region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ return;
+ }
+ // Now program it
+ if ((stat = flash_program((void *)base_addr,
+ (void *)SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ (void **)&err_addr)) != 0) {
+ diag_printf("Can't program region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ }
+}
+RedBoot_cmd("factive",
+ "Enable one flash media for Redboot",
+ "[MMC|SPI]",
+ factive
+ );
+
+typedef void reset_func_t(void);
+
+extern reset_func_t reset_vector;
+
+void factive(int argc, char *argv[])
+{
+ unsigned long phys_addr;
+ unsigned int *fis_addr = IRAM_BASE_ADDR;
+
+ if (argc != 2) {
+ diag_printf("Invalid factive cmd\n");
+ return;
+ }
+
+ if (strcasecmp(argv[1], "MMC") == 0) {
+ *fis_addr = FROM_MMC_FLASH;
+ } else if (strcasecmp(argv[1], "SPI") == 0) {
+ *fis_addr = FROM_SPI_NOR_FLASH;
+ }
+ else {
+ diag_printf("Invalid command: %s\n", argv[1]);
+ return;
+ }
+
+ //HAL_VIRT_TO_PHYS_ADDRESS(ram_end, phys_addr);
+ launchRunImg(reset_vector);
+}
+#endif //CYGPKG_IO_FLASH
+
+#define POST_SDRAM_START_OFFSET 0x800000
+#define POST_MMC_OFFSET 0x100000
+#define POST_SIZE 0x100000
+#define POST_MAGIC_MARKER 0x43
+
+
+void imx_launch_post(void)
+{
+ mmc_data_read(0x100000, // ram location
+ 0x40000, // length
+ 0x100000); // from MMC/SD offset 0x100000
+ spi_nor_erase_block(0, 0x10000);
+ spi_nor_erase_block(0x10000, 0x10000);
+ spi_nor_erase_block(0x20000, 0x10000);
+ spi_nor_erase_block(0x30000, 0x10000);
+ // save the redboot to SPI-NOR
+ spi_nor_program_buf(0, 0x100000, 0x40000);
+
+ diag_printf("Reading POST from MMC to SDRAM...\n");
+ mmc_data_read(SDRAM_BASE_ADDR + POST_SDRAM_START_OFFSET, // ram location
+ 0x200000, // length
+ 0x200000); // from MMC offset
+ diag_printf("Launching POST\n");
+ launchRunImg(SDRAM_BASE_ADDR + POST_SDRAM_START_OFFSET);
+}
+//RedBoot_init(imx_launch_post, RedBoot_INIT_BEFORE_NET);
+
+#endif /* CYG_HAL_STARTUP_ROMRAM */
--- /dev/null
+# ====================================================================
+#
+# hal_arm_board.cdl
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+
+cdl_package CYGPKG_HAL_ARM_MX51_ROCKY {
+ display "Freescale board"
+ parent CYGPKG_HAL_ARM_MX51
+ hardware
+ include_dir cyg/hal
+ define_header hal_arm_board.h
+ description "
+ This HAL platform package provides generic
+ support for the Freescale MX51 Rocky Board."
+
+ compile board_misc.c board_diag.c
+ implements CYGINT_HAL_DEBUG_GDB_STUBS
+ implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+ implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+
+ #implements CYGHWR_HAL_ARM_DUART_UARTB
+ implements CYGHWR_HAL_ARM_SOC_UART1
+ #implements CYGHWR_HAL_ARM_SOC_UART2
+ #implements CYGHWR_HAL_ARM_SOC_UART3
+
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_soc.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_board.h>"
+ puts $::cdl_header "#define HAL_PLATFORM_CPU \"Freescale i.MX51 based\""
+ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"MX51 Rocky\""
+ puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 2001"
+ puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK board_program_new_stack"
+ }
+
+ cdl_component CYG_HAL_STARTUP {
+ display "Startup type"
+ flavor data
+ default_value {"ROM"}
+ legal_values {"RAM" "ROM" "ROMRAM"}
+ no_define
+ define -file system.h CYG_HAL_STARTUP
+ description "
+ When targetting the eval board it is possible to build
+ the system for either RAM bootstrap or ROM bootstrap(s). Select
+ 'ram' when building programs to load into RAM using eCos GDB
+ stubs. Select 'rom' when building a stand-alone application
+ which will be put into ROM, or for the special case of
+ building the eCos GDB stubs themselves. Using ROMRAM will allow
+ the program to exist in ROM, but be copied to RAM during startup."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_DUART_UARTA {
+ display "ST16552 UARTA available as diagnostic/debug channel"
+ description "
+ The board has a ST16552 DUART chip. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_DUART_UARTB {
+ display "ST16552 UARTB available as diagnostic/debug channel"
+ description "
+ The board has a ST16552 DUART chip. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ display "Diagnostic serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the console port.
+ Note: this should match the value chosen for the GDB port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ display "GDB serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the GDB port.
+ Note: this should match the value chosen for the console port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the board"
+ flavor data
+ calculated 6
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ The board has three serial ports. This option
+ chooses which port will be used to connect to a host
+ running GDB."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+ display "Default console channel."
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ calculated 0
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Console serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ description "
+ The board has only three serial ports. This option
+ chooses which port will be used for console output."
+ }
+
+ cdl_component CYGBLD_GLOBAL_OPTIONS {
+ display "Global build options"
+ flavor none
+ no_define
+ description "
+ Global build options including control over
+ compiler flags, linker flags and choice of toolchain."
+
+
+ parent CYGPKG_NONE
+
+ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ display "Global command prefix"
+ flavor data
+ no_define
+ default_value { "arm-none-eabi" }
+ description "
+ This option specifies the command prefix used when
+ invoking the build tools."
+ }
+
+ cdl_option CYGBLD_GLOBAL_CFLAGS {
+ display "Global compiler flags"
+ flavor data
+ no_define
+ default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ description "
+ This option controls the global compiler flags which are used to
+ compile all packages by default. Individual packages may define
+ options which override these global flags."
+ }
+
+ cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ display "Global linker flags"
+ flavor data
+ no_define
+ default_value { "-Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" }
+ description "
+ This option controls the global linker flags. Individual
+ packages may define options which override these global flags."
+ }
+
+ cdl_option CYGBLD_BUILD_GDB_STUBS {
+ display "Build GDB stub ROM image"
+ default_value 0
+ requires { CYG_HAL_STARTUP == "ROM" }
+ requires CYGSEM_HAL_ROM_MONITOR
+ requires CYGBLD_BUILD_COMMON_GDB_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ no_define
+ description "
+ This option enables the building of the GDB stubs for the
+ board. The common HAL controls takes care of most of the
+ build process, but the final conversion from ELF image to
+ binary data is handled by the platform CDL, allowing
+ relocation of the data if necessary."
+
+ make -priority 320 {
+ <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
+ $(OBJCOPY) --remove-section=.fixed_vectors -O binary $< $@
+ }
+ }
+ }
+
+ cdl_component CYGPKG_HAL_ARM_BOARD_OPTIONS {
+ display "Freescale MXC Board build options"
+ flavor none
+ no_define
+ description "
+ Package specific build options including control over
+ compiler flags used only in building this package,
+ and details of which tests are built."
+
+ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the board HAL. These flags are used in addition
+ to the set of global flags."
+ }
+
+ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_REMOVE {
+ display "Suppressed compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the board HAL. These flags are removed from
+ the set of global flags if present."
+ }
+
+ }
+
+ cdl_component CYGHWR_MEMORY_LAYOUT {
+ display "Memory layout"
+ flavor data
+ no_define
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_board_ram" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" :
+ "arm_board_rom" }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ display "Memory layout linker script fragment"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.ldi>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.ldi>" :
+ "<pkgconf/mlt_arm_board_rom.ldi>" }
+ }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ display "Memory layout header file"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_H
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.h>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.h>" :
+ "<pkgconf/mlt_arm_board_rom.h>" }
+ }
+ }
+
+ cdl_option CYGSEM_HAL_ROM_MONITOR {
+ display "Behave as a ROM monitor"
+ flavor bool
+ default_value 0
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+ description "
+ Enable this option if this program is to be used as a ROM monitor,
+ i.e. applications will be loaded into RAM on the board, and this
+ ROM monitor may process exceptions or interrupts generated from the
+ application. This enables features such as utilizing a separate
+ interrupt stack when exceptions are generated."
+ }
+
+ cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ display "Work with a ROM monitor"
+ flavor booldata
+ legal_values { "Generic" "GDB_stubs" }
+ default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "RAM" }
+ description "
+ Support can be enabled for different varieties of ROM monitor.
+ This support changes various eCos semantics such as the encoding
+ of diagnostic output, or the overriding of hardware interrupt
+ vectors.
+ Firstly there is \"Generic\" support which prevents the HAL
+ from overriding the hardware vectors that it does not use, to
+ instead allow an installed ROM monitor to handle them. This is
+ the most basic support which is likely to be common to most
+ implementations of ROM monitor.
+ \"GDB_stubs\" provides support when GDB stubs are included in
+ the ROM monitor or boot ROM."
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ display "Redboot HAL options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+ description "
+ This option lists the target's requirements for a valid Redboot
+ configuration."
+
+ compile -library=libextras.a redboot_cmds.c
+
+ cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ display "Build Redboot ROM binary image"
+ active_if CYGBLD_BUILD_REDBOOT
+ default_value 1
+ no_define
+ description "This option enables the conversion of the Redboot ELF
+ image to a binary image suitable for ROM programming."
+
+ make -priority 325 {
+ <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+ $(OBJCOPY) -O binary $< $@
+ }
+ }
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_BOARD_OPTIONS {
+ display "Redboot HAL variant options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+
+ # RedBoot details
+ requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x90008000 }
+ define_proc {
+ puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00"
+ }
+ }
+}
--- /dev/null
+#ifndef CYGONCE_FSL_BOARD_H
+#define CYGONCE_FSL_BOARD_H
+
+//=============================================================================
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+
+#define BOARD_CS_UART_BASE (0x8000)
+
+#define REDBOOT_IMAGE_SIZE 0x40000
+
+#define PMIC_SPI_BASE CSPI1_BASE_ADDR
+#define PMIC_SPI_CHIP_SELECT_NO SPI_CTRL_CS0
+#define PMIC_SPI_SS_POL SPI_CFG_SS0_POL_HIGH
+
+#define PBC_BASE CS0_BASE_ADDR
+
+/* MX51 3-Stack SDRAM is from 0x40000000, 128M */
+#define SDRAM_BASE_ADDR CSD0_BASE_ADDR
+#define SDRAM_SIZE 0x20000000
+#define RAM_BANK0_BASE SDRAM_BASE_ADDR
+
+#endif /* CYGONCE_FSL_BOARD_H */
--- /dev/null
+#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
+#define CYGONCE_HAL_PLATFORM_SETUP_H
+
+//=============================================================================
+//
+// hal_platform_setup.h
+//
+// Platform specific support for HAL (assembly code)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <pkgconf/system.h> // System-wide configuration info
+#include CYGBLD_HAL_VARIANT_H // Variant specific configuration
+#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
+#include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
+#include <cyg/hal/hal_mmu.h> // MMU definitions
+#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1 _platform_setup1
+#define CYGHWR_HAL_ARM_HAS_MMU
+
+#ifdef CYG_HAL_STARTUP_ROMRAM
+#define CYGSEM_HAL_ROM_RESET_USES_JUMP
+#endif
+
+//#define NFC_2K_BI_SWAP
+#define SDRAM_FULL_PAGE_BIT 0x100
+#define SDRAM_FULL_PAGE_MODE 0x37
+#define SDRAM_BURST_MODE 0x33
+
+#define CYGHWR_HAL_ROM_VADDR 0x0
+
+#if 0
+#define UNALIGNED_ACCESS_ENABLE
+#define SET_T_BIT_DISABLE
+#define BRANCH_PREDICTION_ENABLE
+#endif
+
+#define DCDGEN(i,type, addr, data) \
+dcd_##i: ;\
+ .long type ;\
+ .long addr ;\
+ .long data
+
+#define PLATFORM_PREAMBLE flash_header
+//flash header & DCD @ 0x400
+.macro flash_header
+ b reset_vector
+ .org 0x400
+app_code_jump_v: .long reset_vector
+app_code_barker: .long 0xB1
+app_code_csf: .long 0
+dcd_ptr_ptr: .long dcd_ptr
+super_root_key: .long 0
+dcd_ptr: .long dcd_data
+app_dest_ptr: .long 0xAFF00000
+
+dcd_data: .long 0xB17219E9 // Fixed. can't change.
+dcd_len: .long (20*12)
+
+//DCD
+ // ldr r0, ESDCTL_BASE_W
+ // /* Set CSD0 */
+ // ldr r1, =0x80000000
+ // str r1, [r0, #ESDCTL_ESDCTL0]
+DCDGEN(1, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x80000000)
+ // /* Precharge command */
+ // ldr r1, SDRAM_0x04008008
+ // str r1, [r0, #ESDCTL_ESDSCR]
+DCDGEN(2, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+ // /* 2 refresh commands */
+ // ldr r1, SDRAM_0x00008010
+ // str r1, [r0, #ESDCTL_ESDSCR]
+DCDGEN(3, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+ // str r1, [r0, #ESDCTL_ESDSCR]
+DCDGEN(4, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+ // /* LMR with CAS=3 and BL=3 */
+ // ldr r1, SDRAM_0x00338018
+ // str r1, [r0, #ESDCTL_ESDSCR]
+DCDGEN(5, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00338018)
+ // /* 14 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
+ // ldr r1, SDRAM_0xB2220000
+ // str r1, [r0, #ESDCTL_ESDCTL0]
+DCDGEN(6, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xC3220000)
+ // /* Timing parameters */
+ // ldr r1, SDRAM_0xB02567A9
+ // str r1, [r0, #ESDCTL_ESDCFG0]
+DCDGEN(7, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0xB08567A9)
+ // /* MDDR enable, RLAT=2 */
+ // ldr r1, SDRAM_0x000A0104
+ // str r1, [r0, #ESDCTL_ESDMISC]
+DCDGEN(8, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000A0104)
+ // /* Normal mode */
+ // ldr r1, =0x00000000
+ // str r1, [r0, #ESDCTL_ESDSCR]
+DCDGEN(9, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0)
+
+//////////////////// csd1 //////////////////
+DCDGEN(10, 4, 0x83fd9008, 0x80000000)
+ //Precharge command
+ //setmem /32 0x83fd9014 = 0x0400800C // [MK]
+DCDGEN(11, 4, 0x83fd9014, 0x0400800C)
+ //2 Refresh commands
+ //setmem /32 0x83fd9014 = 0x00008014 // [MK]
+DCDGEN(12, 4, 0x83fd9014, 0x00008014)
+ //setmem /32 0x83fd9014 = 0x00008014 // [MK]
+DCDGEN(13, 4, 0x83fd9014, 0x00008014)
+ //LMR with CAS=3 and BL=3
+ //setmem /32 0x83fd9014 = 0x0033801C // [MK]
+DCDGEN(14, 4, 0x83fd9014, 0x0033801C)
+ //14 ROW, 10 COL, 32Bit, SREF=8 Micron Model
+ //setmem /32 0x83fd9008 = 0xC3220000
+DCDGEN(15, 4, 0x83fd9008, 0xC3220000)
+ //Timing parameters
+ //setmem /32 0x83fd900C = 0xB08567A9
+DCDGEN(16, 4, 0x83fd900C, 0xB08567A9)
+ //MDDR enable, RLAT=2
+ //setmem /32 0x83fd9010 = 0x000a0104
+DCDGEN(17, 4, 0x83fd9010, 0x000a0104)
+ //Normal mode
+ //setmem /32 0x83fd9014 = 0x00000004 // [DB]
+DCDGEN(18, 4, 0x83fd9014, 0x00000004)
+ //setmem /32 0x90000000 = 0x00000000
+DCDGEN(19, 4, 0x90000000, 0x00000000)
+ //setmem /32 0xA0000000 = 0x00000000
+DCDGEN(20, 4, 0xA0000000, 0x00000000)
+
+image_len: .long 256*1024
+
+.endm
+
+//#define ENABLE_IMPRECISE_ABORT
+
+// This macro represents the initial startup code for the platform
+ .macro _platform_setup1
+FSL_BOARD_SETUP_START:
+ // mrc p15, 0, r0, c1, c1, 0 // Read Secure Configuration Register data. Why doesn't work???
+ // mcr p15, 0, <Rd>, c1, c1, 0 ; Write Secure Configuration Register data
+#ifdef ENABLE_IMPRECISE_ABORT
+ mrs r1, spsr // save old spsr
+ mrs r0, cpsr // read out the cpsr
+ bic r0, r0, #0x100 // clear the A bit
+ msr spsr, r0 // update spsr
+ add lr, pc, #0x8 // update lr
+ movs pc, lr // update cpsr
+ nop
+ nop
+ nop
+ nop
+ msr spsr, r1 // restore old spsr
+#endif
+ // explicitly disable L2 cache
+ mrc 15, 0, r0, c1, c0, 1
+ bic r0, r0, #0x2
+ mcr 15, 0, r0, c1, c0, 1
+
+ // reconfigure L2 cache aux control reg
+ mov r0, #0xC0 // tag RAM
+ add r0, r0, #0x4 // data RAM
+ orr r0, r0, #(1 << 25) // disable write combine
+ orr r0, r0, #(1 << 24) // disable write allocate delay
+ orr r0, r0, #(1 << 23) // disable write allocate combine
+ orr r0, r0, #(1 << 22) // disable write allocate
+
+ mcr 15, 1, r0, c9, c0, 2
+
+init_spba_start:
+ init_spba
+init_aips_start:
+ init_aips
+init_max_start:
+ init_max
+init_m4if_start:
+ init_m4if
+init_iomux_start:
+// init_iomux
+
+ // disable wdog
+ ldr r0, =0x30
+ ldr r1, WDOG1_BASE_W
+ strh r0, [r1]
+
+init_clock_start:
+ init_clock
+
+#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
+ /* Copy image from flash to SDRAM first */
+ ldr r0, =0xFFFFF000
+ and r0, r0, pc
+ ldr r1, MXC_REDBOOT_ROM_START
+ cmp r0, r1
+ beq HWInitialise_skip_SDRAM_copy
+
+ add r2, r0, #REDBOOT_IMAGE_SIZE
+
+1: ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ ble 1b
+ /* Jump to SDRAM */
+ ldr r1, =0xFFFF
+ and r0, pc, r1 /* offset of pc */
+ ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
+ add pc, r0, r1
+ nop
+ nop
+ nop
+ nop
+#endif /* CYG_HAL_STARTUP_ROMRAM */
+
+HWInitialise_skip_SDRAM_copy:
+
+init_cs1_start:
+// init_cs1 -- moved to plf_hardware_init()
+
+/*
+ * Note:
+ * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
+ */
+STACK_Setup:
+ // Set up a stack [for calling C code]
+ ldr r1, =__startup_stack
+ ldr r2, =RAM_BANK0_BASE
+ orr sp, r1, r2
+
+ // Create MMU tables
+ bl hal_mmu_init
+
+ // Enable MMU
+ ldr r2, =10f
+ ldr r0, =ROM_BASE_ADDRESS
+ ldr r3, [r0, #ROM_SI_REV_OFFSET]
+ cmp r3, #0x1
+ bne skip_L1_workaround
+ // Workaround for L1 cache issue
+ mrc MMU_CP, 0, r1, c10, c2, 1 // Read normal memory remap register
+ bic r1, r1, #(3 << 14) // Remap inner attribute for TEX[0],C,B = b111 as noncacheable
+ bic r1, r1, #(3 << 6) // Remap inner attribute for TEX[0],C,B = b011 as noncacheable
+ bic r1, r1, #(3 << 4) // Remap inner attribute for TEX[0],C,B = b010 as noncacheable
+ mcr MMU_CP, 0, r1, c10, c2, 1 // Write normal memory remap register
+skip_L1_workaround:
+ mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
+ orr r1, r1, #7 // enable MMU bit
+ orr r1, r1, #0x800 // enable z bit
+ orrne r1, r1, #(1 << 28) // Enable TEX remap, workaround for L1 cache issue
+ mcr MMU_CP, 0, r1, MMU_Control, c0
+ mov pc,r2 /* Change address spaces */
+ nop
+ nop
+ nop
+10:
+
+ // Save shadow copy of BCR, also hardware configuration
+ ldr r1, =_board_BCR
+ str r2, [r1]
+ ldr r1, =_board_CFG
+ str r9, [r1] // Saved far above...
+
+ .endm // _platform_setup1
+
+#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1
+#endif
+
+ /* Do nothing */
+ .macro init_spba
+ .endm /* init_spba */
+
+ /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
+ .macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, AIPS1_CTRL_BASE_ADDR_W
+ ldr r1, AIPS1_PARAM_W
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ ldr r0, AIPS2_CTRL_BASE_ADDR_W
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+
+ .endm /* init_aips */
+
+ /* MAX (Multi-Layer AHB Crossbar Switch) setup */
+ .macro init_max
+ .endm /* init_max */
+
+ .macro init_clock
+ ldr r0, CCM_BASE_ADDR_W
+ /* Disable IPU and HSC dividers */
+ mov r1, #0x60000
+ str r1, [r0, #CLKCTL_CCDR]
+
+ /* Switch ARM to step clock */
+ mov r1, #0x4
+ str r1, [r0, #CLKCTL_CCSR]
+ setup_pll PLL1, 800
+
+ /* Switch peripheral to PLL 3 */
+ ldr r0, CCM_BASE_ADDR_W
+ ldr r1, CCM_VAL_0x0000D3C0
+ str r1, [r0, #CLKCTL_CBCMR]
+ ldr r1, CCM_VAL_0x033B9145
+ str r1, [r0, #CLKCTL_CBCDR]
+ setup_pll PLL2, 665
+ /* Switch peripheral to PLL 2 */
+ ldr r0, CCM_BASE_ADDR_W
+ ldr r1, CCM_VAL_0x013B9145
+ str r1, [r0, #CLKCTL_CBCDR]
+ ldr r1, CCM_VAL_0x0000E3C0
+ str r1, [r0, #CLKCTL_CBCMR]
+
+ setup_pll PLL3, 216
+
+ /* Set the platform clock dividers */
+ ldr r0, PLATFORM_BASE_ADDR_W
+ ldr r1, PLATFORM_CLOCK_DIV_W
+ str r1, [r0, #PLATFORM_ICGC]
+
+ /* Switch ARM back to PLL 1. */
+ ldr r0, CCM_BASE_ADDR_W
+ mov r1, #0x0
+ str r1, [r0, #CLKCTL_CCSR]
+
+ /* setup the rest */
+ mov r1, #0
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Use lp_apm (24MHz) source for perclk */
+ ldr r1, CCM_VAL_0x0000E3C2
+ str r1, [r0, #CLKCTL_CBCMR]
+ // emi=ahb, all perclk dividers are 1 since using 24MHz
+ // DDR divider=6 to have 665/6=110MHz
+ ldr r1, CCM_VAL_0x013D9100
+ str r1, [r0, #CLKCTL_CBCDR]
+
+ /* Use PLL 2 for UART's, get 66.5MHz from it */
+ ldr r1, CCM_VAL_0xA5A2A020
+ str r1, [r0, #CLKCTL_CSCMR1]
+ ldr r1, CCM_VAL_0x00C30321
+ str r1, [r0, #CLKCTL_CSCDR1]
+
+ /* make sure divider effective */
+ 1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ mov r1, #0x00000
+ str r1, [r0, #CLKCTL_CCDR]
+
+ // for cko - for ARM div by 8
+ mov r1, #0x000A0000
+ add r1, r1, #0x00000F0
+ str r1, [r0, #CLKCTL_CCOSR]
+ .endm /* init_clock */
+
+ .macro setup_pll pll_nr, mhz
+ ldr r0, BASE_ADDR_W_\pll_nr
+ ldr r1, PLL_VAL_0x1232
+ str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
+ ldr r1, =0x2
+ str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+
+ ldr r1, W_DP_OP_\mhz
+ str r1, [r0, #PLL_DP_OP]
+ str r1, [r0, #PLL_DP_HFS_OP]
+
+ ldr r1, W_DP_MFD_\mhz
+ str r1, [r0, #PLL_DP_MFD]
+ str r1, [r0, #PLL_DP_HFS_MFD]
+
+ ldr r1, W_DP_MFN_\mhz
+ str r1, [r0, #PLL_DP_MFN]
+ str r1, [r0, #PLL_DP_HFS_MFN]
+
+ /* Now restart PLL */
+ ldr r1, PLL_VAL_0x1232
+ str r1, [r0, #PLL_DP_CTL]
+wait_pll_lock\pll_nr:
+ ldr r1, [r0, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+ beq wait_pll_lock\pll_nr
+ .endm
+
+ /* M4IF setup */
+ .macro init_m4if
+ /* Configure M4IF registers, VPU and IPU given higher priority (=0x4)
+ IPU accesses with ID=0x1 given highest priority (=0xA) */
+ ldr r1, M4IF_BASE_W
+ ldr r0, M4IF_0x00000a01
+ str r0, [r1, #M4IF_FIDBP]
+
+ ldr r0, M4IF_0x00000404
+ str r0, [r1, #M4IF_FBPM0]
+ .endm /* init_m4if */
+
+ .macro init_iomux
+ // do nothing
+ .endm /* init_iomux */
+
+#define PLATFORM_VECTORS _platform_vectors
+ .macro _platform_vectors
+ .globl _board_BCR, _board_CFG
+_board_BCR: .long 0 // Board Control register shadow
+_board_CFG: .long 0 // Board Configuration (read at RESET)
+ .endm
+
+WDOG1_BASE_W: .word WDOG1_BASE_ADDR
+IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
+AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
+AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
+AIPS1_PARAM_W: .word 0x77777777
+MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
+MAX_PARAM1: .word 0x00302154
+ESDCTL_BASE_W: .word ESDCTL_BASE_ADDR
+M4IF_BASE_W: .word M4IF_BASE_ADDR
+M4IF_0x00000a01: .word 0x00000a01
+M4IF_0x00000404: .word 0x00000404
+NFC_BASE_W: .word NFC_BASE_ADDR_AXI
+NFC_IP_BASE_W: .word NFC_IP_BASE
+IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
+MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
+CONST_0x0FFF: .word 0x0FFF
+CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
+CCM_VAL_0x0000E3C2: .word 0x0000E3C2
+CCM_VAL_0x013D9100: .word 0x013D9100
+CCM_VAL_0xA5A2A020: .word 0xA5A2A020
+CCM_VAL_0x00C30321: .word 0x00C30321
+CCM_VAL_0x0000D3C0: .word 0x0000D3C0
+CCM_VAL_0x033B9145: .word 0x033B9145
+CCM_VAL_0x013B9145: .word 0x013B9145
+CCM_VAL_0x0000E3C0: .word 0x0000E3C0
+PLL_VAL_0x222: .word 0x222
+PLL_VAL_0x232: .word 0x232
+BASE_ADDR_W_PLL1: .word PLL1_BASE_ADDR
+BASE_ADDR_W_PLL2: .word PLL2_BASE_ADDR
+BASE_ADDR_W_PLL3: .word PLL3_BASE_ADDR
+PLL_VAL_0x1232: .word 0x1232
+W_DP_OP_850: .word DP_OP_850
+W_DP_MFD_850: .word DP_MFD_850
+W_DP_MFN_850: .word DP_MFN_850
+W_DP_OP_800: .word DP_OP_800
+W_DP_MFD_800: .word DP_MFD_800
+W_DP_MFN_800: .word DP_MFN_800
+W_DP_OP_700: .word DP_OP_700
+W_DP_MFD_700: .word DP_MFD_700
+W_DP_MFN_700: .word DP_MFN_700
+W_DP_OP_400: .word DP_OP_400
+W_DP_MFD_400: .word DP_MFD_400
+W_DP_MFN_400: .word DP_MFN_400
+W_DP_OP_532: .word DP_OP_532
+W_DP_MFD_532: .word DP_MFD_532
+W_DP_MFN_532: .word DP_MFN_532
+W_DP_OP_665: .word DP_OP_665
+W_DP_MFD_665: .word DP_MFD_665
+W_DP_MFN_665: .word DP_MFN_665
+W_DP_OP_216: .word DP_OP_216
+W_DP_MFD_216: .word DP_MFD_216
+W_DP_MFN_216: .word DP_MFN_216
+PLATFORM_BASE_ADDR_W: .word PLATFORM_BASE_ADDR
+PLATFORM_CLOCK_DIV_W: .word 0x00000725
+_nand_pg_sz: .word 0
+
+/*---------------------------------------------------------------------------*/
+/* end of hal_platform_setup.h */
+#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x00000000)
+#define CYGMEM_REGION_ram_SIZE (0x1FF00000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0xAFF00000)
+#define CYGMEM_REGION_rom_SIZE (0x100000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ ram : ORIGIN = 0, LENGTH = 0x1FF00000
+ rom : ORIGIN = 0xAFF00000, LENGTH = 0x100000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_rom_vectors (rom, 0xAFF00000, LMA_EQ_VMA)
+ SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
+ SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table))
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
--- /dev/null
+version 0
+region ram 0 1FF00000 0 !
+region rom AFF00000 100000 1 !
+section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
+section data 0 1 1 1 1 1 0 0 8000 bss !
+section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
+section heap1 0 8 0 0 0 0 0 0 !
+section rom_vectors 0 1 0 1 1 1 1 1 AFF00000 AFF00000 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata rodata !
+section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 4 0 1 0 0 0 1 data !
--- /dev/null
+#ifndef CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+#define CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+
+//=============================================================================
+//
+// plf_io.h
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/hal/fsl_board.h>
+#include <cyg/hal/hal_soc.h>
+
+#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \
+ CYG_MACRO_START \
+ { \
+ extern unsigned int system_rev; \
+ /* Next ATAG_MEM. */ \
+ _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header)) / sizeof(long); \
+ _p_->hdr.tag = ATAG_MEM; \
+ /* Round up so there's only one bit set in the memory size. \
+ * Don't double it if it's already a power of two, though. \
+ */ \
+ _p_->u.mem.size = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE); \
+ if (_p_->u.mem.size < CYGMEM_REGION_ram_SIZE) \
+ _p_->u.mem.size <<= 1; \
+ _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram); \
+ _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size); \
+ _p_->hdr.size = ((sizeof(struct tag_revision)) + sizeof(struct tag_header)) / sizeof(long); \
+ _p_->hdr.tag = ATAG_REVISION; \
+ _p_->u.revision.rev = system_rev; \
+ } \
+ CYG_MACRO_END
+
+#endif // CYGONCE_HAL_ARM_BOARD_PLF_IO_H
--- /dev/null
+#ifndef CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+#define CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+//=============================================================================
+//
+// plf_mmap.h
+//
+// Platform specific memory map support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_misc.h>
+#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+
+// Get the pagesize for a particular virtual address:
+
+// This does not depend on the vaddr.
+#define HAL_MM_PAGESIZE(vaddr, pagesize) CYG_MACRO_START \
+ (pagesize) = SZ_1M; \
+CYG_MACRO_END
+
+// Get the physical address from a virtual address:
+
+#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START \
+ cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
+ if ( _v_ < SDRAM_SIZE ) /* SDRAM */ \
+ _v_ += SDRAM_BASE_ADDR; \
+ else /* Rest of it */ \
+ /* no change */ ; \
+ (paddr) = _v_; \
+CYG_MACRO_END
+
+//---------------------------------------------------------------------------
+#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
--- /dev/null
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware mx51_rocky ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM current ;
+ package -hardware CYGPKG_HAL_ARM_MX51 current ;
+ package -hardware CYGPKG_HAL_ARM_MX51_ROCKY current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ;
+ package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ;
+ package -hardware CYGPKG_COMPRESS_ZLIB current ;
+ package -hardware CYGPKG_IO_FLASH current ;
+ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+ package -hardware CYGPKG_DEVS_IMX_SPI current ;
+ package -hardware CYGPKG_DEVS_MXC_I2C current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package CYGPKG_MEMALLOC current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_IMX_SPI_NOR {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_ATA {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MMC {
+ inferred_value 1
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
+ user_value 50
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ inferred_value 0x00040000
+};
+
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+ inferred_value 0x90008000
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_component CYG_HAL_STARTUP {
+ user_value ROMRAM
+};
+
+cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+ inferred_value 1
+};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+ inferred_value 4
+};
+
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+ user_value 1 "FSL 200904"
+};
--- /dev/null
+/*=============================================================================
+//
+// board_diag.c
+//
+// HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_arch.h> // basic machine info
+#include <cyg/hal/hal_intr.h> // interrupt macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_if.h> // Calling-if API
+#include <cyg/hal/drv_api.h> // driver API
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/fsl_board.h> // Platform specifics
+
+extern void cyg_hal_plf_serial_init(void);
+
+void cyg_hal_plf_comms_init(void)
+{
+ static int initialized = 0;
+
+ if (initialized)
+ return;
+
+ initialized = 1;
+
+ /* Setup GPIO and enable transceiver for UARTs */
+ cyg_hal_plf_serial_init();
+}
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
+
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
+#define __BASE CMA101_DUARTA
+#define _INT CYGNUM_HAL_INTERRUPT_SERIAL_A
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1)
+#define __BASE CMA101_DUARTB
+#define _INT CYGNUM_HAL_INTERRUPT_SERIAL_B
+#endif
+
+#ifdef __BASE
+
+#ifdef CYGSEM_HAL_ROM_MONITOR
+#define CYG_HAL_STARTUP_ROM
+#define CYG_HAL_STARTUP_ROMRAM
+#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#endif
+
+#if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define HAL_DIAG_USES_HARDWARE
+#elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
+#define HAL_DIAG_USES_HARDWARE
+#elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+#define HAL_DIAG_USES_HARDWARE
+#endif
+
+static channel_data_t channel = {
+ (uart_width*) _BASE, 0, 0
+};
+
+#ifdef HAL_DIAG_USES_HARDWARE
+
+void hal_diag_init(void)
+{
+ static int init = 0;
+ char *msg = "\n\rARM eCos\n\r";
+ uart_width lcr;
+
+ if (init++) return;
+
+ init_duart_channel(&channel);
+
+ while (*msg) hal_diag_write_char(*msg++);
+}
+
+#ifdef DEBUG_DIAG
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define DIAG_BUFSIZE 32
+#else
+#define DIAG_BUFSIZE 2048
+#endif
+static char diag_buffer[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+
+void hal_diag_write_char(char c)
+{
+ uart_width lsr;
+
+ hal_diag_init();
+
+ cyg_hal_plf_duart_putc(&channel, c)
+
+#ifdef DEBUG_DIAG
+ diag_buffer[diag_bp++] = c;
+ if (diag_bp == DIAG_BUFSIZE) {
+ while (1) ;
+ diag_bp = 0;
+ }
+#endif
+}
+
+void hal_diag_read_char(char *c)
+{
+ *c = cyg_hal_plf_duart_getc(&channel);
+}
+
+#else // HAL_DIAG relies on GDB
+
+// Initialize diag port - assume GDB channel is already set up
+void hal_diag_init(void)
+{
+ if (0) init_duart_channel(&channel); // avoid warning
+}
+
+// Actually send character down the wire
+static void hal_diag_write_char_serial(char c)
+{
+ cyg_hal_plf_duart_putc(&channel, c);
+}
+
+static bool hal_diag_read_serial(char *c)
+{
+ long timeout = 1000000000; // A long time...
+
+ while (!cyg_hal_plf_duart_getc_nonblock(&channel, c))
+ if (0 == --timeout) return false;
+
+ return true;
+}
+
+void hal_diag_read_char(char *c)
+{
+ while (!hal_diag_read_serial(c)) ;
+}
+
+void hal_diag_write_char(char c)
+{
+ static char line[100];
+ static int pos = 0;
+
+ // No need to send CRs
+ if (c == '\r') return;
+
+ line[pos++] = c;
+
+ if (c == '\n' || pos == sizeof(line)) {
+ CYG_INTERRUPT_STATE old;
+
+ // Disable interrupts. This prevents GDB trying to interrupt us
+ // while we are in the middle of sending a packet. The serial
+ // receive interrupt will be seen when we re-enable interrupts
+ // later.
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+#else
+ HAL_DISABLE_INTERRUPTS(old);
+#endif
+
+ while (1) {
+ static char hex[] = "0123456789ABCDEF";
+ cyg_uint8 csum = 0;
+ int i;
+ char c1;
+
+ hal_diag_write_char_serial('$');
+ hal_diag_write_char_serial('O');
+ csum += 'O';
+ for (i = 0; i < pos; i++) {
+ char ch = line[i];
+ char h = hex[(ch>>4)&0xF];
+ char l = hex[ch&0xF];
+ hal_diag_write_char_serial(h);
+ hal_diag_write_char_serial(l);
+ csum += h;
+ csum += l;
+ }
+ hal_diag_write_char_serial('#');
+ hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
+ hal_diag_write_char_serial(hex[csum&0xF]);
+
+ // Wait for the ACK character '+' from GDB here and handle
+ // receiving a ^C instead. This is the reason for this clause
+ // being a loop.
+ if (!hal_diag_read_serial(&c1))
+ continue; // No response - try sending packet again
+
+ if ( c1 == '+' )
+ break; // a good acknowledge
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
+ if ( c1 == 3 ) {
+ // Ctrl-C: breakpoint.
+ cyg_hal_gdb_interrupt (__builtin_return_address(0));
+ break;
+ }
+#endif
+ // otherwise, loop round again
+ }
+
+ pos = 0;
+
+ // And re-enable interrupts
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+#else
+ HAL_RESTORE_INTERRUPTS(old);
+#endif
+
+ }
+}
+#endif
+
+#endif // __BASE
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
--- /dev/null
+//==========================================================================
+//
+// board_misc.c
+//
+// HAL misc board support code for the board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include <redboot.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h> // Interrupt names
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/fsl_board.h> // Platform specifics
+#include <cyg/infra/diag.h> // diag_printf
+
+// All the MM table layout is here:
+#include <cyg/hal/hal_mm.h>
+
+externC void* memset(void *, int, size_t);
+unsigned int cpld_base_addr;
+
+void hal_mmu_init(void)
+{
+ unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
+ unsigned long i;
+
+ /*
+ * Set the TTB register
+ */
+ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
+
+ /*
+ * Set the Domain Access Control Register
+ */
+ i = ARM_ACCESS_DACR_DEFAULT;
+ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+
+ /*
+ * First clear all TT entries - ie Set them to Faulting
+ */
+ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+
+ /* Actual Virtual Size Attributes Function */
+ /* Base Base MB cached? buffered? access permissions */
+ /* xxx00000 xxx00000 */
+ X_ARM_MMU_SECTION(0x000, 0x200, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */
+ X_ARM_MMU_SECTION(0x1FF, 0x1FF, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IRAM */
+ X_ARM_MMU_SECTION(0x300, 0x300, 0x100, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* GPU */
+ X_ARM_MMU_SECTION(0x400, 0x400, 0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IPUv3D */
+ X_ARM_MMU_SECTION(0x600, 0x600, 0x300, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* periperals */
+ X_ARM_MMU_SECTION(0x900, 0x000, 0x1FF, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0x900, 0x900, 0x200, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0xB00, 0xB00, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS0 EIM control*/
+ X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */
+}
+
+#include <cyg/io/imx_spi.h>
+struct spi_v2_3_reg spi_pmic_reg;
+
+struct imx_spi_dev imx_spi_pmic = {
+ base : CSPI1_BASE_ADDR,
+ freq : 25000000,
+ ss_pol : IMX_SPI_ACTIVE_HIGH,
+ ss : 0, // slave select 0
+ fifo_sz : 64 * 4,
+ reg : &spi_pmic_reg,
+};
+
+struct spi_v2_3_reg spi_nor_reg;
+
+struct imx_spi_dev imx_spi_nor = {
+ base : CSPI1_BASE_ADDR,
+ freq : 25000000,
+ ss_pol : IMX_SPI_ACTIVE_LOW,
+ ss : 1, // slave select 1
+ fifo_sz : 64 * 4,
+ us_delay: 0,
+ reg : &spi_nor_reg,
+};
+
+imx_spi_init_func_t *spi_nor_init;
+imx_spi_xfer_func_t *spi_nor_xfer;
+
+imx_spi_init_func_t *spi_pmic_init;
+imx_spi_xfer_func_t *spi_pmic_xfer;
+
+//
+// Platform specific initialization
+//
+
+void plf_hardware_init(void)
+{
+ unsigned int reg;
+ unsigned long weim_base;
+
+ // CS0 setup
+ weim_base = WEIM_BASE_ADDR;
+ writel(0x00410089, weim_base + CSGCR1);
+ writel(0x00000002, weim_base + CSGCR2);
+ // RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0
+ writel(0x32260000, weim_base + CSRCR1);
+ // APR=0
+ writel(0x00000000, weim_base + CSRCR2);
+ // WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, WCSA=0, WCSN=0
+ writel(0x72080F00, weim_base + CSWCR1);
+
+ /* Disable IPU and HSC dividers */
+ writel(0x60000, CCM_BASE_ADDR + CLKCTL_CCDR);
+ /* Change the DDR divider to run at 166MHz on CPU 2 */
+ reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
+ reg = (reg & (~0x70000)) | 0x30000;
+ writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR);
+ /* make sure divider effective */
+ while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0);
+ writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
+
+ // UART1
+ //RXD
+ writel(0x0, IOMUXC_BASE_ADDR + 0x234);
+ writel(0x1C5, IOMUXC_BASE_ADDR + 0x6E4);
+
+ //TXD
+ writel(0x0, IOMUXC_BASE_ADDR + 0x238);
+ writel(0x1C5, IOMUXC_BASE_ADDR + 0x6E8);
+
+ //RTS
+ writel(0x0, IOMUXC_BASE_ADDR + 0x23C);
+ writel(0x1C4, IOMUXC_BASE_ADDR + 0x6EC);
+
+ //CTS
+ writel(0x0, IOMUXC_BASE_ADDR + 0x240);
+ writel(0x1C4, IOMUXC_BASE_ADDR + 0x6F0);
+
+ // enable GPIO1_9 for CLKO and GPIO1_8 for CLKO2
+ writel(0x00000004, 0x73fa83F4);
+ writel(0x00000004, 0x73fa83F0);
+ // enable ARM clock div by 8
+ writel(0x010900F0, CCM_BASE_ADDR + CLKCTL_CCOSR);
+
+ // now turn on the LCD backlight
+ reg = readl(0x73f84004);
+ writel(reg | 0x4, 0x73f84004);
+ reg = readl(0x73f84000);
+ writel(reg | 0x4, 0x73f84000);
+
+ // now turn on the LCD
+ // Set NANDF_CS7 pin to be GPIO output and set it to 1
+ writel(0x3, 0x73fa8158);
+ reg = readl(0x73f8c004);
+ writel(reg | 0x800000, 0x73f8c004);
+ reg = readl(0x73f8c000);
+ writel(reg | 0x800000, 0x73f8c000);
+
+ spi_nor_init = (imx_spi_init_func_t *)imx_spi_init_v2_3;
+ spi_nor_xfer = (imx_spi_xfer_func_t *)imx_spi_xfer_v2_3;
+
+ spi_pmic_init = (imx_spi_init_func_t *)imx_spi_init_v2_3;
+ spi_pmic_xfer = (imx_spi_xfer_func_t *)imx_spi_xfer_v2_3;
+}
+
+static void rocky_lan_reset(void)
+{
+ unsigned int reg;
+
+ /* Issue a reset to the LAN chip */
+ reg = readl(GPIO2_BASE_ADDR + 0x0);
+ reg |= 0x20000000 ; // write a 1 on the reset line
+ writel(reg, GPIO2_BASE_ADDR + 0x0);
+
+ reg = readl(GPIO2_BASE_ADDR + 0x4);
+ reg |= 0x20000000; // configure GPIO lines as output
+ writel(reg, GPIO2_BASE_ADDR + 0x4);
+
+ hal_delay_us(300);
+
+ reg = readl(GPIO2_BASE_ADDR + 0x0);
+ reg &= ~0x20000000; // write a 0 on the reset line
+ writel(reg, GPIO2_BASE_ADDR + 0x0);
+
+ hal_delay_us(30000);
+
+ reg = readl(GPIO2_BASE_ADDR + 0x0);
+ reg |= 0x20000000 ; // write a 1 on the reset line
+ writel(reg, GPIO2_BASE_ADDR + 0x0);
+}
+
+void mxc_ata_iomux_setup(void)
+{
+ // config NANDF_WE_B pad for pata instance DIOW port
+ // config_pad_mode(NANDF_WE_B, ALT1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull / Keep Select to Pull (Different from Module Level value: NA)
+ // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to Disabled
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_WE_B, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B);
+
+ // config NANDF_RE_B pad for pata instance DIOR port
+ // config_pad_mode(NANDF_RE_B, ALT1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull / Keep Select to Pull (Different from Module Level value: NA)
+ // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to Disabled
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_RE_B, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B);
+
+ // config NANDF_CLE pad for pata instance PATA_RESET_B port
+ // config_pad_mode(NANDF_CLE, ALT1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Hyst. Enable to Disabled
+ // Pull / Keep Select to Keep (Different from Module Level value: NA)
+ // Pull Up / Down Config. to 100Kohm PU (Different from Module Level value: NA)
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Pull / Keep Enable to Disabled
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_CLE, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE);
+
+ // config NANDF_WP_B pad for pata instance DMACK port
+ // config_pad_mode(NANDF_WP_B, ALT1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull / Keep Select to Pull (Different from Module Level value: NA)
+ // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to Disabled
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_WP_B, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B);
+
+ // config NANDF_RB0 pad for pata instance DMARQ port
+ // config_pad_mode(NANDF_RB0, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled (Different from Module Level value: NA)
+ // Drive Strength to NA (CFG in SoC Level however NA in Module Level)
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to CFG(360Kohm PD)
+ // config_pad_settings(NANDF_RB0, 0x20c0);
+ writel(0xC0, IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0);
+
+ // config NANDF_RB1 pad for pata instance IORDY port
+ // config_pad_mode(NANDF_RB1, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to NA (CFG in SoC Level however NA in Module Level)
+ // Drive Strength to NA (CFG in SoC Level however NA in Module Level)
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // config_pad_settings(NANDF_RB1, 0x20e0);
+ writel(0xD0, IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1);
+
+ // config NANDF_RB5 pad for pata instance INTRQ port
+ // config_pad_mode(NANDF_RB5, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RB5);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull Up / Down Config. to 100Kohm PU
+ // Open Drain Enable to Disabled (Different from Module Level value: NA)
+ // Drive Strength to NA (CFG in SoC Level however NA in Module Level)
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // config_pad_settings(NANDF_RB5, 0x20c0);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RB5);
+
+ // config NANDF_CS2 pad for pata instance CS_0 port
+ // config_pad_mode(NANDF_CS2, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull / Keep Select to NA (CFG in SoC Level however NA in Module Level)
+ // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to Disabled
+ // Open Drain Enable to Disabled
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_CS2, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2);
+
+ // config NANDF_CS3 pad for pata instance CS_1 port
+ // config_pad_mode(NANDF_CS3, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull / Keep Select to NA (CFG in SoC Level however NA in Module Level)
+ // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to Disabled
+ // Open Drain Enable to Disabled
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_CS3, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3);
+
+ // config NANDF_CS4 pad for pata instance DA_0 port
+ // config_pad_mode(NANDF_CS4, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull / Keep Select to NA (CFG in SoC Level however NA in Module Level)
+ // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to Disabled
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_CS4, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4);
+
+ // config NANDF_CS5 pad for pata instance DA_1 port
+ // config_pad_mode(NANDF_CS5, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull / Keep Select to NA (CFG in SoC Level however NA in Module Level)
+ // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to Disabled
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_CS5, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5);
+
+ // config NANDF_CS6 pad for pata instance DA_2 port
+ // config_pad_mode(NANDF_CS6, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull / Keep Select to Pull (Different from Module Level value: NA)
+ // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to Disabled
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_CS6, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6);
+
+ // config NANDF_D15 pad for pata instance PATA_DATA[15] port
+ // config_pad_mode(NANDF_D15, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D15);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D15, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D15);
+
+ // config NANDF_D14 pad for pata instance PATA_DATA[14] port
+ // config_pad_mode(NANDF_D14, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D14);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D14, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D14);
+
+ // config NANDF_D13 pad for pata instance PATA_DATA[13] port
+ // config_pad_mode(NANDF_D13, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D13);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D13, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D13);
+
+ // config NANDF_D12 pad for pata instance PATA_DATA[12] port
+ // config_pad_mode(NANDF_D12, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D12);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D12, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D12);
+
+ // config NANDF_D11 pad for pata instance PATA_DATA[11] port
+ // config_pad_mode(NANDF_D11, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D11);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D11, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D11);
+
+ // config NANDF_D10 pad for pata instance PATA_DATA[10] port
+ // config_pad_mode(NANDF_D10, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D10);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D10, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D10);
+
+ // config NANDF_D9 pad for pata instance PATA_DATA[9] port
+ // config_pad_mode(NANDF_D9, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D9);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D9, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D9);
+
+ // config NANDF_D8 pad for pata instance PATA_DATA[8] port
+ // config_pad_mode(NANDF_D8, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D8);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D8, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D8);
+
+ // config NANDF_D7 pad for pata instance PATA_DATA[7] port
+ // config_pad_mode(NANDF_D7, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D7);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull Up / Down Config. to 100Kohm PU
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D7, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D7);
+
+ // config NANDF_D6 pad for pata instance PATA_DATA[6] port
+ // config_pad_mode(NANDF_D6, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D6);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull Up / Down Config. to 100Kohm PU
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Open Drain Enable to Disabled
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D6, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D6);
+
+ // config NANDF_D5 pad for pata instance PATA_DATA[5] port
+ // config_pad_mode(NANDF_D5, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D5);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull Up / Down Config. to 100Kohm PU
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D5, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D5);
+
+ // config NANDF_D4 pad for pata instance PATA_DATA[4] port
+ // config_pad_mode(NANDF_D4, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D4);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Pull Up / Down Config. to 100Kohm PU
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D4, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D4);
+
+ // config NANDF_D3 pad for pata instance PATA_DATA[3] port
+ // config_pad_mode(NANDF_D3, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D3);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D3, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D3);
+
+ // config NANDF_D2 pad for pata instance PATA_DATA[2] port
+ // config_pad_mode(NANDF_D2, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D2);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D2, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D2);
+
+ // config NANDF_D1 pad for pata instance PATA_DATA[1] port
+ // config_pad_mode(NANDF_D1, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D1);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D1, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D1);
+
+ // config NANDF_D0 pad for pata instance PATA_DATA[0] port
+ // config_pad_mode(NANDF_D0, 0x1);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D0);
+ // CONSTANT SETTINGS:
+ // test_ts to Disabled
+ // dse test to regular
+ // strength mode to NA (Different from Module Level value: 4_level)
+ // DDR / CMOS Input Mode to NA
+ // Open Drain Enable to Disabled
+ // Slew Rate to NA
+ // CONFIGURED SETTINGS:
+ // low/high output voltage to CFG(High)
+ // Hyst. Enable to Disabled
+ // Pull / Keep Enable to CFG(Enabled)
+ // Pull / Keep Select to Pull
+ // Pull Up / Down Config. to 100Kohm PU
+ // Drive Strength to CFG(High)
+ // config_pad_settings(NANDF_D0, 0x2004);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D0);
+}
+
+void mxc_i2c_init(unsigned int module_base)
+{
+ unsigned int reg;
+
+ switch (module_base) {
+ case I2C_BASE_ADDR:
+ break;
+ case I2C2_BASE_ADDR:
+ writel(0x13, IOMUXC_BASE_ADDR + 0x0278);
+ writel(0x13, IOMUXC_BASE_ADDR + 0x027C);
+
+ writel(0x1, IOMUXC_BASE_ADDR + 0x0A08);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x0A0C);
+
+ writel(0x1ED, IOMUXC_BASE_ADDR + 0x0728);
+ writel(0x1ED, IOMUXC_BASE_ADDR + 0x072C);
+
+ break;
+ default:
+ diag_printf("Invalid I2C base: 0x%x\n", module_base);
+ return;
+ }
+}
+
+
+void mxc_mmc_init(unsigned int base_address)
+{
+ switch(base_address) {
+ case MMC_SDHC1_BASE_ADDR:
+ //diag_printf("Configure IOMUX of ESDHC1 on i.MX51\n");
+ /* SD1 CMD, SION bit */
+ writel(0x10, IOMUXC_BASE_ADDR + 0x39c);
+#if 0
+ /* SD1 DAT4 */
+ writel(0x1, IOMUXC_BASE_ADDR + 0x3c4);
+ /* SD1 DAT5 */
+ writel(0x1, IOMUXC_BASE_ADDR + 0x3c8);
+ /* SD1 DAT6 */
+ writel(0x1, IOMUXC_BASE_ADDR + 0x3cc);
+ /* SD1 DAT7 */
+ writel(0x1, IOMUXC_BASE_ADDR + 0x3d0);
+#endif
+
+ /* SD1 CD, as gpio1_0 */
+ writel(0x01, IOMUXC_BASE_ADDR + 0x3b4);
+ /* Configure SW PAD */
+ /* SD1 CMD */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x868);
+ /* SD1 CLK */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x86c);
+ /* SD1 DAT0 */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x870);
+ /* SD1 DAT1 */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x874);
+ /* SD1 DAT2 */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x878);
+ /* SD1 DAT3 */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x87c);
+ /* SD1 CD as gpio1_0 */
+ writel(0x1e2, IOMUXC_BASE_ADDR + 0x880);
+ break;
+ default:
+ break;
+ }
+}
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+typedef void code_fun(void);
+
+void board_program_new_stack(void *func)
+{
+ register CYG_ADDRESS stack_ptr asm("sp");
+ register CYG_ADDRESS old_stack asm("r4");
+ register code_fun *new_func asm("r0");
+ old_stack = stack_ptr;
+ stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
+ new_func = (code_fun*)func;
+ new_func();
+ stack_ptr = old_stack;
+}
+
+void increase_core_voltage(bool i)
+{
+ unsigned int val;
+
+ val = pmic_reg(24, 0, 0);
+
+ if (i) {
+ /* Set core voltage to 1.175V */
+ val = val & (~0x1F) | 0x17;
+ } else {
+ /* Set core voltage to 1.05V */
+ val = val & (~0x1F) | 0x12;
+ }
+
+ pmic_reg(24, val, 1);
+}
+
+extern unsigned int pmic_reg(unsigned int reg, unsigned int val, unsigned int write);
+static void rocky_power_init(void)
+{
+ unsigned int val;
+
+ /* power up the system first */
+ pmic_reg(34, 0x00200000, 1);
+
+ if (pll_clock(PLL1) > 800000000) {
+ /* Set core voltage to 1.175V */
+ val = pmic_reg(24, 0, 0);
+ val = val & (~0x1F) | 0x17;
+ pmic_reg(24, val, 1);
+ }
+
+ /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */
+ val = pmic_reg(30, 0, 0);
+ val &= ~0x34030;
+ val |= 0x0020;
+ pmic_reg(30, val, 1);
+
+ /* Set VVIDEO to 2.775V, VAUDIO to 2.775V, VSD to 3.15V */
+ val = pmic_reg(31, 0, 0);
+ val &= ~0x1FC;
+ val |= 0x1F4;
+ pmic_reg(31, val, 1);
+
+ /* Configure VGEN3 and VCAM regulators to use external PNP */
+ val = 0x208;
+ pmic_reg(33, val, 1);
+ hal_delay_us(200);
+
+ /* Enable VGEN1 regulator */
+ val = pmic_reg(32, val, 0);
+ val |= 0x1;
+ pmic_reg(32, val, 1);
+
+ /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
+ val = 0x49249;
+ pmic_reg(33, val, 1);
+
+ /* Enable SWBSTEN */
+ val = pmic_reg(29, val, 0);
+ val |= 0x100000;
+ pmic_reg(29, val, 1);
+
+ /* SW2 to 1.25V (VCC - MX51 Peripheral core) */
+ val = pmic_reg(25, val, 0);
+ val &= ~0x1F;
+ val |= 0x19;
+ pmic_reg(25, val, 1);
+
+ hal_delay_us(300);
+
+ rocky_lan_reset();
+}
+
+RedBoot_init(rocky_power_init, RedBoot_INIT_PRIO(900));
+
+void io_cfg_spi(struct imx_spi_dev *dev)
+{
+ switch (dev->base) {
+ case CSPI1_BASE_ADDR:
+ // 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1
+ writel(0x0, IOMUXC_BASE_ADDR + 0x21C);
+ writel(0x105, IOMUXC_BASE_ADDR + 0x6CC);
+
+ // 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1.
+ writel(0x0, IOMUXC_BASE_ADDR + 0x220);
+ writel(0x105, IOMUXC_BASE_ADDR + 0x6D0);
+ if (dev->ss == 0) {
+ // de-select SS1 of instance: ecspi1.
+ writel(0x3, IOMUXC_BASE_ADDR + 0x228);
+ writel(0x85, IOMUXC_BASE_ADDR + 0x6D8);
+ // 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1.
+ writel(0x0, IOMUXC_BASE_ADDR + 0x224);
+ writel(0x185, IOMUXC_BASE_ADDR + 0x6D4);
+ } else if (dev->ss == 1) {
+ // de-select SS0 of instance: ecspi1.
+ writel(0x3, IOMUXC_BASE_ADDR + 0x224);
+ writel(0x85, IOMUXC_BASE_ADDR + 0x6D4);
+ // 000: Select mux mode: ALT0 mux port: SS1 of instance: ecspi1.
+ writel(0x0, IOMUXC_BASE_ADDR + 0x228);
+ writel(0x105, IOMUXC_BASE_ADDR + 0x6D8);
+ }
+ // 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1.
+ writel(0x0, IOMUXC_BASE_ADDR + 0x22C);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x6DC);
+
+ // 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1.
+ writel(0x0, IOMUXC_BASE_ADDR + 0x230);
+ writel(0x105, IOMUXC_BASE_ADDR + 0x6E0);
+ break;
+ case CSPI2_BASE_ADDR:
+ default:
+ break;
+ }
+}
--- /dev/null
+//==========================================================================
+//
+// redboot_cmds.c
+//
+// Board [platform] specific RedBoot commands
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+#include <redboot.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/plf_mmap.h>
+#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <flash_config.h>
+
+#if (REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE)
+#error REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE
+#endif
+
+RedBoot_config_option("Board specifics",
+ brd_specs,
+ ALWAYS_ENABLED,
+ true,
+ CONFIG_INT,
+ 0
+ );
+#endif //CYGSEM_REDBOOT_FLASH_CONFIG
+
+char HAL_PLATFORM_EXTRA[20] = "PASS x.x [x32 DDR]";
+
+static void runImg(int argc, char *argv[]);
+
+RedBoot_cmd("run",
+ "Run an image at a location with MMU off",
+ "[<virtual addr>]",
+ runImg
+ );
+
+void launchRunImg(unsigned long addr)
+{
+ asm volatile ("mov r12, r0;");
+ HAL_CACHE_FLUSH_ALL();
+ HAL_DISABLE_L2();
+ HAL_MMU_OFF();
+ asm volatile (
+ "mov r0, #0;"
+ "mov r1, r12;"
+ "mov r11, #0;"
+ "mov r12, #0;"
+ "mrs r10, cpsr;"
+ "bic r10, r10, #0xF0000000;"
+ "msr cpsr_f, r10;"
+ "mov pc, r1"
+ );
+}
+
+extern unsigned long entry_address;
+
+static void runImg(int argc,char *argv[])
+{
+ unsigned int virt_addr, phys_addr;
+
+ // Default physical entry point for Symbian
+ if (entry_address == 0xFFFFFFFF)
+ virt_addr = 0x800000;
+ else
+ virt_addr = entry_address;
+
+ if (!scan_opts(argc,argv,1,0,0,(void*)&virt_addr,
+ OPTION_ARG_TYPE_NUM, "virtual address"))
+ return;
+
+ if (entry_address != 0xFFFFFFFF)
+ diag_printf("load entry_address=0x%lx\n", entry_address);
+ HAL_VIRT_TO_PHYS_ADDRESS(virt_addr, phys_addr);
+
+ diag_printf("virt_addr=0x%x\n",virt_addr);
+ diag_printf("phys_addr=0x%x\n",phys_addr);
+
+ launchRunImg(phys_addr);
+}
+
+#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYG_HAL_STARTUP_ROMRAM)
+
+RedBoot_cmd("romupdate",
+ "Update Redboot with currently running image",
+ "",
+ romupdate
+ );
+
+extern int flash_program(void *_addr, void *_data, int len, void **err_addr);
+extern int flash_erase(void *addr, int len, void **err_addr);
+extern char *flash_errmsg(int err);
+extern unsigned char *ram_end; //ram end is where the redboot starts FIXME: use PC value
+extern cyg_uint32 mmc_data_read (cyg_uint32 *,cyg_uint32 ,cyg_uint32);
+extern int spi_nor_erase_block(void* block_addr, unsigned int block_size);
+extern int spi_nor_program_buf(void *addr, void *data, int len);
+
+#ifdef CYGPKG_IO_FLASH
+void romupdate(int argc, char *argv[])
+{
+ void *err_addr, *base_addr;
+ int stat;
+ unsigned int nfc_config3_reg, temp;
+
+ if (IS_FIS_FROM_MMC() || IS_BOOTING_FROM_MMC()) {
+ diag_printf("Updating ROM in MMC/SD flash\n");
+ base_addr = (void*)0;
+ /* Read the first 1K from the card */
+ mmc_data_read((cyg_uint32*)(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000),
+ 0x400, base_addr);
+ diag_printf("Programming Redboot to MMC/SD flash\n");
+ mmc_data_write((cyg_uint32*)(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000),
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE, (cyg_uint32)base_addr);
+ return;
+ } else if (IS_BOOTING_FROM_SPI_NOR() || IS_FIS_FROM_SPI_NOR()) {
+ diag_printf("Updating ROM in SPI-NOR flash\n");
+ base_addr = (void*)0;
+ } else {
+ diag_printf("romupdate not supported\n");
+ diag_printf("Use \"factive [SPI|MMC]\" to select either NAND or MMC flash\n");
+ }
+
+ // Erase area to be programmed
+ if ((stat = flash_erase((void *)base_addr,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ (void **)&err_addr)) != 0) {
+ diag_printf("Can't erase region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ return;
+ }
+ // Now program it
+ if ((stat = flash_program((void *)base_addr,
+ (void *)SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ (void **)&err_addr)) != 0) {
+ diag_printf("Can't program region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ }
+}
+RedBoot_cmd("factive",
+ "Enable one flash media for Redboot",
+ "[MMC|SPI]",
+ factive
+ );
+
+typedef void reset_func_t(void);
+
+extern reset_func_t reset_vector;
+
+void factive(int argc, char *argv[])
+{
+ unsigned long phys_addr;
+ unsigned int *fis_addr = IRAM_BASE_ADDR;
+
+ if (argc != 2) {
+ diag_printf("Invalid factive cmd\n");
+ return;
+ }
+
+ if (strcasecmp(argv[1], "MMC") == 0) {
+ *fis_addr = FROM_MMC_FLASH;
+ } else if (strcasecmp(argv[1], "SPI") == 0) {
+ *fis_addr = FROM_SPI_NOR_FLASH;
+ }
+ else {
+ diag_printf("Invalid command: %s\n", argv[1]);
+ return;
+ }
+
+ //HAL_VIRT_TO_PHYS_ADDRESS(ram_end, phys_addr);
+ launchRunImg(reset_vector);
+}
+#endif //CYGPKG_IO_FLASH
+
+#define POST_SDRAM_START_OFFSET 0x800000
+#define POST_MMC_OFFSET 0x100000
+#define POST_SIZE 0x100000
+#define POST_MAGIC_MARKER 0x43
+
+
+void imx_launch_post(void)
+{
+ mmc_data_read(0x100000, // ram location
+ 0x40000, // length
+ 0x100000); // from MMC/SD offset 0x100000
+ spi_nor_erase_block(0, 0x10000);
+ spi_nor_erase_block(0x10000, 0x10000);
+ spi_nor_erase_block(0x20000, 0x10000);
+ spi_nor_erase_block(0x30000, 0x10000);
+ // save the redboot to SPI-NOR
+ spi_nor_program_buf(0, 0x100000, 0x40000);
+
+ diag_printf("Reading POST from MMC to SDRAM...\n");
+ mmc_data_read(SDRAM_BASE_ADDR + POST_SDRAM_START_OFFSET, // ram location
+ 0x200000, // length
+ 0x200000); // from MMC offset
+ diag_printf("Launching POST\n");
+ launchRunImg(SDRAM_BASE_ADDR + POST_SDRAM_START_OFFSET);
+}
+//RedBoot_init(imx_launch_post, RedBoot_INIT_BEFORE_NET);
+
+#endif /* CYG_HAL_STARTUP_ROMRAM */
--- /dev/null
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): gthomas
+# Original data: gthomas
+# Contributors:
+# Date: 2000-05-08
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+cdl_package CYGPKG_HAL_ARM_MX51 {
+ display "Freescale SoC architecture"
+ parent CYGPKG_HAL_ARM
+ hardware
+ include_dir cyg/hal
+ define_header hal_arm_soc.h
+ description "
+ This HAL variant package provides generic
+ support for the Freescale SoC. It is also
+ necessary to select a specific target platform HAL
+ package."
+
+ implements CYGINT_HAL_ARM_ARCH_ARM9
+ implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+
+ # Let the architectural HAL see this variant's interrupts file -
+ # the SoC has no variation between targets here.
+ define_proc {
+ puts $::cdl_header "#define CYGBLD_HAL_VAR_INTS_H <cyg/hal/hal_var_ints.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H"
+
+ puts $::cdl_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 1000000"
+ }
+
+ compile soc_diag.c soc_misc.c
+ compile -library=libextras.a cmds.c
+
+ cdl_option CYGHWR_MX51_TO2 {
+ display "MX51 Tapeout 2.0 support"
+ default_value 0
+ description "
+ When this option is enabled, it indicates support for
+ MX51 Tapeout 2.0"
+ define_proc {
+ puts $::cdl_system_header "#define IMX51_TO_2"
+ }
+ }
+
+ cdl_option CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK {
+ display "Processor clock rate"
+ active_if { CYG_HAL_STARTUP == "ROM" }
+ flavor data
+ legal_values 150000 200000
+ default_value { CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT ?
+ CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT : 150000}
+ description "
+ The processor can run at various frequencies.
+ These values are expressed in KHz. Note that there are
+ several steppings of the rated to run at different
+ maximum frequencies. Check the specs to make sure that your
+ particular processor can run at the rate you select here."
+ }
+
+ # Real-time clock/counter specifics
+ cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+ display "Real-time clock constants"
+ flavor none
+ no_define
+
+ cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+ display "Real-time clock numerator"
+ flavor data
+ calculated 1000000000
+ }
+ cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+ display "Real-time clock denominator"
+ flavor data
+ default_value 100
+ description "
+ This option selects the heartbeat rate for the real-time clock.
+ The rate is specified in ticks per second. Change this value
+ with caution - too high and your system will become saturated
+ just handling clock interrupts, too low and some operations
+ such as thread scheduling may become sluggish."
+ }
+ cdl_option CYGNUM_HAL_RTC_PERIOD {
+ display "Real-time clock period"
+ flavor data
+ calculated (3686400/CYGNUM_HAL_RTC_DENOMINATOR) ;# Clock for OS Timer is 3.6864MHz
+ }
+ }
+
+ # Control over hardware layout.
+ cdl_interface CYGHWR_HAL_ARM_SOC_UART1 {
+ display "UART1 available as diagnostic/debug channel"
+ description "
+ The chip has multiple serial channels which may be
+ used for different things on different platforms. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_SOC_UART2 {
+ display "UART2 available as diagnostic/debug channel"
+ description "
+ The chip has multiple serial channels which may be
+ used for different things on different platforms. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_SOC_UART3 {
+ display "UART3 available as diagnostic/debug channel"
+ description "
+ The chip has multiple serial channels which may be
+ used for different things on different platforms. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_SOC_UART4 {
+ display "UART4 available as diagnostic/debug channel"
+ description "
+ The chip has multiple serial channels which may be
+ used for different things on different platforms. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGHWR_HAL_ARM_SOC_UART5 {
+ display "UART5 available as diagnostic/debug channel"
+ description "
+ The chip has multiple serial channels which may be
+ used for different things on different platforms. This
+ interface allows a platform to indicate that the specified
+ serial port can be used as a diagnostic and/or debug channel."
+ }
+
+ cdl_interface CYGINT_DEVS_ETH_FEC_REQUIRED {
+ display "FEC ethernet driver required"
+ }
+
+ implements CYGINT_DEVS_ETH_FEC_REQUIRED
+
+}
--- /dev/null
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+
+//=============================================================================
+//
+// hal_cache.h
+//
+// HAL cache control API
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
+
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE_L1() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mrc p15, 0, r1, c1, c0, 0;" \
+ "orr r1, r1, #0x0007;" /* enable DCache (also ensures */ \
+ /* the MMU, alignment faults, and */ \
+ "mcr p15, 0, r1, c1, c0, 0" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Clean+invalidate the both D+I caches at L1 and L2 levels
+#define HAL_CACHE_FLUSH_ALL() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "stmfd sp!, {r0-r5, r7, r9-r11};" \
+ "mrc p15, 1, r0, c0, c0, 1;" /*@ read clidr*/ \
+ "ands r3, r0, #0x7000000;" /*@ extract loc from clidr */ \
+ "mov r3, r3, lsr #23;" /*@ left align loc bit field*/ \
+ "beq 555f;" /* finished;" */ /*@ if loc is 0, then no need to clean*/ \
+ "mov r10, #0;" /*@ start clean at cache level 0*/ \
+ "111:" /*"loop1: */ \
+ "add r2, r10, r10, lsr #1;" /*@ work out 3x current cache level*/ \
+ "mov r1, r0, lsr r2;" /*@ extract cache type bits from clidr*/ \
+ "and r1, r1, #7;" /*@ mask of the bits for current cache only*/ \
+ "cmp r1, #2;" /*@ see what cache we have at this level*/ \
+ "blt 444f;" /* skip;" */ /*@ skip if no cache, or just i-cache*/ \
+ "mcr p15, 2, r10, c0, c0, 0;" /*@ select current cache level in cssr*/ \
+ "mcr p15, 0, r10, c7, c5, 4;" /* @ isb to sych the new cssr&csidr */ \
+ "mrc p15, 1, r1, c0, c0, 0;" /*@ read the new csidr*/ \
+ "and r2, r1, #7;" /*@ extract the length of the cache lines*/ \
+ "add r2, r2, #4;" /*@ add 4 (line length offset) */ \
+ "ldr r4, =0x3ff;" \
+ "ands r4, r4, r1, lsr #3;" /*@ find maximum number on the way size*/ \
+ ".word 0xE16F5F14;" /*"clz r5, r4;" @ find bit position of way size increment*/ \
+ "ldr r7, =0x7fff;" \
+ "ands r7, r7, r1, lsr #13;" /*@ extract max number of the index size*/ \
+ "222:" /* loop2:" */ \
+ "mov r9, r4;" /*@ create working copy of max way size*/ \
+ "333:" /* loop3:" */ \
+ "orr r11, r10, r9, lsl r5;" /*@ factor way and cache number into r11*/ \
+ "orr r11, r11, r7, lsl r2;" /*@ factor index number into r11*/ \
+ "mcr p15, 0, r11, c7, c14, 2;" /*@ clean & invalidate by set/way */ \
+ "subs r9, r9, #1;" /*@ decrement the way */ \
+ "bge 333b;" /* loop3;" */ \
+ "subs r7, r7, #1;" /*@ decrement the index */ \
+ "bge 222b;" /* loop2;" */ \
+ "444:" /* skip:" */ \
+ "add r10, r10, #2;" /*@ increment cache number */ \
+ "cmp r3, r10;" \
+ "bgt 111b;" /*loop1;" */ \
+ "555:" /* "finished:" */ \
+ "mov r10, #0;" /*@ swith back to cache level 0 */ \
+ "mcr p15, 2, r10, c0, c0, 0;" /*@ select current cache level in cssr */ \
+ "mcr p15, 0, r10, c7, c5, 4;" /* @ isb to sych the new cssr&csidr */ \
+ "ldmfd sp!, {r0-r5, r7, r9-r11};" \
+ "666:" /* iflush:" */ \
+ "mov r0, #0x0;" \
+ "mcr p15, 0, r0, c7, c5, 0;" /* @ invalidate I+BTB */ \
+ "mcr p15, 0, r0, c7, c10, 4;" /* @ drain WB */ \
+ ); \
+CYG_MACRO_END
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE_C1() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mrc p15, 0, r1, c1, c0, 0;" \
+ "bic r1, r1, #0x0004;" /* disable DCache by clearing C bit */ \
+ /* but not MMU and alignment faults */ \
+ "mcr p15, 0, r1, c1, c0, 0" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Query the state of the data cache
+#define HAL_DCACHE_IS_ENABLED(_state_) \
+CYG_MACRO_START \
+ register int reg; \
+ asm volatile ( \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "mrc p15, 0, %0, c1, c0, 0;" \
+ : "=r"(reg) \
+ : \
+ ); \
+ (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \
+CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE_L1() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mrc p15, 0, r1, c1, c0, 0;" \
+ "orr r1, r1, #0x1000;" \
+ "orr r1, r1, #0x0003;" /* enable ICache (also ensures */ \
+ /* that MMU and alignment faults */ \
+ /* are enabled) */ \
+ "mcr p15, 0, r1, c1, c0, 0" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Query the state of the instruction cache
+#define HAL_ICACHE_IS_ENABLED(_state_) \
+CYG_MACRO_START \
+ register cyg_uint32 reg; \
+ asm volatile ( \
+ "mrc p15, 0, %0, c1, c0, 0" \
+ : "=r"(reg) \
+ : \
+ ); \
+ \
+ (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \
+CYG_MACRO_END
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE_L1() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mrc p15, 0, r1, c1, c0, 0;" \
+ "bic r1, r1, #0x1000;" /* disable ICache (but not MMU, etc) */ \
+ "mcr p15, 0, r1, c1, c0, 0;" \
+ "mov r1, #0;" \
+ "nop;" /* next few instructions may be via cache */ \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL_L1()
+#ifdef TODO
+#define HAL_ICACHE_INVALIDATE_ALL_L1() \
+CYG_MACRO_START \
+ /* this macro can discard dirty cache lines (N/A for ICache) */ \
+ asm volatile ( \
+ "mov r1, #0;" \
+ "mcr p15, 0, r1, c7, c5, 0;" /* flush ICache */ \
+ "mcr p15, 0, r1, c8, c5, 0;" /* flush ITLB only */ \
+ "mcr p15, 0, r1, c7, c5, 4;" /* flush prefetch buffer */ \
+ "nop;" /* next few instructions may be via cache */ \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+#endif
+
+// Synchronize the contents of the cache with memory.
+// (which includes flushing out pending writes)
+#define HAL_ICACHE_SYNC()
+#ifdef TODO
+#define HAL_ICACHE_SYNC() \
+CYG_MACRO_START \
+ HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
+ HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
+CYG_MACRO_END
+#endif
+
+#ifdef L2CC_ENABLED
+// Query the state of the L2 cache
+#define HAL_L2CACHE_IS_ENABLED(_state_) \
+CYG_MACRO_START \
+ register int reg; \
+ asm volatile ( \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "nop; " \
+ "mrc p15, 0, %0, c1, c0, 1;" \
+ : "=r"(reg) \
+ : \
+ ); \
+ (_state_) = (0 != (2 & reg)); /* Bit 1 is L2 Cache enable */ \
+CYG_MACRO_END
+
+#define HAL_ENABLE_L2() \
+{ \
+ asm("mrc 15, 0, r0, c1, c0, 1"); \
+ asm("orr r0, r0, #0x2"); \
+ asm("mcr 15, 0, r0, c1, c0, 1"); \
+}
+
+#define HAL_DISABLE_L2() \
+{ \
+ asm("mrc 15, 0, r0, c1, c0, 1"); \
+ asm("bic r0, r0, #0x2"); \
+ asm("mcr 15, 0, r0, c1, c0, 1"); \
+}
+
+#else //L2CC_ENABLED
+
+#define HAL_ENABLE_L2()
+#define HAL_DISABLE_L2()
+#endif //L2CC_ENABLED
+
+/*********************** Exported macros *******************/
+
+#define HAL_DCACHE_ENABLE() { \
+ HAL_ENABLE_L2(); \
+ HAL_DCACHE_ENABLE_L1(); \
+}
+
+#define HAL_DCACHE_DISABLE() { \
+ HAL_CACHE_FLUSH_ALL(); \
+ HAL_DCACHE_DISABLE_C1(); \
+}
+
+#define HAL_DCACHE_INVALIDATE_ALL() { \
+ HAL_CACHE_FLUSH_ALL(); \
+}
+
+// not needed
+#define HAL_DCACHE_SYNC()
+
+#define HAL_ICACHE_INVALIDATE_ALL() { \
+ HAL_CACHE_FLUSH_ALL(); \
+}
+
+#define HAL_ICACHE_DISABLE() { \
+ HAL_ICACHE_DISABLE_L1(); \
+}
+
+#define HAL_ICACHE_ENABLE() { \
+ HAL_ICACHE_ENABLE_L1(); \
+}
+
+#define CYGARC_HAL_MMU_OFF(__paddr__) \
+ "mrc p15, 0, r0, c1, c0, 0;" /* read c1 */ \
+ "bic r0, r0, #0x7;" /* disable DCache and MMU */ \
+ "bic r0, r0, #0x1000;" /* disable ICache */ \
+ "mcr p15, 0, r0, c1, c0, 0;" /* */ \
+ "nop;" /* flush i+d-TLBs */ \
+ "nop;" /* flush i+d-TLBs */ \
+ "nop;" /* flush i+d-TLBs */
+
+#define HAL_MMU_OFF() \
+CYG_MACRO_START \
+ asm volatile ( \
+ CYGARC_HAL_MMU_OFF() \
+ ); \
+CYG_MACRO_END
+
+#endif // ifndef CYGONCE_HAL_CACHE_H
+// End of hal_cache.h
--- /dev/null
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+
+/*=============================================================================
+//
+// hal_diag.h
+//
+// HAL Support for Kernel Diagnostic Routines
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+#include <cyg/hal/hal_if.h>
+
+#define HAL_DIAG_INIT() hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
+
+#else // everything by steam
+
+/*---------------------------------------------------------------------------*/
+/* functions implemented in hal_diag.c */
+
+externC void hal_diag_init(void);
+externC void hal_diag_write_char(char c);
+externC void hal_diag_read_char(char *c);
+
+/*---------------------------------------------------------------------------*/
+
+#define HAL_DIAG_INIT() hal_diag_init()
+
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_)
+
+#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_)
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
+// LED
+
+externC void hal_diag_led(int n);
+
+/*---------------------------------------------------------------------------*/
+/* end of hal_diag.h */
+#endif /* CYGONCE_HAL_DIAG_H */
--- /dev/null
+#ifndef CYGONCE_HAL_MM_H
+#define CYGONCE_HAL_MM_H
+
+//=============================================================================
+//
+// hal_mm.h
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+// -------------------------------------------------------------------------
+// MMU initialization:
+//
+// These structures are laid down in memory to define the translation
+// table.
+//
+
+/*
+ * Translation Table Base Bit Masks
+ */
+#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
+
+/*
+ * Domain Access Control Bit Masks
+ */
+#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2)
+
+struct ARM_MMU_FIRST_LEVEL_FAULT {
+ unsigned int id : 2;
+ unsigned int sbz : 30;
+};
+
+#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
+
+struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
+ unsigned int id : 2;
+ unsigned int imp : 2;
+ unsigned int domain : 4;
+ unsigned int sbz : 1;
+ unsigned int base_address : 23;
+};
+
+#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
+
+struct ARM_MMU_FIRST_LEVEL_SECTION {
+ unsigned int id : 2;
+ unsigned int b : 1;
+ unsigned int c : 1;
+ unsigned int imp : 1;
+ unsigned int domain : 4;
+ unsigned int sbz0 : 1;
+ unsigned int ap : 2;
+ unsigned int sbz1 : 8;
+ unsigned int base_address : 12;
+};
+
+#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
+
+struct ARM_MMU_FIRST_LEVEL_RESERVED {
+ unsigned int id : 2;
+ unsigned int sbz : 30;
+};
+
+#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
+
+#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
+ (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
+
+#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
+
+#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
+ cacheable, bufferable, perm) \
+ CYG_MACRO_START \
+ register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
+ \
+ desc.word = 0; \
+ desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
+ desc.section.domain = 0; \
+ desc.section.c = (cacheable); \
+ desc.section.b = (bufferable); \
+ desc.section.ap = (perm); \
+ desc.section.base_address = (actual_base); \
+ *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
+ = desc.word; \
+ CYG_MACRO_END
+
+#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \
+ { \
+ int i; int j = abase; int k = vbase; \
+ for (i = size; i > 0 ; i--,j++,k++) { \
+ ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
+ } \
+ }
+
+union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
+ unsigned long word;
+ struct ARM_MMU_FIRST_LEVEL_FAULT fault;
+ struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
+ struct ARM_MMU_FIRST_LEVEL_SECTION section;
+ struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
+};
+
+#define ARM_UNCACHEABLE 0
+#define ARM_CACHEABLE 1
+#define ARM_UNBUFFERABLE 0
+#define ARM_BUFFERABLE 1
+
+#define ARM_ACCESS_PERM_NONE_NONE 0
+#define ARM_ACCESS_PERM_RO_NONE 0
+#define ARM_ACCESS_PERM_RO_RO 0
+#define ARM_ACCESS_PERM_RW_NONE 1
+#define ARM_ACCESS_PERM_RW_RO 2
+#define ARM_ACCESS_PERM_RW_RW 3
+
+/*
+ * Initialization for the Domain Access Control Register
+ */
+#define ARM_ACCESS_DACR_DEFAULT ( \
+ ARM_ACCESS_TYPE_MANAGER(0) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(1) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(2) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(3) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(4) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(5) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(6) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(7) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(8) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(9) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(10) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(11) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(12) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(13) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(14) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(15) )
+
+// ------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_MM_H
+// End of hal_mm.h
+
+
+
+
+
--- /dev/null
+//==========================================================================
+//
+// hal_soc.h
+//
+// SoC chip definitions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#ifndef __HAL_SOC_H__
+#define __HAL_SOC_H__
+
+#ifdef __ASSEMBLER__
+
+#define REG8_VAL(a) (a)
+#define REG16_VAL(a) (a)
+#define REG32_VAL(a) (a)
+
+#define REG8_PTR(a) (a)
+#define REG16_PTR(a) (a)
+#define REG32_PTR(a) (a)
+
+#else /* __ASSEMBLER__ */
+
+extern char HAL_PLATFORM_EXTRA[];
+#define REG8_VAL(a) ((unsigned char)(a))
+#define REG16_VAL(a) ((unsigned short)(a))
+#define REG32_VAL(a) ((unsigned int)(a))
+
+#define REG8_PTR(a) ((volatile unsigned char *)(a))
+#define REG16_PTR(a) ((volatile unsigned short *)(a))
+#define REG32_PTR(a) ((volatile unsigned int *)(a))
+#define readb(a) (*(volatile unsigned char *)(a))
+#define readw(a) (*(volatile unsigned short *)(a))
+#define readl(a) (*(volatile unsigned int *)(a))
+#define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
+#define writew(v,a) (*(volatile unsigned short *)(a) = (v))
+#define writel(v,a) (*(volatile unsigned int *)(a) = (v))
+
+#endif /* __ASSEMBLER__ */
+
+/*
+ * Default Memory Layout Definitions
+ */
+
+/*
+ * UART Chip level Configuration that a user may not have to edit. These
+ * configuration vary depending on how the UART module is integrated with
+ * the ARM core
+ */
+#define MXC_UART_NR 3
+/*!
+ * This option is used to set or clear the RXDMUXSEL bit in control reg 3.
+ * Certain platforms need this bit to be set in order to receive Irda data.
+ */
+#define MXC_UART_IR_RXDMUX 0x0004
+/*!
+ * This option is used to set or clear the RXDMUXSEL bit in control reg 3.
+ * Certain platforms need this bit to be set in order to receive UART data.
+ */
+#define MXC_UART_RXDMUX 0x0004
+
+/*
+ * IRAM
+ */
+#define IRAM_BASE_ADDR 0x1FFE8000 /* 96K internal ram */
+
+/*
+ * ROM address
+ */
+#define ROM_BASE_ADDRESS 0x0
+#define ROM_BASE_ADDRESS_VIRT 0x20000000
+
+#define ROM_SI_REV_OFFSET 0x48
+
+/*
+ * NFC internal RAM
+ */
+#define NFC_BASE_ADDR_AXI 0xCFFF0000
+#define NFC_BASE NFC_BASE_ADDR_AXI
+
+#define PLATFORM_BASE_ADDR 0x83FA0000
+#define PLATFORM_ICGC 0x14
+/*
+ * Graphics Memory of GPU
+ */
+#define GPU_BASE_ADDR 0x20000000
+
+#define TZIC_BASE_ADDR 0x8FFFC000
+
+#define DEBUG_BASE_ADDR 0x60000000
+#define DEBUG_ROM_ADDR (DEBUG_BASE_ADDR + 0x0)
+#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
+#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
+#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
+#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
+#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
+#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
+#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
+#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
+
+/*
+ * SPBA global module enabled #0
+ */
+#define SPBA0_BASE_ADDR 0x70000000
+
+#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
+#define ESDHC1_REG_BASE MMC_SDHC1_BASE_ADDR
+#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
+#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
+//eCSPI1
+#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
+#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
+#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
+#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
+#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
+#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
+#define SLIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
+#define HSI2C_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
+#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
+
+/*!
+ * defines for SPBA modules
+ */
+#define SPBA_SDHC1 0x04
+#define SPBA_SDHC2 0x08
+#define SPBA_UART3 0x0C
+#define SPBA_CSPI1 0x10
+#define SPBA_SSI2 0x14
+#define SPBA_SDHC3 0x20
+#define SPBA_SDHC4 0x24
+#define SPBA_SPDIF 0x28
+#define SPBA_ATA 0x30
+#define SPBA_SLIM 0x34
+#define SPBA_HSI2C 0x38
+#define SPBA_CTRL 0x3C
+
+
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR 0x73F00000
+#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
+#define USBOH3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
+#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
+#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
+#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
+#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
+#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
+#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
+#define WDOG_BASE_ADDR WDOG1_BASE_ADDR
+#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
+#define GPT_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
+#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
+#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
+#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
+#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
+#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
+#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
+#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
+#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
+#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
+#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
+#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
+
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR 0x83F00000
+#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
+#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
+#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
+#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
+#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
+#define MAX_BASE_ADDR AHBMAX_BASE_ADDR
+#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
+#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
+#define ARM_ELBOW_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
+#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
+#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
+// eCSPI2
+#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
+#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
+#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
+#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
+#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
+// actually cspi1
+#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
+#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
+#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
+#define I2C_BASE_ADDR I2C1_BASE_ADDR
+#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
+#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
+#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
+#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
+#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
+#define NFC_IP_BASE (AIPS2_BASE_ADDR + 0x000DB000)
+#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
+#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
+#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
+#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
+#define SSI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
+#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
+#define SOC_FEC_BASE FEC_BASE_ADDR
+#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
+#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
+#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
+
+/*
+ * Memory regions and CS
+ */
+#define GPU_CTRL_BASE_ADDR 0x30000000
+#define IPU_CTRL_BASE_ADDR 0x40000000
+#define CSD0_BASE_ADDR 0x90000000
+#define CSD1_BASE_ADDR 0xA0000000
+#define CS0_BASE_ADDR 0xB0000000
+#define CS1_BASE_ADDR 0xB8000000
+#define CS2_BASE_ADDR 0xC0000000
+#define CS3_BASE_ADDR 0xC8000000
+#define CS4_BASE_ADDR 0xCC000000
+#define CS5_BASE_ADDR 0xCE000000
+
+/*
+ * DMA request assignments
+ */
+#define DMA_REQ_SSI3_TX1 47
+#define DMA_REQ_SSI3_RX1 46
+#define DMA_REQ_SPDIF 45
+#define DMA_REQ_UART3_TX 44
+#define DMA_REQ_UART3_RX 43
+#define DMA_REQ_SLIM_B_TX 42
+#define DMA_REQ_SDHC4 41
+#define DMA_REQ_SDHC3 40
+#define DMA_REQ_CSPI_TX 39
+#define DMA_REQ_CSPI_RX 38
+#define DMA_REQ_SSI3_TX2 37
+#define DMA_REQ_IPU 36
+#define DMA_REQ_SSI3_RX2 35
+#define DMA_REQ_EPIT2 34
+#define DMA_REQ_CTI2_1 33
+#define DMA_REQ_EMI_WR 32
+#define DMA_REQ_CTI2_0 31
+#define DMA_REQ_EMI_RD 30
+#define DMA_REQ_SSI1_TX1 29
+#define DMA_REQ_SSI1_RX1 28
+#define DMA_REQ_SSI1_TX2 27
+#define DMA_REQ_SSI1_RX2 26
+#define DMA_REQ_SSI2_TX1 25
+#define DMA_REQ_SSI2_RX1 24
+#define DMA_REQ_SSI2_TX2 23
+#define DMA_REQ_SSI2_RX2 22
+#define DMA_REQ_SDHC2_I2C2 21
+#define DMA_REQ_SDHC1_I2C1 20
+#define DMA_REQ_UART1_TX 19
+#define DMA_REQ_UART1_RX 18
+#define DMA_REQ_UART2_TX 17
+#define DMA_REQ_UART2_RX 16
+#define DMA_REQ_GPU_GPIO1_0 15
+#define DMA_REQ_GPIO1_1 14
+#define DMA_REQ_FIRI_TX 13
+#define DMA_REQ_FIRI_RX 12
+#define DMA_REQ_HS_I2C_RX 11
+#define DMA_REQ_HS_I2C_TX 10
+#define DMA_REQ_CSPI2_TX 9
+#define DMA_REQ_CSPI2_RX 8
+#define DMA_REQ_CSPI1_TX 7
+#define DMA_REQ_CSPI1_RX 6
+#define DMA_REQ_SLIM_B 5
+#define DMA_REQ_ATA_TX_END 4
+#define DMA_REQ_ATA_TX 3
+#define DMA_REQ_ATA_RX 2
+#define DMA_REQ_GPC 1
+#define DMA_REQ_VPU 0
+
+/*
+ * Interrupt numbers
+ */
+#define MXC_INT_BASE 0
+#define MXC_INT_RESV0 0
+#define MXC_INT_MMC_SDHC1 1
+#define MXC_INT_MMC_SDHC2 2
+#define MXC_INT_MMC_SDHC3 3
+#define MXC_INT_MMC_SDHC4 4
+#define MXC_INT_RESV5 5
+#define MXC_INT_SDMA 6
+#define MXC_INT_IOMUX 7
+#define MXC_INT_NFC 8
+#define MXC_INT_VPU 9
+#define MXC_INT_IPU_ERR 10
+#define MXC_INT_IPU_SYN 11
+#define MXC_INT_GPU 12
+#define MXC_INT_RESV13 13
+#define MXC_INT_USB_H1 14
+#define MXC_INT_EMI 15
+#define MXC_INT_USB_H2 16
+#define MXC_INT_USB_H3 17
+#define MXC_INT_USB_OTG 18
+#define MXC_INT_SAHARA_H0 19
+#define MXC_INT_SAHARA_H1 20
+#define MXC_INT_SCC_SMN 21
+#define MXC_INT_SCC_STZ 22
+#define MXC_INT_SCC_SCM 23
+#define MXC_INT_SRTC_NTZ 24
+#define MXC_INT_SRTC_TZ 25
+#define MXC_INT_RTIC 26
+#define MXC_INT_CSU 27
+#define MXC_INT_SLIM_B 28
+#define MXC_INT_SSI1 29
+#define MXC_INT_SSI2 30
+#define MXC_INT_UART1 31
+#define MXC_INT_UART2 32
+#define MXC_INT_UART3 33
+#define MXC_INT_RESV34 34
+#define MXC_INT_RESV35 35
+#define MXC_INT_CSPI1 36
+#define MXC_INT_CSPI2 37
+#define MXC_INT_CSPI 38
+#define MXC_INT_GPT 39
+#define MXC_INT_EPIT1 40
+#define MXC_INT_EPIT2 41
+#define MXC_INT_GPIO1_INT7 42
+#define MXC_INT_GPIO1_INT6 43
+#define MXC_INT_GPIO1_INT5 44
+#define MXC_INT_GPIO1_INT4 45
+#define MXC_INT_GPIO1_INT3 46
+#define MXC_INT_GPIO1_INT2 47
+#define MXC_INT_GPIO1_INT1 48
+#define MXC_INT_GPIO1_INT0 49
+#define MXC_INT_GPIO1_LOW 50
+#define MXC_INT_GPIO1_HIGH 51
+#define MXC_INT_GPIO2_LOW 52
+#define MXC_INT_GPIO2_HIGH 53
+#define MXC_INT_GPIO3_LOW 54
+#define MXC_INT_GPIO3_HIGH 55
+#define MXC_INT_GPIO4_LOW 56
+#define MXC_INT_GPIO4_HIGH 57
+#define MXC_INT_WDOG1 58
+#define MXC_INT_WDOG2 59
+#define MXC_INT_KPP 60
+#define MXC_INT_PWM1 61
+#define MXC_INT_I2C1 62
+#define MXC_INT_I2C2 63
+#define MXC_INT_HS_I2C 64
+#define MXC_INT_RESV65 65
+#define MXC_INT_RESV66 66
+#define MXC_INT_SIM_IPB 67
+#define MXC_INT_SIM_DAT 68
+#define MXC_INT_IIM 69
+#define MXC_INT_ATA 70
+#define MXC_INT_CCM1 71
+#define MXC_INT_CCM2 72
+#define MXC_INT_GPC1 73
+#define MXC_INT_GPC2 74
+#define MXC_INT_SRC 75
+#define MXC_INT_NM 76
+#define MXC_INT_PMU 77
+#define MXC_INT_CTI_IRQ 78
+#define MXC_INT_CTI1_TG0 79
+#define MXC_INT_CTI1_TG1 80
+#define MXC_INT_MCG_ERR 81
+#define MXC_INT_MCG_TMR 82
+#define MXC_INT_MCG_FUNC 83
+#define MXC_INT_RESV84 84
+#define MXC_INT_RESV85 85
+#define MXC_INT_RESV86 86
+#define MXC_INT_FEC 87
+#define MXC_INT_OWIRE 88
+#define MXC_INT_CTI1_TG2 89
+#define MXC_INT_SJC 90
+#define MXC_INT_SPDIF 91
+#define MXC_INT_TVE 92
+#define MXC_INT_FIFI 93
+#define MXC_INT_PWM2 94
+#define MXC_INT_SLIM_EXP 95
+#define MXC_INT_SSI3 96
+#define MXC_INT_RESV97 97
+#define MXC_INT_CTI1_TG3 98
+#define MXC_INT_SMC_RX 99
+#define MXC_INT_VPU_IDLE 100
+#define MXC_INT_RESV101 101
+#define MXC_INT_GPU_IDLE 102
+
+/*!
+ * Number of GPIO port as defined in the IC Spec
+ */
+#define GPIO_PORT_NUM 4
+/*!
+ * Number of GPIO pins per port
+ */
+#define GPIO_NUM_PIN 32
+
+/* CCM */
+#define CLKCTL_CCR 0x00
+#define CLKCTL_CCDR 0x04
+#define CLKCTL_CSR 0x08
+#define CLKCTL_CCSR 0x0C
+#define CLKCTL_CACRR 0x10
+#define CLKCTL_CBCDR 0x14
+#define CLKCTL_CBCMR 0x18
+#define CLKCTL_CSCMR1 0x1C
+#define CLKCTL_CSCMR2 0x20
+#define CLKCTL_CSCDR1 0x24
+#define CLKCTL_CS1CDR 0x28
+#define CLKCTL_CS2CDR 0x2C
+#define CLKCTL_CDCDR 0x30
+#define CLKCTL_CHSCCDR 0x34
+#define CLKCTL_CSCDR2 0x38
+#define CLKCTL_CSCDR3 0x3C
+#define CLKCTL_CSCDR4 0x40
+#define CLKCTL_CWDR 0x44
+#define CLKCTL_CDHIPR 0x48
+#define CLKCTL_CDCR 0x4C
+#define CLKCTL_CTOR 0x50
+#define CLKCTL_CLPCR 0x54
+#define CLKCTL_CISR 0x58
+#define CLKCTL_CIMR 0x5C
+#define CLKCTL_CCOSR 0x60
+#define CLKCTL_CGPR 0x64
+#define CLKCTL_CCGR0 0x68
+#define CLKCTL_CCGR1 0x6C
+#define CLKCTL_CCGR2 0x70
+#define CLKCTL_CCGR3 0x74
+#define CLKCTL_CCGR4 0x78
+#define CLKCTL_CCGR5 0x7C
+#define CLKCTL_CMEOR 0x84
+
+#define FREQ_24MHZ 24000000
+#define FREQ_32768HZ (32768 * 1024)
+#define FREQ_38400HZ (38400 * 1024)
+#define FREQ_32000HZ (32000 * 1024)
+#define PLL_REF_CLK FREQ_24MHZ
+#define CKIH 22579200
+//#define PLL_REF_CLK FREQ_32768HZ
+//#define PLL_REF_CLK FREQ_32000HZ
+
+/* WEIM registers */
+#define CSGCR1 0x00
+#define CSGCR2 0x04
+#define CSRCR1 0x08
+#define CSRCR2 0x0C
+#define CSWCR1 0x10
+
+/* M4IF */
+#define M4IF_FBPM0 0x40
+#define M4IF_FIDBP 0x48
+#define M4IF_MIF4 0x48
+
+/* ESDCTL */
+#define ESDCTL_ESDCTL0 0x00
+#define ESDCTL_ESDCFG0 0x04
+#define ESDCTL_ESDCTL1 0x08
+#define ESDCTL_ESDCFG1 0x0C
+#define ESDCTL_ESDMISC 0x10
+#define ESDCTL_ESDSCR 0x14
+#define ESDCTL_ESDCDLY1 0x20
+#define ESDCTL_ESDCDLY2 0x24
+#define ESDCTL_ESDCDLY3 0x28
+#define ESDCTL_ESDCDLY4 0x2C
+#define ESDCTL_ESDCDLY5 0x30
+#define ESDCTL_ESDCDLYGD 0x34
+
+/* DPLL */
+#define PLL_DP_CTL 0x00
+#define PLL_DP_CONFIG 0x04
+#define PLL_DP_OP 0x08
+#define PLL_DP_MFD 0x0C
+#define PLL_DP_MFN 0x10
+#define PLL_DP_MFNMINUS 0x14
+#define PLL_DP_MFNPLUS 0x18
+#define PLL_DP_HFS_OP 0x1C
+#define PLL_DP_HFS_MFD 0x20
+#define PLL_DP_HFS_MFN 0x24
+#define PLL_DP_TOGC 0x28
+#define PLL_DP_DESTAT 0x2C
+
+#define CHIP_REV_1_0 0x0 /* PASS 1.0 */
+#define CHIP_REV_1_1 0x1 /* PASS 1.1 */
+#define CHIP_REV_2_0 0x2 /* PASS 2.0 */
+#define CHIP_LATEST CHIP_REV_1_1
+
+#define IIM_STAT_OFF 0x00
+#define IIM_STAT_BUSY (1 << 7)
+#define IIM_STAT_PRGD (1 << 1)
+#define IIM_STAT_SNSD (1 << 0)
+#define IIM_STATM_OFF 0x04
+#define IIM_ERR_OFF 0x08
+#define IIM_ERR_PRGE (1 << 7)
+#define IIM_ERR_WPE (1 << 6)
+#define IIM_ERR_OPE (1 << 5)
+#define IIM_ERR_RPE (1 << 4)
+#define IIM_ERR_WLRE (1 << 3)
+#define IIM_ERR_SNSE (1 << 2)
+#define IIM_ERR_PARITYE (1 << 1)
+#define IIM_EMASK_OFF 0x0C
+#define IIM_FCTL_OFF 0x10
+#define IIM_UA_OFF 0x14
+#define IIM_LA_OFF 0x18
+#define IIM_SDAT_OFF 0x1C
+#define IIM_PREV_OFF 0x20
+#define IIM_SREV_OFF 0x24
+#define IIM_PREG_P_OFF 0x28
+#define IIM_SCS0_OFF 0x2C
+#define IIM_SCS1_P_OFF 0x30
+#define IIM_SCS2_OFF 0x34
+#define IIM_SCS3_P_OFF 0x38
+
+#define IIM_PROD_REV_SH 3
+#define IIM_PROD_REV_LEN 5
+#define IIM_SREV_REV_SH 4
+#define IIM_SREV_REV_LEN 4
+#define PROD_SIGNATURE_MX51 0x1
+
+#define EPIT_BASE_ADDR EPIT1_BASE_ADDR
+#define EPITCR 0x00
+#define EPITSR 0x04
+#define EPITLR 0x08
+#define EPITCMPR 0x0C
+#define EPITCNR 0x10
+
+#define GPTCR 0x00
+#define GPTPR 0x04
+#define GPTSR 0x08
+#define GPTIR 0x0C
+#define GPTOCR1 0x10
+#define GPTOCR2 0x14
+#define GPTOCR3 0x18
+#define GPTICR1 0x1C
+#define GPTICR2 0x20
+#define GPTCNT 0x24
+
+/* Assuming 24MHz input clock with doubler ON */
+/* MFI PDF */
+#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
+#define DP_MFD_850 (48 - 1)
+#define DP_MFN_850 41
+
+#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
+#define DP_MFD_800 (3 - 1)
+#define DP_MFN_800 1
+
+#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
+#define DP_MFD_700 (24 - 1)
+#define DP_MFN_700 7
+
+#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
+#define DP_MFD_400 (3 - 1)
+#define DP_MFN_400 1
+
+#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
+#define DP_MFD_532 (24 - 1)
+#define DP_MFN_532 13
+
+#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
+#define DP_MFD_665 (96 - 1)
+#define DP_MFN_665 89
+
+#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
+#define DP_MFD_216 (4 - 1)
+#define DP_MFN_216 3
+
+#define PROD_SIGNATURE_SUPPORTED PROD_SIGNATURE_MX51
+
+#define CHIP_VERSION_NONE 0xFFFFFFFF // invalid product ID
+#define CHIP_VERSION_UNKNOWN 0xDEADBEEF // invalid chip rev
+
+#define PART_NUMBER_OFFSET (12)
+#define MAJOR_NUMBER_OFFSET (4)
+#define MINOR_NUMBER_OFFSET (0)
+
+/* IOMUX defines */
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B (IOMUXC_BASE_ADDR + 0x108) // 0x108
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B (IOMUXC_BASE_ADDR + 0x10C) // 0x10c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE (IOMUXC_BASE_ADDR + 0x110) // 0x110
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE (IOMUXC_BASE_ADDR + 0x114) // 0x114
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B (IOMUXC_BASE_ADDR + 0x118) // 0x118
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0 (IOMUXC_BASE_ADDR + 0x11C) // 0x11c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1 (IOMUXC_BASE_ADDR + 0x120) // 0x120
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB2 (IOMUXC_BASE_ADDR + 0x124) // 0x124
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB3 (IOMUXC_BASE_ADDR + 0x128) // 0x128
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB4 (IOMUXC_BASE_ADDR + 0x12C) // 0x12c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB5 (IOMUXC_BASE_ADDR + 0x130) // 0x130
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB6 (IOMUXC_BASE_ADDR + 0x134) // 0x134
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB7 (IOMUXC_BASE_ADDR + 0x138) // 0x138
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS0 (IOMUXC_BASE_ADDR + 0x13C) // 0x13c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS1 (IOMUXC_BASE_ADDR + 0x140) // 0x140
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2 (IOMUXC_BASE_ADDR + 0x144) // 0x144
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3 (IOMUXC_BASE_ADDR + 0x148) // 0x148
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4 (IOMUXC_BASE_ADDR + 0x14C) // 0x14c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5 (IOMUXC_BASE_ADDR + 0x150) // 0x150
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6 (IOMUXC_BASE_ADDR + 0x154) // 0x154
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7 (IOMUXC_BASE_ADDR + 0x158) // 0x158
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT (IOMUXC_BASE_ADDR + 0x15C) // 0x15c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D15 (IOMUXC_BASE_ADDR + 0x160) // 0x160
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D14 (IOMUXC_BASE_ADDR + 0x164) // 0x164
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D13 (IOMUXC_BASE_ADDR + 0x168) // 0x168
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D12 (IOMUXC_BASE_ADDR + 0x16C) // 0x16c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D11 (IOMUXC_BASE_ADDR + 0x170) // 0x170
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D10 (IOMUXC_BASE_ADDR + 0x174) // 0x174
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D9 (IOMUXC_BASE_ADDR + 0x178) // 0x178
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D8 (IOMUXC_BASE_ADDR + 0x17C) // 0x17c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D7 (IOMUXC_BASE_ADDR + 0x180) // 0x180
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D6 (IOMUXC_BASE_ADDR + 0x184) // 0x184
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D5 (IOMUXC_BASE_ADDR + 0x188) // 0x188
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D4 (IOMUXC_BASE_ADDR + 0x18C) // 0x18c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D3 (IOMUXC_BASE_ADDR + 0x190) // 0x190
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D2 (IOMUXC_BASE_ADDR + 0x194) // 0x194
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D1 (IOMUXC_BASE_ADDR + 0x198) // 0x198
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D0 (IOMUXC_BASE_ADDR + 0x19C) // 0x19c
+
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B (IOMUXC_BASE_ADDR + 0x5B0) // 0x5b0
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B (IOMUXC_BASE_ADDR + 0x5B4) // 0x5b4
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE (IOMUXC_BASE_ADDR + 0x5B8) // 0x5b8
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE (IOMUXC_BASE_ADDR + 0x5BC) // 0x5bc
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B (IOMUXC_BASE_ADDR + 0x5C0) // 0x5c0
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0 (IOMUXC_BASE_ADDR + 0x5C4) // 0x5c4
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1 (IOMUXC_BASE_ADDR + 0x5C8) // 0x5c8
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB2 (IOMUXC_BASE_ADDR + 0x5CC) // 0x5cc
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB3 (IOMUXC_BASE_ADDR + 0x5D0) // 0x5d0
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB4 (IOMUXC_BASE_ADDR + 0x5D4) // 0x5d4
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB5 (IOMUXC_BASE_ADDR + 0x5D8) // 0x5d8
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB6 (IOMUXC_BASE_ADDR + 0x5DC) // 0x5dc
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB7 (IOMUXC_BASE_ADDR + 0x5E0) // 0x5e0
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS0 (IOMUXC_BASE_ADDR + 0x5E4) // 0x5e4
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS1 (IOMUXC_BASE_ADDR + 0x5E8) // 0x5e8
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2 (IOMUXC_BASE_ADDR + 0x5EC) // 0x5ec
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3 (IOMUXC_BASE_ADDR + 0x5F0) // 0x5f0
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4 (IOMUXC_BASE_ADDR + 0x5F4) // 0x5f4
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5 (IOMUXC_BASE_ADDR + 0x5F8) // 0x5f8
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6 (IOMUXC_BASE_ADDR + 0x5FC) // 0x5fc
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS7 (IOMUXC_BASE_ADDR + 0x600) // 0x600
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RDY_INT (IOMUXC_BASE_ADDR + 0x604) // 0x604
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D15 (IOMUXC_BASE_ADDR + 0x608) // 0x608
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D14 (IOMUXC_BASE_ADDR + 0x60C) // 0x60c
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D13 (IOMUXC_BASE_ADDR + 0x610) // 0x610
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D12 (IOMUXC_BASE_ADDR + 0x614) // 0x614
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D11 (IOMUXC_BASE_ADDR + 0x618) // 0x618
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D10 (IOMUXC_BASE_ADDR + 0x61C) // 0x61c
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D9 (IOMUXC_BASE_ADDR + 0x620) // 0x620
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D8 (IOMUXC_BASE_ADDR + 0x624) // 0x624
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D7 (IOMUXC_BASE_ADDR + 0x628) // 0x628
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D6 (IOMUXC_BASE_ADDR + 0x62C) // 0x62c
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D5 (IOMUXC_BASE_ADDR + 0x630) // 0x630
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D4 (IOMUXC_BASE_ADDR + 0x634) // 0x634
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D3 (IOMUXC_BASE_ADDR + 0x638) // 0x638
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D2 (IOMUXC_BASE_ADDR + 0x63C) // 0x63c
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D1 (IOMUXC_BASE_ADDR + 0x640) // 0x640
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D0 (IOMUXC_BASE_ADDR + 0x644) // 0x644
+
+
+//#define BARKER_CODE_SWAP_LOC 0x404
+#define BARKER_CODE_VAL 0xB1
+#define NFC_V3_0 0x30
+// This defines the register base for the NAND AXI registers
+#define NAND_REG_BASE (NFC_BASE_ADDR_AXI + 0x1E00)
+
+#define NAND_CMD_REG (NAND_REG_BASE + 0x00)
+#define NAND_ADD0_REG (NAND_REG_BASE + 0x04)
+#define NAND_ADD1_REG (NAND_REG_BASE + 0x08)
+#define NAND_ADD2_REG (NAND_REG_BASE + 0x0C)
+#define NAND_ADD3_REG (NAND_REG_BASE + 0x10)
+#define NAND_ADD4_REG (NAND_REG_BASE + 0x14)
+#define NAND_ADD5_REG (NAND_REG_BASE + 0x18)
+#define NAND_ADD6_REG (NAND_REG_BASE + 0x1C)
+#define NAND_ADD7_REG (NAND_REG_BASE + 0x20)
+#define NAND_ADD8_REG (NAND_REG_BASE + 0x24)
+#define NAND_ADD9_REG (NAND_REG_BASE + 0x28)
+#define NAND_ADD10_REG (NAND_REG_BASE + 0x2C)
+#define NAND_ADD11_REG (NAND_REG_BASE + 0x30)
+
+#define NAND_CONFIGURATION1_REG (NAND_REG_BASE + 0x34)
+#define NAND_CONFIGURATION1_NFC_RST (1 << 2)
+#define NAND_CONFIGURATION1_NF_CE (1 << 1)
+#define NAND_CONFIGURATION1_SP_EN (1 << 0)
+
+#define NAND_ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x38)
+
+#define NAND_STATUS_SUM_REG (NAND_REG_BASE + 0x3C)
+
+#define NAND_LAUNCH_REG (NAND_REG_BASE + 0x40)
+#define NAND_LAUNCH_FCMD (1 << 0)
+#define NAND_LAUNCH_FADD (1 << 1)
+#define NAND_LAUNCH_FDI (1 << 2)
+#define NAND_LAUNCH_AUTO_PROG (1 << 6)
+#define NAND_LAUNCH_AUTO_READ (1 << 7)
+#define NAND_LAUNCH_AUTO_READ_CONT (1 << 8)
+#define NAND_LAUNCH_AUTO_ERASE (1 << 9)
+#define NAND_LAUNCH_COPY_BACK0 (1 << 10)
+#define NAND_LAUNCH_COPY_BACK1 (1 << 11)
+#define NAND_LAUNCH_AUTO_STAT (1 << 12)
+
+#define NFC_WR_PROT_REG (NFC_IP_BASE + 0x00)
+#define UNLOCK_BLK_ADD0_REG (NFC_IP_BASE + 0x04)
+#define UNLOCK_BLK_ADD1_REG (NFC_IP_BASE + 0x08)
+#define UNLOCK_BLK_ADD2_REG (NFC_IP_BASE + 0x0C)
+#define UNLOCK_BLK_ADD3_REG (NFC_IP_BASE + 0x10)
+#define UNLOCK_BLK_ADD4_REG (NFC_IP_BASE + 0x14)
+#define UNLOCK_BLK_ADD5_REG (NFC_IP_BASE + 0x18)
+#define UNLOCK_BLK_ADD6_REG (NFC_IP_BASE + 0x1C)
+#define UNLOCK_BLK_ADD7_REG (NFC_IP_BASE + 0x20)
+
+#define NFC_FLASH_CONFIG2_REG (NFC_IP_BASE + 0x24)
+#define NFC_FLASH_CONFIG2_ECC_EN (1 << 3)
+
+#define NFC_FLASH_CONFIG3_REG (NFC_IP_BASE + 0x28)
+
+#define NFC_IPC_REG (NFC_IP_BASE + 0x2C)
+#define NFC_IPC_INT (1 << 31)
+#define NFC_IPC_AUTO_DONE (1 << 30)
+#define NFC_IPC_LPS (1 << 29)
+#define NFC_IPC_RB_B (1 << 28)
+#define NFC_IPC_CACK (1 << 1)
+#define NFC_IPC_CREQ (1 << 0)
+#define NFC_AXI_ERR_ADD_REG (NFC_IP_BASE + 0x30)
+
+#define MXC_MMC_BASE_DUMMY 0x00000000
+
+#define NAND_FLASH_BOOT 0x10000000
+#define FROM_NAND_FLASH NAND_FLASH_BOOT
+
+#define SDRAM_NON_FLASH_BOOT 0x20000000
+
+#define MMC_FLASH_BOOT 0x40000000
+#define FROM_MMC_FLASH MMC_FLASH_BOOT
+
+#define SPI_NOR_FLASH_BOOT 0x80000000
+#define FROM_SPI_NOR_FLASH SPI_NOR_FLASH_BOOT
+
+#define IS_BOOTING_FROM_NAND() (0)
+#define IS_BOOTING_FROM_SPI_NOR() (0)
+#define IS_BOOTING_FROM_NOR() (0)
+#define IS_BOOTING_FROM_SDRAM() (0)
+#define IS_BOOTING_FROM_MMC() (0)
+
+#ifndef MXCFLASH_SELECT_NAND
+#define IS_FIS_FROM_NAND() 0
+#else
+#define IS_FIS_FROM_NAND() (_mxc_fis == FROM_NAND_FLASH)
+#endif
+
+#ifndef MXCFLASH_SELECT_MMC
+#define IS_FIS_FROM_MMC() 0
+#else
+#define IS_FIS_FROM_MMC() (_mxc_fis == FROM_MMC_FLASH)
+#endif
+
+#define IS_FIS_FROM_SPI_NOR() (_mxc_fis == FROM_SPI_NOR_FLASH)
+
+#define IS_FIS_FROM_NOR() 0
+
+/*
+ * This macro is used to get certain bit field from a number
+ */
+#define MXC_GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1))
+
+/*
+ * This macro is used to set certain bit field inside a number
+ */
+#define MXC_SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
+
+#define L2CC_ENABLED
+#define UART_WIDTH_32 /* internal UART is 32bit access only */
+
+#if !defined(__ASSEMBLER__)
+void cyg_hal_plf_serial_init(void);
+void cyg_hal_plf_serial_stop(void);
+void hal_delay_us(unsigned int usecs);
+#define HAL_DELAY_US(n) hal_delay_us(n)
+extern int _mxc_fis;
+extern unsigned int system_rev;
+
+enum plls {
+ PLL1,
+ PLL2,
+ PLL3,
+};
+
+enum main_clocks {
+ CPU_CLK,
+ AHB_CLK,
+ IPG_CLK,
+ IPG_PER_CLK,
+ DDR_CLK,
+ NFC_CLK,
+ USB_CLK,
+};
+
+enum peri_clocks {
+ UART1_BAUD,
+ UART2_BAUD,
+ UART3_BAUD,
+ SSI1_BAUD,
+ SSI2_BAUD,
+ CSI_BAUD,
+ MSTICK1_CLK,
+ MSTICK2_CLK,
+ SPI1_CLK = CSPI1_BASE_ADDR,
+ SPI2_CLK = CSPI2_BASE_ADDR,
+};
+
+unsigned int pll_clock(enum plls pll);
+
+unsigned int get_main_clock(enum main_clocks clk);
+
+unsigned int get_peri_clock(enum peri_clocks clk);
+
+typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
+
+#endif //#if !defined(__ASSEMBLER__)
+
+#endif /* __HAL_SOC_H__ */
--- /dev/null
+#ifndef CYGONCE_HAL_VAR_INTS_H
+#define CYGONCE_HAL_VAR_INTS_H
+//==========================================================================
+//
+// hal_var_ints.h
+//
+// HAL Interrupt and clock support
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+
+#include <cyg/hal/hal_soc.h> // registers
+
+#define CYGNUM_HAL_INTERRUPT_GPIO0 0
+#define CYGNUM_HAL_INTERRUPT_GPIO1 1
+#define CYGNUM_HAL_INTERRUPT_GPIO2 2
+#define CYGNUM_HAL_INTERRUPT_GPIO3 3
+#define CYGNUM_HAL_INTERRUPT_GPIO4 4
+#define CYGNUM_HAL_INTERRUPT_GPIO5 5
+#define CYGNUM_HAL_INTERRUPT_GPIO6 6
+#define CYGNUM_HAL_INTERRUPT_GPIO7 7
+#define CYGNUM_HAL_INTERRUPT_GPIO8 8
+#define CYGNUM_HAL_INTERRUPT_GPIO9 9
+#define CYGNUM_HAL_INTERRUPT_GPIO10 10
+#define CYGNUM_HAL_INTERRUPT_GPIO 11 // Don't use directly!
+#define CYGNUM_HAL_INTERRUPT_LCD 12
+#define CYGNUM_HAL_INTERRUPT_UDC 13
+#define CYGNUM_HAL_INTERRUPT_UART1 15
+#define CYGNUM_HAL_INTERRUPT_UART2 16
+#define CYGNUM_HAL_INTERRUPT_UART3 17
+#define CYGNUM_HAL_INTERRUPT_UART4 17
+#define CYGNUM_HAL_INTERRUPT_MCP 18
+#define CYGNUM_HAL_INTERRUPT_SSP 19
+#define CYGNUM_HAL_INTERRUPT_TIMER0 26
+#define CYGNUM_HAL_INTERRUPT_TIMER1 27
+#define CYGNUM_HAL_INTERRUPT_TIMER2 28
+#define CYGNUM_HAL_INTERRUPT_TIMER3 29
+#define CYGNUM_HAL_INTERRUPT_HZ 30
+#define CYGNUM_HAL_INTERRUPT_ALARM 31
+
+// GPIO bits 31..11 can generate interrupts as well, but they all
+// end up clumped into interrupt signal #11. Using the symbols
+// below allow for detection of these separately.
+
+#define CYGNUM_HAL_INTERRUPT_GPIO11 (32+11)
+#define CYGNUM_HAL_INTERRUPT_GPIO12 (32+12)
+#define CYGNUM_HAL_INTERRUPT_GPIO13 (32+13)
+#define CYGNUM_HAL_INTERRUPT_GPIO14 (32+14)
+#define CYGNUM_HAL_INTERRUPT_GPIO15 (32+15)
+#define CYGNUM_HAL_INTERRUPT_GPIO16 (32+16)
+#define CYGNUM_HAL_INTERRUPT_GPIO17 (32+17)
+#define CYGNUM_HAL_INTERRUPT_GPIO18 (32+18)
+#define CYGNUM_HAL_INTERRUPT_GPIO19 (32+19)
+#define CYGNUM_HAL_INTERRUPT_GPIO20 (32+20)
+#define CYGNUM_HAL_INTERRUPT_GPIO21 (32+21)
+#define CYGNUM_HAL_INTERRUPT_GPIO22 (32+22)
+#define CYGNUM_HAL_INTERRUPT_GPIO23 (32+23)
+#define CYGNUM_HAL_INTERRUPT_GPIO24 (32+24)
+#define CYGNUM_HAL_INTERRUPT_GPIO25 (32+25)
+#define CYGNUM_HAL_INTERRUPT_GPIO26 (32+26)
+#define CYGNUM_HAL_INTERRUPT_GPIO27 (32+27)
+
+#define CYGNUM_HAL_INTERRUPT_NONE -1
+
+#define CYGNUM_HAL_ISR_MIN 0
+#define CYGNUM_HAL_ISR_MAX (27+32)
+
+#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1)
+
+// The vector used by the Real time clock
+#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0
+
+// The vector used by the Ethernet
+#define CYGNUM_HAL_INTERRUPT_ETH CYGNUM_HAL_INTERRUPT_GPIO0
+
+// method for reading clock interrupt latency
+#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
+externC void hal_clock_latency(cyg_uint32 *);
+# define HAL_CLOCK_LATENCY( _pvalue_ ) \
+ hal_clock_latency( (cyg_uint32 *)(_pvalue_) )
+#endif
+
+//----------------------------------------------------------------------------
+// Reset.
+#define HAL_PLATFORM_RESET() \
+ CYG_MACRO_START \
+ writel(readl(NFC_FLASH_CONFIG3_REG) & ~0x73, NFC_FLASH_CONFIG3_REG); \
+ *(volatile unsigned short *)WDOG_BASE_ADDR |= 0x4; \
+ /* hang here forever if reset fails */ \
+ while (1){} \
+ CYG_MACRO_END
+
+// Fallback (never really used)
+#define HAL_PLATFORM_RESET_ENTRY 0x00000000
+
+#endif // CYGONCE_HAL_VAR_INTS_H
--- /dev/null
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+// plf_stub.h
+//
+// Platform header for GDB stub support.
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM
+
+#include <cyg/hal/hal_soc.h> // registers
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_intr.h> // Interrupt macros
+#include <cyg/hal/arm_stub.h> // architecture stub support
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init()
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
--- /dev/null
+#ifndef CYGONCE_VAR_IO_H
+#define CYGONCE_VAR_IO_H
+
+//=============================================================================
+//
+// var_io.h
+//
+// Variant specific IO support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/hal/plf_io.h> // Platform specifics
+
+//-----------------------------------------------------------------------------
+
+// Memory mapping details
+#ifndef CYGARC_PHYSICAL_ADDRESS
+#define CYGARC_PHYSICAL_ADDRESS(x) (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK0_BASE)
+#endif
+
+//-----------------------------------------------------------------------------
+// end of var_io.h
+#endif // CYGONCE_VAR_IO_H
--- /dev/null
+//==========================================================================
+//
+// cmds.c
+//
+// SoC [platform] specific RedBoot commands
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+#include <redboot.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/plf_mmap.h>
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/hal_cache.h>
+
+int gcd(int m, int n);
+
+typedef unsigned long long u64;
+typedef unsigned int u32;
+typedef unsigned short u16;
+typedef unsigned char u8;
+
+#define SZ_DEC_1M 1000000
+#define PLL_PD_MAX 16 //actual pd+1
+#define PLL_MFI_MAX 15
+#define PLL_MFI_MIN 5
+#define ARM_DIV_MAX 8
+#define IPG_DIV_MAX 4
+#define AHB_DIV_MAX 8
+#define EMI_DIV_MAX 8
+#define NFC_DIV_MAX 8
+
+#define REF_IN_CLK_NUM 4
+struct fixed_pll_mfd {
+ u32 ref_clk_hz;
+ u32 mfd;
+};
+const struct fixed_pll_mfd fixed_mfd[REF_IN_CLK_NUM] = {
+ {0, 0}, // reserved
+ {0, 0}, // reserved
+ {FREQ_24MHZ, 24 * 16}, // 384
+ {0, 0}, // reserved
+};
+
+struct pll_param {
+ u32 pd;
+ u32 mfi;
+ u32 mfn;
+ u32 mfd;
+};
+
+#define PLL_FREQ_MAX(_ref_clk_) (4 * _ref_clk_ * PLL_MFI_MAX)
+#define PLL_FREQ_MIN(_ref_clk_) ((2 * _ref_clk_ * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
+#define MAX_DDR_CLK 200000000
+#define AHB_CLK_MAX 133333333
+#define IPG_CLK_MAX (AHB_CLK_MAX / 2)
+#define NFC_CLK_MAX 25000000
+// IPU-HSP clock is independent of the HCLK and can go up to 177MHz but requires
+// higher voltage support. For simplicity, limit it to 133MHz
+#define HSP_CLK_MAX 133333333
+
+#define ERR_WRONG_CLK -1
+#define ERR_NO_MFI -2
+#define ERR_NO_MFN -3
+#define ERR_NO_PD -4
+#define ERR_NO_PRESC -5
+#define ERR_NO_AHB_DIV -6
+
+u32 pll_clock(enum plls pll);
+u32 get_main_clock(enum main_clocks clk);
+u32 get_peri_clock(enum peri_clocks clk);
+
+static volatile u32 *pll_base[] =
+{
+ REG32_PTR(PLL1_BASE_ADDR),
+ REG32_PTR(PLL2_BASE_ADDR),
+ REG32_PTR(PLL3_BASE_ADDR),
+};
+
+#define NOT_ON_VAL 0xDEADBEEF
+
+static void clock_setup(int argc, char *argv[]);
+
+RedBoot_cmd("clock",
+ "Setup/Display clock\nSyntax:",
+ "[<core clock in MHz> :<DDR clock in MHz>] \n\n\
+ Examples:\n\
+ [clock] -> Show various clocks\n\
+ [clock 665] -> Core=665 \n\
+ [clock 800:133] -> Core=800 DDR=133 \n\
+ [clock :166] -> Core=no change DDR=166 \n",
+ clock_setup
+ );
+
+/*!
+ * This is to calculate various parameters based on reference clock and
+ * targeted clock based on the equation:
+ * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
+ * This calculation is based on a fixed MFD value for simplicity.
+ *
+ * @param ref reference clock freq in Hz
+ * @param target targeted clock in Hz
+ * @param p_pd calculated pd value (pd value from register + 1) upon return
+ * @param p_mfi calculated actual mfi value upon return
+ * @param p_mfn calculated actual mfn value upon return
+ * @param p_mfd fixed mfd value (mfd value from register + 1) upon return
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
+{
+ u64 pd, mfi = 1, mfn, mfd, n_target = target, n_ref = ref, i;
+
+ // make sure targeted freq is in the valid range. Otherwise the
+ // following calculation might be wrong!!!
+ if (n_target < PLL_FREQ_MIN(ref) || n_target > PLL_FREQ_MAX(ref))
+ return ERR_WRONG_CLK;
+ for (i = 0; ; i++) {
+ if (i == REF_IN_CLK_NUM)
+ return ERR_WRONG_CLK;
+ if (fixed_mfd[i].ref_clk_hz == ref) {
+ mfd = fixed_mfd[i].mfd;
+ break;
+ }
+ }
+
+ // Use n_target and n_ref to avoid overflow
+ for (pd = 1; pd <= PLL_PD_MAX; pd++) {
+ mfi = (n_target * pd) / (4 * n_ref);
+ if (mfi > PLL_MFI_MAX) {
+ return ERR_NO_MFI;
+ } else if (mfi < 5) {
+ continue;
+ }
+ break;
+ }
+ // Now got pd and mfi already
+ mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
+#ifdef CMD_CLOCK_DEBUG
+ diag_printf("%d: ref=%d, target=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
+ __LINE__, ref, (u32)n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
+#endif
+ i = 1;
+ if (mfn != 0)
+ i = gcd(mfd, mfn);
+ pll->pd = (u32)pd;
+ pll->mfi = (u32)mfi;
+ pll->mfn = (u32)(mfn / i);
+ pll->mfd = (u32)(mfd / i);
+ return 0;
+}
+
+/*!
+ * This function returns the low power audio clock.
+ */
+u32 get_lp_apm(void)
+{
+ u32 ret_val = 0;
+ u32 ccsr = readl(CCM_BASE_ADDR + CLKCTL_CCSR);
+
+ if (((ccsr >> 9) & 1) == 0) {
+ ret_val = FREQ_24MHZ;
+ } else {
+ ret_val = FREQ_32768HZ;
+ }
+ return ret_val;
+}
+
+/*!
+ * This function returns the periph_clk.
+ */
+u32 get_periph_clk(void)
+{
+ u32 ret_val = 0, clk_sel;
+
+ u32 cbcdr = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
+ u32 cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR);
+
+ if (((cbcdr >> 25) & 1) == 0) {
+ ret_val = pll_clock(PLL2);
+ } else {
+ clk_sel = (cbcmr >> 12) & 3;
+ if (clk_sel == 0) {
+ ret_val = pll_clock(PLL1);
+ } else if (clk_sel == 1) {
+ ret_val = pll_clock(PLL3);
+ } else if (clk_sel == 2) {
+ ret_val = get_lp_apm();
+ }
+ }
+ return ret_val;
+}
+
+/*!
+ * This function assumes the expected core clock has to be changed by
+ * modifying the PLL. This is NOT true always but for most of the times,
+ * it is. So it assumes the PLL output freq is the same as the expected
+ * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
+ * In the latter case, it will try to increase the presc value until
+ * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
+ * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
+ * on the targeted PLL and reference input clock to the PLL. Lastly,
+ * it sets the register based on these values along with the dividers.
+ * Note 1) There is no value checking for the passed-in divider values
+ * so the caller has to make sure those values are sensible.
+ * 2) Also adjust the NFC divider such that the NFC clock doesn't
+ * exceed NFC_CLK_MAX.
+ * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
+ * 177MHz for higher voltage, this function fixes the max to 133MHz.
+ * 4) This function should not have allowed diag_printf() calls since
+ * the serial driver has been stoped. But leave then here to allow
+ * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
+ *
+ * @param ref pll input reference clock (24MHz)
+ * @param core_clk core clock in Hz
+ * @param emi_clk emi clock in Hz
+ # @return 0 if successful; non-zero otherwise
+ */
+int configure_clock(u32 ref, u32 core_clk, u32 emi_clk)
+{
+
+ u32 pll, clk_src;
+ struct pll_param pll_param;
+ int ret, clk_sel, div = 1, div_core = 1, div_per = 1, shift = 0;
+ u32 cbcdr = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
+ u32 cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR);
+ u32 ccsr = readl(CCM_BASE_ADDR + CLKCTL_CCSR);
+ u32 icgc = readl(PLATFORM_BASE_ADDR + PLATFORM_ICGC);
+
+ if (core_clk != 0) {
+ // assume pll default to core clock first
+ pll = core_clk;
+ if ((ret = calc_pll_params(ref, pll, &pll_param)) != 0) {
+ diag_printf("can't find pll parameters: %d\n", ret);
+ return ret;
+ }
+#ifdef CMD_CLOCK_DEBUG
+ diag_printf("ref=%d, pll=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
+ ref, pll, pll_param.pd, pll_param.mfi, pll_param.mfn, pll_param.mfd);
+#endif
+
+ /* Applies for TO 2 only */
+ if (((cbcdr >> 30) & 0x1) == 0x1) {
+ /* Disable IPU and HSC dividers */
+ writel(0x60000, CCM_BASE_ADDR + CLKCTL_CCDR);
+ /* Switch DDR to different source */
+ writel(cbcdr & ~0x40000000, CCM_BASE_ADDR + CLKCTL_CBCDR);
+ while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0);
+ writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
+ }
+
+ /* Switch ARM to PLL2 clock */
+ writel(ccsr | 0x4, CCM_BASE_ADDR + CLKCTL_CCSR);
+
+ if ((core_clk > 665000000) && (core_clk <= 800000000)) {
+ div_per = 5;
+ } else if (core_clk > 800000000) {
+ div_per = 6;
+ } else {
+ div_per = 4;
+ }
+
+ if (core_clk > 800000000) {
+ div_core = 3;
+ increase_core_voltage(true);
+ } else {
+ div_core = 2;
+ increase_core_voltage(false);
+ }
+
+ // adjust pll settings
+ writel(((pll_param.pd - 1) << 0) | (pll_param.mfi << 4),
+ PLL1_BASE_ADDR + PLL_DP_OP);
+ writel(pll_param.mfn, PLL1_BASE_ADDR + PLL_DP_MFN);
+ writel(pll_param.mfd - 1, PLL1_BASE_ADDR + PLL_DP_MFD);
+ writel(((pll_param.pd - 1) << 0) | (pll_param.mfi << 4),
+ PLL1_BASE_ADDR + PLL_DP_HFS_OP);
+ writel(pll_param.mfn, PLL1_BASE_ADDR + PLL_DP_HFS_MFN);
+ writel(pll_param.mfd - 1, PLL1_BASE_ADDR + PLL_DP_HFS_MFD);
+
+ icgc &= ~(0x77);
+ icgc |= (div_core << 4);
+ icgc |= div_per;
+ /* Set the platform clock dividers */
+ writel(icgc, PLATFORM_BASE_ADDR + PLATFORM_ICGC);
+ /* Switch ARM back to PLL1 */
+ writel((ccsr & ~0x4), CCM_BASE_ADDR + CLKCTL_CCSR);
+ /* Applies for TO 2 only */
+ if (((cbcdr >> 30) & 0x1) == 0x1) {
+ /* Disable IPU and HSC dividers */
+ writel(0x60000, CCM_BASE_ADDR + CLKCTL_CCDR);
+ /* Switch DDR back to PLL1 */
+ writel(cbcdr | 0x40000000, CCM_BASE_ADDR + CLKCTL_CBCDR);
+ while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0);
+ writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
+ if (emi_clk == 0) {
+ /* Keep EMI clock to the max if not specified */
+ emi_clk = 200000000;
+ }
+ }
+ }
+
+ if (emi_clk != 0) {
+ /* Applies for TO 2 only */
+ if (((cbcdr >> 30) & 0x1) == 0x1) {
+ clk_src = pll_clock(PLL1);
+ shift = 27;
+ } else {
+ clk_src = get_periph_clk();
+ /* Find DDR clock input */
+ clk_sel = (cbcmr >> 10) & 0x3;
+ if (clk_sel == 0) {
+ shift = 16;
+ } else if (clk_sel == 1) {
+ shift = 19;
+ } else if (clk_sel == 2) {
+ shift = 22;
+ } else if (clk_sel == 3) {
+ shift = 10;
+ }
+ }
+ if ((clk_src % emi_clk) == 0)
+ div = clk_src / emi_clk;
+ else
+ div = (clk_src / emi_clk) + 1;
+ if (div > 8)
+ div = 8;
+
+ cbcdr = cbcdr & ~(0x7 << shift);
+ cbcdr |= ((div - 1) << shift);
+ /* Disable IPU and HSC dividers */
+ writel(0x60000, CCM_BASE_ADDR + CLKCTL_CCDR);
+ writel(cbcdr, CCM_BASE_ADDR + CLKCTL_CBCDR);
+ while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0);
+ writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
+ }
+ return 0;
+}
+
+static void clock_setup(int argc,char *argv[])
+{
+
+ u32 i, core_clk, ddr_clk, data[3];
+ unsigned long temp;
+ int ret;
+
+ if (argc == 1)
+ goto print_clock;
+
+ for (i = 0; i < 2; i++) {
+ if (!parse_num(*(&argv[1]), &temp, &argv[1], ":")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ data[i] = temp;
+ }
+
+ core_clk = data[0] * SZ_DEC_1M;
+ ddr_clk = data[1] * SZ_DEC_1M;
+
+ if (core_clk != 0) {
+ if ((core_clk < PLL_FREQ_MIN(PLL_REF_CLK)) || (core_clk > PLL_FREQ_MAX(PLL_REF_CLK))) {
+ diag_printf("Targeted core clock should be within [%d - %d]\n",
+ PLL_FREQ_MIN(PLL_REF_CLK), PLL_FREQ_MAX(PLL_REF_CLK));
+ return;
+ }
+ }
+
+ if (ddr_clk != 0) {
+ if (ddr_clk > MAX_DDR_CLK) {
+ diag_printf("DDR clock should be less than %d MHz, assuming max value \n", (MAX_DDR_CLK / SZ_DEC_1M));
+ ddr_clk = MAX_DDR_CLK;
+ }
+ }
+
+ // stop the serial to be ready to adjust the clock
+ hal_delay_us(100000);
+ cyg_hal_plf_serial_stop();
+ // adjust the clock
+ ret = configure_clock(PLL_REF_CLK, core_clk, ddr_clk);
+ // restart the serial driver
+ cyg_hal_plf_serial_init();
+ hal_delay_us(100000);
+
+ if (ret != 0) {
+ diag_printf("Failed to setup clock: %d\n", ret);
+ return;
+ }
+ diag_printf("\n<<<New clock setting>>>\n");
+
+ // Now printing clocks
+print_clock:
+
+ diag_printf("\nPLL1\t\tPLL2\t\tPLL3\n");
+ diag_printf("========================================\n");
+ diag_printf("%-16d%-16d%-16d\n\n", pll_clock(PLL1), pll_clock(PLL2),
+ pll_clock(PLL3));
+ diag_printf("CPU\t\tAHB\t\tIPG\t\tEMI_CLK\n");
+ diag_printf("========================================================\n");
+ diag_printf("%-16d%-16d%-16d%-16d\n\n",
+ get_main_clock(CPU_CLK),
+ get_main_clock(AHB_CLK),
+ get_main_clock(IPG_CLK),
+ get_main_clock(DDR_CLK));
+
+ diag_printf("NFC\t\tUSB\t\tIPG_PER_CLK\n");
+ diag_printf("========================================\n");
+ diag_printf("%-16d%-16d%-16d\n\n",
+ get_main_clock(NFC_CLK),
+ get_main_clock(USB_CLK),
+ get_main_clock(IPG_PER_CLK));
+
+ diag_printf("UART1-3\t\tSSI1\t\tSSI2\t\tSPI\n");
+ diag_printf("===========================================");
+ diag_printf("=============\n");
+
+ diag_printf("%-16d%-16d%-16d%-16d\n\n",
+ get_peri_clock(UART1_BAUD),
+ get_peri_clock(SSI1_BAUD),
+ get_peri_clock(SSI2_BAUD),
+ get_peri_clock(SPI1_CLK));
+
+#if 0
+ diag_printf("IPG_PERCLK as baud clock for: UART1-5, I2C, OWIRE, SDHC");
+ if (((readl(EPIT1_BASE_ADDR) >> 24) & 0x3) == 0x2) {
+ diag_printf(", EPIT");
+ }
+ if (((readl(GPT1_BASE_ADDR) >> 6) & 0x7) == 0x2) {
+ diag_printf("GPT,");
+ }
+#endif
+ diag_printf("\n");
+
+}
+
+/*!
+ * This function returns the PLL output value in Hz based on pll.
+ */
+u32 pll_clock(enum plls pll)
+{
+ u64 mfi, mfn, mfd, pdf, ref_clk, pll_out, sign;
+ u64 dp_ctrl, dp_op, dp_mfd, dp_mfn, clk_sel;
+ u8 dbl = 0;
+
+ dp_ctrl = pll_base[pll][PLL_DP_CTL >> 2];
+ clk_sel = MXC_GET_FIELD(dp_ctrl, 2, 8);
+ ref_clk = fixed_mfd[clk_sel].ref_clk_hz;
+
+ if ((pll_base[pll][PLL_DP_CTL >> 2] & 0x80) == 0) {
+ dp_op = pll_base[pll][PLL_DP_OP >> 2];
+ dp_mfd = pll_base[pll][PLL_DP_MFD >> 2];
+ dp_mfn = pll_base[pll][PLL_DP_MFN >> 2];
+ } else {
+ dp_op = pll_base[pll][PLL_DP_HFS_OP >> 2];
+ dp_mfd = pll_base[pll][PLL_DP_HFS_MFD >> 2];
+ dp_mfn = pll_base[pll][PLL_DP_HFS_MFN >> 2];
+ }
+ pdf = dp_op & 0xF;
+ mfi = (dp_op >> 4) & 0xF;
+ mfi = (mfi <= 5) ? 5: mfi;
+ mfd = dp_mfd & 0x07FFFFFF;
+ mfn = dp_mfn & 0x07FFFFFF;
+
+ sign = (mfn < 0x4000000) ? 0: 1;
+ mfn = (mfn <= 0x4000000) ? mfn: (0x8000000 - mfn);
+
+ dbl = ((dp_ctrl >> 12) & 0x1) + 1;
+
+ dbl = dbl * 2;
+ if (sign == 0) {
+ pll_out = (dbl * ref_clk * mfi + ((dbl * ref_clk * mfn) / (mfd + 1))) /
+ (pdf + 1);
+ } else {
+ pll_out = (dbl * ref_clk * mfi - ((dbl * ref_clk * mfn) / (mfd + 1))) /
+ (pdf + 1);
+ }
+
+ return (u32)pll_out;
+}
+
+/*!
+ * This function returns the emi_core_clk_root clock.
+ */
+u32 get_emi_core_clk(void)
+{
+ u32 cbcdr = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
+ u32 clk_sel = 0, max_pdf = 0, peri_clk = 0, ahb_clk = 0;
+ u32 ret_val = 0;
+
+ max_pdf = (cbcdr >> 10) & 0x7;
+ peri_clk = get_periph_clk();
+ ahb_clk = peri_clk / (max_pdf + 1);
+
+ clk_sel = (cbcdr >> 26) & 1;
+ if (clk_sel == 0) {
+ ret_val = peri_clk;
+ } else {
+ ret_val = ahb_clk ;
+ }
+ return ret_val;
+}
+
+/*!
+ * This function returns the main clock value in Hz.
+ */
+u32 get_main_clock(enum main_clocks clk)
+{
+ u32 pdf, max_pdf, ipg_pdf, nfc_pdf, clk_sel;
+ u32 pll, ret_val = 0;
+ u32 cacrr = readl(CCM_BASE_ADDR + CLKCTL_CACRR);
+ u32 cbcdr = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
+ u32 cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR);
+ u32 cscmr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCMR1);
+ u32 cscdr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCDR1);
+
+ switch (clk) {
+ case CPU_CLK:
+ pdf = cacrr & 0x7;
+ pll = pll_clock(PLL1);
+ ret_val = pll / (pdf + 1);
+ break;
+ case AHB_CLK:
+ max_pdf = (cbcdr >> 10) & 0x7;
+ pll = get_periph_clk();
+ ret_val = pll / (max_pdf + 1);
+ break;
+ case IPG_CLK:
+ max_pdf = (cbcdr >> 10) & 0x7;
+ ipg_pdf = (cbcdr >> 8) & 0x3;
+ pll = get_periph_clk();
+ ret_val = pll / ((max_pdf + 1) * (ipg_pdf + 1));
+ break;
+ case IPG_PER_CLK:
+ clk_sel = cbcmr & 1;
+ if (clk_sel == 0) {
+ clk_sel = (cbcmr >> 1) & 1;
+ pdf = (((cbcdr >> 6) & 3) + 1) * (((cbcdr >> 3) & 7) + 1) * ((cbcdr & 7) + 1);
+ if (clk_sel == 0) {
+ ret_val = get_periph_clk() / pdf;
+ } else {
+ ret_val = get_lp_apm();
+ }
+ } else {
+ /* Same as IPG_CLK */
+ max_pdf = (cbcdr >> 10) & 0x7;
+ ipg_pdf = (cbcdr >> 8) & 0x3;
+ pll = get_periph_clk();
+ ret_val = pll / ((max_pdf + 1) * (ipg_pdf + 1));
+ }
+ break;
+ case DDR_CLK:
+ if (((cbcdr >> 30) & 0x1) == 0x1) {
+ pll = pll_clock(PLL1);
+ pdf = (cbcdr >> 27) & 0x7;
+ } else {
+ clk_sel = (cbcmr >> 10) & 3;
+ pll = get_periph_clk();
+ if (clk_sel == 0) {
+ /* AXI A */
+ pdf = (cbcdr >> 16) & 0x7;
+ } else if (clk_sel == 1) {
+ /* AXI B */
+ pdf = (cbcdr >> 19) & 0x7;
+ } else if (clk_sel == 2) {
+ /* EMI SLOW CLOCK ROOT */
+ pll = get_emi_core_clk();
+ pdf = (cbcdr >> 22) & 0x7;
+ } else if (clk_sel == 3) {
+ /* AHB CLOCK */
+ pdf = (cbcdr >> 10) & 0x7;
+ }
+ }
+
+ ret_val = pll / (pdf + 1);
+ break;
+ case NFC_CLK:
+ pdf = (cbcdr >> 22) & 0x7;
+ nfc_pdf = (cbcdr >> 13) & 0x7;
+ pll = get_emi_core_clk();
+ ret_val = pll / ((pdf + 1) * (nfc_pdf + 1));
+ break;
+ case USB_CLK:
+ clk_sel = (cscmr1 >> 22) & 3;
+ if (clk_sel == 0) {
+ pll = pll_clock(PLL1);
+ } else if (clk_sel == 1) {
+ pll = pll_clock(PLL2);
+ } else if (clk_sel == 2) {
+ pll = pll_clock(PLL3);
+ } else if (clk_sel == 3) {
+ pll = get_lp_apm();
+ }
+ pdf = (cscdr1 >> 8) & 0x7;
+ max_pdf = (cscdr1 >> 6) & 0x3;
+ ret_val = pll / ((pdf + 1) * (max_pdf + 1));
+ break;
+ default:
+ diag_printf("Unknown clock: %d\n", clk);
+ break;
+ }
+
+ return ret_val;
+}
+
+/*!
+ * This function returns the peripheral clock value in Hz.
+ */
+u32 get_peri_clock(enum peri_clocks clk)
+{
+ u32 ret_val = 0, pdf, pre_pdf, clk_sel;
+ u32 cscmr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCMR1);
+ u32 cscdr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCDR1);
+ u32 cscdr2 = readl(CCM_BASE_ADDR + CLKCTL_CSCDR2);
+ u32 cs1cdr = readl(CCM_BASE_ADDR + CLKCTL_CS1CDR);
+ u32 cs2cdr = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);
+
+ switch (clk) {
+ case UART1_BAUD:
+ case UART2_BAUD:
+ case UART3_BAUD:
+ pre_pdf = (cscdr1 >> 3) & 0x7;
+ pdf = cscdr1 & 0x7;
+ clk_sel = (cscmr1 >> 24) & 3;
+ if (clk_sel == 0) {
+ ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 1) {
+ ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 2) {
+ ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
+ } else {
+ ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
+ }
+ break;
+ case SSI1_BAUD:
+ pre_pdf = (cs1cdr >> 6) & 0x7;
+ pdf = cs1cdr & 0x3F;
+ clk_sel = (cscmr1 >> 14) & 3;
+ if (clk_sel == 0) {
+ ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 0x1) {
+ ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 0x2) {
+ ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
+ } else {
+ ret_val = CKIH /((pre_pdf + 1) * (pdf + 1));
+ }
+ break;
+ case SSI2_BAUD:
+ pre_pdf = (cs2cdr >> 6) & 0x7;
+ pdf = cs2cdr & 0x3F;
+ clk_sel = (cscmr1 >> 12) & 3;
+ if (clk_sel == 0) {
+ ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 0x1) {
+ ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 0x2) {
+ ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
+ } else {
+ ret_val = CKIH /((pre_pdf + 1) * (pdf + 1));
+ }
+ break;
+ case SPI1_CLK:
+ case SPI2_CLK:
+ pre_pdf = (cscdr2 >> 25) & 0x7;
+ pdf = (cscdr2 >> 19) & 0x3F;
+ clk_sel = (cscmr1 >> 4) & 3;
+ if (clk_sel == 0) {
+ ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 1) {
+ ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 2) {
+ ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
+ } else {
+ ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
+ }
+ break;
+ default:
+ diag_printf("%s(): This clock: %d not supported yet \n",
+ __FUNCTION__, clk);
+ break;
+ }
+
+ return ret_val;
+}
+
+#ifdef L2CC_ENABLED
+/*
+ * This command is added for some simple testing only. It turns on/off
+ * L2 cache regardless of L1 cache state. The side effect of this is
+ * when doing any flash operations such as "fis init", the L2
+ * will be turned back on along with L1 caches even though it is off
+ * by using this command.
+ */
+RedBoot_cmd("L2",
+ "L2 cache",
+ "[ON | OFF]",
+ do_L2_caches
+ );
+
+void do_L2_caches(int argc, char *argv[])
+{
+ u32 oldints;
+ int L2cache_on=0;
+
+ if (argc == 2) {
+ if (strcasecmp(argv[1], "on") == 0) {
+ HAL_DISABLE_INTERRUPTS(oldints);
+ HAL_ENABLE_L2();
+ HAL_RESTORE_INTERRUPTS(oldints);
+ } else if (strcasecmp(argv[1], "off") == 0) {
+ HAL_DISABLE_INTERRUPTS(oldints);
+ HAL_DCACHE_DISABLE_C1();
+ HAL_CACHE_FLUSH_ALL();
+ HAL_DISABLE_L2();
+ HAL_DCACHE_ENABLE_L1();
+ HAL_RESTORE_INTERRUPTS(oldints);
+ } else {
+ diag_printf("Invalid L2 cache mode: %s\n", argv[1]);
+ }
+ } else {
+ HAL_L2CACHE_IS_ENABLED(L2cache_on);
+ diag_printf("L2 cache: %s\n", L2cache_on?"On":"Off");
+ }
+}
+#endif //L2CC_ENABLED
+
+#define IIM_ERR_SHIFT 8
+#define POLL_FUSE_PRGD (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT))
+#define POLL_FUSE_SNSD (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT))
+
+static void fuse_op_start(void)
+{
+ /* Do not generate interrupt */
+ writel(0, IIM_BASE_ADDR + IIM_STATM_OFF);
+ // clear the status bits and error bits
+ writel(0x3, IIM_BASE_ADDR + IIM_STAT_OFF);
+ writel(0xFE, IIM_BASE_ADDR + IIM_ERR_OFF);
+}
+
+/*
+ * The action should be either:
+ * POLL_FUSE_PRGD
+ * or:
+ * POLL_FUSE_SNSD
+ */
+static int poll_fuse_op_done(int action)
+{
+
+ u32 status, error;
+
+ if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) {
+ diag_printf("%s(%d) invalid operation\n", __FUNCTION__, action);
+ return -1;
+ }
+
+ /* Poll busy bit till it is NOT set */
+ while ((readl(IIM_BASE_ADDR + IIM_STAT_OFF) & IIM_STAT_BUSY) != 0 ) {
+ }
+
+ /* Test for successful write */
+ status = readl(IIM_BASE_ADDR + IIM_STAT_OFF);
+ error = readl(IIM_BASE_ADDR + IIM_ERR_OFF);
+
+ if ((status & action) != 0 && (error & (action >> IIM_ERR_SHIFT)) == 0) {
+ if (error) {
+ diag_printf("Even though the operation seems successful...\n");
+ diag_printf("There are some error(s) at addr=0x%x: 0x%x\n",
+ (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+ }
+ return 0;
+ }
+ diag_printf("%s(%d) failed\n", __FUNCTION__, action);
+ diag_printf("status address=0x%x, value=0x%x\n",
+ (IIM_BASE_ADDR + IIM_STAT_OFF), status);
+ diag_printf("There are some error(s) at addr=0x%x: 0x%x\n",
+ (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+ return -1;
+}
+
+static void sense_fuse(int bank, int row, int bit)
+{
+ int addr, addr_l, addr_h, reg_addr;
+
+ fuse_op_start();
+
+ addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+ /* Set IIM Program Upper Address */
+ addr_h = (addr >> 8) & 0x000000FF;
+ /* Set IIM Program Lower Address */
+ addr_l = (addr & 0x000000FF);
+
+#ifdef IIM_FUSE_DEBUG
+ diag_printf("%s: addr_h=0x%x, addr_l=0x%x\n",
+ __FUNCTION__, addr_h, addr_l);
+#endif
+ writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
+ writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
+ /* Start sensing */
+ writel(0x8, IIM_BASE_ADDR + IIM_FCTL_OFF);
+ if (poll_fuse_op_done(POLL_FUSE_SNSD) != 0) {
+ diag_printf("%s(bank: %d, row: %d, bit: %d failed\n",
+ __FUNCTION__, bank, row, bit);
+ }
+ reg_addr = IIM_BASE_ADDR + IIM_SDAT_OFF;
+ diag_printf("fuses at (bank:%d, row:%d) = 0x%x\n", bank, row, readl(reg_addr));
+}
+
+void do_fuse_read(int argc, char *argv[])
+{
+ unsigned long bank, row;
+
+ if (argc == 1) {
+ diag_printf("Useage: fuse_read <bank> <row>\n");
+ return;
+ } else if (argc == 3) {
+ if (!parse_num(*(&argv[1]), &bank, &argv[1], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(*(&argv[2]), &row, &argv[2], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+
+ diag_printf("Read fuse at bank:%ld row:%ld\n", bank, row);
+ sense_fuse(bank, row, 0);
+
+ } else {
+ diag_printf("Passing in wrong arguments: %d\n", argc);
+ diag_printf("Useage: fuse_read <bank> <row>\n");
+ }
+}
+
+/* Blow fuses based on the bank, row and bit positions (all 0-based)
+*/
+static int fuse_blow(int bank,int row,int bit)
+{
+ int addr, addr_l, addr_h, ret = -1;
+
+ fuse_op_start();
+
+ /* Disable IIM Program Protect */
+ writel(0xAA, IIM_BASE_ADDR + IIM_PREG_P_OFF);
+
+ addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+ /* Set IIM Program Upper Address */
+ addr_h = (addr >> 8) & 0x000000FF;
+ /* Set IIM Program Lower Address */
+ addr_l = (addr & 0x000000FF);
+
+#ifdef IIM_FUSE_DEBUG
+ diag_printf("blowing addr_h=0x%x, addr_l=0x%x\n", addr_h, addr_l);
+#endif
+
+ writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
+ writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
+ /* Start Programming */
+ writel(0x31, IIM_BASE_ADDR + IIM_FCTL_OFF);
+ if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) {
+ ret = 0;
+ }
+
+ /* Enable IIM Program Protect */
+ writel(0x0, IIM_BASE_ADDR + IIM_PREG_P_OFF);
+ return ret;
+}
+
+/*
+ * This command is added for burning IIM fuses
+ */
+RedBoot_cmd("fuse_read",
+ "read some fuses",
+ "<bank> <row>",
+ do_fuse_read
+ );
+
+RedBoot_cmd("fuse_blow",
+ "blow some fuses",
+ "<bank> <row> <value>",
+ do_fuse_blow
+ );
+
+#define INIT_STRING "12345678"
+
+void quick_itoa(u32 num, char *a)
+{
+ int i, j, k;
+ for (i = 0; i <= 7; i++) {
+ j = (num >> (4 * i)) & 0xF;
+ k = (j < 10) ? '0' : ('a' - 0xa);
+ a[i] = j + k;
+ }
+}
+
+void do_fuse_blow(int argc, char *argv[])
+{
+ unsigned long bank, row, value;
+ unsigned int reg, i;
+
+ if (argc != 4) {
+ diag_printf("It is too dangeous for you to use this command.\n");
+ return;
+ }
+ if (!parse_num(*(&argv[1]), &bank, &argv[1], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(*(&argv[2]), &row, &argv[2], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(*(&argv[3]), &value, &argv[3], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+
+ reg = readl(CCM_BASE_ADDR + 0x64);
+ reg |= 0x10;
+ writel(reg, CCM_BASE_ADDR + 0x64);
+
+ diag_printf("Blowing fuse at bank:%ld row:%ld value:%ld\n",
+ bank, row, value);
+ for (i = 0; i < 8; i++) {
+ if (((value >> i) & 0x1) == 0) {
+ continue;
+ }
+ if (fuse_blow(bank, row, i) != 0) {
+ diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d failed\n",
+ bank, row, i);
+ } else {
+ diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d successful\n",
+ bank, row, i);
+ }
+ }
+ sense_fuse(bank, row, 0);
+ reg &= ~0x10;
+ writel(reg, CCM_BASE_ADDR + 0x64);
+}
+
+/* precondition: m>0 and n>0. Let g=gcd(m,n). */
+int gcd(int m, int n)
+{
+ int t;
+ while(m > 0) {
+ if(n > m) {t = m; m = n; n = t;} /* swap */
+ m -= n;
+ }
+ return n;
+}
+
+#define CLOCK_SRC_DETECT_MS 100
+#define CLOCK_IPG_DEFAULT 66500000
+#define CLOCK_SRC_DETECT_MARGIN 500000
+void mxc_show_clk_input(void)
+{
+// u32 c1, c2, diff, ipg_real, num = 0;
+
+ return; // FIXME
+#if 0
+ switch (prcs) {
+ case 0x01:
+ diag_printf("FPM enabled --> 32KHz input source\n");
+ return;
+ case 0x02:
+ break;
+ default:
+ diag_printf("Error %d: unknown clock source %d\n", __LINE__, prcs);
+ return;
+ }
+
+ // enable GPT with IPG clock input
+ writel(0x241, GPT_BASE_ADDR + GPTCR);
+ // prescaler = 1
+ writel(0, GPT_BASE_ADDR + GPTPR);
+
+ c1 = readl(GPT_BASE_ADDR + GPTCNT);
+ // use 32KHz input clock to get the delay
+ hal_delay_us(CLOCK_SRC_DETECT_MS * 1000);
+ c2 = readl(GPT_BASE_ADDR + GPTCNT);
+ diff = (c2 > c1) ? (c2 - c1) : (0xFFFFFFFF - c1 + c2);
+
+ ipg_real = diff * (1000 / CLOCK_SRC_DETECT_MS);
+
+ if (num != 0) {
+ diag_printf("Error: Actural clock input is %d MHz\n", num);
+ diag_printf(" ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n\n",
+ ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
+ hal_delay_us(2000000);
+ } else {
+ diag_printf("ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n\n",
+ ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
+ }
+#endif
+}
+
+RedBoot_init(mxc_show_clk_input, RedBoot_INIT_LAST);
+#if 0
+void imx_power_mode(int mode)
+{
+ volatile unsigned int val;
+ switch (mode) {
+ case 2:
+ writel(0x0000030f, GPC_PGR);
+ writel(0x1, SRPGCR_EMI);
+ writel(0x1, SRPGCR_ARM);
+ writel(0x1, PGC_PGCR_VPU);
+ writel(0x1, PGC_PGCR_IPU);
+
+
+ case 1:
+ // stop mode - from validation code
+ // Set DSM_INT_HOLDOFF bit in TZIC
+ // If the TZIC didn't write the bit then there was interrupt pending
+ // It will be serviced while we're in the loop
+ // So we write to this bit again
+ while (readl(INTC_BASE_ADDR + 0x14) == 0) {
+ writel(1, INTC_BASE_ADDR + 0x14);
+ // Wait few cycles
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ }
+ diag_printf("Entering stop mode\n");
+ val = readl(CCM_BASE_ADDR + 0x74);
+ val = (val & 0xfffffffc) | 0x2; // set STOP mode
+ writel(val, CCM_BASE_ADDR + 0x74);
+ val = readl(PLATFORM_LPC_REG);
+ writel(val | (1 << 16), PLATFORM_LPC_REG);// ENABLE DSM in ELBOW submodule of ARM platform
+ writel(val | (1 << 17), PLATFORM_LPC_REG);// ENABLE DSM in ELBOW submodule of ARM platform
+ break;
+ default:
+ break;
+ }
+
+ hal_delay_us(50);
+
+ asm("mov r1, #0");
+ asm("mcr p15, 0, r1, c7, c0, 4");
+}
+
+void do_power_mode(int argc, char *argv[])
+{
+ int mode;
+
+ if (argc == 1) {
+ diag_printf("Useage: power_mode <mode>\n");
+ return;
+ } else if (argc == 2) {
+ if (!parse_num(*(&argv[1]), (unsigned long *)&mode, &argv[1], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ diag_printf("Entering power mode: %d\n", mode);
+ imx_power_mode(mode);
+
+ } else {
+ diag_printf("Passing in wrong arguments: %d\n", argc);
+ diag_printf("Useage: power_mode <mode>\n");
+ }
+}
+
+/*
+ * This command is added for burning IIM fuses
+ */
+RedBoot_cmd("power_mode",
+ "Enter various power modes:",
+ "\n\
+ <0> - WAIT\n\
+ <1> - SRPG\n\
+ <2> - STOP\n\
+ <3> - STOP with Power-Gating\n\
+ -- need reset after issuing the command",
+ do_power_mode
+ );
+#endif
--- /dev/null
+/*=============================================================================
+//
+// hal_diag.c
+//
+// HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_arch.h> // basic machine info
+#include <cyg/hal/hal_intr.h> // interrupt macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_if.h> // Calling interface definitions
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/drv_api.h> // cyg_drv_interrupt_acknowledge
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+
+/*
+ * UART Control Register 0 Bit Fields.
+ */
+#define EUartUCR1_ADEN (1 << 15) // Auto dectect interrupt
+#define EUartUCR1_ADBR (1 << 14) // Auto detect baud rate
+#define EUartUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable
+#define EUartUCR1_IDEN (1 << 12) // Idle condition interrupt
+#define EUartUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable
+#define EUartUCR1_RDMAEN (1 << 8) // Recv ready DMA enable
+#define EUartUCR1_IREN (1 << 7) // Infrared interface enable
+#define EUartUCR1_TXMPTYEN (1 << 6) // Transimitter empty interrupt enable
+#define EUartUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable
+#define EUartUCR1_SNDBRK (1 << 4) // Send break
+#define EUartUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable
+#define EUartUCR1_DOZE (1 << 1) // Doze
+#define EUartUCR1_UARTEN (1 << 0) // UART enabled
+#define EUartUCR2_ESCI (1 << 15) // Escape seq interrupt enable
+#define EUartUCR2_IRTS (1 << 14) // Ignore RTS pin
+#define EUartUCR2_CTSC (1 << 13) // CTS pin control
+#define EUartUCR2_CTS (1 << 12) // Clear to send
+#define EUartUCR2_ESCEN (1 << 11) // Escape enable
+#define EUartUCR2_PREN (1 << 8) // Parity enable
+#define EUartUCR2_PROE (1 << 7) // Parity odd/even
+#define EUartUCR2_STPB (1 << 6) // Stop
+#define EUartUCR2_WS (1 << 5) // Word size
+#define EUartUCR2_RTSEN (1 << 4) // Request to send interrupt enable
+#define EUartUCR2_ATEN (1 << 3) // Aging timer enable
+#define EUartUCR2_TXEN (1 << 2) // Transmitter enabled
+#define EUartUCR2_RXEN (1 << 1) // Receiver enabled
+#define EUartUCR2_SRST_ (1 << 0) // SW reset
+#define EUartUCR3_PARERREN (1 << 12) // Parity enable
+#define EUartUCR3_FRAERREN (1 << 11) // Frame error interrupt enable
+#define EUartUCR3_ADNIMP (1 << 7) // Autobaud detection not improved
+#define EUartUCR3_RXDSEN (1 << 6) // Receive status interrupt enable
+#define EUartUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable
+#define EUartUCR3_AWAKEN (1 << 4) // Async wake interrupt enable
+#define EUartUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected
+#define EUartUCR3_INVT (1 << 1) // Inverted Infrared transmission
+#define EUartUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable
+#define EUartUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars)
+#define EUartUCR4_INVR (1 << 9) // Inverted infrared reception
+#define EUartUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable
+#define EUartUCR4_WKEN (1 << 7) // Wake interrupt enable
+#define EUartUCR4_IRSC (1 << 5) // IR special case
+#define EUartUCR4_LPBYP (1 << 4) // Low power bypass
+#define EUartUCR4_TCEN (1 << 3) // Transmit complete interrupt enable
+#define EUartUCR4_BKEN (1 << 2) // Break condition interrupt enable
+#define EUartUCR4_OREN (1 << 1) // Receiver overrun interrupt enable
+#define EUartUCR4_DREN (1 << 0) // Recv data ready interrupt enable
+#define EUartUFCR_RXTL_SHF 0 // Receiver trigger level shift
+#define EUartUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div 1)
+#define EUartUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div 2)
+#define EUartUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3)
+#define EUartUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4)
+#define EUartUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5)
+#define EUartUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6)
+#define EUartUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7)
+#define EUartUFCR_TXTL_SHF 10 // Transmitter trigger level shift
+#define EUartUSR1_PARITYERR (1 << 15) // Parity error interrupt flag
+#define EUartUSR1_RTSS (1 << 14) // RTS pin status
+#define EUartUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag
+#define EUartUSR1_RTSD (1 << 12) // RTS delta
+#define EUartUSR1_ESCF (1 << 11) // Escape seq interrupt flag
+#define EUartUSR1_FRAMERR (1 << 10) // Frame error interrupt flag
+#define EUartUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag
+#define EUartUSR1_AGTIM (1 << 8) // Aging timeout interrupt status
+#define EUartUSR1_RXDS (1 << 6) // Receiver idle interrupt flag
+#define EUartUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag
+#define EUartUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag
+#define EUartUSR2_ADET (1 << 15) // Auto baud rate detect complete
+#define EUartUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty
+#define EUartUSR2_IDLE (1 << 12) // Idle condition
+#define EUartUSR2_ACST (1 << 11) // Autobaud counter stopped
+#define EUartUSR2_IRINT (1 << 8) // Serial infrared interrupt flag
+#define EUartUSR2_WAKE (1 << 7) // Wake
+#define EUartUSR2_RTSF (1 << 4) // RTS edge interrupt flag
+#define EUartUSR2_TXDC (1 << 3) // Transmitter complete
+#define EUartUSR2_BRCD (1 << 2) // Break condition
+#define EUartUSR2_ORE (1 << 1) // Overrun error
+#define EUartUSR2_RDR (1 << 0) // Recv data ready
+#define EUartUTS_FRCPERR (1 << 13) // Force parity error
+#define EUartUTS_LOOP (1 << 12) // Loop tx and rx
+#define EUartUTS_TXEMPTY (1 << 6) // TxFIFO empty
+#define EUartUTS_RXEMPTY (1 << 5) // RxFIFO empty
+#define EUartUTS_TXFULL (1 << 4) // TxFIFO full
+#define EUartUTS_RXFULL (1 << 3) // RxFIFO full
+#define EUartUTS_SOFTRST (1 << 0) // Software reset
+
+#define EUartUFCR_RFDIV EUartUFCR_RFDIV_2
+//#define EUartUFCR_RFDIV EUartUFCR_RFDIV_4
+//#define EUartUFCR_RFDIV EUartUFCR_RFDIV_7
+
+#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_2)
+#define MXC_UART_REFFREQ (get_peri_clock(UART1_BAUD) / 2)
+#endif
+
+#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_4)
+#define MXC_UART_REFFREQ (get_peri_clock(UART1_BAUD) / 4)
+#endif
+
+#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_7)
+#define MXC_UART_REFFREQ (get_peri_clock(UART1_BAUD) / 7)
+#endif
+
+#if 0
+void
+cyg_hal_plf_comms_init(void)
+{
+ static int initialized = 0;
+
+ if (initialized)
+ return;
+
+ initialized = 1;
+
+ cyg_hal_plf_serial_init();
+}
+#endif
+
+//=============================================================================
+// MXC Serial Port (UARTx) for Debug
+//=============================================================================
+#ifdef UART_WIDTH_32
+struct mxc_serial {
+ volatile cyg_uint32 urxd[16];
+ volatile cyg_uint32 utxd[16];
+ volatile cyg_uint32 ucr1;
+ volatile cyg_uint32 ucr2;
+ volatile cyg_uint32 ucr3;
+ volatile cyg_uint32 ucr4;
+ volatile cyg_uint32 ufcr;
+ volatile cyg_uint32 usr1;
+ volatile cyg_uint32 usr2;
+ volatile cyg_uint32 uesc;
+ volatile cyg_uint32 utim;
+ volatile cyg_uint32 ubir;
+ volatile cyg_uint32 ubmr;
+ volatile cyg_uint32 ubrc;
+ volatile cyg_uint32 onems;
+ volatile cyg_uint32 uts;
+};
+#else
+struct mxc_serial {
+ volatile cyg_uint16 urxd[1];
+ volatile cyg_uint16 resv0[31];
+
+ volatile cyg_uint16 utxd[1];
+ volatile cyg_uint16 resv1[31];
+ volatile cyg_uint16 ucr1;
+ volatile cyg_uint16 resv2;
+ volatile cyg_uint16 ucr2;
+ volatile cyg_uint16 resv3;
+ volatile cyg_uint16 ucr3;
+ volatile cyg_uint16 resv4;
+ volatile cyg_uint16 ucr4;
+ volatile cyg_uint16 resv5;
+ volatile cyg_uint16 ufcr;
+ volatile cyg_uint16 resv6;
+ volatile cyg_uint16 usr1;
+ volatile cyg_uint16 resv7;
+ volatile cyg_uint16 usr2;
+ volatile cyg_uint16 resv8;
+ volatile cyg_uint16 uesc;
+ volatile cyg_uint16 resv9;
+ volatile cyg_uint16 utim;
+ volatile cyg_uint16 resv10;
+ volatile cyg_uint16 ubir;
+ volatile cyg_uint16 resv11;
+ volatile cyg_uint16 ubmr;
+ volatile cyg_uint16 resv12;
+ volatile cyg_uint16 ubrc;
+ volatile cyg_uint16 resv13;
+ volatile cyg_uint16 onems;
+ volatile cyg_uint16 resv14;
+ volatile cyg_uint16 uts;
+ volatile cyg_uint16 resv15;
+};
+#endif
+
+typedef struct {
+ volatile struct mxc_serial* base;
+ cyg_int32 msec_timeout;
+ int isr_vector;
+ int baud_rate;
+} channel_data_t;
+
+static channel_data_t channels[] = {
+#if CYGHWR_HAL_ARM_SOC_UART1 != 0
+ {(volatile struct mxc_serial*)UART1_BASE_ADDR, 1000,
+ CYGNUM_HAL_INTERRUPT_UART1, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#endif
+#if CYGHWR_HAL_ARM_SOC_UART2 != 0
+ {(volatile struct mxc_serial*)UART2_BASE_ADDR, 1000,
+ CYGNUM_HAL_INTERRUPT_UART2, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#endif
+#if CYGHWR_HAL_ARM_SOC_UART3 != 0
+ {(volatile struct mxc_serial*)UART3_BASE_ADDR, 1000,
+ CYGNUM_HAL_INTERRUPT_UART3, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#endif
+};
+
+/*---------------------------------------------------------------------------*/
+
+static void init_serial_channel(channel_data_t* __ch_data)
+{
+ volatile struct mxc_serial* base = __ch_data->base;
+
+ /* Wait for UART to finish transmitting */
+ while (!(base->uts & EUartUTS_TXEMPTY));
+
+ /* Disable UART */
+ base->ucr1 &= ~EUartUCR1_UARTEN;
+
+ /* Set to default POR state */
+ base->ucr1 = 0x00000000;
+ base->ucr2 = 0x00000000;
+
+ while (!(base->ucr2 & EUartUCR2_SRST_));
+
+ base->ucr3 = 0x00000704;
+ base->ucr4 = 0x00008000;
+ base->ufcr = 0x00000801;
+ base->uesc = 0x0000002B;
+ base->utim = 0x00000000;
+ base->ubir = 0x00000000;
+ base->ubmr = 0x00000000;
+ base->onems = 0x00000000;
+ base->uts = 0x00000000;
+
+ /* Configure FIFOs */
+ base->ufcr = (1 << EUartUFCR_RXTL_SHF) | EUartUFCR_RFDIV
+ | (2 << EUartUFCR_TXTL_SHF);
+
+ /* Setup One MS timer */
+ base->onems = (MXC_UART_REFFREQ / 1000);
+
+ /* Set to 8N1 */
+ base->ucr2 &= ~EUartUCR2_PREN;
+ base->ucr2 |= EUartUCR2_WS;
+ base->ucr2 &= ~EUartUCR2_STPB;
+
+ /* Ignore RTS */
+ base->ucr2 |= EUartUCR2_IRTS;
+
+ /* Enable UART */
+ base->ucr1 |= EUartUCR1_UARTEN;
+
+ /* Enable FIFOs */
+ base->ucr2 |= EUartUCR2_SRST_ | EUartUCR2_RXEN | EUartUCR2_TXEN;
+
+ /* Clear status flags */
+ base->usr2 |= EUartUSR2_ADET |
+ EUartUSR2_IDLE |
+ EUartUSR2_IRINT |
+ EUartUSR2_WAKE |
+ EUartUSR2_RTSF |
+ EUartUSR2_BRCD |
+ EUartUSR2_ORE |
+ EUartUSR2_RDR;
+
+ /* Clear status flags */
+ base->usr1 |= EUartUSR1_PARITYERR |
+ EUartUSR1_RTSD |
+ EUartUSR1_ESCF |
+ EUartUSR1_FRAMERR |
+ EUartUSR1_AIRINT |
+ EUartUSR1_AWAKE;
+
+ /* Set the numerator value minus one of the BRM ratio */
+ base->ubir = (__ch_data->baud_rate / 100) - 1;
+
+ /* Set the denominator value minus one of the BRM ratio */
+ base->ubmr = ((MXC_UART_REFFREQ / 1600) - 1);
+
+}
+
+static void stop_serial_channel(channel_data_t* __ch_data)
+{
+ volatile struct mxc_serial* base = __ch_data->base;
+
+ /* Wait for UART to finish transmitting */
+ while (!(base->uts & EUartUTS_TXEMPTY));
+
+ /* Disable UART */
+ base->ucr1 &= ~EUartUCR1_UARTEN;
+}
+
+//#define debug_uart_log_buf
+#ifdef debug_uart_log_buf
+#define DIAG_BUFSIZE 2048
+static char __log_buf[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+
+void cyg_hal_plf_serial_putc(void *__ch_data, char c)
+{
+ volatile struct mxc_serial* base = ((channel_data_t*)__ch_data)->base;
+
+#ifdef debug_uart_log_buf
+ __log_buf[diag_bp++] = c;
+ return;
+#endif
+
+ CYGARC_HAL_SAVE_GP();
+
+ // Wait for Tx FIFO not full
+ while (base->uts & EUartUTS_TXFULL)
+ ;
+ base->utxd[0] = c;
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool cyg_hal_plf_serial_getc_nonblock(void* __ch_data,
+ cyg_uint8* ch)
+{
+ volatile struct mxc_serial* base = ((channel_data_t*)__ch_data)->base;
+
+ // If receive fifo is empty, return false
+ if (base->uts & EUartUTS_RXEMPTY)
+ return false;
+
+ *ch = (char)base->urxd[0];
+
+ return true;
+}
+
+cyg_uint8 cyg_hal_plf_serial_getc(void* __ch_data)
+{
+ cyg_uint8 ch;
+ CYGARC_HAL_SAVE_GP();
+
+ while (!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
+
+ CYGARC_HAL_RESTORE_GP();
+ return ch;
+}
+
+static void cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while(__len-- > 0)
+ cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static void cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while (__len-- > 0)
+ *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool cyg_hal_plf_serial_getc_timeout(void* __ch_data,
+ cyg_uint8* ch)
+{
+ int delay_count;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_bool res;
+ CYGARC_HAL_SAVE_GP();
+
+ delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+
+ for(;;) {
+ res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
+ if (res || 0 == delay_count--)
+ break;
+
+ CYGACC_CALL_IF_DELAY_US(100);
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static int cyg_hal_plf_serial_control(void *__ch_data,
+ __comm_control_cmd_t __func, ...)
+{
+ static int irq_state = 0;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ int ret = -1;
+ va_list ap;
+
+ CYGARC_HAL_SAVE_GP();
+ va_start(ap, __func);
+
+ switch (__func) {
+ case __COMMCTL_GETBAUD:
+ ret = chan->baud_rate;
+ break;
+ case __COMMCTL_SETBAUD:
+ chan->baud_rate = va_arg(ap, cyg_int32);
+ // Should we verify this value here?
+ init_serial_channel(chan);
+ ret = 0;
+ break;
+ case __COMMCTL_IRQ_ENABLE:
+ irq_state = 1;
+
+ chan->base->ucr1 |= EUartUCR1_RRDYEN;
+
+ HAL_INTERRUPT_UNMASK(chan->isr_vector);
+ break;
+ case __COMMCTL_IRQ_DISABLE:
+ ret = irq_state;
+ irq_state = 0;
+
+ chan->base->ucr1 &= ~EUartUCR1_RRDYEN;
+
+ HAL_INTERRUPT_MASK(chan->isr_vector);
+ break;
+ case __COMMCTL_DBG_ISR_VECTOR:
+ ret = chan->isr_vector;
+ break;
+ case __COMMCTL_SET_TIMEOUT:
+ ret = chan->msec_timeout;
+ chan->msec_timeout = va_arg(ap, cyg_uint32);
+ break;
+ default:
+ break;
+ }
+ va_end(ap);
+ CYGARC_HAL_RESTORE_GP();
+ return ret;
+}
+
+static int cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
+ CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+ int res = 0;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ char c;
+
+ CYGARC_HAL_SAVE_GP();
+
+ cyg_drv_interrupt_acknowledge(chan->isr_vector);
+
+ *__ctrlc = 0;
+ if (!(chan->base->uts & EUartUTS_RXEMPTY)) {
+ c = (char)chan->base->urxd[0];
+
+ if (cyg_hal_is_break( &c , 1 ))
+ *__ctrlc = 1;
+
+ res = CYG_ISR_HANDLED;
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+void cyg_hal_plf_serial_init(void)
+{
+ hal_virtual_comm_table_t* comm;
+ int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ int i;
+ static int jjj = 0;
+
+ // Init channels
+#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
+ for (i = 0; i < NUMOF(channels); i++) {
+ init_serial_channel(&channels[i]);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(i+2);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+ if (jjj == 0) {
+ cyg_hal_plf_serial_putc(&channels[i], '+');
+ jjj++;
+ }
+ cyg_hal_plf_serial_putc(&channels[i], '+');
+ }
+
+ // Restore original console
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+void cyg_hal_plf_serial_stop(void)
+{
+ int i;
+
+ // Init channels
+#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
+ for (i = 0; i < NUMOF(channels); i++) {
+ stop_serial_channel(&channels[i]);
+ }
+}
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
+
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 2)
+#define __BASE ((void*)UART1_BASE_ADDR)
+#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART1
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 3)
+#define __BASE ((void*)UART2_BASE_ADDR)
+#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART2
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 4)
+#define __BASE ((void*)UART3_BASE_ADDR)
+#endif
+
+#ifdef __BASE
+
+#ifdef CYGSEM_HAL_ROM_MONITOR
+#define CYG_HAL_STARTUP_ROM
+#define CYG_HAL_STARTUP_ROMRAM
+#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#endif
+
+#if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define HAL_DIAG_USES_HARDWARE
+#elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
+#define HAL_DIAG_USES_HARDWARE
+#elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+#define HAL_DIAG_USES_HARDWARE
+#endif
+
+static channel_data_t channel = {
+ (volatile struct mxc_serial*)__BASE, 0, CYGHWR_HAL_GDB_PORT_VECTOR
+};
+
+#ifdef HAL_DIAG_USES_HARDWARE
+
+void hal_diag_init(void)
+{
+ static int init = 0;
+ char *msg = "\n\rARM eCos\n\r";
+ cyg_uint8 lcr;
+
+ if (init++) return;
+
+ init_serial_channel(&channel);
+
+ while (*msg) hal_diag_write_char(*msg++);
+}
+
+#ifdef DEBUG_DIAG
+#ifndef CYG_HAL_STARTUP_ROM
+#define DIAG_BUFSIZE 2048
+static char diag_buffer[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+#endif
+
+void hal_diag_write_char(char c)
+{
+#ifdef DEBUG_DIAG
+#ifndef CYG_HAL_STARTUP_ROM
+ diag_buffer[diag_bp++] = c;
+ if (diag_bp == sizeof(diag_buffer)) diag_bp = 0;
+#endif
+#endif
+ cyg_hal_plf_serial_putc(&channel, c);
+}
+
+void hal_diag_read_char(char *c)
+{
+ *c = cyg_hal_plf_serial_getc(&channel);
+}
+
+#else // not HAL_DIAG_USES_HARDWARE - it uses GDB protocol
+
+void hal_diag_read_char(char *c)
+{
+ *c = cyg_hal_plf_serial_getc(&channel);
+}
+
+void hal_diag_write_char(char c)
+{
+ static char line[100];
+ static int pos = 0;
+
+ // FIXME: Some LED blinking might be nice right here.
+
+ // No need to send CRs
+ if( c == '\r' ) return;
+
+ line[pos++] = c;
+
+ if (c == '\n' || pos == sizeof(line)) {
+ CYG_INTERRUPT_STATE old;
+
+ // Disable interrupts. This prevents GDB trying to interrupt us
+ // while we are in the middle of sending a packet. The serial
+ // receive interrupt will be seen when we re-enable interrupts
+ // later.
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+#else
+ HAL_DISABLE_INTERRUPTS(old);
+#endif
+
+ while (1) {
+ static char hex[] = "0123456789ABCDEF";
+ cyg_uint8 csum = 0;
+ int i;
+#ifndef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ char c1;
+#endif
+ cyg_hal_plf_serial_putc(&channel, '$');
+ cyg_hal_plf_serial_putc(&channel, 'O');
+ csum += 'O';
+ for(i = 0; i < pos; i++) {
+ char ch = line[i];
+ char h = hex[(ch>>4)&0xF];
+ char l = hex[ch&0xF];
+ cyg_hal_plf_serial_putc(&channel, h);
+ cyg_hal_plf_serial_putc(&channel, l);
+ csum += h;
+ csum += l;
+ }
+ cyg_hal_plf_serial_putc(&channel, '#');
+ cyg_hal_plf_serial_putc(&channel, hex[(csum>>4)&0xF]);
+ cyg_hal_plf_serial_putc(&channel, hex[csum&0xF]);
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+
+ break; // regardless
+
+#else // not CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT Ie. usually...
+
+ // Wait for the ACK character '+' from GDB here and handle
+ // receiving a ^C instead. This is the reason for this clause
+ // being a loop.
+ c1 = cyg_hal_plf_serial_getc(&channel);
+
+ if( c1 == '+' )
+ break; // a good acknowledge
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ cyg_drv_interrupt_acknowledge(CYGHWR_HAL_GDB_PORT_VECTOR);
+ if( c1 == 3 ) {
+ // Ctrl-C: breakpoint.
+ cyg_hal_gdb_interrupt(
+ (target_register_t)__builtin_return_address(0) );
+ break;
+ }
+#endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+
+#endif // ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ // otherwise, loop round again
+ }
+
+ pos = 0;
+
+ // And re-enable interrupts
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+#else
+ HAL_RESTORE_INTERRUPTS(old);
+#endif
+
+ }
+}
+#endif
+
+#endif // __BASE
+
+#endif // !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
+/* End of hal_diag.c */
--- /dev/null
+//==========================================================================
+//
+// soc_misc.c
+//
+// HAL misc board support code
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#include <redboot.h>
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_misc.h> // Size constants
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h> // Interrupt names
+#include <cyg/hal/hal_cache.h> // Cache control
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/hal_mm.h> // MMap table definitions
+
+#include <cyg/infra/diag.h> // diag_printf
+
+// Most initialization has already been done before we get here.
+// All we do here is set up the interrupt environment.
+// FIXME: some of the stuff in hal_platform_setup could be moved here.
+
+externC void plf_hardware_init(void);
+int _mxc_fis;
+
+/*
+ * System_rev will have the following format
+ * 31-12 = part # (0x31, 0x32, 0x27, 0x91131, 0x91321, etc)
+ * 11-8 = unused
+ * 7-4 = major (1.y)
+ * 3-0 = minor (x.0)
+ */
+unsigned int system_rev = CHIP_REV_1_0;
+static int find_correct_chip;
+extern char HAL_PLATFORM_EXTRA[20];
+extern int _mxc_fis;
+static int _reset_reason;
+
+struct soc_sbmr {
+ unsigned int bt_mem_ctl:2,
+ bt_bus_width:1,
+ bt_page_size:2,
+ rsv2:1,
+ bt_spare_size:1,
+ bt_mem_type:2,
+ rsv1:1,
+ bt_ecc_sel:1,
+ bt_usb_src_0:1,
+ bt_eeprom_cfg:1,
+ dir_bt_dis:1,
+ bmod:2,
+ bt_weim_muxed:2,
+ bt_spare:1,
+ bt_sdmmc_src:2,
+ bt_chih_freq_sel:2,
+ bt_i2c_src:2,
+ bt_uart_src:2,
+ bt_cspi_src:2,
+ rsv0:3;
+} __attribute__ ((packed));
+struct soc_sbmr *soc_sbmr = (struct soc_sbmr *) (SRC_BASE_ADDR + 0x4);
+/*
+ * This functions reads the IIM module and returns the system revision number.
+ * It returns the IIM silicon revision reg value if valid product rev is found.
+ . Otherwise, it returns -1.
+ */
+static int read_system_rev(void)
+{
+ int val;
+ int *rom_id_address;
+
+ rom_id_address = ROM_BASE_ADDRESS_VIRT + ROM_SI_REV_OFFSET;
+
+ val = readl(IIM_BASE_ADDR + IIM_PREV_OFF);
+
+ system_rev = 0x51 << PART_NUMBER_OFFSET; /* For MX51 Platform*/
+
+ /* Now trying to retrieve the silicon rev from IIM's SREV register */
+ return *rom_id_address;
+}
+
+#ifdef MXCFLASH_SELECT_NAND
+extern nfc_setup_func_t *nfc_setup;
+#endif
+unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz,
+ unsigned int is_mlc, unsigned int num_of_chips);
+void hal_hardware_init(void)
+{
+ int ver = read_system_rev();
+ unsigned int i;
+ unsigned int *fis_addr = (unsigned int *)IRAM_BASE_ADDR;
+
+ _reset_reason = readl(SRC_BASE_ADDR + 0x8);
+ switch (*fis_addr) {
+ case FROM_MMC_FLASH:
+ _mxc_fis = FROM_MMC_FLASH;
+ break;
+ case FROM_NAND_FLASH:
+ _mxc_fis = FROM_NAND_FLASH;
+ break;
+ case FROM_SPI_NOR_FLASH:
+ _mxc_fis = FROM_SPI_NOR_FLASH;
+ break;
+ default:
+ if (soc_sbmr->bt_mem_ctl == 0x3) {
+ if (soc_sbmr->bt_mem_type == 0) {
+ _mxc_fis = MMC_FLASH_BOOT;
+ } else if (soc_sbmr->bt_mem_type == 3) {
+ _mxc_fis = SPI_NOR_FLASH_BOOT;
+ }
+ } else if (soc_sbmr->bt_mem_ctl == 1) {
+ _mxc_fis = NAND_FLASH_BOOT;
+ }
+ }
+
+ find_correct_chip = ver;
+
+ if (ver != CHIP_VERSION_NONE) {
+ /* Valid product revision found. Check actual silicon rev from the ROM code. */
+ if (ver == 0x1) {
+ HAL_PLATFORM_EXTRA[5] = '1';
+ HAL_PLATFORM_EXTRA[7] = '0';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ } else if (ver == 0x2) {
+ HAL_PLATFORM_EXTRA[5] = '1';
+ HAL_PLATFORM_EXTRA[7] = '1';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 1 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ } else if (ver == 0x10) {
+ HAL_PLATFORM_EXTRA[5] = '2';
+ HAL_PLATFORM_EXTRA[7] = '0';
+ system_rev |= 2 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ } else {
+ HAL_PLATFORM_EXTRA[5] = 'x';
+ HAL_PLATFORM_EXTRA[7] = 'x';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ find_correct_chip = CHIP_VERSION_UNKNOWN;
+ }
+
+ }
+ // Enable caches
+ HAL_ICACHE_ENABLE();
+ HAL_DCACHE_ENABLE();
+
+ // enable EPIT and start it with 32KHz input clock
+ writel(0x00010000, EPIT_BASE_ADDR + EPITCR);
+
+ // make sure reset is complete
+ while ((readl(EPIT_BASE_ADDR + EPITCR) & 0x10000) != 0) {
+ }
+
+ writel(0x030E0002, EPIT_BASE_ADDR + EPITCR);
+ writel(0x030E0003, EPIT_BASE_ADDR + EPITCR);
+
+ writel(0, EPIT_BASE_ADDR + EPITCMPR); // always compare with 0
+
+ if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
+ // increase the WDOG timeout value to the max
+ writew(readw(WDOG_BASE_ADDR) | 0xFF00, WDOG_BASE_ADDR);
+ }
+
+ // Perform any platform specific initializations
+ plf_hardware_init();
+
+ // Set up eCos/ROM interfaces
+ hal_if_init();
+
+ // initial NAND setup
+ writel(0xFFFF0000, UNLOCK_BLK_ADD0_REG);
+ writel(0xFFFF0000, UNLOCK_BLK_ADD1_REG);
+ writel(0xFFFF0000, UNLOCK_BLK_ADD2_REG);
+ writel(0xFFFF0000, UNLOCK_BLK_ADD3_REG);
+ writel(0xFFFF0000, UNLOCK_BLK_ADD4_REG);
+ writel(0xFFFF0000, UNLOCK_BLK_ADD5_REG);
+ writel(0xFFFF0000, UNLOCK_BLK_ADD6_REG);
+ writel(0xFFFF0000, UNLOCK_BLK_ADD7_REG);
+
+ // unlock all the CS's
+ for (i = 0; i < 8; i++) {
+ writel(0x84 | (i << 3), NFC_WR_PROT_REG);
+ }
+ writel(0, NFC_IPC_REG);
+#ifdef MXCFLASH_SELECT_NAND
+ nfc_setup = (nfc_setup_func_t*)mxc_nfc_soc_setup;
+#endif
+}
+
+// -------------------------------------------------------------------------
+void hal_clock_initialize(cyg_uint32 period)
+{
+}
+
+// This routine is called during a clock interrupt.
+
+// Define this if you want to ensure that the clock is perfect (i.e. does
+// not drift). One reason to leave it turned off is that it costs some
+// us per system clock interrupt for this maintenance.
+#undef COMPENSATE_FOR_CLOCK_DRIFT
+
+void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
+{
+}
+
+// Read the current value of the clock, returning the number of hardware
+// "ticks" that have occurred (i.e. how far away the current value is from
+// the start)
+
+// Note: The "contract" for this function is that the value is the number
+// of hardware clocks that have happened since the last interrupt (i.e.
+// when it was reset). This value is used to measure interrupt latencies.
+// However, since the hardware counter runs freely, this routine computes
+// the difference between the current clock period and the number of hardware
+// ticks left before the next timer interrupt.
+void hal_clock_read(cyg_uint32 *pvalue)
+{
+}
+
+// This is to cope with the test read used by tm_basic with
+// CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY defined; we read the count ASAP
+// in the ISR, *before* resetting the clock. Which returns 1tick +
+// latency if we just use plain hal_clock_read().
+void hal_clock_latency(cyg_uint32 *pvalue)
+{
+}
+
+unsigned int hal_timer_count(void)
+{
+ return (0xFFFFFFFF - readl(EPIT_BASE_ADDR + EPITCNR));
+}
+
+#define WDT_MAGIC_1 0x5555
+#define WDT_MAGIC_2 0xAAAA
+#define MXC_WDT_WSR 0x2
+
+unsigned int i2c_base_addr[] = {
+ I2C_BASE_ADDR,
+ I2C2_BASE_ADDR,
+};
+unsigned int i2c_num = 2;
+
+//
+// Delay for some number of micro-seconds
+//
+void hal_delay_us(unsigned int usecs)
+{
+ /*
+ * This causes overflow.
+ * unsigned int delayCount = (usecs * 32768) / 1000000;
+ * So use the following one instead
+ */
+ unsigned int delayCount = (usecs * 512) / 15625;
+
+ if (delayCount == 0) {
+ return;
+ }
+
+ // issue the service sequence instructions
+ if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
+ writew(WDT_MAGIC_1, WDOG_BASE_ADDR + MXC_WDT_WSR);
+ writew(WDT_MAGIC_2, WDOG_BASE_ADDR + MXC_WDT_WSR);
+ }
+
+ writel(0x01, EPIT_BASE_ADDR + EPITSR); // clear the compare status bit
+
+ writel(delayCount, EPIT_BASE_ADDR + EPITLR);
+
+ while ((0x1 & readl(EPIT_BASE_ADDR + EPITSR)) == 0); // return until compare bit is set
+}
+
+// -------------------------------------------------------------------------
+
+// This routine is called to respond to a hardware interrupt (IRQ). It
+// should interrogate the hardware and return the IRQ vector number.
+int hal_IRQ_handler(void)
+{
+#ifdef HAL_EXTENDED_IRQ_HANDLER
+ cyg_uint32 index;
+
+ // Use platform specific IRQ handler, if defined
+ // Note: this macro should do a 'return' with the appropriate
+ // interrupt number if such an extended interrupt exists. The
+ // assumption is that the line after the macro starts 'normal' processing.
+ HAL_EXTENDED_IRQ_HANDLER(index);
+#endif
+
+ return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
+}
+
+//
+// Interrupt control
+//
+
+void hal_interrupt_mask(int vector)
+{
+// diag_printf("6hal_interrupt_mask(vector=%d) \n", vector);
+#ifdef HAL_EXTENDED_INTERRUPT_MASK
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_MASK(vector);
+#endif
+}
+
+void hal_interrupt_unmask(int vector)
+{
+// diag_printf("7hal_interrupt_unmask(vector=%d) \n", vector);
+
+#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_UNMASK(vector);
+#endif
+}
+
+void hal_interrupt_acknowledge(int vector)
+{
+
+// diag_printf("8hal_interrupt_acknowledge(vector=%d) \n", vector);
+#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector);
+#endif
+}
+
+void hal_interrupt_configure(int vector, int level, int up)
+{
+
+#ifdef HAL_EXTENDED_INTERRUPT_CONFIGURE
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_CONFIGURE(vector, level, up);
+#endif
+}
+
+void hal_interrupt_set_level(int vector, int level)
+{
+
+#ifdef HAL_EXTENDED_INTERRUPT_SET_LEVEL
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_SET_LEVEL(vector, level);
+#endif
+
+ // Interrupt priorities are not configurable.
+}
+
+unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz, unsigned int is_mlc, unsigned int num_of_chips)
+{
+ unsigned int nfc_config_reg3;
+
+ if (pg_sz == 2048 && io_sz == 8) {
+ writel(0x70202179, NFC_FLASH_CONFIG2_REG);
+ nfc_config_reg3 = 0x00160608 | ((num_of_chips - 1) << 12);
+ if (num_of_chips > 1)
+ nfc_config_reg3 |= 0x1;
+ writel(nfc_config_reg3, NFC_FLASH_CONFIG3_REG);
+ } else if (pg_sz == 4096 && io_sz == 8) {
+ // This only works for 4KB with 218 spare area size
+ writel(0x706D217A, NFC_FLASH_CONFIG2_REG); // default is 0x706D273A
+ nfc_config_reg3 = 0x00120608 | ((num_of_chips - 1) << 12);
+ if (num_of_chips > 1)
+ nfc_config_reg3 |= 0x1;
+ writel(nfc_config_reg3, NFC_FLASH_CONFIG3_REG);
+ } else {
+ diag_printf("not supported nand flash: pg_sz=%d, io_sz=%d\n",
+ pg_sz, io_sz);
+ while (1) {
+ }
+ }
+ return 0x30;
+}
+
+static void show_sys_info(void)
+{
+ if (find_correct_chip == CHIP_VERSION_UNKNOWN) {
+ diag_printf("Unrecognized chip version: 0x%x!!!\n", read_system_rev());
+ diag_printf("Assuming chip version=0x%x\n", system_rev);
+ } else if (find_correct_chip == CHIP_VERSION_NONE) {
+ diag_printf("Unrecognized chip: 0x%x!!!\n", readl(IIM_BASE_ADDR + IIM_PREV_OFF));
+ }
+
+ diag_printf("Reset reason: ");
+ switch (_reset_reason) {
+ case 0x09:
+ diag_printf("User reset\n");
+ break;
+ case 0x01:
+ diag_printf("Power-on reset\n");
+ break;
+ case 0x10:
+ case 0x11:
+ diag_printf("WDOG reset\n");
+ break;
+ default:
+ diag_printf("Unknown: 0x%x\n", _reset_reason);
+ }
+
+ if (_mxc_fis == MMC_FLASH_BOOT) {
+ diag_printf("fis/fconfig from MMC\n");
+ } else if (_mxc_fis == SPI_NOR_FLASH_BOOT) {
+ diag_printf("fis/fconfig from SPI-NOR\n");
+ } else if (_mxc_fis == NAND_FLASH_BOOT) {
+ diag_printf("fis/fconfig from NAND\n");
+ } else {
+ diag_printf("Use \"factive [MMC|SPI|NAND]\" to choose fis/fconfig storage\n");
+ }
+
+ //diag_printf("SBMR = 0x%x\n", readl(SRC_BASE_ADDR + 0x4));
+ diag_printf("Boot switch: ");
+ if (soc_sbmr->bmod == 0) {
+ diag_printf("INTERNAL\n");
+ } else if (soc_sbmr->bmod == 3){
+ diag_printf("BOOTSTRAP\n");
+ } else if (soc_sbmr->bmod == 0x1 && soc_sbmr->dir_bt_dis == 0) {
+ diag_printf("TEST EXEC\n");
+ } else {
+ diag_printf("UNKNOWN\n");
+ }
+ diag_printf("\t");
+ if (soc_sbmr->bt_mem_ctl == 0) {
+ diag_printf("WEIM: ");
+ if (soc_sbmr->bt_mem_type == 0) {
+ diag_printf("NOR");
+ } else if (soc_sbmr->bt_mem_type == 2) {
+ diag_printf("ONE NAND");
+ } else {
+ diag_printf("UNKNOWN");
+ }
+ } else if (soc_sbmr->bt_mem_ctl == 1) {
+ diag_printf("NAND: ADDR CYCLES:");
+ if (soc_sbmr->bt_mem_type == 0) {
+ diag_printf("3: ");
+ } else if (soc_sbmr->bt_mem_type == 1) {
+ diag_printf("4: ");
+ } else if (soc_sbmr->bt_mem_type == 2) {
+ diag_printf("5: ");
+ } else {
+ diag_printf("UNKNOWN: ");
+ }
+ if (soc_sbmr->bt_ecc_sel == 0) {
+ diag_printf("SLC: ");
+ } else {
+ diag_printf("MLC: ");
+ }
+ if (soc_sbmr->bt_spare_size == 0) {
+ diag_printf("128B spare (4-bit ECC): ");
+ } else {
+ diag_printf("218B spare (8-bit ECC): ");
+ }
+ diag_printf("PAGE SIZE: ");
+ if (soc_sbmr->bt_page_size == 0) {
+ diag_printf("512: ");
+ } else if (soc_sbmr->bt_page_size == 1) {
+ diag_printf("2K: ");
+ } else if (soc_sbmr->bt_page_size == 2) {
+ diag_printf("4K: ");
+ } else {
+ diag_printf("UNKNOWN: ");
+ }
+ diag_printf("BUS WIDTH: ");
+ if (soc_sbmr->bt_bus_width == 0) {
+ diag_printf("8");
+ } else {
+ diag_printf("16");
+ }
+ } else if (soc_sbmr->bt_mem_ctl == 3) {
+ diag_printf("EXPANSION: ");
+ if (soc_sbmr->bt_mem_type == 0) {
+ diag_printf("SD/MMC-%d", soc_sbmr->bt_sdmmc_src);
+ } else if (soc_sbmr->bt_mem_type == 2) {
+ diag_printf("I2C-NOR: ");
+ if (soc_sbmr->bt_sdmmc_src == 0) {
+ diag_printf("I2C-1");
+ } else if (soc_sbmr->bt_sdmmc_src == 1) {
+ diag_printf("I2C-2");
+ } else if (soc_sbmr->bt_sdmmc_src == 2) {
+ diag_printf("HS-I2C");
+ } else {
+ diag_printf("UNKNOWN");
+ }
+ } else if (soc_sbmr->bt_mem_type == 3) {
+ diag_printf("SPI-NOR: ");
+ if (soc_sbmr->bt_sdmmc_src == 0) {
+ diag_printf("eCSPI1");
+ } else if (soc_sbmr->bt_sdmmc_src == 1) {
+ diag_printf("eCSPI2");
+ } else if (soc_sbmr->bt_sdmmc_src == 2) {
+ diag_printf("CSPI");
+ } else {
+ diag_printf("UNKNOWN");
+ }
+ } else {
+ diag_printf("UNKNOWN");
+ }
+ } else {
+ diag_printf("UNKNOWN");
+ }
+ diag_printf("\n");
+}
+
+RedBoot_init(show_sys_info, RedBoot_INIT_LAST);
--- /dev/null
+//==========================================================================
+//
+// imx_usb.c
+//
+// usb download support for RedBoot
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002, 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Fisher ZHU
+// Contributors: Fisher ZHU
+// Date: 2008-10-27
+// Purpose:
+// Description: this code architecture is based on mxc_usb.c
+//
+// This code is part of RedBoot (tm).
+//
+// Revision History:
+// Date Author Comments
+// 2008-10-27 Fisher ZHU Initial Creation, support for i.mx37
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <redboot.h>
+#include <pkgconf/devs_usb_imx_otg.h>
+static struct {
+ bool open;
+ int total_timeouts, packets_received;
+ unsigned long last_good_block;
+ int avail, actual_len;
+// char data[SEGSIZE+sizeof(struct imxotghdr)];
+// char *bufp;
+} imxotg_stream;
+
+EXTERN unsigned long entry_address;
+EXTERN unsigned long load_address;
+EXTERN unsigned long load_address_end;
+
+extern cyg_uint32 usb_download_address;
+extern cyg_uint32 usb_download_length;
+
+extern void usbs_imx_otg_device_init(void);
+extern void usbs_imx_otg_device_deinit(void);
+#if defined(CYGBLD_IMX_USB_DOWNLOAD_SUPPORT)
+extern void usbs_imx_otg_download(unsigned char * buffer, unsigned int length);
+#endif
+
+int
+imxotg_stream_open(connection_info_t *info,
+ int *err)
+{
+ //diag_printf("%s()\n", __FUNCTION__);
+ usbs_imx_otg_device_init();
+ return 0;
+}
+
+void
+imxotg_stream_close(int *err)
+{
+ //diag_printf("%s()\n", __FUNCTION__);
+ usbs_imx_otg_device_deinit();
+}
+
+void
+imxotg_stream_terminate(bool abort,
+ int (*getc)(void))
+{
+ int err;
+ //diag_printf("%s()\n", __FUNCTION__);
+ load_address_end = load_address + usb_download_length;
+ entry_address = load_address;
+}
+
+int
+imxotg_stream_read(char *buf,
+ int len,
+ int *err)
+{
+
+ //diag_printf("%s(transfer length=%d,buffer address=0x%08x)\n", __FUNCTION__, len, buf);
+
+ /*buf and len are not used by usb download.
+ buf is a buffer pointer created by redboot, but USB download will download the binary file directly to
+ the memory pointed by load_address.
+ len is the buffer length, while USB download will download all the binary file once.
+ The two variables are actually dummy.*/
+ usb_download_address = load_address;
+ usbs_imx_otg_download(buf,len);
+ return 0;
+}
+
+char *
+imxotg_error(int err)
+{
+ char *errmsg = "Unknown error";
+
+ //diag_printf("%s()\n", __FUNCTION__);
+#if 0
+ switch (err) {
+ case MXCUSB_ENOTFOUND:
+ return "file not found";
+ case MXCUSB_EACCESS:
+ return "access violation";
+ case MXCUSB_ENOSPACE:
+ return "disk full or allocation exceeded";
+ case MXCUSB_EBADOP:
+ return "illegal MXCUSB operation";
+ case MXCUSB_EBADID:
+ return "unknown transfer ID";
+ case MXCUSB_EEXISTS:
+ return "file already exists";
+ case MXCUSB_ENOUSER:
+ return "no such user";
+ case MXCUSB_TIMEOUT:
+ return "operation timed out";
+ case MXCUSB_INVALID:
+ return "invalid parameter";
+ case MXCUSB_TOOLARGE:
+ return "file is larger than buffer";
+ }
+#endif
+ return errmsg;
+}
+
+//
+// RedBoot interface
+//
+GETC_IO_FUNCS(imxotg_io, imxotg_stream_open, imxotg_stream_close,
+ imxotg_stream_terminate, imxotg_stream_read, imxotg_error);
+RedBoot_load(usb, imxotg_io, true, false, 0);
+
+
projects / karo-tx-redboot.git / commitdiff