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+v2_0 packages/hal/h8300/aki3068net/current
+v2_0 packages/hal/h8300/arch/current
+v2_0 packages/hal/h8300/edosk2674/current
+v2_0 packages/hal/h8300/h8300h/current
+v2_0 packages/hal/h8300/h8max/current
+v2_0 packages/hal/h8300/h8s/current
+v2_0 packages/hal/h8300/sim/current
+v2_0 packages/hal/h8300/sim_s/current
+v2_0 packages/hal/i386/arch/current
+v2_0 packages/hal/i386/generic/current
+v2_0 packages/hal/i386/pc/current
+v2_0 packages/hal/i386/pcmb/current
+v2_0 packages/hal/m68k/arch/current
+v2_0 packages/hal/m68k/mcf52xx/mcf5272/mcf5272c3/plf/current
+v2_0 packages/hal/m68k/mcf52xx/mcf5272/proc/current
+v2_0 packages/hal/m68k/mcf52xx/var/current
+v2_0 packages/hal/mips/arch/current
+v2_0 packages/hal/mips/atlas/current
+v2_0 packages/hal/mips/idt32334/current
+v2_0 packages/hal/mips/idt79s334a/current
+v2_0 packages/hal/mips/jmr3904/current
+v2_0 packages/hal/mips/malta/current
+v2_0 packages/hal/mips/mips32/current
+v2_0 packages/hal/mips/mips64/current
+v2_0 packages/hal/mips/ref4955/current
+v2_0 packages/hal/mips/rm7000/ocelot/current
+v2_0 packages/hal/mips/rm7000/var/current
+v2_0 packages/hal/mips/sim/current
+v2_0 packages/hal/mips/tx39/current
+v2_0 packages/hal/mips/tx49/current
+v2_0 packages/hal/mips/upd985xx/current
+v2_0 packages/hal/mips/vr4300/current
+v2_0 packages/hal/mips/vrc4373/current
+v2_0 packages/hal/mips/vrc4375/current
+v2_0 packages/hal/mips/vrc437x/current
+v2_0 packages/hal/mn10300/am31/current
+v2_0 packages/hal/mn10300/am33/current
+v2_0 packages/hal/mn10300/arch/current
+v2_0 packages/hal/mn10300/asb/current
+v2_0 packages/hal/mn10300/asb2305/current
+v2_0 packages/hal/mn10300/sim/current
+v2_0 packages/hal/mn10300/stb/current
+v2_0 packages/hal/mn10300/stdeval1/current
+v2_0 packages/hal/openrisc/arch/current
+v2_0 packages/hal/openrisc/orp/current
+v2_0 packages/hal/powerpc/adder/current
+v2_0 packages/hal/powerpc/arch/current
+v2_0 packages/hal/powerpc/cme555/current
+v2_0 packages/hal/powerpc/cogent/current
+v2_0 packages/hal/powerpc/csb281/current
+v2_0 packages/hal/powerpc/ec555/current
+v2_0 packages/hal/powerpc/fads/current
+v2_0 packages/hal/powerpc/mbx/current
+v2_0 packages/hal/powerpc/moab/current
+v2_0 packages/hal/powerpc/mpc5xx/current
+v2_0 packages/hal/powerpc/mpc8260/current
+v2_0 packages/hal/powerpc/mpc8xx/current
+v2_0 packages/hal/powerpc/mpc8xxx/current
+v2_0 packages/hal/powerpc/ppc40x/current
+v2_0 packages/hal/powerpc/ppc60x/current
+v2_0 packages/hal/powerpc/quicc/current
+v2_0 packages/hal/powerpc/rattler/current
+v2_0 packages/hal/powerpc/sim/current
+v2_0 packages/hal/powerpc/ts1000/current
+v2_0 packages/hal/powerpc/ts6/current
+v2_0 packages/hal/powerpc/vads/current
+v2_0 packages/hal/powerpc/viper/current
+v2_0 packages/hal/sh/arch/current
+v2_0 packages/hal/sh/cq7708/current
+v2_0 packages/hal/sh/cq7750/current
+v2_0 packages/hal/sh/dreamcast/current
+v2_0 packages/hal/sh/edk7708/current
+v2_0 packages/hal/sh/hs7729pci/current
+v2_0 packages/hal/sh/se7751/current
+v2_0 packages/hal/sh/se77x9/current
+v2_0 packages/hal/sh/sh2/current
+v2_0 packages/hal/sh/sh3/current
+v2_0 packages/hal/sh/sh4/current
+v2_0 packages/hal/sh/sh4_202_md/current
+v2_0 packages/hal/sparc/arch/current
+v2_0 packages/hal/sparc/erc32/current
+v2_0 packages/hal/sparc/leon/current
+v2_0 packages/hal/sparclite/arch/current
+v2_0 packages/hal/sparclite/sim/current
+v2_0 packages/hal/sparclite/sleb/current
+v2_0 packages/hal/synth/arch/current
+v2_0 packages/hal/synth/i386linux/current
+v2_0 packages/hal/v85x/arch/current
+v2_0 packages/hal/v85x/ceb_v850/current
+v2_0 packages/hal/v85x/v850/current
+v2_0 packages/infra/current
+v2_0 packages/io/can/current
+v2_0 packages/io/common/current
+v2_0 packages/io/disk/current
+v2_0 packages/io/eth/current
+v2_0 packages/io/fileio/current
+v2_0 packages/io/flash/current
+v2_0 packages/io/i2c/current
+v2_0 packages/io/pci/current
+v2_0 packages/io/pcmcia/current
+v2_0 packages/io/serial/current
+v2_0 packages/io/spi/current
+v2_0 packages/io/usb/common/current
+v2_0 packages/io/usb/eth/slave/current
+v2_0 packages/io/usb/serial/slave/current
+v2_0 packages/io/usb/slave/current
+v2_0 packages/io/wallclock/current
+v2_0 packages/io/watchdog/current
+v2_0 packages/isoinfra/current
+v2_0 packages/kernel/current
+v2_0 packages/language/c/libc/common/current
+v2_0 packages/language/c/libc/i18n/current
+v2_0 packages/language/c/libc/setjmp/current
+v2_0 packages/language/c/libc/signals/current
+v2_0 packages/language/c/libc/startup/current
+v2_0 packages/language/c/libc/stdio/current
+v2_0 packages/language/c/libc/stdlib/current
+v2_0 packages/language/c/libc/string/current
+v2_0 packages/language/c/libc/time/current
+v2_0 packages/language/c/libm/current
+v2_0 packages/net/athttpd/current
+v2_0 packages/net/autotest/current
+v2_0 packages/net/bsd_tcpip/current
+v2_0 packages/net/common/current
+v2_0 packages/net/ftpclient/current
+v2_0 packages/net/httpd/current
+v2_0 packages/net/ipsec/libipsec/current
+v2_0 packages/net/lwip_tcpip/current
+v2_0 packages/net/ns/dns/current
+v2_0 packages/net/ppp/current
+v2_0 packages/net/snmp/agent/current
+v2_0 packages/net/snmp/lib/current
+v2_0 packages/net/sntp/current
+v2_0 packages/net/tcpip/current
+v2_0 packages/net/vnc_server/current
+v2_0 packages/redboot/current
+v2_0 packages/services/blib/current
+v2_0 packages/services/compress/zlib/current
+v2_0 packages/services/cpuload/current
+v2_0 packages/services/crc/current
+v2_0 packages/services/diagnosis/current
+v2_0 packages/services/ezxml/current
+v2_0 packages/services/gfx/mw/current
+v2_0 packages/services/loader/current
+v2_0 packages/services/memalloc/common/current
+v2_0 packages/services/objloader/current
+v2_0 packages/services/power/common/current
+v2_0 packages/services/profile/gprof/current
#!/bin/sh
options="cnqrR"
release=false
-tools_dir=${HOME}/projects/RedBoot/ecos/tools/bin/
-src_dir=$PWD/packages
+tools_dir="$PWD/tools/bin"
+ecosconfig="$tools_dir/tools/configtool/standalone/common/ecosconfig"
+src_dir="$PWD/packages"
quiet=false
clean=false
rebuild=false
doit=true
make_opts=
+cmd_prefix=${CROSS_COMPILE-arm-926ejs-linux-gnu-}
+
error() {
if [ -n "${target}" ];then
echo "${target} build aborted"
fi
}
+build_host_tools() {
+ echo "Building host tools in $tools_dir"
+
+ local wd="$PWD"
+ local tcldirs="/usr/lib/tcl /usr/local/lib/tcl"
+ local config_opts=""
+ for d in $tcldirs;do
+ if [ -d "$d" ];then
+ config_opts="$config_opts --with-tcl=${d%lib/tcl}"
+ break
+ fi
+ done
+ if [ -z "$config_opts" ];then
+ for d in /usr/lib/tcl*;do
+ config_opts="$config_opts --with-tcl-version=${d##*tcl}"
+ done
+ fi
+ if [ -z "$config_opts" ];then
+ echo "No Tcl installation found"
+ exit 1
+ fi
+
+ mkdir -p "$tools_dir"
+ cd "$tools_dir"
+ sh ../src/configure $config_opts
+ make
+ cd "$wd"
+}
+
if [ `uname -s` = Linux ];then
- PATH=/usr/local/arm/cross-gcc-1.2.0/i686-pc-linux-gnu/bin:$PATH
-# PATH=/usr/local/arm/cross-gcc-3.4.3-2.6.17/i686-pc-linux-gnu/bin:$PATH
-# PATH=/usr/local/arm/cross-gcc/i686-pc-linux-gnu/bin:$PATH
- PATH=$tools_dir:$PATH
-else
- PATH=$PWD/host/tools/configtool:$PWD/build/tools/src/tools/configtool/standalone/common/:$PATH
+ PATH="/usr/local/arm/cross-gcc-4.2.0/i686-pc-linux-gnu/bin:$PATH"
fi
-ECOSCONFIG=$tools_dir/ecosconfig
-
while getopts "$options" opt;do
case $opt in
c)
done
shift $(($OPTIND - 1))
-cmd_prefix=${CROSS_COMPILE-arm-linux-}
-
if [ $# -gt 0 ];then
targets="$@"
else
fi
set -e
+trap error 0
conf_dir="$PWD/config"
[ -d build ] || mkdir -p build
cd build
wd=$PWD
-trap error 0
+if [ ! -x "${ecosconfig}" ];then
+ build_host_tools
+fi
for target in ${targets};do
target="${target%.ecc}"
if [ ! -d "${target}" ];then
inst_dir="$PWD/${target}_install"
$quiet || echo "Checking configuration ${target}"
+ cp -p "${conf_dir}/${target}.ecc" "${conf_dir}/${target}.ecc.bak"
echo ecosconfig --srcdir="$src_dir" --config="${conf_dir}/${target}.ecc" check
- $doit && ${ECOSCONFIG} --srcdir="$src_dir" --config="${conf_dir}/${target}.ecc" check
+ if $doit;then
+ stty -isig # prevent CTRL-C from trashing the config file
+ set +e
+ "${ecosconfig}" --srcdir="$src_dir" --config="${conf_dir}/${target}.ecc" check
+ if [ $? != 0 ];then
+ mv "${conf_dir}/${target}.ecc.bak" "${conf_dir}/${target}.ecc"
+ exit 1
+ fi
+ set -e
+ stty isig
+ fi
if $rebuild;then
echo "Removing build dir ${build_dir} and ${inst_dir}"
echo mkdir "${build_dir}"
$doit && mkdir "${build_dir}"
fi
- echo ecosconfig --srcdir="$src_dir" --prefix="${inst_dir}" --config="${conf_dir}/${target}.ecc" tree
+ $doit && cd "${build_dir}"
+ echo ecosconfig --srcdir="$src_dir" --prefix="${inst_dir}" \
+ --config="${conf_dir}/${target}.ecc" tree
if $doit;then
- cd "${build_dir}"
- ${ECOSCONFIG} --srcdir="$src_dir" --prefix="${inst_dir}" --config="${conf_dir}/${target}.ecc" tree
- rm -f ${target} ../../current && ln -svf ${target} ../../current
- rm -f ../install && ln -svf ${target}_install ../install
- rm -f ../build && ln -svf ${target}_build ../build
+ stty -isig
+ "${ecosconfig}" --srcdir="$src_dir" --prefix="${inst_dir}" \
+ --config="${conf_dir}/${target}.ecc" tree
+ stty isig
+ rm -f "${target}" ../../current && ln -svf "${target}" ../../current
+ rm -f ../install && ln -svf "${target}_install" ../install
+ rm -f ../build && ln -svf "${target}_build" ../build
fi
if $clean;then
fi
$quiet || echo "Compiling ${target}"
- [ -d "${build_dir}" ] && make -C "${build_dir}" COMMAND_PREFIX=${cmd_prefix} ${make_opts}
+ [ -d "${build_dir}" ]
+ make -C "${build_dir}" COMMAND_PREFIX=${cmd_prefix} ${make_opts}
cd $wd
if $doit && [ -s "${inst_dir}/bin/redboot.elf" ];then
- ${cmd_prefix}objdump -d "${inst_dir}/bin/redboot.elf" | grep '<Now_in_SDRAM>:' | grep -v 'a1f00[89a-f]'
+ bootstrap_addr="$(${cmd_prefix}nm "${inst_dir}/bin/redboot.elf" \
+ | sed '/Now_in_SDRAM/!d;s/ .*$//')"
+ if ! echo "$bootstrap_addr" | grep -i '^[0-9a-f]\{4\}0[0-7]';then
+# if ! ${cmd_prefix}nm "${inst_dir}/bin/redboot.elf" \
+# | grep 'Now_in_SDRAM' | grep -i '^[0-9a-f]\{4\}0[0-7]';then
+ echo "ERROR: Bootstrap does not fit into first NAND page!"
+ echo $bootstrap_addr
+ exit 1
+ fi
fi
echo "${target} build finished"
-done
+done
trap - 0
--- /dev/null
+# eCos saved configuration
+
+# ---- commands --------------------------------------------------------
+# This section contains information about the savefile format.
+# It should not be edited. Any modifications made to this section
+# may make it impossible for the configuration tools to read
+# the savefile.
+
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+# ---- toplevel --------------------------------------------------------
+# This section defines the toplevel configuration object. The only
+# values that can be changed are the name of the configuration and
+# the description field. It is not possible to modify the target,
+# the template or the set of packages simply by editing the lines
+# below because these changes have wide-ranging effects. Instead
+# the appropriate tools should be used to make such modifications.
+
+cdl_configuration eCos {
+ description "" ;
+
+ # These fields should not be modified.
+ hardware tx25karo ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM current ;
+ package -hardware CYGPKG_HAL_ARM_MX25 current ;
+ package -hardware CYGPKG_HAL_ARM_TX25KARO current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_TX25 current ;
+ package -hardware CYGPKG_DEVS_ETH_FEC current ;
+ package -hardware CYGPKG_COMPRESS_ZLIB current ;
+ package -hardware CYGPKG_IO_FLASH current ;
+ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+ package -template CYGPKG_MEMALLOC current ;
+ package -template CYGPKG_DEVS_ETH_PHY current ;
+ package -template CYGPKG_LIBC_I18N current ;
+ package -template CYGPKG_LIBC_STDLIB current ;
+ package -template CYGPKG_ERROR current ;
+};
+
+# ---- conflicts -------------------------------------------------------
+# There are no conflicts.
+
+# ---- contents --------------------------------------------------------
+# >
+# >
+# Global build options
+# Global build options including control over
+# compiler flags, linker flags and choice of toolchain.
+#
+cdl_component CYGBLD_GLOBAL_OPTIONS {
+ # There is no associated value.
+
+ # The following properties are affected by this value
+};
+
+# >
+# Global command prefix
+# This option specifies the command prefix used when
+# invoking the build tools.
+#
+cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value arm-926ejs-linux-gnu
+ # value_source default
+ # Default value: arm-926ejs-linux-gnu
+};
+
+# Global compiler flags
+# This option controls the global compiler flags which are used to
+# compile all packages by default. Individual packages may define
+# options which override these global flags.
+#
+cdl_option CYGBLD_GLOBAL_CFLAGS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe"
+ # value_source default
+ # Default value: "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe"
+ # Requires: CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS
+ # CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS
+ # Requires: is_substr(CYGBLD_GLOBAL_CFLAGS, " -Werror")
+ # option CYGBLD_INFRA_CFLAGS_PIPE
+ # Requires: is_substr(CYGBLD_GLOBAL_CFLAGS, " -pipe")
+};
+
+# Global linker flags
+# This option controls the global linker flags. Individual
+# packages may define options which override these global flags.
+#
+cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-Wl,--gc-sections -Wl,-static -O2 -nostdlib"
+ # value_source default
+ # Default value: "-Wl,--gc-sections -Wl,-static -O2 -nostdlib"
+};
+
+# Build common GDB stub ROM image
+# Unless a target board has specific requirements to the
+# stub implementation, it can use a simple common stub.
+# This option, which gets enabled by platform HALs as
+# appropriate, controls the building of the common stub.
+#
+cdl_option CYGBLD_BUILD_COMMON_GDB_STUBS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+};
+
+# <
+# ISO C library string functions
+# doc: ref/libc.html
+# This package provides string functions specified by the
+# ISO C standard - ISO/IEC 9899:1990.
+#
+cdl_package CYGPKG_LIBC_STRING {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER == "<cyg/libc/string/string.h>"
+ # CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER == <cyg/libc/string/string.h>
+ # --> 1
+ # Requires: CYGBLD_ISO_STRING_MEMFUNCS_HEADER == "<cyg/libc/string/string.h>"
+ # CYGBLD_ISO_STRING_MEMFUNCS_HEADER == <cyg/libc/string/string.h>
+ # --> 1
+ # Requires: CYGBLD_ISO_STRING_STRFUNCS_HEADER == "<cyg/libc/string/string.h>"
+ # CYGBLD_ISO_STRING_STRFUNCS_HEADER == <cyg/libc/string/string.h>
+ # --> 1
+ # Requires: CYGBLD_ISO_STRTOK_R_HEADER == "<cyg/libc/string/string.h>"
+ # CYGBLD_ISO_STRTOK_R_HEADER == <cyg/libc/string/string.h>
+ # --> 1
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+};
+
+# >
+# Inline versions of <string.h> functions
+# This option chooses whether some of the
+# particularly simple string functions from
+# <string.h> are available as inline
+# functions. This may improve performance, and as
+# the functions are small, may even improve code
+# size.
+#
+cdl_option CYGIMP_LIBC_STRING_INLINES {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Optimize string functions for code size
+# This option tries to reduce string function
+# code size at the expense of execution speed. The
+# same effect can be produced if the code is
+# compiled with the -Os option to the compiler.
+#
+cdl_option CYGIMP_LIBC_STRING_PREFER_SMALL_TO_FAST {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Provide BSD compatibility functions
+# Enabling this option causes various compatibility functions
+# commonly found in the BSD UNIX operating system to be included.
+# These are functions such as bzero, bcmp, bcopy, bzero, strcasecmp,
+# strncasecmp, index, rindex and swab.
+#
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+ # Requires: CYGBLD_ISO_STRING_BSD_FUNCS_HEADER == "<cyg/libc/string/bsdstring.h>"
+ # CYGBLD_ISO_STRING_BSD_FUNCS_HEADER == <cyg/libc/string/bsdstring.h>
+ # --> 1
+ # Requires: CYGINT_ISO_CTYPE
+ # CYGINT_ISO_CTYPE == 1
+ # --> 1
+};
+
+# strtok
+# These options control the behaviour of the
+# strtok() and strtok_r() string tokenization
+# functions.
+#
+cdl_component CYGPKG_LIBC_STRING_STRTOK {
+ # There is no associated value.
+};
+
+# >
+# Per-thread strtok()
+# This option controls whether the string function
+# strtok() has its state recorded on a per-thread
+# basis rather than global. If this option is
+# disabled, some per-thread space can be saved.
+# Note there is also a POSIX-standard strtok_r()
+# function to achieve a similar effect with user
+# support. Enabling this option will use one slot
+# of kernel per-thread data. You should ensure you
+# have enough slots configured for all your
+# per-thread data.
+#
+cdl_option CYGSEM_LIBC_STRING_PER_THREAD_STRTOK {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGVAR_KERNEL_THREADS_DATA
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+ # Requires: CYGVAR_KERNEL_THREADS_DATA
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+};
+
+# Tracing level
+# Trace verbosity level for debugging the <string.h>
+# functions strtok() and strtok_r(). Increase this
+# value to get additional trace output.
+#
+cdl_option CYGNUM_LIBC_STRING_STRTOK_TRACE_LEVEL {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to 1
+};
+
+# <
+# strdup
+# This option indicates whether strdup() is to be supported.
+#
+cdl_option CYGFUN_LIBC_STRING_STRDUP {
+ # ActiveIf constraint: CYGINT_ISO_MALLOC
+ # CYGINT_ISO_MALLOC == 1
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+};
+
+# C library string functions build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_LIBC_STRING_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the C library. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_LIBC_STRING_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-fno-rtti -Woverloaded-virtual"
+ # value_source default
+ # Default value: "-fno-rtti -Woverloaded-virtual"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the C library. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_LIBC_STRING_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wno-pointer-sign
+ # value_source default
+ # Default value: -Wno-pointer-sign
+};
+
+# C library string function tests
+# This option specifies the set of tests for the C library
+# string functions.
+#
+cdl_option CYGPKG_LIBC_STRING_TESTS {
+ # Calculated value: "tests/memchr tests/memcmp1 tests/memcmp2 tests/memcpy1 tests/memcpy2 tests/memmove1 tests/memmove2 tests/memset tests/strcat1 tests/strcat2 tests/strchr tests/strcmp1 tests/strcmp2 tests/strcoll1 tests/strcoll2 tests/strcpy1 tests/strcpy2 tests/strcspn tests/strcspn tests/strlen tests/strncat1 tests/strncat2 tests/strncpy1 tests/strncpy2 tests/strpbrk tests/strrchr tests/strspn tests/strstr tests/strtok tests/strxfrm1 tests/strxfrm2"
+ # Flavor: data
+ # Current_value: tests/memchr tests/memcmp1 tests/memcmp2 tests/memcpy1 tests/memcpy2 tests/memmove1 tests/memmove2 tests/memset tests/strcat1 tests/strcat2 tests/strchr tests/strcmp1 tests/strcmp2 tests/strcoll1 tests/strcoll2 tests/strcpy1 tests/strcpy2 tests/strcspn tests/strcspn tests/strlen tests/strncat1 tests/strncat2 tests/strncpy1 tests/strncpy2 tests/strpbrk tests/strrchr tests/strspn tests/strstr tests/strtok tests/strxfrm1 tests/strxfrm2
+};
+
+# <
+# <
+# Common ethernet support
+# doc: ref/io-eth-drv-generic.html
+# Platform independent ethernet drivers
+#
+cdl_package CYGPKG_IO_ETH_DRIVERS {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # component CYGPKG_REDBOOT_NETWORKING
+ # ActiveIf: CYGPKG_IO_ETH_DRIVERS
+ # package CYGPKG_DEVS_ETH_ARM_TX25
+ # ActiveIf: CYGPKG_IO_ETH_DRIVERS
+ # package CYGPKG_DEVS_ETH_FEC
+ # ActiveIf: CYGPKG_IO_ETH_DRIVERS
+ # package CYGPKG_DEVS_ETH_PHY
+ # ActiveIf: CYGPKG_IO_ETH_DRIVERS
+};
+
+# >
+# Network drivers
+#
+cdl_interface CYGHWR_NET_DRIVERS {
+ # Implemented by CYGPKG_DEVS_ETH_FEC, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGDAT_REDBOOT_DEFAULT_NETWORK_DEVICE
+ # ActiveIf: CYGHWR_NET_DRIVERS > 1
+ # option CYGSEM_REDBOOT_NETWORK_INIT_ONE_DEVICE
+ # ActiveIf: CYGHWR_NET_DRIVERS > 1
+};
+
+# Driver supports multicast addressing
+# This interface defines whether or not a driver can handle
+# requests for multicast addressing.
+#
+cdl_interface CYGINT_IO_ETH_MULTICAST {
+ # Implemented by CYGPKG_DEVS_ETH_FEC, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+};
+
+# Support printing driver debug information
+# Selecting this option will include code to allow the driver to
+# print lots of information on diagnostic output such as full
+# packet dumps.
+#
+cdl_component CYGDBG_IO_ETH_DRIVERS_DEBUG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Driver debug output verbosity
+# The value of this option indicates the default verbosity
+# level of debugging output. 0 means no debugging output
+# is made by default. Higher values indicate higher verbosity.
+# The verbosity level may also be changed at run time by
+# changing the variable cyg_io_eth_net_debug.
+#
+cdl_option CYGDBG_IO_ETH_DRIVERS_DEBUG_VERBOSITY {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Size of scatter-gather I/O lists
+# A scatter-gather list is used to pass requests to/from
+# the physical device driver. This list can typically be
+# small, as the data is normally already packed into reasonable
+# chunks.
+#
+cdl_option CYGNUM_IO_ETH_DRIVERS_SG_LIST_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 32
+ # value_source default
+ # Default value: 32
+};
+
+# Support for standard eCos TCP/IP stack.
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_NET {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_NET
+ # CYGPKG_NET (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+};
+
+# >
+# Warn when there are no more mbufs
+# Warnings about running out of mbufs are printed to the
+# diagnostic output channel via diag_printf() if this option
+# is enabled. Mbufs are the network stack's basic dynamic
+# memory objects that hold all packets in transit; running
+# out is bad for performance but not fatal, not a crash.
+# You might want to turn off the warnings to preserve realtime
+# properties of the system even in extremis.
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_WARN_NO_MBUFS {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_NET is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Simulate network failures for testing
+# This package contains a suite of simulated failure modes
+# for the ethernet device layer, including dropping and/or
+# corrupting received packets, dropping packets queued for
+# transmission, and simulating a complete network break.
+# It requires the kernel as a source of time information.
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_NET is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# >
+# Drop incoming packets (percentage)
+#
+cdl_option CYGPKG_IO_ETH_DRIVERS_SIMULATE_DROP_RX {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 1 10
+ # value_source default
+ # Default value: 1 10
+ # Legal values: 10 50 80
+};
+
+# Corrupt incoming packets (percentage)
+#
+cdl_option CYGPKG_IO_ETH_DRIVERS_SIMULATE_CORRUPT_RX {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 1 10
+ # value_source default
+ # Default value: 1 10
+ # Legal values: 10 50 80
+};
+
+# Drop outgoing packets (percentage)
+#
+cdl_option CYGPKG_IO_ETH_DRIVERS_SIMULATE_DROP_TX {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 1 10
+ # value_source default
+ # Default value: 1 10
+ # Legal values: 10 50 80
+};
+
+# Simulate a line cut from time to time
+# This option causes the system to drop all packets for a
+# short random period (10s of seconds), and then act
+# normally for up to 4 times that long. This simulates your
+# sysadmin fiddling with plugs in the network switch
+# cupboard.
+#
+cdl_option CYGPKG_IO_ETH_DRIVERS_SIMULATE_LINE_CUT {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# <
+# Support for stand-alone network stack.
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_STAND_ALONE {
+ # ActiveIf constraint: !CYGPKG_NET
+ # CYGPKG_NET (unknown) == 0
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGINT_ISO_STRING_MEMFUNCS
+ # CYGINT_ISO_STRING_MEMFUNCS == 1
+ # --> 1
+};
+
+# >
+# Pass packets to an alternate stack
+# Define this to allow packets seen by this layer to be
+# passed on to the previous logical layer, i.e. when
+# stand-alone processing replaces system (eCos) processing.
+#
+cdl_option CYGSEM_IO_ETH_DRIVERS_PASS_PACKETS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 0 != CYGPKG_REDBOOT_NETWORKING
+ # CYGPKG_REDBOOT_NETWORKING == 1
+ # --> 1
+};
+
+# Number of [network] buffers
+# This option is used to allocate space to buffer incoming network
+# packets. These buffers are used to hold data until they can be
+# logically processed by higher layers.
+#
+cdl_option CYGNUM_IO_ETH_DRIVERS_NUM_PKT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 4
+ # value_source default
+ # Default value: 4
+ # Legal values: 2 to 32
+};
+
+# Show driver warnings
+# Selecting this option will allows the stand-alone ethernet driver
+# to display warnings on the system console when incoming network
+# packets are being discarded due to lack of buffer space.
+#
+cdl_option CYGSEM_IO_ETH_DRIVERS_WARN {
+ # ActiveIf constraint: CYGPKG_REDBOOT
+ # CYGPKG_REDBOOT == current
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Support for lwIP network stack.
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_LWIP {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_NET_LWIP
+ # CYGPKG_NET_LWIP (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: !CYGPKG_NET
+ # CYGPKG_NET (unknown) == 0
+ # --> 1
+};
+
+# Interrupt support required
+# This interface is used to indicate to the low
+# level device drivers that interrupt driven operation
+# is required by higher layers.
+#
+cdl_interface CYGINT_IO_ETH_INT_SUPPORT_REQUIRED {
+ # Implemented by CYGPKG_IO_ETH_DRIVERS_NET, inactive, enabled
+ # Implemented by CYGPKG_IO_ETH_DRIVERS_LWIP, inactive, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+
+ # The following properties are affected by this value
+};
+
+# Common ethernet support build options
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the common ethernet support package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_IO_ETH_DRIVERS_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-D_KERNEL -D__ECOS"
+ # value_source default
+ # Default value: "-D_KERNEL -D__ECOS"
+};
+
+# <
+# Ethernet driver for Ka-Ro electronics TX25 processor module
+#
+cdl_package CYGPKG_DEVS_ETH_ARM_TX25 {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # ActiveIf constraint: CYGPKG_IO_ETH_DRIVERS
+ # CYGPKG_IO_ETH_DRIVERS == current
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+};
+
+# >
+# FEC ethernet driver required
+#
+cdl_interface CYGINT_DEVS_ETH_FEC_REQUIRED {
+ # Implemented by CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # package CYGPKG_DEVS_ETH_FEC
+ # ActiveIf: CYGINT_DEVS_ETH_FEC_REQUIRED
+};
+
+# Ka-Ro TX25 ethernet port driver
+# This option includes the ethernet device driver for the
+# MXC Board port.
+#
+cdl_component CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ # CYGSEM_REDBOOT_PLF_ESA_VALIDATE == 1
+ # --> 1
+ # Requires: CYGHWR_DEVS_ETH_PHY_LAN8700
+ # CYGHWR_DEVS_ETH_PHY_LAN8700 == 1
+ # --> 1
+};
+
+# >
+# Device name for the ETH0 ethernet driver
+# This option sets the name of the ethernet device.
+#
+cdl_option CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "\"eth0\""
+ # value_source default
+ # Default value: "\"eth0\""
+};
+
+# OUI part of MAC address
+# This option sets OUI part (manufacturer ID) of the MAC address
+# for validation.
+#
+cdl_option CYGDAT_DEVS_ETH_ARM_TX25KARO_OUI {
+ # ActiveIf constraint: CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ # CYGSEM_REDBOOT_PLF_ESA_VALIDATE == 1
+ # --> 1
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "{ 0x00, 0x0c, 0xc6 }"
+ # value_source default
+ # Default value: "{ 0x00, 0x0c, 0xc6 }"
+};
+
+# <
+# <
+# Driver for fast ethernet controller.
+# Driver for fast ethernet controller.
+#
+cdl_package CYGPKG_DEVS_ETH_FEC {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # ActiveIf constraint: CYGPKG_IO_ETH_DRIVERS
+ # CYGPKG_IO_ETH_DRIVERS == current
+ # --> 1
+ # ActiveIf constraint: CYGINT_DEVS_ETH_FEC_REQUIRED
+ # CYGINT_DEVS_ETH_FEC_REQUIRED == 1
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+};
+
+# >
+# MXC FEC ethernet driver build options
+#
+cdl_component CYGPKG_DEVS_ETH_FEC_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the Cirrus Logic ethernet driver package.
+# These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_DEVS_ETH_FEC_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-D_KERNEL -D__ECOS"
+ # value_source default
+ # Default value: "-D_KERNEL -D__ECOS"
+};
+
+# <
+# <
+# Ethernet transceiver (PHY) support
+# API for ethernet PHY devices
+#
+cdl_package CYGPKG_DEVS_ETH_PHY {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # ActiveIf constraint: CYGPKG_IO_ETH_DRIVERS
+ # CYGPKG_IO_ETH_DRIVERS == current
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT == 1
+ # --> 1
+};
+
+# >
+# Enable driver debugging
+# Enables the diagnostic debug messages on the
+# console device.
+#
+cdl_option CYGDBG_DEVS_ETH_PHY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Time period (seconds) to wait for auto-negotiation
+# The length of time to wait for auto-negotiation to complete
+# before giving up and declaring the link dead/missing.
+#
+cdl_option CYGINT_DEVS_ETH_PHY_AUTO_NEGOTIATION_TIME {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 5
+ # value_source default
+ # Default value: 5
+};
+
+# NSDP83847
+# Include support for National Semiconductor DP83847 DsPHYTER II
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_DP83847 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# AMD 79C874
+# Include support for AMD 79C874 NetPHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_AM79C874 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Intel LXT972
+# Include support for Intel LXT972xxx PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_INLXT972 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# ICS 1890
+# Include support for ICS 1890 PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_ICS1890 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# ICS 1892
+# Include support for ICS 1892 PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_ICS1892 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# ICS 1893
+# Include support for ICS 1893 and 1893AF PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_ICS1893 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Davicom DM9161A
+# Include support for the Davicom DM9161A PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_DM9161A {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Micrel KS8721
+# Include support for the Micrel KS8721 PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_KS8721 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# SMSC LAN8700
+# Include support for SMSC LAN8700 NetPHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_LAN8700 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # component CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
+ # Requires: CYGHWR_DEVS_ETH_PHY_LAN8700
+};
+
+# <
+# <
+# ISO C library internationalization functions
+# doc: ref/libc.html
+# This package provides internationalization functions specified by the
+# ISO C standard - ISO/IEC 9899:1990. These include locale-related
+# functionality and <ctype.h> functionality.
+#
+cdl_package CYGPKG_LIBC_I18N {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+};
+
+# >
+# Supported locales
+# These options determine which locales other than the "C" locale
+# are supported and hence contribute to the size of the executable.
+#
+cdl_component CYGPKG_LIBC_I18N_LOCALES {
+ # There is no associated value.
+};
+
+# >
+# Support for multiple locales required
+#
+cdl_interface CYGINT_LIBC_I18N_MB_REQUIRED {
+ # Implemented by CYGFUN_LIBC_I18N_LOCALE_C_SJIS, active, disabled
+ # Implemented by CYGFUN_LIBC_I18N_LOCALE_C_JIS, active, disabled
+ # Implemented by CYGFUN_LIBC_I18N_LOCALE_C_EUCJP, active, disabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: CYGBLD_ISO_STDLIB_MB_CUR_MAX_HEADER == "<cyg/libc/i18n/mb.h>"
+ # CYGBLD_ISO_STDLIB_MB_CUR_MAX_HEADER == 0
+ # --> 0
+
+ # The following properties are affected by this value
+};
+
+# C-SJIS locale support
+# This option controls if the "C-SJIS" locale will be
+# supported by setlocale(). The locale is a hybrid locale
+# that is mostly the "C" locale with Japanese SJIS multibyte
+# support added.
+#
+cdl_option CYGFUN_LIBC_I18N_LOCALE_C_SJIS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # LegalValues: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2))) to 0x7fffffff
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # DefaultValue: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2)))
+};
+
+# C-JIS locale support
+# This option controls if the "C-JIS" locale will be
+# supported by setlocale(). The locale is a hybrid locale
+# that is mostly the "C" locale with Japanese JIS multibyte
+# support added.
+#
+cdl_option CYGFUN_LIBC_I18N_LOCALE_C_JIS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # LegalValues: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2))) to 0x7fffffff
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # DefaultValue: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2)))
+};
+
+# C-EUCJP locale support
+# This option controls if the "C-EUCJP" locale will be
+# supported by setlocale(). The locale is a hybrid locale
+# that is mostly the "C" locale with Japanese EUCJP multibyte
+# support added.
+#
+cdl_option CYGFUN_LIBC_I18N_LOCALE_C_EUCJP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # LegalValues: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2))) to 0x7fffffff
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # DefaultValue: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2)))
+};
+
+# <
+# Newlib's ctype implementation
+# This option enables the implementation of the ctype functions
+# that comes with newlib. It is table driven and therefore
+# exhibits different performance characteristics. It also offers
+# a limited amount of binary compatibility
+# with newlib so that programs linked against newlib ctype/locale
+# do not need to be recompiled when linked with eCos.
+#
+cdl_option CYGPKG_LIBC_I18N_NEWLIB_CTYPE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGBLD_ISO_CTYPE_HEADER == "<cyg/libc/i18n/newlibctype.h>"
+ # CYGBLD_ISO_CTYPE_HEADER == <cyg/libc/i18n/ctype.inl>
+ # --> 0
+};
+
+# Per-thread multibyte state
+# This option controls whether the multibyte character
+# handling functions mblen(), mbtowc(), and wctomb(),
+# have their state recorded on a per-thread
+# basis rather than global. If this option is
+# disabled, some per-thread space can be saved.
+# Enabling this option will use three slots
+# of kernel per-thread data. You should ensure you
+# have enough slots configured for all your
+# per-thread data.
+#
+cdl_option CYGSEM_LIBC_I18N_PER_THREAD_MB {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGVAR_KERNEL_THREADS_DATA != 0
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+ # Requires: CYGVAR_KERNEL_THREADS_DATA
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+};
+
+# Size of locale name strings
+# This option controls the maximum size of
+# locale names and is used, among other things
+# to instantiate a static string used
+# as a return value from the
+# setlocale() function. When requesting the
+# current locale settings with LC_ALL, a string
+# must be constructed to contain this data, rather
+# than just returning a constant string. This
+# string data is stored in the static string.
+# This depends on the length of locale names,
+# hence this option. If just the C locale is
+# present, this option can be set as low as 2.
+#
+cdl_option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 2
+ # value_source default
+ # Default value: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2)))
+ # CYGFUN_LIBC_I18N_LOCALE_C_EUCJP == 0
+ # CYGFUN_LIBC_I18N_LOCALE_C_SJIS == 0
+ # CYGFUN_LIBC_I18N_LOCALE_C_JIS == 0
+ # --> 2
+ # Legal values: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2))) to 0x7fffffff
+ # CYGFUN_LIBC_I18N_LOCALE_C_EUCJP == 0
+ # CYGFUN_LIBC_I18N_LOCALE_C_SJIS == 0
+ # CYGFUN_LIBC_I18N_LOCALE_C_JIS == 0
+};
+
+# Inline versions of <ctype.h> functions
+# This option chooses whether the simple character
+# classification and conversion functions (e.g.
+# isupper(), isalpha(), toupper(), etc.)
+# from <ctype.h> are available as inline
+# functions. This may improve performance and as
+# the functions are small, may even improve code
+# size.
+#
+cdl_option CYGIMP_LIBC_I18N_CTYPE_INLINES {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_CTYPE_HEADER == "<cyg/libc/i18n/ctype.inl>"
+ # CYGBLD_ISO_CTYPE_HEADER == <cyg/libc/i18n/ctype.inl>
+ # --> 1
+};
+
+# C library i18n functions build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_LIBC_I18N_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the C library. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_LIBC_I18N_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-fno-rtti -Woverloaded-virtual"
+ # value_source default
+ # Default value: "-fno-rtti -Woverloaded-virtual"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the C library. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_LIBC_I18N_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wno-pointer-sign
+ # value_source default
+ # Default value: -Wno-pointer-sign
+};
+
+# C library i18n function tests
+# This option specifies the set of tests for the C library
+# i18n functions.
+#
+cdl_option CYGPKG_LIBC_I18N_TESTS {
+ # Calculated value: "tests/ctype tests/setlocale tests/i18nmb"
+ # Flavor: data
+ # Current_value: tests/ctype tests/setlocale tests/i18nmb
+};
+
+# <
+# <
+# ISO C library general utility functions
+# doc: ref/libc.html
+# This package provides general utility functions in <stdlib.h>
+# as specified by the ISO C standard - ISO/IEC 9899:1990.
+#
+cdl_package CYGPKG_LIBC_STDLIB {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+ # Requires: CYGINT_ISO_CTYPE
+ # CYGINT_ISO_CTYPE == 1
+ # --> 1
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+};
+
+# >
+# Inline versions of <stdlib.h> functions
+# This option chooses whether some of the
+# particularly simple standard utility functions
+# from <stdlib.h> are available as inline
+# functions. This may improve performance, and as
+# the functions are small, may even improve code
+# size.
+#
+cdl_component CYGIMP_LIBC_STDLIB_INLINES {
+ # There is no associated value.
+};
+
+# >
+# abs() / labs()
+#
+cdl_option CYGIMP_LIBC_STDLIB_INLINE_ABS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_STDLIB_ABS_HEADER == "<cyg/libc/stdlib/abs.inl>"
+ # CYGBLD_ISO_STDLIB_ABS_HEADER == <cyg/libc/stdlib/abs.inl>
+ # --> 1
+};
+
+# div() / ldiv()
+#
+cdl_option CYGIMP_LIBC_STDLIB_INLINE_DIV {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_STDLIB_DIV_HEADER == "<cyg/libc/stdlib/div.inl>"
+ # CYGBLD_ISO_STDLIB_DIV_HEADER == <cyg/libc/stdlib/div.inl>
+ # --> 1
+};
+
+# atof() / atoi() / atol()
+#
+cdl_option CYGIMP_LIBC_STDLIB_INLINE_ATOX {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_STDLIB_STRCONV_HEADER == "<cyg/libc/stdlib/atox.inl>"
+ # CYGBLD_ISO_STDLIB_STRCONV_HEADER == <cyg/libc/stdlib/atox.inl>
+ # --> 1
+};
+
+# <
+# Random number generation
+# These options control the behaviour of the
+# functions rand(), srand() and rand_r()
+#
+cdl_component CYGPKG_LIBC_RAND {
+ # There is no associated value.
+};
+
+# >
+# Per-thread random seed
+# doc: ref/libc-thread-safety.html
+# This option controls whether the pseudo-random
+# number generation functions rand() and srand()
+# have their state recorded on a per-thread
+# basis rather than global. If this option is
+# disabled, some per-thread space can be saved.
+# Note there is also a POSIX-standard rand_r()
+# function to achieve a similar effect with user
+# support. Enabling this option will use one slot
+# of kernel per-thread data. You should ensure you
+# have enough slots configured for all your
+# per-thread data.
+#
+cdl_option CYGSEM_LIBC_PER_THREAD_RAND {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGVAR_KERNEL_THREADS_DATA
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+};
+
+# Random number seed
+# This selects the initial random number seed for
+# rand()'s pseudo-random number generator. For
+# strict ISO standard compliance, this should be 1,
+# as per section 7.10.2.2 of the standard.
+#
+cdl_option CYGNUM_LIBC_RAND_SEED {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Legal values: 0 to 0x7fffffff
+};
+
+# Tracing level
+# Trace verbosity level for debugging the rand(),
+# srand() and rand_r() functions. Increase this
+# value to get additional trace output.
+#
+cdl_option CYGNUM_LIBC_RAND_TRACE_LEVEL {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to 1
+};
+
+# Simplest implementation
+# This provides a very simple implementation of rand()
+# that does not perform well with randomness in the
+# lower significant bits. However it is exceptionally
+# fast. It uses the sample algorithm from the ISO C
+# standard itself.
+#
+cdl_option CYGIMP_LIBC_RAND_SIMPLEST {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Simple implementation #1
+# This provides a very simple implementation of rand()
+# based on the simplest implementation above. However
+# it does try to work around the lack of randomness
+# in the lower significant bits, at the expense of a
+# little speed.
+#
+cdl_option CYGIMP_LIBC_RAND_SIMPLE1 {
+ # Flavor: bool
+ user_value 0
+ # value_source user
+ # Default value: 1
+};
+
+# Knuth implementation #1
+# This implements a slightly more complex algorithm
+# published in Donald E. Knuth's Art of Computer
+# Programming Vol.2 section 3.6 (p.185 in the 3rd ed.).
+# This produces better random numbers than the
+# simplest approach but is slower.
+#
+cdl_option CYGIMP_LIBC_RAND_KNUTH1 {
+ # Flavor: bool
+ user_value 1
+ # value_source user
+ # Default value: 0
+};
+
+# <
+# Provides strtod()
+# This option allows use of the utility function
+# strtod() (and consequently atof()) to convert
+# from string to double precision floating point
+# numbers. Disabling this option removes the
+# dependency on the math library package.
+#
+cdl_option CYGFUN_LIBC_strtod {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0 != CYGPKG_LIBM
+ # CYGPKG_LIBM (unknown) == 0
+ # --> 0
+ # Requires: CYGPKG_LIBM
+ # CYGPKG_LIBM (unknown) == 0
+ # --> 0
+};
+
+# Provides long long conversion functions
+# Enabling this option will provide support for the strtoll(),
+# strtoull() and atoll() conversion functions, which are
+# the long long variants of the standard versions of these
+# functions. Supporting this requires extra code and compile
+# time.
+#
+cdl_option CYGFUN_LIBC_STDLIB_CONV_LONGLONG {
+ # Flavor: bool
+ user_value 0
+ # value_source user
+ # Default value: 1
+};
+
+# bsearch() tracing level
+# Trace verbosity level for debugging the <stdlib.h>
+# binary search function bsearch(). Increase this
+# value to get additional trace output.
+#
+cdl_option CYGNUM_LIBC_BSEARCH_TRACE_LEVEL {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to 1
+};
+
+# qsort() tracing level
+# Trace verbosity level for debugging the <stdlib.h>
+# quicksort function qsort(). Increase this value
+# to get additional trace output.
+#
+cdl_option CYGNUM_LIBC_QSORT_TRACE_LEVEL {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to 1
+};
+
+# C library stdlib build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_LIBC_STDLIB_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_LIBC_STDLIB_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-fno-rtti -Woverloaded-virtual"
+ # value_source default
+ # Default value: "-fno-rtti -Woverloaded-virtual"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_LIBC_STDLIB_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wno-pointer-sign
+ # value_source default
+ # Default value: -Wno-pointer-sign
+};
+
+# C library stdlib tests
+# This option specifies the set of tests for this package.
+#
+cdl_option CYGPKG_LIBC_STDLIB_TESTS {
+ # Calculated value: "tests/abs tests/atoi tests/atol tests/bsearch tests/div tests/getenv tests/labs tests/ldiv tests/qsort tests/rand1 tests/rand2 tests/rand3 tests/rand4 tests/srand tests/strtol tests/strtoul"
+ # Flavor: data
+ # Current_value: tests/abs tests/atoi tests/atol tests/bsearch tests/div tests/getenv tests/labs tests/ldiv tests/qsort tests/rand1 tests/rand2 tests/rand3 tests/rand4 tests/srand tests/strtol tests/strtoul
+};
+
+# <
+# <
+# <
+# eCos HAL
+# doc: ref/the-ecos-hardware-abstraction-layer.html
+# The eCos HAL package provide a porting layer for
+# higher-level parts of the system such as the kernel and the
+# C library. Each installation should have HAL packages for
+# one or more architectures, and for each architecture there
+# may be one or more supported platforms. It is necessary to
+# select one target architecture and one platform for that
+# architecture. There are also a number of configuration
+# options that are common to all HAL packages.
+#
+cdl_package CYGPKG_HAL {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGPKG_INFRA
+ # CYGPKG_INFRA == current
+ # --> 1
+
+ # The following properties are affected by this value
+};
+
+# >
+# Platform-independent HAL options
+# A number of configuration options are common to most or all
+# HAL packages, for example options controlling how much state
+# should be saved during a context switch. The implementations
+# of these options will vary from architecture to architecture.
+#
+cdl_component CYGPKG_HAL_COMMON {
+ # There is no associated value.
+};
+
+# >
+# Provide eCos kernel support
+# The HAL can be configured to either support the full eCos
+# kernel, or to support only very simple applications which do
+# not require a full kernel. If kernel support is not required
+# then some of the startup, exception, and interrupt handling
+# code can be eliminated.
+#
+cdl_option CYGFUN_HAL_COMMON_KERNEL_SUPPORT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+ # Requires: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+};
+
+# HAL exception support
+# When a processor exception occurs, for example an attempt to
+# execute an illegal instruction or to perform a divide by
+# zero, this exception may be handled in a number of different
+# ways. If the target system has gdb support then typically
+# the exception will be handled by gdb code. Otherwise if the
+# HAL exception support is enabled then the HAL will invoke a
+# routine deliver_exception(). Typically this routine will be
+# provided by the eCos kernel, but it is possible for
+# application code to provide its own implementation. If the
+# HAL exception support is not enabled and a processor
+# exception occurs then the behaviour of the system is
+# undefined.
+#
+cdl_option CYGPKG_HAL_EXCEPTIONS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGPKG_KERNEL_EXCEPTIONS
+ # CYGPKG_KERNEL_EXCEPTIONS (unknown) == 0
+ # --> 0
+ # Requires: CYGPKG_KERNEL_EXCEPTIONS
+ # CYGPKG_KERNEL_EXCEPTIONS (unknown) == 0
+ # --> 0
+};
+
+# Stop calling constructors early
+# This option supports environments where some constructors
+# must be run in the context of a thread rather than at
+# simple system startup time. A boolean flag named
+# cyg_hal_stop_constructors is set to 1 when constructors
+# should no longer be invoked. It is up to some other
+# package to deal with the rest of the constructors.
+# In the current version this is only possible with the
+# C library.
+#
+cdl_option CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGSEM_LIBC_INVOKE_DEFAULT_STATIC_CONSTRUCTORS
+ # CYGSEM_LIBC_INVOKE_DEFAULT_STATIC_CONSTRUCTORS (unknown) == 0
+ # --> 0
+};
+
+# HAL uses the MMU and allows for CDL manipulation of it's use
+#
+cdl_interface CYGINT_HAL_SUPPORTS_MMU_TABLES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_INSTALL_MMU_TABLES
+ # ActiveIf: CYGINT_HAL_SUPPORTS_MMU_TABLES
+};
+
+# Install MMU tables.
+# This option controls whether this application installs
+# its own Memory Management Unit (MMU) tables, or relies on the
+# existing environment to run.
+#
+cdl_option CYGSEM_HAL_INSTALL_MMU_TABLES {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_HAL_SUPPORTS_MMU_TABLES
+ # CYGINT_HAL_SUPPORTS_MMU_TABLES == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYG_HAL_STARTUP != "RAM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_STATIC_MMU_TABLES
+ # Requires: CYGSEM_HAL_INSTALL_MMU_TABLES
+};
+
+# Use static MMU tables.
+# This option defines an environment where any Memory
+# Management Unit (MMU) tables are constant. Normally used by ROM
+# based environments, this provides a way to save RAM usage which
+# would otherwise be required for these tables.
+#
+cdl_option CYGSEM_HAL_STATIC_MMU_TABLES {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGSEM_HAL_INSTALL_MMU_TABLES
+ # CYGSEM_HAL_INSTALL_MMU_TABLES == 0
+ # --> 0
+};
+
+# Route diagnostic output to debug channel
+# If not inheriting the console setup from the ROM monitor,
+# it is possible to redirect diagnostic output to the debug
+# channel by enabling this option. Depending on the debugger
+# used it may also be necessary to select a mangler for the
+# output to be displayed by the debugger.
+#
+cdl_component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN {
+ # ActiveIf constraint: !CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE == 0
+ # --> 1
+ # ActiveIf constraint: CYGPKG_HAL_ARM || CYGPKG_HAL_POWERPC_MPC8xx || CYGPKG_HAL_V85X_V850 || CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+ # CYGPKG_HAL_ARM == current
+ # CYGPKG_HAL_POWERPC_MPC8xx (unknown) == 0
+ # CYGPKG_HAL_V85X_V850 (unknown) == 0
+ # CYGSEM_HAL_VIRTUAL_VECTOR_DIAG == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: (CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS || CYG_HAL_STARTUP == "RAM") ? 1 : 0
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 0
+
+ # The following properties are affected by this value
+ # option CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ # Calculated: !CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE && !CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+};
+
+# >
+# Mangler used on diag output
+# It is sometimes necessary to mangle (encode) the
+# diag ASCII text output in order for it to show up at the
+# other end. In particular, GDB may silently ignore raw
+# ASCII text.
+#
+cdl_option CYGSEM_HAL_DIAG_MANGLER {
+ # This option is not active
+ # The parent CYGDBG_HAL_DIAG_TO_DEBUG_CHAN is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value GDB
+ # value_source default
+ # Default value: GDB
+ # Legal values: "GDB" "None"
+};
+
+# <
+# <
+# HAL interrupt handling
+# A number of configuration options related to interrupt
+# handling are common to most or all HAL packages, even though
+# the implementations will vary from architecture to
+# architecture.
+#
+cdl_component CYGPKG_HAL_COMMON_INTERRUPTS {
+ # There is no associated value.
+};
+
+# >
+# Use separate stack for interrupts
+# When an interrupt occurs this interrupt can be handled either
+# on the current stack or on a separate stack maintained by the
+# HAL. Using a separate stack requires a small number of extra
+# instructions in the interrupt handling code, but it has the
+# advantage that it is no longer necessary to allow extra space
+# in every thread stack for the interrupt handlers. The amount
+# of extra space required depends on the interrupt handlers
+# that are being used.
+#
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # package CYGPKG_REDBOOT
+ # Requires: CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK == 0
+};
+
+# Interrupt stack size
+# This configuration option specifies the stack size in bytes
+# for the interrupt stack. Typically this should be a multiple
+# of 16, but the exact requirements will vary from architecture
+# to architecture. The interrupt stack serves two separate
+# purposes. It is used as the stack during system
+# initialization. In addition, if the interrupt system is
+# configured to use a separate stack then all interrupts will
+# be processed on this stack. The exact memory requirements
+# will vary from application to application, and will depend
+# heavily on whether or not other interrupt-related options,
+# for example nested interrupts, are enabled. On most targets,
+# in a configuration with no kernel this stack will also be
+# the stack used to invoke the application, and must obviously
+# be appropriately large in that case.
+#
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 32768
+ # value_source default
+ # Default value: CYGPKG_KERNEL ? 4096 : 32768
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 32768
+ # Legal values: 128 to 1048576
+};
+
+# Allow nested interrupts
+# When an interrupt occurs the HAL interrupt handling code can
+# either leave interrupts disabled for the duration of the
+# interrupt handling code, or by doing some extra work it can
+# reenable interrupts before invoking the interrupt handler and
+# thus allow nested interrupts to happen. If all the interrupt
+# handlers being used are small and do not involve any loops
+# then it is usually better to disallow nested interrupts.
+# However if any of the interrupt handlers are more complicated
+# than nested interrupts will usually be required.
+#
+cdl_option CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Save minimum context on interrupt
+# The HAL interrupt handling code can exploit the calling conventions
+# defined for a given architecture to reduce the amount of state
+# that has to be saved. Generally this improves performance and
+# reduces code size. However it can make source-level debugging
+# more difficult.
+#
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # Requires: ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+};
+
+# Chain all interrupts together
+# Interrupts can be attached to vectors either singly, or be
+# chained together. The latter is necessary if there is no way
+# of discovering which device has interrupted without
+# inspecting the device itself. It can also reduce the amount
+# of RAM needed for interrupt decoding tables and code.
+#
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Ignore spurious [fleeting] interrupts
+# On some hardware, interrupt sources may not be de-bounced or
+# de-glitched. Rather than try to handle these interrupts (no
+# handling may be possible), this option allows the HAL to simply
+# ignore them. In most cases, if the interrupt is real it will
+# reoccur in a detectable form.
+#
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# HAL context switch support
+# A number of configuration options related to thread contexts
+# are common to most or all HAL packages, even though the
+# implementations will vary from architecture to architecture.
+#
+cdl_component CYGPKG_HAL_COMMON_CONTEXT {
+ # There is no associated value.
+
+ # The following properties are affected by this value
+};
+
+# >
+# Use minimum thread context
+# The thread context switch code can exploit the calling
+# conventions defined for a given architecture to reduce the
+# amount of state that has to be saved during a context
+# switch. Generally this improves performance and reduces
+# code size. However it can make source-level debugging more
+# difficult.
+#
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # Requires: ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+};
+
+# <
+# Explicit control over cache behaviour
+# These options let the default behaviour of the caches
+# be easily configurable.
+#
+cdl_component CYGPKG_HAL_CACHE_CONTROL {
+ # There is no associated value.
+};
+
+# >
+# Enable DATA cache on startup
+# Enabling this option will cause the data cache to be enabled
+# as soon as practicable when eCos starts up. One would choose
+# to disable this if the data cache cannot safely be turned on,
+# such as a case where the cache(s) require additional platform
+# specific setup.
+#
+cdl_component CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# DATA cache mode on startup
+# This option controls the mode the cache will be set to
+# when enabled on startup.
+#
+cdl_option CYGSEM_HAL_DCACHE_STARTUP_MODE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value COPYBACK
+ # value_source default
+ # Default value: COPYBACK
+ # Legal values: "COPYBACK" "WRITETHRU"
+};
+
+# <
+# Enable INSTRUCTION cache on startup
+# Enabling this option will cause the instruction cache to be enabled
+# as soon as practicable when eCos starts up. One would choose
+# to disable this if the instruction cache cannot safely be turned on,
+# such as a case where the cache(s) require additional platform
+# specific setup.
+#
+cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Source-level debugging support
+# If the source level debugger gdb is to be used for debugging
+# application code then it may be necessary to configure in support
+# for this in the HAL.
+#
+cdl_component CYGPKG_HAL_DEBUG {
+ # There is no associated value.
+};
+
+# >
+# Support for GDB stubs
+# The HAL implements GDB stubs for the target.
+#
+cdl_interface CYGINT_HAL_DEBUG_GDB_STUBS {
+ # Implemented by CYGPKG_HAL_ARM_TX25KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # ActiveIf: CYGINT_HAL_DEBUG_GDB_STUBS
+ # option CYGBLD_BUILD_REDBOOT_WITH_GDB
+ # ActiveIf: CYGINT_HAL_DEBUG_GDB_STUBS
+};
+
+# Include GDB stubs in HAL
+# This option causes a set of GDB stubs to be included into the
+# system. On some target systems the GDB support will be
+# provided by other means, for example by a ROM monitor. On
+# other targets, especially when building a ROM-booting system,
+# the necessary support has to go into the target library
+# itself. When GDB stubs are include in a configuration, HAL
+# serial drivers must also be included.
+#
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ # ActiveIf constraint: CYGINT_HAL_DEBUG_GDB_STUBS
+ # CYGINT_HAL_DEBUG_GDB_STUBS == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 0
+ # Requires: ! CYGSEM_HAL_USE_ROM_MONITOR
+ # CYGSEM_HAL_USE_ROM_MONITOR == 0
+ # --> 1
+ # Requires: ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ # CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT == 0
+ # --> 1
+ # Requires: ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ # CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM == 0
+ # --> 1
+ # Requires: !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # CYGSEM_HAL_VIRTUAL_VECTOR_DIAG == 1
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # DefaultValue: (CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS || CYG_HAL_STARTUP == "RAM") ? 1 : 0
+ # option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # DefaultValue: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # ActiveIf: CYGSEM_HAL_USE_ROM_MONITOR || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # DefaultValue: !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGBLD_BUILD_COMMON_GDB_STUBS
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGPKG_HAL_GDB_FILEIO
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGHWR_HAL_ARM_DUMP_EXCEPTIONS
+ # Requires: !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGBLD_BUILD_REDBOOT_WITH_GDB
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+};
+
+# Support for external break support in GDB stubs
+# The HAL implements external break (or asynchronous interrupt)
+# in the GDB stubs for the target.
+#
+cdl_interface CYGINT_HAL_DEBUG_GDB_STUBS_BREAK {
+ # Implemented by CYGPKG_HAL_ARM_TX25KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # ActiveIf: CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+};
+
+# Include GDB external break support for stubs
+# This option causes the GDB stub to add a serial interrupt handler
+# which will listen for GDB break packets. This lets you stop the
+# target asynchronously when using GDB, usually by hitting Control+C
+# or pressing the STOP button. This option differs from
+# CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT in that it is used when
+# GDB stubs are present.
+#
+cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT {
+ # ActiveIf constraint: CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+ # CYGINT_HAL_DEBUG_GDB_STUBS_BREAK == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # Requires: !CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # option CYGOPT_HAL_ARM_SYSCALL_GPROF_SUPPORT
+ # ActiveIf: CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT || CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # option CYGBLD_BUILD_REDBOOT_WITH_GDB
+ # Requires: CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+};
+
+# Platform does not support CTRLC
+#
+cdl_interface CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # ActiveIf: CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED == 0
+};
+
+# Include GDB external break support when no stubs
+# This option adds an interrupt handler for the GDB serial line
+# which will listen for GDB break packets. This lets you stop the
+# target asynchronously when using GDB, usually by hitting Control+C
+# or pressing the STOP button. This option differs from
+# CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT in that it is used when the GDB
+# stubs are NOT present.
+#
+cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT {
+ # This option is not active
+ # ActiveIf constraint: CYGSEM_HAL_USE_ROM_MONITOR || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGSEM_HAL_USE_ROM_MONITOR == 0
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+ # ActiveIf constraint: CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED == 0
+ # CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED == 0
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 1
+ # Requires: !CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGOPT_HAL_ARM_SYSCALL_GPROF_SUPPORT
+ # ActiveIf: CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT || CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+};
+
+# Include GDB multi-threading debug support
+# This option enables some extra HAL code which is needed
+# to support multi-threaded source level debugging.
+#
+cdl_option CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT {
+ # ActiveIf constraint: CYGSEM_HAL_ROM_MONITOR || CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT
+ # CYGSEM_HAL_ROM_MONITOR == 1
+ # CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT (unknown) == 0
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT
+ # Requires: CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ # option CYGBLD_BUILD_REDBOOT_WITH_THREADS
+ # Requires: CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+};
+
+# Number of times to retry sending a $O packet
+# This option controls the number of attempts that eCos programs
+# will make to send a $O packet to a host GDB process. If it is
+# set non-zero, then the target process will attempt to resend the
+# $O packet data up to this number of retries. Caution: use of
+# this option is not recommended as it can thoroughly confuse the
+# host GDB process.
+#
+cdl_option CYGNUM_HAL_DEBUG_GDB_PROTOCOL_RETRIES {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Timeout period for GDB packets
+# This option controls the time (in milliseconds) that eCos programs
+# will wait for a response when sending packets to a host GDB process.
+# If this time elapses, then the packet will be resent, up to some
+# maximum number of times (CYGNUM_HAL_DEBUG_GDB_PROTOCOL_RETRIES).
+#
+cdl_option CYGNUM_HAL_DEBUG_GDB_PROTOCOL_TIMEOUT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 500
+ # value_source default
+ # Default value: 500
+};
+
+# Location of CRC32 table
+# The stubs use a 1 kilobyte CRC table that can either be pregenerated
+# and placed in ROM, or generated at runtime in RAM. Depending on
+# your memory constraints, one of these options may be better.
+#
+cdl_option CYGDBG_HAL_CRCTABLE_LOCATION {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value RAM
+ # value_source default
+ # Default value: RAM
+ # Legal values: "ROM" "RAM"
+};
+
+# <
+# ROM monitor support
+# Support for ROM monitors can be built in to your application.
+# It may also be relevant to build your application as a ROM monitor
+# itself. Such options are contained here if relevant for your chosen
+# platform. The options and ROM monitors available to choose are
+# platform-dependent.
+#
+cdl_component CYGPKG_HAL_ROM_MONITOR {
+ # There is no associated value.
+
+ # The following properties are affected by this value
+};
+
+# >
+# Target has virtual vector support
+#
+cdl_interface CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT {
+ # Implemented by CYGPKG_HAL_ARM_TX25KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # component CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+ # ActiveIf: CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+};
+
+# Target supports baud rate control via vectors
+# Whether this target supports the __COMMCTL_GETBAUD
+# and __COMMCTL_SETBAUD virtual vector comm control operations.
+#
+cdl_interface CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT {
+ # Implemented by CYGPKG_HAL_ARM_MX25, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_VARIABLE_BAUD_RATE
+ # ActiveIf: CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+};
+
+# Enable use of virtual vector calling interface
+# Virtual vector support allows the HAL to let the ROM
+# monitor handle certain operations. The virtual vector table
+# defines a calling interface between applications running in
+# RAM and the ROM monitor.
+#
+cdl_component CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT {
+ # ActiveIf constraint: CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+ # CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT == 1
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+
+ # The following properties are affected by this value
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+ # package CYGPKG_DEVS_ETH_PHY
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+};
+
+# >
+# Inherit console settings from ROM monitor
+# When this option is set, the application will inherit
+# the console as set up by the ROM monitor. This means
+# that the application will use whatever channel and
+# mangling style was used by the ROM monitor when
+# the application was launched.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE {
+ # This option is not active
+ # ActiveIf constraint: CYGSEM_HAL_USE_ROM_MONITOR
+ # CYGSEM_HAL_USE_ROM_MONITOR == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: !CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS == 1
+ # --> 0
+
+ # The following properties are affected by this value
+ # component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # ActiveIf: !CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE
+ # option CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ # Calculated: !CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE && !CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+};
+
+# Debug channel is configurable
+# This option is a configuration hint - it is enabled
+# when the HAL initialization code will make use
+# of the debug channel configuration option.
+#
+cdl_option CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE {
+ # Calculated value: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS == 1
+ # Flavor: bool
+ # Current value: 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+ # ActiveIf: CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+};
+
+# Console channel is configurable
+# This option is a configuration hint - it is enabled
+# when the HAL initialization code will make use
+# of the console channel configuration option.
+#
+cdl_option CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE {
+ # Calculated value: !CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE && !CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE == 0
+ # CYGDBG_HAL_DIAG_TO_DEBUG_CHAN == 0
+ # Flavor: bool
+ # Current value: 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL
+ # ActiveIf: CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+};
+
+# Initialize whole of virtual vector table
+# This option will cause the whole of the virtual
+# vector table to be initialized with dummy values on
+# startup. When this option is enabled, all the
+# options below must also be enabled - or the
+# table would be empty when the application
+# launches.
+# On targets where older ROM monitors without
+# virtual vector support may still be in use, it is
+# necessary for RAM applictions to initialize the
+# table (since all HAL diagnostics and debug IO
+# happens via the table).
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYG_HAL_STARTUP != "RAM" || !CYGSEM_HAL_USE_ROM_MONITOR
+ # CYG_HAL_STARTUP == ROMRAM
+ # CYGSEM_HAL_USE_ROM_MONITOR == 0
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET == 1
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US == 1
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE == 1
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA == 1
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # ActiveIf: !CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_VERSION
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+};
+
+# Claim virtual vector table entries by default
+# By default most virtual vectors will be claimed by
+# RAM startup configurations, meaning that the RAM
+# application will provide the services. The
+# exception is COMMS support (HAL
+# diagnostics/debugging IO) which is left in the
+# control of the ROM monitor.
+# The reasoning behind this is to get as much of the
+# code exercised during regular development so it
+# is known to be working the few times a new ROM
+# monitor or a ROM production configuration is used
+# - COMMS are excluded only by necessity in order to
+# avoid breaking an existing debugger connections
+# (there may be ways around this).
+# For production RAM configurations this option can
+# be switched off, causing the appliction to rely on
+# the ROM monitor for these services, thus
+# saving some space.
+# Individual vectors may also be left unclaimed,
+# controlled by the below options (meaning that the
+# associated service provided by the ROM monitor
+# will be used).
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT {
+ # This option is not active
+ # ActiveIf constraint: !CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+};
+
+# Claim reset virtual vectors
+# This option will cause the reset and kill_by_reset
+# virtual vectors to be claimed.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET
+};
+
+# Claim version virtual vectors
+# This option will cause the version
+# virtual vectors to be claimed.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_VERSION {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # --> 1
+};
+
+# Claim delay_us virtual vector
+# This option will cause the delay_us
+# virtual vector to be claimed.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US
+};
+
+# Claim cache virtual vectors
+# This option will cause the cache virtual vectors
+# to be claimed.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE
+};
+
+# Claim data virtual vectors
+# This option will cause the data virtual vectors
+# to be claimed. At present there is only one, used
+# by the RedBoot ethernet driver to share diag output.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA
+};
+
+# Claim comms virtual vectors
+# This option will cause the communication tables
+# that are part of the virtual vectors mechanism to
+# be claimed. Note that doing this may cause an
+# existing ROM monitor communication connection to
+# be closed. For this reason, the option is disabled
+# per default for normal application
+# configurations.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # Requires: !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE
+ # DefaultValue: !CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # option CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ # Calculated: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+};
+
+# Do diagnostic IO via virtual vector table
+# All HAL IO happens via the virtual vector table / comm
+# tables when those tables are supported by the HAL.
+# If so desired, the low-level IO functions can
+# still be provided by the RAM application by
+# enabling the CLAIM_COMMS option.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_DIAG {
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+
+ # The following properties are affected by this value
+ # component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # ActiveIf: CYGPKG_HAL_ARM || CYGPKG_HAL_POWERPC_MPC8xx || CYGPKG_HAL_V85X_V850 || CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # Requires: !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+};
+
+# <
+# Behave as a ROM monitor
+# Enable this option if this program is to be used as a ROM monitor,
+# i.e. applications will be loaded into RAM on the TX25 module, and this
+# ROM monitor may process exceptions or interrupts generated from the
+# application. This enables features such as utilizing a separate
+# interrupt stack when exceptions are generated.
+#
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+ # Requires: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGBLD_ARM_ENABLE_THUMB_INTERWORK
+ # DefaultValue: (CYGHWR_THUMB || CYGSEM_HAL_ROM_MONITOR)
+ # option CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ # ActiveIf: CYGSEM_HAL_ROM_MONITOR || CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT
+ # option CYGPRI_REDBOOT_ROM_MONITOR
+ # Requires: CYGSEM_HAL_ROM_MONITOR
+};
+
+# Work with a ROM monitor
+# Support can be enabled for different varieties of ROM monitor.
+# This support changes various eCos semantics such as the encoding
+# of diagnostic output, or the overriding of hardware interrupt
+# vectors.
+# Firstly there is "Generic" support which prevents the HAL
+# from overriding the hardware vectors that it does not use, to
+# instead allow an installed ROM monitor to handle them. This is
+# the most basic support which is likely to be common to most
+# implementations of ROM monitor.
+# "GDB_stubs" provides support when GDB stubs are included in
+# the ROM monitor or boot ROM.
+#
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 0 0
+ # Legal values: "Generic" "GDB_stubs"
+ # Requires: CYG_HAL_STARTUP == "RAM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 0
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # Requires: ! CYGSEM_HAL_USE_ROM_MONITOR
+ # option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # ActiveIf: CYGSEM_HAL_USE_ROM_MONITOR || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE
+ # ActiveIf: CYGSEM_HAL_USE_ROM_MONITOR
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # DefaultValue: CYG_HAL_STARTUP != "RAM" || !CYGSEM_HAL_USE_ROM_MONITOR
+};
+
+# <
+# Platform defined I/O channels.
+# Platforms which provide additional I/O channels can implement
+# this interface, indicating that the function plf_if_init()
+# needs to be called.
+#
+cdl_interface CYGINT_HAL_PLF_IF_INIT {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+};
+
+# Platform IDE I/O support.
+# Platforms which provide IDE controllers can implement
+# this interface, indicating that IDE I/O macros are
+# available.
+#
+cdl_interface CYGINT_HAL_PLF_IF_IDE {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # component CYGSEM_REDBOOT_DISK_IDE
+ # ActiveIf: CYGINT_HAL_PLF_IF_IDE != 0
+};
+
+# File I/O operations via GDB
+# This option enables support for various file I/O
+# operations using the GDB remote protocol to communicate
+# with GDB. The operations are then performed on the
+# debugging host by proxy. These operations are only
+# currently available by using a system call interface
+# to RedBoot. This may change in the future.
+#
+cdl_option CYGPKG_HAL_GDB_FILEIO {
+ # This option is not active
+ # ActiveIf constraint: CYGSEM_REDBOOT_BSP_SYSCALLS
+ # CYGSEM_REDBOOT_BSP_SYSCALLS == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+};
+
+# Build Compiler sanity checking tests
+# Enabling this option causes compiler tests to be built.
+#
+cdl_option CYGPKG_HAL_BUILD_COMPILER_TESTS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # component CYGPKG_HAL_TESTS
+ # Calculated: "tests/context tests/basic"
+ # . ((!CYGINT_HAL_TESTS_NO_CACHES) ? " tests/cache" : "")
+ # . ((CYGPKG_HAL_BUILD_COMPILER_TESTS) ? " tests/cpp1 tests/vaargs" : "")
+ # . ((!CYGVAR_KERNEL_COUNTERS_CLOCK) ? " tests/intr" : "")
+};
+
+# Common HAL tests
+# This option specifies the set of tests for the common HAL.
+#
+cdl_component CYGPKG_HAL_TESTS {
+ # Calculated value: "tests/context tests/basic"
+ # . ((!CYGINT_HAL_TESTS_NO_CACHES) ? " tests/cache" : "")
+ # . ((CYGPKG_HAL_BUILD_COMPILER_TESTS) ? " tests/cpp1 tests/vaargs" : "")
+ # . ((!CYGVAR_KERNEL_COUNTERS_CLOCK) ? " tests/intr" : "")
+ # CYGINT_HAL_TESTS_NO_CACHES == 0
+ # CYGPKG_HAL_BUILD_COMPILER_TESTS == 0
+ # CYGVAR_KERNEL_COUNTERS_CLOCK (unknown) == 0
+ # Flavor: data
+ # Current_value: tests/context tests/basic tests/cache tests/intr
+};
+
+# >
+# Interface for cache presence
+# Some architectures and/or platforms do not have caches. By
+# implementing this interface, these can disable the various
+# cache-related tests.
+#
+cdl_interface CYGINT_HAL_TESTS_NO_CACHES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+
+ # The following properties are affected by this value
+ # component CYGPKG_HAL_TESTS
+ # Calculated: "tests/context tests/basic"
+ # . ((!CYGINT_HAL_TESTS_NO_CACHES) ? " tests/cache" : "")
+ # . ((CYGPKG_HAL_BUILD_COMPILER_TESTS) ? " tests/cpp1 tests/vaargs" : "")
+ # . ((!CYGVAR_KERNEL_COUNTERS_CLOCK) ? " tests/intr" : "")
+};
+
+# <
+# ARM architecture
+# The ARM architecture HAL package provides generic
+# support for this processor architecture. It is also
+# necessary to select a specific target platform HAL
+# package.
+#
+cdl_package CYGPKG_HAL_ARM {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # ActiveIf: CYGPKG_HAL_ARM || CYGPKG_HAL_POWERPC_MPC8xx || CYGPKG_HAL_V85X_V850 || CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+ # interface CYGINT_REDBOOT_ARM_FLASH_SIB_SUPPORTED
+ # ActiveIf: CYGPKG_HAL_ARM
+};
+
+# >
+# The CPU architecture supports THUMB mode
+#
+cdl_interface CYGINT_HAL_ARM_THUMB_ARCH {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_THUMB
+ # ActiveIf: CYGINT_HAL_ARM_THUMB_ARCH != 0
+ # option CYGBLD_ARM_ENABLE_THUMB_INTERWORK
+ # ActiveIf: CYGINT_HAL_ARM_THUMB_ARCH != 0
+};
+
+# Enable Thumb instruction set
+# Enable use of the Thumb instruction set.
+#
+cdl_option CYGHWR_THUMB {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_HAL_ARM_THUMB_ARCH != 0
+ # CYGINT_HAL_ARM_THUMB_ARCH == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGBLD_ARM_ENABLE_THUMB_INTERWORK
+ # DefaultValue: (CYGHWR_THUMB || CYGSEM_HAL_ROM_MONITOR)
+};
+
+# Enable Thumb interworking compiler option
+# This option controls the use of -mthumb-interwork in the
+# compiler flags. It defaults enabled in Thumb or ROM monitor
+# configurations, but can be overridden for reduced memory
+# footprint where interworking is not a requirement.
+#
+cdl_option CYGBLD_ARM_ENABLE_THUMB_INTERWORK {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_HAL_ARM_THUMB_ARCH != 0
+ # CYGINT_HAL_ARM_THUMB_ARCH == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: (CYGHWR_THUMB || CYGSEM_HAL_ROM_MONITOR)
+ # CYGHWR_THUMB == 0
+ # CYGSEM_HAL_ROM_MONITOR == 1
+ # --> 1
+};
+
+# The platform and architecture supports Big Endian operation
+#
+cdl_interface CYGINT_HAL_ARM_BIGENDIAN {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_BIGENDIAN
+ # ActiveIf: CYGINT_HAL_ARM_BIGENDIAN != 0
+};
+
+# Use big-endian mode
+# Use the CPU in big-endian mode.
+#
+cdl_option CYGHWR_HAL_ARM_BIGENDIAN {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_HAL_ARM_BIGENDIAN != 0
+ # CYGINT_HAL_ARM_BIGENDIAN == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# The platform uses a processor with an ARM7 core
+#
+cdl_interface CYGINT_HAL_ARM_ARCH_ARM7 {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # LegalValues: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" : ""
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" : ""
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" : ""
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" : ""
+ # ""
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # DefaultValue: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" :
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" :
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" :
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" :
+ # "unknown"
+};
+
+# The platform uses a processor with an ARM9 core
+#
+cdl_interface CYGINT_HAL_ARM_ARCH_ARM9 {
+ # Implemented by CYGPKG_HAL_ARM_MX25, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # LegalValues: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" : ""
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" : ""
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" : ""
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" : ""
+ # ""
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # DefaultValue: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" :
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" :
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" :
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" :
+ # "unknown"
+};
+
+# The platform uses a processor with a StrongARM core
+#
+cdl_interface CYGINT_HAL_ARM_ARCH_STRONGARM {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # LegalValues: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" : ""
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" : ""
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" : ""
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" : ""
+ # ""
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # DefaultValue: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" :
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" :
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" :
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" :
+ # "unknown"
+};
+
+# The platform uses a processor with a XScale core
+#
+cdl_interface CYGINT_HAL_ARM_ARCH_XSCALE {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # LegalValues: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" : ""
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" : ""
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" : ""
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" : ""
+ # ""
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # DefaultValue: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" :
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" :
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" :
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" :
+ # "unknown"
+};
+
+# ARM CPU family
+# It is possible to optimize code for different
+# ARM CPU families. This option selects which CPU to
+# optimize for on boards that support multiple CPU types.
+#
+cdl_option CYGHWR_HAL_ARM_CPU_FAMILY {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ARM9
+ # value_source default
+ # Default value: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" :
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" :
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" :
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" :
+ # "unknown"
+ # CYGINT_HAL_ARM_ARCH_ARM7 == 0
+ # CYGINT_HAL_ARM_ARCH_ARM9 == 1
+ # CYGINT_HAL_ARM_ARCH_STRONGARM == 0
+ # CYGINT_HAL_ARM_ARCH_XSCALE == 0
+ # --> ARM9
+ # Legal values: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" : ""
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" : ""
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" : ""
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" : ""
+ # ""
+ # CYGINT_HAL_ARM_ARCH_ARM7 == 0
+ # CYGINT_HAL_ARM_ARCH_ARM9 == 1
+ # CYGINT_HAL_ARM_ARCH_STRONGARM == 0
+ # CYGINT_HAL_ARM_ARCH_XSCALE == 0
+};
+
+# Provide diagnostic dump for exceptions
+# Print messages about hardware exceptions, including
+# raw exception frame dump and register contents.
+#
+cdl_option CYGHWR_HAL_ARM_DUMP_EXCEPTIONS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 1
+};
+
+# Process all exceptions with the eCos application
+# Normal RAM-based programs which do not include GDB stubs
+# defer processing of the illegal instruction exception to GDB.
+# Setting this options allows the program to explicitly handle
+# the illegal instruction exception itself. Note: this will
+# prevent the use of GDB to debug the application as breakpoints
+# will no longer work.
+#
+cdl_option CYGIMP_HAL_PROCESS_ALL_EXCEPTIONS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Support GDB thread operations via ICE/Multi-ICE
+# Allow GDB to get thread information via the ICE/Multi-ICE
+# connection.
+#
+cdl_option CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT == 1
+ # --> 1
+ # Requires: CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT
+ # CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT (unknown) == 0
+ # --> 0
+};
+
+# Support for 'gprof' callbacks
+# The ARM HAL provides the macro for 'gprof' callbacks from RedBoot
+# to acquire the interrupt-context PC and SP, when this option is
+# active.
+#
+cdl_option CYGOPT_HAL_ARM_SYSCALL_GPROF_SUPPORT {
+ # This option is not active
+ # ActiveIf constraint: CYGSEM_REDBOOT_BSP_SYSCALLS
+ # CYGSEM_REDBOOT_BSP_SYSCALLS == 0
+ # --> 0
+ # ActiveIf constraint: CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT || CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT == 0
+ # CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT == 0
+ # --> 0
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+};
+
+# Accept exceptions and irq's occurring in user mode
+# For standalone Redboot based programs running in user mode.
+#
+cdl_option CYGOPT_HAL_ARM_WITH_USER_MODE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Preserve svc spsr before returning to svc mode
+# This option secures exception and breakpoint processing
+# triggered during execution of application specific SWI
+# handlers.
+#
+cdl_option CYGOPT_HAL_ARM_PRESERVE_SVC_SPSR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Linker script
+#
+cdl_option CYGBLD_LINKER_SCRIPT {
+ # Calculated value: "src/arm.ld"
+ # Flavor: data
+ # Current_value: src/arm.ld
+};
+
+# Implementations of hal_arm_mem_real_region_top()
+#
+cdl_interface CYGINT_HAL_ARM_MEM_REAL_REGION_TOP {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+};
+
+# Freescale SoC architecture
+# This HAL variant package provides generic
+# support for the Freescale SoC. It is also
+# necessary to select a specific target platform HAL
+# package.
+#
+cdl_package CYGPKG_HAL_ARM_MX25 {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+};
+
+# >
+# mDDR/DDR2 support
+# When this option is enabled, it indicates support
+# for Mobile DDR on the MX25 3stack CPU board. mDDR
+# was used on TO1.0 boards. Subsequent boards use
+# DDR2 memory.
+#
+cdl_option CYGHWR_MX25_MDDR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Processor clock rate
+# The processor can run at various frequencies.
+# These values are expressed in KHz. Note that there are
+# several steppings of the rate to run at different
+# maximum frequencies. Check the specs to make sure that your
+# particular processor can run at the rate you select here.
+#
+cdl_option CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK {
+ # This option is not active
+ # ActiveIf constraint: CYG_HAL_STARTUP == "ROM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 0
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 150000
+ # value_source default
+ # Default value: CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT ?
+ # CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT : 150000
+ # CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT (unknown) == 0
+ # CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT (unknown) == 0
+ # --> 150000
+ # Legal values: 150000 200000
+};
+
+# Real-time clock constants
+#
+cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+ # There is no associated value.
+};
+
+# >
+# Real-time clock numerator
+#
+cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+ # Calculated value: 1000000000
+ # Flavor: data
+ # Current_value: 1000000000
+};
+
+# Real-time clock denominator
+# This option selects the heartbeat rate for the real-time clock.
+# The rate is specified in ticks per second. Change this value
+# with caution - too high and your system will become saturated
+# just handling clock interrupts, too low and some operations
+# such as thread scheduling may become sluggish.
+#
+cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 100
+ # value_source default
+ # Default value: 100
+
+ # The following properties are affected by this value
+ # option CYGNUM_HAL_RTC_PERIOD
+ # Calculated: (3686400/CYGNUM_HAL_RTC_DENOMINATOR)
+};
+
+# Real-time clock period
+#
+cdl_option CYGNUM_HAL_RTC_PERIOD {
+ # Calculated value: (3686400/CYGNUM_HAL_RTC_DENOMINATOR)
+ # CYGNUM_HAL_RTC_DENOMINATOR == 100
+ # Flavor: data
+ # Current_value: 36864
+};
+
+# <
+# UART1 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART1 {
+ # Implemented by CYGPKG_HAL_ARM_TX25KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+};
+
+# UART2 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART2 {
+ # Implemented by CYGPKG_HAL_ARM_TX25KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+};
+
+# UART3 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART3 {
+ # Implemented by CYGPKG_HAL_ARM_TX25KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+};
+
+# UART4 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART4 {
+ # Implemented by CYGPKG_HAL_ARM_TX25KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+};
+
+# UART5 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART5 {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+};
+
+# Ka-Ro TX25 module
+# This HAL platform package provides generic
+# support for the Ka-Ro electronics TX25 module.
+#
+cdl_package CYGPKG_HAL_ARM_TX25KARO {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGINT_ISO_CTYPE
+ # CYGINT_ISO_CTYPE == 1
+ # --> 1
+ # Requires: CYGBLD_BUILD_REDBOOT == 1
+ # CYGBLD_BUILD_REDBOOT == 1
+ # --> 1
+};
+
+# >
+# Startup type
+# The only startup type allowed is ROMRAM, since this will allow
+# the program to exist in ROM, but be copied to RAM during startup
+# which is required to boot from NAND flash.
+#
+cdl_component CYG_HAL_STARTUP {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ROMRAM
+ # value_source default
+ # Default value: ROMRAM
+ # Legal values: "ROMRAM"
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_ROM_MONITOR
+ # Requires: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+ # option CYGSEM_HAL_ROM_MONITOR
+ # Requires: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+ # option CYGSEM_HAL_USE_ROM_MONITOR
+ # DefaultValue: CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0
+ # option CYGSEM_HAL_USE_ROM_MONITOR
+ # Requires: CYG_HAL_STARTUP == "RAM"
+ # option CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK
+ # ActiveIf: CYG_HAL_STARTUP == "ROM"
+ # option CYGSEM_HAL_INSTALL_MMU_TABLES
+ # DefaultValue: CYG_HAL_STARTUP != "RAM"
+ # component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # DefaultValue: (CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS || CYG_HAL_STARTUP == "RAM") ? 1 : 0
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # DefaultValue: CYG_HAL_STARTUP != "RAM" || !CYGSEM_HAL_USE_ROM_MONITOR
+ # option CYGBLD_BUILD_REDBOOT_WITH_THREADS
+ # ActiveIf: CYG_HAL_STARTUP != "RAM"
+ # option CYGPRI_REDBOOT_ROM_MONITOR
+ # ActiveIf: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+ # option CYGPRI_REDBOOT_ROM_MONITOR
+ # ActiveIf: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+};
+
+# Diagnostic serial port baud rate
+# This option selects the baud rate used for the console port.
+# Note: this should match the value chosen for the GDB port if the
+# console and GDB port are the same.
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 115200
+ # value_source default
+ # Default value: 115200
+ # Legal values: 9600 19200 38400 57600 115200
+};
+
+# GDB serial port baud rate
+# This option selects the baud rate used for the GDB port.
+# Note: this should match the value chosen for the console port if the
+# console and GDB port are the same.
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 115200
+ # value_source default
+ # Default value: 115200
+ # Legal values: 9600 19200 38400 57600 115200
+};
+
+# Number of communication channels on the TX25
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ # Calculated value: 3
+ # Flavor: data
+ # Current_value: 3
+
+ # The following properties are affected by this value
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+ # LegalValues: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ # LegalValues: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL
+ # LegalValues: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+};
+
+# Debug serial port
+# The TX25 provides access to three serial ports. This option
+# chooses which port will be used to connect to a host
+# running GDB.
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ # ActiveIf constraint: CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ # CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE == 1
+ # --> 1
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ # CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS == 3
+};
+
+# Default console channel.
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+ # Calculated value: 0
+ # Flavor: data
+ # Current_value: 0
+ # Legal values: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ # CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS == 3
+
+ # The following properties are affected by this value
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL
+ # DefaultValue: CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+};
+
+# Console serial port
+# The TX25 provides access to three serial ports. This option
+# chooses which port will be used for console output.
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ # ActiveIf constraint: CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ # CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE == 1
+ # --> 1
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ # CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT == 0
+ # --> 0
+ # Legal values: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ # CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS == 3
+};
+
+# Ka-Ro electronics TX25 module build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_HAL_ARM_TX25_OPTIONS {
+ # There is no associated value.
+ # Requires: CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0
+ # CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0
+ # --> 1
+};
+
+# >
+# SDRAM size
+# This option specifies the SDRAM size of the TX25 module.
+#
+cdl_option CYGNUM_HAL_ARM_TX25_SDRAM_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x04000000
+ # value_source default
+ # Default value: 0x04000000
+ # Legal values: 0x02000000 0x04000000 0x08000000
+};
+
+# Enable low level debugging with LED
+# This option enables low level debugging by blink codes
+# of the LED on STK5.
+#
+cdl_option CYGOPT_HAL_ARM_TX25_DEBUG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: false
+ # false (unknown) == 0
+ # --> 0
+};
+
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the TX25 HAL. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_HAL_ARM_TX25_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the TX25 HAL. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_HAL_ARM_TX25_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# <
+# Memory layout
+#
+cdl_component CYGHWR_MEMORY_LAYOUT {
+ # Calculated value: "arm_tx25_romram"
+ # Flavor: data
+ # Current_value: arm_tx25_romram
+};
+
+# >
+# Memory layout linker script fragment
+#
+cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ # Calculated value: "<pkgconf/mlt_arm_tx25_romram.ldi>"
+ # Flavor: data
+ # Current_value: <pkgconf/mlt_arm_tx25_romram.ldi>
+};
+
+# Memory layout header file
+#
+cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ # Calculated value: "<pkgconf/mlt_arm_tx25_romram.h>"
+ # Flavor: data
+ # Current_value: <pkgconf/mlt_arm_tx25_romram.h>
+};
+
+# <
+# <
+# <
+# <
+# <
+# Infrastructure
+# Common types and useful macros.
+# Tracing and assertion facilities.
+# Package startup options.
+#
+cdl_package CYGPKG_INFRA {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # package CYGPKG_HAL
+ # Requires: CYGPKG_INFRA
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGPKG_INFRA
+};
+
+# >
+# Asserts & Tracing
+# The eCos source code contains a significant amount of
+# internal debugging support, in the form of assertions and
+# tracing.
+# Assertions check at runtime that various conditions are as
+# expected; if not, execution is halted.
+# Tracing takes the form of text messages that are output
+# whenever certain events occur, or whenever functions are
+# called or return.
+# The most important property of these checks and messages is
+# that they are not required for the program to run.
+# It is prudent to develop software with assertions enabled,
+# but disable them when making a product release, thus
+# removing the overhead of that checking.
+# It is possible to enable assertions and tracing
+# independently.
+# There are also options controlling the exact behaviour of
+# the assertion and tracing facilities, thus giving users
+# finer control over the code and data size requirements.
+#
+cdl_component CYGPKG_INFRA_DEBUG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGNUM_INFRA_EMPTY_DELETE_THRESHOLD
+ # ActiveIf: CYGPKG_INFRA_DEBUG
+};
+
+# >
+# Use asserts
+# If this option is defined, asserts in the code are tested.
+# Assert functions (CYG_ASSERT()) are defined in
+# 'include/cyg/infra/cyg_ass.h' within the 'install' tree.
+# If it is not defined, these result in no additional
+# object code and no checking of the asserted conditions.
+#
+cdl_component CYGDBG_USE_ASSERTS {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: 1 == CYGINT_INFRA_DEBUG_TRACE_IMPL
+ # CYGINT_INFRA_DEBUG_TRACE_IMPL == 0
+ # --> 0
+
+ # The following properties are affected by this value
+ # option CYGDBG_MEMALLOC_ALLOCATOR_DLMALLOC_DEBUG
+ # Requires: CYGDBG_USE_ASSERTS
+ # option CYGDBG_MEMALLOC_ALLOCATOR_DLMALLOC_DEBUG
+ # DefaultValue: 0 != CYGDBG_USE_ASSERTS
+};
+
+# >
+# Preconditions
+# This option allows individual control of preconditions.
+# A precondition is one type of assert, which it is
+# useful to control separately from more general asserts.
+# The function is CYG_PRECONDITION(condition,msg).
+#
+cdl_option CYGDBG_INFRA_DEBUG_PRECONDITIONS {
+ # This option is not active
+ # The parent CYGDBG_USE_ASSERTS is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Postconditions
+# This option allows individual control of postconditions.
+# A postcondition is one type of assert, which it is
+# useful to control separately from more general asserts.
+# The function is CYG_POSTCONDITION(condition,msg).
+#
+cdl_option CYGDBG_INFRA_DEBUG_POSTCONDITIONS {
+ # This option is not active
+ # The parent CYGDBG_USE_ASSERTS is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Loop invariants
+# This option allows individual control of loop invariants.
+# A loop invariant is one type of assert, which it is
+# useful to control separately from more general asserts,
+# particularly since a loop invariant is typically evaluated
+# a great many times when used correctly.
+# The function is CYG_LOOP_INVARIANT(condition,msg).
+#
+cdl_option CYGDBG_INFRA_DEBUG_LOOP_INVARIANTS {
+ # This option is not active
+ # The parent CYGDBG_USE_ASSERTS is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Use assert text
+# All assertions within eCos contain a text message
+# which should give some information about the condition
+# being tested.
+# These text messages will end up being embedded in the
+# application image and hence there is a significant penalty
+# in terms of image size.
+# It is possible to suppress the use of these messages by
+# disabling this option.
+# This results in smaller code size, but there is less
+# human-readable information if an assertion actually gets
+# triggered.
+#
+cdl_option CYGDBG_INFRA_DEBUG_ASSERT_MESSAGE {
+ # This option is not active
+ # The parent CYGDBG_USE_ASSERTS is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Use tracing
+# If this option is defined, tracing operations
+# result in output or logging, depending on other options.
+# This may have adverse effects on performance, if the time
+# taken to output message overwhelms the available CPU
+# power or output bandwidth.
+# Trace functions (CYG_TRACE()) are defined in
+# 'include/cyg/infra/cyg_trac.h' within the 'install' tree.
+# If it is not defined, these result in no additional
+# object code and no trace information.
+#
+cdl_component CYGDBG_USE_TRACING {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: 1 == CYGINT_INFRA_DEBUG_TRACE_IMPL
+ # CYGINT_INFRA_DEBUG_TRACE_IMPL == 0
+ # --> 0
+
+ # The following properties are affected by this value
+ # option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_SIZE
+ # ActiveIf: CYGDBG_USE_TRACING
+ # option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_WRAP
+ # ActiveIf: CYGDBG_USE_TRACING
+ # option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_HALT
+ # ActiveIf: CYGDBG_USE_TRACING
+ # option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_PRINT
+ # ActiveIf: CYGDBG_USE_TRACING
+ # option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_PRINT_ON_ASSERT
+ # ActiveIf: CYGDBG_USE_TRACING
+};
+
+# >
+# Trace function reports
+# This option allows individual control of
+# function entry/exit tracing, independent of
+# more general tracing output.
+# This may be useful to remove clutter from a
+# trace log.
+#
+cdl_option CYGDBG_INFRA_DEBUG_FUNCTION_REPORTS {
+ # This option is not active
+ # The parent CYGDBG_USE_TRACING is not active
+ # The parent CYGDBG_USE_TRACING is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Use trace text
+# All trace calls within eCos contain a text message
+# which should give some information about the circumstances.
+# These text messages will end up being embedded in the
+# application image and hence there is a significant penalty
+# in terms of image size.
+# It is possible to suppress the use of these messages by
+# disabling this option.
+# This results in smaller code size, but there is less
+# human-readable information available in the trace output,
+# possibly only filenames and line numbers.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_MESSAGE {
+ # This option is not active
+ # The parent CYGDBG_USE_TRACING is not active
+ # The parent CYGDBG_USE_TRACING is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Trace output implementations
+#
+cdl_interface CYGINT_INFRA_DEBUG_TRACE_IMPL {
+ # Implemented by CYGDBG_INFRA_DEBUG_TRACE_ASSERT_NULL, inactive, disabled
+ # Implemented by CYGDBG_INFRA_DEBUG_TRACE_ASSERT_SIMPLE, inactive, disabled
+ # Implemented by CYGDBG_INFRA_DEBUG_TRACE_ASSERT_FANCY, inactive, disabled
+ # Implemented by CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER, inactive, enabled
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # component CYGDBG_USE_ASSERTS
+ # Requires: 1 == CYGINT_INFRA_DEBUG_TRACE_IMPL
+ # component CYGDBG_USE_TRACING
+ # Requires: 1 == CYGINT_INFRA_DEBUG_TRACE_IMPL
+};
+
+# Null output
+# A null output module which is useful when
+# debugging interactively; the output routines
+# can be breakpointed rather than have them actually
+# 'print' something.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_ASSERT_NULL {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Simple output
+# An output module which produces simple output
+# from tracing and assertion events.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_ASSERT_SIMPLE {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Fancy output
+# An output module which produces fancy output
+# from tracing and assertion events.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_ASSERT_FANCY {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Buffered tracing
+# An output module which buffers output
+# from tracing and assertion events. The stored
+# messages are output when an assert fires, or
+# CYG_TRACE_PRINT() (defined in <cyg/infra/cyg_trac.h>)
+# is called.
+# Of course, there will only be stored messages
+# if tracing per se (CYGDBG_USE_TRACING)
+# is enabled above.
+#
+cdl_component CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Trace buffer size
+# The size of the trace buffer. This counts the number
+# of trace records stored. When the buffer fills it
+# either wraps, stops recording, or generates output.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_SIZE {
+ # This option is not active
+ # The parent CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER is not active
+ # ActiveIf constraint: CYGDBG_USE_TRACING
+ # CYGDBG_USE_TRACING == 0
+ # --> 0
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 32
+ # value_source default
+ # Default value: 32
+ # Legal values: 5 to 65535
+};
+
+# Wrap trace buffer when full
+# When the trace buffer has filled with records it
+# starts again at the beginning. Hence only the last
+# CYGDBG_INFRA_DEBUG_TRACE_BUFFER_SIZE messages will
+# be recorded.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_WRAP {
+ # This option is not active
+ # The parent CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER is not active
+ # ActiveIf constraint: CYGDBG_USE_TRACING
+ # CYGDBG_USE_TRACING == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Halt trace buffer when full
+# When the trace buffer has filled with records it
+# stops recording. Hence only the first
+# CYGDBG_INFRA_DEBUG_TRACE_BUFFER_SIZE messages will
+# be recorded.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_HALT {
+ # This option is not active
+ # The parent CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER is not active
+ # ActiveIf constraint: CYGDBG_USE_TRACING
+ # CYGDBG_USE_TRACING == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Print trace buffer when full
+# When the trace buffer has filled with records it
+# prints the contents of the buffer. The buffer is then
+# emptied and the system continues.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_PRINT {
+ # This option is not active
+ # The parent CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER is not active
+ # ActiveIf constraint: CYGDBG_USE_TRACING
+ # CYGDBG_USE_TRACING == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Print trace buffer on assert fail
+# When an assertion fails the trace buffer will be
+# printed to the default diagnostic device.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_PRINT_ON_ASSERT {
+ # This option is not active
+ # The parent CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER is not active
+ # ActiveIf constraint: CYGDBG_USE_TRACING
+ # CYGDBG_USE_TRACING == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Use function names
+# All trace and assert calls within eCos contain a
+# reference to the builtin macro '__PRETTY_FUNCTION__',
+# which evaluates to a string containing
+# the name of the current function.
+# This is useful when reading a trace log.
+# It is possible to suppress the use of the function name
+# by disabling this option.
+# This results in smaller code size, but there is less
+# human-readable information available in the trace output,
+# possibly only filenames and line numbers.
+#
+cdl_option CYGDBG_INFRA_DEBUG_FUNCTION_PSEUDOMACRO {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Startup options
+# Some packages require a startup routine to be called.
+# This can be carried out by application code, by supplying
+# a routine called cyg_package_start() which calls the
+# appropriate package startup routine(s).
+# Alternatively, this routine can be constructed automatically
+# and configured to call the startup routines of your choice.
+#
+cdl_component CYGPKG_INFRA_STARTUP {
+ # There is no associated value.
+};
+
+# >
+# Start uITRON subsystem
+# Generate a call to initialize the
+# uITRON compatibility subsystem
+# within the system version of cyg_package_start().
+# This enables compatibility with uITRON.
+# You must configure uITRON with the correct tasks before
+# starting the uItron subsystem.
+# If this is disabled, and you want to use uITRON,
+# you must call cyg_uitron_start() from your own
+# cyg_package_start() or cyg_userstart().
+#
+cdl_option CYGSEM_START_UITRON_COMPATIBILITY {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_UITRON
+ # CYGPKG_UITRON (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGPKG_UITRON
+ # CYGPKG_UITRON (unknown) == 0
+ # --> 0
+};
+
+# <
+# Smaller slower memcpy()
+# Enabling this option causes the implementation of
+# the standard memcpy() routine to reduce code
+# size at the expense of execution speed. This
+# option is automatically enabled with the use of
+# the -Os option to the compiler. Also note that
+# the compiler will try to use its own builtin
+# version of memcpy() if possible, ignoring the
+# implementation in this package, unless given
+# the -fno-builtin compiler option.
+#
+cdl_option CYGIMP_INFRA_PREFER_SMALL_TO_FAST_MEMCPY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Smaller slower memset()
+# Enabling this option causes the implementation of
+# the standard memset() routine to reduce code
+# size at the expense of execution speed. This
+# option is automatically enabled with the use of
+# the -Os option to the compiler. Also note that
+# the compiler will try to use its own builtin
+# version of memset() if possible, ignoring the
+# implementation in this package, unless given
+# the -fno-builtin compiler option.
+#
+cdl_option CYGIMP_INFRA_PREFER_SMALL_TO_FAST_MEMSET {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Provide empty C++ delete functions
+# To deal with virtual destructors, where the correct delete()
+# function must be called for the derived class in question, the
+# underlying delete is called when needed, from destructors. This
+# is regardless of whether the destructor is called by delete itself.
+# So there is a reference to delete() from all destructors. The
+# default builtin delete() attempts to call free() if there is
+# one defined. So, if you have destructors, and you have free(),
+# as in malloc() and free(), any destructor counts as a reference
+# to free(). So the dynamic memory allocation code is linked
+# in regardless of whether it gets explicitly called. This
+# increases code and data size needlessly.
+# To defeat this undesirable behaviour, we define empty versions
+# of delete and delete. But doing this prevents proper use
+# of dynamic memory in C++ programs via C++'s new and delete
+# operators.
+# Therefore, this option is provided
+# for explicitly disabling the provision of these empty functions,
+# so that new and delete can be used, if that is what is required.
+#
+cdl_option CYGFUN_INFRA_EMPTY_DELETE_FUNCTIONS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Threshold for valid number of delete calls
+# Some users don't know about the empty delete function and then
+# wonder why their C++ classes are leaking memory. If
+# INFRA_DEBUG is enabled we keep a counter for the number of
+# times delete is called. If it goes above this threshold we throw
+# an assertion failure. This should point heavy users of
+# delete in the right direction without upsetting those who want
+# an empty delete function.
+#
+cdl_option CYGNUM_INFRA_EMPTY_DELETE_THRESHOLD {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_INFRA_DEBUG
+ # CYGPKG_INFRA_DEBUG == 0
+ # --> 0
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 100
+ # value_source default
+ # Default value: 100
+};
+
+# Provide dummy abort() function
+# This option controls the inclusion of a dummy abort() function.
+# Parts of the C and C++ compiler runtime systems contain references
+# to abort(), particulary in the C++ exception handling code. It is
+# not possible to eliminate these references, so this dummy function
+# in included to satisfy them. It is not expected that this function
+# will ever be called, so its current behaviour is to simply loop.
+#
+cdl_option CYGFUN_INFRA_DUMMY_ABORT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGINT_ISO_EXIT == 0
+ # CYGINT_ISO_EXIT == 0
+ # --> 1
+ # Requires: !CYGINT_ISO_EXIT
+ # CYGINT_ISO_EXIT == 0
+ # --> 1
+};
+
+# Reset platform at end of test case execution
+# If this option is set then test case programs will reset the platform
+# when they terminate, as opposed to the default which is to just hang
+# in a loop.
+#
+cdl_option CYGSEM_INFRA_RESET_ON_TEST_EXIT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Provide dummy strlen() function
+# This option controls the inclusion of a dummy strlen() function.
+# Parts of the C and C++ compiler runtime systems contain references
+# to strlen(), particulary in the C++ exception handling code. It is
+# not possible to eliminate these references, so this dummy function
+# in included to satisfy them. While it is not expected that this function
+# will ever be called, it is functional but uses the simplest, smallest
+# algorithm. There is a faster version of strlen() in the C library.
+#
+cdl_option CYGFUN_INFRA_DUMMY_STRLEN {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGINT_ISO_STRING_STRFUNCS == 0
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 0
+ # Requires: !CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 0
+};
+
+# Make all compiler warnings show as errors
+# Enabling this option will cause all compiler warnings to show
+# as errors and bring the library build to a halt. This is used
+# to ensure that the code base is warning free, and thus ensure
+# that newly introduced warnings stand out and get fixed before
+# they show up as weird run-time behavior.
+#
+cdl_option CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS {
+ # Flavor: bool
+ user_value 1
+ # value_source user
+ # Default value: 0
+ # Requires: is_substr(CYGBLD_GLOBAL_CFLAGS, " -Werror")
+ # CYGBLD_GLOBAL_CFLAGS == "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe"
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGBLD_GLOBAL_CFLAGS
+ # Requires: CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS
+};
+
+# Make compiler and assembler communicate by pipe
+# Enabling this option will cause the compiler to feed the
+# assembly output the the assembler via a pipe instead of
+# via a temporary file. This normally reduces the build
+# time.
+#
+cdl_option CYGBLD_INFRA_CFLAGS_PIPE {
+ # Flavor: bool
+ user_value 1
+ # value_source user
+ # Default value: 0
+ # Requires: is_substr(CYGBLD_GLOBAL_CFLAGS, " -pipe")
+ # CYGBLD_GLOBAL_CFLAGS == "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe"
+ # --> 1
+};
+
+# Infra build options
+# Package specific build options including control over
+# compiler flags used only in building this package.
+#
+cdl_component CYGPKG_INFRA_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the eCos infra package. These flags are used
+# in addition to the set of global flags.
+#
+cdl_option CYGPKG_INFRA_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-fno-rtti -Woverloaded-virtual"
+ # value_source default
+ # Default value: "-fno-rtti -Woverloaded-virtual"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the eCos infra package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_INFRA_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wno-pointer-sign
+ # value_source default
+ # Default value: -Wno-pointer-sign
+};
+
+# Suppressed linker flags
+# This option modifies the set of linker flags for
+# building the eCos infra package tests. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_INFRA_LDFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wl,--gc-sections
+ # value_source default
+ # Default value: -Wl,--gc-sections
+};
+
+# Additional linker flags
+# This option modifies the set of linker flags for
+# building the eCos infra package tests. These flags are added to
+# the set of global flags if present.
+#
+cdl_option CYGPKG_INFRA_LDFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wl,--fatal-warnings
+ # value_source default
+ # Default value: -Wl,--fatal-warnings
+};
+
+# Infra package tests
+#
+cdl_component CYGPKG_INFRA_TESTS {
+ # Calculated value: "tests/cxxsupp tests/diag_sprintf1 tests/diag_sprintf2"
+ # Flavor: data
+ # Current_value: tests/cxxsupp tests/diag_sprintf1 tests/diag_sprintf2
+};
+
+# >
+# Number of times a test runs
+# This option controls the number of times tests will execute their
+# basic function. Not all tests will honor this setting, but those
+# that do will execute the test N times before terminating. A value
+# less than 0 indicates to run forever.
+#
+cdl_option CYGNUM_TESTS_RUN_COUNT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# <
+# <
+# Redboot ROM monitor
+# doc: ref/redboot.html
+# This package supports the Redboot [stand-alone debug monitor]
+# using eCos as the underlying board support mechanism.
+#
+cdl_package CYGPKG_REDBOOT {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK == 0
+ # CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGPKG_REDBOOT_ARM_OPTIONS
+ # ActiveIf: CYGPKG_REDBOOT
+ # component CYGPKG_REDBOOT_HAL_OPTIONS
+ # ActiveIf: CYGPKG_REDBOOT
+ # component CYGPKG_REDBOOT_HAL_TX25_OPTIONS
+ # ActiveIf: CYGPKG_REDBOOT
+ # option CYGSEM_IO_ETH_DRIVERS_WARN
+ # ActiveIf: CYGPKG_REDBOOT
+};
+
+# >
+# Include support for ELF file format
+#
+cdl_component CYGSEM_REDBOOT_ELF {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Use the virtual address in the ELF headers
+# The ELF headers contain both a virtual and a physical address
+# for where code/data should be loaded. By default the physical
+# address is used but sometimes it is necassary to use the
+# virtual address because of bugy toolchains
+#
+cdl_option CYGOPT_REDBOOT_ELF_VIRTUAL_ADDRESS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Methods of loading images using redboot
+#
+cdl_interface CYGINT_REDBOOT_LOAD_METHOD {
+ # Implemented by CYGBLD_BUILD_REDBOOT_WITH_XYZMODEM, active, enabled
+ # Implemented by CYGPKG_REDBOOT_NETWORKING, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 2
+
+ # The following properties are affected by this value
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGINT_REDBOOT_LOAD_METHOD
+};
+
+# Build Redboot ROM ELF image
+# This option enables the building of the Redboot ELF image.
+# The image may require further relocation or symbol
+# stripping before being converted to a binary image.
+# This is handled by a rule in the target CDL.
+#
+cdl_component CYGBLD_BUILD_REDBOOT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+ # Requires: CYGPKG_INFRA
+ # CYGPKG_INFRA == current
+ # --> 1
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+ # Requires: ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT == 0
+ # --> 1
+ # Requires: ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ # CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT == 0
+ # --> 1
+ # Requires: ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ # CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM == 0
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT == 1
+ # --> 1
+ # Requires: CYGINT_ISO_STRING_MEMFUNCS
+ # CYGINT_ISO_STRING_MEMFUNCS == 1
+ # --> 1
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+ # Requires: CYGINT_REDBOOT_LOAD_METHOD
+ # CYGINT_REDBOOT_LOAD_METHOD == 2
+ # --> 1
+
+ # The following properties are affected by this value
+ # package CYGPKG_HAL_ARM_TX25KARO
+ # Requires: CYGBLD_BUILD_REDBOOT == 1
+ # option CYGBLD_BUILD_REDBOOT_BIN
+ # ActiveIf: CYGBLD_BUILD_REDBOOT
+};
+
+# >
+# Include GDB support in RedBoot
+# RedBoot normally includes support for the GDB debugging
+# protocols. This option allows this to be disabled which
+# may yield a substantial savings in terms of code and memory
+# usage by RedBoot.
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_GDB {
+ # ActiveIf constraint: CYGINT_HAL_DEBUG_GDB_STUBS
+ # CYGINT_HAL_DEBUG_GDB_STUBS == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT == 0
+ # --> 0
+};
+
+# Threads debugging support
+# Enabling this option will include special code in the
+# GDB stubs to support debugging of threaded programs. In
+# the case of eCos programs, this support allows GDB to
+# have complete access to the eCos threads in the
+# program.
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_THREADS {
+ # ActiveIf constraint: CYG_HAL_STARTUP != "RAM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT == 1
+ # --> 1
+};
+
+# Customized version string
+# Use this option to define a customized version "string" for
+# RedBoot. Note: this value is only cosmetic, displayed by the
+# "version" command, but is useful for providing site specific
+# information about the RedBoot configuration.
+#
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 "Ka-Ro 2009-06-10"
+ # value_source inferred
+ # Default value: 0 0
+};
+
+# Enable command line editing
+# If this option is non-zero, RedBoot will remember the
+# last N command lines. These lines may be reused.
+# Enabling this history will also enable rudimentary
+# editting of the lines themselves.
+#
+cdl_option CYGNUM_REDBOOT_CMD_LINE_EDITING {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 16
+ # value_source default
+ # Default value: 16
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_CMD_LINE_ANSI_SEQUENCES
+ # ActiveIf: CYGNUM_REDBOOT_CMD_LINE_EDITING != 0
+ # option CYGBLD_REDBOOT_CMD_LINE_HISTORY
+ # Requires: CYGNUM_REDBOOT_CMD_LINE_EDITING > 0
+};
+
+# Enable command line editing using ANSI arrows, etc
+# If this option is enabled, RedBoot will accept standard ANSI key
+# sequences for cursor movement (along with the emacs style keys).
+#
+cdl_option CYGSEM_REDBOOT_CMD_LINE_ANSI_SEQUENCES {
+ # ActiveIf constraint: CYGNUM_REDBOOT_CMD_LINE_EDITING != 0
+ # CYGNUM_REDBOOT_CMD_LINE_EDITING == 16
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Enable history command and expansion
+# Enabling this option will allow RedBoot to provide a
+# history command to list previous commands. Also enables
+# history expansion via '!' character similar to bash
+# shell.
+#
+cdl_option CYGBLD_REDBOOT_CMD_LINE_HISTORY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGNUM_REDBOOT_CMD_LINE_EDITING > 0
+ # CYGNUM_REDBOOT_CMD_LINE_EDITING == 16
+ # --> 1
+};
+
+# Number of unique RAM segments on platform
+# Change this option to be the number of memory segments which are
+# supported by the platform. If the value is greater than 1, then
+# a platform specific function must provide information about the
+# additional segments.
+#
+cdl_option CYGBLD_REDBOOT_MAX_MEM_SEGMENTS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include support gzip/zlib decompression
+#
+cdl_component CYGBLD_BUILD_REDBOOT_WITH_ZLIB {
+ # ActiveIf constraint: CYGPKG_COMPRESS_ZLIB
+ # CYGPKG_COMPRESS_ZLIB == current
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGOPT_REDBOOT_FIS_ZLIB_COMMON_BUFFER
+ # ActiveIf: CYGBLD_BUILD_REDBOOT_WITH_ZLIB && CYGOPT_REDBOOT_FIS
+};
+
+# >
+# Size of zlib decompression buffer
+# This is the size of the buffer filled with incoming data
+# during load before calls are made to the decompressor
+# function. For ethernet downloads this can be made bigger
+# (at the cost of memory), but for serial downloads on slow
+# processors it may be necessary to reduce the size to
+# avoid serial overruns. zlib appears to bail out if less
+# than five bytes are available initially so this is the
+# minimum.
+#
+cdl_option CYGNUM_REDBOOT_LOAD_ZLIB_BUFFER {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 64
+ # value_source default
+ # Default value: 64
+ # Legal values: 5 to 256
+};
+
+# Support compression of Flash images
+# This CDL indicates whether flash images can
+# be decompressed from gzip/zlib format into RAM.
+#
+cdl_option CYGPRI_REDBOOT_ZLIB_FLASH {
+ # ActiveIf constraint: CYGPKG_REDBOOT_FLASH
+ # CYGPKG_REDBOOT_FLASH == 1
+ # --> 1
+ # ActiveIf constraint: (!CYGSEM_IO_FLASH_READ_INDIRECT) || CYGPRI_REDBOOT_ZLIB_FLASH_FORCE
+ # CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # CYGPRI_REDBOOT_ZLIB_FLASH_FORCE == 1
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+};
+
+# Include GZIP uncompress command
+# Enable this option to include a 'gunzip' command
+# to uncompress GZIP compressed data.
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_GUNZIP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Turn on CYGPRI_REDBOOT_ZLIB_FLASH
+# Force CYGPRI_REDBOOT_ZLIB_FLASH to be chosen
+#
+cdl_option CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGPRI_REDBOOT_ZLIB_FLASH
+ # ActiveIf: (!CYGSEM_IO_FLASH_READ_INDIRECT) || CYGPRI_REDBOOT_ZLIB_FLASH_FORCE
+};
+
+# <
+# Include support for xyzModem downloads
+# doc: ref/download-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_XYZMODEM {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Allow the load-command write into Flash.
+# Write images direct to Flash via the load command.
+# We assume anything which is invalid RAM is flash, hence
+# the requires statement
+#
+cdl_option CYGBLD_REDBOOT_LOAD_INTO_FLASH {
+ # ActiveIf constraint: CYGPKG_REDBOOT_FLASH
+ # CYGPKG_REDBOOT_FLASH == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS
+ # CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS == 1
+ # --> 1
+};
+
+# Include MS Windows CE support
+# doc: ref/wince.html
+# This option enables MS Windows CE EShell support
+# and Windows CE .BIN images support
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_WINCE_SUPPORT {
+ # Flavor: bool
+ user_value 1
+ # value_source user
+ # Default value: 0
+};
+
+# Include support for MXC USB downloads
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_MXCUSB {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Include support for i.MX USB OTG downloads
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_IMXOTG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Include POSIX checksum command
+# doc: ref/cksum-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_CKSUM {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include memory fill command
+# doc: ref/mfill-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_MFILL {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include memory compare command
+# doc: ref/mcmp-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_MCMP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include memory copy command
+# doc: ref/mcopy-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_MCOPY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include memory dump command
+# doc: ref/dump-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_DUMP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include cache command
+# doc: ref/cache-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include exec command
+# doc: ref/exec-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGPKG_REDBOOT_ARM_LINUX_EXEC
+ # ActiveIf: CYGBLD_BUILD_REDBOOT_WITH_EXEC
+};
+
+# Include I/O Memory commands 'iopeek' and 'iopoke'
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_IOMEM {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Granularity of timer/ticks
+# This option controls the granularity of the timers.
+# Faster CPUs can afford higher granularity (lower values)
+# which should give higher network performance since the stack
+# is purely polled.
+#
+cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 250
+ # value_source default
+ # Default value: 250
+ # Legal values: 10 25 50 100 250 500 1000
+};
+
+# Redboot Networking
+# This option includes networking support in RedBoot.
+#
+cdl_component CYGPKG_REDBOOT_NETWORKING {
+ # ActiveIf constraint: CYGPKG_IO_ETH_DRIVERS
+ # CYGPKG_IO_ETH_DRIVERS == current
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_IO_ETH_DRIVERS_PASS_PACKETS
+ # DefaultValue: 0 != CYGPKG_REDBOOT_NETWORKING
+};
+
+# >
+# Print net debug information
+# This option is overriden by the configuration stored
+# in flash.
+#
+cdl_option CYGDBG_REDBOOT_NET_DEBUG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Support TFTP for download
+# This option enables the use of the TFTP protocol for
+# download
+#
+cdl_option CYGSEM_REDBOOT_NET_TFTP_DOWNLOAD {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Support HTTP for download
+# This option enables the use of the HTTP protocol for
+# download
+#
+cdl_option CYGSEM_REDBOOT_NET_HTTP_DOWNLOAD {
+ # Flavor: bool
+ user_value 0
+ # value_source user
+ # Default value: 1
+};
+
+# Default IP address
+# This IP address is the default used by RedBoot if
+# a BOOTP/DHCP server does not respond. The numbers
+# should be separated by *commas*, and not dots. If
+# an IP address is configured into the Flash
+# configuration, that will be used in preference.
+#
+cdl_component CYGDAT_REDBOOT_DEFAULT_IP_ADDR {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 0 0
+};
+
+# >
+# Do not try to use BOOTP
+# By default Redboot tries to use BOOTP to get an IP
+# address. If there's no BOOTP server on your network
+# use this option to avoid to wait until the
+# timeout. This option is overriden by the
+# configuration stored in flash.
+#
+cdl_option CYGSEM_REDBOOT_DEFAULT_NO_BOOTP {
+ # This option is not active
+ # The parent CYGDAT_REDBOOT_DEFAULT_IP_ADDR is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Default bootp server
+# This IP address is the default server
+# address used by RedBoot if a BOOTP/DHCP
+# server does not respond. The numbers should
+# be separated by *commas*, and not dots. If
+# an IP address is configured into the Flash
+# configuration, that will be used in
+# preference.
+#
+cdl_option CYGDAT_REDBOOT_DEFAULT_BOOTP_SERVER_IP_ADDR {
+ # This option is not active
+ # The parent CYGDAT_REDBOOT_DEFAULT_IP_ADDR is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 0 0
+};
+
+# <
+# Use DHCP to get IP information
+# Use DHCP protocol to obtain pertinent IP addresses, such
+# as the client, server, gateway, etc.
+#
+cdl_component CYGSEM_REDBOOT_NETWORKING_DHCP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGSEM_REDBOOT_NETWORKING_USE_GATEWAY
+ # Requires: CYGSEM_REDBOOT_NETWORKING_DHCP
+};
+
+# Use a gateway for non-local IP traffic
+# Enabling this option will allow the RedBoot networking
+# stack to use a [single] gateway to reach a non-local
+# IP address. If disabled, RedBoot will only be able to
+# reach nodes on the same subnet.
+#
+cdl_component CYGSEM_REDBOOT_NETWORKING_USE_GATEWAY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGSEM_REDBOOT_NETWORKING_DHCP
+ # CYGSEM_REDBOOT_NETWORKING_DHCP == 1
+ # --> 1
+};
+
+# >
+# Default gateway IP address
+# This IP address is the default used by RedBoot
+# if a BOOTP/DHCP server does not respond. The
+# numbers should be separated by *commas*, and
+# not dots. If an IP address is configured into
+# the Flash configuration, that will be used in
+# preference.
+#
+cdl_component CYGDAT_REDBOOT_DEFAULT_GATEWAY_IP_ADDR {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 0 0
+};
+
+# Default IP address mask
+# This IP address mask is the default used by
+# RedBoot if a BOOTP/DHCP server does not
+# respond. The numbers should be separated by
+# *commas*, and not dots. If an IP address is
+# configured into the Flash configuration, that
+# will be used in preference.
+#
+cdl_component CYGDAT_REDBOOT_DEFAULT_IP_ADDR_MASK {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "255, 255, 255, 0"
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 0 0
+};
+
+# <
+# TCP port to listen for incoming connections
+# RedBoot will 'listen' on this port for incoming TCP
+# connections. This allows outside connections to be made
+# to the platform, either for GDB or RedBoot commands.
+#
+cdl_option CYGNUM_REDBOOT_NETWORKING_TCP_PORT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 9000
+ # value_source default
+ # Default value: 9000
+};
+
+# Number of [network] packet buffers
+# RedBoot may need to buffer network data to support
+# various connections. This option allows control
+# over the number of such buffered packets, and in
+# turn, controls the amount of memory used by RedBoot
+# (which is not available to user applications).
+# Each packet buffer takes up about 1514 bytes.
+# Note: there is little need to make this larger than
+# the default.
+#
+cdl_option CYGNUM_REDBOOT_NETWORKING_MAX_PKTBUF {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 4
+ # value_source default
+ # Default value: 4
+ # Legal values: 3 to 8
+};
+
+# DNS support
+# When this option is enabled, RedBoot will be built with
+# support for DNS, allowing use of hostnames on the command
+# line.
+#
+cdl_component CYGPKG_REDBOOT_NETWORKING_DNS {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_NS_DNS
+ # CYGPKG_NS_DNS (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: !CYGPKG_NS_DNS_BUILD
+ # CYGPKG_NS_DNS_BUILD (unknown) == 0
+ # --> 1
+};
+
+# >
+# Default DNS IP
+# This option sets the IP of the default DNS. The IP can be
+# changed at runtime as well.
+#
+cdl_option CYGPKG_REDBOOT_NETWORKING_DNS_IP {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS is not active
+ # ActiveIf constraint: !CYGSEM_REDBOOT_FLASH_CONFIG
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 0
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0.0.0.0
+ # value_source default
+ # Default value: 0.0.0.0
+};
+
+# Timeout in DNS lookup
+# This option sets the timeout used when looking up an
+# address via the DNS. Default is 10 seconds.
+#
+cdl_option CYGNUM_REDBOOT_NETWORKING_DNS_TIMEOUT {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS is not active
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 10
+ # value_source default
+ # Default value: 10
+};
+
+# Support the use of a domain name
+# This option controls if Redboot supports domain
+# names when performing DNS lookups
+#
+cdl_component CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# >
+# Default DNS domain
+# This option sets the default DNS domain name.
+# This value will be overwritten by the value in
+# flash or a domain returned by DHCP
+#
+cdl_option CYGPKG_REDBOOT_NETWORKING_DNS_DEFAULT_DOMAIN {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Get DNS domain from Flash
+# This option enables getting the domain name
+# from the flash configuration. This can later be
+# overwritten by a value learnt from DHCP
+#
+cdl_option CYGPKG_REDBOOT_NETWORKING_DNS_FCONFIG_DOMAIN {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is disabled
+ # ActiveIf constraint: CYGSEM_REDBOOT_FLASH_CONFIG
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Use DNS domain from DHCP
+# This option enables the use of the domain name
+# returned by DHCP.
+#
+cdl_option CYGPKG_REDBOOT_NETWORKING_DNS_DHCP_DOMAIN {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# BOOTP/DHCP DNS domain buffer size
+# This options sets the size of the static
+# buffer used by BOOTP/DHCP to store the DNS
+# domain name. The domain name will not be
+# set if the buffer is too small to hold it.
+#
+cdl_option CYGNUM_REDBOOT_NETWORK_DNS_DOMAIN_BUFSIZE {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 32
+ # value_source default
+ # Default value: 32
+};
+
+# <
+# <
+# Default network device driver
+# This is the name of the default network device to use.
+#
+cdl_option CYGDAT_REDBOOT_DEFAULT_NETWORK_DEVICE {
+ # This option is not active
+ # ActiveIf constraint: CYGHWR_NET_DRIVERS > 1
+ # CYGHWR_NET_DRIVERS == 1
+ # --> 0
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "\"\""
+ # value_source default
+ # Default value: "\"\""
+};
+
+# Initialize only one net device
+# This option tells RedBoot to stop initializing network
+# devices when it finds the first device which is
+# successfully initialized. The default behavior causes
+# all network devices to be initialized.
+#
+cdl_option CYGSEM_REDBOOT_NETWORK_INIT_ONE_DEVICE {
+ # This option is not active
+ # ActiveIf constraint: CYGHWR_NET_DRIVERS > 1
+ # CYGHWR_NET_DRIVERS == 1
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Let RedBoot use any I/O channel for its console.
+# If this option is enabled then RedBoot will attempt to use all
+# defined serial I/O channels for its console device. Once input
+# arrives at one of these channels then the console will use only
+# that port.
+#
+cdl_option CYGPKG_REDBOOT_ANY_CONSOLE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+};
+
+# Let RedBoot adjust the baud rate of the serial console.
+# If this option is enabled then RedBoot will support commands
+# to set and query the baud rate on the selected console.
+#
+cdl_option CYGSEM_REDBOOT_VARIABLE_BAUD_RATE {
+ # ActiveIf constraint: CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+ # CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Run a platform specific startup function.
+# If this option is enabled then RedBoot will execute a platform
+# specific startup function before entering into its command line
+# processing. This allows the platform to perform any special
+# setups before RedBoot actually starts running. Note: the entire
+# RedBoot environment will already be initialized at this point.
+#
+cdl_option CYGSEM_REDBOOT_PLF_STARTUP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Run a platform specific ESA validation function.
+# If this option is enabled then RedBoot will execute a platform
+# specific function to validate an ethernet ESA. This would be
+# useful if the address must conform to standards set by the
+# hardware manufacturer, etc.
+#
+cdl_option CYGSEM_REDBOOT_PLF_ESA_VALIDATE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # component CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
+ # Requires: CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ # option CYGDAT_DEVS_ETH_ARM_TX25KARO_OUI
+ # ActiveIf: CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+};
+
+# Maximum command line length
+# This option allows control over how long the CLI command line
+# should be. This space will be allocated statically
+# rather than from RedBoot's stack.
+#
+cdl_option CYGPKG_REDBOOT_MAX_CMD_LINE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 256
+ # The inferred value should not be edited directly.
+ inferred_value 1024
+ # value_source inferred
+ # Default value: 256
+};
+
+# Command processing idle timeout (ms)
+# This option controls the timeout period before the
+# command processing is considered 'idle'. Making this
+# number smaller will cause idle processing to take place
+# more often, etc. The default value of 10ms is a reasonable
+# tradeoff between responsiveness and overhead.
+#
+cdl_option CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 10
+ # value_source default
+ # Default value: 10
+};
+
+# Validate RAM addresses during load
+# This option controls whether or not RedBoot will make
+# sure that memory being used by the "load" command is
+# in fact in user RAM. Leaving the option enabled makes
+# for a safer environment, but this check may not be valid
+# on all platforms, thus the ability to disable it.
+# ** Disable this only with great care **
+#
+cdl_option CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ # Requires: CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS
+};
+
+# Allow RedBoot to support FLASH programming
+# If this option is enabled then RedBoot will provide commands
+# to manage images in FLASH memory. These images can be loaded
+# into memory for execution or executed in place.
+#
+cdl_component CYGPKG_REDBOOT_FLASH {
+ # ActiveIf constraint: CYGHWR_IO_FLASH_DEVICE
+ # CYGHWR_IO_FLASH_DEVICE == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGPRI_REDBOOT_ZLIB_FLASH
+ # ActiveIf: CYGPKG_REDBOOT_FLASH
+ # option CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ # ActiveIf: CYGPKG_REDBOOT_FLASH
+};
+
+# >
+# Byte order used to store info in flash.
+# This option controls the byte ordering used to store
+# the FIS directory info and flash config info.
+#
+cdl_option CYGOPT_REDBOOT_FLASH_BYTEORDER {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value NATURAL
+ # value_source default
+ # Default value: NATURAL
+ # Legal values: "NATURAL" "MSBFIRST" "LSBFIRST"
+};
+
+# RedBoot Flash Image System support
+# doc: ref/flash-image-system.html
+# This option enables the Flash Image System commands
+# and support within RedBoot. If disabled, simple Flash
+# access commands such as "fis write" will still exist.
+# This option would be disabled for targets that need simple
+# FLASH manipulation, but do not have the need or space for
+# complete image management.
+#
+cdl_option CYGOPT_REDBOOT_FIS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGPKG_REDBOOT_FIS_CONTENTS
+ # ActiveIf: CYGOPT_REDBOOT_FIS
+ # option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
+ # ActiveIf: CYGOPT_REDBOOT_FIS && (CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == "FLASH")
+ # component CYGOPT_REDBOOT_FIS_ZLIB_COMMON_BUFFER
+ # ActiveIf: CYGBLD_BUILD_REDBOOT_WITH_ZLIB && CYGOPT_REDBOOT_FIS
+};
+
+# Max number of chunks of free space to manage
+# If this option is defined then "fis free" will
+# rely on the FIS directory to determine what space is
+# free within the FLASH. This option controls the
+# maximum number of free segment which can be handled
+# (typically this number is small). If this option is
+# not enabled, the the archaic behaviour of actually
+# scanning the FLASH for erased sectors (unreliable)
+# will be used to determine what's free and what's
+# not.
+#
+cdl_option CYGDAT_REDBOOT_FIS_MAX_FREE_CHUNKS {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 1 32
+ # value_source default
+ # Default value: 1 32
+};
+
+# Flash Image System default directory contents
+#
+cdl_component CYGPKG_REDBOOT_FIS_CONTENTS {
+ # ActiveIf constraint: CYGOPT_REDBOOT_FIS
+ # CYGOPT_REDBOOT_FIS == 1
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+};
+
+# >
+# Flash block containing the Directory
+# Which block of flash should hold the directory
+# information. Positive numbers are absolute block
+# numbers. Negative block numbers count backwards
+# from the last block. eg 2 means block 2, -2
+# means the last but one block.
+#
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -1
+ # value_source default
+ # Default value: -1
+
+ # The following properties are affected by this value
+ # option CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK
+ # Requires: CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK !=
+ # CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK
+};
+
+# Redundant Flash Image System Directory Support
+# This option enables the use of a redundant FIS
+# directory within RedBoot. If enabled a flash block
+# will be reserved for a second copy of the fis
+# directory. Doing this allow for power failure safe
+# updates of the directory by the application.
+#
+cdl_component CYGOPT_REDBOOT_REDUNDANT_FIS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: 0 == CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
+ # CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG == 1
+ # --> 0
+};
+
+# >
+# Flash block containing the backup Directory
+# Which block of flash should hold the redundant
+# directory information. Positive numbers are
+# absolute block numbers. Negative block numbers
+# count backwards from the last block. eg 2 means
+# block 2, -2 means the last but one block.
+#
+cdl_option CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK {
+ # This option is not active
+ # The parent CYGOPT_REDBOOT_REDUNDANT_FIS is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -3
+ # value_source default
+ # Default value: -3
+ # Requires: CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK !=
+ # CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK
+ # CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK == 0
+ # CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK == -1
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK
+ # Requires: CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK !=
+ # CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK
+};
+
+# <
+# Pseudo-file to describe reserved area
+# If an area of FLASH is reserved, it is informative to
+# have a fis entry describing it. This option controls
+# creation of such an entry by default in the fis init
+# command.
+#
+cdl_option CYGOPT_REDBOOT_FIS_RESERVED_BASE {
+ # This option is not active
+ # ActiveIf constraint: 0 != CYGNUM_REDBOOT_FLASH_RESERVED_BASE
+ # CYGNUM_REDBOOT_FLASH_RESERVED_BASE == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# File to describe RedBoot boot image
+# Normally a ROM-startup RedBoot image is first in the
+# FLASH, and the system boots using that image. This
+# option controls creation of an entry describing it in
+# the fis init command. It might be disabled if a
+# platform has an immutable boot image of its own, where
+# we use a POST-startup RedBoot instead, which performs
+# less board initialization.
+#
+cdl_option CYGOPT_REDBOOT_FIS_REDBOOT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGOPT_REDBOOT_FIS_REDBOOT_POST
+ # DefaultValue: !CYGOPT_REDBOOT_FIS_REDBOOT
+ # option CYGBLD_REDBOOT_MIN_IMAGE_SIZE
+ # DefaultValue: CYGOPT_REDBOOT_FIS_REDBOOT ? 0x20000 : 0
+};
+
+# File to describe RedBoot POST-compatible image
+# This option controls creation of an entry describing a
+# POST-startup RedBoot image in the fis init command.
+# Not all platforms support POST-startup. A platform
+# might have both for testing purposes, where the
+# eventual user would substitute their own POST code for
+# the initial ROM-startup RedBoot, and then jump to the
+# POST-compatible RedBoot immediately following.
+#
+cdl_component CYGOPT_REDBOOT_FIS_REDBOOT_POST {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: !CYGOPT_REDBOOT_FIS_REDBOOT
+ # CYGOPT_REDBOOT_FIS_REDBOOT == 1
+ # --> 0
+};
+
+# >
+# Offset of POST image from FLASH start
+# This option specifies the offset for a POST image from
+# the start of FLASH. If unset, then the fis entry
+# describing the POST image will be placed where
+# convenient.
+#
+cdl_option CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET {
+ # This option is not active
+ # The parent CYGOPT_REDBOOT_FIS_REDBOOT_POST is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+ # Requires: CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET >= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET == 0
+ # CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET
+ # Requires: CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET >= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+};
+
+# <
+# File to describe RedBoot backup image
+# This option controls creation of an entry describing a
+# backup RedBoot image in the fis init command.
+# Conventionally a RAM-startup RedBoot image is kept
+# under this name for use in updating the ROM-based
+# RedBoot that boots the board.
+#
+cdl_option CYGOPT_REDBOOT_FIS_REDBOOT_BACKUP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Include ARM SIB ID in FIS
+# If set, this option will cause the last 5 words of
+# the FIS to include the special ID needed for the
+# flash to be recognized as a reserved area for RedBoot
+# by an ARM BootRom monitor.
+#
+cdl_option CYGOPT_REDBOOT_FIS_DIRECTORY_ARM_SIB_ID {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Size of FIS directory entry
+# The FIS directory is limited to one single flash
+# sector. If your flash has tiny sectors, you may wish
+# to reduce this value in order to get more slots in
+# the FIS directory.
+#
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 256
+ # value_source default
+ # Default value: 256
+};
+
+# Number of FIS directory entries
+# The FIS directory normally occupies a single flash
+# sector. Adjusting this value can allow for more than
+# one flash sector to be used, which is useful if your
+# sectors are very small.
+#
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_COUNT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 8
+ # value_source default
+ # Default value: 8
+};
+
+# Maximum RedBoot image size
+# This option controls the maximum length reserved
+# for the RedBoot boot image in the FIS table.
+# This should be a multiple of the flash's erase
+# block size.
+#
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00020000
+ # The inferred value should not be edited directly.
+ inferred_value 0x00040000
+ # value_source inferred
+ # Default value: CYGOPT_REDBOOT_FIS_REDBOOT ? 0x20000 : 0
+ # CYGOPT_REDBOOT_FIS_REDBOOT == 1
+ # --> 0x00020000
+};
+
+# Offset from start of FLASH to RedBoot boot image
+# This option controls where the RedBoot boot image is
+# located relative to the start of FLASH.
+#
+cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGNUM_REDBOOT_FLASH_RESERVED_BASE
+ # CYGNUM_REDBOOT_FLASH_RESERVED_BASE == 0
+ # --> 0
+ # Requires: CYGNUM_REDBOOT_FLASH_RESERVED_BASE <= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # CYGNUM_REDBOOT_FLASH_RESERVED_BASE == 0
+ # CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET
+ # Requires: CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET >= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # Requires: CYGNUM_REDBOOT_FLASH_RESERVED_BASE <= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # component CYGPKG_HAL_ARM_TX25_OPTIONS
+ # Requires: CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0
+};
+
+# Size of reserved area at start of FLASH
+# This option reserves an area at the start of
+# FLASH where RedBoot will never interfere; it is
+# expected that this area contains
+# (non-RedBoot-based) POST code or some other boot
+# monitor that executes before RedBoot.
+#
+cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGOPT_REDBOOT_FIS_RESERVED_BASE
+ # ActiveIf: 0 != CYGNUM_REDBOOT_FLASH_RESERVED_BASE
+ # option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # DefaultValue: CYGNUM_REDBOOT_FLASH_RESERVED_BASE
+ # option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # Requires: CYGNUM_REDBOOT_FLASH_RESERVED_BASE <= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+};
+
+# <
+# Keep all RedBoot FLASH data blocks locked.
+# When this option is enabled, RedBoot will keep configuration
+# data and the FIS directory blocks implicitly locked. While
+# this is somewhat safer, it does add overhead during updates.
+#
+cdl_option CYGSEM_REDBOOT_FLASH_LOCK_SPECIAL {
+ # This option is not active
+ # ActiveIf constraint: CYGHWR_IO_FLASH_BLOCK_LOCKING != 0
+ # CYGHWR_IO_FLASH_BLOCK_LOCKING == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Use CRC checksums on FIS images.
+# When this option is enabled, RedBoot will use CRC checksums
+# when reading and writing flash images.
+#
+cdl_option CYGSEM_REDBOOT_FIS_CRC_CHECK {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# ARM FLASH drivers support SIB flash block structure
+# This interface is implemented by a flash driver
+# to indicate that it supports the ARM SIB flash
+# block structure
+#
+cdl_interface CYGINT_REDBOOT_ARM_FLASH_SIB_SUPPORTED {
+ # No options implement this inferface
+ # ActiveIf constraint: CYGPKG_HAL_ARM
+ # CYGPKG_HAL_ARM == current
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_REDBOOT_ARM_FLASH_SIB
+ # ActiveIf: CYGINT_REDBOOT_ARM_FLASH_SIB_SUPPORTED
+};
+
+# Use ARM SIB flash block structure
+# This option is used to interpret ARM Flash System
+# information blocks.
+#
+cdl_option CYGHWR_REDBOOT_ARM_FLASH_SIB {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_REDBOOT_ARM_FLASH_SIB_SUPPORTED
+ # CYGINT_REDBOOT_ARM_FLASH_SIB_SUPPORTED == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Keep RedBoot configuration data in FLASH
+# When this option is enabled, RedBoot will keep configuration
+# data in a separate block of FLASH memory. This data will
+# include such items as the node IP address or startup scripts.
+#
+cdl_component CYGSEM_REDBOOT_FLASH_CONFIG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGPKG_IO_FLASH != 0
+ # CYGPKG_IO_FLASH == current
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGDAT_REDBOOT_DEFAULT_IP_ADDR
+ # DefaultValue: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # option CYGDAT_REDBOOT_DEFAULT_BOOTP_SERVER_IP_ADDR
+ # DefaultValue: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # component CYGDAT_REDBOOT_DEFAULT_GATEWAY_IP_ADDR
+ # DefaultValue: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # component CYGDAT_REDBOOT_DEFAULT_IP_ADDR_MASK
+ # DefaultValue: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "255, 255, 255, 0"
+ # option CYGPKG_REDBOOT_NETWORKING_DNS_IP
+ # ActiveIf: !CYGSEM_REDBOOT_FLASH_CONFIG
+ # option CYGPKG_REDBOOT_NETWORKING_DNS_FCONFIG_DOMAIN
+ # ActiveIf: CYGSEM_REDBOOT_FLASH_CONFIG
+ # option CYGFUN_REDBOOT_BOOT_SCRIPT
+ # ActiveIf: CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT || CYGSEM_REDBOOT_FLASH_CONFIG
+};
+
+# >
+# Length of configuration data in FLASH
+# This option is used to control the amount of memory and FLASH
+# to be used for configuration options (persistent storage).
+#
+cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 4096
+ # value_source default
+ # Default value: 4096
+};
+
+# Style of media used for persistent data storage
+# Persistent data storage can either be held in 'norma' FLASH
+# or some other device (represented by the 'EEPROM' choice).
+# The different styles utilize different access methods.
+#
+cdl_option CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value FLASH
+ # value_source default
+ # Default value: FLASH
+ # Legal values: "FLASH" "EEPROM"
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
+ # ActiveIf: CYGOPT_REDBOOT_FIS && (CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == "FLASH")
+ # option CYGSEM_REDBOOT_FLASH_CONFIG_READONLY_FALLBACK
+ # DefaultValue: (CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == "FLASH")
+};
+
+# Merged config data and FIS directory
+# If this option is set, then the FIS directory and FLASH
+# configuration database will be stored in the same physical
+# FLASH block.
+#
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+ # ActiveIf constraint: CYGOPT_REDBOOT_FIS && (CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == "FLASH")
+ # CYGOPT_REDBOOT_FIS == 1
+ # CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == FLASH
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGOPT_REDBOOT_REDUNDANT_FIS
+ # Requires: 0 == CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
+};
+
+# Which block of flash to use
+# Which block of flash should hold the configuration
+# information. Positive numbers are absolute block numbers.
+# Negative block numbers count backwards from the last block.
+# eg 2 means block 2, -2 means the last but one block.
+#
+cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -2
+ # value_source default
+ # Default value: -2
+};
+
+# Support simple macros/aliases in FLASH
+# This option is used to allow support for simple text-based
+# macros (aliases). These aliases are kept in the FLASH
+# configuration data (persistent storage).
+#
+cdl_option CYGSEM_REDBOOT_FLASH_ALIASES {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Length of strings in FLASH configuration data
+# This option is used to control the amount of memory
+# and FLASH to be used for string configuration
+# options (persistent storage).
+#
+cdl_option CYGNUM_REDBOOT_FLASH_STRING_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 128
+ # value_source default
+ # Default value: 128
+};
+
+# Length of configuration script(s) in FLASH
+# This option is used to control the amount of memory and
+# FLASH to be used for configuration options (persistent
+# storage).
+#
+cdl_option CYGNUM_REDBOOT_FLASH_SCRIPT_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 512
+ # The inferred value should not be edited directly.
+ inferred_value 2048
+ # value_source inferred
+ # Default value: 512
+};
+
+# Fallback to read-only FLASH configuration
+# This option will cause the configuration information to
+# revert to the readonly information stored in the FLASH.
+# The option only takes effect after
+# 1) the config_ok flag has been set to be true,
+# indicating that at one time the copy in RAM was valid;
+# and
+# 2) the information in RAM has been verified to be invalid
+#
+cdl_option CYGSEM_REDBOOT_FLASH_CONFIG_READONLY_FALLBACK {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: (CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == "FLASH")
+ # CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == FLASH
+ # --> 1
+};
+
+# <
+# Allow RedBoot to support fileio
+# If this option is enabled then RedBoot will provide commands
+# to load files from fileio file systems such as JFFS2.
+#
+cdl_component CYGPKG_REDBOOT_FILEIO {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_IO_FILEIO
+ # CYGPKG_IO_FILEIO (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_REDBOOT_GETC_BUFFER
+ # DefaultValue: CYGPKG_REDBOOT_FILEIO ? 4096 : 256
+};
+
+# >
+# Include an ls command
+# If this option is enabled a simple ls command will be
+# included in redboot so the contents of a directory
+# can be listed
+#
+cdl_option CYGBLD_REDBOOT_FILEIO_WITH_LS {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_FILEIO is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Allow RedBoot to support disks
+# If this option is enabled then RedBoot will provide commands
+# to load disk files.
+#
+cdl_component CYGPKG_REDBOOT_DISK {
+ # Flavor: bool
+ user_value 0
+ # value_source user
+ # Default value: 1
+};
+
+# >
+# Include Redboot commands for disk access
+#
+cdl_option CYGSEM_REDBOOT_DISK {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGINT_REDBOOT_DISK_DRIVERS != 0
+ # CYGINT_REDBOOT_DISK_DRIVERS == 0
+ # --> 0
+};
+
+# Hardware drivers for disk-type devices
+#
+cdl_interface CYGINT_REDBOOT_DISK_DRIVERS {
+ # Implemented by CYGSEM_REDBOOT_DISK_IDE, inactive, enabled
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_DISK
+ # DefaultValue: CYGINT_REDBOOT_DISK_DRIVERS != 0
+};
+
+# Maximum number of supported disks
+# This option controls the number of disks supported by
+# RedBoot.
+#
+cdl_option CYGNUM_REDBOOT_MAX_DISKS {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 4
+ # value_source default
+ # Default value: 4
+};
+
+# Maximum number of partitions per disk
+# This option controls the maximum number of supported
+# partitions per disk.
+#
+cdl_option CYGNUM_REDBOOT_MAX_PARTITIONS {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 8
+ # value_source default
+ # Default value: 8
+};
+
+# Support IDE disks.
+# When this option is enabled, RedBoot will support IDE disks.
+#
+cdl_component CYGSEM_REDBOOT_DISK_IDE {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+ # ActiveIf constraint: CYGINT_HAL_PLF_IF_IDE != 0
+ # CYGINT_HAL_PLF_IF_IDE == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Work with VMware virtual disks
+# This option controls the disk driver behavior at
+# ide-init
+#
+cdl_option CYGSEM_REDBOOT_DISK_IDE_VMWARE {
+ # This option is not active
+ # The parent CYGSEM_REDBOOT_DISK_IDE is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Support Linux second extended filesystems.
+# When this option is enabled, RedBoot will support EXT2
+# filesystems.
+#
+cdl_component CYGSEM_REDBOOT_DISK_EXT2FS {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Support ISO9660 filesystems.
+# When this option is enabled, RedBoot will support ISO9660
+# filesystems.
+#
+cdl_component CYGSEM_REDBOOT_DISK_ISO9660 {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # Calculated value: 0
+ # Flavor: bool
+ # Current value: 0
+};
+
+# <
+# Boot scripting
+# doc: ref/persistent-state-flash.html
+# This contains options related to RedBoot's boot script
+# functionality.
+#
+cdl_component CYGPKG_REDBOOT_BOOT_SCRIPT {
+ # There is no associated value.
+};
+
+# >
+# Boot scripting enabled
+# This option controls whether RedBoot boot script
+# functionality is enabled.
+#
+cdl_option CYGFUN_REDBOOT_BOOT_SCRIPT {
+ # ActiveIf constraint: CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT || CYGSEM_REDBOOT_FLASH_CONFIG
+ # CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT == 0
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+};
+
+# Use default RedBoot boot script
+# If enabled, this option will tell RedBoot to use the
+# value of this option as a default boot script.
+#
+cdl_option CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGFUN_REDBOOT_BOOT_SCRIPT
+ # ActiveIf: CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT || CYGSEM_REDBOOT_FLASH_CONFIG
+};
+
+# Resolution (in ms) for script timeout value.
+# This option controls the resolution of the script
+# timeout. The value is specified in milliseconds
+# (ms), thus to have the script timeout be defined in
+# terms of tenths of seconds, use 100.
+#
+cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_TIMEOUT_RESOLUTION {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 1000
+ # The inferred value should not be edited directly.
+ inferred_value 10
+ # value_source inferred
+ # Default value: 1000
+};
+
+# Script default timeout value
+# This option is used to set the default timeout for startup
+# scripts, when they are enabled.
+#
+cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_DEFAULT_TIMEOUT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 10
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 10
+};
+
+# <
+# Support RTC for time & date functions
+# When this option is enabled, RedBoot will support commands to
+# query and set the real time clock (time and date)
+#
+cdl_option CYGSEM_REDBOOT_RTC {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_IO_WALLCLOCK
+ # CYGPKG_IO_WALLCLOCK (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Behave like a ROM monitor
+# Enabling this option will allow RedBoot to provide ROM
+# monitor-style services to programs which it executes.
+#
+cdl_option CYGPRI_REDBOOT_ROM_MONITOR {
+ # ActiveIf constraint: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+ # Requires: CYGSEM_HAL_ROM_MONITOR
+ # CYGSEM_HAL_ROM_MONITOR == 1
+ # --> 1
+};
+
+# Allow RedBoot to handle GNUPro application 'syscalls'.
+# If this option is enabled then RedBoot will install a
+# syscall handler to support debugging of applications
+# based on GNUPro newlib/bsp.
+#
+cdl_component CYGSEM_REDBOOT_BSP_SYSCALLS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGOPT_HAL_ARM_SYSCALL_GPROF_SUPPORT
+ # ActiveIf: CYGSEM_REDBOOT_BSP_SYSCALLS
+ # option CYGPKG_HAL_GDB_FILEIO
+ # ActiveIf: CYGSEM_REDBOOT_BSP_SYSCALLS
+};
+
+# >
+# Support additional syscalls for 'gprof' profiling
+# Support additional syscalls to support a periodic callback
+# function for histogram-style profiling, and an enquire/set
+# of the tick rate.
+# The application must use the GNUPro newlib facilities
+# to set this up.
+#
+cdl_option CYGSEM_REDBOOT_BSP_SYSCALLS_GPROF {
+ # This option is not active
+ # The parent CYGSEM_REDBOOT_BSP_SYSCALLS is disabled
+ # ActiveIf constraint: 0 < CYGINT_REDBOOT_BSP_SYSCALLS_GPROF_SUPPORT
+ # CYGINT_REDBOOT_BSP_SYSCALLS_GPROF_SUPPORT == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Does the HAL support 'gprof' profiling?
+#
+cdl_interface CYGINT_REDBOOT_BSP_SYSCALLS_GPROF_SUPPORT {
+ # Implemented by CYGOPT_HAL_ARM_SYSCALL_GPROF_SUPPORT, inactive, enabled
+ # This option is not active
+ # The parent CYGSEM_REDBOOT_BSP_SYSCALLS is disabled
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_BSP_SYSCALLS_GPROF
+ # ActiveIf: 0 < CYGINT_REDBOOT_BSP_SYSCALLS_GPROF_SUPPORT
+};
+
+# Do not raise SIGTRAP when program exits
+# For some (single shot) newlib based programs,
+# exiting and returning a termination status may be
+# the normal expected behavior.
+#
+cdl_option CYGOPT_REDBOOT_BSP_SYSCALLS_EXIT_WITHOUT_TRAP {
+ # This option is not active
+ # The parent CYGSEM_REDBOOT_BSP_SYSCALLS is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Use a common buffer for Zlib and FIS
+# Use a common memory buffer for both the zlib workspace
+# and FIS directory operations. This can save a substantial
+# amount of RAM, especially when flash sectors are large.
+#
+cdl_component CYGOPT_REDBOOT_FIS_ZLIB_COMMON_BUFFER {
+ # ActiveIf constraint: CYGBLD_BUILD_REDBOOT_WITH_ZLIB && CYGOPT_REDBOOT_FIS
+ # CYGBLD_BUILD_REDBOOT_WITH_ZLIB == 1
+ # CYGOPT_REDBOOT_FIS == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# >
+# Size of Zlib/FIS common buffer
+# Size of common buffer to allocate. Must be at least the
+# size of one flash sector.
+#
+cdl_option CYGNUM_REDBOOT_FIS_ZLIB_COMMON_BUFFER_SIZE {
+ # This option is not active
+ # The parent CYGOPT_REDBOOT_FIS_ZLIB_COMMON_BUFFER is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x0000C000
+ # value_source default
+ # Default value: 0x0000C000
+ # Legal values: 0x4000 to 0x80000000
+};
+
+# <
+# Buffer size in getc when loading images
+# When loading images a buffer is used between redboot and the
+# underlying storage medium, eg a filesystem, or a socket etc.
+# The size of this buffer can have a big impart on load speed.
+#
+cdl_option CYGNUM_REDBOOT_GETC_BUFFER {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 256
+ # value_source default
+ # Default value: CYGPKG_REDBOOT_FILEIO ? 4096 : 256
+ # CYGPKG_REDBOOT_FILEIO == 0
+ # --> 256
+};
+
+# <
+# Redboot for ARM options
+# This option lists the target's requirements for a valid Redboot
+# configuration.
+#
+cdl_component CYGPKG_REDBOOT_ARM_OPTIONS {
+ # ActiveIf constraint: CYGPKG_REDBOOT
+ # CYGPKG_REDBOOT == current
+ # --> 1
+
+ # There is no associated value.
+
+ # The following properties are affected by this value
+};
+
+# >
+# Provide the exec command in RedBoot
+# This option contains requirements for booting linux
+# from RedBoot. The component is enabled/disabled from
+# RedBoots CDL.
+#
+cdl_component CYGPKG_REDBOOT_ARM_LINUX_EXEC {
+ # ActiveIf constraint: CYGBLD_BUILD_REDBOOT_WITH_EXEC
+ # CYGBLD_BUILD_REDBOOT_WITH_EXEC == 1
+ # --> 1
+
+ # There is no associated value.
+};
+
+# >
+# Enable -x switch for exec command.
+# This option allows bi-endian platforms to launch kernels
+# built for an endianess different than the RedBoot endianess
+#
+cdl_option CYGHWR_REDBOOT_LINUX_EXEC_X_SWITCH {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Physical base address of linux kernel
+# This is the physical address of the base of the
+# Linux kernel image.
+#
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x80108000
+ # value_source default
+ # Default value: CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT
+ # CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x80108000
+ # --> 0x80108000
+};
+
+# Default physical base address of linux kernel
+# This is the physical address of the base of the
+# Linux kernel image. This option gets set by the
+# platform CDL.
+#
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00008000
+ # The inferred value should not be edited directly.
+ inferred_value 0x80108000
+ # value_source inferred
+ # Default value: 0x00008000
+
+ # The following properties are affected by this value
+ # option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS
+ # DefaultValue: CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT
+ # component CYGPKG_REDBOOT_HAL_TX25_OPTIONS
+ # Requires: CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x80108000
+};
+
+# Base address of linux kernel parameter tags
+# This is the base address of the area of memory used to
+# pass parameters to the Linux kernel. This should be chosen
+# to avoid overlap with the kernel and any ramdisk image.
+#
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_TAGS_ADDRESS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00000100
+ # value_source default
+ # Default value: 0x00000100
+};
+
+# <
+# <
+# Redboot HAL options
+# This option lists the target's requirements for a valid Redboot
+# configuration.
+#
+cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ # ActiveIf constraint: CYGPKG_REDBOOT
+ # CYGPKG_REDBOOT == current
+ # --> 1
+
+ # There is no associated value.
+};
+
+# >
+# Build Redboot ROM binary image
+# This option enables the conversion of the Redboot ELF
+# image to a binary image suitable for ROM programming.
+#
+cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ # ActiveIf constraint: CYGBLD_BUILD_REDBOOT
+ # CYGBLD_BUILD_REDBOOT == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Redboot HAL variant options
+#
+cdl_component CYGPKG_REDBOOT_HAL_TX25_OPTIONS {
+ # ActiveIf constraint: CYGPKG_REDBOOT
+ # CYGPKG_REDBOOT == current
+ # --> 1
+
+ # There is no associated value.
+ # Requires: CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x80108000
+ # CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x80108000
+ # --> 1
+};
+
+# <
+# ISO C and POSIX infrastructure
+# eCos supports implementations of ISO C libraries and POSIX
+# implementations. This package provides infrastructure used by
+# all such implementations.
+#
+cdl_package CYGPKG_ISOINFRA {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGPKG_ISOINFRA
+ # package CYGPKG_LIBC_STRING
+ # Requires: CYGPKG_ISOINFRA
+ # package CYGPKG_COMPRESS_ZLIB
+ # Requires: CYGPKG_ISOINFRA
+ # package CYGPKG_IO_FLASH
+ # Requires: CYGPKG_ISOINFRA
+ # option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_USE_MEMCPY
+ # Requires: CYGPKG_ISOINFRA
+ # option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_USE_MEMCPY
+ # DefaultValue: 0 != CYGPKG_ISOINFRA
+ # component CYGPKG_MEMALLOC_MALLOC_ALLOCATORS
+ # ActiveIf: CYGPKG_ISOINFRA
+ # package CYGPKG_LIBC_I18N
+ # Requires: CYGPKG_ISOINFRA
+ # package CYGPKG_LIBC_STDLIB
+ # Requires: CYGPKG_ISOINFRA
+};
+
+# >
+# Startup and termination
+#
+cdl_component CYGPKG_ISO_STARTUP {
+ # There is no associated value.
+};
+
+# >
+# main() startup implementations
+# Implementations of this interface arrange for a user-supplied
+# main() to be called in an ISO compatible environment.
+#
+cdl_interface CYGINT_ISO_MAIN_STARTUP {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_MAIN_STARTUP
+ # CYGINT_ISO_MAIN_STARTUP == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_MAIN_STARTUP
+ # Requires: 1 >= CYGINT_ISO_MAIN_STARTUP
+};
+
+# environ implementations
+# Implementations of this interface provide the environ
+# variable required by POSIX.
+#
+cdl_interface CYGINT_ISO_ENVIRON {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_ENVIRON
+ # CYGINT_ISO_ENVIRON == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_ENVIRON
+ # Requires: 1 >= CYGINT_ISO_ENVIRON
+};
+
+# <
+# ctype.h functions
+#
+cdl_component CYGPKG_ISO_CTYPE_H {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of ctype functions
+#
+cdl_interface CYGINT_ISO_CTYPE {
+ # Implemented by CYGPKG_LIBC_I18N, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_CTYPE
+ # CYGINT_ISO_CTYPE == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_CTYPE
+ # Requires: 1 >= CYGINT_ISO_CTYPE
+ # package CYGPKG_HAL_ARM_TX25KARO
+ # Requires: CYGINT_ISO_CTYPE
+ # option CYGFUN_LIBC_STRING_BSD_FUNCS
+ # Requires: CYGINT_ISO_CTYPE
+ # package CYGPKG_LIBC_STDLIB
+ # Requires: CYGINT_ISO_CTYPE
+};
+
+# Ctype implementation header
+#
+cdl_option CYGBLD_ISO_CTYPE_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/i18n/ctype.inl>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGPKG_LIBC_I18N_NEWLIB_CTYPE
+ # Requires: CYGBLD_ISO_CTYPE_HEADER == "<cyg/libc/i18n/newlibctype.h>"
+ # option CYGIMP_LIBC_I18N_CTYPE_INLINES
+ # Requires: CYGBLD_ISO_CTYPE_HEADER == "<cyg/libc/i18n/ctype.inl>"
+};
+
+# <
+# Error handling
+#
+cdl_component CYGPKG_ISO_ERRNO {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of error codes
+#
+cdl_interface CYGINT_ISO_ERRNO_CODES {
+ # Implemented by CYGPKG_ERROR, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_ERRNO_CODES
+ # CYGINT_ISO_ERRNO_CODES == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_ERRNO_CODES
+ # Requires: 1 >= CYGINT_ISO_ERRNO_CODES
+};
+
+# Error codes implementation header
+#
+cdl_option CYGBLD_ISO_ERRNO_CODES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/error/codes.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # package CYGPKG_ERROR
+ # Requires: CYGBLD_ISO_ERRNO_CODES_HEADER == "<cyg/error/codes.h>"
+};
+
+# Number of implementations of errno variable
+#
+cdl_interface CYGINT_ISO_ERRNO {
+ # Implemented by CYGPKG_ERROR_ERRNO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_ERRNO
+ # CYGINT_ISO_ERRNO == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_ERRNO
+ # Requires: 1 >= CYGINT_ISO_ERRNO
+};
+
+# errno variable implementation header
+#
+cdl_option CYGBLD_ISO_ERRNO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/error/errno.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # component CYGPKG_ERROR_ERRNO
+ # Requires: CYGBLD_ISO_ERRNO_HEADER == "<cyg/error/errno.h>"
+};
+
+# <
+# Locale-related functions
+#
+cdl_component CYGPKG_ISO_LOCALE {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of locale functions
+#
+cdl_interface CYGINT_ISO_LOCALE {
+ # Implemented by CYGPKG_LIBC_I18N, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_LOCALE
+ # CYGINT_ISO_LOCALE == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_LOCALE
+ # Requires: 1 >= CYGINT_ISO_LOCALE
+};
+
+# Locale implementation header
+#
+cdl_option CYGBLD_ISO_LOCALE_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Standard I/O-related functionality
+#
+cdl_component CYGPKG_ISO_STDIO {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of stdio file types
+#
+cdl_interface CYGINT_ISO_STDIO_FILETYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILETYPES
+ # CYGINT_ISO_STDIO_FILETYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_FILETYPES
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILETYPES
+};
+
+# Stdio file types implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_FILETYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Stdio standard streams implementations
+#
+cdl_interface CYGINT_ISO_STDIO_STREAMS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_STREAMS
+ # CYGINT_ISO_STDIO_STREAMS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_STREAMS
+ # Requires: 1 >= CYGINT_ISO_STDIO_STREAMS
+};
+
+# Stdio standard streams implementation header
+# This header file must define stdin, stdout
+# and stderr.
+#
+cdl_option CYGBLD_ISO_STDIO_STREAMS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio file operations
+#
+cdl_interface CYGINT_ISO_STDIO_FILEOPS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEOPS
+ # CYGINT_ISO_STDIO_FILEOPS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_FILEOPS
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEOPS
+};
+
+# Stdio file operations implementation header
+# This header controls the file system operations on a file
+# such as remove(), rename(), tmpfile(), tmpnam() and associated
+# constants.
+#
+cdl_option CYGBLD_ISO_STDIO_FILEOPS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio file access functionals
+#
+cdl_interface CYGINT_ISO_STDIO_FILEACCESS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEACCESS
+ # CYGINT_ISO_STDIO_FILEACCESS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_FILEACCESS
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEACCESS
+ # option CYGFUN_COMPRESS_ZLIB_GZIO
+ # Requires: CYGINT_ISO_STDIO_FILEACCESS
+};
+
+# Stdio file access implementation header
+# This header controls the file access operations
+# such as fclose(), fflush(), fopen(), freopen(), setbuf(),
+# setvbuf(), and associated constants.
+#
+cdl_option CYGBLD_ISO_STDIO_FILEACCESS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio formatted I/O
+#
+cdl_interface CYGINT_ISO_STDIO_FORMATTED_IO {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_FORMATTED_IO
+ # CYGINT_ISO_STDIO_FORMATTED_IO == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_FORMATTED_IO
+ # Requires: 1 >= CYGINT_ISO_STDIO_FORMATTED_IO
+ # option CYGFUN_COMPRESS_ZLIB_GZIO
+ # Requires: CYGINT_ISO_STDIO_FORMATTED_IO
+};
+
+# Stdio formatted I/O implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_FORMATTED_IO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio character I/O
+#
+cdl_interface CYGINT_ISO_STDIO_CHAR_IO {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_CHAR_IO
+ # CYGINT_ISO_STDIO_CHAR_IO == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_CHAR_IO
+ # Requires: 1 >= CYGINT_ISO_STDIO_CHAR_IO
+};
+
+# Stdio character I/O implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_CHAR_IO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio direct I/O
+#
+cdl_interface CYGINT_ISO_STDIO_DIRECT_IO {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_DIRECT_IO
+ # CYGINT_ISO_STDIO_DIRECT_IO == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_DIRECT_IO
+ # Requires: 1 >= CYGINT_ISO_STDIO_DIRECT_IO
+};
+
+# Stdio direct I/O implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_DIRECT_IO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio file positioning
+#
+cdl_interface CYGINT_ISO_STDIO_FILEPOS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEPOS
+ # CYGINT_ISO_STDIO_FILEPOS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_FILEPOS
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEPOS
+ # option CYGFUN_COMPRESS_ZLIB_GZIO
+ # Requires: CYGINT_ISO_STDIO_FILEPOS
+};
+
+# Stdio file positioning implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_FILEPOS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio error handling
+#
+cdl_interface CYGINT_ISO_STDIO_ERROR {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_ERROR
+ # CYGINT_ISO_STDIO_ERROR == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_ERROR
+ # Requires: 1 >= CYGINT_ISO_STDIO_ERROR
+};
+
+# Stdio error handling implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_ERROR_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX fd-related function implementations
+#
+cdl_interface CYGINT_ISO_STDIO_POSIX_FDFUNCS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_POSIX_FDFUNCS
+ # CYGINT_ISO_STDIO_POSIX_FDFUNCS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_POSIX_FDFUNCS
+ # Requires: 1 >= CYGINT_ISO_STDIO_POSIX_FDFUNCS
+};
+
+# POSIX fd-related function implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_POSIX_FDFUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Standard general utility functions
+#
+cdl_component CYGPKG_ISO_STDLIB {
+ # There is no associated value.
+};
+
+# >
+# String conversion function implementations
+#
+cdl_interface CYGINT_ISO_STDLIB_STRCONV {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_STRCONV
+ # CYGINT_ISO_STDLIB_STRCONV == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDLIB_STRCONV
+ # Requires: 1 >= CYGINT_ISO_STDLIB_STRCONV
+};
+
+# String conversion function implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_STRCONV_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/stdlib/atox.inl>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGIMP_LIBC_STDLIB_INLINE_ATOX
+ # Requires: CYGBLD_ISO_STDLIB_STRCONV_HEADER == "<cyg/libc/stdlib/atox.inl>"
+};
+
+# String to FP conversion function implementations
+#
+cdl_interface CYGINT_ISO_STDLIB_STRCONV_FLOAT {
+ # Implemented by CYGFUN_LIBC_strtod, active, disabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_STDLIB_STRCONV_FLOAT
+ # CYGINT_ISO_STDLIB_STRCONV_FLOAT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDLIB_STRCONV_FLOAT
+ # Requires: 1 >= CYGINT_ISO_STDLIB_STRCONV_FLOAT
+};
+
+# String to FP conversion function implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_STRCONV_FLOAT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Random number generator implementations
+#
+cdl_interface CYGINT_ISO_RAND {
+ # Implemented by CYGIMP_LIBC_RAND_SIMPLEST, active, disabled
+ # Implemented by CYGIMP_LIBC_RAND_SIMPLE1, active, disabled
+ # Implemented by CYGIMP_LIBC_RAND_KNUTH1, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_RAND
+ # CYGINT_ISO_RAND == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_RAND
+ # Requires: 1 >= CYGINT_ISO_RAND
+};
+
+# Random number generator implementation header
+#
+cdl_option CYGBLD_ISO_RAND_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Malloc implementations
+#
+cdl_interface CYGINT_ISO_MALLOC {
+ # Implemented by CYGPKG_MEMALLOC_MALLOC_ALLOCATORS, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_MALLOC
+ # CYGINT_ISO_MALLOC == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_MALLOC
+ # Requires: 1 >= CYGINT_ISO_MALLOC
+ # option CYGFUN_LIBC_STRING_STRDUP
+ # ActiveIf: CYGINT_ISO_MALLOC
+};
+
+# Malloc implementation header
+#
+cdl_option CYGBLD_ISO_MALLOC_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Mallinfo() implementations
+#
+cdl_interface CYGINT_ISO_MALLINFO {
+ # Implemented by CYGPKG_MEMALLOC_MALLOC_ALLOCATORS, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_MALLINFO
+ # CYGINT_ISO_MALLINFO == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_MALLINFO
+ # Requires: 1 >= CYGINT_ISO_MALLINFO
+};
+
+# Mallinfo() implementation header
+#
+cdl_option CYGBLD_ISO_MALLINFO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Program exit functionality implementations
+#
+cdl_interface CYGINT_ISO_EXIT {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_EXIT
+ # CYGINT_ISO_EXIT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_EXIT
+ # Requires: 1 >= CYGINT_ISO_EXIT
+ # option CYGFUN_INFRA_DUMMY_ABORT
+ # Requires: !CYGINT_ISO_EXIT
+ # option CYGFUN_INFRA_DUMMY_ABORT
+ # DefaultValue: CYGINT_ISO_EXIT == 0
+};
+
+# Program exit functionality implementation header
+#
+cdl_option CYGBLD_ISO_EXIT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Program environment implementations
+#
+cdl_interface CYGINT_ISO_STDLIB_ENVIRON {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_ENVIRON
+ # CYGINT_ISO_STDLIB_ENVIRON == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDLIB_ENVIRON
+ # Requires: 1 >= CYGINT_ISO_STDLIB_ENVIRON
+};
+
+# Program environment implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_ENVIRON_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# system() implementations
+#
+cdl_interface CYGINT_ISO_STDLIB_SYSTEM {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_SYSTEM
+ # CYGINT_ISO_STDLIB_SYSTEM == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDLIB_SYSTEM
+ # Requires: 1 >= CYGINT_ISO_STDLIB_SYSTEM
+};
+
+# system() implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_SYSTEM_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# bsearch() implementations
+#
+cdl_interface CYGINT_ISO_BSEARCH {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_BSEARCH
+ # CYGINT_ISO_BSEARCH == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_BSEARCH
+ # Requires: 1 >= CYGINT_ISO_BSEARCH
+};
+
+# bsearch() implementation header
+#
+cdl_option CYGBLD_ISO_BSEARCH_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# qsort() implementations
+#
+cdl_interface CYGINT_ISO_QSORT {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_QSORT
+ # CYGINT_ISO_STDLIB_QSORT (unknown) == 0
+ # --> 1
+
+ # The following properties are affected by this value
+};
+
+# qsort() implementation header
+#
+cdl_option CYGBLD_ISO_QSORT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# abs()/labs() implementations
+#
+cdl_interface CYGINT_ISO_ABS {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_ABS
+ # CYGINT_ISO_STDLIB_ABS (unknown) == 0
+ # --> 1
+
+ # The following properties are affected by this value
+};
+
+# abs()/labs() implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_ABS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/stdlib/abs.inl>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGIMP_LIBC_STDLIB_INLINE_ABS
+ # Requires: CYGBLD_ISO_STDLIB_ABS_HEADER == "<cyg/libc/stdlib/abs.inl>"
+};
+
+# div()/ldiv() implementations
+#
+cdl_interface CYGINT_ISO_DIV {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_DIV
+ # CYGINT_ISO_STDLIB_DIV (unknown) == 0
+ # --> 1
+
+ # The following properties are affected by this value
+};
+
+# div()/ldiv() implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_DIV_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/stdlib/div.inl>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGIMP_LIBC_STDLIB_INLINE_DIV
+ # Requires: CYGBLD_ISO_STDLIB_DIV_HEADER == "<cyg/libc/stdlib/div.inl>"
+};
+
+# Header defining the implementation's MB_CUR_MAX
+#
+cdl_option CYGBLD_ISO_STDLIB_MB_CUR_MAX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # interface CYGINT_LIBC_I18N_MB_REQUIRED
+ # Requires: CYGBLD_ISO_STDLIB_MB_CUR_MAX_HEADER == "<cyg/libc/i18n/mb.h>"
+};
+
+# Multibyte character implementations
+#
+cdl_interface CYGINT_ISO_STDLIB_MULTIBYTE {
+ # Implemented by CYGPKG_LIBC_I18N, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_MULTIBYTE
+ # CYGINT_ISO_STDLIB_MULTIBYTE == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDLIB_MULTIBYTE
+ # Requires: 1 >= CYGINT_ISO_STDLIB_MULTIBYTE
+};
+
+# Multibyte character implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_MULTIBYTE_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# String functions
+#
+cdl_component CYGPKG_ISO_STRING {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of strerror() function
+#
+cdl_interface CYGINT_ISO_STRERROR {
+ # Implemented by CYGPKG_ERROR_STRERROR, active, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 1
+ # Requires: 1 >= CYGINT_ISO_STRERROR
+ # CYGINT_ISO_STRERROR == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRERROR
+ # Requires: 1 >= CYGINT_ISO_STRERROR
+};
+
+# strerror() implementation header
+#
+cdl_option CYGBLD_ISO_STRERROR_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/error/strerror.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGPKG_ERROR_STRERROR
+ # Requires: CYGBLD_ISO_STRERROR_HEADER == "<cyg/error/strerror.h>"
+};
+
+# memcpy() implementation header
+#
+cdl_option CYGBLD_ISO_MEMCPY_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# memset() implementation header
+#
+cdl_option CYGBLD_ISO_MEMSET_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of strtok_r() function
+#
+cdl_interface CYGINT_ISO_STRTOK_R {
+ # Implemented by CYGPKG_LIBC_STRING, active, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 1
+ # Requires: 1 >= CYGINT_ISO_STRTOK_R
+ # CYGINT_ISO_STRTOK_R == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRTOK_R
+ # Requires: 1 >= CYGINT_ISO_STRTOK_R
+};
+
+# strtok_r() implementation header
+#
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/string/string.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # package CYGPKG_LIBC_STRING
+ # Requires: CYGBLD_ISO_STRTOK_R_HEADER == "<cyg/libc/string/string.h>"
+};
+
+# Number of implementations of locale-specific string functions
+# This covers locale-dependent string functions such as strcoll()
+# and strxfrm().
+#
+cdl_interface CYGINT_ISO_STRING_LOCALE_FUNCS {
+ # Implemented by CYGPKG_LIBC_STRING, active, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 1
+ # Requires: 1 >= CYGINT_ISO_STRING_LOCALE_FUNCS
+ # CYGINT_ISO_STRING_LOCALE_FUNCS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRING_LOCALE_FUNCS
+ # Requires: 1 >= CYGINT_ISO_STRING_LOCALE_FUNCS
+};
+
+# Locale-specific string functions' implementation header
+# This covers locale-dependent string functions such as strcoll()
+# and strxfrm().
+#
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/string/string.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # package CYGPKG_LIBC_STRING
+ # Requires: CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER == "<cyg/libc/string/string.h>"
+};
+
+# Number of implementations of BSD string functions
+#
+cdl_interface CYGINT_ISO_STRING_BSD_FUNCS {
+ # Implemented by CYGFUN_LIBC_STRING_BSD_FUNCS, active, disabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STRING_BSD_FUNCS
+ # CYGINT_ISO_STRING_BSD_FUNCS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRING_BSD_FUNCS
+ # Requires: 1 >= CYGINT_ISO_STRING_BSD_FUNCS
+};
+
+# BSD string functions' implementation header
+#
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGFUN_LIBC_STRING_BSD_FUNCS
+ # Requires: CYGBLD_ISO_STRING_BSD_FUNCS_HEADER == "<cyg/libc/string/bsdstring.h>"
+};
+
+# Number of implementations of other mem*() functions
+#
+cdl_interface CYGINT_ISO_STRING_MEMFUNCS {
+ # Implemented by CYGPKG_LIBC_STRING, active, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 1
+ # Requires: 1 >= CYGINT_ISO_STRING_MEMFUNCS
+ # CYGINT_ISO_STRING_MEMFUNCS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRING_MEMFUNCS
+ # Requires: 1 >= CYGINT_ISO_STRING_MEMFUNCS
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGINT_ISO_STRING_MEMFUNCS
+ # component CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
+ # Requires: CYGINT_ISO_STRING_MEMFUNCS
+};
+
+# Other mem*() functions' implementation header
+#
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/string/string.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # package CYGPKG_LIBC_STRING
+ # Requires: CYGBLD_ISO_STRING_MEMFUNCS_HEADER == "<cyg/libc/string/string.h>"
+};
+
+# Number of implementations of other ISO C str*() functions
+# This covers the other str*() functions defined by ISO C.
+#
+cdl_interface CYGINT_ISO_STRING_STRFUNCS {
+ # Implemented by CYGPKG_LIBC_STRING, active, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 1
+ # Requires: 1 >= CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRING_STRFUNCS
+ # Requires: 1 >= CYGINT_ISO_STRING_STRFUNCS
+ # option CYGFUN_INFRA_DUMMY_STRLEN
+ # Requires: !CYGINT_ISO_STRING_STRFUNCS
+ # option CYGFUN_INFRA_DUMMY_STRLEN
+ # DefaultValue: CYGINT_ISO_STRING_STRFUNCS == 0
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # component CYGPKG_IO_ETH_DRIVERS_NET
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # option CYGFUN_COMPRESS_ZLIB_GZIO
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # package CYGPKG_IO_FLASH
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # package CYGPKG_LIBC_STDLIB
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+};
+
+# Other ISO C str*() functions' implementation header
+# This covers the other str*() functions defined by ISO C.
+#
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/string/string.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # package CYGPKG_LIBC_STRING
+ # Requires: CYGBLD_ISO_STRING_STRFUNCS_HEADER == "<cyg/libc/string/string.h>"
+};
+
+# <
+# Clock and time functionality
+#
+cdl_component CYGPKG_ISO_TIME {
+ # There is no associated value.
+};
+
+# >
+# time_t implementation header
+#
+cdl_option CYGBLD_ISO_TIME_T_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# clock_t implementation header
+#
+cdl_option CYGBLD_ISO_CLOCK_T_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# struct timeval implementation header
+#
+cdl_option CYGBLD_ISO_STRUCTTIMEVAL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# fnmatch implementation header
+#
+cdl_option CYGBLD_ISO_FNMATCH_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of POSIX timer types
+#
+cdl_interface CYGINT_ISO_POSIX_TIMER_TYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMER_TYPES
+ # CYGINT_ISO_POSIX_TIMER_TYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_TIMER_TYPES
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMER_TYPES
+};
+
+# POSIX timer types implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_TIMER_TYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of POSIX clock types
+#
+cdl_interface CYGINT_ISO_POSIX_CLOCK_TYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_CLOCK_TYPES
+ # CYGINT_ISO_POSIX_CLOCK_TYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_CLOCK_TYPES
+ # Requires: 1 >= CYGINT_ISO_POSIX_CLOCK_TYPES
+};
+
+# POSIX clock types implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_CLOCK_TYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of ISO C types
+#
+cdl_interface CYGINT_ISO_C_TIME_TYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_C_TIME_TYPES
+ # CYGINT_ISO_C_TIME_TYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_C_TIME_TYPES
+ # Requires: 1 >= CYGINT_ISO_C_TIME_TYPES
+};
+
+# ISO C time types implementation header
+#
+cdl_option CYGBLD_ISO_C_TIME_TYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of POSIX timers
+#
+cdl_interface CYGINT_ISO_POSIX_TIMERS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMERS
+ # CYGINT_ISO_POSIX_TIMERS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_TIMERS
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMERS
+};
+
+# POSIX timer implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_TIMERS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of POSIX clocks
+#
+cdl_interface CYGINT_ISO_POSIX_CLOCKS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_CLOCKS
+ # CYGINT_ISO_POSIX_CLOCKS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_CLOCKS
+ # Requires: 1 >= CYGINT_ISO_POSIX_CLOCKS
+};
+
+# POSIX clocks implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_CLOCKS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of ISO C clock functions
+#
+cdl_interface CYGINT_ISO_C_CLOCK_FUNCS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_C_CLOCK_FUNCS
+ # CYGINT_ISO_C_CLOCK_FUNCS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_C_CLOCK_FUNCS
+ # Requires: 1 >= CYGINT_ISO_C_CLOCK_FUNCS
+};
+
+# ISO C clock functions' implementation header
+#
+cdl_option CYGBLD_ISO_C_CLOCK_FUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of tzset() function
+#
+cdl_interface CYGINT_ISO_TZSET {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_TZSET
+ # CYGINT_ISO_TZSET == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_TZSET
+ # Requires: 1 >= CYGINT_ISO_TZSET
+};
+
+# tzset() implementation header
+#
+cdl_option CYGBLD_ISO_TZSET_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Signal functionality
+#
+cdl_component CYGPKG_ISO_SIGNAL {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of signal numbers
+#
+cdl_interface CYGINT_ISO_SIGNAL_NUMBERS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SIGNAL_NUMBERS
+ # CYGINT_ISO_SIGNAL_NUMBERS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SIGNAL_NUMBERS
+ # Requires: 1 >= CYGINT_ISO_SIGNAL_NUMBERS
+};
+
+# Signal numbering implementation header
+# This header provides the mapping of signal
+# names (e.g. SIGBUS) to numbers.
+#
+cdl_option CYGBLD_ISO_SIGNAL_NUMBERS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of signal implementations
+#
+cdl_interface CYGINT_ISO_SIGNAL_IMPL {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SIGNAL_IMPL
+ # CYGINT_ISO_SIGNAL_IMPL == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SIGNAL_IMPL
+ # Requires: 1 >= CYGINT_ISO_SIGNAL_IMPL
+};
+
+# Signals implementation header
+#
+cdl_option CYGBLD_ISO_SIGNAL_IMPL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX real time signals feature test macro
+# This defines the POSIX feature test macro
+# that indicates that the POSIX real time signals
+# are present.
+#
+cdl_interface CYGINT_POSIX_REALTIME_SIGNALS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_POSIX_REALTIME_SIGNALS
+ # CYGINT_POSIX_REALTIME_SIGNALS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_POSIX_REALTIME_SIGNALS
+ # Requires: 1 >= CYGINT_POSIX_REALTIME_SIGNALS
+};
+
+# <
+# Non-local jumps functionality
+#
+cdl_component CYGPKG_ISO_SETJMP {
+ # There is no associated value.
+};
+
+# >
+# setjmp() / longjmp() implementations
+#
+cdl_interface CYGINT_ISO_SETJMP {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SETJMP
+ # CYGINT_ISO_SETJMP == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SETJMP
+ # Requires: 1 >= CYGINT_ISO_SETJMP
+};
+
+# setjmp() / longjmp() implementation header
+#
+cdl_option CYGBLD_ISO_SETJMP_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# sigsetjmp() / siglongjmp() implementations
+#
+cdl_interface CYGINT_ISO_SIGSETJMP {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SIGSETJMP
+ # CYGINT_ISO_SIGSETJMP == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SIGSETJMP
+ # Requires: 1 >= CYGINT_ISO_SIGSETJMP
+};
+
+# sigsetjmp() / siglongjmp() implementation header
+#
+cdl_option CYGBLD_ISO_SIGSETJMP_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Assertions implementation header
+#
+cdl_option CYGBLD_ISO_ASSERT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX file control
+# This covers the POSIX file control definitions,
+# normally found in <fcntl.h>
+#
+cdl_component CYGPKG_ISO_POSIX_FCNTL {
+ # There is no associated value.
+};
+
+# >
+# POSIX open flags implementation header
+#
+cdl_option CYGBLD_ISO_OFLAG_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX fcntl() implementations
+#
+cdl_interface CYGINT_ISO_FCNTL {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_FCNTL
+ # CYGINT_ISO_FCNTL == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_FCNTL
+ # Requires: 1 >= CYGINT_ISO_FCNTL
+};
+
+# POSIX fcntl() implementation header
+#
+cdl_option CYGBLD_ISO_FCNTL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX file open implementations
+#
+cdl_interface CYGINT_ISO_OPEN {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_OPEN
+ # CYGINT_ISO_OPEN == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_OPEN
+ # Requires: 1 >= CYGINT_ISO_OPEN
+};
+
+# POSIX file open implementation header
+#
+cdl_option CYGBLD_ISO_OPEN_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# <sys/stat.h> definitions implementation header
+#
+cdl_option CYGBLD_ISO_STAT_DEFS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX directory reading implementation
+#
+cdl_interface CYGINT_ISO_DIRENT {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_DIRENT
+ # CYGINT_ISO_DIRENT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_DIRENT
+ # Requires: 1 >= CYGINT_ISO_DIRENT
+};
+
+# <dirent.h> definitions implementation header
+#
+cdl_option CYGBLD_ISO_DIRENT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX <sys/types.h> contents
+# This covers the types required by POSIX to be in
+# <sys/types.h>
+#
+cdl_component CYGPKG_ISO_POSIX_TYPES {
+ # There is no associated value.
+};
+
+# >
+# POSIX thread types implementations
+#
+cdl_interface CYGINT_ISO_PTHREADTYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_PTHREADTYPES
+ # CYGINT_ISO_PTHREADTYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_PTHREADTYPES
+ # Requires: 1 >= CYGINT_ISO_PTHREADTYPES
+ # interface CYGINT_ISO_PMUTEXTYPES
+ # Requires: 1 >= CYGINT_ISO_PTHREADTYPES
+};
+
+# POSIX thread types implementation header
+#
+cdl_option CYGBLD_ISO_PTHREADTYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX mutex types implementations
+#
+cdl_interface CYGINT_ISO_PMUTEXTYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_PTHREADTYPES
+ # CYGINT_ISO_PTHREADTYPES == 0
+ # --> 1
+};
+
+# POSIX mutex types implementation header
+#
+cdl_option CYGBLD_ISO_PMUTEXTYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# ssize_t implementation header
+#
+cdl_option CYGBLD_ISO_SSIZE_T_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Filesystem types implementation header
+#
+cdl_option CYGBLD_ISO_FSTYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# gid_t, pid_t, uid_t implementation header
+#
+cdl_option CYGBLD_ISO_SCHEDTYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Non-POSIX <sys/types.h> contents
+# This covers the extra types required by non-POSIX
+# packages to be in <sys/types.h>. These would normally
+# only be visible if _POSIX_SOURCE is not defined.
+#
+cdl_component CYGPKG_ISO_EXTRA_TYPES {
+ # There is no associated value.
+};
+
+# >
+# BSD compatible types
+#
+cdl_interface CYGINT_ISO_BSDTYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_BSDTYPES
+ # CYGINT_ISO_BSDTYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_BSDTYPES
+ # Requires: 1 >= CYGINT_ISO_BSDTYPES
+};
+
+# BSD types header
+#
+cdl_option CYGBLD_ISO_BSDTYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Utsname structure
+#
+cdl_component CYGPKG_ISO_UTSNAME {
+ # There is no associated value.
+};
+
+# >
+# Utsname header
+#
+cdl_option CYGBLD_ISO_UTSNAME_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# POSIX scheduler
+#
+cdl_component CYGPKG_ISO_SCHED {
+ # There is no associated value.
+};
+
+# >
+# POSIX scheduler implementations
+#
+cdl_interface CYGINT_ISO_SCHED_IMPL {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SCHED_IMPL
+ # CYGINT_ISO_SCHED_IMPL == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SCHED_IMPL
+ # Requires: 1 >= CYGINT_ISO_SCHED_IMPL
+};
+
+# POSIX scheduler implementation header
+#
+cdl_option CYGBLD_ISO_SCHED_IMPL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# POSIX semaphores
+#
+cdl_component CYGPKG_ISO_SEMAPHORES {
+ # There is no associated value.
+};
+
+# >
+# POSIX semaphore implementations
+#
+cdl_interface CYGINT_ISO_SEMAPHORES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SEMAPHORES
+ # CYGINT_ISO_SEMAPHORES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SEMAPHORES
+ # Requires: 1 >= CYGINT_ISO_SEMAPHORES
+};
+
+# POSIX semaphore implementation header
+#
+cdl_option CYGBLD_ISO_SEMAPHORES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# POSIX message queues
+#
+cdl_component CYGPKG_ISO_MQUEUE {
+ # There is no associated value.
+};
+
+# >
+# Implementations
+#
+cdl_interface CYGINT_ISO_MQUEUE {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_MQUEUE
+ # CYGINT_ISO_MQUEUE == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_MQUEUE
+ # Requires: 1 >= CYGINT_ISO_MQUEUE
+ # option CYGNUM_ISO_MQUEUE_OPEN_MAX
+ # ActiveIf: CYGINT_ISO_MQUEUE
+ # option CYGNUM_ISO_MQUEUE_PRIO_MAX
+ # ActiveIf: CYGINT_ISO_MQUEUE
+};
+
+# Implementation header
+#
+cdl_option CYGBLD_ISO_MQUEUE_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Maximum number of open message queues
+#
+cdl_option CYGNUM_ISO_MQUEUE_OPEN_MAX {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_ISO_MQUEUE
+ # CYGINT_ISO_MQUEUE == 0
+ # --> 0
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYGNUM_POSIX_MQUEUE_OPEN_MAX > 0 ? CYGNUM_POSIX_MQUEUE_OPEN_MAX : 0
+ # CYGNUM_POSIX_MQUEUE_OPEN_MAX (unknown) == 0
+ # CYGNUM_POSIX_MQUEUE_OPEN_MAX (unknown) == 0
+ # --> 0 0
+};
+
+# Maximum number of message priorities
+#
+cdl_option CYGNUM_ISO_MQUEUE_PRIO_MAX {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_ISO_MQUEUE
+ # CYGINT_ISO_MQUEUE == 0
+ # --> 0
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 1 65535
+ # value_source default
+ # Default value: 1 65535
+};
+
+# <
+# POSIX threads
+#
+cdl_component CYGPKG_ISO_PTHREAD {
+ # There is no associated value.
+};
+
+# >
+# POSIX pthread implementations
+#
+cdl_interface CYGINT_ISO_PTHREAD_IMPL {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_PTHREAD_IMPL
+ # CYGINT_ISO_PTHREAD_IMPL == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_PTHREAD_IMPL
+ # Requires: 1 >= CYGINT_ISO_PTHREAD_IMPL
+};
+
+# POSIX pthread implementation header
+#
+cdl_option CYGBLD_ISO_PTHREAD_IMPL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX mutex/cond var implementations
+#
+cdl_interface CYGINT_ISO_PTHREAD_MUTEX {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_PTHREAD_MUTEX
+ # CYGINT_ISO_PTHREAD_MUTEX == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_PTHREAD_MUTEX
+ # Requires: 1 >= CYGINT_ISO_PTHREAD_MUTEX
+};
+
+# POSIX mutex/cond var implementation header
+#
+cdl_option CYGBLD_ISO_PTHREAD_MUTEX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Limits
+#
+cdl_component CYGPKG_ISO_LIMITS {
+ # There is no associated value.
+};
+
+# >
+# POSIX pthread limits implementations
+#
+cdl_interface CYGINT_ISO_POSIX_LIMITS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_LIMITS
+ # CYGINT_ISO_POSIX_LIMITS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_LIMITS
+ # Requires: 1 >= CYGINT_ISO_POSIX_LIMITS
+};
+
+# POSIX pthread limits implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_LIMITS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# OPEN_MAX implementation header
+#
+cdl_option CYGBLD_ISO_OPEN_MAX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# LINK_MAX implementation header
+#
+cdl_option CYGBLD_ISO_LINK_MAX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# NAME_MAX implementation header
+#
+cdl_option CYGBLD_ISO_NAME_MAX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# PATH_MAX implementation header
+#
+cdl_option CYGBLD_ISO_PATH_MAX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# POSIX termios
+#
+cdl_component CYGPKG_ISO_TERMIOS {
+ # There is no associated value.
+};
+
+# >
+# POSIX termios implementations
+#
+cdl_interface CYGINT_ISO_TERMIOS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_TERMIOS
+ # CYGINT_ISO_TERMIOS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_TERMIOS
+ # Requires: 1 >= CYGINT_ISO_TERMIOS
+};
+
+# POSIX termios implementation header
+#
+cdl_option CYGBLD_ISO_TERMIOS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Dynamic load API
+#
+cdl_component CYGPKG_ISO_DLFCN {
+ # There is no associated value.
+};
+
+# >
+# Dynamic load implementations
+#
+cdl_interface CYGINT_ISO_DLFCN {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_DLFCN
+ # CYGINT_ISO_DLFCN == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_DLFCN
+ # Requires: 1 >= CYGINT_ISO_DLFCN
+};
+
+# Dynamic load implementation header
+#
+cdl_option CYGBLD_ISO_DLFCN_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# UNIX standard functions
+#
+cdl_component CYGPKG_ISO_UNISTD {
+ # There is no associated value.
+};
+
+# >
+# POSIX timer operations implementations
+#
+cdl_interface CYGINT_ISO_POSIX_TIMER_OPS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMER_OPS
+ # CYGINT_ISO_POSIX_TIMER_OPS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_TIMER_OPS
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMER_OPS
+};
+
+# POSIX timer operations implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_TIMER_OPS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX sleep() implementations
+#
+cdl_interface CYGINT_ISO_POSIX_SLEEP {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_SLEEP
+ # CYGINT_ISO_POSIX_SLEEP == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_SLEEP
+ # Requires: 1 >= CYGINT_ISO_POSIX_SLEEP
+};
+
+# POSIX sleep() implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_SLEEP_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# select()/poll() functions
+#
+cdl_component CYGPKG_ISO_SELECT {
+ # There is no associated value.
+};
+
+# >
+# select() implementations
+#
+cdl_interface CYGINT_ISO_SELECT {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_SELECT
+ # CYGINT_ISO_SELECT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SELECT
+ # Requires: 1 >= CYGINT_ISO_SELECT
+};
+
+# select() implementation header
+#
+cdl_option CYGBLD_ISO_SELECT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# poll() implementations
+#
+cdl_interface CYGINT_ISO_POLL {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POLL
+ # CYGINT_ISO_POLL == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POLL
+ # Requires: 1 >= CYGINT_ISO_POLL
+};
+
+# poll() implementation header
+#
+cdl_option CYGBLD_ISO_POLL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# NetDB utility functions
+#
+cdl_component CYGPKG_ISO_NETDB {
+ # There is no associated value.
+};
+
+# >
+# DNS implementations
+#
+cdl_interface CYGINT_ISO_DNS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: bool
+ # Current value: 0
+ # Requires: 1 >= CYGINT_ISO_DNS
+ # CYGINT_ISO_DNS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_DNS
+ # Requires: 1 >= CYGINT_ISO_DNS
+};
+
+# DNS implementation header
+#
+cdl_option CYGBLD_ISO_DNS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Protocol network database implementations
+#
+cdl_interface CYGINT_ISO_NETDB_PROTO {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: bool
+ # Current value: 0
+ # Requires: 1 >= CYGINT_ISO_NETDB_PROTO
+ # CYGINT_ISO_NETDB_PROTO == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_NETDB_PROTO
+ # Requires: 1 >= CYGINT_ISO_NETDB_PROTO
+};
+
+# Protocol network database implementation header
+#
+cdl_option CYGBLD_ISO_NETDB_PROTO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Services network database implementations
+#
+cdl_interface CYGINT_ISO_NETDB_SERV {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: bool
+ # Current value: 0
+ # Requires: 1 >= CYGINT_ISO_NETDB_SERV
+ # CYGINT_ISO_NETDB_SERV == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_NETDB_SERV
+ # Requires: 1 >= CYGINT_ISO_NETDB_SERV
+};
+
+# Services network database implementation header
+#
+cdl_option CYGBLD_ISO_NETDB_SERV_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_ISOINFRA_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the ISO C and POSIX infrastructure package.
+# These flags are used in addition to the set of global flags.
+#
+cdl_option CYGPKG_ISOINFRA_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the ISO C and POSIX infrastructure package.
+# These flags are removed from the set of global flags
+# if present.
+#
+cdl_option CYGPKG_ISOINFRA_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# <
+# <
+# Compute CRCs
+# doc: ref/services-crc.html
+# This package provides support for CRC calculation. Currently
+# this is the POSIX 1003 defined CRC algorithm, a 32 CRC by
+# Gary S. Brown, and a 16 bit CRC.
+#
+cdl_package CYGPKG_CRC {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # package CYGPKG_COMPRESS_ZLIB
+ # Requires: CYGPKG_CRC
+};
+
+# >
+# POSIX CRC tests
+#
+cdl_option CYGPKG_CRC_TESTS {
+ # Calculated value: "tests/crc_test"
+ # Flavor: data
+ # Current_value: tests/crc_test
+};
+
+# <
+# Zlib compress and decompress package
+# This package provides support for compression and
+# decompression.
+#
+cdl_package CYGPKG_COMPRESS_ZLIB {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+ # Requires: CYGPKG_CRC
+ # CYGPKG_CRC == current
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGBLD_BUILD_REDBOOT_WITH_ZLIB
+ # ActiveIf: CYGPKG_COMPRESS_ZLIB
+};
+
+# >
+# Override memory allocation routines.
+#
+cdl_interface CYGINT_COMPRESS_ZLIB_LOCAL_ALLOC {
+ # Implemented by CYGBLD_BUILD_REDBOOT_WITH_ZLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_COMPRESS_ZLIB_NEEDS_MALLOC
+ # ActiveIf: CYGINT_COMPRESS_ZLIB_LOCAL_ALLOC == 0
+};
+
+# Should deflate() produce 'gzip' compatible output?
+# If this option is set then the output of calling deflate()
+# will be wrapped up as a 'gzip' compatible file.
+#
+cdl_option CYGSEM_COMPRESS_ZLIB_DEFLATE_MAKES_GZIP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Does this library need malloc?
+# This pseudo-option will force the memalloc library to be
+# required iff the application does not provide it's own
+# infrastructure.
+#
+cdl_option CYGSEM_COMPRESS_ZLIB_NEEDS_MALLOC {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_COMPRESS_ZLIB_LOCAL_ALLOC == 0
+ # CYGINT_COMPRESS_ZLIB_LOCAL_ALLOC == 1
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGPKG_MEMALLOC
+ # CYGPKG_MEMALLOC == current
+ # --> 1
+};
+
+# Include stdio-like utility functions
+# This option enables the stdio-like zlib utility functions
+# (gzread/gzwrite and friends) provided in gzio.c.
+#
+cdl_option CYGFUN_COMPRESS_ZLIB_GZIO {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGPKG_LIBC_STDIO_OPEN ? 1 : 0
+ # CYGPKG_LIBC_STDIO_OPEN (unknown) == 0
+ # --> 0
+ # Requires: CYGINT_ISO_STDIO_FILEPOS
+ # CYGINT_ISO_STDIO_FILEPOS == 0
+ # --> 0
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+ # Requires: CYGINT_ISO_STDIO_FORMATTED_IO
+ # CYGINT_ISO_STDIO_FORMATTED_IO == 0
+ # --> 0
+ # Requires: CYGINT_ISO_STDIO_FILEACCESS
+ # CYGINT_ISO_STDIO_FILEACCESS == 0
+ # --> 0
+};
+
+# Zlib compress and decompress package build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_COMPRESS_ZLIB_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_COMPRESS_ZLIB_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-D__ECOS__ -DNO_ERRNO_H"
+ # value_source default
+ # Default value: "-D__ECOS__ -DNO_ERRNO_H"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_COMPRESS_ZLIB_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wstrict-prototypes
+ # value_source default
+ # Default value: -Wstrict-prototypes
+};
+
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_COMPRESS_ZLIB_LDFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_COMPRESS_ZLIB_LDFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# <
+# zlib tests
+#
+cdl_option CYGPKG_COMPRESS_ZLIB_TESTS {
+ # Calculated value: "tests/zlib1.c tests/zlib2.c"
+ # Flavor: data
+ # Current_value: tests/zlib1.c tests/zlib2.c
+};
+
+# <
+# FLASH device drivers
+# doc: ref/flash.html
+# This option enables drivers for basic I/O services on
+# flash devices.
+#
+cdl_package CYGPKG_IO_FLASH {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGSEM_REDBOOT_FLASH_CONFIG
+ # DefaultValue: CYGPKG_IO_FLASH != 0
+ # package CYGPKG_DEVS_FLASH_ONMXC
+ # ActiveIf: CYGPKG_IO_FLASH
+};
+
+# >
+# Hardware FLASH device drivers
+# This option enables the hardware device drivers
+# for the current platform.
+#
+cdl_interface CYGHWR_IO_FLASH_DEVICE {
+ # Implemented by CYGPKG_DEVS_FLASH_ONMXC, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # component CYGPKG_REDBOOT_FLASH
+ # ActiveIf: CYGHWR_IO_FLASH_DEVICE
+};
+
+# Hardware FLASH device drivers are not in RAM
+# Use of this interface is deprecated.
+# Drivers should make sure that the functions are
+# linked to RAM by putting them in .2ram sections.
+#
+cdl_interface CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: !CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM
+ # CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM
+ # Requires: !CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM
+};
+
+# Hardware can support block locking
+# This option will be enabled by devices which can support
+# locking (write-protection) of individual blocks.
+#
+cdl_interface CYGHWR_IO_FLASH_BLOCK_LOCKING {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_FLASH_LOCK_SPECIAL
+ # ActiveIf: CYGHWR_IO_FLASH_BLOCK_LOCKING != 0
+};
+
+# Hardware cannot support direct access to FLASH memory
+# This option will be asserted by devices which cannot support
+# direct access to the FLASH memory contents (e.g. EEPROM or NAND
+# devices). In these cases, the driver must provide an appropriate
+# hardware access function.
+#
+cdl_option CYGSEM_IO_FLASH_READ_INDIRECT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+ # Requires: !CYGSEM_IO_FLASH_VERIFY_PROGRAM
+ # CYGSEM_IO_FLASH_VERIFY_PROGRAM == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGPRI_REDBOOT_ZLIB_FLASH
+ # ActiveIf: (!CYGSEM_IO_FLASH_READ_INDIRECT) || CYGPRI_REDBOOT_ZLIB_FLASH_FORCE
+ # component CYGHWR_DEVS_FLASH_MMC
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # option CYGHWR_DEVS_FLASH_MMC_ESDHC
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # option CYGHWR_DEVS_FLASH_MMC_SD
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # option CYGHWR_DEVS_FLASH_MXC_NAND
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+};
+
+# Display status messages during flash operations
+# Selecting this option will cause the drivers to print status
+# messages as various flash operations are undertaken.
+#
+cdl_option CYGSEM_IO_FLASH_CHATTER {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Verify data programmed to flash
+# Selecting this option will cause verification of data
+# programmed to flash.
+#
+cdl_option CYGSEM_IO_FLASH_VERIFY_PROGRAM {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_IO_FLASH_READ_INDIRECT
+ # Requires: !CYGSEM_IO_FLASH_VERIFY_PROGRAM
+};
+
+# Platform has flash soft DIP switch write-protect
+# Selecting this option will cause the state of a hardware jumper or
+# dipswitch to be read by software to determine whether the flash is
+# write-protected or not.
+#
+cdl_option CYGSEM_IO_FLASH_SOFT_WRITE_PROTECT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Instantiate in I/O block device API
+# Provides a block device accessible using the standard I/O
+# API ( cyg_io_read() etc. )
+#
+cdl_component CYGPKG_IO_FLASH_BLOCK_DEVICE {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_IO
+ # CYGPKG_IO (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# >
+# Name of flash device 1 block device
+#
+cdl_component CYGDAT_IO_FLASH_BLOCK_DEVICE_NAME_1 {
+ # This option is not active
+ # The parent CYGPKG_IO_FLASH_BLOCK_DEVICE is not active
+ # The parent CYGPKG_IO_FLASH_BLOCK_DEVICE is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "\"/dev/flash1\""
+ # value_source default
+ # Default value: "\"/dev/flash1\""
+};
+
+# >
+#
+cdl_interface CYGINT_IO_FLASH_BLOCK_CFG_1 {
+ # Implemented by CYGNUM_IO_FLASH_BLOCK_CFG_STATIC_1, inactive, enabled
+ # Implemented by CYGNUM_IO_FLASH_BLOCK_CFG_FIS_1, inactive, disabled
+ # This option is not active
+ # The parent CYGDAT_IO_FLASH_BLOCK_DEVICE_NAME_1 is not active
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 == CYGINT_IO_FLASH_BLOCK_CFG_1
+ # CYGINT_IO_FLASH_BLOCK_CFG_1 == 0
+ # --> 0
+
+ # The following properties are affected by this value
+ # interface CYGINT_IO_FLASH_BLOCK_CFG_1
+ # Requires: 1 == CYGINT_IO_FLASH_BLOCK_CFG_1
+};
+
+# Static configuration
+# This configures the flash device 1 block device
+# with static base and length
+#
+cdl_component CYGNUM_IO_FLASH_BLOCK_CFG_STATIC_1 {
+ # This option is not active
+ # The parent CYGDAT_IO_FLASH_BLOCK_DEVICE_NAME_1 is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Start offset from flash base
+# This gives the offset from the base of flash which this
+# block device corresponds to.
+#
+cdl_option CYGNUM_IO_FLASH_BLOCK_OFFSET_1 {
+ # This option is not active
+ # The parent CYGNUM_IO_FLASH_BLOCK_CFG_STATIC_1 is not active
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00100000
+ # value_source default
+ # Default value: 0x00100000
+};
+
+# Length
+# This gives the length of the region of flash given over
+# to this block device.
+#
+cdl_option CYGNUM_IO_FLASH_BLOCK_LENGTH_1 {
+ # This option is not active
+ # The parent CYGNUM_IO_FLASH_BLOCK_CFG_STATIC_1 is not active
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00100000
+ # value_source default
+ # Default value: 0x00100000
+};
+
+# <
+# Configuration from FIS
+# This configures the flash device 1 block device
+# from Redboot FIS
+#
+cdl_component CYGNUM_IO_FLASH_BLOCK_CFG_FIS_1 {
+ # This option is not active
+ # The parent CYGDAT_IO_FLASH_BLOCK_DEVICE_NAME_1 is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# >
+# Name of FIS entry
+#
+cdl_component CYGDAT_IO_FLASH_BLOCK_FIS_NAME_1 {
+ # This option is not active
+ # The parent CYGNUM_IO_FLASH_BLOCK_CFG_FIS_1 is not active
+ # The parent CYGNUM_IO_FLASH_BLOCK_CFG_FIS_1 is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "\"jffs2\""
+ # value_source default
+ # Default value: "\"jffs2\""
+};
+
+# <
+# <
+# <
+# Flash device driver build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_IO_FLASH_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the flash device drivers. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_IO_FLASH_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the flash device drivers. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_IO_FLASH_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Flash device driver tests
+# This option specifies the set of tests for the flash device drivers.
+#
+cdl_component CYGPKG_IO_FLASH_TESTS {
+ # Calculated value: "tests/flash1"
+ # Flavor: data
+ # Current_value: tests/flash1
+};
+
+# >
+# Start offset from flash base
+# This gives the offset from the base of flash where tests
+# can be run. It is important to set this correctly, as an
+# incorrect value could allow the tests to write over critical
+# portions of the FLASH device and possibly render the target
+# board totally non-functional.
+#
+cdl_option CYGNUM_IO_FLASH_TEST_OFFSET {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00100000
+ # value_source default
+ # Default value: 0x00100000
+};
+
+# Length
+# This gives the length of the region of flash used for testing.
+#
+cdl_option CYGNUM_IO_FLASH_TEST_LENGTH {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00100000
+ # value_source default
+ # Default value: 0x00100000
+};
+
+# <
+# <
+# Support FLASH memory on Freescale MXC platforms
+#
+cdl_package CYGPKG_DEVS_FLASH_ONMXC {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # ActiveIf constraint: CYGPKG_IO_FLASH
+ # CYGPKG_IO_FLASH == current
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+};
+
+# >
+# MXC platform MMC card support
+# When this option is enabled, it indicates MMC card is
+# supported on the MXC platforms
+#
+cdl_component CYGHWR_DEVS_FLASH_MMC {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+};
+
+# >
+# MXC platform MMC card for newer SDHC controllers
+#
+cdl_option CYGHWR_DEVS_FLASH_MMC_ESDHC {
+ # This option is not active
+ # The parent CYGHWR_DEVS_FLASH_MMC is disabled
+ # ActiveIf constraint: CYGPKG_HAL_ARM_MX37_3STACK || CYGPKG_HAL_ARM_MX35_3STACK || CYGPKG_HAL_ARM_MX25_3STACK || CYGPKG_HAL_ARM_MX51
+ # CYGPKG_HAL_ARM_MX37_3STACK (unknown) == 0
+ # CYGPKG_HAL_ARM_MX35_3STACK (unknown) == 0
+ # CYGPKG_HAL_ARM_MX25_3STACK (unknown) == 0
+ # CYGPKG_HAL_ARM_MX51 (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # --> 1
+};
+
+# MXC platform MMC card for older MMC/SD controllers
+#
+cdl_option CYGHWR_DEVS_FLASH_MMC_SD {
+ # This option is not active
+ # The parent CYGHWR_DEVS_FLASH_MMC is disabled
+ # ActiveIf constraint: CYGPKG_HAL_ARM_MX31_3STACK || CYGPKG_HAL_ARM_MX31ADS
+ # CYGPKG_HAL_ARM_MX31_3STACK (unknown) == 0
+ # CYGPKG_HAL_ARM_MX31ADS (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # --> 1
+};
+
+# <
+# MXC platform NOR flash memory support
+# When this option is enabled, it indicates NOR flash is
+# supported on the MXC platforms
+#
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_DEVS_FLASH_IMX_SPI_NOR
+ # Requires: CYGHWR_DEVS_FLASH_MXC_NOR == 1
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+};
+
+# MXC platform NAND flash memory support
+# When this option is enabled, it indicates NAND flash is
+# supported on the MXC platforms
+#
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGPKG_DEVS_FLASH_NAND_BBT_IN_FLASH
+ # ActiveIf: CYGHWR_DEVS_FLASH_MXC_NAND
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+ # interface CYGHWR_DEVS_FLASH_MXC_NAND_RESET_WORKAROUND
+ # ActiveIf: CYGHWR_DEVS_FLASH_MXC_NAND
+};
+
+# i.MX platform SPI NOR flash memory support
+# When this option is enabled, it indicates SPI NOR flash is
+# supported on the i.MX platforms
+#
+cdl_option CYGHWR_DEVS_FLASH_IMX_SPI_NOR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGHWR_DEVS_FLASH_MXC_NOR == 1
+ # CYGHWR_DEVS_FLASH_MXC_NOR == 0
+ # --> 0
+};
+
+# MXC platform ATA support
+# When this option is enabled, it indicates ATA is
+# supported on the MXC platforms
+#
+cdl_option CYGHWR_DEVS_FLASH_MXC_ATA {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Use a flash based Bad Block Table
+#
+cdl_component CYGPKG_DEVS_FLASH_NAND_BBT_IN_FLASH {
+ # ActiveIf constraint: CYGHWR_DEVS_FLASH_MXC_NAND
+ # CYGHWR_DEVS_FLASH_MXC_NAND == 1
+ # --> 1
+
+ # There is no associated value.
+};
+
+# >
+# When this option is enabled, the driver will search for a flash
+# based bad block table
+#
+cdl_option CYGHWR_DEVS_FLASH_MXC_BBT_IN_FLASH {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# header file defining the NAND BBT descriptor
+# defines the name of the header file that describes the BBT layout
+#
+cdl_component CYGHWR_FLASH_NAND_BBT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/io/tx25_nand_bbt.h>
+ # value_source inferred
+ # Default value: 0 0
+};
+
+# Number of blocks to reserve for BBT
+# Number of blocks to reserve for BBT
+#
+cdl_option CYGNUM_FLASH_NAND_BBT_BLOCKS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 4
+ # value_source default
+ # Default value: 4
+};
+
+# <
+# MXC platform multi flash memory support
+# When this option is enabled, it indicates multi flashes are
+# supported on the MXC platforms (like NAND and NOR)
+#
+cdl_option CYGHWR_DEVS_FLASH_MXC_MULTI {
+ # This option is not active
+ # ActiveIf constraint: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+ # CYGHWR_DEVS_FLASH_MXC_NAND == 1
+ # CYGHWR_DEVS_FLASH_MXC_NOR == 0
+ # CYGHWR_DEVS_FLASH_MXC_NAND == 1
+ # CYGHWR_DEVS_FLASH_MMC == 0
+ # CYGHWR_DEVS_FLASH_MXC_NOR == 0
+ # CYGHWR_DEVS_FLASH_MMC == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+};
+
+# MXC platform NAND flash reset workaround support
+# When this option is enabled, it indicates 0xFFFF is used for
+# the NAND reset command instead of 0xFF.
+#
+cdl_interface CYGHWR_DEVS_FLASH_MXC_NAND_RESET_WORKAROUND {
+ # No options implement this inferface
+ # ActiveIf constraint: CYGHWR_DEVS_FLASH_MXC_NAND
+ # CYGHWR_DEVS_FLASH_MXC_NAND == 1
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+};
+
+# <
+# <
+# Dynamic memory allocation
+# doc: ref/memalloc.html
+# This package provides memory allocator infrastructure required for
+# dynamic memory allocators, including the ISO standard malloc
+# interface. It also contains some sample implementations.
+#
+cdl_package CYGPKG_MEMALLOC {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # option CYGSEM_COMPRESS_ZLIB_NEEDS_MALLOC
+ # Requires: CYGPKG_MEMALLOC
+};
+
+# >
+# Memory allocator implementations
+# This component contains configuration options related to the
+# various memory allocators available.
+#
+cdl_component CYGPKG_MEMALLOC_ALLOCATORS {
+ # There is no associated value.
+};
+
+# >
+# Fixed block allocator
+# This component contains configuration options related to the
+# fixed block memory allocator.
+#
+cdl_component CYGPKG_MEMALLOC_ALLOCATOR_FIXED {
+ # There is no associated value.
+};
+
+# >
+# Make thread safe
+# With this option enabled, this allocator will be
+# made thread-safe. Additionally allocation functions
+# are made available that allow a thread to wait
+# until memory is available.
+#
+cdl_option CYGSEM_MEMALLOC_ALLOCATOR_FIXED_THREADAWARE {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Simple variable block allocator
+# This component contains configuration options related to the
+# simple variable block memory allocator. This allocator is not
+# very fast, and in particular does not scale well with large
+# numbers of allocations. It is however very compact in terms of
+# code size and does not have very much overhead per allocation.
+#
+cdl_component CYGPKG_MEMALLOC_ALLOCATOR_VARIABLE {
+ # There is no associated value.
+};
+
+# >
+# Make thread safe
+# With this option enabled, this allocator will be
+# made thread-safe. Additionally allocation functions
+# are added that allow a thread to wait until memory
+# are made available that allow a thread to wait
+# until memory is available.
+#
+cdl_option CYGSEM_MEMALLOC_ALLOCATOR_VARIABLE_THREADAWARE {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Coalesce memory
+# The variable-block memory allocator can perform coalescing
+# of memory whenever the application code releases memory back
+# to the pool. This coalescing reduces the possibility of
+# memory fragmentation problems, but involves extra code and
+# processor cycles.
+#
+cdl_option CYGSEM_MEMALLOC_ALLOCATOR_VARIABLE_COALESCE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGIMP_MEMALLOC_MALLOC_VARIABLE_SIMPLE
+ # Requires: CYGSEM_MEMALLOC_ALLOCATOR_VARIABLE_COALESCE
+};
+
+# <
+# Doug Lea's malloc
+# This component contains configuration options related to the
+# port of Doug Lea's memory allocator, normally known as
+# dlmalloc. dlmalloc has a reputation for being both fast
+# and space-conserving, as well as resisting fragmentation well.
+# It is a common choice for a general purpose allocator and
+# has been used in both newlib and Linux glibc.
+#
+cdl_component CYGPKG_MEMALLOC_ALLOCATOR_DLMALLOC {
+ # There is no associated value.
+};
+
+# >
+# Debug build
+# Doug Lea's malloc implementation has substantial amounts
+# of internal checking in order to verify the operation
+# and consistency of the allocator. However this imposes
+# substantial overhead on each operation. Therefore this
+# checking may be individually disabled.
+#
+cdl_option CYGDBG_MEMALLOC_ALLOCATOR_DLMALLOC_DEBUG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0 != CYGDBG_USE_ASSERTS
+ # CYGDBG_USE_ASSERTS == 0
+ # --> 0
+ # Requires: CYGDBG_USE_ASSERTS
+ # CYGDBG_USE_ASSERTS == 0
+ # --> 0
+};
+
+# Make thread safe
+# With this option enabled, this allocator will be
+# made thread-safe. Additionally allocation functions
+# are made available that allow a thread to wait
+# until memory is available.
+#
+cdl_option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_THREADAWARE {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+};
+
+# Support more than one instance
+# Having this option disabled allows important
+# implementation structures to be declared as a single
+# static instance, allowing faster access. However this
+# would fail if there is more than one instance of
+# the dlmalloc allocator class. Therefore this option can
+# be enabled if multiple instances are required. Note: as
+# a special case, if this allocator is used as the
+# implementation of malloc, and it can be determined there
+# is more than one malloc pool, then this option will be
+# silently enabled.
+#
+cdl_option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_SAFE_MULTIPLE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Use system memmove() and memset()
+# This may be used to control whether memset() and memmove()
+# are used within the implementation. The alternative is
+# to use some macro equivalents, which some people report
+# are faster in some circumstances.
+#
+cdl_option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_USE_MEMCPY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 0 != CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+};
+
+# Minimum alignment of allocated blocks
+# This option controls the minimum alignment that the
+# allocated memory blocks are aligned on, specified as
+# 2^N. Note that using large mininum alignments can lead
+# to excessive memory wastage.
+#
+cdl_option CYGNUM_MEMALLOC_ALLOCATOR_DLMALLOC_ALIGNMENT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 3
+ # value_source default
+ # Default value: 3
+ # Legal values: 3 to 10
+};
+
+# <
+# Variable block allocator with separate metadata
+# This component contains configuration options related to the
+# variable block memory allocator with separate metadata.
+#
+cdl_component CYGPKG_MEMALLOC_ALLOCATOR_SEPMETA {
+ # There is no associated value.
+};
+
+# >
+# Make thread safe
+# With this option enabled, this allocator will be
+# made thread-safe. Additionally allocation functions
+# are made available that allow a thread to wait
+# until memory is available.
+#
+cdl_option CYGSEM_MEMALLOC_ALLOCATOR_SEPMETA_THREADAWARE {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# <
+# Kernel C API support for memory allocation
+# This option must be enabled to provide the extensions required
+# to support integration into the kernel C API.
+#
+cdl_option CYGFUN_MEMALLOC_KAPI {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGFUN_KERNEL_API_C
+ # CYGFUN_KERNEL_API_C (unknown) == 0
+ # --> 0
+};
+
+# malloc(0) returns NULL
+# This option controls the behavior of malloc(0) ( or calloc with
+# either argument 0 ). It is permitted by the standard to return
+# either a NULL pointer or a unique pointer. Enabling this option
+# forces a NULL pointer to be returned.
+#
+cdl_option CYGSEM_MEMALLOC_MALLOC_ZERO_RETURNS_NULL {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Breakpoint site when running out of memory
+# Whenever the system runs out of memory, it invokes this function
+# before either going to sleep waiting for memory to become
+# available or returning failure.
+#
+cdl_option CYGSEM_MEMALLOC_INVOKE_OUT_OF_MEMORY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# malloc() and supporting allocators
+# This component enables support for dynamic memory
+# allocation as supplied by the functions malloc(),
+# free(), calloc() and realloc(). As these
+# functions are often used, but can have quite an
+# overhead, disabling them here can ensure they
+# cannot even be used accidentally when static
+# allocation is preferred. Within this component are
+# various allocators that can be selected for use
+# as the underlying implementation of the dynamic
+# allocation functions.
+#
+cdl_component CYGPKG_MEMALLOC_MALLOC_ALLOCATORS {
+ # ActiveIf constraint: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Use external heap definition
+# This option allows other components in the
+# system to override the default system
+# provision of heap memory pools. This should
+# be set to a header which provides the equivalent
+# definitions to <pkgconf/heaps.hxx>.
+#
+cdl_component CYGBLD_MEMALLOC_MALLOC_EXTERNAL_HEAP_H {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Use external implementation of joining multiple heaps
+# The default implementation of joining multiple heaps
+# is fine for the case where there are multiple disjoint
+# memory regions of the same type. However, in a system
+# there might be e.g. a small amount of internal SRAM and
+# a large amount of external DRAM. The SRAM is faster and
+# the DRAM is slower. An application can implement some
+# heuristic to choose which pool to allocate from. This
+# heuristic can be highly application specific.
+#
+cdl_component CYGBLD_MEMALLOC_MALLOC_EXTERNAL_JOIN_H {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# malloc() allocator implementations
+#
+cdl_interface CYGINT_MEMALLOC_MALLOC_ALLOCATORS {
+ # Implemented by CYGIMP_MEMALLOC_MALLOC_VARIABLE_SIMPLE, active, disabled
+ # Implemented by CYGIMP_MEMALLOC_MALLOC_DLMALLOC, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: CYGINT_MEMALLOC_MALLOC_ALLOCATORS == 1
+ # CYGINT_MEMALLOC_MALLOC_ALLOCATORS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_MEMALLOC_MALLOC_ALLOCATORS
+ # Requires: CYGINT_MEMALLOC_MALLOC_ALLOCATORS == 1
+};
+
+# malloc() implementation instantiation data
+# Memory allocator implementations that are capable of being
+# used underneath malloc() must be instantiated. The code
+# to do this is set in this option. It is only intended to
+# be set by the implementation, not the user.
+#
+cdl_option CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value <cyg/memalloc/dlmalloc.hxx>
+ # value_source default
+ # Default value: <cyg/memalloc/dlmalloc.hxx>
+
+ # The following properties are affected by this value
+ # option CYGIMP_MEMALLOC_MALLOC_VARIABLE_SIMPLE
+ # Requires: CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == "<cyg/memalloc/memvar.hxx>"
+ # option CYGIMP_MEMALLOC_MALLOC_DLMALLOC
+ # Requires: CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == "<cyg/memalloc/dlmalloc.hxx>"
+};
+
+# Simple variable block implementation
+# This causes malloc() to use the simple
+# variable block allocator.
+#
+cdl_option CYGIMP_MEMALLOC_MALLOC_VARIABLE_SIMPLE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == "<cyg/memalloc/memvar.hxx>"
+ # CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == <cyg/memalloc/dlmalloc.hxx>
+ # --> 0
+ # Requires: CYGSEM_MEMALLOC_ALLOCATOR_VARIABLE_COALESCE
+ # CYGSEM_MEMALLOC_ALLOCATOR_VARIABLE_COALESCE == 1
+ # --> 1
+};
+
+# Doug Lea's malloc implementation
+# This causes malloc() to use a version of Doug Lea's
+# malloc (dlmalloc) as the underlying implementation.
+#
+cdl_option CYGIMP_MEMALLOC_MALLOC_DLMALLOC {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == "<cyg/memalloc/dlmalloc.hxx>"
+ # CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == <cyg/memalloc/dlmalloc.hxx>
+ # --> 1
+};
+
+# <
+# Size of the fallback dynamic memory pool in bytes
+# If *no* heaps are configured in your memory layout,
+# dynamic memory allocation by
+# malloc() and calloc() must be from a fixed-size,
+# contiguous memory pool (note here that it is the
+# pool that is of a fixed size, but malloc() is still
+# able to allocate variable sized chunks of memory
+# from it). This option is the size
+# of that pool, in bytes. Note that not all of
+# this is available for programs to
+# use - some is needed for internal information
+# about memory regions, and some may be lost to
+# ensure that memory allocation only returns
+# memory aligned on word (or double word)
+# boundaries - a very common architecture
+# constraint.
+#
+cdl_option CYGNUM_MEMALLOC_FALLBACK_MALLOC_POOL_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 16384
+ # value_source default
+ # Default value: 16384
+ # Legal values: 32 to 0x7fffffff
+};
+
+# Common memory allocator package build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_MEMALLOC_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_MEMALLOC_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-fno-rtti -Woverloaded-virtual"
+ # value_source default
+ # Default value: "-fno-rtti -Woverloaded-virtual"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_MEMALLOC_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wno-pointer-sign
+ # value_source default
+ # Default value: -Wno-pointer-sign
+};
+
+# Tests
+# This option specifies the set of tests for this package.
+#
+cdl_option CYGPKG_MEMALLOC_TESTS {
+ # Calculated value: "tests/dlmalloc1 tests/dlmalloc2 tests/heaptest tests/kmemfix1 tests/kmemvar1 tests/malloc1 tests/malloc2 tests/malloc3 tests/malloc4 tests/memfix1 tests/memfix2 tests/memvar1 tests/memvar2 tests/realloc tests/sepmeta1 tests/sepmeta2"
+ # Flavor: data
+ # Current_value: tests/dlmalloc1 tests/dlmalloc2 tests/heaptest tests/kmemfix1 tests/kmemvar1 tests/malloc1 tests/malloc2 tests/malloc3 tests/malloc4 tests/memfix1 tests/memfix2 tests/memvar1 tests/memvar2 tests/realloc tests/sepmeta1 tests/sepmeta2
+};
+
+# <
+# <
+# Common error code support
+# This package contains the common list of error and
+# status codes. It is held centrally to allow
+# packages to interchange error codes and status
+# codes in a common way, rather than each package
+# having its own conventions for error/status
+# reporting. The error codes are modelled on the
+# POSIX style naming e.g. EINVAL etc. This package
+# also provides the standard strerror() function to
+# convert error codes to textual representation, as
+# well as an implementation of the errno idiom.
+#
+cdl_package CYGPKG_ERROR {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGBLD_ISO_ERRNO_CODES_HEADER == "<cyg/error/codes.h>"
+ # CYGBLD_ISO_ERRNO_CODES_HEADER == <cyg/error/codes.h>
+ # --> 1
+};
+
+# >
+# errno variable
+# This package controls the behaviour of the
+# errno variable (or more strictly, expression)
+# from <errno.h>.
+#
+cdl_component CYGPKG_ERROR_ERRNO {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_ERRNO_HEADER == "<cyg/error/errno.h>"
+ # CYGBLD_ISO_ERRNO_HEADER == <cyg/error/errno.h>
+ # --> 1
+};
+
+# >
+# Per-thread errno
+# This option controls whether the standard error
+# code reporting variable errno is a per-thread
+# variable, rather than global.
+#
+cdl_option CYGSEM_ERROR_PER_THREAD_ERRNO {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+ # Requires: CYGVAR_KERNEL_THREADS_DATA
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+};
+
+# Tracing level
+# Trace verbosity level for debugging the errno
+# retrieval mechanism in errno.cxx. Increase this
+# value to get additional trace output.
+#
+cdl_option CYGNUM_ERROR_ERRNO_TRACE_LEVEL {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to 1
+};
+
+# <
+# strerror function
+# This package controls the presence and behaviour of the
+# strerror() function from <string.h>
+#
+cdl_option CYGPKG_ERROR_STRERROR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_STRERROR_HEADER == "<cyg/error/strerror.h>"
+ # CYGBLD_ISO_STRERROR_HEADER == <cyg/error/strerror.h>
+ # --> 1
+};
+
+# Error package build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_ERROR_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the error package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_ERROR_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the error package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_ERROR_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# <
+# <
+# <
+
--- /dev/null
+# eCos saved configuration
+
+# ---- commands --------------------------------------------------------
+# This section contains information about the savefile format.
+# It should not be edited. Any modifications made to this section
+# may make it impossible for the configuration tools to read
+# the savefile.
+
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+# ---- toplevel --------------------------------------------------------
+# This section defines the toplevel configuration object. The only
+# values that can be changed are the name of the configuration and
+# the description field. It is not possible to modify the target,
+# the template or the set of packages simply by editing the lines
+# below because these changes have wide-ranging effects. Instead
+# the appropriate tools should be used to make such modifications.
+
+cdl_configuration eCos {
+ description "" ;
+
+ # These fields should not be modified.
+ hardware tx27karo ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM current ;
+ package -hardware CYGPKG_HAL_ARM_MX27 current ;
+ package -hardware CYGPKG_HAL_ARM_TX27KARO current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_TX27 current ;
+ package -hardware CYGPKG_DEVS_ETH_FEC current ;
+ package -hardware CYGPKG_COMPRESS_ZLIB current ;
+ package -hardware CYGPKG_IO_FLASH current ;
+ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+ package -template CYGPKG_MEMALLOC current ;
+ package -template CYGPKG_DEVS_ETH_PHY current ;
+ package -template CYGPKG_LIBC_I18N current ;
+ package -template CYGPKG_LIBC_STDLIB current ;
+ package -template CYGPKG_ERROR current ;
+};
+
+# ---- conflicts -------------------------------------------------------
+# There are no conflicts.
+
+# ---- contents --------------------------------------------------------
+# >
+# >
+# Global build options
+# Global build options including control over
+# compiler flags, linker flags and choice of toolchain.
+#
+cdl_component CYGBLD_GLOBAL_OPTIONS {
+ # There is no associated value.
+
+ # The following properties are affected by this value
+};
+
+# >
+# Global command prefix
+# This option specifies the command prefix used when
+# invoking the build tools.
+#
+cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value arm-926ejs-linux-gnu
+ # value_source default
+ # Default value: arm-926ejs-linux-gnu
+};
+
+# Global compiler flags
+# This option controls the global compiler flags which are used to
+# compile all packages by default. Individual packages may define
+# options which override these global flags.
+#
+cdl_option CYGBLD_GLOBAL_CFLAGS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe"
+ # The inferred value should not be edited directly.
+ inferred_value "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe"
+ # value_source inferred
+ # Default value: "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe"
+ # Requires: CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS
+ # CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS
+ # Requires: is_substr(CYGBLD_GLOBAL_CFLAGS, " -Werror")
+ # option CYGBLD_INFRA_CFLAGS_PIPE
+ # Requires: is_substr(CYGBLD_GLOBAL_CFLAGS, " -pipe")
+};
+
+# Global linker flags
+# This option controls the global linker flags. Individual
+# packages may define options which override these global flags.
+#
+cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-Wl,--gc-sections -Wl,-static -O2 -nostdlib"
+ # value_source default
+ # Default value: "-Wl,--gc-sections -Wl,-static -O2 -nostdlib"
+};
+
+# Build common GDB stub ROM image
+# Unless a target board has specific requirements to the
+# stub implementation, it can use a simple common stub.
+# This option, which gets enabled by platform HALs as
+# appropriate, controls the building of the common stub.
+#
+cdl_option CYGBLD_BUILD_COMMON_GDB_STUBS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+};
+
+# <
+# ISO C library string functions
+# doc: ref/libc.html
+# This package provides string functions specified by the
+# ISO C standard - ISO/IEC 9899:1990.
+#
+cdl_package CYGPKG_LIBC_STRING {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER == "<cyg/libc/string/string.h>"
+ # CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER == <cyg/libc/string/string.h>
+ # --> 1
+ # Requires: CYGBLD_ISO_STRING_MEMFUNCS_HEADER == "<cyg/libc/string/string.h>"
+ # CYGBLD_ISO_STRING_MEMFUNCS_HEADER == <cyg/libc/string/string.h>
+ # --> 1
+ # Requires: CYGBLD_ISO_STRING_STRFUNCS_HEADER == "<cyg/libc/string/string.h>"
+ # CYGBLD_ISO_STRING_STRFUNCS_HEADER == <cyg/libc/string/string.h>
+ # --> 1
+ # Requires: CYGBLD_ISO_STRTOK_R_HEADER == "<cyg/libc/string/string.h>"
+ # CYGBLD_ISO_STRTOK_R_HEADER == <cyg/libc/string/string.h>
+ # --> 1
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+};
+
+# >
+# Inline versions of <string.h> functions
+# This option chooses whether some of the
+# particularly simple string functions from
+# <string.h> are available as inline
+# functions. This may improve performance, and as
+# the functions are small, may even improve code
+# size.
+#
+cdl_option CYGIMP_LIBC_STRING_INLINES {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Optimize string functions for code size
+# This option tries to reduce string function
+# code size at the expense of execution speed. The
+# same effect can be produced if the code is
+# compiled with the -Os option to the compiler.
+#
+cdl_option CYGIMP_LIBC_STRING_PREFER_SMALL_TO_FAST {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Provide BSD compatibility functions
+# Enabling this option causes various compatibility functions
+# commonly found in the BSD UNIX operating system to be included.
+# These are functions such as bzero, bcmp, bcopy, bzero, strcasecmp,
+# strncasecmp, index, rindex and swab.
+#
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+ # Requires: CYGBLD_ISO_STRING_BSD_FUNCS_HEADER == "<cyg/libc/string/bsdstring.h>"
+ # CYGBLD_ISO_STRING_BSD_FUNCS_HEADER == <cyg/libc/string/bsdstring.h>
+ # --> 1
+ # Requires: CYGINT_ISO_CTYPE
+ # CYGINT_ISO_CTYPE == 1
+ # --> 1
+};
+
+# strtok
+# These options control the behaviour of the
+# strtok() and strtok_r() string tokenization
+# functions.
+#
+cdl_component CYGPKG_LIBC_STRING_STRTOK {
+ # There is no associated value.
+};
+
+# >
+# Per-thread strtok()
+# This option controls whether the string function
+# strtok() has its state recorded on a per-thread
+# basis rather than global. If this option is
+# disabled, some per-thread space can be saved.
+# Note there is also a POSIX-standard strtok_r()
+# function to achieve a similar effect with user
+# support. Enabling this option will use one slot
+# of kernel per-thread data. You should ensure you
+# have enough slots configured for all your
+# per-thread data.
+#
+cdl_option CYGSEM_LIBC_STRING_PER_THREAD_STRTOK {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGVAR_KERNEL_THREADS_DATA
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+ # Requires: CYGVAR_KERNEL_THREADS_DATA
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+};
+
+# Tracing level
+# Trace verbosity level for debugging the <string.h>
+# functions strtok() and strtok_r(). Increase this
+# value to get additional trace output.
+#
+cdl_option CYGNUM_LIBC_STRING_STRTOK_TRACE_LEVEL {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to 1
+};
+
+# <
+# strdup
+# This option indicates whether strdup() is to be supported.
+#
+cdl_option CYGFUN_LIBC_STRING_STRDUP {
+ # ActiveIf constraint: CYGINT_ISO_MALLOC
+ # CYGINT_ISO_MALLOC == 1
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+};
+
+# C library string functions build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_LIBC_STRING_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the C library. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_LIBC_STRING_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-fno-rtti -Woverloaded-virtual"
+ # value_source default
+ # Default value: "-fno-rtti -Woverloaded-virtual"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the C library. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_LIBC_STRING_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wno-pointer-sign
+ # value_source default
+ # Default value: -Wno-pointer-sign
+};
+
+# C library string function tests
+# This option specifies the set of tests for the C library
+# string functions.
+#
+cdl_option CYGPKG_LIBC_STRING_TESTS {
+ # Calculated value: "tests/memchr tests/memcmp1 tests/memcmp2 tests/memcpy1 tests/memcpy2 tests/memmove1 tests/memmove2 tests/memset tests/strcat1 tests/strcat2 tests/strchr tests/strcmp1 tests/strcmp2 tests/strcoll1 tests/strcoll2 tests/strcpy1 tests/strcpy2 tests/strcspn tests/strcspn tests/strlen tests/strncat1 tests/strncat2 tests/strncpy1 tests/strncpy2 tests/strpbrk tests/strrchr tests/strspn tests/strstr tests/strtok tests/strxfrm1 tests/strxfrm2"
+ # Flavor: data
+ # Current_value: tests/memchr tests/memcmp1 tests/memcmp2 tests/memcpy1 tests/memcpy2 tests/memmove1 tests/memmove2 tests/memset tests/strcat1 tests/strcat2 tests/strchr tests/strcmp1 tests/strcmp2 tests/strcoll1 tests/strcoll2 tests/strcpy1 tests/strcpy2 tests/strcspn tests/strcspn tests/strlen tests/strncat1 tests/strncat2 tests/strncpy1 tests/strncpy2 tests/strpbrk tests/strrchr tests/strspn tests/strstr tests/strtok tests/strxfrm1 tests/strxfrm2
+};
+
+# <
+# <
+# Common ethernet support
+# doc: ref/io-eth-drv-generic.html
+# Platform independent ethernet drivers
+#
+cdl_package CYGPKG_IO_ETH_DRIVERS {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # component CYGPKG_REDBOOT_NETWORKING
+ # ActiveIf: CYGPKG_IO_ETH_DRIVERS
+ # package CYGPKG_DEVS_ETH_ARM_TX27
+ # ActiveIf: CYGPKG_IO_ETH_DRIVERS
+ # package CYGPKG_DEVS_ETH_FEC
+ # ActiveIf: CYGPKG_IO_ETH_DRIVERS
+ # package CYGPKG_DEVS_ETH_PHY
+ # ActiveIf: CYGPKG_IO_ETH_DRIVERS
+};
+
+# >
+# Network drivers
+#
+cdl_interface CYGHWR_NET_DRIVERS {
+ # Implemented by CYGPKG_DEVS_ETH_FEC, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGDAT_REDBOOT_DEFAULT_NETWORK_DEVICE
+ # ActiveIf: CYGHWR_NET_DRIVERS > 1
+ # option CYGSEM_REDBOOT_NETWORK_INIT_ONE_DEVICE
+ # ActiveIf: CYGHWR_NET_DRIVERS > 1
+};
+
+# Driver supports multicast addressing
+# This interface defines whether or not a driver can handle
+# requests for multicast addressing.
+#
+cdl_interface CYGINT_IO_ETH_MULTICAST {
+ # Implemented by CYGPKG_DEVS_ETH_FEC, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+};
+
+# Support printing driver debug information
+# Selecting this option will include code to allow the driver to
+# print lots of information on diagnostic output such as full
+# packet dumps.
+#
+cdl_component CYGDBG_IO_ETH_DRIVERS_DEBUG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Driver debug output verbosity
+# The value of this option indicates the default verbosity
+# level of debugging output. 0 means no debugging output
+# is made by default. Higher values indicate higher verbosity.
+# The verbosity level may also be changed at run time by
+# changing the variable cyg_io_eth_net_debug.
+#
+cdl_option CYGDBG_IO_ETH_DRIVERS_DEBUG_VERBOSITY {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Size of scatter-gather I/O lists
+# A scatter-gather list is used to pass requests to/from
+# the physical device driver. This list can typically be
+# small, as the data is normally already packed into reasonable
+# chunks.
+#
+cdl_option CYGNUM_IO_ETH_DRIVERS_SG_LIST_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 32
+ # value_source default
+ # Default value: 32
+};
+
+# Support for standard eCos TCP/IP stack.
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_NET {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_NET
+ # CYGPKG_NET (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+};
+
+# >
+# Warn when there are no more mbufs
+# Warnings about running out of mbufs are printed to the
+# diagnostic output channel via diag_printf() if this option
+# is enabled. Mbufs are the network stack's basic dynamic
+# memory objects that hold all packets in transit; running
+# out is bad for performance but not fatal, not a crash.
+# You might want to turn off the warnings to preserve realtime
+# properties of the system even in extremis.
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_WARN_NO_MBUFS {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_NET is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Simulate network failures for testing
+# This package contains a suite of simulated failure modes
+# for the ethernet device layer, including dropping and/or
+# corrupting received packets, dropping packets queued for
+# transmission, and simulating a complete network break.
+# It requires the kernel as a source of time information.
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_NET is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# >
+# Drop incoming packets (percentage)
+#
+cdl_option CYGPKG_IO_ETH_DRIVERS_SIMULATE_DROP_RX {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 1 10
+ # value_source default
+ # Default value: 1 10
+ # Legal values: 10 50 80
+};
+
+# Corrupt incoming packets (percentage)
+#
+cdl_option CYGPKG_IO_ETH_DRIVERS_SIMULATE_CORRUPT_RX {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 1 10
+ # value_source default
+ # Default value: 1 10
+ # Legal values: 10 50 80
+};
+
+# Drop outgoing packets (percentage)
+#
+cdl_option CYGPKG_IO_ETH_DRIVERS_SIMULATE_DROP_TX {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 1 10
+ # value_source default
+ # Default value: 1 10
+ # Legal values: 10 50 80
+};
+
+# Simulate a line cut from time to time
+# This option causes the system to drop all packets for a
+# short random period (10s of seconds), and then act
+# normally for up to 4 times that long. This simulates your
+# sysadmin fiddling with plugs in the network switch
+# cupboard.
+#
+cdl_option CYGPKG_IO_ETH_DRIVERS_SIMULATE_LINE_CUT {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# <
+# Support for stand-alone network stack.
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_STAND_ALONE {
+ # ActiveIf constraint: !CYGPKG_NET
+ # CYGPKG_NET (unknown) == 0
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGINT_ISO_STRING_MEMFUNCS
+ # CYGINT_ISO_STRING_MEMFUNCS == 1
+ # --> 1
+};
+
+# >
+# Pass packets to an alternate stack
+# Define this to allow packets seen by this layer to be
+# passed on to the previous logical layer, i.e. when
+# stand-alone processing replaces system (eCos) processing.
+#
+cdl_option CYGSEM_IO_ETH_DRIVERS_PASS_PACKETS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 0 != CYGPKG_REDBOOT_NETWORKING
+ # CYGPKG_REDBOOT_NETWORKING == 1
+ # --> 1
+};
+
+# Number of [network] buffers
+# This option is used to allocate space to buffer incoming network
+# packets. These buffers are used to hold data until they can be
+# logically processed by higher layers.
+#
+cdl_option CYGNUM_IO_ETH_DRIVERS_NUM_PKT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 4
+ # value_source default
+ # Default value: 4
+ # Legal values: 2 to 32
+};
+
+# Show driver warnings
+# Selecting this option will allows the stand-alone ethernet driver
+# to display warnings on the system console when incoming network
+# packets are being discarded due to lack of buffer space.
+#
+cdl_option CYGSEM_IO_ETH_DRIVERS_WARN {
+ # ActiveIf constraint: CYGPKG_REDBOOT
+ # CYGPKG_REDBOOT == current
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Support for lwIP network stack.
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_LWIP {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_NET_LWIP
+ # CYGPKG_NET_LWIP (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: !CYGPKG_NET
+ # CYGPKG_NET (unknown) == 0
+ # --> 1
+};
+
+# Interrupt support required
+# This interface is used to indicate to the low
+# level device drivers that interrupt driven operation
+# is required by higher layers.
+#
+cdl_interface CYGINT_IO_ETH_INT_SUPPORT_REQUIRED {
+ # Implemented by CYGPKG_IO_ETH_DRIVERS_NET, inactive, enabled
+ # Implemented by CYGPKG_IO_ETH_DRIVERS_LWIP, inactive, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+
+ # The following properties are affected by this value
+};
+
+# Common ethernet support build options
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the common ethernet support package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_IO_ETH_DRIVERS_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-D_KERNEL -D__ECOS"
+ # value_source default
+ # Default value: "-D_KERNEL -D__ECOS"
+};
+
+# <
+# Ethernet driver for Ka-Ro electronics TX27 processor module
+#
+cdl_package CYGPKG_DEVS_ETH_ARM_TX27 {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # ActiveIf constraint: CYGPKG_IO_ETH_DRIVERS
+ # CYGPKG_IO_ETH_DRIVERS == current
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+};
+
+# >
+# FEC ethernet driver required
+#
+cdl_interface CYGINT_DEVS_ETH_FEC_REQUIRED {
+ # Implemented by CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # package CYGPKG_DEVS_ETH_FEC
+ # ActiveIf: CYGINT_DEVS_ETH_FEC_REQUIRED
+};
+
+# Ka-Ro TX27 ethernet port driver
+# This option includes the ethernet device driver for the
+# MXC Board port.
+#
+cdl_component CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ # CYGSEM_REDBOOT_PLF_ESA_VALIDATE == 1
+ # --> 1
+ # Requires: CYGHWR_DEVS_ETH_PHY_LAN8700
+ # CYGHWR_DEVS_ETH_PHY_LAN8700 == 1
+ # --> 1
+};
+
+# >
+# Device name for the ETH0 ethernet driver
+# This option sets the name of the ethernet device.
+#
+cdl_option CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "\"eth0\""
+ # value_source default
+ # Default value: "\"eth0\""
+};
+
+# OUI part of MAC address
+# This option sets OUI part (manufacturer ID) of the MAC address
+# for validation.
+#
+cdl_option CYGDAT_DEVS_ETH_ARM_TX27KARO_OUI {
+ # ActiveIf constraint: CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ # CYGSEM_REDBOOT_PLF_ESA_VALIDATE == 1
+ # --> 1
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "{ 0x00, 0x0c, 0xc6 }"
+ # value_source default
+ # Default value: "{ 0x00, 0x0c, 0xc6 }"
+};
+
+# <
+# <
+# Driver for fast ethernet controller.
+# Driver for fast ethernet controller.
+#
+cdl_package CYGPKG_DEVS_ETH_FEC {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # ActiveIf constraint: CYGPKG_IO_ETH_DRIVERS
+ # CYGPKG_IO_ETH_DRIVERS == current
+ # --> 1
+ # ActiveIf constraint: CYGINT_DEVS_ETH_FEC_REQUIRED
+ # CYGINT_DEVS_ETH_FEC_REQUIRED == 1
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+};
+
+# >
+# MXC FEC ethernet driver build options
+#
+cdl_component CYGPKG_DEVS_ETH_FEC_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the Cirrus Logic ethernet driver package.
+# These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_DEVS_ETH_FEC_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-D_KERNEL -D__ECOS"
+ # value_source default
+ # Default value: "-D_KERNEL -D__ECOS"
+};
+
+# <
+# <
+# Ethernet transceiver (PHY) support
+# API for ethernet PHY devices
+#
+cdl_package CYGPKG_DEVS_ETH_PHY {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # ActiveIf constraint: CYGPKG_IO_ETH_DRIVERS
+ # CYGPKG_IO_ETH_DRIVERS == current
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT == 1
+ # --> 1
+};
+
+# >
+# Enable driver debugging
+# Enables the diagnostic debug messages on the
+# console device.
+#
+cdl_option CYGDBG_DEVS_ETH_PHY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Time period (seconds) to wait for auto-negotiation
+# The length of time to wait for auto-negotiation to complete
+# before giving up and declaring the link dead/missing.
+#
+cdl_option CYGINT_DEVS_ETH_PHY_AUTO_NEGOTIATION_TIME {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 5
+ # value_source default
+ # Default value: 5
+};
+
+# NSDP83847
+# Include support for National Semiconductor DP83847 DsPHYTER II
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_DP83847 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# AMD 79C874
+# Include support for AMD 79C874 NetPHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_AM79C874 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Intel LXT972
+# Include support for Intel LXT972xxx PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_INLXT972 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# ICS 1890
+# Include support for ICS 1890 PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_ICS1890 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# ICS 1892
+# Include support for ICS 1892 PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_ICS1892 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# ICS 1893
+# Include support for ICS 1893 and 1893AF PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_ICS1893 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Davicom DM9161A
+# Include support for the Davicom DM9161A PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_DM9161A {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Micrel KS8721
+# Include support for the Micrel KS8721 PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_KS8721 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# SMSC LAN8700
+# Include support for SMSC LAN8700 NetPHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_LAN8700 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # component CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
+ # Requires: CYGHWR_DEVS_ETH_PHY_LAN8700
+};
+
+# <
+# <
+# ISO C library internationalization functions
+# doc: ref/libc.html
+# This package provides internationalization functions specified by the
+# ISO C standard - ISO/IEC 9899:1990. These include locale-related
+# functionality and <ctype.h> functionality.
+#
+cdl_package CYGPKG_LIBC_I18N {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+};
+
+# >
+# Supported locales
+# These options determine which locales other than the "C" locale
+# are supported and hence contribute to the size of the executable.
+#
+cdl_component CYGPKG_LIBC_I18N_LOCALES {
+ # There is no associated value.
+};
+
+# >
+# Support for multiple locales required
+#
+cdl_interface CYGINT_LIBC_I18N_MB_REQUIRED {
+ # Implemented by CYGFUN_LIBC_I18N_LOCALE_C_SJIS, active, disabled
+ # Implemented by CYGFUN_LIBC_I18N_LOCALE_C_JIS, active, disabled
+ # Implemented by CYGFUN_LIBC_I18N_LOCALE_C_EUCJP, active, disabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: CYGBLD_ISO_STDLIB_MB_CUR_MAX_HEADER == "<cyg/libc/i18n/mb.h>"
+ # CYGBLD_ISO_STDLIB_MB_CUR_MAX_HEADER == 0
+ # --> 0
+
+ # The following properties are affected by this value
+};
+
+# C-SJIS locale support
+# This option controls if the "C-SJIS" locale will be
+# supported by setlocale(). The locale is a hybrid locale
+# that is mostly the "C" locale with Japanese SJIS multibyte
+# support added.
+#
+cdl_option CYGFUN_LIBC_I18N_LOCALE_C_SJIS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # LegalValues: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2))) to 0x7fffffff
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # DefaultValue: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2)))
+};
+
+# C-JIS locale support
+# This option controls if the "C-JIS" locale will be
+# supported by setlocale(). The locale is a hybrid locale
+# that is mostly the "C" locale with Japanese JIS multibyte
+# support added.
+#
+cdl_option CYGFUN_LIBC_I18N_LOCALE_C_JIS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # LegalValues: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2))) to 0x7fffffff
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # DefaultValue: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2)))
+};
+
+# C-EUCJP locale support
+# This option controls if the "C-EUCJP" locale will be
+# supported by setlocale(). The locale is a hybrid locale
+# that is mostly the "C" locale with Japanese EUCJP multibyte
+# support added.
+#
+cdl_option CYGFUN_LIBC_I18N_LOCALE_C_EUCJP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # LegalValues: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2))) to 0x7fffffff
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # DefaultValue: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2)))
+};
+
+# <
+# Newlib's ctype implementation
+# This option enables the implementation of the ctype functions
+# that comes with newlib. It is table driven and therefore
+# exhibits different performance characteristics. It also offers
+# a limited amount of binary compatibility
+# with newlib so that programs linked against newlib ctype/locale
+# do not need to be recompiled when linked with eCos.
+#
+cdl_option CYGPKG_LIBC_I18N_NEWLIB_CTYPE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGBLD_ISO_CTYPE_HEADER == "<cyg/libc/i18n/newlibctype.h>"
+ # CYGBLD_ISO_CTYPE_HEADER == <cyg/libc/i18n/ctype.inl>
+ # --> 0
+};
+
+# Per-thread multibyte state
+# This option controls whether the multibyte character
+# handling functions mblen(), mbtowc(), and wctomb(),
+# have their state recorded on a per-thread
+# basis rather than global. If this option is
+# disabled, some per-thread space can be saved.
+# Enabling this option will use three slots
+# of kernel per-thread data. You should ensure you
+# have enough slots configured for all your
+# per-thread data.
+#
+cdl_option CYGSEM_LIBC_I18N_PER_THREAD_MB {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGVAR_KERNEL_THREADS_DATA != 0
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+ # Requires: CYGVAR_KERNEL_THREADS_DATA
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+};
+
+# Size of locale name strings
+# This option controls the maximum size of
+# locale names and is used, among other things
+# to instantiate a static string used
+# as a return value from the
+# setlocale() function. When requesting the
+# current locale settings with LC_ALL, a string
+# must be constructed to contain this data, rather
+# than just returning a constant string. This
+# string data is stored in the static string.
+# This depends on the length of locale names,
+# hence this option. If just the C locale is
+# present, this option can be set as low as 2.
+#
+cdl_option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 2
+ # value_source default
+ # Default value: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2)))
+ # CYGFUN_LIBC_I18N_LOCALE_C_EUCJP == 0
+ # CYGFUN_LIBC_I18N_LOCALE_C_SJIS == 0
+ # CYGFUN_LIBC_I18N_LOCALE_C_JIS == 0
+ # --> 2
+ # Legal values: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2))) to 0x7fffffff
+ # CYGFUN_LIBC_I18N_LOCALE_C_EUCJP == 0
+ # CYGFUN_LIBC_I18N_LOCALE_C_SJIS == 0
+ # CYGFUN_LIBC_I18N_LOCALE_C_JIS == 0
+};
+
+# Inline versions of <ctype.h> functions
+# This option chooses whether the simple character
+# classification and conversion functions (e.g.
+# isupper(), isalpha(), toupper(), etc.)
+# from <ctype.h> are available as inline
+# functions. This may improve performance and as
+# the functions are small, may even improve code
+# size.
+#
+cdl_option CYGIMP_LIBC_I18N_CTYPE_INLINES {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_CTYPE_HEADER == "<cyg/libc/i18n/ctype.inl>"
+ # CYGBLD_ISO_CTYPE_HEADER == <cyg/libc/i18n/ctype.inl>
+ # --> 1
+};
+
+# C library i18n functions build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_LIBC_I18N_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the C library. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_LIBC_I18N_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-fno-rtti -Woverloaded-virtual"
+ # value_source default
+ # Default value: "-fno-rtti -Woverloaded-virtual"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the C library. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_LIBC_I18N_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wno-pointer-sign
+ # value_source default
+ # Default value: -Wno-pointer-sign
+};
+
+# C library i18n function tests
+# This option specifies the set of tests for the C library
+# i18n functions.
+#
+cdl_option CYGPKG_LIBC_I18N_TESTS {
+ # Calculated value: "tests/ctype tests/setlocale tests/i18nmb"
+ # Flavor: data
+ # Current_value: tests/ctype tests/setlocale tests/i18nmb
+};
+
+# <
+# <
+# ISO C library general utility functions
+# doc: ref/libc.html
+# This package provides general utility functions in <stdlib.h>
+# as specified by the ISO C standard - ISO/IEC 9899:1990.
+#
+cdl_package CYGPKG_LIBC_STDLIB {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+ # Requires: CYGINT_ISO_CTYPE
+ # CYGINT_ISO_CTYPE == 1
+ # --> 1
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+};
+
+# >
+# Inline versions of <stdlib.h> functions
+# This option chooses whether some of the
+# particularly simple standard utility functions
+# from <stdlib.h> are available as inline
+# functions. This may improve performance, and as
+# the functions are small, may even improve code
+# size.
+#
+cdl_component CYGIMP_LIBC_STDLIB_INLINES {
+ # There is no associated value.
+};
+
+# >
+# abs() / labs()
+#
+cdl_option CYGIMP_LIBC_STDLIB_INLINE_ABS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_STDLIB_ABS_HEADER == "<cyg/libc/stdlib/abs.inl>"
+ # CYGBLD_ISO_STDLIB_ABS_HEADER == <cyg/libc/stdlib/abs.inl>
+ # --> 1
+};
+
+# div() / ldiv()
+#
+cdl_option CYGIMP_LIBC_STDLIB_INLINE_DIV {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_STDLIB_DIV_HEADER == "<cyg/libc/stdlib/div.inl>"
+ # CYGBLD_ISO_STDLIB_DIV_HEADER == <cyg/libc/stdlib/div.inl>
+ # --> 1
+};
+
+# atof() / atoi() / atol()
+#
+cdl_option CYGIMP_LIBC_STDLIB_INLINE_ATOX {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_STDLIB_STRCONV_HEADER == "<cyg/libc/stdlib/atox.inl>"
+ # CYGBLD_ISO_STDLIB_STRCONV_HEADER == <cyg/libc/stdlib/atox.inl>
+ # --> 1
+};
+
+# <
+# Random number generation
+# These options control the behaviour of the
+# functions rand(), srand() and rand_r()
+#
+cdl_component CYGPKG_LIBC_RAND {
+ # There is no associated value.
+};
+
+# >
+# Per-thread random seed
+# doc: ref/libc-thread-safety.html
+# This option controls whether the pseudo-random
+# number generation functions rand() and srand()
+# have their state recorded on a per-thread
+# basis rather than global. If this option is
+# disabled, some per-thread space can be saved.
+# Note there is also a POSIX-standard rand_r()
+# function to achieve a similar effect with user
+# support. Enabling this option will use one slot
+# of kernel per-thread data. You should ensure you
+# have enough slots configured for all your
+# per-thread data.
+#
+cdl_option CYGSEM_LIBC_PER_THREAD_RAND {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGVAR_KERNEL_THREADS_DATA
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+};
+
+# Random number seed
+# This selects the initial random number seed for
+# rand()'s pseudo-random number generator. For
+# strict ISO standard compliance, this should be 1,
+# as per section 7.10.2.2 of the standard.
+#
+cdl_option CYGNUM_LIBC_RAND_SEED {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Legal values: 0 to 0x7fffffff
+};
+
+# Tracing level
+# Trace verbosity level for debugging the rand(),
+# srand() and rand_r() functions. Increase this
+# value to get additional trace output.
+#
+cdl_option CYGNUM_LIBC_RAND_TRACE_LEVEL {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to 1
+};
+
+# Simplest implementation
+# This provides a very simple implementation of rand()
+# that does not perform well with randomness in the
+# lower significant bits. However it is exceptionally
+# fast. It uses the sample algorithm from the ISO C
+# standard itself.
+#
+cdl_option CYGIMP_LIBC_RAND_SIMPLEST {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Simple implementation #1
+# This provides a very simple implementation of rand()
+# based on the simplest implementation above. However
+# it does try to work around the lack of randomness
+# in the lower significant bits, at the expense of a
+# little speed.
+#
+cdl_option CYGIMP_LIBC_RAND_SIMPLE1 {
+ # Flavor: bool
+ user_value 0
+ # value_source user
+ # Default value: 1
+};
+
+# Knuth implementation #1
+# This implements a slightly more complex algorithm
+# published in Donald E. Knuth's Art of Computer
+# Programming Vol.2 section 3.6 (p.185 in the 3rd ed.).
+# This produces better random numbers than the
+# simplest approach but is slower.
+#
+cdl_option CYGIMP_LIBC_RAND_KNUTH1 {
+ # Flavor: bool
+ user_value 1
+ # value_source user
+ # Default value: 0
+};
+
+# <
+# Provides strtod()
+# This option allows use of the utility function
+# strtod() (and consequently atof()) to convert
+# from string to double precision floating point
+# numbers. Disabling this option removes the
+# dependency on the math library package.
+#
+cdl_option CYGFUN_LIBC_strtod {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0 != CYGPKG_LIBM
+ # CYGPKG_LIBM (unknown) == 0
+ # --> 0
+ # Requires: CYGPKG_LIBM
+ # CYGPKG_LIBM (unknown) == 0
+ # --> 0
+};
+
+# Provides long long conversion functions
+# Enabling this option will provide support for the strtoll(),
+# strtoull() and atoll() conversion functions, which are
+# the long long variants of the standard versions of these
+# functions. Supporting this requires extra code and compile
+# time.
+#
+cdl_option CYGFUN_LIBC_STDLIB_CONV_LONGLONG {
+ # Flavor: bool
+ user_value 0
+ # value_source user
+ # Default value: 1
+};
+
+# bsearch() tracing level
+# Trace verbosity level for debugging the <stdlib.h>
+# binary search function bsearch(). Increase this
+# value to get additional trace output.
+#
+cdl_option CYGNUM_LIBC_BSEARCH_TRACE_LEVEL {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to 1
+};
+
+# qsort() tracing level
+# Trace verbosity level for debugging the <stdlib.h>
+# quicksort function qsort(). Increase this value
+# to get additional trace output.
+#
+cdl_option CYGNUM_LIBC_QSORT_TRACE_LEVEL {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to 1
+};
+
+# C library stdlib build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_LIBC_STDLIB_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_LIBC_STDLIB_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-fno-rtti -Woverloaded-virtual"
+ # value_source default
+ # Default value: "-fno-rtti -Woverloaded-virtual"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_LIBC_STDLIB_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wno-pointer-sign
+ # value_source default
+ # Default value: -Wno-pointer-sign
+};
+
+# C library stdlib tests
+# This option specifies the set of tests for this package.
+#
+cdl_option CYGPKG_LIBC_STDLIB_TESTS {
+ # Calculated value: "tests/abs tests/atoi tests/atol tests/bsearch tests/div tests/getenv tests/labs tests/ldiv tests/qsort tests/rand1 tests/rand2 tests/rand3 tests/rand4 tests/srand tests/strtol tests/strtoul"
+ # Flavor: data
+ # Current_value: tests/abs tests/atoi tests/atol tests/bsearch tests/div tests/getenv tests/labs tests/ldiv tests/qsort tests/rand1 tests/rand2 tests/rand3 tests/rand4 tests/srand tests/strtol tests/strtoul
+};
+
+# <
+# <
+# <
+# eCos HAL
+# doc: ref/the-ecos-hardware-abstraction-layer.html
+# The eCos HAL package provide a porting layer for
+# higher-level parts of the system such as the kernel and the
+# C library. Each installation should have HAL packages for
+# one or more architectures, and for each architecture there
+# may be one or more supported platforms. It is necessary to
+# select one target architecture and one platform for that
+# architecture. There are also a number of configuration
+# options that are common to all HAL packages.
+#
+cdl_package CYGPKG_HAL {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGPKG_INFRA
+ # CYGPKG_INFRA == current
+ # --> 1
+
+ # The following properties are affected by this value
+};
+
+# >
+# Platform-independent HAL options
+# A number of configuration options are common to most or all
+# HAL packages, for example options controlling how much state
+# should be saved during a context switch. The implementations
+# of these options will vary from architecture to architecture.
+#
+cdl_component CYGPKG_HAL_COMMON {
+ # There is no associated value.
+};
+
+# >
+# Provide eCos kernel support
+# The HAL can be configured to either support the full eCos
+# kernel, or to support only very simple applications which do
+# not require a full kernel. If kernel support is not required
+# then some of the startup, exception, and interrupt handling
+# code can be eliminated.
+#
+cdl_option CYGFUN_HAL_COMMON_KERNEL_SUPPORT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+ # Requires: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+};
+
+# HAL exception support
+# When a processor exception occurs, for example an attempt to
+# execute an illegal instruction or to perform a divide by
+# zero, this exception may be handled in a number of different
+# ways. If the target system has gdb support then typically
+# the exception will be handled by gdb code. Otherwise if the
+# HAL exception support is enabled then the HAL will invoke a
+# routine deliver_exception(). Typically this routine will be
+# provided by the eCos kernel, but it is possible for
+# application code to provide its own implementation. If the
+# HAL exception support is not enabled and a processor
+# exception occurs then the behaviour of the system is
+# undefined.
+#
+cdl_option CYGPKG_HAL_EXCEPTIONS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGPKG_KERNEL_EXCEPTIONS
+ # CYGPKG_KERNEL_EXCEPTIONS (unknown) == 0
+ # --> 0
+ # Requires: CYGPKG_KERNEL_EXCEPTIONS
+ # CYGPKG_KERNEL_EXCEPTIONS (unknown) == 0
+ # --> 0
+};
+
+# Stop calling constructors early
+# This option supports environments where some constructors
+# must be run in the context of a thread rather than at
+# simple system startup time. A boolean flag named
+# cyg_hal_stop_constructors is set to 1 when constructors
+# should no longer be invoked. It is up to some other
+# package to deal with the rest of the constructors.
+# In the current version this is only possible with the
+# C library.
+#
+cdl_option CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGSEM_LIBC_INVOKE_DEFAULT_STATIC_CONSTRUCTORS
+ # CYGSEM_LIBC_INVOKE_DEFAULT_STATIC_CONSTRUCTORS (unknown) == 0
+ # --> 0
+};
+
+# HAL uses the MMU and allows for CDL manipulation of it's use
+#
+cdl_interface CYGINT_HAL_SUPPORTS_MMU_TABLES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_INSTALL_MMU_TABLES
+ # ActiveIf: CYGINT_HAL_SUPPORTS_MMU_TABLES
+};
+
+# Install MMU tables.
+# This option controls whether this application installs
+# its own Memory Management Unit (MMU) tables, or relies on the
+# existing environment to run.
+#
+cdl_option CYGSEM_HAL_INSTALL_MMU_TABLES {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_HAL_SUPPORTS_MMU_TABLES
+ # CYGINT_HAL_SUPPORTS_MMU_TABLES == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYG_HAL_STARTUP != "RAM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_STATIC_MMU_TABLES
+ # Requires: CYGSEM_HAL_INSTALL_MMU_TABLES
+};
+
+# Use static MMU tables.
+# This option defines an environment where any Memory
+# Management Unit (MMU) tables are constant. Normally used by ROM
+# based environments, this provides a way to save RAM usage which
+# would otherwise be required for these tables.
+#
+cdl_option CYGSEM_HAL_STATIC_MMU_TABLES {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGSEM_HAL_INSTALL_MMU_TABLES
+ # CYGSEM_HAL_INSTALL_MMU_TABLES == 0
+ # --> 0
+};
+
+# Route diagnostic output to debug channel
+# If not inheriting the console setup from the ROM monitor,
+# it is possible to redirect diagnostic output to the debug
+# channel by enabling this option. Depending on the debugger
+# used it may also be necessary to select a mangler for the
+# output to be displayed by the debugger.
+#
+cdl_component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN {
+ # ActiveIf constraint: !CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE == 0
+ # --> 1
+ # ActiveIf constraint: CYGPKG_HAL_ARM || CYGPKG_HAL_POWERPC_MPC8xx || CYGPKG_HAL_V85X_V850 || CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+ # CYGPKG_HAL_ARM == current
+ # CYGPKG_HAL_POWERPC_MPC8xx (unknown) == 0
+ # CYGPKG_HAL_V85X_V850 (unknown) == 0
+ # CYGSEM_HAL_VIRTUAL_VECTOR_DIAG == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: (CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS || CYG_HAL_STARTUP == "RAM") ? 1 : 0
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 0
+
+ # The following properties are affected by this value
+ # option CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ # Calculated: !CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE && !CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+};
+
+# >
+# Mangler used on diag output
+# It is sometimes necessary to mangle (encode) the
+# diag ASCII text output in order for it to show up at the
+# other end. In particular, GDB may silently ignore raw
+# ASCII text.
+#
+cdl_option CYGSEM_HAL_DIAG_MANGLER {
+ # This option is not active
+ # The parent CYGDBG_HAL_DIAG_TO_DEBUG_CHAN is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value GDB
+ # value_source default
+ # Default value: GDB
+ # Legal values: "GDB" "None"
+};
+
+# <
+# <
+# HAL interrupt handling
+# A number of configuration options related to interrupt
+# handling are common to most or all HAL packages, even though
+# the implementations will vary from architecture to
+# architecture.
+#
+cdl_component CYGPKG_HAL_COMMON_INTERRUPTS {
+ # There is no associated value.
+};
+
+# >
+# Use separate stack for interrupts
+# When an interrupt occurs this interrupt can be handled either
+# on the current stack or on a separate stack maintained by the
+# HAL. Using a separate stack requires a small number of extra
+# instructions in the interrupt handling code, but it has the
+# advantage that it is no longer necessary to allow extra space
+# in every thread stack for the interrupt handlers. The amount
+# of extra space required depends on the interrupt handlers
+# that are being used.
+#
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # package CYGPKG_REDBOOT
+ # Requires: CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK == 0
+};
+
+# Interrupt stack size
+# This configuration option specifies the stack size in bytes
+# for the interrupt stack. Typically this should be a multiple
+# of 16, but the exact requirements will vary from architecture
+# to architecture. The interrupt stack serves two separate
+# purposes. It is used as the stack during system
+# initialization. In addition, if the interrupt system is
+# configured to use a separate stack then all interrupts will
+# be processed on this stack. The exact memory requirements
+# will vary from application to application, and will depend
+# heavily on whether or not other interrupt-related options,
+# for example nested interrupts, are enabled. On most targets,
+# in a configuration with no kernel this stack will also be
+# the stack used to invoke the application, and must obviously
+# be appropriately large in that case.
+#
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 32768
+ # value_source default
+ # Default value: CYGPKG_KERNEL ? 4096 : 32768
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 32768
+ # Legal values: 128 to 1048576
+};
+
+# Allow nested interrupts
+# When an interrupt occurs the HAL interrupt handling code can
+# either leave interrupts disabled for the duration of the
+# interrupt handling code, or by doing some extra work it can
+# reenable interrupts before invoking the interrupt handler and
+# thus allow nested interrupts to happen. If all the interrupt
+# handlers being used are small and do not involve any loops
+# then it is usually better to disallow nested interrupts.
+# However if any of the interrupt handlers are more complicated
+# than nested interrupts will usually be required.
+#
+cdl_option CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Save minimum context on interrupt
+# The HAL interrupt handling code can exploit the calling conventions
+# defined for a given architecture to reduce the amount of state
+# that has to be saved. Generally this improves performance and
+# reduces code size. However it can make source-level debugging
+# more difficult.
+#
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # Requires: ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+};
+
+# Chain all interrupts together
+# Interrupts can be attached to vectors either singly, or be
+# chained together. The latter is necessary if there is no way
+# of discovering which device has interrupted without
+# inspecting the device itself. It can also reduce the amount
+# of RAM needed for interrupt decoding tables and code.
+#
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Ignore spurious [fleeting] interrupts
+# On some hardware, interrupt sources may not be de-bounced or
+# de-glitched. Rather than try to handle these interrupts (no
+# handling may be possible), this option allows the HAL to simply
+# ignore them. In most cases, if the interrupt is real it will
+# reoccur in a detectable form.
+#
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# HAL context switch support
+# A number of configuration options related to thread contexts
+# are common to most or all HAL packages, even though the
+# implementations will vary from architecture to architecture.
+#
+cdl_component CYGPKG_HAL_COMMON_CONTEXT {
+ # There is no associated value.
+
+ # The following properties are affected by this value
+};
+
+# >
+# Use minimum thread context
+# The thread context switch code can exploit the calling
+# conventions defined for a given architecture to reduce the
+# amount of state that has to be saved during a context
+# switch. Generally this improves performance and reduces
+# code size. However it can make source-level debugging more
+# difficult.
+#
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # Requires: ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+};
+
+# <
+# Explicit control over cache behaviour
+# These options let the default behaviour of the caches
+# be easily configurable.
+#
+cdl_component CYGPKG_HAL_CACHE_CONTROL {
+ # There is no associated value.
+};
+
+# >
+# Enable DATA cache on startup
+# Enabling this option will cause the data cache to be enabled
+# as soon as practicable when eCos starts up. One would choose
+# to disable this if the data cache cannot safely be turned on,
+# such as a case where the cache(s) require additional platform
+# specific setup.
+#
+cdl_component CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# DATA cache mode on startup
+# This option controls the mode the cache will be set to
+# when enabled on startup.
+#
+cdl_option CYGSEM_HAL_DCACHE_STARTUP_MODE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value COPYBACK
+ # value_source default
+ # Default value: COPYBACK
+ # Legal values: "COPYBACK" "WRITETHRU"
+};
+
+# <
+# Enable INSTRUCTION cache on startup
+# Enabling this option will cause the instruction cache to be enabled
+# as soon as practicable when eCos starts up. One would choose
+# to disable this if the instruction cache cannot safely be turned on,
+# such as a case where the cache(s) require additional platform
+# specific setup.
+#
+cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Source-level debugging support
+# If the source level debugger gdb is to be used for debugging
+# application code then it may be necessary to configure in support
+# for this in the HAL.
+#
+cdl_component CYGPKG_HAL_DEBUG {
+ # There is no associated value.
+};
+
+# >
+# Support for GDB stubs
+# The HAL implements GDB stubs for the target.
+#
+cdl_interface CYGINT_HAL_DEBUG_GDB_STUBS {
+ # Implemented by CYGPKG_HAL_ARM_TX27KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # ActiveIf: CYGINT_HAL_DEBUG_GDB_STUBS
+ # option CYGBLD_BUILD_REDBOOT_WITH_GDB
+ # ActiveIf: CYGINT_HAL_DEBUG_GDB_STUBS
+};
+
+# Include GDB stubs in HAL
+# This option causes a set of GDB stubs to be included into the
+# system. On some target systems the GDB support will be
+# provided by other means, for example by a ROM monitor. On
+# other targets, especially when building a ROM-booting system,
+# the necessary support has to go into the target library
+# itself. When GDB stubs are include in a configuration, HAL
+# serial drivers must also be included.
+#
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ # ActiveIf constraint: CYGINT_HAL_DEBUG_GDB_STUBS
+ # CYGINT_HAL_DEBUG_GDB_STUBS == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 0
+ # Requires: ! CYGSEM_HAL_USE_ROM_MONITOR
+ # CYGSEM_HAL_USE_ROM_MONITOR == 0
+ # --> 1
+ # Requires: ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ # CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT == 0
+ # --> 1
+ # Requires: ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ # CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM == 0
+ # --> 1
+ # Requires: !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # CYGSEM_HAL_VIRTUAL_VECTOR_DIAG == 1
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # DefaultValue: (CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS || CYG_HAL_STARTUP == "RAM") ? 1 : 0
+ # option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # DefaultValue: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # ActiveIf: CYGSEM_HAL_USE_ROM_MONITOR || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # DefaultValue: !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGBLD_BUILD_COMMON_GDB_STUBS
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGPKG_HAL_GDB_FILEIO
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGHWR_HAL_ARM_DUMP_EXCEPTIONS
+ # Requires: !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGBLD_BUILD_REDBOOT_WITH_GDB
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+};
+
+# Support for external break support in GDB stubs
+# The HAL implements external break (or asynchronous interrupt)
+# in the GDB stubs for the target.
+#
+cdl_interface CYGINT_HAL_DEBUG_GDB_STUBS_BREAK {
+ # Implemented by CYGPKG_HAL_ARM_TX27KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # ActiveIf: CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+};
+
+# Include GDB external break support for stubs
+# This option causes the GDB stub to add a serial interrupt handler
+# which will listen for GDB break packets. This lets you stop the
+# target asynchronously when using GDB, usually by hitting Control+C
+# or pressing the STOP button. This option differs from
+# CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT in that it is used when
+# GDB stubs are present.
+#
+cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT {
+ # ActiveIf constraint: CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+ # CYGINT_HAL_DEBUG_GDB_STUBS_BREAK == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # Requires: !CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # option CYGOPT_HAL_ARM_SYSCALL_GPROF_SUPPORT
+ # ActiveIf: CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT || CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # option CYGBLD_BUILD_REDBOOT_WITH_GDB
+ # Requires: CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+};
+
+# Platform does not support CTRLC
+#
+cdl_interface CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # ActiveIf: CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED == 0
+};
+
+# Include GDB external break support when no stubs
+# This option adds an interrupt handler for the GDB serial line
+# which will listen for GDB break packets. This lets you stop the
+# target asynchronously when using GDB, usually by hitting Control+C
+# or pressing the STOP button. This option differs from
+# CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT in that it is used when the GDB
+# stubs are NOT present.
+#
+cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT {
+ # This option is not active
+ # ActiveIf constraint: CYGSEM_HAL_USE_ROM_MONITOR || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGSEM_HAL_USE_ROM_MONITOR == 0
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+ # ActiveIf constraint: CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED == 0
+ # CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED == 0
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 1
+ # Requires: !CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGOPT_HAL_ARM_SYSCALL_GPROF_SUPPORT
+ # ActiveIf: CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT || CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+};
+
+# Include GDB multi-threading debug support
+# This option enables some extra HAL code which is needed
+# to support multi-threaded source level debugging.
+#
+cdl_option CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT {
+ # ActiveIf constraint: CYGSEM_HAL_ROM_MONITOR || CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT
+ # CYGSEM_HAL_ROM_MONITOR == 1
+ # CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT (unknown) == 0
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT
+ # Requires: CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ # option CYGBLD_BUILD_REDBOOT_WITH_THREADS
+ # Requires: CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+};
+
+# Number of times to retry sending a $O packet
+# This option controls the number of attempts that eCos programs
+# will make to send a $O packet to a host GDB process. If it is
+# set non-zero, then the target process will attempt to resend the
+# $O packet data up to this number of retries. Caution: use of
+# this option is not recommended as it can thoroughly confuse the
+# host GDB process.
+#
+cdl_option CYGNUM_HAL_DEBUG_GDB_PROTOCOL_RETRIES {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Timeout period for GDB packets
+# This option controls the time (in milliseconds) that eCos programs
+# will wait for a response when sending packets to a host GDB process.
+# If this time elapses, then the packet will be resent, up to some
+# maximum number of times (CYGNUM_HAL_DEBUG_GDB_PROTOCOL_RETRIES).
+#
+cdl_option CYGNUM_HAL_DEBUG_GDB_PROTOCOL_TIMEOUT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 500
+ # value_source default
+ # Default value: 500
+};
+
+# Location of CRC32 table
+# The stubs use a 1 kilobyte CRC table that can either be pregenerated
+# and placed in ROM, or generated at runtime in RAM. Depending on
+# your memory constraints, one of these options may be better.
+#
+cdl_option CYGDBG_HAL_CRCTABLE_LOCATION {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value RAM
+ # value_source default
+ # Default value: RAM
+ # Legal values: "ROM" "RAM"
+};
+
+# <
+# ROM monitor support
+# Support for ROM monitors can be built in to your application.
+# It may also be relevant to build your application as a ROM monitor
+# itself. Such options are contained here if relevant for your chosen
+# platform. The options and ROM monitors available to choose are
+# platform-dependent.
+#
+cdl_component CYGPKG_HAL_ROM_MONITOR {
+ # There is no associated value.
+
+ # The following properties are affected by this value
+};
+
+# >
+# Target has virtual vector support
+#
+cdl_interface CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT {
+ # Implemented by CYGPKG_HAL_ARM_TX27KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # component CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+ # ActiveIf: CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+};
+
+# Target supports baud rate control via vectors
+# Whether this target supports the __COMMCTL_GETBAUD
+# and __COMMCTL_SETBAUD virtual vector comm control operations.
+#
+cdl_interface CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT {
+ # Implemented by CYGPKG_HAL_ARM_MX27, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_VARIABLE_BAUD_RATE
+ # ActiveIf: CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+};
+
+# Enable use of virtual vector calling interface
+# Virtual vector support allows the HAL to let the ROM
+# monitor handle certain operations. The virtual vector table
+# defines a calling interface between applications running in
+# RAM and the ROM monitor.
+#
+cdl_component CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT {
+ # ActiveIf constraint: CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+ # CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT == 1
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+
+ # The following properties are affected by this value
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+ # package CYGPKG_DEVS_ETH_PHY
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+};
+
+# >
+# Inherit console settings from ROM monitor
+# When this option is set, the application will inherit
+# the console as set up by the ROM monitor. This means
+# that the application will use whatever channel and
+# mangling style was used by the ROM monitor when
+# the application was launched.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE {
+ # This option is not active
+ # ActiveIf constraint: CYGSEM_HAL_USE_ROM_MONITOR
+ # CYGSEM_HAL_USE_ROM_MONITOR == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: !CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS == 1
+ # --> 0
+
+ # The following properties are affected by this value
+ # component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # ActiveIf: !CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE
+ # option CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ # Calculated: !CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE && !CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+};
+
+# Debug channel is configurable
+# This option is a configuration hint - it is enabled
+# when the HAL initialization code will make use
+# of the debug channel configuration option.
+#
+cdl_option CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE {
+ # Calculated value: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS == 1
+ # Flavor: bool
+ # Current value: 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+ # ActiveIf: CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+};
+
+# Console channel is configurable
+# This option is a configuration hint - it is enabled
+# when the HAL initialization code will make use
+# of the console channel configuration option.
+#
+cdl_option CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE {
+ # Calculated value: !CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE && !CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE == 0
+ # CYGDBG_HAL_DIAG_TO_DEBUG_CHAN == 0
+ # Flavor: bool
+ # Current value: 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL
+ # ActiveIf: CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+};
+
+# Initialize whole of virtual vector table
+# This option will cause the whole of the virtual
+# vector table to be initialized with dummy values on
+# startup. When this option is enabled, all the
+# options below must also be enabled - or the
+# table would be empty when the application
+# launches.
+# On targets where older ROM monitors without
+# virtual vector support may still be in use, it is
+# necessary for RAM applictions to initialize the
+# table (since all HAL diagnostics and debug IO
+# happens via the table).
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYG_HAL_STARTUP != "RAM" || !CYGSEM_HAL_USE_ROM_MONITOR
+ # CYG_HAL_STARTUP == ROMRAM
+ # CYGSEM_HAL_USE_ROM_MONITOR == 0
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET == 1
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US == 1
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE == 1
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA == 1
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # ActiveIf: !CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_VERSION
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+};
+
+# Claim virtual vector table entries by default
+# By default most virtual vectors will be claimed by
+# RAM startup configurations, meaning that the RAM
+# application will provide the services. The
+# exception is COMMS support (HAL
+# diagnostics/debugging IO) which is left in the
+# control of the ROM monitor.
+# The reasoning behind this is to get as much of the
+# code exercised during regular development so it
+# is known to be working the few times a new ROM
+# monitor or a ROM production configuration is used
+# - COMMS are excluded only by necessity in order to
+# avoid breaking an existing debugger connections
+# (there may be ways around this).
+# For production RAM configurations this option can
+# be switched off, causing the appliction to rely on
+# the ROM monitor for these services, thus
+# saving some space.
+# Individual vectors may also be left unclaimed,
+# controlled by the below options (meaning that the
+# associated service provided by the ROM monitor
+# will be used).
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT {
+ # This option is not active
+ # ActiveIf constraint: !CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+};
+
+# Claim reset virtual vectors
+# This option will cause the reset and kill_by_reset
+# virtual vectors to be claimed.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET
+};
+
+# Claim version virtual vectors
+# This option will cause the version
+# virtual vectors to be claimed.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_VERSION {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # --> 1
+};
+
+# Claim delay_us virtual vector
+# This option will cause the delay_us
+# virtual vector to be claimed.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US
+};
+
+# Claim cache virtual vectors
+# This option will cause the cache virtual vectors
+# to be claimed.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE
+};
+
+# Claim data virtual vectors
+# This option will cause the data virtual vectors
+# to be claimed. At present there is only one, used
+# by the RedBoot ethernet driver to share diag output.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA
+};
+
+# Claim comms virtual vectors
+# This option will cause the communication tables
+# that are part of the virtual vectors mechanism to
+# be claimed. Note that doing this may cause an
+# existing ROM monitor communication connection to
+# be closed. For this reason, the option is disabled
+# per default for normal application
+# configurations.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # Requires: !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE
+ # DefaultValue: !CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # option CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ # Calculated: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+};
+
+# Do diagnostic IO via virtual vector table
+# All HAL IO happens via the virtual vector table / comm
+# tables when those tables are supported by the HAL.
+# If so desired, the low-level IO functions can
+# still be provided by the RAM application by
+# enabling the CLAIM_COMMS option.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_DIAG {
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+
+ # The following properties are affected by this value
+ # component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # ActiveIf: CYGPKG_HAL_ARM || CYGPKG_HAL_POWERPC_MPC8xx || CYGPKG_HAL_V85X_V850 || CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # Requires: !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+};
+
+# <
+# Behave as a ROM monitor
+# Enable this option if this program is to be used as a ROM monitor,
+# i.e. applications will be loaded into RAM on the TX27 module, and this
+# ROM monitor may process exceptions or interrupts generated from the
+# application. This enables features such as utilizing a separate
+# interrupt stack when exceptions are generated.
+#
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+ # Requires: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGBLD_ARM_ENABLE_THUMB_INTERWORK
+ # DefaultValue: (CYGHWR_THUMB || CYGSEM_HAL_ROM_MONITOR)
+ # option CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ # ActiveIf: CYGSEM_HAL_ROM_MONITOR || CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT
+ # option CYGPRI_REDBOOT_ROM_MONITOR
+ # Requires: CYGSEM_HAL_ROM_MONITOR
+};
+
+# Work with a ROM monitor
+# Support can be enabled for different varieties of ROM monitor.
+# This support changes various eCos semantics such as the encoding
+# of diagnostic output, or the overriding of hardware interrupt
+# vectors.
+# Firstly there is "Generic" support which prevents the HAL
+# from overriding the hardware vectors that it does not use, to
+# instead allow an installed ROM monitor to handle them. This is
+# the most basic support which is likely to be common to most
+# implementations of ROM monitor.
+# "GDB_stubs" provides support when GDB stubs are included in
+# the ROM monitor or boot ROM.
+#
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 0 0
+ # Legal values: "Generic" "GDB_stubs"
+ # Requires: CYG_HAL_STARTUP == "RAM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 0
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # Requires: ! CYGSEM_HAL_USE_ROM_MONITOR
+ # option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # ActiveIf: CYGSEM_HAL_USE_ROM_MONITOR || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE
+ # ActiveIf: CYGSEM_HAL_USE_ROM_MONITOR
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # DefaultValue: CYG_HAL_STARTUP != "RAM" || !CYGSEM_HAL_USE_ROM_MONITOR
+};
+
+# <
+# Platform defined I/O channels.
+# Platforms which provide additional I/O channels can implement
+# this interface, indicating that the function plf_if_init()
+# needs to be called.
+#
+cdl_interface CYGINT_HAL_PLF_IF_INIT {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+};
+
+# Platform IDE I/O support.
+# Platforms which provide IDE controllers can implement
+# this interface, indicating that IDE I/O macros are
+# available.
+#
+cdl_interface CYGINT_HAL_PLF_IF_IDE {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # component CYGSEM_REDBOOT_DISK_IDE
+ # ActiveIf: CYGINT_HAL_PLF_IF_IDE != 0
+};
+
+# File I/O operations via GDB
+# This option enables support for various file I/O
+# operations using the GDB remote protocol to communicate
+# with GDB. The operations are then performed on the
+# debugging host by proxy. These operations are only
+# currently available by using a system call interface
+# to RedBoot. This may change in the future.
+#
+cdl_option CYGPKG_HAL_GDB_FILEIO {
+ # This option is not active
+ # ActiveIf constraint: CYGSEM_REDBOOT_BSP_SYSCALLS
+ # CYGSEM_REDBOOT_BSP_SYSCALLS == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+};
+
+# Build Compiler sanity checking tests
+# Enabling this option causes compiler tests to be built.
+#
+cdl_option CYGPKG_HAL_BUILD_COMPILER_TESTS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # component CYGPKG_HAL_TESTS
+ # Calculated: "tests/context tests/basic"
+ # . ((!CYGINT_HAL_TESTS_NO_CACHES) ? " tests/cache" : "")
+ # . ((CYGPKG_HAL_BUILD_COMPILER_TESTS) ? " tests/cpp1 tests/vaargs" : "")
+ # . ((!CYGVAR_KERNEL_COUNTERS_CLOCK) ? " tests/intr" : "")
+};
+
+# Common HAL tests
+# This option specifies the set of tests for the common HAL.
+#
+cdl_component CYGPKG_HAL_TESTS {
+ # Calculated value: "tests/context tests/basic"
+ # . ((!CYGINT_HAL_TESTS_NO_CACHES) ? " tests/cache" : "")
+ # . ((CYGPKG_HAL_BUILD_COMPILER_TESTS) ? " tests/cpp1 tests/vaargs" : "")
+ # . ((!CYGVAR_KERNEL_COUNTERS_CLOCK) ? " tests/intr" : "")
+ # CYGINT_HAL_TESTS_NO_CACHES == 0
+ # CYGPKG_HAL_BUILD_COMPILER_TESTS == 0
+ # CYGVAR_KERNEL_COUNTERS_CLOCK (unknown) == 0
+ # Flavor: data
+ # Current_value: tests/context tests/basic tests/cache tests/intr
+};
+
+# >
+# Interface for cache presence
+# Some architectures and/or platforms do not have caches. By
+# implementing this interface, these can disable the various
+# cache-related tests.
+#
+cdl_interface CYGINT_HAL_TESTS_NO_CACHES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+
+ # The following properties are affected by this value
+ # component CYGPKG_HAL_TESTS
+ # Calculated: "tests/context tests/basic"
+ # . ((!CYGINT_HAL_TESTS_NO_CACHES) ? " tests/cache" : "")
+ # . ((CYGPKG_HAL_BUILD_COMPILER_TESTS) ? " tests/cpp1 tests/vaargs" : "")
+ # . ((!CYGVAR_KERNEL_COUNTERS_CLOCK) ? " tests/intr" : "")
+};
+
+# <
+# ARM architecture
+# The ARM architecture HAL package provides generic
+# support for this processor architecture. It is also
+# necessary to select a specific target platform HAL
+# package.
+#
+cdl_package CYGPKG_HAL_ARM {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # ActiveIf: CYGPKG_HAL_ARM || CYGPKG_HAL_POWERPC_MPC8xx || CYGPKG_HAL_V85X_V850 || CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+ # interface CYGINT_REDBOOT_ARM_FLASH_SIB_SUPPORTED
+ # ActiveIf: CYGPKG_HAL_ARM
+};
+
+# >
+# The CPU architecture supports THUMB mode
+#
+cdl_interface CYGINT_HAL_ARM_THUMB_ARCH {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_THUMB
+ # ActiveIf: CYGINT_HAL_ARM_THUMB_ARCH != 0
+ # option CYGBLD_ARM_ENABLE_THUMB_INTERWORK
+ # ActiveIf: CYGINT_HAL_ARM_THUMB_ARCH != 0
+};
+
+# Enable Thumb instruction set
+# Enable use of the Thumb instruction set.
+#
+cdl_option CYGHWR_THUMB {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_HAL_ARM_THUMB_ARCH != 0
+ # CYGINT_HAL_ARM_THUMB_ARCH == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGBLD_ARM_ENABLE_THUMB_INTERWORK
+ # DefaultValue: (CYGHWR_THUMB || CYGSEM_HAL_ROM_MONITOR)
+};
+
+# Enable Thumb interworking compiler option
+# This option controls the use of -mthumb-interwork in the
+# compiler flags. It defaults enabled in Thumb or ROM monitor
+# configurations, but can be overridden for reduced memory
+# footprint where interworking is not a requirement.
+#
+cdl_option CYGBLD_ARM_ENABLE_THUMB_INTERWORK {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_HAL_ARM_THUMB_ARCH != 0
+ # CYGINT_HAL_ARM_THUMB_ARCH == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: (CYGHWR_THUMB || CYGSEM_HAL_ROM_MONITOR)
+ # CYGHWR_THUMB == 0
+ # CYGSEM_HAL_ROM_MONITOR == 1
+ # --> 1
+};
+
+# The platform and architecture supports Big Endian operation
+#
+cdl_interface CYGINT_HAL_ARM_BIGENDIAN {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_BIGENDIAN
+ # ActiveIf: CYGINT_HAL_ARM_BIGENDIAN != 0
+};
+
+# Use big-endian mode
+# Use the CPU in big-endian mode.
+#
+cdl_option CYGHWR_HAL_ARM_BIGENDIAN {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_HAL_ARM_BIGENDIAN != 0
+ # CYGINT_HAL_ARM_BIGENDIAN == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# The platform uses a processor with an ARM7 core
+#
+cdl_interface CYGINT_HAL_ARM_ARCH_ARM7 {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # LegalValues: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" : ""
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" : ""
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" : ""
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" : ""
+ # ""
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # DefaultValue: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" :
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" :
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" :
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" :
+ # "unknown"
+};
+
+# The platform uses a processor with an ARM9 core
+#
+cdl_interface CYGINT_HAL_ARM_ARCH_ARM9 {
+ # Implemented by CYGPKG_HAL_ARM_MX27, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # LegalValues: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" : ""
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" : ""
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" : ""
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" : ""
+ # ""
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # DefaultValue: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" :
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" :
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" :
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" :
+ # "unknown"
+};
+
+# The platform uses a processor with a StrongARM core
+#
+cdl_interface CYGINT_HAL_ARM_ARCH_STRONGARM {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # LegalValues: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" : ""
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" : ""
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" : ""
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" : ""
+ # ""
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # DefaultValue: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" :
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" :
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" :
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" :
+ # "unknown"
+};
+
+# The platform uses a processor with a XScale core
+#
+cdl_interface CYGINT_HAL_ARM_ARCH_XSCALE {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # LegalValues: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" : ""
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" : ""
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" : ""
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" : ""
+ # ""
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # DefaultValue: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" :
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" :
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" :
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" :
+ # "unknown"
+};
+
+# ARM CPU family
+# It is possible to optimize code for different
+# ARM CPU families. This option selects which CPU to
+# optimize for on boards that support multiple CPU types.
+#
+cdl_option CYGHWR_HAL_ARM_CPU_FAMILY {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ARM9
+ # value_source default
+ # Default value: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" :
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" :
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" :
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" :
+ # "unknown"
+ # CYGINT_HAL_ARM_ARCH_ARM7 == 0
+ # CYGINT_HAL_ARM_ARCH_ARM9 == 1
+ # CYGINT_HAL_ARM_ARCH_STRONGARM == 0
+ # CYGINT_HAL_ARM_ARCH_XSCALE == 0
+ # --> ARM9
+ # Legal values: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" : ""
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" : ""
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" : ""
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" : ""
+ # ""
+ # CYGINT_HAL_ARM_ARCH_ARM7 == 0
+ # CYGINT_HAL_ARM_ARCH_ARM9 == 1
+ # CYGINT_HAL_ARM_ARCH_STRONGARM == 0
+ # CYGINT_HAL_ARM_ARCH_XSCALE == 0
+};
+
+# Provide diagnostic dump for exceptions
+# Print messages about hardware exceptions, including
+# raw exception frame dump and register contents.
+#
+cdl_option CYGHWR_HAL_ARM_DUMP_EXCEPTIONS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 1
+};
+
+# Process all exceptions with the eCos application
+# Normal RAM-based programs which do not include GDB stubs
+# defer processing of the illegal instruction exception to GDB.
+# Setting this options allows the program to explicitly handle
+# the illegal instruction exception itself. Note: this will
+# prevent the use of GDB to debug the application as breakpoints
+# will no longer work.
+#
+cdl_option CYGIMP_HAL_PROCESS_ALL_EXCEPTIONS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Support GDB thread operations via ICE/Multi-ICE
+# Allow GDB to get thread information via the ICE/Multi-ICE
+# connection.
+#
+cdl_option CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT == 1
+ # --> 1
+ # Requires: CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT
+ # CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT (unknown) == 0
+ # --> 0
+};
+
+# Support for 'gprof' callbacks
+# The ARM HAL provides the macro for 'gprof' callbacks from RedBoot
+# to acquire the interrupt-context PC and SP, when this option is
+# active.
+#
+cdl_option CYGOPT_HAL_ARM_SYSCALL_GPROF_SUPPORT {
+ # This option is not active
+ # ActiveIf constraint: CYGSEM_REDBOOT_BSP_SYSCALLS
+ # CYGSEM_REDBOOT_BSP_SYSCALLS == 0
+ # --> 0
+ # ActiveIf constraint: CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT || CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT == 0
+ # CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT == 0
+ # --> 0
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+};
+
+# Accept exceptions and irq's occurring in user mode
+# For standalone Redboot based programs running in user mode.
+#
+cdl_option CYGOPT_HAL_ARM_WITH_USER_MODE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Preserve svc spsr before returning to svc mode
+# This option secures exception and breakpoint processing
+# triggered during execution of application specific SWI
+# handlers.
+#
+cdl_option CYGOPT_HAL_ARM_PRESERVE_SVC_SPSR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Linker script
+#
+cdl_option CYGBLD_LINKER_SCRIPT {
+ # Calculated value: "src/arm.ld"
+ # Flavor: data
+ # Current_value: src/arm.ld
+};
+
+# Implementations of hal_arm_mem_real_region_top()
+#
+cdl_interface CYGINT_HAL_ARM_MEM_REAL_REGION_TOP {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+};
+
+# Freescale SoC architecture
+# This HAL variant package provides generic
+# support for the Freescale SoC. It is also
+# necessary to select a specific target platform HAL
+# package.
+#
+cdl_package CYGPKG_HAL_ARM_MX27 {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+};
+
+# >
+# PLL base clock
+# The processor can run at various frequencies.
+# These values are expressed in KHz. Note that there are
+# several steppings of the rate to run at different
+# maximum frequencies. Check the specs to make sure that your
+# particular processor can run at the rate you select here.
+#
+cdl_option CYGHWR_HAL_ARM_SOC_PLL_REF_CLOCK {
+ # Flavor: data
+ user_value 33554432
+ # value_source user
+ # Default value: 26000000
+ # Legal values: 26000000 27000000 33554432 32768000
+};
+
+# Processor clock rate
+# The processor can run at various frequencies.
+# These values are expressed in KHz. Note that there are
+# several steppings of the rate to run at different
+# maximum frequencies. Check the specs to make sure that your
+# particular processor can run at the rate you select here.
+#
+cdl_option CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 399
+ # value_source default
+ # Default value: CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT ?
+ # CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT : 399
+ # CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT (unknown) == 0
+ # CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT (unknown) == 0
+ # --> 399
+ # Legal values: 266 399
+};
+
+# System clock (hclk) rate
+# The processor can run at various frequencies.
+# These values are expressed in KHz. Note that there are
+# several steppings of the rate to run at different
+# maximum frequencies. Check the specs to make sure that your
+# particular processor can run at the rate you select here.
+#
+cdl_option CYGHWR_HAL_ARM_SOC_SYSTEM_CLOCK {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 133
+ # value_source default
+ # Default value: 133
+ # Legal values: 133 100
+};
+
+# Real-time clock constants
+#
+cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+ # There is no associated value.
+};
+
+# >
+# Real-time clock numerator
+#
+cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+ # Calculated value: 1000000000
+ # Flavor: data
+ # Current_value: 1000000000
+};
+
+# Real-time clock denominator
+# This option selects the heartbeat rate for the real-time clock.
+# The rate is specified in ticks per second. Change this value
+# with caution - too high and your system will become saturated
+# just handling clock interrupts, too low and some operations
+# such as thread scheduling may become sluggish.
+#
+cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 100
+ # value_source default
+ # Default value: 100
+
+ # The following properties are affected by this value
+ # option CYGNUM_HAL_RTC_PERIOD
+ # Calculated: (3686400/CYGNUM_HAL_RTC_DENOMINATOR)
+};
+
+# Real-time clock period
+#
+cdl_option CYGNUM_HAL_RTC_PERIOD {
+ # Calculated value: (3686400/CYGNUM_HAL_RTC_DENOMINATOR)
+ # CYGNUM_HAL_RTC_DENOMINATOR == 100
+ # Flavor: data
+ # Current_value: 36864
+};
+
+# <
+# UART1 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART1 {
+ # Implemented by CYGPKG_HAL_ARM_TX27KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+};
+
+# UART2 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART2 {
+ # Implemented by CYGPKG_HAL_ARM_TX27KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+};
+
+# UART3 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART3 {
+ # Implemented by CYGPKG_HAL_ARM_TX27KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+};
+
+# UART4 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART4 {
+ # Implemented by CYGPKG_HAL_ARM_TX27KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+};
+
+# UART5 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART5 {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+};
+
+# UART6 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART6 {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+};
+
+# Ka-Ro TX27 module
+# This HAL platform package provides generic
+# support for the Ka-Ro electronics TX27 module.
+#
+cdl_package CYGPKG_HAL_ARM_TX27KARO {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGINT_ISO_CTYPE
+ # CYGINT_ISO_CTYPE == 1
+ # --> 1
+ # Requires: CYGBLD_BUILD_REDBOOT == 1
+ # CYGBLD_BUILD_REDBOOT == 1
+ # --> 1
+};
+
+# >
+# Startup type
+# The only startup type allowed is ROMRAM, since this will allow
+# the program to exist in ROM, but be copied to RAM during startup
+# which is required to boot from NAND flash.
+#
+cdl_component CYG_HAL_STARTUP {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ROMRAM
+ # value_source default
+ # Default value: ROMRAM
+ # Legal values: "ROMRAM"
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_ROM_MONITOR
+ # Requires: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+ # option CYGSEM_HAL_ROM_MONITOR
+ # Requires: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+ # option CYGSEM_HAL_USE_ROM_MONITOR
+ # DefaultValue: CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0
+ # option CYGSEM_HAL_USE_ROM_MONITOR
+ # Requires: CYG_HAL_STARTUP == "RAM"
+ # option CYGSEM_HAL_INSTALL_MMU_TABLES
+ # DefaultValue: CYG_HAL_STARTUP != "RAM"
+ # component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # DefaultValue: (CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS || CYG_HAL_STARTUP == "RAM") ? 1 : 0
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # DefaultValue: CYG_HAL_STARTUP != "RAM" || !CYGSEM_HAL_USE_ROM_MONITOR
+ # option CYGBLD_BUILD_REDBOOT_WITH_THREADS
+ # ActiveIf: CYG_HAL_STARTUP != "RAM"
+ # option CYGPRI_REDBOOT_ROM_MONITOR
+ # ActiveIf: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+ # option CYGPRI_REDBOOT_ROM_MONITOR
+ # ActiveIf: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+};
+
+# Diagnostic serial port baud rate
+# This option selects the baud rate used for the console port.
+# Note: this should match the value chosen for the GDB port if the
+# console and GDB port are the same.
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 115200
+ # value_source default
+ # Default value: 115200
+ # Legal values: 9600 19200 38400 57600 115200
+};
+
+# GDB serial port baud rate
+# This option selects the baud rate used for the GDB port.
+# Note: this should match the value chosen for the console port if the
+# console and GDB port are the same.
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 115200
+ # value_source default
+ # Default value: 115200
+ # Legal values: 9600 19200 38400 57600 115200
+};
+
+# Number of communication channels on the TX27
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ # Calculated value: 3
+ # Flavor: data
+ # Current_value: 3
+
+ # The following properties are affected by this value
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+ # LegalValues: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ # LegalValues: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL
+ # LegalValues: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+};
+
+# Debug serial port
+# The TX27 provides access to three serial ports. This option
+# chooses which port will be used to connect to a host
+# running GDB.
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ # ActiveIf constraint: CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ # CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE == 1
+ # --> 1
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ # CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS == 3
+};
+
+# Default console channel.
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+ # Calculated value: 0
+ # Flavor: data
+ # Current_value: 0
+ # Legal values: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ # CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS == 3
+
+ # The following properties are affected by this value
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL
+ # DefaultValue: CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+};
+
+# Console serial port
+# The TX27 provides access to three serial ports. This option
+# chooses which port will be used for console output.
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ # ActiveIf constraint: CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ # CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE == 1
+ # --> 1
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ # CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT == 0
+ # --> 0
+ # Legal values: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ # CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS == 3
+};
+
+# Ka-Ro electronics TX27 module build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_HAL_ARM_TX27_OPTIONS {
+ # There is no associated value.
+ # Requires: CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0
+ # CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0
+ # --> 1
+};
+
+# >
+# SDRAM size
+# This option specifies the SDRAM size of the TX27 module.
+#
+cdl_option CYGNUM_HAL_ARM_TX27_SDRAM_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x04000000
+ # value_source default
+ # Default value: 0x04000000
+ # Legal values: 0x04000000 0x08000000
+};
+
+# Enable low level debugging with LED
+# This option enables low level debugging by blink codes
+# of the LED on STK5.
+#
+cdl_option CYGOPT_HAL_ARM_TX27_DEBUG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: false
+ # false (unknown) == 0
+ # --> 0
+};
+
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the TX27 HAL. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_HAL_ARM_TX27_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the TX27 HAL. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_HAL_ARM_TX27_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# <
+# Memory layout
+#
+cdl_component CYGHWR_MEMORY_LAYOUT {
+ # Calculated value: "arm_tx27_romram"
+ # Flavor: data
+ # Current_value: arm_tx27_romram
+};
+
+# >
+# Memory layout linker script fragment
+#
+cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ # Calculated value: "<pkgconf/mlt_arm_tx27_romram.ldi>"
+ # Flavor: data
+ # Current_value: <pkgconf/mlt_arm_tx27_romram.ldi>
+};
+
+# Memory layout header file
+#
+cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ # Calculated value: "<pkgconf/mlt_arm_tx27_romram.h>"
+ # Flavor: data
+ # Current_value: <pkgconf/mlt_arm_tx27_romram.h>
+};
+
+# <
+# <
+# <
+# <
+# <
+# Infrastructure
+# Common types and useful macros.
+# Tracing and assertion facilities.
+# Package startup options.
+#
+cdl_package CYGPKG_INFRA {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # package CYGPKG_HAL
+ # Requires: CYGPKG_INFRA
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGPKG_INFRA
+};
+
+# >
+# Asserts & Tracing
+# The eCos source code contains a significant amount of
+# internal debugging support, in the form of assertions and
+# tracing.
+# Assertions check at runtime that various conditions are as
+# expected; if not, execution is halted.
+# Tracing takes the form of text messages that are output
+# whenever certain events occur, or whenever functions are
+# called or return.
+# The most important property of these checks and messages is
+# that they are not required for the program to run.
+# It is prudent to develop software with assertions enabled,
+# but disable them when making a product release, thus
+# removing the overhead of that checking.
+# It is possible to enable assertions and tracing
+# independently.
+# There are also options controlling the exact behaviour of
+# the assertion and tracing facilities, thus giving users
+# finer control over the code and data size requirements.
+#
+cdl_component CYGPKG_INFRA_DEBUG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGNUM_INFRA_EMPTY_DELETE_THRESHOLD
+ # ActiveIf: CYGPKG_INFRA_DEBUG
+};
+
+# >
+# Use asserts
+# If this option is defined, asserts in the code are tested.
+# Assert functions (CYG_ASSERT()) are defined in
+# 'include/cyg/infra/cyg_ass.h' within the 'install' tree.
+# If it is not defined, these result in no additional
+# object code and no checking of the asserted conditions.
+#
+cdl_component CYGDBG_USE_ASSERTS {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: 1 == CYGINT_INFRA_DEBUG_TRACE_IMPL
+ # CYGINT_INFRA_DEBUG_TRACE_IMPL == 0
+ # --> 0
+
+ # The following properties are affected by this value
+ # option CYGDBG_MEMALLOC_ALLOCATOR_DLMALLOC_DEBUG
+ # Requires: CYGDBG_USE_ASSERTS
+ # option CYGDBG_MEMALLOC_ALLOCATOR_DLMALLOC_DEBUG
+ # DefaultValue: 0 != CYGDBG_USE_ASSERTS
+};
+
+# >
+# Preconditions
+# This option allows individual control of preconditions.
+# A precondition is one type of assert, which it is
+# useful to control separately from more general asserts.
+# The function is CYG_PRECONDITION(condition,msg).
+#
+cdl_option CYGDBG_INFRA_DEBUG_PRECONDITIONS {
+ # This option is not active
+ # The parent CYGDBG_USE_ASSERTS is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Postconditions
+# This option allows individual control of postconditions.
+# A postcondition is one type of assert, which it is
+# useful to control separately from more general asserts.
+# The function is CYG_POSTCONDITION(condition,msg).
+#
+cdl_option CYGDBG_INFRA_DEBUG_POSTCONDITIONS {
+ # This option is not active
+ # The parent CYGDBG_USE_ASSERTS is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Loop invariants
+# This option allows individual control of loop invariants.
+# A loop invariant is one type of assert, which it is
+# useful to control separately from more general asserts,
+# particularly since a loop invariant is typically evaluated
+# a great many times when used correctly.
+# The function is CYG_LOOP_INVARIANT(condition,msg).
+#
+cdl_option CYGDBG_INFRA_DEBUG_LOOP_INVARIANTS {
+ # This option is not active
+ # The parent CYGDBG_USE_ASSERTS is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Use assert text
+# All assertions within eCos contain a text message
+# which should give some information about the condition
+# being tested.
+# These text messages will end up being embedded in the
+# application image and hence there is a significant penalty
+# in terms of image size.
+# It is possible to suppress the use of these messages by
+# disabling this option.
+# This results in smaller code size, but there is less
+# human-readable information if an assertion actually gets
+# triggered.
+#
+cdl_option CYGDBG_INFRA_DEBUG_ASSERT_MESSAGE {
+ # This option is not active
+ # The parent CYGDBG_USE_ASSERTS is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Use tracing
+# If this option is defined, tracing operations
+# result in output or logging, depending on other options.
+# This may have adverse effects on performance, if the time
+# taken to output message overwhelms the available CPU
+# power or output bandwidth.
+# Trace functions (CYG_TRACE()) are defined in
+# 'include/cyg/infra/cyg_trac.h' within the 'install' tree.
+# If it is not defined, these result in no additional
+# object code and no trace information.
+#
+cdl_component CYGDBG_USE_TRACING {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: 1 == CYGINT_INFRA_DEBUG_TRACE_IMPL
+ # CYGINT_INFRA_DEBUG_TRACE_IMPL == 0
+ # --> 0
+
+ # The following properties are affected by this value
+ # option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_SIZE
+ # ActiveIf: CYGDBG_USE_TRACING
+ # option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_WRAP
+ # ActiveIf: CYGDBG_USE_TRACING
+ # option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_HALT
+ # ActiveIf: CYGDBG_USE_TRACING
+ # option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_PRINT
+ # ActiveIf: CYGDBG_USE_TRACING
+ # option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_PRINT_ON_ASSERT
+ # ActiveIf: CYGDBG_USE_TRACING
+};
+
+# >
+# Trace function reports
+# This option allows individual control of
+# function entry/exit tracing, independent of
+# more general tracing output.
+# This may be useful to remove clutter from a
+# trace log.
+#
+cdl_option CYGDBG_INFRA_DEBUG_FUNCTION_REPORTS {
+ # This option is not active
+ # The parent CYGDBG_USE_TRACING is not active
+ # The parent CYGDBG_USE_TRACING is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Use trace text
+# All trace calls within eCos contain a text message
+# which should give some information about the circumstances.
+# These text messages will end up being embedded in the
+# application image and hence there is a significant penalty
+# in terms of image size.
+# It is possible to suppress the use of these messages by
+# disabling this option.
+# This results in smaller code size, but there is less
+# human-readable information available in the trace output,
+# possibly only filenames and line numbers.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_MESSAGE {
+ # This option is not active
+ # The parent CYGDBG_USE_TRACING is not active
+ # The parent CYGDBG_USE_TRACING is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Trace output implementations
+#
+cdl_interface CYGINT_INFRA_DEBUG_TRACE_IMPL {
+ # Implemented by CYGDBG_INFRA_DEBUG_TRACE_ASSERT_NULL, inactive, disabled
+ # Implemented by CYGDBG_INFRA_DEBUG_TRACE_ASSERT_SIMPLE, inactive, disabled
+ # Implemented by CYGDBG_INFRA_DEBUG_TRACE_ASSERT_FANCY, inactive, disabled
+ # Implemented by CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER, inactive, enabled
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # component CYGDBG_USE_ASSERTS
+ # Requires: 1 == CYGINT_INFRA_DEBUG_TRACE_IMPL
+ # component CYGDBG_USE_TRACING
+ # Requires: 1 == CYGINT_INFRA_DEBUG_TRACE_IMPL
+};
+
+# Null output
+# A null output module which is useful when
+# debugging interactively; the output routines
+# can be breakpointed rather than have them actually
+# 'print' something.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_ASSERT_NULL {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Simple output
+# An output module which produces simple output
+# from tracing and assertion events.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_ASSERT_SIMPLE {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Fancy output
+# An output module which produces fancy output
+# from tracing and assertion events.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_ASSERT_FANCY {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Buffered tracing
+# An output module which buffers output
+# from tracing and assertion events. The stored
+# messages are output when an assert fires, or
+# CYG_TRACE_PRINT() (defined in <cyg/infra/cyg_trac.h>)
+# is called.
+# Of course, there will only be stored messages
+# if tracing per se (CYGDBG_USE_TRACING)
+# is enabled above.
+#
+cdl_component CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Trace buffer size
+# The size of the trace buffer. This counts the number
+# of trace records stored. When the buffer fills it
+# either wraps, stops recording, or generates output.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_SIZE {
+ # This option is not active
+ # The parent CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER is not active
+ # ActiveIf constraint: CYGDBG_USE_TRACING
+ # CYGDBG_USE_TRACING == 0
+ # --> 0
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 32
+ # value_source default
+ # Default value: 32
+ # Legal values: 5 to 65535
+};
+
+# Wrap trace buffer when full
+# When the trace buffer has filled with records it
+# starts again at the beginning. Hence only the last
+# CYGDBG_INFRA_DEBUG_TRACE_BUFFER_SIZE messages will
+# be recorded.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_WRAP {
+ # This option is not active
+ # The parent CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER is not active
+ # ActiveIf constraint: CYGDBG_USE_TRACING
+ # CYGDBG_USE_TRACING == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Halt trace buffer when full
+# When the trace buffer has filled with records it
+# stops recording. Hence only the first
+# CYGDBG_INFRA_DEBUG_TRACE_BUFFER_SIZE messages will
+# be recorded.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_HALT {
+ # This option is not active
+ # The parent CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER is not active
+ # ActiveIf constraint: CYGDBG_USE_TRACING
+ # CYGDBG_USE_TRACING == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Print trace buffer when full
+# When the trace buffer has filled with records it
+# prints the contents of the buffer. The buffer is then
+# emptied and the system continues.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_PRINT {
+ # This option is not active
+ # The parent CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER is not active
+ # ActiveIf constraint: CYGDBG_USE_TRACING
+ # CYGDBG_USE_TRACING == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Print trace buffer on assert fail
+# When an assertion fails the trace buffer will be
+# printed to the default diagnostic device.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_PRINT_ON_ASSERT {
+ # This option is not active
+ # The parent CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER is not active
+ # ActiveIf constraint: CYGDBG_USE_TRACING
+ # CYGDBG_USE_TRACING == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Use function names
+# All trace and assert calls within eCos contain a
+# reference to the builtin macro '__PRETTY_FUNCTION__',
+# which evaluates to a string containing
+# the name of the current function.
+# This is useful when reading a trace log.
+# It is possible to suppress the use of the function name
+# by disabling this option.
+# This results in smaller code size, but there is less
+# human-readable information available in the trace output,
+# possibly only filenames and line numbers.
+#
+cdl_option CYGDBG_INFRA_DEBUG_FUNCTION_PSEUDOMACRO {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Startup options
+# Some packages require a startup routine to be called.
+# This can be carried out by application code, by supplying
+# a routine called cyg_package_start() which calls the
+# appropriate package startup routine(s).
+# Alternatively, this routine can be constructed automatically
+# and configured to call the startup routines of your choice.
+#
+cdl_component CYGPKG_INFRA_STARTUP {
+ # There is no associated value.
+};
+
+# >
+# Start uITRON subsystem
+# Generate a call to initialize the
+# uITRON compatibility subsystem
+# within the system version of cyg_package_start().
+# This enables compatibility with uITRON.
+# You must configure uITRON with the correct tasks before
+# starting the uItron subsystem.
+# If this is disabled, and you want to use uITRON,
+# you must call cyg_uitron_start() from your own
+# cyg_package_start() or cyg_userstart().
+#
+cdl_option CYGSEM_START_UITRON_COMPATIBILITY {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_UITRON
+ # CYGPKG_UITRON (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGPKG_UITRON
+ # CYGPKG_UITRON (unknown) == 0
+ # --> 0
+};
+
+# <
+# Smaller slower memcpy()
+# Enabling this option causes the implementation of
+# the standard memcpy() routine to reduce code
+# size at the expense of execution speed. This
+# option is automatically enabled with the use of
+# the -Os option to the compiler. Also note that
+# the compiler will try to use its own builtin
+# version of memcpy() if possible, ignoring the
+# implementation in this package, unless given
+# the -fno-builtin compiler option.
+#
+cdl_option CYGIMP_INFRA_PREFER_SMALL_TO_FAST_MEMCPY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Smaller slower memset()
+# Enabling this option causes the implementation of
+# the standard memset() routine to reduce code
+# size at the expense of execution speed. This
+# option is automatically enabled with the use of
+# the -Os option to the compiler. Also note that
+# the compiler will try to use its own builtin
+# version of memset() if possible, ignoring the
+# implementation in this package, unless given
+# the -fno-builtin compiler option.
+#
+cdl_option CYGIMP_INFRA_PREFER_SMALL_TO_FAST_MEMSET {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Provide empty C++ delete functions
+# To deal with virtual destructors, where the correct delete()
+# function must be called for the derived class in question, the
+# underlying delete is called when needed, from destructors. This
+# is regardless of whether the destructor is called by delete itself.
+# So there is a reference to delete() from all destructors. The
+# default builtin delete() attempts to call free() if there is
+# one defined. So, if you have destructors, and you have free(),
+# as in malloc() and free(), any destructor counts as a reference
+# to free(). So the dynamic memory allocation code is linked
+# in regardless of whether it gets explicitly called. This
+# increases code and data size needlessly.
+# To defeat this undesirable behaviour, we define empty versions
+# of delete and delete. But doing this prevents proper use
+# of dynamic memory in C++ programs via C++'s new and delete
+# operators.
+# Therefore, this option is provided
+# for explicitly disabling the provision of these empty functions,
+# so that new and delete can be used, if that is what is required.
+#
+cdl_option CYGFUN_INFRA_EMPTY_DELETE_FUNCTIONS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Threshold for valid number of delete calls
+# Some users don't know about the empty delete function and then
+# wonder why their C++ classes are leaking memory. If
+# INFRA_DEBUG is enabled we keep a counter for the number of
+# times delete is called. If it goes above this threshold we throw
+# an assertion failure. This should point heavy users of
+# delete in the right direction without upsetting those who want
+# an empty delete function.
+#
+cdl_option CYGNUM_INFRA_EMPTY_DELETE_THRESHOLD {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_INFRA_DEBUG
+ # CYGPKG_INFRA_DEBUG == 0
+ # --> 0
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 100
+ # value_source default
+ # Default value: 100
+};
+
+# Provide dummy abort() function
+# This option controls the inclusion of a dummy abort() function.
+# Parts of the C and C++ compiler runtime systems contain references
+# to abort(), particulary in the C++ exception handling code. It is
+# not possible to eliminate these references, so this dummy function
+# in included to satisfy them. It is not expected that this function
+# will ever be called, so its current behaviour is to simply loop.
+#
+cdl_option CYGFUN_INFRA_DUMMY_ABORT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGINT_ISO_EXIT == 0
+ # CYGINT_ISO_EXIT == 0
+ # --> 1
+ # Requires: !CYGINT_ISO_EXIT
+ # CYGINT_ISO_EXIT == 0
+ # --> 1
+};
+
+# Reset platform at end of test case execution
+# If this option is set then test case programs will reset the platform
+# when they terminate, as opposed to the default which is to just hang
+# in a loop.
+#
+cdl_option CYGSEM_INFRA_RESET_ON_TEST_EXIT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Provide dummy strlen() function
+# This option controls the inclusion of a dummy strlen() function.
+# Parts of the C and C++ compiler runtime systems contain references
+# to strlen(), particulary in the C++ exception handling code. It is
+# not possible to eliminate these references, so this dummy function
+# in included to satisfy them. While it is not expected that this function
+# will ever be called, it is functional but uses the simplest, smallest
+# algorithm. There is a faster version of strlen() in the C library.
+#
+cdl_option CYGFUN_INFRA_DUMMY_STRLEN {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGINT_ISO_STRING_STRFUNCS == 0
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 0
+ # Requires: !CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 0
+};
+
+# Make all compiler warnings show as errors
+# Enabling this option will cause all compiler warnings to show
+# as errors and bring the library build to a halt. This is used
+# to ensure that the code base is warning free, and thus ensure
+# that newly introduced warnings stand out and get fixed before
+# they show up as weird run-time behavior.
+#
+cdl_option CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS {
+ # Flavor: bool
+ user_value 1
+ # value_source user
+ # Default value: 0
+ # Requires: is_substr(CYGBLD_GLOBAL_CFLAGS, " -Werror")
+ # CYGBLD_GLOBAL_CFLAGS == "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe"
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGBLD_GLOBAL_CFLAGS
+ # Requires: CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS
+};
+
+# Make compiler and assembler communicate by pipe
+# Enabling this option will cause the compiler to feed the
+# assembly output the the assembler via a pipe instead of
+# via a temporary file. This normally reduces the build
+# time.
+#
+cdl_option CYGBLD_INFRA_CFLAGS_PIPE {
+ # Flavor: bool
+ user_value 1
+ # value_source user
+ # Default value: 0
+ # Requires: is_substr(CYGBLD_GLOBAL_CFLAGS, " -pipe")
+ # CYGBLD_GLOBAL_CFLAGS == "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe"
+ # --> 1
+};
+
+# Infra build options
+# Package specific build options including control over
+# compiler flags used only in building this package.
+#
+cdl_component CYGPKG_INFRA_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the eCos infra package. These flags are used
+# in addition to the set of global flags.
+#
+cdl_option CYGPKG_INFRA_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-fno-rtti -Woverloaded-virtual"
+ # value_source default
+ # Default value: "-fno-rtti -Woverloaded-virtual"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the eCos infra package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_INFRA_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wno-pointer-sign
+ # value_source default
+ # Default value: -Wno-pointer-sign
+};
+
+# Suppressed linker flags
+# This option modifies the set of linker flags for
+# building the eCos infra package tests. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_INFRA_LDFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wl,--gc-sections
+ # value_source default
+ # Default value: -Wl,--gc-sections
+};
+
+# Additional linker flags
+# This option modifies the set of linker flags for
+# building the eCos infra package tests. These flags are added to
+# the set of global flags if present.
+#
+cdl_option CYGPKG_INFRA_LDFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wl,--fatal-warnings
+ # value_source default
+ # Default value: -Wl,--fatal-warnings
+};
+
+# Infra package tests
+#
+cdl_component CYGPKG_INFRA_TESTS {
+ # Calculated value: "tests/cxxsupp tests/diag_sprintf1 tests/diag_sprintf2"
+ # Flavor: data
+ # Current_value: tests/cxxsupp tests/diag_sprintf1 tests/diag_sprintf2
+};
+
+# >
+# Number of times a test runs
+# This option controls the number of times tests will execute their
+# basic function. Not all tests will honor this setting, but those
+# that do will execute the test N times before terminating. A value
+# less than 0 indicates to run forever.
+#
+cdl_option CYGNUM_TESTS_RUN_COUNT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# <
+# <
+# Redboot ROM monitor
+# doc: ref/redboot.html
+# This package supports the Redboot [stand-alone debug monitor]
+# using eCos as the underlying board support mechanism.
+#
+cdl_package CYGPKG_REDBOOT {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK == 0
+ # CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGPKG_REDBOOT_ARM_OPTIONS
+ # ActiveIf: CYGPKG_REDBOOT
+ # component CYGPKG_REDBOOT_HAL_OPTIONS
+ # ActiveIf: CYGPKG_REDBOOT
+ # component CYGPKG_REDBOOT_HAL_TX27_OPTIONS
+ # ActiveIf: CYGPKG_REDBOOT
+ # option CYGSEM_IO_ETH_DRIVERS_WARN
+ # ActiveIf: CYGPKG_REDBOOT
+};
+
+# >
+# Include support for ELF file format
+#
+cdl_component CYGSEM_REDBOOT_ELF {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Use the virtual address in the ELF headers
+# The ELF headers contain both a virtual and a physical address
+# for where code/data should be loaded. By default the physical
+# address is used but sometimes it is necassary to use the
+# virtual address because of bugy toolchains
+#
+cdl_option CYGOPT_REDBOOT_ELF_VIRTUAL_ADDRESS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Methods of loading images using redboot
+#
+cdl_interface CYGINT_REDBOOT_LOAD_METHOD {
+ # Implemented by CYGBLD_BUILD_REDBOOT_WITH_XYZMODEM, active, enabled
+ # Implemented by CYGPKG_REDBOOT_NETWORKING, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 2
+
+ # The following properties are affected by this value
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGINT_REDBOOT_LOAD_METHOD
+};
+
+# Build Redboot ROM ELF image
+# This option enables the building of the Redboot ELF image.
+# The image may require further relocation or symbol
+# stripping before being converted to a binary image.
+# This is handled by a rule in the target CDL.
+#
+cdl_component CYGBLD_BUILD_REDBOOT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+ # Requires: CYGPKG_INFRA
+ # CYGPKG_INFRA == current
+ # --> 1
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+ # Requires: ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT == 0
+ # --> 1
+ # Requires: ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ # CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT == 0
+ # --> 1
+ # Requires: ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ # CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM == 0
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT == 1
+ # --> 1
+ # Requires: CYGINT_ISO_STRING_MEMFUNCS
+ # CYGINT_ISO_STRING_MEMFUNCS == 1
+ # --> 1
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+ # Requires: CYGINT_REDBOOT_LOAD_METHOD
+ # CYGINT_REDBOOT_LOAD_METHOD == 2
+ # --> 1
+
+ # The following properties are affected by this value
+ # package CYGPKG_HAL_ARM_TX27KARO
+ # Requires: CYGBLD_BUILD_REDBOOT == 1
+ # option CYGBLD_BUILD_REDBOOT_BIN
+ # ActiveIf: CYGBLD_BUILD_REDBOOT
+};
+
+# >
+# Include GDB support in RedBoot
+# RedBoot normally includes support for the GDB debugging
+# protocols. This option allows this to be disabled which
+# may yield a substantial savings in terms of code and memory
+# usage by RedBoot.
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_GDB {
+ # ActiveIf constraint: CYGINT_HAL_DEBUG_GDB_STUBS
+ # CYGINT_HAL_DEBUG_GDB_STUBS == 1
+ # --> 1
+
+ # Flavor: bool
+ user_value 0
+ # value_source user
+ # Default value: 1
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT == 0
+ # --> 0
+};
+
+# Threads debugging support
+# Enabling this option will include special code in the
+# GDB stubs to support debugging of threaded programs. In
+# the case of eCos programs, this support allows GDB to
+# have complete access to the eCos threads in the
+# program.
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_THREADS {
+ # ActiveIf constraint: CYG_HAL_STARTUP != "RAM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT == 1
+ # --> 1
+};
+
+# Customized version string
+# Use this option to define a customized version "string" for
+# RedBoot. Note: this value is only cosmetic, displayed by the
+# "version" command, but is useful for providing site specific
+# information about the RedBoot configuration.
+#
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 "Ka-Ro 2009-06-10"
+ # value_source inferred
+ # Default value: 0 0
+};
+
+# Enable command line editing
+# If this option is non-zero, RedBoot will remember the
+# last N command lines. These lines may be reused.
+# Enabling this history will also enable rudimentary
+# editting of the lines themselves.
+#
+cdl_option CYGNUM_REDBOOT_CMD_LINE_EDITING {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 16
+ # value_source default
+ # Default value: 16
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_CMD_LINE_ANSI_SEQUENCES
+ # ActiveIf: CYGNUM_REDBOOT_CMD_LINE_EDITING != 0
+ # option CYGBLD_REDBOOT_CMD_LINE_HISTORY
+ # Requires: CYGNUM_REDBOOT_CMD_LINE_EDITING > 0
+};
+
+# Enable command line editing using ANSI arrows, etc
+# If this option is enabled, RedBoot will accept standard ANSI key
+# sequences for cursor movement (along with the emacs style keys).
+#
+cdl_option CYGSEM_REDBOOT_CMD_LINE_ANSI_SEQUENCES {
+ # ActiveIf constraint: CYGNUM_REDBOOT_CMD_LINE_EDITING != 0
+ # CYGNUM_REDBOOT_CMD_LINE_EDITING == 16
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Enable history command and expansion
+# Enabling this option will allow RedBoot to provide a
+# history command to list previous commands. Also enables
+# history expansion via '!' character similar to bash
+# shell.
+#
+cdl_option CYGBLD_REDBOOT_CMD_LINE_HISTORY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGNUM_REDBOOT_CMD_LINE_EDITING > 0
+ # CYGNUM_REDBOOT_CMD_LINE_EDITING == 16
+ # --> 1
+};
+
+# Number of unique RAM segments on platform
+# Change this option to be the number of memory segments which are
+# supported by the platform. If the value is greater than 1, then
+# a platform specific function must provide information about the
+# additional segments.
+#
+cdl_option CYGBLD_REDBOOT_MAX_MEM_SEGMENTS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include support gzip/zlib decompression
+#
+cdl_component CYGBLD_BUILD_REDBOOT_WITH_ZLIB {
+ # ActiveIf constraint: CYGPKG_COMPRESS_ZLIB
+ # CYGPKG_COMPRESS_ZLIB == current
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGOPT_REDBOOT_FIS_ZLIB_COMMON_BUFFER
+ # ActiveIf: CYGBLD_BUILD_REDBOOT_WITH_ZLIB && CYGOPT_REDBOOT_FIS
+};
+
+# >
+# Size of zlib decompression buffer
+# This is the size of the buffer filled with incoming data
+# during load before calls are made to the decompressor
+# function. For ethernet downloads this can be made bigger
+# (at the cost of memory), but for serial downloads on slow
+# processors it may be necessary to reduce the size to
+# avoid serial overruns. zlib appears to bail out if less
+# than five bytes are available initially so this is the
+# minimum.
+#
+cdl_option CYGNUM_REDBOOT_LOAD_ZLIB_BUFFER {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 64
+ # value_source default
+ # Default value: 64
+ # Legal values: 5 to 256
+};
+
+# Support compression of Flash images
+# This CDL indicates whether flash images can
+# be decompressed from gzip/zlib format into RAM.
+#
+cdl_option CYGPRI_REDBOOT_ZLIB_FLASH {
+ # ActiveIf constraint: CYGPKG_REDBOOT_FLASH
+ # CYGPKG_REDBOOT_FLASH == 1
+ # --> 1
+ # ActiveIf constraint: (!CYGSEM_IO_FLASH_READ_INDIRECT) || CYGPRI_REDBOOT_ZLIB_FLASH_FORCE
+ # CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # CYGPRI_REDBOOT_ZLIB_FLASH_FORCE == 1
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+};
+
+# Include GZIP uncompress command
+# Enable this option to include a 'gunzip' command
+# to uncompress GZIP compressed data.
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_GUNZIP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Turn on CYGPRI_REDBOOT_ZLIB_FLASH
+# Force CYGPRI_REDBOOT_ZLIB_FLASH to be chosen
+#
+cdl_option CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGPRI_REDBOOT_ZLIB_FLASH
+ # ActiveIf: (!CYGSEM_IO_FLASH_READ_INDIRECT) || CYGPRI_REDBOOT_ZLIB_FLASH_FORCE
+};
+
+# <
+# Include support for xyzModem downloads
+# doc: ref/download-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_XYZMODEM {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Allow the load-command write into Flash.
+# Write images direct to Flash via the load command.
+# We assume anything which is invalid RAM is flash, hence
+# the requires statement
+#
+cdl_option CYGBLD_REDBOOT_LOAD_INTO_FLASH {
+ # ActiveIf constraint: CYGPKG_REDBOOT_FLASH
+ # CYGPKG_REDBOOT_FLASH == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS
+ # CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS == 1
+ # --> 1
+};
+
+# Include MS Windows CE support
+# doc: ref/wince.html
+# This option enables MS Windows CE EShell support
+# and Windows CE .BIN images support
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_WINCE_SUPPORT {
+ # Flavor: bool
+ user_value 1
+ # value_source user
+ # Default value: 0
+};
+
+# Include support for MXC USB downloads
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_MXCUSB {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Include support for i.MX USB OTG downloads
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_IMXOTG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Include POSIX checksum command
+# doc: ref/cksum-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_CKSUM {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include memory fill command
+# doc: ref/mfill-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_MFILL {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include memory compare command
+# doc: ref/mcmp-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_MCMP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include memory copy command
+# doc: ref/mcopy-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_MCOPY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include memory dump command
+# doc: ref/dump-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_DUMP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include cache command
+# doc: ref/cache-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include exec command
+# doc: ref/exec-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGPKG_REDBOOT_ARM_LINUX_EXEC
+ # ActiveIf: CYGBLD_BUILD_REDBOOT_WITH_EXEC
+};
+
+# Include I/O Memory commands 'iopeek' and 'iopoke'
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_IOMEM {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Granularity of timer/ticks
+# This option controls the granularity of the timers.
+# Faster CPUs can afford higher granularity (lower values)
+# which should give higher network performance since the stack
+# is purely polled.
+#
+cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 250
+ # value_source default
+ # Default value: 250
+ # Legal values: 10 25 50 100 250 500 1000
+};
+
+# Redboot Networking
+# This option includes networking support in RedBoot.
+#
+cdl_component CYGPKG_REDBOOT_NETWORKING {
+ # ActiveIf constraint: CYGPKG_IO_ETH_DRIVERS
+ # CYGPKG_IO_ETH_DRIVERS == current
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_IO_ETH_DRIVERS_PASS_PACKETS
+ # DefaultValue: 0 != CYGPKG_REDBOOT_NETWORKING
+};
+
+# >
+# Print net debug information
+# This option is overriden by the configuration stored
+# in flash.
+#
+cdl_option CYGDBG_REDBOOT_NET_DEBUG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Support TFTP for download
+# This option enables the use of the TFTP protocol for
+# download
+#
+cdl_option CYGSEM_REDBOOT_NET_TFTP_DOWNLOAD {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Support HTTP for download
+# This option enables the use of the HTTP protocol for
+# download
+#
+cdl_option CYGSEM_REDBOOT_NET_HTTP_DOWNLOAD {
+ # Flavor: bool
+ user_value 0
+ # value_source user
+ # Default value: 1
+};
+
+# Default IP address
+# This IP address is the default used by RedBoot if
+# a BOOTP/DHCP server does not respond. The numbers
+# should be separated by *commas*, and not dots. If
+# an IP address is configured into the Flash
+# configuration, that will be used in preference.
+#
+cdl_component CYGDAT_REDBOOT_DEFAULT_IP_ADDR {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 0 0
+};
+
+# >
+# Do not try to use BOOTP
+# By default Redboot tries to use BOOTP to get an IP
+# address. If there's no BOOTP server on your network
+# use this option to avoid to wait until the
+# timeout. This option is overriden by the
+# configuration stored in flash.
+#
+cdl_option CYGSEM_REDBOOT_DEFAULT_NO_BOOTP {
+ # This option is not active
+ # The parent CYGDAT_REDBOOT_DEFAULT_IP_ADDR is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Default bootp server
+# This IP address is the default server
+# address used by RedBoot if a BOOTP/DHCP
+# server does not respond. The numbers should
+# be separated by *commas*, and not dots. If
+# an IP address is configured into the Flash
+# configuration, that will be used in
+# preference.
+#
+cdl_option CYGDAT_REDBOOT_DEFAULT_BOOTP_SERVER_IP_ADDR {
+ # This option is not active
+ # The parent CYGDAT_REDBOOT_DEFAULT_IP_ADDR is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 0 0
+};
+
+# <
+# Use DHCP to get IP information
+# Use DHCP protocol to obtain pertinent IP addresses, such
+# as the client, server, gateway, etc.
+#
+cdl_component CYGSEM_REDBOOT_NETWORKING_DHCP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGSEM_REDBOOT_NETWORKING_USE_GATEWAY
+ # Requires: CYGSEM_REDBOOT_NETWORKING_DHCP
+};
+
+# Use a gateway for non-local IP traffic
+# Enabling this option will allow the RedBoot networking
+# stack to use a [single] gateway to reach a non-local
+# IP address. If disabled, RedBoot will only be able to
+# reach nodes on the same subnet.
+#
+cdl_component CYGSEM_REDBOOT_NETWORKING_USE_GATEWAY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGSEM_REDBOOT_NETWORKING_DHCP
+ # CYGSEM_REDBOOT_NETWORKING_DHCP == 1
+ # --> 1
+};
+
+# >
+# Default gateway IP address
+# This IP address is the default used by RedBoot
+# if a BOOTP/DHCP server does not respond. The
+# numbers should be separated by *commas*, and
+# not dots. If an IP address is configured into
+# the Flash configuration, that will be used in
+# preference.
+#
+cdl_component CYGDAT_REDBOOT_DEFAULT_GATEWAY_IP_ADDR {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 0 0
+};
+
+# Default IP address mask
+# This IP address mask is the default used by
+# RedBoot if a BOOTP/DHCP server does not
+# respond. The numbers should be separated by
+# *commas*, and not dots. If an IP address is
+# configured into the Flash configuration, that
+# will be used in preference.
+#
+cdl_component CYGDAT_REDBOOT_DEFAULT_IP_ADDR_MASK {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "255, 255, 255, 0"
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 0 0
+};
+
+# <
+# TCP port to listen for incoming connections
+# RedBoot will 'listen' on this port for incoming TCP
+# connections. This allows outside connections to be made
+# to the platform, either for GDB or RedBoot commands.
+#
+cdl_option CYGNUM_REDBOOT_NETWORKING_TCP_PORT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 9000
+ # value_source default
+ # Default value: 9000
+};
+
+# Number of [network] packet buffers
+# RedBoot may need to buffer network data to support
+# various connections. This option allows control
+# over the number of such buffered packets, and in
+# turn, controls the amount of memory used by RedBoot
+# (which is not available to user applications).
+# Each packet buffer takes up about 1514 bytes.
+# Note: there is little need to make this larger than
+# the default.
+#
+cdl_option CYGNUM_REDBOOT_NETWORKING_MAX_PKTBUF {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 4
+ # value_source default
+ # Default value: 4
+ # Legal values: 3 to 8
+};
+
+# DNS support
+# When this option is enabled, RedBoot will be built with
+# support for DNS, allowing use of hostnames on the command
+# line.
+#
+cdl_component CYGPKG_REDBOOT_NETWORKING_DNS {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_NS_DNS
+ # CYGPKG_NS_DNS (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: !CYGPKG_NS_DNS_BUILD
+ # CYGPKG_NS_DNS_BUILD (unknown) == 0
+ # --> 1
+};
+
+# >
+# Default DNS IP
+# This option sets the IP of the default DNS. The IP can be
+# changed at runtime as well.
+#
+cdl_option CYGPKG_REDBOOT_NETWORKING_DNS_IP {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS is not active
+ # ActiveIf constraint: !CYGSEM_REDBOOT_FLASH_CONFIG
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 0
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0.0.0.0
+ # value_source default
+ # Default value: 0.0.0.0
+};
+
+# Timeout in DNS lookup
+# This option sets the timeout used when looking up an
+# address via the DNS. Default is 10 seconds.
+#
+cdl_option CYGNUM_REDBOOT_NETWORKING_DNS_TIMEOUT {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS is not active
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 10
+ # value_source default
+ # Default value: 10
+};
+
+# Support the use of a domain name
+# This option controls if Redboot supports domain
+# names when performing DNS lookups
+#
+cdl_component CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# >
+# Default DNS domain
+# This option sets the default DNS domain name.
+# This value will be overwritten by the value in
+# flash or a domain returned by DHCP
+#
+cdl_option CYGPKG_REDBOOT_NETWORKING_DNS_DEFAULT_DOMAIN {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Get DNS domain from Flash
+# This option enables getting the domain name
+# from the flash configuration. This can later be
+# overwritten by a value learnt from DHCP
+#
+cdl_option CYGPKG_REDBOOT_NETWORKING_DNS_FCONFIG_DOMAIN {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is disabled
+ # ActiveIf constraint: CYGSEM_REDBOOT_FLASH_CONFIG
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Use DNS domain from DHCP
+# This option enables the use of the domain name
+# returned by DHCP.
+#
+cdl_option CYGPKG_REDBOOT_NETWORKING_DNS_DHCP_DOMAIN {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# BOOTP/DHCP DNS domain buffer size
+# This options sets the size of the static
+# buffer used by BOOTP/DHCP to store the DNS
+# domain name. The domain name will not be
+# set if the buffer is too small to hold it.
+#
+cdl_option CYGNUM_REDBOOT_NETWORK_DNS_DOMAIN_BUFSIZE {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 32
+ # value_source default
+ # Default value: 32
+};
+
+# <
+# <
+# Default network device driver
+# This is the name of the default network device to use.
+#
+cdl_option CYGDAT_REDBOOT_DEFAULT_NETWORK_DEVICE {
+ # This option is not active
+ # ActiveIf constraint: CYGHWR_NET_DRIVERS > 1
+ # CYGHWR_NET_DRIVERS == 1
+ # --> 0
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "\"\""
+ # value_source default
+ # Default value: "\"\""
+};
+
+# Initialize only one net device
+# This option tells RedBoot to stop initializing network
+# devices when it finds the first device which is
+# successfully initialized. The default behavior causes
+# all network devices to be initialized.
+#
+cdl_option CYGSEM_REDBOOT_NETWORK_INIT_ONE_DEVICE {
+ # This option is not active
+ # ActiveIf constraint: CYGHWR_NET_DRIVERS > 1
+ # CYGHWR_NET_DRIVERS == 1
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Let RedBoot use any I/O channel for its console.
+# If this option is enabled then RedBoot will attempt to use all
+# defined serial I/O channels for its console device. Once input
+# arrives at one of these channels then the console will use only
+# that port.
+#
+cdl_option CYGPKG_REDBOOT_ANY_CONSOLE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+};
+
+# Let RedBoot adjust the baud rate of the serial console.
+# If this option is enabled then RedBoot will support commands
+# to set and query the baud rate on the selected console.
+#
+cdl_option CYGSEM_REDBOOT_VARIABLE_BAUD_RATE {
+ # ActiveIf constraint: CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+ # CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Run a platform specific startup function.
+# If this option is enabled then RedBoot will execute a platform
+# specific startup function before entering into its command line
+# processing. This allows the platform to perform any special
+# setups before RedBoot actually starts running. Note: the entire
+# RedBoot environment will already be initialized at this point.
+#
+cdl_option CYGSEM_REDBOOT_PLF_STARTUP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Run a platform specific ESA validation function.
+# If this option is enabled then RedBoot will execute a platform
+# specific function to validate an ethernet ESA. This would be
+# useful if the address must conform to standards set by the
+# hardware manufacturer, etc.
+#
+cdl_option CYGSEM_REDBOOT_PLF_ESA_VALIDATE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # component CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
+ # Requires: CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ # option CYGDAT_DEVS_ETH_ARM_TX27KARO_OUI
+ # ActiveIf: CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+};
+
+# Maximum command line length
+# This option allows control over how long the CLI command line
+# should be. This space will be allocated statically
+# rather than from RedBoot's stack.
+#
+cdl_option CYGPKG_REDBOOT_MAX_CMD_LINE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 256
+ # The inferred value should not be edited directly.
+ inferred_value 1024
+ # value_source inferred
+ # Default value: 256
+};
+
+# Command processing idle timeout (ms)
+# This option controls the timeout period before the
+# command processing is considered 'idle'. Making this
+# number smaller will cause idle processing to take place
+# more often, etc. The default value of 10ms is a reasonable
+# tradeoff between responsiveness and overhead.
+#
+cdl_option CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 10
+ # value_source default
+ # Default value: 10
+};
+
+# Validate RAM addresses during load
+# This option controls whether or not RedBoot will make
+# sure that memory being used by the "load" command is
+# in fact in user RAM. Leaving the option enabled makes
+# for a safer environment, but this check may not be valid
+# on all platforms, thus the ability to disable it.
+# ** Disable this only with great care **
+#
+cdl_option CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ # Requires: CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS
+};
+
+# Allow RedBoot to support FLASH programming
+# If this option is enabled then RedBoot will provide commands
+# to manage images in FLASH memory. These images can be loaded
+# into memory for execution or executed in place.
+#
+cdl_component CYGPKG_REDBOOT_FLASH {
+ # ActiveIf constraint: CYGHWR_IO_FLASH_DEVICE
+ # CYGHWR_IO_FLASH_DEVICE == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGPRI_REDBOOT_ZLIB_FLASH
+ # ActiveIf: CYGPKG_REDBOOT_FLASH
+ # option CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ # ActiveIf: CYGPKG_REDBOOT_FLASH
+};
+
+# >
+# Byte order used to store info in flash.
+# This option controls the byte ordering used to store
+# the FIS directory info and flash config info.
+#
+cdl_option CYGOPT_REDBOOT_FLASH_BYTEORDER {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value NATURAL
+ # value_source default
+ # Default value: NATURAL
+ # Legal values: "NATURAL" "MSBFIRST" "LSBFIRST"
+};
+
+# RedBoot Flash Image System support
+# doc: ref/flash-image-system.html
+# This option enables the Flash Image System commands
+# and support within RedBoot. If disabled, simple Flash
+# access commands such as "fis write" will still exist.
+# This option would be disabled for targets that need simple
+# FLASH manipulation, but do not have the need or space for
+# complete image management.
+#
+cdl_option CYGOPT_REDBOOT_FIS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGPKG_REDBOOT_FIS_CONTENTS
+ # ActiveIf: CYGOPT_REDBOOT_FIS
+ # option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
+ # ActiveIf: CYGOPT_REDBOOT_FIS && (CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == "FLASH")
+ # component CYGOPT_REDBOOT_FIS_ZLIB_COMMON_BUFFER
+ # ActiveIf: CYGBLD_BUILD_REDBOOT_WITH_ZLIB && CYGOPT_REDBOOT_FIS
+};
+
+# Max number of chunks of free space to manage
+# If this option is defined then "fis free" will
+# rely on the FIS directory to determine what space is
+# free within the FLASH. This option controls the
+# maximum number of free segment which can be handled
+# (typically this number is small). If this option is
+# not enabled, the the archaic behaviour of actually
+# scanning the FLASH for erased sectors (unreliable)
+# will be used to determine what's free and what's
+# not.
+#
+cdl_option CYGDAT_REDBOOT_FIS_MAX_FREE_CHUNKS {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 1 32
+ # value_source default
+ # Default value: 1 32
+};
+
+# Flash Image System default directory contents
+#
+cdl_component CYGPKG_REDBOOT_FIS_CONTENTS {
+ # ActiveIf constraint: CYGOPT_REDBOOT_FIS
+ # CYGOPT_REDBOOT_FIS == 1
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+};
+
+# >
+# Flash block containing the Directory
+# Which block of flash should hold the directory
+# information. Positive numbers are absolute block
+# numbers. Negative block numbers count backwards
+# from the last block. eg 2 means block 2, -2
+# means the last but one block.
+#
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -1
+ # value_source default
+ # Default value: -1
+
+ # The following properties are affected by this value
+ # option CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK
+ # Requires: CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK !=
+ # CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK
+};
+
+# Redundant Flash Image System Directory Support
+# This option enables the use of a redundant FIS
+# directory within RedBoot. If enabled a flash block
+# will be reserved for a second copy of the fis
+# directory. Doing this allow for power failure safe
+# updates of the directory by the application.
+#
+cdl_component CYGOPT_REDBOOT_REDUNDANT_FIS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: 0 == CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
+ # CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG == 1
+ # --> 0
+};
+
+# >
+# Flash block containing the backup Directory
+# Which block of flash should hold the redundant
+# directory information. Positive numbers are
+# absolute block numbers. Negative block numbers
+# count backwards from the last block. eg 2 means
+# block 2, -2 means the last but one block.
+#
+cdl_option CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK {
+ # This option is not active
+ # The parent CYGOPT_REDBOOT_REDUNDANT_FIS is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -3
+ # value_source default
+ # Default value: -3
+ # Requires: CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK !=
+ # CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK
+ # CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK == 0
+ # CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK == -1
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK
+ # Requires: CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK !=
+ # CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK
+};
+
+# <
+# Pseudo-file to describe reserved area
+# If an area of FLASH is reserved, it is informative to
+# have a fis entry describing it. This option controls
+# creation of such an entry by default in the fis init
+# command.
+#
+cdl_option CYGOPT_REDBOOT_FIS_RESERVED_BASE {
+ # This option is not active
+ # ActiveIf constraint: 0 != CYGNUM_REDBOOT_FLASH_RESERVED_BASE
+ # CYGNUM_REDBOOT_FLASH_RESERVED_BASE == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# File to describe RedBoot boot image
+# Normally a ROM-startup RedBoot image is first in the
+# FLASH, and the system boots using that image. This
+# option controls creation of an entry describing it in
+# the fis init command. It might be disabled if a
+# platform has an immutable boot image of its own, where
+# we use a POST-startup RedBoot instead, which performs
+# less board initialization.
+#
+cdl_option CYGOPT_REDBOOT_FIS_REDBOOT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGOPT_REDBOOT_FIS_REDBOOT_POST
+ # DefaultValue: !CYGOPT_REDBOOT_FIS_REDBOOT
+ # option CYGBLD_REDBOOT_MIN_IMAGE_SIZE
+ # DefaultValue: CYGOPT_REDBOOT_FIS_REDBOOT ? 0x20000 : 0
+};
+
+# File to describe RedBoot POST-compatible image
+# This option controls creation of an entry describing a
+# POST-startup RedBoot image in the fis init command.
+# Not all platforms support POST-startup. A platform
+# might have both for testing purposes, where the
+# eventual user would substitute their own POST code for
+# the initial ROM-startup RedBoot, and then jump to the
+# POST-compatible RedBoot immediately following.
+#
+cdl_component CYGOPT_REDBOOT_FIS_REDBOOT_POST {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: !CYGOPT_REDBOOT_FIS_REDBOOT
+ # CYGOPT_REDBOOT_FIS_REDBOOT == 1
+ # --> 0
+};
+
+# >
+# Offset of POST image from FLASH start
+# This option specifies the offset for a POST image from
+# the start of FLASH. If unset, then the fis entry
+# describing the POST image will be placed where
+# convenient.
+#
+cdl_option CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET {
+ # This option is not active
+ # The parent CYGOPT_REDBOOT_FIS_REDBOOT_POST is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+ # Requires: CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET >= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET == 0
+ # CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET
+ # Requires: CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET >= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+};
+
+# <
+# File to describe RedBoot backup image
+# This option controls creation of an entry describing a
+# backup RedBoot image in the fis init command.
+# Conventionally a RAM-startup RedBoot image is kept
+# under this name for use in updating the ROM-based
+# RedBoot that boots the board.
+#
+cdl_option CYGOPT_REDBOOT_FIS_REDBOOT_BACKUP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Include ARM SIB ID in FIS
+# If set, this option will cause the last 5 words of
+# the FIS to include the special ID needed for the
+# flash to be recognized as a reserved area for RedBoot
+# by an ARM BootRom monitor.
+#
+cdl_option CYGOPT_REDBOOT_FIS_DIRECTORY_ARM_SIB_ID {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Size of FIS directory entry
+# The FIS directory is limited to one single flash
+# sector. If your flash has tiny sectors, you may wish
+# to reduce this value in order to get more slots in
+# the FIS directory.
+#
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 256
+ # value_source default
+ # Default value: 256
+};
+
+# Number of FIS directory entries
+# The FIS directory normally occupies a single flash
+# sector. Adjusting this value can allow for more than
+# one flash sector to be used, which is useful if your
+# sectors are very small.
+#
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_COUNT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 8
+ # value_source default
+ # Default value: 8
+};
+
+# Maximum RedBoot image size
+# This option controls the maximum length reserved
+# for the RedBoot boot image in the FIS table.
+# This should be a multiple of the flash's erase
+# block size.
+#
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00020000
+ # The inferred value should not be edited directly.
+ inferred_value 0x00040000
+ # value_source inferred
+ # Default value: CYGOPT_REDBOOT_FIS_REDBOOT ? 0x20000 : 0
+ # CYGOPT_REDBOOT_FIS_REDBOOT == 1
+ # --> 0x00020000
+};
+
+# Offset from start of FLASH to RedBoot boot image
+# This option controls where the RedBoot boot image is
+# located relative to the start of FLASH.
+#
+cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGNUM_REDBOOT_FLASH_RESERVED_BASE
+ # CYGNUM_REDBOOT_FLASH_RESERVED_BASE == 0
+ # --> 0
+ # Requires: CYGNUM_REDBOOT_FLASH_RESERVED_BASE <= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # CYGNUM_REDBOOT_FLASH_RESERVED_BASE == 0
+ # CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET
+ # Requires: CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET >= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # Requires: CYGNUM_REDBOOT_FLASH_RESERVED_BASE <= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # component CYGPKG_HAL_ARM_TX27_OPTIONS
+ # Requires: CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0
+};
+
+# Size of reserved area at start of FLASH
+# This option reserves an area at the start of
+# FLASH where RedBoot will never interfere; it is
+# expected that this area contains
+# (non-RedBoot-based) POST code or some other boot
+# monitor that executes before RedBoot.
+#
+cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGOPT_REDBOOT_FIS_RESERVED_BASE
+ # ActiveIf: 0 != CYGNUM_REDBOOT_FLASH_RESERVED_BASE
+ # option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # DefaultValue: CYGNUM_REDBOOT_FLASH_RESERVED_BASE
+ # option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # Requires: CYGNUM_REDBOOT_FLASH_RESERVED_BASE <= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+};
+
+# <
+# Keep all RedBoot FLASH data blocks locked.
+# When this option is enabled, RedBoot will keep configuration
+# data and the FIS directory blocks implicitly locked. While
+# this is somewhat safer, it does add overhead during updates.
+#
+cdl_option CYGSEM_REDBOOT_FLASH_LOCK_SPECIAL {
+ # This option is not active
+ # ActiveIf constraint: CYGHWR_IO_FLASH_BLOCK_LOCKING != 0
+ # CYGHWR_IO_FLASH_BLOCK_LOCKING == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Use CRC checksums on FIS images.
+# When this option is enabled, RedBoot will use CRC checksums
+# when reading and writing flash images.
+#
+cdl_option CYGSEM_REDBOOT_FIS_CRC_CHECK {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# ARM FLASH drivers support SIB flash block structure
+# This interface is implemented by a flash driver
+# to indicate that it supports the ARM SIB flash
+# block structure
+#
+cdl_interface CYGINT_REDBOOT_ARM_FLASH_SIB_SUPPORTED {
+ # No options implement this inferface
+ # ActiveIf constraint: CYGPKG_HAL_ARM
+ # CYGPKG_HAL_ARM == current
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_REDBOOT_ARM_FLASH_SIB
+ # ActiveIf: CYGINT_REDBOOT_ARM_FLASH_SIB_SUPPORTED
+};
+
+# Use ARM SIB flash block structure
+# This option is used to interpret ARM Flash System
+# information blocks.
+#
+cdl_option CYGHWR_REDBOOT_ARM_FLASH_SIB {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_REDBOOT_ARM_FLASH_SIB_SUPPORTED
+ # CYGINT_REDBOOT_ARM_FLASH_SIB_SUPPORTED == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Keep RedBoot configuration data in FLASH
+# When this option is enabled, RedBoot will keep configuration
+# data in a separate block of FLASH memory. This data will
+# include such items as the node IP address or startup scripts.
+#
+cdl_component CYGSEM_REDBOOT_FLASH_CONFIG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGPKG_IO_FLASH != 0
+ # CYGPKG_IO_FLASH == current
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGDAT_REDBOOT_DEFAULT_IP_ADDR
+ # DefaultValue: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # option CYGDAT_REDBOOT_DEFAULT_BOOTP_SERVER_IP_ADDR
+ # DefaultValue: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # component CYGDAT_REDBOOT_DEFAULT_GATEWAY_IP_ADDR
+ # DefaultValue: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # component CYGDAT_REDBOOT_DEFAULT_IP_ADDR_MASK
+ # DefaultValue: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "255, 255, 255, 0"
+ # option CYGPKG_REDBOOT_NETWORKING_DNS_IP
+ # ActiveIf: !CYGSEM_REDBOOT_FLASH_CONFIG
+ # option CYGPKG_REDBOOT_NETWORKING_DNS_FCONFIG_DOMAIN
+ # ActiveIf: CYGSEM_REDBOOT_FLASH_CONFIG
+ # option CYGFUN_REDBOOT_BOOT_SCRIPT
+ # ActiveIf: CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT || CYGSEM_REDBOOT_FLASH_CONFIG
+};
+
+# >
+# Length of configuration data in FLASH
+# This option is used to control the amount of memory and FLASH
+# to be used for configuration options (persistent storage).
+#
+cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 4096
+ # value_source default
+ # Default value: 4096
+};
+
+# Style of media used for persistent data storage
+# Persistent data storage can either be held in 'norma' FLASH
+# or some other device (represented by the 'EEPROM' choice).
+# The different styles utilize different access methods.
+#
+cdl_option CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value FLASH
+ # value_source default
+ # Default value: FLASH
+ # Legal values: "FLASH" "EEPROM"
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
+ # ActiveIf: CYGOPT_REDBOOT_FIS && (CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == "FLASH")
+ # option CYGSEM_REDBOOT_FLASH_CONFIG_READONLY_FALLBACK
+ # DefaultValue: (CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == "FLASH")
+};
+
+# Merged config data and FIS directory
+# If this option is set, then the FIS directory and FLASH
+# configuration database will be stored in the same physical
+# FLASH block.
+#
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+ # ActiveIf constraint: CYGOPT_REDBOOT_FIS && (CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == "FLASH")
+ # CYGOPT_REDBOOT_FIS == 1
+ # CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == FLASH
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGOPT_REDBOOT_REDUNDANT_FIS
+ # Requires: 0 == CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
+};
+
+# Which block of flash to use
+# Which block of flash should hold the configuration
+# information. Positive numbers are absolute block numbers.
+# Negative block numbers count backwards from the last block.
+# eg 2 means block 2, -2 means the last but one block.
+#
+cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -2
+ # value_source default
+ # Default value: -2
+};
+
+# Support simple macros/aliases in FLASH
+# This option is used to allow support for simple text-based
+# macros (aliases). These aliases are kept in the FLASH
+# configuration data (persistent storage).
+#
+cdl_option CYGSEM_REDBOOT_FLASH_ALIASES {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Length of strings in FLASH configuration data
+# This option is used to control the amount of memory
+# and FLASH to be used for string configuration
+# options (persistent storage).
+#
+cdl_option CYGNUM_REDBOOT_FLASH_STRING_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 128
+ # value_source default
+ # Default value: 128
+};
+
+# Length of configuration script(s) in FLASH
+# This option is used to control the amount of memory and
+# FLASH to be used for configuration options (persistent
+# storage).
+#
+cdl_option CYGNUM_REDBOOT_FLASH_SCRIPT_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 512
+ # The inferred value should not be edited directly.
+ inferred_value 2048
+ # value_source inferred
+ # Default value: 512
+};
+
+# Fallback to read-only FLASH configuration
+# This option will cause the configuration information to
+# revert to the readonly information stored in the FLASH.
+# The option only takes effect after
+# 1) the config_ok flag has been set to be true,
+# indicating that at one time the copy in RAM was valid;
+# and
+# 2) the information in RAM has been verified to be invalid
+#
+cdl_option CYGSEM_REDBOOT_FLASH_CONFIG_READONLY_FALLBACK {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: (CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == "FLASH")
+ # CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == FLASH
+ # --> 1
+};
+
+# <
+# Allow RedBoot to support fileio
+# If this option is enabled then RedBoot will provide commands
+# to load files from fileio file systems such as JFFS2.
+#
+cdl_component CYGPKG_REDBOOT_FILEIO {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_IO_FILEIO
+ # CYGPKG_IO_FILEIO (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_REDBOOT_GETC_BUFFER
+ # DefaultValue: CYGPKG_REDBOOT_FILEIO ? 4096 : 256
+};
+
+# >
+# Include an ls command
+# If this option is enabled a simple ls command will be
+# included in redboot so the contents of a directory
+# can be listed
+#
+cdl_option CYGBLD_REDBOOT_FILEIO_WITH_LS {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_FILEIO is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Allow RedBoot to support disks
+# If this option is enabled then RedBoot will provide commands
+# to load disk files.
+#
+cdl_component CYGPKG_REDBOOT_DISK {
+ # Flavor: bool
+ user_value 0
+ # value_source user
+ # Default value: 1
+};
+
+# >
+# Include Redboot commands for disk access
+#
+cdl_option CYGSEM_REDBOOT_DISK {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGINT_REDBOOT_DISK_DRIVERS != 0
+ # CYGINT_REDBOOT_DISK_DRIVERS == 0
+ # --> 0
+};
+
+# Hardware drivers for disk-type devices
+#
+cdl_interface CYGINT_REDBOOT_DISK_DRIVERS {
+ # Implemented by CYGSEM_REDBOOT_DISK_IDE, inactive, enabled
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_DISK
+ # DefaultValue: CYGINT_REDBOOT_DISK_DRIVERS != 0
+};
+
+# Maximum number of supported disks
+# This option controls the number of disks supported by
+# RedBoot.
+#
+cdl_option CYGNUM_REDBOOT_MAX_DISKS {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 4
+ # value_source default
+ # Default value: 4
+};
+
+# Maximum number of partitions per disk
+# This option controls the maximum number of supported
+# partitions per disk.
+#
+cdl_option CYGNUM_REDBOOT_MAX_PARTITIONS {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 8
+ # value_source default
+ # Default value: 8
+};
+
+# Support IDE disks.
+# When this option is enabled, RedBoot will support IDE disks.
+#
+cdl_component CYGSEM_REDBOOT_DISK_IDE {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+ # ActiveIf constraint: CYGINT_HAL_PLF_IF_IDE != 0
+ # CYGINT_HAL_PLF_IF_IDE == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Work with VMware virtual disks
+# This option controls the disk driver behavior at
+# ide-init
+#
+cdl_option CYGSEM_REDBOOT_DISK_IDE_VMWARE {
+ # This option is not active
+ # The parent CYGSEM_REDBOOT_DISK_IDE is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Support Linux second extended filesystems.
+# When this option is enabled, RedBoot will support EXT2
+# filesystems.
+#
+cdl_component CYGSEM_REDBOOT_DISK_EXT2FS {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Support ISO9660 filesystems.
+# When this option is enabled, RedBoot will support ISO9660
+# filesystems.
+#
+cdl_component CYGSEM_REDBOOT_DISK_ISO9660 {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # Calculated value: 0
+ # Flavor: bool
+ # Current value: 0
+};
+
+# <
+# Boot scripting
+# doc: ref/persistent-state-flash.html
+# This contains options related to RedBoot's boot script
+# functionality.
+#
+cdl_component CYGPKG_REDBOOT_BOOT_SCRIPT {
+ # There is no associated value.
+};
+
+# >
+# Boot scripting enabled
+# This option controls whether RedBoot boot script
+# functionality is enabled.
+#
+cdl_option CYGFUN_REDBOOT_BOOT_SCRIPT {
+ # ActiveIf constraint: CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT || CYGSEM_REDBOOT_FLASH_CONFIG
+ # CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT == 0
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+};
+
+# Use default RedBoot boot script
+# If enabled, this option will tell RedBoot to use the
+# value of this option as a default boot script.
+#
+cdl_option CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 0 0
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGFUN_REDBOOT_BOOT_SCRIPT
+ # ActiveIf: CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT || CYGSEM_REDBOOT_FLASH_CONFIG
+};
+
+# Resolution (in ms) for script timeout value.
+# This option controls the resolution of the script
+# timeout. The value is specified in milliseconds
+# (ms), thus to have the script timeout be defined in
+# terms of tenths of seconds, use 100.
+#
+cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_TIMEOUT_RESOLUTION {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 1000
+ # The inferred value should not be edited directly.
+ inferred_value 10
+ # value_source inferred
+ # Default value: 1000
+};
+
+# Script default timeout value
+# This option is used to set the default timeout for startup
+# scripts, when they are enabled.
+#
+cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_DEFAULT_TIMEOUT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 10
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 10
+};
+
+# <
+# Support RTC for time & date functions
+# When this option is enabled, RedBoot will support commands to
+# query and set the real time clock (time and date)
+#
+cdl_option CYGSEM_REDBOOT_RTC {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_IO_WALLCLOCK
+ # CYGPKG_IO_WALLCLOCK (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Behave like a ROM monitor
+# Enabling this option will allow RedBoot to provide ROM
+# monitor-style services to programs which it executes.
+#
+cdl_option CYGPRI_REDBOOT_ROM_MONITOR {
+ # ActiveIf constraint: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+ # Requires: CYGSEM_HAL_ROM_MONITOR
+ # CYGSEM_HAL_ROM_MONITOR == 1
+ # --> 1
+};
+
+# Allow RedBoot to handle GNUPro application 'syscalls'.
+# If this option is enabled then RedBoot will install a
+# syscall handler to support debugging of applications
+# based on GNUPro newlib/bsp.
+#
+cdl_component CYGSEM_REDBOOT_BSP_SYSCALLS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGOPT_HAL_ARM_SYSCALL_GPROF_SUPPORT
+ # ActiveIf: CYGSEM_REDBOOT_BSP_SYSCALLS
+ # option CYGPKG_HAL_GDB_FILEIO
+ # ActiveIf: CYGSEM_REDBOOT_BSP_SYSCALLS
+};
+
+# >
+# Support additional syscalls for 'gprof' profiling
+# Support additional syscalls to support a periodic callback
+# function for histogram-style profiling, and an enquire/set
+# of the tick rate.
+# The application must use the GNUPro newlib facilities
+# to set this up.
+#
+cdl_option CYGSEM_REDBOOT_BSP_SYSCALLS_GPROF {
+ # This option is not active
+ # The parent CYGSEM_REDBOOT_BSP_SYSCALLS is disabled
+ # ActiveIf constraint: 0 < CYGINT_REDBOOT_BSP_SYSCALLS_GPROF_SUPPORT
+ # CYGINT_REDBOOT_BSP_SYSCALLS_GPROF_SUPPORT == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Does the HAL support 'gprof' profiling?
+#
+cdl_interface CYGINT_REDBOOT_BSP_SYSCALLS_GPROF_SUPPORT {
+ # Implemented by CYGOPT_HAL_ARM_SYSCALL_GPROF_SUPPORT, inactive, enabled
+ # This option is not active
+ # The parent CYGSEM_REDBOOT_BSP_SYSCALLS is disabled
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_BSP_SYSCALLS_GPROF
+ # ActiveIf: 0 < CYGINT_REDBOOT_BSP_SYSCALLS_GPROF_SUPPORT
+};
+
+# Do not raise SIGTRAP when program exits
+# For some (single shot) newlib based programs,
+# exiting and returning a termination status may be
+# the normal expected behavior.
+#
+cdl_option CYGOPT_REDBOOT_BSP_SYSCALLS_EXIT_WITHOUT_TRAP {
+ # This option is not active
+ # The parent CYGSEM_REDBOOT_BSP_SYSCALLS is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Use a common buffer for Zlib and FIS
+# Use a common memory buffer for both the zlib workspace
+# and FIS directory operations. This can save a substantial
+# amount of RAM, especially when flash sectors are large.
+#
+cdl_component CYGOPT_REDBOOT_FIS_ZLIB_COMMON_BUFFER {
+ # ActiveIf constraint: CYGBLD_BUILD_REDBOOT_WITH_ZLIB && CYGOPT_REDBOOT_FIS
+ # CYGBLD_BUILD_REDBOOT_WITH_ZLIB == 1
+ # CYGOPT_REDBOOT_FIS == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# >
+# Size of Zlib/FIS common buffer
+# Size of common buffer to allocate. Must be at least the
+# size of one flash sector.
+#
+cdl_option CYGNUM_REDBOOT_FIS_ZLIB_COMMON_BUFFER_SIZE {
+ # This option is not active
+ # The parent CYGOPT_REDBOOT_FIS_ZLIB_COMMON_BUFFER is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x0000C000
+ # value_source default
+ # Default value: 0x0000C000
+ # Legal values: 0x4000 to 0x80000000
+};
+
+# <
+# Buffer size in getc when loading images
+# When loading images a buffer is used between redboot and the
+# underlying storage medium, eg a filesystem, or a socket etc.
+# The size of this buffer can have a big impart on load speed.
+#
+cdl_option CYGNUM_REDBOOT_GETC_BUFFER {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 256
+ # value_source default
+ # Default value: CYGPKG_REDBOOT_FILEIO ? 4096 : 256
+ # CYGPKG_REDBOOT_FILEIO == 0
+ # --> 256
+};
+
+# <
+# Redboot for ARM options
+# This option lists the target's requirements for a valid Redboot
+# configuration.
+#
+cdl_component CYGPKG_REDBOOT_ARM_OPTIONS {
+ # ActiveIf constraint: CYGPKG_REDBOOT
+ # CYGPKG_REDBOOT == current
+ # --> 1
+
+ # There is no associated value.
+
+ # The following properties are affected by this value
+};
+
+# >
+# Provide the exec command in RedBoot
+# This option contains requirements for booting linux
+# from RedBoot. The component is enabled/disabled from
+# RedBoots CDL.
+#
+cdl_component CYGPKG_REDBOOT_ARM_LINUX_EXEC {
+ # ActiveIf constraint: CYGBLD_BUILD_REDBOOT_WITH_EXEC
+ # CYGBLD_BUILD_REDBOOT_WITH_EXEC == 1
+ # --> 1
+
+ # There is no associated value.
+};
+
+# >
+# Enable -x switch for exec command.
+# This option allows bi-endian platforms to launch kernels
+# built for an endianess different than the RedBoot endianess
+#
+cdl_option CYGHWR_REDBOOT_LINUX_EXEC_X_SWITCH {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Physical base address of linux kernel
+# This is the physical address of the base of the
+# Linux kernel image.
+#
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0xA0108000
+ # value_source default
+ # Default value: CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT
+ # CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0xA0108000
+ # --> 0xA0108000
+};
+
+# Default physical base address of linux kernel
+# This is the physical address of the base of the
+# Linux kernel image. This option gets set by the
+# platform CDL.
+#
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00008000
+ # The inferred value should not be edited directly.
+ inferred_value 0xA0108000
+ # value_source inferred
+ # Default value: 0x00008000
+
+ # The following properties are affected by this value
+ # option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS
+ # DefaultValue: CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT
+ # component CYGPKG_REDBOOT_HAL_TX27_OPTIONS
+ # Requires: CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0xA0108000
+};
+
+# Base address of linux kernel parameter tags
+# This is the base address of the area of memory used to
+# pass parameters to the Linux kernel. This should be chosen
+# to avoid overlap with the kernel and any ramdisk image.
+#
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_TAGS_ADDRESS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00000100
+ # value_source default
+ # Default value: 0x00000100
+};
+
+# <
+# <
+# Redboot HAL options
+# This option lists the target's requirements for a valid Redboot
+# configuration.
+#
+cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ # ActiveIf constraint: CYGPKG_REDBOOT
+ # CYGPKG_REDBOOT == current
+ # --> 1
+
+ # There is no associated value.
+};
+
+# >
+# Build Redboot ROM binary image
+# This option enables the conversion of the Redboot ELF
+# image to a binary image suitable for ROM programming.
+#
+cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ # ActiveIf constraint: CYGBLD_BUILD_REDBOOT
+ # CYGBLD_BUILD_REDBOOT == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Redboot HAL variant options
+#
+cdl_component CYGPKG_REDBOOT_HAL_TX27_OPTIONS {
+ # ActiveIf constraint: CYGPKG_REDBOOT
+ # CYGPKG_REDBOOT == current
+ # --> 1
+
+ # There is no associated value.
+ # Requires: CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0xA0108000
+ # CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0xA0108000
+ # --> 1
+};
+
+# <
+# ISO C and POSIX infrastructure
+# eCos supports implementations of ISO C libraries and POSIX
+# implementations. This package provides infrastructure used by
+# all such implementations.
+#
+cdl_package CYGPKG_ISOINFRA {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGPKG_ISOINFRA
+ # package CYGPKG_LIBC_STRING
+ # Requires: CYGPKG_ISOINFRA
+ # package CYGPKG_COMPRESS_ZLIB
+ # Requires: CYGPKG_ISOINFRA
+ # package CYGPKG_IO_FLASH
+ # Requires: CYGPKG_ISOINFRA
+ # option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_USE_MEMCPY
+ # Requires: CYGPKG_ISOINFRA
+ # option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_USE_MEMCPY
+ # DefaultValue: 0 != CYGPKG_ISOINFRA
+ # component CYGPKG_MEMALLOC_MALLOC_ALLOCATORS
+ # ActiveIf: CYGPKG_ISOINFRA
+ # package CYGPKG_LIBC_I18N
+ # Requires: CYGPKG_ISOINFRA
+ # package CYGPKG_LIBC_STDLIB
+ # Requires: CYGPKG_ISOINFRA
+};
+
+# >
+# Startup and termination
+#
+cdl_component CYGPKG_ISO_STARTUP {
+ # There is no associated value.
+};
+
+# >
+# main() startup implementations
+# Implementations of this interface arrange for a user-supplied
+# main() to be called in an ISO compatible environment.
+#
+cdl_interface CYGINT_ISO_MAIN_STARTUP {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_MAIN_STARTUP
+ # CYGINT_ISO_MAIN_STARTUP == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_MAIN_STARTUP
+ # Requires: 1 >= CYGINT_ISO_MAIN_STARTUP
+};
+
+# environ implementations
+# Implementations of this interface provide the environ
+# variable required by POSIX.
+#
+cdl_interface CYGINT_ISO_ENVIRON {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_ENVIRON
+ # CYGINT_ISO_ENVIRON == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_ENVIRON
+ # Requires: 1 >= CYGINT_ISO_ENVIRON
+};
+
+# <
+# ctype.h functions
+#
+cdl_component CYGPKG_ISO_CTYPE_H {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of ctype functions
+#
+cdl_interface CYGINT_ISO_CTYPE {
+ # Implemented by CYGPKG_LIBC_I18N, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_CTYPE
+ # CYGINT_ISO_CTYPE == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_CTYPE
+ # Requires: 1 >= CYGINT_ISO_CTYPE
+ # package CYGPKG_HAL_ARM_TX27KARO
+ # Requires: CYGINT_ISO_CTYPE
+ # option CYGFUN_LIBC_STRING_BSD_FUNCS
+ # Requires: CYGINT_ISO_CTYPE
+ # package CYGPKG_LIBC_STDLIB
+ # Requires: CYGINT_ISO_CTYPE
+};
+
+# Ctype implementation header
+#
+cdl_option CYGBLD_ISO_CTYPE_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/i18n/ctype.inl>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGPKG_LIBC_I18N_NEWLIB_CTYPE
+ # Requires: CYGBLD_ISO_CTYPE_HEADER == "<cyg/libc/i18n/newlibctype.h>"
+ # option CYGIMP_LIBC_I18N_CTYPE_INLINES
+ # Requires: CYGBLD_ISO_CTYPE_HEADER == "<cyg/libc/i18n/ctype.inl>"
+};
+
+# <
+# Error handling
+#
+cdl_component CYGPKG_ISO_ERRNO {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of error codes
+#
+cdl_interface CYGINT_ISO_ERRNO_CODES {
+ # Implemented by CYGPKG_ERROR, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_ERRNO_CODES
+ # CYGINT_ISO_ERRNO_CODES == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_ERRNO_CODES
+ # Requires: 1 >= CYGINT_ISO_ERRNO_CODES
+};
+
+# Error codes implementation header
+#
+cdl_option CYGBLD_ISO_ERRNO_CODES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/error/codes.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # package CYGPKG_ERROR
+ # Requires: CYGBLD_ISO_ERRNO_CODES_HEADER == "<cyg/error/codes.h>"
+};
+
+# Number of implementations of errno variable
+#
+cdl_interface CYGINT_ISO_ERRNO {
+ # Implemented by CYGPKG_ERROR_ERRNO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_ERRNO
+ # CYGINT_ISO_ERRNO == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_ERRNO
+ # Requires: 1 >= CYGINT_ISO_ERRNO
+};
+
+# errno variable implementation header
+#
+cdl_option CYGBLD_ISO_ERRNO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/error/errno.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # component CYGPKG_ERROR_ERRNO
+ # Requires: CYGBLD_ISO_ERRNO_HEADER == "<cyg/error/errno.h>"
+};
+
+# <
+# Locale-related functions
+#
+cdl_component CYGPKG_ISO_LOCALE {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of locale functions
+#
+cdl_interface CYGINT_ISO_LOCALE {
+ # Implemented by CYGPKG_LIBC_I18N, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_LOCALE
+ # CYGINT_ISO_LOCALE == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_LOCALE
+ # Requires: 1 >= CYGINT_ISO_LOCALE
+};
+
+# Locale implementation header
+#
+cdl_option CYGBLD_ISO_LOCALE_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Standard I/O-related functionality
+#
+cdl_component CYGPKG_ISO_STDIO {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of stdio file types
+#
+cdl_interface CYGINT_ISO_STDIO_FILETYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILETYPES
+ # CYGINT_ISO_STDIO_FILETYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_FILETYPES
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILETYPES
+};
+
+# Stdio file types implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_FILETYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Stdio standard streams implementations
+#
+cdl_interface CYGINT_ISO_STDIO_STREAMS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_STREAMS
+ # CYGINT_ISO_STDIO_STREAMS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_STREAMS
+ # Requires: 1 >= CYGINT_ISO_STDIO_STREAMS
+};
+
+# Stdio standard streams implementation header
+# This header file must define stdin, stdout
+# and stderr.
+#
+cdl_option CYGBLD_ISO_STDIO_STREAMS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio file operations
+#
+cdl_interface CYGINT_ISO_STDIO_FILEOPS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEOPS
+ # CYGINT_ISO_STDIO_FILEOPS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_FILEOPS
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEOPS
+};
+
+# Stdio file operations implementation header
+# This header controls the file system operations on a file
+# such as remove(), rename(), tmpfile(), tmpnam() and associated
+# constants.
+#
+cdl_option CYGBLD_ISO_STDIO_FILEOPS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio file access functionals
+#
+cdl_interface CYGINT_ISO_STDIO_FILEACCESS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEACCESS
+ # CYGINT_ISO_STDIO_FILEACCESS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_FILEACCESS
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEACCESS
+ # option CYGFUN_COMPRESS_ZLIB_GZIO
+ # Requires: CYGINT_ISO_STDIO_FILEACCESS
+};
+
+# Stdio file access implementation header
+# This header controls the file access operations
+# such as fclose(), fflush(), fopen(), freopen(), setbuf(),
+# setvbuf(), and associated constants.
+#
+cdl_option CYGBLD_ISO_STDIO_FILEACCESS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio formatted I/O
+#
+cdl_interface CYGINT_ISO_STDIO_FORMATTED_IO {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_FORMATTED_IO
+ # CYGINT_ISO_STDIO_FORMATTED_IO == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_FORMATTED_IO
+ # Requires: 1 >= CYGINT_ISO_STDIO_FORMATTED_IO
+ # option CYGFUN_COMPRESS_ZLIB_GZIO
+ # Requires: CYGINT_ISO_STDIO_FORMATTED_IO
+};
+
+# Stdio formatted I/O implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_FORMATTED_IO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio character I/O
+#
+cdl_interface CYGINT_ISO_STDIO_CHAR_IO {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_CHAR_IO
+ # CYGINT_ISO_STDIO_CHAR_IO == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_CHAR_IO
+ # Requires: 1 >= CYGINT_ISO_STDIO_CHAR_IO
+};
+
+# Stdio character I/O implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_CHAR_IO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio direct I/O
+#
+cdl_interface CYGINT_ISO_STDIO_DIRECT_IO {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_DIRECT_IO
+ # CYGINT_ISO_STDIO_DIRECT_IO == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_DIRECT_IO
+ # Requires: 1 >= CYGINT_ISO_STDIO_DIRECT_IO
+};
+
+# Stdio direct I/O implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_DIRECT_IO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio file positioning
+#
+cdl_interface CYGINT_ISO_STDIO_FILEPOS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEPOS
+ # CYGINT_ISO_STDIO_FILEPOS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_FILEPOS
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEPOS
+ # option CYGFUN_COMPRESS_ZLIB_GZIO
+ # Requires: CYGINT_ISO_STDIO_FILEPOS
+};
+
+# Stdio file positioning implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_FILEPOS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio error handling
+#
+cdl_interface CYGINT_ISO_STDIO_ERROR {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_ERROR
+ # CYGINT_ISO_STDIO_ERROR == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_ERROR
+ # Requires: 1 >= CYGINT_ISO_STDIO_ERROR
+};
+
+# Stdio error handling implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_ERROR_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX fd-related function implementations
+#
+cdl_interface CYGINT_ISO_STDIO_POSIX_FDFUNCS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_POSIX_FDFUNCS
+ # CYGINT_ISO_STDIO_POSIX_FDFUNCS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_POSIX_FDFUNCS
+ # Requires: 1 >= CYGINT_ISO_STDIO_POSIX_FDFUNCS
+};
+
+# POSIX fd-related function implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_POSIX_FDFUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Standard general utility functions
+#
+cdl_component CYGPKG_ISO_STDLIB {
+ # There is no associated value.
+};
+
+# >
+# String conversion function implementations
+#
+cdl_interface CYGINT_ISO_STDLIB_STRCONV {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_STRCONV
+ # CYGINT_ISO_STDLIB_STRCONV == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDLIB_STRCONV
+ # Requires: 1 >= CYGINT_ISO_STDLIB_STRCONV
+};
+
+# String conversion function implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_STRCONV_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/stdlib/atox.inl>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGIMP_LIBC_STDLIB_INLINE_ATOX
+ # Requires: CYGBLD_ISO_STDLIB_STRCONV_HEADER == "<cyg/libc/stdlib/atox.inl>"
+};
+
+# String to FP conversion function implementations
+#
+cdl_interface CYGINT_ISO_STDLIB_STRCONV_FLOAT {
+ # Implemented by CYGFUN_LIBC_strtod, active, disabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_STDLIB_STRCONV_FLOAT
+ # CYGINT_ISO_STDLIB_STRCONV_FLOAT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDLIB_STRCONV_FLOAT
+ # Requires: 1 >= CYGINT_ISO_STDLIB_STRCONV_FLOAT
+};
+
+# String to FP conversion function implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_STRCONV_FLOAT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Random number generator implementations
+#
+cdl_interface CYGINT_ISO_RAND {
+ # Implemented by CYGIMP_LIBC_RAND_SIMPLEST, active, disabled
+ # Implemented by CYGIMP_LIBC_RAND_SIMPLE1, active, disabled
+ # Implemented by CYGIMP_LIBC_RAND_KNUTH1, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_RAND
+ # CYGINT_ISO_RAND == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_RAND
+ # Requires: 1 >= CYGINT_ISO_RAND
+};
+
+# Random number generator implementation header
+#
+cdl_option CYGBLD_ISO_RAND_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Malloc implementations
+#
+cdl_interface CYGINT_ISO_MALLOC {
+ # Implemented by CYGPKG_MEMALLOC_MALLOC_ALLOCATORS, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_MALLOC
+ # CYGINT_ISO_MALLOC == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_MALLOC
+ # Requires: 1 >= CYGINT_ISO_MALLOC
+ # option CYGFUN_LIBC_STRING_STRDUP
+ # ActiveIf: CYGINT_ISO_MALLOC
+};
+
+# Malloc implementation header
+#
+cdl_option CYGBLD_ISO_MALLOC_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Mallinfo() implementations
+#
+cdl_interface CYGINT_ISO_MALLINFO {
+ # Implemented by CYGPKG_MEMALLOC_MALLOC_ALLOCATORS, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_MALLINFO
+ # CYGINT_ISO_MALLINFO == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_MALLINFO
+ # Requires: 1 >= CYGINT_ISO_MALLINFO
+};
+
+# Mallinfo() implementation header
+#
+cdl_option CYGBLD_ISO_MALLINFO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Program exit functionality implementations
+#
+cdl_interface CYGINT_ISO_EXIT {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_EXIT
+ # CYGINT_ISO_EXIT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_EXIT
+ # Requires: 1 >= CYGINT_ISO_EXIT
+ # option CYGFUN_INFRA_DUMMY_ABORT
+ # Requires: !CYGINT_ISO_EXIT
+ # option CYGFUN_INFRA_DUMMY_ABORT
+ # DefaultValue: CYGINT_ISO_EXIT == 0
+};
+
+# Program exit functionality implementation header
+#
+cdl_option CYGBLD_ISO_EXIT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Program environment implementations
+#
+cdl_interface CYGINT_ISO_STDLIB_ENVIRON {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_ENVIRON
+ # CYGINT_ISO_STDLIB_ENVIRON == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDLIB_ENVIRON
+ # Requires: 1 >= CYGINT_ISO_STDLIB_ENVIRON
+};
+
+# Program environment implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_ENVIRON_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# system() implementations
+#
+cdl_interface CYGINT_ISO_STDLIB_SYSTEM {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_SYSTEM
+ # CYGINT_ISO_STDLIB_SYSTEM == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDLIB_SYSTEM
+ # Requires: 1 >= CYGINT_ISO_STDLIB_SYSTEM
+};
+
+# system() implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_SYSTEM_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# bsearch() implementations
+#
+cdl_interface CYGINT_ISO_BSEARCH {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_BSEARCH
+ # CYGINT_ISO_BSEARCH == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_BSEARCH
+ # Requires: 1 >= CYGINT_ISO_BSEARCH
+};
+
+# bsearch() implementation header
+#
+cdl_option CYGBLD_ISO_BSEARCH_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# qsort() implementations
+#
+cdl_interface CYGINT_ISO_QSORT {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_QSORT
+ # CYGINT_ISO_STDLIB_QSORT (unknown) == 0
+ # --> 1
+
+ # The following properties are affected by this value
+};
+
+# qsort() implementation header
+#
+cdl_option CYGBLD_ISO_QSORT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# abs()/labs() implementations
+#
+cdl_interface CYGINT_ISO_ABS {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_ABS
+ # CYGINT_ISO_STDLIB_ABS (unknown) == 0
+ # --> 1
+
+ # The following properties are affected by this value
+};
+
+# abs()/labs() implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_ABS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/stdlib/abs.inl>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGIMP_LIBC_STDLIB_INLINE_ABS
+ # Requires: CYGBLD_ISO_STDLIB_ABS_HEADER == "<cyg/libc/stdlib/abs.inl>"
+};
+
+# div()/ldiv() implementations
+#
+cdl_interface CYGINT_ISO_DIV {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_DIV
+ # CYGINT_ISO_STDLIB_DIV (unknown) == 0
+ # --> 1
+
+ # The following properties are affected by this value
+};
+
+# div()/ldiv() implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_DIV_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/stdlib/div.inl>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGIMP_LIBC_STDLIB_INLINE_DIV
+ # Requires: CYGBLD_ISO_STDLIB_DIV_HEADER == "<cyg/libc/stdlib/div.inl>"
+};
+
+# Header defining the implementation's MB_CUR_MAX
+#
+cdl_option CYGBLD_ISO_STDLIB_MB_CUR_MAX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # interface CYGINT_LIBC_I18N_MB_REQUIRED
+ # Requires: CYGBLD_ISO_STDLIB_MB_CUR_MAX_HEADER == "<cyg/libc/i18n/mb.h>"
+};
+
+# Multibyte character implementations
+#
+cdl_interface CYGINT_ISO_STDLIB_MULTIBYTE {
+ # Implemented by CYGPKG_LIBC_I18N, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_MULTIBYTE
+ # CYGINT_ISO_STDLIB_MULTIBYTE == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDLIB_MULTIBYTE
+ # Requires: 1 >= CYGINT_ISO_STDLIB_MULTIBYTE
+};
+
+# Multibyte character implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_MULTIBYTE_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# String functions
+#
+cdl_component CYGPKG_ISO_STRING {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of strerror() function
+#
+cdl_interface CYGINT_ISO_STRERROR {
+ # Implemented by CYGPKG_ERROR_STRERROR, active, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 1
+ # Requires: 1 >= CYGINT_ISO_STRERROR
+ # CYGINT_ISO_STRERROR == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRERROR
+ # Requires: 1 >= CYGINT_ISO_STRERROR
+};
+
+# strerror() implementation header
+#
+cdl_option CYGBLD_ISO_STRERROR_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/error/strerror.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGPKG_ERROR_STRERROR
+ # Requires: CYGBLD_ISO_STRERROR_HEADER == "<cyg/error/strerror.h>"
+};
+
+# memcpy() implementation header
+#
+cdl_option CYGBLD_ISO_MEMCPY_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# memset() implementation header
+#
+cdl_option CYGBLD_ISO_MEMSET_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of strtok_r() function
+#
+cdl_interface CYGINT_ISO_STRTOK_R {
+ # Implemented by CYGPKG_LIBC_STRING, active, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 1
+ # Requires: 1 >= CYGINT_ISO_STRTOK_R
+ # CYGINT_ISO_STRTOK_R == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRTOK_R
+ # Requires: 1 >= CYGINT_ISO_STRTOK_R
+};
+
+# strtok_r() implementation header
+#
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/string/string.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # package CYGPKG_LIBC_STRING
+ # Requires: CYGBLD_ISO_STRTOK_R_HEADER == "<cyg/libc/string/string.h>"
+};
+
+# Number of implementations of locale-specific string functions
+# This covers locale-dependent string functions such as strcoll()
+# and strxfrm().
+#
+cdl_interface CYGINT_ISO_STRING_LOCALE_FUNCS {
+ # Implemented by CYGPKG_LIBC_STRING, active, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 1
+ # Requires: 1 >= CYGINT_ISO_STRING_LOCALE_FUNCS
+ # CYGINT_ISO_STRING_LOCALE_FUNCS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRING_LOCALE_FUNCS
+ # Requires: 1 >= CYGINT_ISO_STRING_LOCALE_FUNCS
+};
+
+# Locale-specific string functions' implementation header
+# This covers locale-dependent string functions such as strcoll()
+# and strxfrm().
+#
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/string/string.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # package CYGPKG_LIBC_STRING
+ # Requires: CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER == "<cyg/libc/string/string.h>"
+};
+
+# Number of implementations of BSD string functions
+#
+cdl_interface CYGINT_ISO_STRING_BSD_FUNCS {
+ # Implemented by CYGFUN_LIBC_STRING_BSD_FUNCS, active, disabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STRING_BSD_FUNCS
+ # CYGINT_ISO_STRING_BSD_FUNCS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRING_BSD_FUNCS
+ # Requires: 1 >= CYGINT_ISO_STRING_BSD_FUNCS
+};
+
+# BSD string functions' implementation header
+#
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGFUN_LIBC_STRING_BSD_FUNCS
+ # Requires: CYGBLD_ISO_STRING_BSD_FUNCS_HEADER == "<cyg/libc/string/bsdstring.h>"
+};
+
+# Number of implementations of other mem*() functions
+#
+cdl_interface CYGINT_ISO_STRING_MEMFUNCS {
+ # Implemented by CYGPKG_LIBC_STRING, active, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 1
+ # Requires: 1 >= CYGINT_ISO_STRING_MEMFUNCS
+ # CYGINT_ISO_STRING_MEMFUNCS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRING_MEMFUNCS
+ # Requires: 1 >= CYGINT_ISO_STRING_MEMFUNCS
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGINT_ISO_STRING_MEMFUNCS
+ # component CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
+ # Requires: CYGINT_ISO_STRING_MEMFUNCS
+};
+
+# Other mem*() functions' implementation header
+#
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/string/string.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # package CYGPKG_LIBC_STRING
+ # Requires: CYGBLD_ISO_STRING_MEMFUNCS_HEADER == "<cyg/libc/string/string.h>"
+};
+
+# Number of implementations of other ISO C str*() functions
+# This covers the other str*() functions defined by ISO C.
+#
+cdl_interface CYGINT_ISO_STRING_STRFUNCS {
+ # Implemented by CYGPKG_LIBC_STRING, active, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 1
+ # Requires: 1 >= CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRING_STRFUNCS
+ # Requires: 1 >= CYGINT_ISO_STRING_STRFUNCS
+ # option CYGFUN_INFRA_DUMMY_STRLEN
+ # Requires: !CYGINT_ISO_STRING_STRFUNCS
+ # option CYGFUN_INFRA_DUMMY_STRLEN
+ # DefaultValue: CYGINT_ISO_STRING_STRFUNCS == 0
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # component CYGPKG_IO_ETH_DRIVERS_NET
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # option CYGFUN_COMPRESS_ZLIB_GZIO
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # package CYGPKG_IO_FLASH
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # package CYGPKG_LIBC_STDLIB
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+};
+
+# Other ISO C str*() functions' implementation header
+# This covers the other str*() functions defined by ISO C.
+#
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/string/string.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # package CYGPKG_LIBC_STRING
+ # Requires: CYGBLD_ISO_STRING_STRFUNCS_HEADER == "<cyg/libc/string/string.h>"
+};
+
+# <
+# Clock and time functionality
+#
+cdl_component CYGPKG_ISO_TIME {
+ # There is no associated value.
+};
+
+# >
+# time_t implementation header
+#
+cdl_option CYGBLD_ISO_TIME_T_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# clock_t implementation header
+#
+cdl_option CYGBLD_ISO_CLOCK_T_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# struct timeval implementation header
+#
+cdl_option CYGBLD_ISO_STRUCTTIMEVAL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# fnmatch implementation header
+#
+cdl_option CYGBLD_ISO_FNMATCH_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of POSIX timer types
+#
+cdl_interface CYGINT_ISO_POSIX_TIMER_TYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMER_TYPES
+ # CYGINT_ISO_POSIX_TIMER_TYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_TIMER_TYPES
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMER_TYPES
+};
+
+# POSIX timer types implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_TIMER_TYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of POSIX clock types
+#
+cdl_interface CYGINT_ISO_POSIX_CLOCK_TYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_CLOCK_TYPES
+ # CYGINT_ISO_POSIX_CLOCK_TYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_CLOCK_TYPES
+ # Requires: 1 >= CYGINT_ISO_POSIX_CLOCK_TYPES
+};
+
+# POSIX clock types implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_CLOCK_TYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of ISO C types
+#
+cdl_interface CYGINT_ISO_C_TIME_TYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_C_TIME_TYPES
+ # CYGINT_ISO_C_TIME_TYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_C_TIME_TYPES
+ # Requires: 1 >= CYGINT_ISO_C_TIME_TYPES
+};
+
+# ISO C time types implementation header
+#
+cdl_option CYGBLD_ISO_C_TIME_TYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of POSIX timers
+#
+cdl_interface CYGINT_ISO_POSIX_TIMERS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMERS
+ # CYGINT_ISO_POSIX_TIMERS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_TIMERS
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMERS
+};
+
+# POSIX timer implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_TIMERS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of POSIX clocks
+#
+cdl_interface CYGINT_ISO_POSIX_CLOCKS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_CLOCKS
+ # CYGINT_ISO_POSIX_CLOCKS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_CLOCKS
+ # Requires: 1 >= CYGINT_ISO_POSIX_CLOCKS
+};
+
+# POSIX clocks implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_CLOCKS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of ISO C clock functions
+#
+cdl_interface CYGINT_ISO_C_CLOCK_FUNCS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_C_CLOCK_FUNCS
+ # CYGINT_ISO_C_CLOCK_FUNCS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_C_CLOCK_FUNCS
+ # Requires: 1 >= CYGINT_ISO_C_CLOCK_FUNCS
+};
+
+# ISO C clock functions' implementation header
+#
+cdl_option CYGBLD_ISO_C_CLOCK_FUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of tzset() function
+#
+cdl_interface CYGINT_ISO_TZSET {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_TZSET
+ # CYGINT_ISO_TZSET == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_TZSET
+ # Requires: 1 >= CYGINT_ISO_TZSET
+};
+
+# tzset() implementation header
+#
+cdl_option CYGBLD_ISO_TZSET_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Signal functionality
+#
+cdl_component CYGPKG_ISO_SIGNAL {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of signal numbers
+#
+cdl_interface CYGINT_ISO_SIGNAL_NUMBERS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SIGNAL_NUMBERS
+ # CYGINT_ISO_SIGNAL_NUMBERS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SIGNAL_NUMBERS
+ # Requires: 1 >= CYGINT_ISO_SIGNAL_NUMBERS
+};
+
+# Signal numbering implementation header
+# This header provides the mapping of signal
+# names (e.g. SIGBUS) to numbers.
+#
+cdl_option CYGBLD_ISO_SIGNAL_NUMBERS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of signal implementations
+#
+cdl_interface CYGINT_ISO_SIGNAL_IMPL {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SIGNAL_IMPL
+ # CYGINT_ISO_SIGNAL_IMPL == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SIGNAL_IMPL
+ # Requires: 1 >= CYGINT_ISO_SIGNAL_IMPL
+};
+
+# Signals implementation header
+#
+cdl_option CYGBLD_ISO_SIGNAL_IMPL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX real time signals feature test macro
+# This defines the POSIX feature test macro
+# that indicates that the POSIX real time signals
+# are present.
+#
+cdl_interface CYGINT_POSIX_REALTIME_SIGNALS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_POSIX_REALTIME_SIGNALS
+ # CYGINT_POSIX_REALTIME_SIGNALS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_POSIX_REALTIME_SIGNALS
+ # Requires: 1 >= CYGINT_POSIX_REALTIME_SIGNALS
+};
+
+# <
+# Non-local jumps functionality
+#
+cdl_component CYGPKG_ISO_SETJMP {
+ # There is no associated value.
+};
+
+# >
+# setjmp() / longjmp() implementations
+#
+cdl_interface CYGINT_ISO_SETJMP {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SETJMP
+ # CYGINT_ISO_SETJMP == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SETJMP
+ # Requires: 1 >= CYGINT_ISO_SETJMP
+};
+
+# setjmp() / longjmp() implementation header
+#
+cdl_option CYGBLD_ISO_SETJMP_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# sigsetjmp() / siglongjmp() implementations
+#
+cdl_interface CYGINT_ISO_SIGSETJMP {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SIGSETJMP
+ # CYGINT_ISO_SIGSETJMP == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SIGSETJMP
+ # Requires: 1 >= CYGINT_ISO_SIGSETJMP
+};
+
+# sigsetjmp() / siglongjmp() implementation header
+#
+cdl_option CYGBLD_ISO_SIGSETJMP_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Assertions implementation header
+#
+cdl_option CYGBLD_ISO_ASSERT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX file control
+# This covers the POSIX file control definitions,
+# normally found in <fcntl.h>
+#
+cdl_component CYGPKG_ISO_POSIX_FCNTL {
+ # There is no associated value.
+};
+
+# >
+# POSIX open flags implementation header
+#
+cdl_option CYGBLD_ISO_OFLAG_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX fcntl() implementations
+#
+cdl_interface CYGINT_ISO_FCNTL {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_FCNTL
+ # CYGINT_ISO_FCNTL == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_FCNTL
+ # Requires: 1 >= CYGINT_ISO_FCNTL
+};
+
+# POSIX fcntl() implementation header
+#
+cdl_option CYGBLD_ISO_FCNTL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX file open implementations
+#
+cdl_interface CYGINT_ISO_OPEN {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_OPEN
+ # CYGINT_ISO_OPEN == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_OPEN
+ # Requires: 1 >= CYGINT_ISO_OPEN
+};
+
+# POSIX file open implementation header
+#
+cdl_option CYGBLD_ISO_OPEN_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# <sys/stat.h> definitions implementation header
+#
+cdl_option CYGBLD_ISO_STAT_DEFS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX directory reading implementation
+#
+cdl_interface CYGINT_ISO_DIRENT {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_DIRENT
+ # CYGINT_ISO_DIRENT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_DIRENT
+ # Requires: 1 >= CYGINT_ISO_DIRENT
+};
+
+# <dirent.h> definitions implementation header
+#
+cdl_option CYGBLD_ISO_DIRENT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX <sys/types.h> contents
+# This covers the types required by POSIX to be in
+# <sys/types.h>
+#
+cdl_component CYGPKG_ISO_POSIX_TYPES {
+ # There is no associated value.
+};
+
+# >
+# POSIX thread types implementations
+#
+cdl_interface CYGINT_ISO_PTHREADTYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_PTHREADTYPES
+ # CYGINT_ISO_PTHREADTYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_PTHREADTYPES
+ # Requires: 1 >= CYGINT_ISO_PTHREADTYPES
+ # interface CYGINT_ISO_PMUTEXTYPES
+ # Requires: 1 >= CYGINT_ISO_PTHREADTYPES
+};
+
+# POSIX thread types implementation header
+#
+cdl_option CYGBLD_ISO_PTHREADTYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX mutex types implementations
+#
+cdl_interface CYGINT_ISO_PMUTEXTYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_PTHREADTYPES
+ # CYGINT_ISO_PTHREADTYPES == 0
+ # --> 1
+};
+
+# POSIX mutex types implementation header
+#
+cdl_option CYGBLD_ISO_PMUTEXTYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# ssize_t implementation header
+#
+cdl_option CYGBLD_ISO_SSIZE_T_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Filesystem types implementation header
+#
+cdl_option CYGBLD_ISO_FSTYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# gid_t, pid_t, uid_t implementation header
+#
+cdl_option CYGBLD_ISO_SCHEDTYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Non-POSIX <sys/types.h> contents
+# This covers the extra types required by non-POSIX
+# packages to be in <sys/types.h>. These would normally
+# only be visible if _POSIX_SOURCE is not defined.
+#
+cdl_component CYGPKG_ISO_EXTRA_TYPES {
+ # There is no associated value.
+};
+
+# >
+# BSD compatible types
+#
+cdl_interface CYGINT_ISO_BSDTYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_BSDTYPES
+ # CYGINT_ISO_BSDTYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_BSDTYPES
+ # Requires: 1 >= CYGINT_ISO_BSDTYPES
+};
+
+# BSD types header
+#
+cdl_option CYGBLD_ISO_BSDTYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Utsname structure
+#
+cdl_component CYGPKG_ISO_UTSNAME {
+ # There is no associated value.
+};
+
+# >
+# Utsname header
+#
+cdl_option CYGBLD_ISO_UTSNAME_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# POSIX scheduler
+#
+cdl_component CYGPKG_ISO_SCHED {
+ # There is no associated value.
+};
+
+# >
+# POSIX scheduler implementations
+#
+cdl_interface CYGINT_ISO_SCHED_IMPL {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SCHED_IMPL
+ # CYGINT_ISO_SCHED_IMPL == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SCHED_IMPL
+ # Requires: 1 >= CYGINT_ISO_SCHED_IMPL
+};
+
+# POSIX scheduler implementation header
+#
+cdl_option CYGBLD_ISO_SCHED_IMPL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# POSIX semaphores
+#
+cdl_component CYGPKG_ISO_SEMAPHORES {
+ # There is no associated value.
+};
+
+# >
+# POSIX semaphore implementations
+#
+cdl_interface CYGINT_ISO_SEMAPHORES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SEMAPHORES
+ # CYGINT_ISO_SEMAPHORES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SEMAPHORES
+ # Requires: 1 >= CYGINT_ISO_SEMAPHORES
+};
+
+# POSIX semaphore implementation header
+#
+cdl_option CYGBLD_ISO_SEMAPHORES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# POSIX message queues
+#
+cdl_component CYGPKG_ISO_MQUEUE {
+ # There is no associated value.
+};
+
+# >
+# Implementations
+#
+cdl_interface CYGINT_ISO_MQUEUE {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_MQUEUE
+ # CYGINT_ISO_MQUEUE == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_MQUEUE
+ # Requires: 1 >= CYGINT_ISO_MQUEUE
+ # option CYGNUM_ISO_MQUEUE_OPEN_MAX
+ # ActiveIf: CYGINT_ISO_MQUEUE
+ # option CYGNUM_ISO_MQUEUE_PRIO_MAX
+ # ActiveIf: CYGINT_ISO_MQUEUE
+};
+
+# Implementation header
+#
+cdl_option CYGBLD_ISO_MQUEUE_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Maximum number of open message queues
+#
+cdl_option CYGNUM_ISO_MQUEUE_OPEN_MAX {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_ISO_MQUEUE
+ # CYGINT_ISO_MQUEUE == 0
+ # --> 0
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYGNUM_POSIX_MQUEUE_OPEN_MAX > 0 ? CYGNUM_POSIX_MQUEUE_OPEN_MAX : 0
+ # CYGNUM_POSIX_MQUEUE_OPEN_MAX (unknown) == 0
+ # CYGNUM_POSIX_MQUEUE_OPEN_MAX (unknown) == 0
+ # --> 0 0
+};
+
+# Maximum number of message priorities
+#
+cdl_option CYGNUM_ISO_MQUEUE_PRIO_MAX {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_ISO_MQUEUE
+ # CYGINT_ISO_MQUEUE == 0
+ # --> 0
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 1 65535
+ # value_source default
+ # Default value: 1 65535
+};
+
+# <
+# POSIX threads
+#
+cdl_component CYGPKG_ISO_PTHREAD {
+ # There is no associated value.
+};
+
+# >
+# POSIX pthread implementations
+#
+cdl_interface CYGINT_ISO_PTHREAD_IMPL {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_PTHREAD_IMPL
+ # CYGINT_ISO_PTHREAD_IMPL == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_PTHREAD_IMPL
+ # Requires: 1 >= CYGINT_ISO_PTHREAD_IMPL
+};
+
+# POSIX pthread implementation header
+#
+cdl_option CYGBLD_ISO_PTHREAD_IMPL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX mutex/cond var implementations
+#
+cdl_interface CYGINT_ISO_PTHREAD_MUTEX {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_PTHREAD_MUTEX
+ # CYGINT_ISO_PTHREAD_MUTEX == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_PTHREAD_MUTEX
+ # Requires: 1 >= CYGINT_ISO_PTHREAD_MUTEX
+};
+
+# POSIX mutex/cond var implementation header
+#
+cdl_option CYGBLD_ISO_PTHREAD_MUTEX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Limits
+#
+cdl_component CYGPKG_ISO_LIMITS {
+ # There is no associated value.
+};
+
+# >
+# POSIX pthread limits implementations
+#
+cdl_interface CYGINT_ISO_POSIX_LIMITS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_LIMITS
+ # CYGINT_ISO_POSIX_LIMITS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_LIMITS
+ # Requires: 1 >= CYGINT_ISO_POSIX_LIMITS
+};
+
+# POSIX pthread limits implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_LIMITS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# OPEN_MAX implementation header
+#
+cdl_option CYGBLD_ISO_OPEN_MAX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# LINK_MAX implementation header
+#
+cdl_option CYGBLD_ISO_LINK_MAX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# NAME_MAX implementation header
+#
+cdl_option CYGBLD_ISO_NAME_MAX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# PATH_MAX implementation header
+#
+cdl_option CYGBLD_ISO_PATH_MAX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# POSIX termios
+#
+cdl_component CYGPKG_ISO_TERMIOS {
+ # There is no associated value.
+};
+
+# >
+# POSIX termios implementations
+#
+cdl_interface CYGINT_ISO_TERMIOS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_TERMIOS
+ # CYGINT_ISO_TERMIOS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_TERMIOS
+ # Requires: 1 >= CYGINT_ISO_TERMIOS
+};
+
+# POSIX termios implementation header
+#
+cdl_option CYGBLD_ISO_TERMIOS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Dynamic load API
+#
+cdl_component CYGPKG_ISO_DLFCN {
+ # There is no associated value.
+};
+
+# >
+# Dynamic load implementations
+#
+cdl_interface CYGINT_ISO_DLFCN {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_DLFCN
+ # CYGINT_ISO_DLFCN == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_DLFCN
+ # Requires: 1 >= CYGINT_ISO_DLFCN
+};
+
+# Dynamic load implementation header
+#
+cdl_option CYGBLD_ISO_DLFCN_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# UNIX standard functions
+#
+cdl_component CYGPKG_ISO_UNISTD {
+ # There is no associated value.
+};
+
+# >
+# POSIX timer operations implementations
+#
+cdl_interface CYGINT_ISO_POSIX_TIMER_OPS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMER_OPS
+ # CYGINT_ISO_POSIX_TIMER_OPS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_TIMER_OPS
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMER_OPS
+};
+
+# POSIX timer operations implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_TIMER_OPS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX sleep() implementations
+#
+cdl_interface CYGINT_ISO_POSIX_SLEEP {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_SLEEP
+ # CYGINT_ISO_POSIX_SLEEP == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_SLEEP
+ # Requires: 1 >= CYGINT_ISO_POSIX_SLEEP
+};
+
+# POSIX sleep() implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_SLEEP_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# select()/poll() functions
+#
+cdl_component CYGPKG_ISO_SELECT {
+ # There is no associated value.
+};
+
+# >
+# select() implementations
+#
+cdl_interface CYGINT_ISO_SELECT {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_SELECT
+ # CYGINT_ISO_SELECT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SELECT
+ # Requires: 1 >= CYGINT_ISO_SELECT
+};
+
+# select() implementation header
+#
+cdl_option CYGBLD_ISO_SELECT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# poll() implementations
+#
+cdl_interface CYGINT_ISO_POLL {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POLL
+ # CYGINT_ISO_POLL == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POLL
+ # Requires: 1 >= CYGINT_ISO_POLL
+};
+
+# poll() implementation header
+#
+cdl_option CYGBLD_ISO_POLL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# NetDB utility functions
+#
+cdl_component CYGPKG_ISO_NETDB {
+ # There is no associated value.
+};
+
+# >
+# DNS implementations
+#
+cdl_interface CYGINT_ISO_DNS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: bool
+ # Current value: 0
+ # Requires: 1 >= CYGINT_ISO_DNS
+ # CYGINT_ISO_DNS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_DNS
+ # Requires: 1 >= CYGINT_ISO_DNS
+};
+
+# DNS implementation header
+#
+cdl_option CYGBLD_ISO_DNS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Protocol network database implementations
+#
+cdl_interface CYGINT_ISO_NETDB_PROTO {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: bool
+ # Current value: 0
+ # Requires: 1 >= CYGINT_ISO_NETDB_PROTO
+ # CYGINT_ISO_NETDB_PROTO == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_NETDB_PROTO
+ # Requires: 1 >= CYGINT_ISO_NETDB_PROTO
+};
+
+# Protocol network database implementation header
+#
+cdl_option CYGBLD_ISO_NETDB_PROTO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Services network database implementations
+#
+cdl_interface CYGINT_ISO_NETDB_SERV {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: bool
+ # Current value: 0
+ # Requires: 1 >= CYGINT_ISO_NETDB_SERV
+ # CYGINT_ISO_NETDB_SERV == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_NETDB_SERV
+ # Requires: 1 >= CYGINT_ISO_NETDB_SERV
+};
+
+# Services network database implementation header
+#
+cdl_option CYGBLD_ISO_NETDB_SERV_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_ISOINFRA_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the ISO C and POSIX infrastructure package.
+# These flags are used in addition to the set of global flags.
+#
+cdl_option CYGPKG_ISOINFRA_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the ISO C and POSIX infrastructure package.
+# These flags are removed from the set of global flags
+# if present.
+#
+cdl_option CYGPKG_ISOINFRA_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# <
+# <
+# Compute CRCs
+# doc: ref/services-crc.html
+# This package provides support for CRC calculation. Currently
+# this is the POSIX 1003 defined CRC algorithm, a 32 CRC by
+# Gary S. Brown, and a 16 bit CRC.
+#
+cdl_package CYGPKG_CRC {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # package CYGPKG_COMPRESS_ZLIB
+ # Requires: CYGPKG_CRC
+};
+
+# >
+# POSIX CRC tests
+#
+cdl_option CYGPKG_CRC_TESTS {
+ # Calculated value: "tests/crc_test"
+ # Flavor: data
+ # Current_value: tests/crc_test
+};
+
+# <
+# Zlib compress and decompress package
+# This package provides support for compression and
+# decompression.
+#
+cdl_package CYGPKG_COMPRESS_ZLIB {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+ # Requires: CYGPKG_CRC
+ # CYGPKG_CRC == current
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGBLD_BUILD_REDBOOT_WITH_ZLIB
+ # ActiveIf: CYGPKG_COMPRESS_ZLIB
+};
+
+# >
+# Override memory allocation routines.
+#
+cdl_interface CYGINT_COMPRESS_ZLIB_LOCAL_ALLOC {
+ # Implemented by CYGBLD_BUILD_REDBOOT_WITH_ZLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_COMPRESS_ZLIB_NEEDS_MALLOC
+ # ActiveIf: CYGINT_COMPRESS_ZLIB_LOCAL_ALLOC == 0
+};
+
+# Should deflate() produce 'gzip' compatible output?
+# If this option is set then the output of calling deflate()
+# will be wrapped up as a 'gzip' compatible file.
+#
+cdl_option CYGSEM_COMPRESS_ZLIB_DEFLATE_MAKES_GZIP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Does this library need malloc?
+# This pseudo-option will force the memalloc library to be
+# required iff the application does not provide it's own
+# infrastructure.
+#
+cdl_option CYGSEM_COMPRESS_ZLIB_NEEDS_MALLOC {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_COMPRESS_ZLIB_LOCAL_ALLOC == 0
+ # CYGINT_COMPRESS_ZLIB_LOCAL_ALLOC == 1
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGPKG_MEMALLOC
+ # CYGPKG_MEMALLOC == current
+ # --> 1
+};
+
+# Include stdio-like utility functions
+# This option enables the stdio-like zlib utility functions
+# (gzread/gzwrite and friends) provided in gzio.c.
+#
+cdl_option CYGFUN_COMPRESS_ZLIB_GZIO {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGPKG_LIBC_STDIO_OPEN ? 1 : 0
+ # CYGPKG_LIBC_STDIO_OPEN (unknown) == 0
+ # --> 0
+ # Requires: CYGINT_ISO_STDIO_FILEPOS
+ # CYGINT_ISO_STDIO_FILEPOS == 0
+ # --> 0
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+ # Requires: CYGINT_ISO_STDIO_FORMATTED_IO
+ # CYGINT_ISO_STDIO_FORMATTED_IO == 0
+ # --> 0
+ # Requires: CYGINT_ISO_STDIO_FILEACCESS
+ # CYGINT_ISO_STDIO_FILEACCESS == 0
+ # --> 0
+};
+
+# Zlib compress and decompress package build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_COMPRESS_ZLIB_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_COMPRESS_ZLIB_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-D__ECOS__ -DNO_ERRNO_H"
+ # value_source default
+ # Default value: "-D__ECOS__ -DNO_ERRNO_H"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_COMPRESS_ZLIB_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wstrict-prototypes
+ # value_source default
+ # Default value: -Wstrict-prototypes
+};
+
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_COMPRESS_ZLIB_LDFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_COMPRESS_ZLIB_LDFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# <
+# zlib tests
+#
+cdl_option CYGPKG_COMPRESS_ZLIB_TESTS {
+ # Calculated value: "tests/zlib1.c tests/zlib2.c"
+ # Flavor: data
+ # Current_value: tests/zlib1.c tests/zlib2.c
+};
+
+# <
+# FLASH device drivers
+# doc: ref/flash.html
+# This option enables drivers for basic I/O services on
+# flash devices.
+#
+cdl_package CYGPKG_IO_FLASH {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGSEM_REDBOOT_FLASH_CONFIG
+ # DefaultValue: CYGPKG_IO_FLASH != 0
+ # package CYGPKG_DEVS_FLASH_ONMXC
+ # ActiveIf: CYGPKG_IO_FLASH
+};
+
+# >
+# Hardware FLASH device drivers
+# This option enables the hardware device drivers
+# for the current platform.
+#
+cdl_interface CYGHWR_IO_FLASH_DEVICE {
+ # Implemented by CYGPKG_DEVS_FLASH_ONMXC, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # component CYGPKG_REDBOOT_FLASH
+ # ActiveIf: CYGHWR_IO_FLASH_DEVICE
+};
+
+# Hardware FLASH device drivers are not in RAM
+# Use of this interface is deprecated.
+# Drivers should make sure that the functions are
+# linked to RAM by putting them in .2ram sections.
+#
+cdl_interface CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: !CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM
+ # CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM
+ # Requires: !CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM
+};
+
+# Hardware can support block locking
+# This option will be enabled by devices which can support
+# locking (write-protection) of individual blocks.
+#
+cdl_interface CYGHWR_IO_FLASH_BLOCK_LOCKING {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_FLASH_LOCK_SPECIAL
+ # ActiveIf: CYGHWR_IO_FLASH_BLOCK_LOCKING != 0
+};
+
+# Hardware cannot support direct access to FLASH memory
+# This option will be asserted by devices which cannot support
+# direct access to the FLASH memory contents (e.g. EEPROM or NAND
+# devices). In these cases, the driver must provide an appropriate
+# hardware access function.
+#
+cdl_option CYGSEM_IO_FLASH_READ_INDIRECT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+ # Requires: !CYGSEM_IO_FLASH_VERIFY_PROGRAM
+ # CYGSEM_IO_FLASH_VERIFY_PROGRAM == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGPRI_REDBOOT_ZLIB_FLASH
+ # ActiveIf: (!CYGSEM_IO_FLASH_READ_INDIRECT) || CYGPRI_REDBOOT_ZLIB_FLASH_FORCE
+ # component CYGHWR_DEVS_FLASH_MMC
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # option CYGHWR_DEVS_FLASH_MMC_ESDHC
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # option CYGHWR_DEVS_FLASH_MMC_SD
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # option CYGHWR_DEVS_FLASH_MXC_NAND
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+};
+
+# Display status messages during flash operations
+# Selecting this option will cause the drivers to print status
+# messages as various flash operations are undertaken.
+#
+cdl_option CYGSEM_IO_FLASH_CHATTER {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Verify data programmed to flash
+# Selecting this option will cause verification of data
+# programmed to flash.
+#
+cdl_option CYGSEM_IO_FLASH_VERIFY_PROGRAM {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_IO_FLASH_READ_INDIRECT
+ # Requires: !CYGSEM_IO_FLASH_VERIFY_PROGRAM
+};
+
+# Platform has flash soft DIP switch write-protect
+# Selecting this option will cause the state of a hardware jumper or
+# dipswitch to be read by software to determine whether the flash is
+# write-protected or not.
+#
+cdl_option CYGSEM_IO_FLASH_SOFT_WRITE_PROTECT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Instantiate in I/O block device API
+# Provides a block device accessible using the standard I/O
+# API ( cyg_io_read() etc. )
+#
+cdl_component CYGPKG_IO_FLASH_BLOCK_DEVICE {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_IO
+ # CYGPKG_IO (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# >
+# Name of flash device 1 block device
+#
+cdl_component CYGDAT_IO_FLASH_BLOCK_DEVICE_NAME_1 {
+ # This option is not active
+ # The parent CYGPKG_IO_FLASH_BLOCK_DEVICE is not active
+ # The parent CYGPKG_IO_FLASH_BLOCK_DEVICE is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "\"/dev/flash1\""
+ # value_source default
+ # Default value: "\"/dev/flash1\""
+};
+
+# >
+#
+cdl_interface CYGINT_IO_FLASH_BLOCK_CFG_1 {
+ # Implemented by CYGNUM_IO_FLASH_BLOCK_CFG_STATIC_1, inactive, enabled
+ # Implemented by CYGNUM_IO_FLASH_BLOCK_CFG_FIS_1, inactive, disabled
+ # This option is not active
+ # The parent CYGDAT_IO_FLASH_BLOCK_DEVICE_NAME_1 is not active
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 == CYGINT_IO_FLASH_BLOCK_CFG_1
+ # CYGINT_IO_FLASH_BLOCK_CFG_1 == 0
+ # --> 0
+
+ # The following properties are affected by this value
+ # interface CYGINT_IO_FLASH_BLOCK_CFG_1
+ # Requires: 1 == CYGINT_IO_FLASH_BLOCK_CFG_1
+};
+
+# Static configuration
+# This configures the flash device 1 block device
+# with static base and length
+#
+cdl_component CYGNUM_IO_FLASH_BLOCK_CFG_STATIC_1 {
+ # This option is not active
+ # The parent CYGDAT_IO_FLASH_BLOCK_DEVICE_NAME_1 is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Start offset from flash base
+# This gives the offset from the base of flash which this
+# block device corresponds to.
+#
+cdl_option CYGNUM_IO_FLASH_BLOCK_OFFSET_1 {
+ # This option is not active
+ # The parent CYGNUM_IO_FLASH_BLOCK_CFG_STATIC_1 is not active
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00100000
+ # value_source default
+ # Default value: 0x00100000
+};
+
+# Length
+# This gives the length of the region of flash given over
+# to this block device.
+#
+cdl_option CYGNUM_IO_FLASH_BLOCK_LENGTH_1 {
+ # This option is not active
+ # The parent CYGNUM_IO_FLASH_BLOCK_CFG_STATIC_1 is not active
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00100000
+ # value_source default
+ # Default value: 0x00100000
+};
+
+# <
+# Configuration from FIS
+# This configures the flash device 1 block device
+# from Redboot FIS
+#
+cdl_component CYGNUM_IO_FLASH_BLOCK_CFG_FIS_1 {
+ # This option is not active
+ # The parent CYGDAT_IO_FLASH_BLOCK_DEVICE_NAME_1 is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# >
+# Name of FIS entry
+#
+cdl_component CYGDAT_IO_FLASH_BLOCK_FIS_NAME_1 {
+ # This option is not active
+ # The parent CYGNUM_IO_FLASH_BLOCK_CFG_FIS_1 is not active
+ # The parent CYGNUM_IO_FLASH_BLOCK_CFG_FIS_1 is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "\"jffs2\""
+ # value_source default
+ # Default value: "\"jffs2\""
+};
+
+# <
+# <
+# <
+# Flash device driver build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_IO_FLASH_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the flash device drivers. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_IO_FLASH_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the flash device drivers. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_IO_FLASH_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Flash device driver tests
+# This option specifies the set of tests for the flash device drivers.
+#
+cdl_component CYGPKG_IO_FLASH_TESTS {
+ # Calculated value: "tests/flash1"
+ # Flavor: data
+ # Current_value: tests/flash1
+};
+
+# >
+# Start offset from flash base
+# This gives the offset from the base of flash where tests
+# can be run. It is important to set this correctly, as an
+# incorrect value could allow the tests to write over critical
+# portions of the FLASH device and possibly render the target
+# board totally non-functional.
+#
+cdl_option CYGNUM_IO_FLASH_TEST_OFFSET {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00100000
+ # value_source default
+ # Default value: 0x00100000
+};
+
+# Length
+# This gives the length of the region of flash used for testing.
+#
+cdl_option CYGNUM_IO_FLASH_TEST_LENGTH {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00100000
+ # value_source default
+ # Default value: 0x00100000
+};
+
+# <
+# <
+# Support FLASH memory on Freescale MXC platforms
+#
+cdl_package CYGPKG_DEVS_FLASH_ONMXC {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # ActiveIf constraint: CYGPKG_IO_FLASH
+ # CYGPKG_IO_FLASH == current
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+};
+
+# >
+# MXC platform MMC card support
+# When this option is enabled, it indicates MMC card is
+# supported on the MXC platforms
+#
+cdl_component CYGHWR_DEVS_FLASH_MMC {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+};
+
+# >
+# MXC platform MMC card for newer SDHC controllers
+#
+cdl_option CYGHWR_DEVS_FLASH_MMC_ESDHC {
+ # This option is not active
+ # The parent CYGHWR_DEVS_FLASH_MMC is disabled
+ # ActiveIf constraint: CYGPKG_HAL_ARM_MX37_3STACK || CYGPKG_HAL_ARM_MX35_3STACK || CYGPKG_HAL_ARM_MX25_3STACK || CYGPKG_HAL_ARM_MX51
+ # CYGPKG_HAL_ARM_MX37_3STACK (unknown) == 0
+ # CYGPKG_HAL_ARM_MX35_3STACK (unknown) == 0
+ # CYGPKG_HAL_ARM_MX25_3STACK (unknown) == 0
+ # CYGPKG_HAL_ARM_MX51 (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # --> 1
+};
+
+# MXC platform MMC card for older MMC/SD controllers
+#
+cdl_option CYGHWR_DEVS_FLASH_MMC_SD {
+ # This option is not active
+ # The parent CYGHWR_DEVS_FLASH_MMC is disabled
+ # ActiveIf constraint: CYGPKG_HAL_ARM_MX31_3STACK || CYGPKG_HAL_ARM_MX31ADS
+ # CYGPKG_HAL_ARM_MX31_3STACK (unknown) == 0
+ # CYGPKG_HAL_ARM_MX31ADS (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # --> 1
+};
+
+# <
+# MXC platform NOR flash memory support
+# When this option is enabled, it indicates NOR flash is
+# supported on the MXC platforms
+#
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_DEVS_FLASH_IMX_SPI_NOR
+ # Requires: CYGHWR_DEVS_FLASH_MXC_NOR == 1
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+};
+
+# MXC platform NAND flash memory support
+# When this option is enabled, it indicates NAND flash is
+# supported on the MXC platforms
+#
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGPKG_DEVS_FLASH_NAND_BBT_IN_FLASH
+ # ActiveIf: CYGHWR_DEVS_FLASH_MXC_NAND
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+ # interface CYGHWR_DEVS_FLASH_MXC_NAND_RESET_WORKAROUND
+ # ActiveIf: CYGHWR_DEVS_FLASH_MXC_NAND
+};
+
+# i.MX platform SPI NOR flash memory support
+# When this option is enabled, it indicates SPI NOR flash is
+# supported on the i.MX platforms
+#
+cdl_option CYGHWR_DEVS_FLASH_IMX_SPI_NOR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGHWR_DEVS_FLASH_MXC_NOR == 1
+ # CYGHWR_DEVS_FLASH_MXC_NOR == 0
+ # --> 0
+};
+
+# MXC platform ATA support
+# When this option is enabled, it indicates ATA is
+# supported on the MXC platforms
+#
+cdl_option CYGHWR_DEVS_FLASH_MXC_ATA {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Use a flash based Bad Block Table
+#
+cdl_component CYGPKG_DEVS_FLASH_NAND_BBT_IN_FLASH {
+ # ActiveIf constraint: CYGHWR_DEVS_FLASH_MXC_NAND
+ # CYGHWR_DEVS_FLASH_MXC_NAND == 1
+ # --> 1
+
+ # There is no associated value.
+};
+
+# >
+# When this option is enabled, the driver will search for a flash
+# based bad block table
+#
+cdl_option CYGHWR_DEVS_FLASH_MXC_BBT_IN_FLASH {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# header file defining the NAND BBT descriptor
+# defines the name of the header file that describes the BBT layout
+#
+cdl_component CYGHWR_FLASH_NAND_BBT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/io/tx27_nand_bbt.h>
+ # value_source inferred
+ # Default value: 0 0
+};
+
+# Number of blocks to reserve for BBT
+# Number of blocks to reserve for BBT
+#
+cdl_option CYGNUM_FLASH_NAND_BBT_BLOCKS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 4
+ # value_source default
+ # Default value: 4
+};
+
+# <
+# MXC platform multi flash memory support
+# When this option is enabled, it indicates multi flashes are
+# supported on the MXC platforms (like NAND and NOR)
+#
+cdl_option CYGHWR_DEVS_FLASH_MXC_MULTI {
+ # This option is not active
+ # ActiveIf constraint: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+ # CYGHWR_DEVS_FLASH_MXC_NAND == 1
+ # CYGHWR_DEVS_FLASH_MXC_NOR == 0
+ # CYGHWR_DEVS_FLASH_MXC_NAND == 1
+ # CYGHWR_DEVS_FLASH_MMC == 0
+ # CYGHWR_DEVS_FLASH_MXC_NOR == 0
+ # CYGHWR_DEVS_FLASH_MMC == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+};
+
+# MXC platform NAND flash reset workaround support
+# When this option is enabled, it indicates 0xFFFF is used for
+# the NAND reset command instead of 0xFF.
+#
+cdl_interface CYGHWR_DEVS_FLASH_MXC_NAND_RESET_WORKAROUND {
+ # No options implement this inferface
+ # ActiveIf constraint: CYGHWR_DEVS_FLASH_MXC_NAND
+ # CYGHWR_DEVS_FLASH_MXC_NAND == 1
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+};
+
+# <
+# <
+# Dynamic memory allocation
+# doc: ref/memalloc.html
+# This package provides memory allocator infrastructure required for
+# dynamic memory allocators, including the ISO standard malloc
+# interface. It also contains some sample implementations.
+#
+cdl_package CYGPKG_MEMALLOC {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # option CYGSEM_COMPRESS_ZLIB_NEEDS_MALLOC
+ # Requires: CYGPKG_MEMALLOC
+};
+
+# >
+# Memory allocator implementations
+# This component contains configuration options related to the
+# various memory allocators available.
+#
+cdl_component CYGPKG_MEMALLOC_ALLOCATORS {
+ # There is no associated value.
+};
+
+# >
+# Fixed block allocator
+# This component contains configuration options related to the
+# fixed block memory allocator.
+#
+cdl_component CYGPKG_MEMALLOC_ALLOCATOR_FIXED {
+ # There is no associated value.
+};
+
+# >
+# Make thread safe
+# With this option enabled, this allocator will be
+# made thread-safe. Additionally allocation functions
+# are made available that allow a thread to wait
+# until memory is available.
+#
+cdl_option CYGSEM_MEMALLOC_ALLOCATOR_FIXED_THREADAWARE {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Simple variable block allocator
+# This component contains configuration options related to the
+# simple variable block memory allocator. This allocator is not
+# very fast, and in particular does not scale well with large
+# numbers of allocations. It is however very compact in terms of
+# code size and does not have very much overhead per allocation.
+#
+cdl_component CYGPKG_MEMALLOC_ALLOCATOR_VARIABLE {
+ # There is no associated value.
+};
+
+# >
+# Make thread safe
+# With this option enabled, this allocator will be
+# made thread-safe. Additionally allocation functions
+# are added that allow a thread to wait until memory
+# are made available that allow a thread to wait
+# until memory is available.
+#
+cdl_option CYGSEM_MEMALLOC_ALLOCATOR_VARIABLE_THREADAWARE {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Coalesce memory
+# The variable-block memory allocator can perform coalescing
+# of memory whenever the application code releases memory back
+# to the pool. This coalescing reduces the possibility of
+# memory fragmentation problems, but involves extra code and
+# processor cycles.
+#
+cdl_option CYGSEM_MEMALLOC_ALLOCATOR_VARIABLE_COALESCE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGIMP_MEMALLOC_MALLOC_VARIABLE_SIMPLE
+ # Requires: CYGSEM_MEMALLOC_ALLOCATOR_VARIABLE_COALESCE
+};
+
+# <
+# Doug Lea's malloc
+# This component contains configuration options related to the
+# port of Doug Lea's memory allocator, normally known as
+# dlmalloc. dlmalloc has a reputation for being both fast
+# and space-conserving, as well as resisting fragmentation well.
+# It is a common choice for a general purpose allocator and
+# has been used in both newlib and Linux glibc.
+#
+cdl_component CYGPKG_MEMALLOC_ALLOCATOR_DLMALLOC {
+ # There is no associated value.
+};
+
+# >
+# Debug build
+# Doug Lea's malloc implementation has substantial amounts
+# of internal checking in order to verify the operation
+# and consistency of the allocator. However this imposes
+# substantial overhead on each operation. Therefore this
+# checking may be individually disabled.
+#
+cdl_option CYGDBG_MEMALLOC_ALLOCATOR_DLMALLOC_DEBUG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0 != CYGDBG_USE_ASSERTS
+ # CYGDBG_USE_ASSERTS == 0
+ # --> 0
+ # Requires: CYGDBG_USE_ASSERTS
+ # CYGDBG_USE_ASSERTS == 0
+ # --> 0
+};
+
+# Make thread safe
+# With this option enabled, this allocator will be
+# made thread-safe. Additionally allocation functions
+# are made available that allow a thread to wait
+# until memory is available.
+#
+cdl_option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_THREADAWARE {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+};
+
+# Support more than one instance
+# Having this option disabled allows important
+# implementation structures to be declared as a single
+# static instance, allowing faster access. However this
+# would fail if there is more than one instance of
+# the dlmalloc allocator class. Therefore this option can
+# be enabled if multiple instances are required. Note: as
+# a special case, if this allocator is used as the
+# implementation of malloc, and it can be determined there
+# is more than one malloc pool, then this option will be
+# silently enabled.
+#
+cdl_option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_SAFE_MULTIPLE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Use system memmove() and memset()
+# This may be used to control whether memset() and memmove()
+# are used within the implementation. The alternative is
+# to use some macro equivalents, which some people report
+# are faster in some circumstances.
+#
+cdl_option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_USE_MEMCPY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 0 != CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+};
+
+# Minimum alignment of allocated blocks
+# This option controls the minimum alignment that the
+# allocated memory blocks are aligned on, specified as
+# 2^N. Note that using large mininum alignments can lead
+# to excessive memory wastage.
+#
+cdl_option CYGNUM_MEMALLOC_ALLOCATOR_DLMALLOC_ALIGNMENT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 3
+ # value_source default
+ # Default value: 3
+ # Legal values: 3 to 10
+};
+
+# <
+# Variable block allocator with separate metadata
+# This component contains configuration options related to the
+# variable block memory allocator with separate metadata.
+#
+cdl_component CYGPKG_MEMALLOC_ALLOCATOR_SEPMETA {
+ # There is no associated value.
+};
+
+# >
+# Make thread safe
+# With this option enabled, this allocator will be
+# made thread-safe. Additionally allocation functions
+# are made available that allow a thread to wait
+# until memory is available.
+#
+cdl_option CYGSEM_MEMALLOC_ALLOCATOR_SEPMETA_THREADAWARE {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# <
+# Kernel C API support for memory allocation
+# This option must be enabled to provide the extensions required
+# to support integration into the kernel C API.
+#
+cdl_option CYGFUN_MEMALLOC_KAPI {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGFUN_KERNEL_API_C
+ # CYGFUN_KERNEL_API_C (unknown) == 0
+ # --> 0
+};
+
+# malloc(0) returns NULL
+# This option controls the behavior of malloc(0) ( or calloc with
+# either argument 0 ). It is permitted by the standard to return
+# either a NULL pointer or a unique pointer. Enabling this option
+# forces a NULL pointer to be returned.
+#
+cdl_option CYGSEM_MEMALLOC_MALLOC_ZERO_RETURNS_NULL {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Breakpoint site when running out of memory
+# Whenever the system runs out of memory, it invokes this function
+# before either going to sleep waiting for memory to become
+# available or returning failure.
+#
+cdl_option CYGSEM_MEMALLOC_INVOKE_OUT_OF_MEMORY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# malloc() and supporting allocators
+# This component enables support for dynamic memory
+# allocation as supplied by the functions malloc(),
+# free(), calloc() and realloc(). As these
+# functions are often used, but can have quite an
+# overhead, disabling them here can ensure they
+# cannot even be used accidentally when static
+# allocation is preferred. Within this component are
+# various allocators that can be selected for use
+# as the underlying implementation of the dynamic
+# allocation functions.
+#
+cdl_component CYGPKG_MEMALLOC_MALLOC_ALLOCATORS {
+ # ActiveIf constraint: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Use external heap definition
+# This option allows other components in the
+# system to override the default system
+# provision of heap memory pools. This should
+# be set to a header which provides the equivalent
+# definitions to <pkgconf/heaps.hxx>.
+#
+cdl_component CYGBLD_MEMALLOC_MALLOC_EXTERNAL_HEAP_H {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Use external implementation of joining multiple heaps
+# The default implementation of joining multiple heaps
+# is fine for the case where there are multiple disjoint
+# memory regions of the same type. However, in a system
+# there might be e.g. a small amount of internal SRAM and
+# a large amount of external DRAM. The SRAM is faster and
+# the DRAM is slower. An application can implement some
+# heuristic to choose which pool to allocate from. This
+# heuristic can be highly application specific.
+#
+cdl_component CYGBLD_MEMALLOC_MALLOC_EXTERNAL_JOIN_H {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# malloc() allocator implementations
+#
+cdl_interface CYGINT_MEMALLOC_MALLOC_ALLOCATORS {
+ # Implemented by CYGIMP_MEMALLOC_MALLOC_VARIABLE_SIMPLE, active, disabled
+ # Implemented by CYGIMP_MEMALLOC_MALLOC_DLMALLOC, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: CYGINT_MEMALLOC_MALLOC_ALLOCATORS == 1
+ # CYGINT_MEMALLOC_MALLOC_ALLOCATORS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_MEMALLOC_MALLOC_ALLOCATORS
+ # Requires: CYGINT_MEMALLOC_MALLOC_ALLOCATORS == 1
+};
+
+# malloc() implementation instantiation data
+# Memory allocator implementations that are capable of being
+# used underneath malloc() must be instantiated. The code
+# to do this is set in this option. It is only intended to
+# be set by the implementation, not the user.
+#
+cdl_option CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value <cyg/memalloc/dlmalloc.hxx>
+ # value_source default
+ # Default value: <cyg/memalloc/dlmalloc.hxx>
+
+ # The following properties are affected by this value
+ # option CYGIMP_MEMALLOC_MALLOC_VARIABLE_SIMPLE
+ # Requires: CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == "<cyg/memalloc/memvar.hxx>"
+ # option CYGIMP_MEMALLOC_MALLOC_DLMALLOC
+ # Requires: CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == "<cyg/memalloc/dlmalloc.hxx>"
+};
+
+# Simple variable block implementation
+# This causes malloc() to use the simple
+# variable block allocator.
+#
+cdl_option CYGIMP_MEMALLOC_MALLOC_VARIABLE_SIMPLE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == "<cyg/memalloc/memvar.hxx>"
+ # CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == <cyg/memalloc/dlmalloc.hxx>
+ # --> 0
+ # Requires: CYGSEM_MEMALLOC_ALLOCATOR_VARIABLE_COALESCE
+ # CYGSEM_MEMALLOC_ALLOCATOR_VARIABLE_COALESCE == 1
+ # --> 1
+};
+
+# Doug Lea's malloc implementation
+# This causes malloc() to use a version of Doug Lea's
+# malloc (dlmalloc) as the underlying implementation.
+#
+cdl_option CYGIMP_MEMALLOC_MALLOC_DLMALLOC {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == "<cyg/memalloc/dlmalloc.hxx>"
+ # CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == <cyg/memalloc/dlmalloc.hxx>
+ # --> 1
+};
+
+# <
+# Size of the fallback dynamic memory pool in bytes
+# If *no* heaps are configured in your memory layout,
+# dynamic memory allocation by
+# malloc() and calloc() must be from a fixed-size,
+# contiguous memory pool (note here that it is the
+# pool that is of a fixed size, but malloc() is still
+# able to allocate variable sized chunks of memory
+# from it). This option is the size
+# of that pool, in bytes. Note that not all of
+# this is available for programs to
+# use - some is needed for internal information
+# about memory regions, and some may be lost to
+# ensure that memory allocation only returns
+# memory aligned on word (or double word)
+# boundaries - a very common architecture
+# constraint.
+#
+cdl_option CYGNUM_MEMALLOC_FALLBACK_MALLOC_POOL_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 16384
+ # value_source default
+ # Default value: 16384
+ # Legal values: 32 to 0x7fffffff
+};
+
+# Common memory allocator package build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_MEMALLOC_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_MEMALLOC_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-fno-rtti -Woverloaded-virtual"
+ # value_source default
+ # Default value: "-fno-rtti -Woverloaded-virtual"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_MEMALLOC_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wno-pointer-sign
+ # value_source default
+ # Default value: -Wno-pointer-sign
+};
+
+# Tests
+# This option specifies the set of tests for this package.
+#
+cdl_option CYGPKG_MEMALLOC_TESTS {
+ # Calculated value: "tests/dlmalloc1 tests/dlmalloc2 tests/heaptest tests/kmemfix1 tests/kmemvar1 tests/malloc1 tests/malloc2 tests/malloc3 tests/malloc4 tests/memfix1 tests/memfix2 tests/memvar1 tests/memvar2 tests/realloc tests/sepmeta1 tests/sepmeta2"
+ # Flavor: data
+ # Current_value: tests/dlmalloc1 tests/dlmalloc2 tests/heaptest tests/kmemfix1 tests/kmemvar1 tests/malloc1 tests/malloc2 tests/malloc3 tests/malloc4 tests/memfix1 tests/memfix2 tests/memvar1 tests/memvar2 tests/realloc tests/sepmeta1 tests/sepmeta2
+};
+
+# <
+# <
+# Common error code support
+# This package contains the common list of error and
+# status codes. It is held centrally to allow
+# packages to interchange error codes and status
+# codes in a common way, rather than each package
+# having its own conventions for error/status
+# reporting. The error codes are modelled on the
+# POSIX style naming e.g. EINVAL etc. This package
+# also provides the standard strerror() function to
+# convert error codes to textual representation, as
+# well as an implementation of the errno idiom.
+#
+cdl_package CYGPKG_ERROR {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGBLD_ISO_ERRNO_CODES_HEADER == "<cyg/error/codes.h>"
+ # CYGBLD_ISO_ERRNO_CODES_HEADER == <cyg/error/codes.h>
+ # --> 1
+};
+
+# >
+# errno variable
+# This package controls the behaviour of the
+# errno variable (or more strictly, expression)
+# from <errno.h>.
+#
+cdl_component CYGPKG_ERROR_ERRNO {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_ERRNO_HEADER == "<cyg/error/errno.h>"
+ # CYGBLD_ISO_ERRNO_HEADER == <cyg/error/errno.h>
+ # --> 1
+};
+
+# >
+# Per-thread errno
+# This option controls whether the standard error
+# code reporting variable errno is a per-thread
+# variable, rather than global.
+#
+cdl_option CYGSEM_ERROR_PER_THREAD_ERRNO {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+ # Requires: CYGVAR_KERNEL_THREADS_DATA
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+};
+
+# Tracing level
+# Trace verbosity level for debugging the errno
+# retrieval mechanism in errno.cxx. Increase this
+# value to get additional trace output.
+#
+cdl_option CYGNUM_ERROR_ERRNO_TRACE_LEVEL {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to 1
+};
+
+# <
+# strerror function
+# This package controls the presence and behaviour of the
+# strerror() function from <string.h>
+#
+cdl_option CYGPKG_ERROR_STRERROR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_STRERROR_HEADER == "<cyg/error/strerror.h>"
+ # CYGBLD_ISO_STRERROR_HEADER == <cyg/error/strerror.h>
+ # --> 1
+};
+
+# Error package build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_ERROR_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the error package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_ERROR_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the error package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_ERROR_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# <
+# <
+# <
+
--- /dev/null
+# eCos saved configuration
+
+# ---- commands --------------------------------------------------------
+# This section contains information about the savefile format.
+# It should not be edited. Any modifications made to this section
+# may make it impossible for the configuration tools to read
+# the savefile.
+
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+# ---- toplevel --------------------------------------------------------
+# This section defines the toplevel configuration object. The only
+# values that can be changed are the name of the configuration and
+# the description field. It is not possible to modify the target,
+# the template or the set of packages simply by editing the lines
+# below because these changes have wide-ranging effects. Instead
+# the appropriate tools should be used to make such modifications.
+
+cdl_configuration eCos {
+ description "" ;
+
+ # These fields should not be modified.
+ hardware tx27karo ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM current ;
+ package -hardware CYGPKG_HAL_ARM_MX27 current ;
+ package -hardware CYGPKG_HAL_ARM_TX27KARO current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_TX27 current ;
+ package -hardware CYGPKG_DEVS_ETH_FEC current ;
+ package -hardware CYGPKG_COMPRESS_ZLIB current ;
+ package -hardware CYGPKG_IO_FLASH current ;
+ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+ package -template CYGPKG_MEMALLOC current ;
+ package -template CYGPKG_DEVS_ETH_PHY current ;
+ package -template CYGPKG_LIBC_I18N current ;
+ package -template CYGPKG_LIBC_STDLIB current ;
+ package -template CYGPKG_ERROR current ;
+};
+
+# ---- conflicts -------------------------------------------------------
+# There are no conflicts.
+
+# ---- contents --------------------------------------------------------
+# >
+# >
+# Global build options
+# Global build options including control over
+# compiler flags, linker flags and choice of toolchain.
+#
+cdl_component CYGBLD_GLOBAL_OPTIONS {
+ # There is no associated value.
+
+ # The following properties are affected by this value
+};
+
+# >
+# Global command prefix
+# This option specifies the command prefix used when
+# invoking the build tools.
+#
+cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value arm-926ejs-linux-gnu
+ # value_source default
+ # Default value: arm-926ejs-linux-gnu
+};
+
+# Global compiler flags
+# This option controls the global compiler flags which are used to
+# compile all packages by default. Individual packages may define
+# options which override these global flags.
+#
+cdl_option CYGBLD_GLOBAL_CFLAGS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe"
+ # The inferred value should not be edited directly.
+ inferred_value "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe"
+ # value_source inferred
+ # Default value: "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe"
+ # Requires: CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS
+ # CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS
+ # Requires: is_substr(CYGBLD_GLOBAL_CFLAGS, " -Werror")
+ # option CYGBLD_INFRA_CFLAGS_PIPE
+ # Requires: is_substr(CYGBLD_GLOBAL_CFLAGS, " -pipe")
+};
+
+# Global linker flags
+# This option controls the global linker flags. Individual
+# packages may define options which override these global flags.
+#
+cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-Wl,--gc-sections -Wl,-static -O2 -nostdlib"
+ # value_source default
+ # Default value: "-Wl,--gc-sections -Wl,-static -O2 -nostdlib"
+};
+
+# Build common GDB stub ROM image
+# Unless a target board has specific requirements to the
+# stub implementation, it can use a simple common stub.
+# This option, which gets enabled by platform HALs as
+# appropriate, controls the building of the common stub.
+#
+cdl_option CYGBLD_BUILD_COMMON_GDB_STUBS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+};
+
+# <
+# ISO C library string functions
+# doc: ref/libc.html
+# This package provides string functions specified by the
+# ISO C standard - ISO/IEC 9899:1990.
+#
+cdl_package CYGPKG_LIBC_STRING {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER == "<cyg/libc/string/string.h>"
+ # CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER == <cyg/libc/string/string.h>
+ # --> 1
+ # Requires: CYGBLD_ISO_STRING_MEMFUNCS_HEADER == "<cyg/libc/string/string.h>"
+ # CYGBLD_ISO_STRING_MEMFUNCS_HEADER == <cyg/libc/string/string.h>
+ # --> 1
+ # Requires: CYGBLD_ISO_STRING_STRFUNCS_HEADER == "<cyg/libc/string/string.h>"
+ # CYGBLD_ISO_STRING_STRFUNCS_HEADER == <cyg/libc/string/string.h>
+ # --> 1
+ # Requires: CYGBLD_ISO_STRTOK_R_HEADER == "<cyg/libc/string/string.h>"
+ # CYGBLD_ISO_STRTOK_R_HEADER == <cyg/libc/string/string.h>
+ # --> 1
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+};
+
+# >
+# Inline versions of <string.h> functions
+# This option chooses whether some of the
+# particularly simple string functions from
+# <string.h> are available as inline
+# functions. This may improve performance, and as
+# the functions are small, may even improve code
+# size.
+#
+cdl_option CYGIMP_LIBC_STRING_INLINES {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Optimize string functions for code size
+# This option tries to reduce string function
+# code size at the expense of execution speed. The
+# same effect can be produced if the code is
+# compiled with the -Os option to the compiler.
+#
+cdl_option CYGIMP_LIBC_STRING_PREFER_SMALL_TO_FAST {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Provide BSD compatibility functions
+# Enabling this option causes various compatibility functions
+# commonly found in the BSD UNIX operating system to be included.
+# These are functions such as bzero, bcmp, bcopy, bzero, strcasecmp,
+# strncasecmp, index, rindex and swab.
+#
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+ # Requires: CYGBLD_ISO_STRING_BSD_FUNCS_HEADER == "<cyg/libc/string/bsdstring.h>"
+ # CYGBLD_ISO_STRING_BSD_FUNCS_HEADER == <cyg/libc/string/bsdstring.h>
+ # --> 1
+ # Requires: CYGINT_ISO_CTYPE
+ # CYGINT_ISO_CTYPE == 1
+ # --> 1
+};
+
+# strtok
+# These options control the behaviour of the
+# strtok() and strtok_r() string tokenization
+# functions.
+#
+cdl_component CYGPKG_LIBC_STRING_STRTOK {
+ # There is no associated value.
+};
+
+# >
+# Per-thread strtok()
+# This option controls whether the string function
+# strtok() has its state recorded on a per-thread
+# basis rather than global. If this option is
+# disabled, some per-thread space can be saved.
+# Note there is also a POSIX-standard strtok_r()
+# function to achieve a similar effect with user
+# support. Enabling this option will use one slot
+# of kernel per-thread data. You should ensure you
+# have enough slots configured for all your
+# per-thread data.
+#
+cdl_option CYGSEM_LIBC_STRING_PER_THREAD_STRTOK {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGVAR_KERNEL_THREADS_DATA
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+ # Requires: CYGVAR_KERNEL_THREADS_DATA
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+};
+
+# Tracing level
+# Trace verbosity level for debugging the <string.h>
+# functions strtok() and strtok_r(). Increase this
+# value to get additional trace output.
+#
+cdl_option CYGNUM_LIBC_STRING_STRTOK_TRACE_LEVEL {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to 1
+};
+
+# <
+# strdup
+# This option indicates whether strdup() is to be supported.
+#
+cdl_option CYGFUN_LIBC_STRING_STRDUP {
+ # ActiveIf constraint: CYGINT_ISO_MALLOC
+ # CYGINT_ISO_MALLOC == 1
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+};
+
+# C library string functions build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_LIBC_STRING_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the C library. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_LIBC_STRING_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-fno-rtti -Woverloaded-virtual"
+ # value_source default
+ # Default value: "-fno-rtti -Woverloaded-virtual"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the C library. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_LIBC_STRING_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wno-pointer-sign
+ # value_source default
+ # Default value: -Wno-pointer-sign
+};
+
+# C library string function tests
+# This option specifies the set of tests for the C library
+# string functions.
+#
+cdl_option CYGPKG_LIBC_STRING_TESTS {
+ # Calculated value: "tests/memchr tests/memcmp1 tests/memcmp2 tests/memcpy1 tests/memcpy2 tests/memmove1 tests/memmove2 tests/memset tests/strcat1 tests/strcat2 tests/strchr tests/strcmp1 tests/strcmp2 tests/strcoll1 tests/strcoll2 tests/strcpy1 tests/strcpy2 tests/strcspn tests/strcspn tests/strlen tests/strncat1 tests/strncat2 tests/strncpy1 tests/strncpy2 tests/strpbrk tests/strrchr tests/strspn tests/strstr tests/strtok tests/strxfrm1 tests/strxfrm2"
+ # Flavor: data
+ # Current_value: tests/memchr tests/memcmp1 tests/memcmp2 tests/memcpy1 tests/memcpy2 tests/memmove1 tests/memmove2 tests/memset tests/strcat1 tests/strcat2 tests/strchr tests/strcmp1 tests/strcmp2 tests/strcoll1 tests/strcoll2 tests/strcpy1 tests/strcpy2 tests/strcspn tests/strcspn tests/strlen tests/strncat1 tests/strncat2 tests/strncpy1 tests/strncpy2 tests/strpbrk tests/strrchr tests/strspn tests/strstr tests/strtok tests/strxfrm1 tests/strxfrm2
+};
+
+# <
+# <
+# Common ethernet support
+# doc: ref/io-eth-drv-generic.html
+# Platform independent ethernet drivers
+#
+cdl_package CYGPKG_IO_ETH_DRIVERS {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # component CYGPKG_REDBOOT_NETWORKING
+ # ActiveIf: CYGPKG_IO_ETH_DRIVERS
+ # package CYGPKG_DEVS_ETH_ARM_TX27
+ # ActiveIf: CYGPKG_IO_ETH_DRIVERS
+ # package CYGPKG_DEVS_ETH_FEC
+ # ActiveIf: CYGPKG_IO_ETH_DRIVERS
+ # package CYGPKG_DEVS_ETH_PHY
+ # ActiveIf: CYGPKG_IO_ETH_DRIVERS
+};
+
+# >
+# Network drivers
+#
+cdl_interface CYGHWR_NET_DRIVERS {
+ # Implemented by CYGPKG_DEVS_ETH_FEC, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGDAT_REDBOOT_DEFAULT_NETWORK_DEVICE
+ # ActiveIf: CYGHWR_NET_DRIVERS > 1
+ # option CYGSEM_REDBOOT_NETWORK_INIT_ONE_DEVICE
+ # ActiveIf: CYGHWR_NET_DRIVERS > 1
+};
+
+# Driver supports multicast addressing
+# This interface defines whether or not a driver can handle
+# requests for multicast addressing.
+#
+cdl_interface CYGINT_IO_ETH_MULTICAST {
+ # Implemented by CYGPKG_DEVS_ETH_FEC, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+};
+
+# Support printing driver debug information
+# Selecting this option will include code to allow the driver to
+# print lots of information on diagnostic output such as full
+# packet dumps.
+#
+cdl_component CYGDBG_IO_ETH_DRIVERS_DEBUG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Driver debug output verbosity
+# The value of this option indicates the default verbosity
+# level of debugging output. 0 means no debugging output
+# is made by default. Higher values indicate higher verbosity.
+# The verbosity level may also be changed at run time by
+# changing the variable cyg_io_eth_net_debug.
+#
+cdl_option CYGDBG_IO_ETH_DRIVERS_DEBUG_VERBOSITY {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Size of scatter-gather I/O lists
+# A scatter-gather list is used to pass requests to/from
+# the physical device driver. This list can typically be
+# small, as the data is normally already packed into reasonable
+# chunks.
+#
+cdl_option CYGNUM_IO_ETH_DRIVERS_SG_LIST_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 32
+ # value_source default
+ # Default value: 32
+};
+
+# Support for standard eCos TCP/IP stack.
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_NET {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_NET
+ # CYGPKG_NET (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+};
+
+# >
+# Warn when there are no more mbufs
+# Warnings about running out of mbufs are printed to the
+# diagnostic output channel via diag_printf() if this option
+# is enabled. Mbufs are the network stack's basic dynamic
+# memory objects that hold all packets in transit; running
+# out is bad for performance but not fatal, not a crash.
+# You might want to turn off the warnings to preserve realtime
+# properties of the system even in extremis.
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_WARN_NO_MBUFS {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_NET is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Simulate network failures for testing
+# This package contains a suite of simulated failure modes
+# for the ethernet device layer, including dropping and/or
+# corrupting received packets, dropping packets queued for
+# transmission, and simulating a complete network break.
+# It requires the kernel as a source of time information.
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_NET is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# >
+# Drop incoming packets (percentage)
+#
+cdl_option CYGPKG_IO_ETH_DRIVERS_SIMULATE_DROP_RX {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 1 10
+ # value_source default
+ # Default value: 1 10
+ # Legal values: 10 50 80
+};
+
+# Corrupt incoming packets (percentage)
+#
+cdl_option CYGPKG_IO_ETH_DRIVERS_SIMULATE_CORRUPT_RX {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 1 10
+ # value_source default
+ # Default value: 1 10
+ # Legal values: 10 50 80
+};
+
+# Drop outgoing packets (percentage)
+#
+cdl_option CYGPKG_IO_ETH_DRIVERS_SIMULATE_DROP_TX {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 1 10
+ # value_source default
+ # Default value: 1 10
+ # Legal values: 10 50 80
+};
+
+# Simulate a line cut from time to time
+# This option causes the system to drop all packets for a
+# short random period (10s of seconds), and then act
+# normally for up to 4 times that long. This simulates your
+# sysadmin fiddling with plugs in the network switch
+# cupboard.
+#
+cdl_option CYGPKG_IO_ETH_DRIVERS_SIMULATE_LINE_CUT {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# <
+# Support for stand-alone network stack.
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_STAND_ALONE {
+ # ActiveIf constraint: !CYGPKG_NET
+ # CYGPKG_NET (unknown) == 0
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGINT_ISO_STRING_MEMFUNCS
+ # CYGINT_ISO_STRING_MEMFUNCS == 1
+ # --> 1
+};
+
+# >
+# Pass packets to an alternate stack
+# Define this to allow packets seen by this layer to be
+# passed on to the previous logical layer, i.e. when
+# stand-alone processing replaces system (eCos) processing.
+#
+cdl_option CYGSEM_IO_ETH_DRIVERS_PASS_PACKETS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 0 != CYGPKG_REDBOOT_NETWORKING
+ # CYGPKG_REDBOOT_NETWORKING == 1
+ # --> 1
+};
+
+# Number of [network] buffers
+# This option is used to allocate space to buffer incoming network
+# packets. These buffers are used to hold data until they can be
+# logically processed by higher layers.
+#
+cdl_option CYGNUM_IO_ETH_DRIVERS_NUM_PKT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 4
+ # value_source default
+ # Default value: 4
+ # Legal values: 2 to 32
+};
+
+# Show driver warnings
+# Selecting this option will allows the stand-alone ethernet driver
+# to display warnings on the system console when incoming network
+# packets are being discarded due to lack of buffer space.
+#
+cdl_option CYGSEM_IO_ETH_DRIVERS_WARN {
+ # ActiveIf constraint: CYGPKG_REDBOOT
+ # CYGPKG_REDBOOT == current
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Support for lwIP network stack.
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_LWIP {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_NET_LWIP
+ # CYGPKG_NET_LWIP (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: !CYGPKG_NET
+ # CYGPKG_NET (unknown) == 0
+ # --> 1
+};
+
+# Interrupt support required
+# This interface is used to indicate to the low
+# level device drivers that interrupt driven operation
+# is required by higher layers.
+#
+cdl_interface CYGINT_IO_ETH_INT_SUPPORT_REQUIRED {
+ # Implemented by CYGPKG_IO_ETH_DRIVERS_NET, inactive, enabled
+ # Implemented by CYGPKG_IO_ETH_DRIVERS_LWIP, inactive, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+
+ # The following properties are affected by this value
+};
+
+# Common ethernet support build options
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the common ethernet support package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_IO_ETH_DRIVERS_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-D_KERNEL -D__ECOS"
+ # value_source default
+ # Default value: "-D_KERNEL -D__ECOS"
+};
+
+# <
+# Ethernet driver for Ka-Ro electronics TX27 processor module
+#
+cdl_package CYGPKG_DEVS_ETH_ARM_TX27 {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # ActiveIf constraint: CYGPKG_IO_ETH_DRIVERS
+ # CYGPKG_IO_ETH_DRIVERS == current
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+};
+
+# >
+# FEC ethernet driver required
+#
+cdl_interface CYGINT_DEVS_ETH_FEC_REQUIRED {
+ # Implemented by CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # package CYGPKG_DEVS_ETH_FEC
+ # ActiveIf: CYGINT_DEVS_ETH_FEC_REQUIRED
+};
+
+# Ka-Ro TX27 ethernet port driver
+# This option includes the ethernet device driver for the
+# MXC Board port.
+#
+cdl_component CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ # CYGSEM_REDBOOT_PLF_ESA_VALIDATE == 1
+ # --> 1
+ # Requires: CYGHWR_DEVS_ETH_PHY_LAN8700
+ # CYGHWR_DEVS_ETH_PHY_LAN8700 == 1
+ # --> 1
+};
+
+# >
+# Device name for the ETH0 ethernet driver
+# This option sets the name of the ethernet device.
+#
+cdl_option CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "\"eth0\""
+ # value_source default
+ # Default value: "\"eth0\""
+};
+
+# OUI part of MAC address
+# This option sets OUI part (manufacturer ID) of the MAC address
+# for validation.
+#
+cdl_option CYGDAT_DEVS_ETH_ARM_TX27KARO_OUI {
+ # ActiveIf constraint: CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ # CYGSEM_REDBOOT_PLF_ESA_VALIDATE == 1
+ # --> 1
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "{ 0x00, 0x0c, 0xc6 }"
+ # value_source default
+ # Default value: "{ 0x00, 0x0c, 0xc6 }"
+};
+
+# <
+# <
+# Driver for fast ethernet controller.
+# Driver for fast ethernet controller.
+#
+cdl_package CYGPKG_DEVS_ETH_FEC {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # ActiveIf constraint: CYGPKG_IO_ETH_DRIVERS
+ # CYGPKG_IO_ETH_DRIVERS == current
+ # --> 1
+ # ActiveIf constraint: CYGINT_DEVS_ETH_FEC_REQUIRED
+ # CYGINT_DEVS_ETH_FEC_REQUIRED == 1
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+};
+
+# >
+# MXC FEC ethernet driver build options
+#
+cdl_component CYGPKG_DEVS_ETH_FEC_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the Cirrus Logic ethernet driver package.
+# These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_DEVS_ETH_FEC_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-D_KERNEL -D__ECOS"
+ # value_source default
+ # Default value: "-D_KERNEL -D__ECOS"
+};
+
+# <
+# <
+# Ethernet transceiver (PHY) support
+# API for ethernet PHY devices
+#
+cdl_package CYGPKG_DEVS_ETH_PHY {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # ActiveIf constraint: CYGPKG_IO_ETH_DRIVERS
+ # CYGPKG_IO_ETH_DRIVERS == current
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT == 1
+ # --> 1
+};
+
+# >
+# Enable driver debugging
+# Enables the diagnostic debug messages on the
+# console device.
+#
+cdl_option CYGDBG_DEVS_ETH_PHY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Time period (seconds) to wait for auto-negotiation
+# The length of time to wait for auto-negotiation to complete
+# before giving up and declaring the link dead/missing.
+#
+cdl_option CYGINT_DEVS_ETH_PHY_AUTO_NEGOTIATION_TIME {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 5
+ # value_source default
+ # Default value: 5
+};
+
+# NSDP83847
+# Include support for National Semiconductor DP83847 DsPHYTER II
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_DP83847 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# AMD 79C874
+# Include support for AMD 79C874 NetPHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_AM79C874 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Intel LXT972
+# Include support for Intel LXT972xxx PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_INLXT972 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# ICS 1890
+# Include support for ICS 1890 PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_ICS1890 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# ICS 1892
+# Include support for ICS 1892 PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_ICS1892 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# ICS 1893
+# Include support for ICS 1893 and 1893AF PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_ICS1893 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Davicom DM9161A
+# Include support for the Davicom DM9161A PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_DM9161A {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Micrel KS8721
+# Include support for the Micrel KS8721 PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_KS8721 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# SMSC LAN8700
+# Include support for SMSC LAN8700 NetPHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_LAN8700 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # component CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
+ # Requires: CYGHWR_DEVS_ETH_PHY_LAN8700
+};
+
+# <
+# <
+# ISO C library internationalization functions
+# doc: ref/libc.html
+# This package provides internationalization functions specified by the
+# ISO C standard - ISO/IEC 9899:1990. These include locale-related
+# functionality and <ctype.h> functionality.
+#
+cdl_package CYGPKG_LIBC_I18N {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+};
+
+# >
+# Supported locales
+# These options determine which locales other than the "C" locale
+# are supported and hence contribute to the size of the executable.
+#
+cdl_component CYGPKG_LIBC_I18N_LOCALES {
+ # There is no associated value.
+};
+
+# >
+# Support for multiple locales required
+#
+cdl_interface CYGINT_LIBC_I18N_MB_REQUIRED {
+ # Implemented by CYGFUN_LIBC_I18N_LOCALE_C_SJIS, active, disabled
+ # Implemented by CYGFUN_LIBC_I18N_LOCALE_C_JIS, active, disabled
+ # Implemented by CYGFUN_LIBC_I18N_LOCALE_C_EUCJP, active, disabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: CYGBLD_ISO_STDLIB_MB_CUR_MAX_HEADER == "<cyg/libc/i18n/mb.h>"
+ # CYGBLD_ISO_STDLIB_MB_CUR_MAX_HEADER == 0
+ # --> 0
+
+ # The following properties are affected by this value
+};
+
+# C-SJIS locale support
+# This option controls if the "C-SJIS" locale will be
+# supported by setlocale(). The locale is a hybrid locale
+# that is mostly the "C" locale with Japanese SJIS multibyte
+# support added.
+#
+cdl_option CYGFUN_LIBC_I18N_LOCALE_C_SJIS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # LegalValues: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2))) to 0x7fffffff
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # DefaultValue: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2)))
+};
+
+# C-JIS locale support
+# This option controls if the "C-JIS" locale will be
+# supported by setlocale(). The locale is a hybrid locale
+# that is mostly the "C" locale with Japanese JIS multibyte
+# support added.
+#
+cdl_option CYGFUN_LIBC_I18N_LOCALE_C_JIS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # LegalValues: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2))) to 0x7fffffff
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # DefaultValue: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2)))
+};
+
+# C-EUCJP locale support
+# This option controls if the "C-EUCJP" locale will be
+# supported by setlocale(). The locale is a hybrid locale
+# that is mostly the "C" locale with Japanese EUCJP multibyte
+# support added.
+#
+cdl_option CYGFUN_LIBC_I18N_LOCALE_C_EUCJP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # LegalValues: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2))) to 0x7fffffff
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # DefaultValue: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2)))
+};
+
+# <
+# Newlib's ctype implementation
+# This option enables the implementation of the ctype functions
+# that comes with newlib. It is table driven and therefore
+# exhibits different performance characteristics. It also offers
+# a limited amount of binary compatibility
+# with newlib so that programs linked against newlib ctype/locale
+# do not need to be recompiled when linked with eCos.
+#
+cdl_option CYGPKG_LIBC_I18N_NEWLIB_CTYPE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGBLD_ISO_CTYPE_HEADER == "<cyg/libc/i18n/newlibctype.h>"
+ # CYGBLD_ISO_CTYPE_HEADER == <cyg/libc/i18n/ctype.inl>
+ # --> 0
+};
+
+# Per-thread multibyte state
+# This option controls whether the multibyte character
+# handling functions mblen(), mbtowc(), and wctomb(),
+# have their state recorded on a per-thread
+# basis rather than global. If this option is
+# disabled, some per-thread space can be saved.
+# Enabling this option will use three slots
+# of kernel per-thread data. You should ensure you
+# have enough slots configured for all your
+# per-thread data.
+#
+cdl_option CYGSEM_LIBC_I18N_PER_THREAD_MB {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGVAR_KERNEL_THREADS_DATA != 0
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+ # Requires: CYGVAR_KERNEL_THREADS_DATA
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+};
+
+# Size of locale name strings
+# This option controls the maximum size of
+# locale names and is used, among other things
+# to instantiate a static string used
+# as a return value from the
+# setlocale() function. When requesting the
+# current locale settings with LC_ALL, a string
+# must be constructed to contain this data, rather
+# than just returning a constant string. This
+# string data is stored in the static string.
+# This depends on the length of locale names,
+# hence this option. If just the C locale is
+# present, this option can be set as low as 2.
+#
+cdl_option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 2
+ # value_source default
+ # Default value: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2)))
+ # CYGFUN_LIBC_I18N_LOCALE_C_EUCJP == 0
+ # CYGFUN_LIBC_I18N_LOCALE_C_SJIS == 0
+ # CYGFUN_LIBC_I18N_LOCALE_C_JIS == 0
+ # --> 2
+ # Legal values: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2))) to 0x7fffffff
+ # CYGFUN_LIBC_I18N_LOCALE_C_EUCJP == 0
+ # CYGFUN_LIBC_I18N_LOCALE_C_SJIS == 0
+ # CYGFUN_LIBC_I18N_LOCALE_C_JIS == 0
+};
+
+# Inline versions of <ctype.h> functions
+# This option chooses whether the simple character
+# classification and conversion functions (e.g.
+# isupper(), isalpha(), toupper(), etc.)
+# from <ctype.h> are available as inline
+# functions. This may improve performance and as
+# the functions are small, may even improve code
+# size.
+#
+cdl_option CYGIMP_LIBC_I18N_CTYPE_INLINES {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_CTYPE_HEADER == "<cyg/libc/i18n/ctype.inl>"
+ # CYGBLD_ISO_CTYPE_HEADER == <cyg/libc/i18n/ctype.inl>
+ # --> 1
+};
+
+# C library i18n functions build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_LIBC_I18N_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the C library. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_LIBC_I18N_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-fno-rtti -Woverloaded-virtual"
+ # value_source default
+ # Default value: "-fno-rtti -Woverloaded-virtual"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the C library. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_LIBC_I18N_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wno-pointer-sign
+ # value_source default
+ # Default value: -Wno-pointer-sign
+};
+
+# C library i18n function tests
+# This option specifies the set of tests for the C library
+# i18n functions.
+#
+cdl_option CYGPKG_LIBC_I18N_TESTS {
+ # Calculated value: "tests/ctype tests/setlocale tests/i18nmb"
+ # Flavor: data
+ # Current_value: tests/ctype tests/setlocale tests/i18nmb
+};
+
+# <
+# <
+# ISO C library general utility functions
+# doc: ref/libc.html
+# This package provides general utility functions in <stdlib.h>
+# as specified by the ISO C standard - ISO/IEC 9899:1990.
+#
+cdl_package CYGPKG_LIBC_STDLIB {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+ # Requires: CYGINT_ISO_CTYPE
+ # CYGINT_ISO_CTYPE == 1
+ # --> 1
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+};
+
+# >
+# Inline versions of <stdlib.h> functions
+# This option chooses whether some of the
+# particularly simple standard utility functions
+# from <stdlib.h> are available as inline
+# functions. This may improve performance, and as
+# the functions are small, may even improve code
+# size.
+#
+cdl_component CYGIMP_LIBC_STDLIB_INLINES {
+ # There is no associated value.
+};
+
+# >
+# abs() / labs()
+#
+cdl_option CYGIMP_LIBC_STDLIB_INLINE_ABS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_STDLIB_ABS_HEADER == "<cyg/libc/stdlib/abs.inl>"
+ # CYGBLD_ISO_STDLIB_ABS_HEADER == <cyg/libc/stdlib/abs.inl>
+ # --> 1
+};
+
+# div() / ldiv()
+#
+cdl_option CYGIMP_LIBC_STDLIB_INLINE_DIV {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_STDLIB_DIV_HEADER == "<cyg/libc/stdlib/div.inl>"
+ # CYGBLD_ISO_STDLIB_DIV_HEADER == <cyg/libc/stdlib/div.inl>
+ # --> 1
+};
+
+# atof() / atoi() / atol()
+#
+cdl_option CYGIMP_LIBC_STDLIB_INLINE_ATOX {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_STDLIB_STRCONV_HEADER == "<cyg/libc/stdlib/atox.inl>"
+ # CYGBLD_ISO_STDLIB_STRCONV_HEADER == <cyg/libc/stdlib/atox.inl>
+ # --> 1
+};
+
+# <
+# Random number generation
+# These options control the behaviour of the
+# functions rand(), srand() and rand_r()
+#
+cdl_component CYGPKG_LIBC_RAND {
+ # There is no associated value.
+};
+
+# >
+# Per-thread random seed
+# doc: ref/libc-thread-safety.html
+# This option controls whether the pseudo-random
+# number generation functions rand() and srand()
+# have their state recorded on a per-thread
+# basis rather than global. If this option is
+# disabled, some per-thread space can be saved.
+# Note there is also a POSIX-standard rand_r()
+# function to achieve a similar effect with user
+# support. Enabling this option will use one slot
+# of kernel per-thread data. You should ensure you
+# have enough slots configured for all your
+# per-thread data.
+#
+cdl_option CYGSEM_LIBC_PER_THREAD_RAND {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGVAR_KERNEL_THREADS_DATA
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+};
+
+# Random number seed
+# This selects the initial random number seed for
+# rand()'s pseudo-random number generator. For
+# strict ISO standard compliance, this should be 1,
+# as per section 7.10.2.2 of the standard.
+#
+cdl_option CYGNUM_LIBC_RAND_SEED {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Legal values: 0 to 0x7fffffff
+};
+
+# Tracing level
+# Trace verbosity level for debugging the rand(),
+# srand() and rand_r() functions. Increase this
+# value to get additional trace output.
+#
+cdl_option CYGNUM_LIBC_RAND_TRACE_LEVEL {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to 1
+};
+
+# Simplest implementation
+# This provides a very simple implementation of rand()
+# that does not perform well with randomness in the
+# lower significant bits. However it is exceptionally
+# fast. It uses the sample algorithm from the ISO C
+# standard itself.
+#
+cdl_option CYGIMP_LIBC_RAND_SIMPLEST {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Simple implementation #1
+# This provides a very simple implementation of rand()
+# based on the simplest implementation above. However
+# it does try to work around the lack of randomness
+# in the lower significant bits, at the expense of a
+# little speed.
+#
+cdl_option CYGIMP_LIBC_RAND_SIMPLE1 {
+ # Flavor: bool
+ user_value 0
+ # value_source user
+ # Default value: 1
+};
+
+# Knuth implementation #1
+# This implements a slightly more complex algorithm
+# published in Donald E. Knuth's Art of Computer
+# Programming Vol.2 section 3.6 (p.185 in the 3rd ed.).
+# This produces better random numbers than the
+# simplest approach but is slower.
+#
+cdl_option CYGIMP_LIBC_RAND_KNUTH1 {
+ # Flavor: bool
+ user_value 1
+ # value_source user
+ # Default value: 0
+};
+
+# <
+# Provides strtod()
+# This option allows use of the utility function
+# strtod() (and consequently atof()) to convert
+# from string to double precision floating point
+# numbers. Disabling this option removes the
+# dependency on the math library package.
+#
+cdl_option CYGFUN_LIBC_strtod {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0 != CYGPKG_LIBM
+ # CYGPKG_LIBM (unknown) == 0
+ # --> 0
+ # Requires: CYGPKG_LIBM
+ # CYGPKG_LIBM (unknown) == 0
+ # --> 0
+};
+
+# Provides long long conversion functions
+# Enabling this option will provide support for the strtoll(),
+# strtoull() and atoll() conversion functions, which are
+# the long long variants of the standard versions of these
+# functions. Supporting this requires extra code and compile
+# time.
+#
+cdl_option CYGFUN_LIBC_STDLIB_CONV_LONGLONG {
+ # Flavor: bool
+ user_value 0
+ # value_source user
+ # Default value: 1
+};
+
+# bsearch() tracing level
+# Trace verbosity level for debugging the <stdlib.h>
+# binary search function bsearch(). Increase this
+# value to get additional trace output.
+#
+cdl_option CYGNUM_LIBC_BSEARCH_TRACE_LEVEL {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to 1
+};
+
+# qsort() tracing level
+# Trace verbosity level for debugging the <stdlib.h>
+# quicksort function qsort(). Increase this value
+# to get additional trace output.
+#
+cdl_option CYGNUM_LIBC_QSORT_TRACE_LEVEL {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to 1
+};
+
+# C library stdlib build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_LIBC_STDLIB_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_LIBC_STDLIB_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-fno-rtti -Woverloaded-virtual"
+ # value_source default
+ # Default value: "-fno-rtti -Woverloaded-virtual"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_LIBC_STDLIB_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wno-pointer-sign
+ # value_source default
+ # Default value: -Wno-pointer-sign
+};
+
+# C library stdlib tests
+# This option specifies the set of tests for this package.
+#
+cdl_option CYGPKG_LIBC_STDLIB_TESTS {
+ # Calculated value: "tests/abs tests/atoi tests/atol tests/bsearch tests/div tests/getenv tests/labs tests/ldiv tests/qsort tests/rand1 tests/rand2 tests/rand3 tests/rand4 tests/srand tests/strtol tests/strtoul"
+ # Flavor: data
+ # Current_value: tests/abs tests/atoi tests/atol tests/bsearch tests/div tests/getenv tests/labs tests/ldiv tests/qsort tests/rand1 tests/rand2 tests/rand3 tests/rand4 tests/srand tests/strtol tests/strtoul
+};
+
+# <
+# <
+# <
+# eCos HAL
+# doc: ref/the-ecos-hardware-abstraction-layer.html
+# The eCos HAL package provide a porting layer for
+# higher-level parts of the system such as the kernel and the
+# C library. Each installation should have HAL packages for
+# one or more architectures, and for each architecture there
+# may be one or more supported platforms. It is necessary to
+# select one target architecture and one platform for that
+# architecture. There are also a number of configuration
+# options that are common to all HAL packages.
+#
+cdl_package CYGPKG_HAL {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGPKG_INFRA
+ # CYGPKG_INFRA == current
+ # --> 1
+
+ # The following properties are affected by this value
+};
+
+# >
+# Platform-independent HAL options
+# A number of configuration options are common to most or all
+# HAL packages, for example options controlling how much state
+# should be saved during a context switch. The implementations
+# of these options will vary from architecture to architecture.
+#
+cdl_component CYGPKG_HAL_COMMON {
+ # There is no associated value.
+};
+
+# >
+# Provide eCos kernel support
+# The HAL can be configured to either support the full eCos
+# kernel, or to support only very simple applications which do
+# not require a full kernel. If kernel support is not required
+# then some of the startup, exception, and interrupt handling
+# code can be eliminated.
+#
+cdl_option CYGFUN_HAL_COMMON_KERNEL_SUPPORT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+ # Requires: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+};
+
+# HAL exception support
+# When a processor exception occurs, for example an attempt to
+# execute an illegal instruction or to perform a divide by
+# zero, this exception may be handled in a number of different
+# ways. If the target system has gdb support then typically
+# the exception will be handled by gdb code. Otherwise if the
+# HAL exception support is enabled then the HAL will invoke a
+# routine deliver_exception(). Typically this routine will be
+# provided by the eCos kernel, but it is possible for
+# application code to provide its own implementation. If the
+# HAL exception support is not enabled and a processor
+# exception occurs then the behaviour of the system is
+# undefined.
+#
+cdl_option CYGPKG_HAL_EXCEPTIONS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGPKG_KERNEL_EXCEPTIONS
+ # CYGPKG_KERNEL_EXCEPTIONS (unknown) == 0
+ # --> 0
+ # Requires: CYGPKG_KERNEL_EXCEPTIONS
+ # CYGPKG_KERNEL_EXCEPTIONS (unknown) == 0
+ # --> 0
+};
+
+# Stop calling constructors early
+# This option supports environments where some constructors
+# must be run in the context of a thread rather than at
+# simple system startup time. A boolean flag named
+# cyg_hal_stop_constructors is set to 1 when constructors
+# should no longer be invoked. It is up to some other
+# package to deal with the rest of the constructors.
+# In the current version this is only possible with the
+# C library.
+#
+cdl_option CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGSEM_LIBC_INVOKE_DEFAULT_STATIC_CONSTRUCTORS
+ # CYGSEM_LIBC_INVOKE_DEFAULT_STATIC_CONSTRUCTORS (unknown) == 0
+ # --> 0
+};
+
+# HAL uses the MMU and allows for CDL manipulation of it's use
+#
+cdl_interface CYGINT_HAL_SUPPORTS_MMU_TABLES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_INSTALL_MMU_TABLES
+ # ActiveIf: CYGINT_HAL_SUPPORTS_MMU_TABLES
+};
+
+# Install MMU tables.
+# This option controls whether this application installs
+# its own Memory Management Unit (MMU) tables, or relies on the
+# existing environment to run.
+#
+cdl_option CYGSEM_HAL_INSTALL_MMU_TABLES {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_HAL_SUPPORTS_MMU_TABLES
+ # CYGINT_HAL_SUPPORTS_MMU_TABLES == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYG_HAL_STARTUP != "RAM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_STATIC_MMU_TABLES
+ # Requires: CYGSEM_HAL_INSTALL_MMU_TABLES
+};
+
+# Use static MMU tables.
+# This option defines an environment where any Memory
+# Management Unit (MMU) tables are constant. Normally used by ROM
+# based environments, this provides a way to save RAM usage which
+# would otherwise be required for these tables.
+#
+cdl_option CYGSEM_HAL_STATIC_MMU_TABLES {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGSEM_HAL_INSTALL_MMU_TABLES
+ # CYGSEM_HAL_INSTALL_MMU_TABLES == 0
+ # --> 0
+};
+
+# Route diagnostic output to debug channel
+# If not inheriting the console setup from the ROM monitor,
+# it is possible to redirect diagnostic output to the debug
+# channel by enabling this option. Depending on the debugger
+# used it may also be necessary to select a mangler for the
+# output to be displayed by the debugger.
+#
+cdl_component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN {
+ # ActiveIf constraint: !CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE == 0
+ # --> 1
+ # ActiveIf constraint: CYGPKG_HAL_ARM || CYGPKG_HAL_POWERPC_MPC8xx || CYGPKG_HAL_V85X_V850 || CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+ # CYGPKG_HAL_ARM == current
+ # CYGPKG_HAL_POWERPC_MPC8xx (unknown) == 0
+ # CYGPKG_HAL_V85X_V850 (unknown) == 0
+ # CYGSEM_HAL_VIRTUAL_VECTOR_DIAG == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: (CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS || CYG_HAL_STARTUP == "RAM") ? 1 : 0
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 0
+
+ # The following properties are affected by this value
+ # option CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ # Calculated: !CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE && !CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+};
+
+# >
+# Mangler used on diag output
+# It is sometimes necessary to mangle (encode) the
+# diag ASCII text output in order for it to show up at the
+# other end. In particular, GDB may silently ignore raw
+# ASCII text.
+#
+cdl_option CYGSEM_HAL_DIAG_MANGLER {
+ # This option is not active
+ # The parent CYGDBG_HAL_DIAG_TO_DEBUG_CHAN is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value GDB
+ # value_source default
+ # Default value: GDB
+ # Legal values: "GDB" "None"
+};
+
+# <
+# <
+# HAL interrupt handling
+# A number of configuration options related to interrupt
+# handling are common to most or all HAL packages, even though
+# the implementations will vary from architecture to
+# architecture.
+#
+cdl_component CYGPKG_HAL_COMMON_INTERRUPTS {
+ # There is no associated value.
+};
+
+# >
+# Use separate stack for interrupts
+# When an interrupt occurs this interrupt can be handled either
+# on the current stack or on a separate stack maintained by the
+# HAL. Using a separate stack requires a small number of extra
+# instructions in the interrupt handling code, but it has the
+# advantage that it is no longer necessary to allow extra space
+# in every thread stack for the interrupt handlers. The amount
+# of extra space required depends on the interrupt handlers
+# that are being used.
+#
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # package CYGPKG_REDBOOT
+ # Requires: CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK == 0
+};
+
+# Interrupt stack size
+# This configuration option specifies the stack size in bytes
+# for the interrupt stack. Typically this should be a multiple
+# of 16, but the exact requirements will vary from architecture
+# to architecture. The interrupt stack serves two separate
+# purposes. It is used as the stack during system
+# initialization. In addition, if the interrupt system is
+# configured to use a separate stack then all interrupts will
+# be processed on this stack. The exact memory requirements
+# will vary from application to application, and will depend
+# heavily on whether or not other interrupt-related options,
+# for example nested interrupts, are enabled. On most targets,
+# in a configuration with no kernel this stack will also be
+# the stack used to invoke the application, and must obviously
+# be appropriately large in that case.
+#
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 32768
+ # value_source default
+ # Default value: CYGPKG_KERNEL ? 4096 : 32768
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 32768
+ # Legal values: 128 to 1048576
+};
+
+# Allow nested interrupts
+# When an interrupt occurs the HAL interrupt handling code can
+# either leave interrupts disabled for the duration of the
+# interrupt handling code, or by doing some extra work it can
+# reenable interrupts before invoking the interrupt handler and
+# thus allow nested interrupts to happen. If all the interrupt
+# handlers being used are small and do not involve any loops
+# then it is usually better to disallow nested interrupts.
+# However if any of the interrupt handlers are more complicated
+# than nested interrupts will usually be required.
+#
+cdl_option CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Save minimum context on interrupt
+# The HAL interrupt handling code can exploit the calling conventions
+# defined for a given architecture to reduce the amount of state
+# that has to be saved. Generally this improves performance and
+# reduces code size. However it can make source-level debugging
+# more difficult.
+#
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # Requires: ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+};
+
+# Chain all interrupts together
+# Interrupts can be attached to vectors either singly, or be
+# chained together. The latter is necessary if there is no way
+# of discovering which device has interrupted without
+# inspecting the device itself. It can also reduce the amount
+# of RAM needed for interrupt decoding tables and code.
+#
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Ignore spurious [fleeting] interrupts
+# On some hardware, interrupt sources may not be de-bounced or
+# de-glitched. Rather than try to handle these interrupts (no
+# handling may be possible), this option allows the HAL to simply
+# ignore them. In most cases, if the interrupt is real it will
+# reoccur in a detectable form.
+#
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# HAL context switch support
+# A number of configuration options related to thread contexts
+# are common to most or all HAL packages, even though the
+# implementations will vary from architecture to architecture.
+#
+cdl_component CYGPKG_HAL_COMMON_CONTEXT {
+ # There is no associated value.
+
+ # The following properties are affected by this value
+};
+
+# >
+# Use minimum thread context
+# The thread context switch code can exploit the calling
+# conventions defined for a given architecture to reduce the
+# amount of state that has to be saved during a context
+# switch. Generally this improves performance and reduces
+# code size. However it can make source-level debugging more
+# difficult.
+#
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # Requires: ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+};
+
+# <
+# Explicit control over cache behaviour
+# These options let the default behaviour of the caches
+# be easily configurable.
+#
+cdl_component CYGPKG_HAL_CACHE_CONTROL {
+ # There is no associated value.
+};
+
+# >
+# Enable DATA cache on startup
+# Enabling this option will cause the data cache to be enabled
+# as soon as practicable when eCos starts up. One would choose
+# to disable this if the data cache cannot safely be turned on,
+# such as a case where the cache(s) require additional platform
+# specific setup.
+#
+cdl_component CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# DATA cache mode on startup
+# This option controls the mode the cache will be set to
+# when enabled on startup.
+#
+cdl_option CYGSEM_HAL_DCACHE_STARTUP_MODE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value COPYBACK
+ # value_source default
+ # Default value: COPYBACK
+ # Legal values: "COPYBACK" "WRITETHRU"
+};
+
+# <
+# Enable INSTRUCTION cache on startup
+# Enabling this option will cause the instruction cache to be enabled
+# as soon as practicable when eCos starts up. One would choose
+# to disable this if the instruction cache cannot safely be turned on,
+# such as a case where the cache(s) require additional platform
+# specific setup.
+#
+cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Source-level debugging support
+# If the source level debugger gdb is to be used for debugging
+# application code then it may be necessary to configure in support
+# for this in the HAL.
+#
+cdl_component CYGPKG_HAL_DEBUG {
+ # There is no associated value.
+};
+
+# >
+# Support for GDB stubs
+# The HAL implements GDB stubs for the target.
+#
+cdl_interface CYGINT_HAL_DEBUG_GDB_STUBS {
+ # Implemented by CYGPKG_HAL_ARM_TX27KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # ActiveIf: CYGINT_HAL_DEBUG_GDB_STUBS
+ # option CYGBLD_BUILD_REDBOOT_WITH_GDB
+ # ActiveIf: CYGINT_HAL_DEBUG_GDB_STUBS
+};
+
+# Include GDB stubs in HAL
+# This option causes a set of GDB stubs to be included into the
+# system. On some target systems the GDB support will be
+# provided by other means, for example by a ROM monitor. On
+# other targets, especially when building a ROM-booting system,
+# the necessary support has to go into the target library
+# itself. When GDB stubs are include in a configuration, HAL
+# serial drivers must also be included.
+#
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ # ActiveIf constraint: CYGINT_HAL_DEBUG_GDB_STUBS
+ # CYGINT_HAL_DEBUG_GDB_STUBS == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 0
+ # Requires: ! CYGSEM_HAL_USE_ROM_MONITOR
+ # CYGSEM_HAL_USE_ROM_MONITOR == 0
+ # --> 1
+ # Requires: ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ # CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT == 0
+ # --> 1
+ # Requires: ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ # CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM == 0
+ # --> 1
+ # Requires: !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # CYGSEM_HAL_VIRTUAL_VECTOR_DIAG == 1
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # DefaultValue: (CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS || CYG_HAL_STARTUP == "RAM") ? 1 : 0
+ # option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # DefaultValue: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # ActiveIf: CYGSEM_HAL_USE_ROM_MONITOR || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # DefaultValue: !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGBLD_BUILD_COMMON_GDB_STUBS
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGPKG_HAL_GDB_FILEIO
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGHWR_HAL_ARM_DUMP_EXCEPTIONS
+ # Requires: !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGBLD_BUILD_REDBOOT_WITH_GDB
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+};
+
+# Support for external break support in GDB stubs
+# The HAL implements external break (or asynchronous interrupt)
+# in the GDB stubs for the target.
+#
+cdl_interface CYGINT_HAL_DEBUG_GDB_STUBS_BREAK {
+ # Implemented by CYGPKG_HAL_ARM_TX27KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # ActiveIf: CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+};
+
+# Include GDB external break support for stubs
+# This option causes the GDB stub to add a serial interrupt handler
+# which will listen for GDB break packets. This lets you stop the
+# target asynchronously when using GDB, usually by hitting Control+C
+# or pressing the STOP button. This option differs from
+# CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT in that it is used when
+# GDB stubs are present.
+#
+cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT {
+ # ActiveIf constraint: CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+ # CYGINT_HAL_DEBUG_GDB_STUBS_BREAK == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # Requires: !CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # option CYGOPT_HAL_ARM_SYSCALL_GPROF_SUPPORT
+ # ActiveIf: CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT || CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # option CYGBLD_BUILD_REDBOOT_WITH_GDB
+ # Requires: CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+};
+
+# Platform does not support CTRLC
+#
+cdl_interface CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # ActiveIf: CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED == 0
+};
+
+# Include GDB external break support when no stubs
+# This option adds an interrupt handler for the GDB serial line
+# which will listen for GDB break packets. This lets you stop the
+# target asynchronously when using GDB, usually by hitting Control+C
+# or pressing the STOP button. This option differs from
+# CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT in that it is used when the GDB
+# stubs are NOT present.
+#
+cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT {
+ # This option is not active
+ # ActiveIf constraint: CYGSEM_HAL_USE_ROM_MONITOR || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGSEM_HAL_USE_ROM_MONITOR == 0
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+ # ActiveIf constraint: CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED == 0
+ # CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED == 0
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 1
+ # Requires: !CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGOPT_HAL_ARM_SYSCALL_GPROF_SUPPORT
+ # ActiveIf: CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT || CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+};
+
+# Include GDB multi-threading debug support
+# This option enables some extra HAL code which is needed
+# to support multi-threaded source level debugging.
+#
+cdl_option CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT {
+ # ActiveIf constraint: CYGSEM_HAL_ROM_MONITOR || CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT
+ # CYGSEM_HAL_ROM_MONITOR == 1
+ # CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT (unknown) == 0
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT
+ # Requires: CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ # option CYGBLD_BUILD_REDBOOT_WITH_THREADS
+ # Requires: CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+};
+
+# Number of times to retry sending a $O packet
+# This option controls the number of attempts that eCos programs
+# will make to send a $O packet to a host GDB process. If it is
+# set non-zero, then the target process will attempt to resend the
+# $O packet data up to this number of retries. Caution: use of
+# this option is not recommended as it can thoroughly confuse the
+# host GDB process.
+#
+cdl_option CYGNUM_HAL_DEBUG_GDB_PROTOCOL_RETRIES {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Timeout period for GDB packets
+# This option controls the time (in milliseconds) that eCos programs
+# will wait for a response when sending packets to a host GDB process.
+# If this time elapses, then the packet will be resent, up to some
+# maximum number of times (CYGNUM_HAL_DEBUG_GDB_PROTOCOL_RETRIES).
+#
+cdl_option CYGNUM_HAL_DEBUG_GDB_PROTOCOL_TIMEOUT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 500
+ # value_source default
+ # Default value: 500
+};
+
+# Location of CRC32 table
+# The stubs use a 1 kilobyte CRC table that can either be pregenerated
+# and placed in ROM, or generated at runtime in RAM. Depending on
+# your memory constraints, one of these options may be better.
+#
+cdl_option CYGDBG_HAL_CRCTABLE_LOCATION {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value RAM
+ # value_source default
+ # Default value: RAM
+ # Legal values: "ROM" "RAM"
+};
+
+# <
+# ROM monitor support
+# Support for ROM monitors can be built in to your application.
+# It may also be relevant to build your application as a ROM monitor
+# itself. Such options are contained here if relevant for your chosen
+# platform. The options and ROM monitors available to choose are
+# platform-dependent.
+#
+cdl_component CYGPKG_HAL_ROM_MONITOR {
+ # There is no associated value.
+
+ # The following properties are affected by this value
+};
+
+# >
+# Target has virtual vector support
+#
+cdl_interface CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT {
+ # Implemented by CYGPKG_HAL_ARM_TX27KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # component CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+ # ActiveIf: CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+};
+
+# Target supports baud rate control via vectors
+# Whether this target supports the __COMMCTL_GETBAUD
+# and __COMMCTL_SETBAUD virtual vector comm control operations.
+#
+cdl_interface CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT {
+ # Implemented by CYGPKG_HAL_ARM_MX27, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_VARIABLE_BAUD_RATE
+ # ActiveIf: CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+};
+
+# Enable use of virtual vector calling interface
+# Virtual vector support allows the HAL to let the ROM
+# monitor handle certain operations. The virtual vector table
+# defines a calling interface between applications running in
+# RAM and the ROM monitor.
+#
+cdl_component CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT {
+ # ActiveIf constraint: CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+ # CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT == 1
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+
+ # The following properties are affected by this value
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+ # package CYGPKG_DEVS_ETH_PHY
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+};
+
+# >
+# Inherit console settings from ROM monitor
+# When this option is set, the application will inherit
+# the console as set up by the ROM monitor. This means
+# that the application will use whatever channel and
+# mangling style was used by the ROM monitor when
+# the application was launched.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE {
+ # This option is not active
+ # ActiveIf constraint: CYGSEM_HAL_USE_ROM_MONITOR
+ # CYGSEM_HAL_USE_ROM_MONITOR == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: !CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS == 1
+ # --> 0
+
+ # The following properties are affected by this value
+ # component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # ActiveIf: !CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE
+ # option CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ # Calculated: !CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE && !CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+};
+
+# Debug channel is configurable
+# This option is a configuration hint - it is enabled
+# when the HAL initialization code will make use
+# of the debug channel configuration option.
+#
+cdl_option CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE {
+ # Calculated value: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS == 1
+ # Flavor: bool
+ # Current value: 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+ # ActiveIf: CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+};
+
+# Console channel is configurable
+# This option is a configuration hint - it is enabled
+# when the HAL initialization code will make use
+# of the console channel configuration option.
+#
+cdl_option CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE {
+ # Calculated value: !CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE && !CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE == 0
+ # CYGDBG_HAL_DIAG_TO_DEBUG_CHAN == 0
+ # Flavor: bool
+ # Current value: 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL
+ # ActiveIf: CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+};
+
+# Initialize whole of virtual vector table
+# This option will cause the whole of the virtual
+# vector table to be initialized with dummy values on
+# startup. When this option is enabled, all the
+# options below must also be enabled - or the
+# table would be empty when the application
+# launches.
+# On targets where older ROM monitors without
+# virtual vector support may still be in use, it is
+# necessary for RAM applictions to initialize the
+# table (since all HAL diagnostics and debug IO
+# happens via the table).
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYG_HAL_STARTUP != "RAM" || !CYGSEM_HAL_USE_ROM_MONITOR
+ # CYG_HAL_STARTUP == ROMRAM
+ # CYGSEM_HAL_USE_ROM_MONITOR == 0
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET == 1
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US == 1
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE == 1
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA == 1
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # ActiveIf: !CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_VERSION
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+};
+
+# Claim virtual vector table entries by default
+# By default most virtual vectors will be claimed by
+# RAM startup configurations, meaning that the RAM
+# application will provide the services. The
+# exception is COMMS support (HAL
+# diagnostics/debugging IO) which is left in the
+# control of the ROM monitor.
+# The reasoning behind this is to get as much of the
+# code exercised during regular development so it
+# is known to be working the few times a new ROM
+# monitor or a ROM production configuration is used
+# - COMMS are excluded only by necessity in order to
+# avoid breaking an existing debugger connections
+# (there may be ways around this).
+# For production RAM configurations this option can
+# be switched off, causing the appliction to rely on
+# the ROM monitor for these services, thus
+# saving some space.
+# Individual vectors may also be left unclaimed,
+# controlled by the below options (meaning that the
+# associated service provided by the ROM monitor
+# will be used).
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT {
+ # This option is not active
+ # ActiveIf constraint: !CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+};
+
+# Claim reset virtual vectors
+# This option will cause the reset and kill_by_reset
+# virtual vectors to be claimed.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET
+};
+
+# Claim version virtual vectors
+# This option will cause the version
+# virtual vectors to be claimed.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_VERSION {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # --> 1
+};
+
+# Claim delay_us virtual vector
+# This option will cause the delay_us
+# virtual vector to be claimed.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US
+};
+
+# Claim cache virtual vectors
+# This option will cause the cache virtual vectors
+# to be claimed.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE
+};
+
+# Claim data virtual vectors
+# This option will cause the data virtual vectors
+# to be claimed. At present there is only one, used
+# by the RedBoot ethernet driver to share diag output.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA
+};
+
+# Claim comms virtual vectors
+# This option will cause the communication tables
+# that are part of the virtual vectors mechanism to
+# be claimed. Note that doing this may cause an
+# existing ROM monitor communication connection to
+# be closed. For this reason, the option is disabled
+# per default for normal application
+# configurations.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # Requires: !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE
+ # DefaultValue: !CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # option CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ # Calculated: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+};
+
+# Do diagnostic IO via virtual vector table
+# All HAL IO happens via the virtual vector table / comm
+# tables when those tables are supported by the HAL.
+# If so desired, the low-level IO functions can
+# still be provided by the RAM application by
+# enabling the CLAIM_COMMS option.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_DIAG {
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+
+ # The following properties are affected by this value
+ # component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # ActiveIf: CYGPKG_HAL_ARM || CYGPKG_HAL_POWERPC_MPC8xx || CYGPKG_HAL_V85X_V850 || CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # Requires: !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+};
+
+# <
+# Behave as a ROM monitor
+# Enable this option if this program is to be used as a ROM monitor,
+# i.e. applications will be loaded into RAM on the TX27 module, and this
+# ROM monitor may process exceptions or interrupts generated from the
+# application. This enables features such as utilizing a separate
+# interrupt stack when exceptions are generated.
+#
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+ # Requires: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGBLD_ARM_ENABLE_THUMB_INTERWORK
+ # DefaultValue: (CYGHWR_THUMB || CYGSEM_HAL_ROM_MONITOR)
+ # option CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ # ActiveIf: CYGSEM_HAL_ROM_MONITOR || CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT
+ # option CYGPRI_REDBOOT_ROM_MONITOR
+ # Requires: CYGSEM_HAL_ROM_MONITOR
+};
+
+# Work with a ROM monitor
+# Support can be enabled for different varieties of ROM monitor.
+# This support changes various eCos semantics such as the encoding
+# of diagnostic output, or the overriding of hardware interrupt
+# vectors.
+# Firstly there is "Generic" support which prevents the HAL
+# from overriding the hardware vectors that it does not use, to
+# instead allow an installed ROM monitor to handle them. This is
+# the most basic support which is likely to be common to most
+# implementations of ROM monitor.
+# "GDB_stubs" provides support when GDB stubs are included in
+# the ROM monitor or boot ROM.
+#
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 0 0
+ # Legal values: "Generic" "GDB_stubs"
+ # Requires: CYG_HAL_STARTUP == "RAM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 0
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # Requires: ! CYGSEM_HAL_USE_ROM_MONITOR
+ # option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # ActiveIf: CYGSEM_HAL_USE_ROM_MONITOR || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE
+ # ActiveIf: CYGSEM_HAL_USE_ROM_MONITOR
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # DefaultValue: CYG_HAL_STARTUP != "RAM" || !CYGSEM_HAL_USE_ROM_MONITOR
+};
+
+# <
+# Platform defined I/O channels.
+# Platforms which provide additional I/O channels can implement
+# this interface, indicating that the function plf_if_init()
+# needs to be called.
+#
+cdl_interface CYGINT_HAL_PLF_IF_INIT {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+};
+
+# Platform IDE I/O support.
+# Platforms which provide IDE controllers can implement
+# this interface, indicating that IDE I/O macros are
+# available.
+#
+cdl_interface CYGINT_HAL_PLF_IF_IDE {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # component CYGSEM_REDBOOT_DISK_IDE
+ # ActiveIf: CYGINT_HAL_PLF_IF_IDE != 0
+};
+
+# File I/O operations via GDB
+# This option enables support for various file I/O
+# operations using the GDB remote protocol to communicate
+# with GDB. The operations are then performed on the
+# debugging host by proxy. These operations are only
+# currently available by using a system call interface
+# to RedBoot. This may change in the future.
+#
+cdl_option CYGPKG_HAL_GDB_FILEIO {
+ # This option is not active
+ # ActiveIf constraint: CYGSEM_REDBOOT_BSP_SYSCALLS
+ # CYGSEM_REDBOOT_BSP_SYSCALLS == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+};
+
+# Build Compiler sanity checking tests
+# Enabling this option causes compiler tests to be built.
+#
+cdl_option CYGPKG_HAL_BUILD_COMPILER_TESTS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # component CYGPKG_HAL_TESTS
+ # Calculated: "tests/context tests/basic"
+ # . ((!CYGINT_HAL_TESTS_NO_CACHES) ? " tests/cache" : "")
+ # . ((CYGPKG_HAL_BUILD_COMPILER_TESTS) ? " tests/cpp1 tests/vaargs" : "")
+ # . ((!CYGVAR_KERNEL_COUNTERS_CLOCK) ? " tests/intr" : "")
+};
+
+# Common HAL tests
+# This option specifies the set of tests for the common HAL.
+#
+cdl_component CYGPKG_HAL_TESTS {
+ # Calculated value: "tests/context tests/basic"
+ # . ((!CYGINT_HAL_TESTS_NO_CACHES) ? " tests/cache" : "")
+ # . ((CYGPKG_HAL_BUILD_COMPILER_TESTS) ? " tests/cpp1 tests/vaargs" : "")
+ # . ((!CYGVAR_KERNEL_COUNTERS_CLOCK) ? " tests/intr" : "")
+ # CYGINT_HAL_TESTS_NO_CACHES == 0
+ # CYGPKG_HAL_BUILD_COMPILER_TESTS == 0
+ # CYGVAR_KERNEL_COUNTERS_CLOCK (unknown) == 0
+ # Flavor: data
+ # Current_value: tests/context tests/basic tests/cache tests/intr
+};
+
+# >
+# Interface for cache presence
+# Some architectures and/or platforms do not have caches. By
+# implementing this interface, these can disable the various
+# cache-related tests.
+#
+cdl_interface CYGINT_HAL_TESTS_NO_CACHES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+
+ # The following properties are affected by this value
+ # component CYGPKG_HAL_TESTS
+ # Calculated: "tests/context tests/basic"
+ # . ((!CYGINT_HAL_TESTS_NO_CACHES) ? " tests/cache" : "")
+ # . ((CYGPKG_HAL_BUILD_COMPILER_TESTS) ? " tests/cpp1 tests/vaargs" : "")
+ # . ((!CYGVAR_KERNEL_COUNTERS_CLOCK) ? " tests/intr" : "")
+};
+
+# <
+# ARM architecture
+# The ARM architecture HAL package provides generic
+# support for this processor architecture. It is also
+# necessary to select a specific target platform HAL
+# package.
+#
+cdl_package CYGPKG_HAL_ARM {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # ActiveIf: CYGPKG_HAL_ARM || CYGPKG_HAL_POWERPC_MPC8xx || CYGPKG_HAL_V85X_V850 || CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+ # interface CYGINT_REDBOOT_ARM_FLASH_SIB_SUPPORTED
+ # ActiveIf: CYGPKG_HAL_ARM
+};
+
+# >
+# The CPU architecture supports THUMB mode
+#
+cdl_interface CYGINT_HAL_ARM_THUMB_ARCH {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_THUMB
+ # ActiveIf: CYGINT_HAL_ARM_THUMB_ARCH != 0
+ # option CYGBLD_ARM_ENABLE_THUMB_INTERWORK
+ # ActiveIf: CYGINT_HAL_ARM_THUMB_ARCH != 0
+};
+
+# Enable Thumb instruction set
+# Enable use of the Thumb instruction set.
+#
+cdl_option CYGHWR_THUMB {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_HAL_ARM_THUMB_ARCH != 0
+ # CYGINT_HAL_ARM_THUMB_ARCH == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGBLD_ARM_ENABLE_THUMB_INTERWORK
+ # DefaultValue: (CYGHWR_THUMB || CYGSEM_HAL_ROM_MONITOR)
+};
+
+# Enable Thumb interworking compiler option
+# This option controls the use of -mthumb-interwork in the
+# compiler flags. It defaults enabled in Thumb or ROM monitor
+# configurations, but can be overridden for reduced memory
+# footprint where interworking is not a requirement.
+#
+cdl_option CYGBLD_ARM_ENABLE_THUMB_INTERWORK {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_HAL_ARM_THUMB_ARCH != 0
+ # CYGINT_HAL_ARM_THUMB_ARCH == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: (CYGHWR_THUMB || CYGSEM_HAL_ROM_MONITOR)
+ # CYGHWR_THUMB == 0
+ # CYGSEM_HAL_ROM_MONITOR == 1
+ # --> 1
+};
+
+# The platform and architecture supports Big Endian operation
+#
+cdl_interface CYGINT_HAL_ARM_BIGENDIAN {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_BIGENDIAN
+ # ActiveIf: CYGINT_HAL_ARM_BIGENDIAN != 0
+};
+
+# Use big-endian mode
+# Use the CPU in big-endian mode.
+#
+cdl_option CYGHWR_HAL_ARM_BIGENDIAN {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_HAL_ARM_BIGENDIAN != 0
+ # CYGINT_HAL_ARM_BIGENDIAN == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# The platform uses a processor with an ARM7 core
+#
+cdl_interface CYGINT_HAL_ARM_ARCH_ARM7 {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # LegalValues: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" : ""
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" : ""
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" : ""
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" : ""
+ # ""
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # DefaultValue: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" :
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" :
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" :
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" :
+ # "unknown"
+};
+
+# The platform uses a processor with an ARM9 core
+#
+cdl_interface CYGINT_HAL_ARM_ARCH_ARM9 {
+ # Implemented by CYGPKG_HAL_ARM_MX27, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # LegalValues: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" : ""
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" : ""
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" : ""
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" : ""
+ # ""
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # DefaultValue: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" :
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" :
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" :
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" :
+ # "unknown"
+};
+
+# The platform uses a processor with a StrongARM core
+#
+cdl_interface CYGINT_HAL_ARM_ARCH_STRONGARM {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # LegalValues: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" : ""
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" : ""
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" : ""
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" : ""
+ # ""
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # DefaultValue: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" :
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" :
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" :
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" :
+ # "unknown"
+};
+
+# The platform uses a processor with a XScale core
+#
+cdl_interface CYGINT_HAL_ARM_ARCH_XSCALE {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # LegalValues: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" : ""
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" : ""
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" : ""
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" : ""
+ # ""
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # DefaultValue: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" :
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" :
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" :
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" :
+ # "unknown"
+};
+
+# ARM CPU family
+# It is possible to optimize code for different
+# ARM CPU families. This option selects which CPU to
+# optimize for on boards that support multiple CPU types.
+#
+cdl_option CYGHWR_HAL_ARM_CPU_FAMILY {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ARM9
+ # value_source default
+ # Default value: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" :
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" :
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" :
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" :
+ # "unknown"
+ # CYGINT_HAL_ARM_ARCH_ARM7 == 0
+ # CYGINT_HAL_ARM_ARCH_ARM9 == 1
+ # CYGINT_HAL_ARM_ARCH_STRONGARM == 0
+ # CYGINT_HAL_ARM_ARCH_XSCALE == 0
+ # --> ARM9
+ # Legal values: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" : ""
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" : ""
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" : ""
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" : ""
+ # ""
+ # CYGINT_HAL_ARM_ARCH_ARM7 == 0
+ # CYGINT_HAL_ARM_ARCH_ARM9 == 1
+ # CYGINT_HAL_ARM_ARCH_STRONGARM == 0
+ # CYGINT_HAL_ARM_ARCH_XSCALE == 0
+};
+
+# Provide diagnostic dump for exceptions
+# Print messages about hardware exceptions, including
+# raw exception frame dump and register contents.
+#
+cdl_option CYGHWR_HAL_ARM_DUMP_EXCEPTIONS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 1
+};
+
+# Process all exceptions with the eCos application
+# Normal RAM-based programs which do not include GDB stubs
+# defer processing of the illegal instruction exception to GDB.
+# Setting this options allows the program to explicitly handle
+# the illegal instruction exception itself. Note: this will
+# prevent the use of GDB to debug the application as breakpoints
+# will no longer work.
+#
+cdl_option CYGIMP_HAL_PROCESS_ALL_EXCEPTIONS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Support GDB thread operations via ICE/Multi-ICE
+# Allow GDB to get thread information via the ICE/Multi-ICE
+# connection.
+#
+cdl_option CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT == 1
+ # --> 1
+ # Requires: CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT
+ # CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT (unknown) == 0
+ # --> 0
+};
+
+# Support for 'gprof' callbacks
+# The ARM HAL provides the macro for 'gprof' callbacks from RedBoot
+# to acquire the interrupt-context PC and SP, when this option is
+# active.
+#
+cdl_option CYGOPT_HAL_ARM_SYSCALL_GPROF_SUPPORT {
+ # This option is not active
+ # ActiveIf constraint: CYGSEM_REDBOOT_BSP_SYSCALLS
+ # CYGSEM_REDBOOT_BSP_SYSCALLS == 0
+ # --> 0
+ # ActiveIf constraint: CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT || CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT == 0
+ # CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT == 0
+ # --> 0
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+};
+
+# Accept exceptions and irq's occurring in user mode
+# For standalone Redboot based programs running in user mode.
+#
+cdl_option CYGOPT_HAL_ARM_WITH_USER_MODE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Preserve svc spsr before returning to svc mode
+# This option secures exception and breakpoint processing
+# triggered during execution of application specific SWI
+# handlers.
+#
+cdl_option CYGOPT_HAL_ARM_PRESERVE_SVC_SPSR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Linker script
+#
+cdl_option CYGBLD_LINKER_SCRIPT {
+ # Calculated value: "src/arm.ld"
+ # Flavor: data
+ # Current_value: src/arm.ld
+};
+
+# Implementations of hal_arm_mem_real_region_top()
+#
+cdl_interface CYGINT_HAL_ARM_MEM_REAL_REGION_TOP {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+};
+
+# Freescale SoC architecture
+# This HAL variant package provides generic
+# support for the Freescale SoC. It is also
+# necessary to select a specific target platform HAL
+# package.
+#
+cdl_package CYGPKG_HAL_ARM_MX27 {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+};
+
+# >
+# PLL base clock
+# The processor can run at various frequencies.
+# These values are expressed in KHz. Note that there are
+# several steppings of the rate to run at different
+# maximum frequencies. Check the specs to make sure that your
+# particular processor can run at the rate you select here.
+#
+cdl_option CYGHWR_HAL_ARM_SOC_PLL_REF_CLOCK {
+ # Flavor: data
+ user_value 33554432
+ # value_source user
+ # Default value: 26000000
+ # Legal values: 26000000 27000000 33554432 32768000
+};
+
+# Processor clock rate
+# The processor can run at various frequencies.
+# These values are expressed in KHz. Note that there are
+# several steppings of the rate to run at different
+# maximum frequencies. Check the specs to make sure that your
+# particular processor can run at the rate you select here.
+#
+cdl_option CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 399
+ # value_source default
+ # Default value: CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT ?
+ # CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT : 399
+ # CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT (unknown) == 0
+ # CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT (unknown) == 0
+ # --> 399
+ # Legal values: 266 399
+};
+
+# System clock (hclk) rate
+# The processor can run at various frequencies.
+# These values are expressed in KHz. Note that there are
+# several steppings of the rate to run at different
+# maximum frequencies. Check the specs to make sure that your
+# particular processor can run at the rate you select here.
+#
+cdl_option CYGHWR_HAL_ARM_SOC_SYSTEM_CLOCK {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 133
+ # value_source default
+ # Default value: 133
+ # Legal values: 133 100
+};
+
+# Real-time clock constants
+#
+cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+ # There is no associated value.
+};
+
+# >
+# Real-time clock numerator
+#
+cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+ # Calculated value: 1000000000
+ # Flavor: data
+ # Current_value: 1000000000
+};
+
+# Real-time clock denominator
+# This option selects the heartbeat rate for the real-time clock.
+# The rate is specified in ticks per second. Change this value
+# with caution - too high and your system will become saturated
+# just handling clock interrupts, too low and some operations
+# such as thread scheduling may become sluggish.
+#
+cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 100
+ # value_source default
+ # Default value: 100
+
+ # The following properties are affected by this value
+ # option CYGNUM_HAL_RTC_PERIOD
+ # Calculated: (3686400/CYGNUM_HAL_RTC_DENOMINATOR)
+};
+
+# Real-time clock period
+#
+cdl_option CYGNUM_HAL_RTC_PERIOD {
+ # Calculated value: (3686400/CYGNUM_HAL_RTC_DENOMINATOR)
+ # CYGNUM_HAL_RTC_DENOMINATOR == 100
+ # Flavor: data
+ # Current_value: 36864
+};
+
+# <
+# UART1 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART1 {
+ # Implemented by CYGPKG_HAL_ARM_TX27KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+};
+
+# UART2 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART2 {
+ # Implemented by CYGPKG_HAL_ARM_TX27KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+};
+
+# UART3 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART3 {
+ # Implemented by CYGPKG_HAL_ARM_TX27KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+};
+
+# UART4 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART4 {
+ # Implemented by CYGPKG_HAL_ARM_TX27KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+};
+
+# UART5 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART5 {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+};
+
+# UART6 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART6 {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+};
+
+# Ka-Ro TX27 module
+# This HAL platform package provides generic
+# support for the Ka-Ro electronics TX27 module.
+#
+cdl_package CYGPKG_HAL_ARM_TX27KARO {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGINT_ISO_CTYPE
+ # CYGINT_ISO_CTYPE == 1
+ # --> 1
+ # Requires: CYGBLD_BUILD_REDBOOT == 1
+ # CYGBLD_BUILD_REDBOOT == 1
+ # --> 1
+};
+
+# >
+# Startup type
+# The only startup type allowed is ROMRAM, since this will allow
+# the program to exist in ROM, but be copied to RAM during startup
+# which is required to boot from NAND flash.
+#
+cdl_component CYG_HAL_STARTUP {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ROMRAM
+ # value_source default
+ # Default value: ROMRAM
+ # Legal values: "ROMRAM"
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_ROM_MONITOR
+ # Requires: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+ # option CYGSEM_HAL_ROM_MONITOR
+ # Requires: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+ # option CYGSEM_HAL_USE_ROM_MONITOR
+ # DefaultValue: CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0
+ # option CYGSEM_HAL_USE_ROM_MONITOR
+ # Requires: CYG_HAL_STARTUP == "RAM"
+ # option CYGSEM_HAL_INSTALL_MMU_TABLES
+ # DefaultValue: CYG_HAL_STARTUP != "RAM"
+ # component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # DefaultValue: (CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS || CYG_HAL_STARTUP == "RAM") ? 1 : 0
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # DefaultValue: CYG_HAL_STARTUP != "RAM" || !CYGSEM_HAL_USE_ROM_MONITOR
+ # option CYGBLD_BUILD_REDBOOT_WITH_THREADS
+ # ActiveIf: CYG_HAL_STARTUP != "RAM"
+ # option CYGPRI_REDBOOT_ROM_MONITOR
+ # ActiveIf: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+ # option CYGPRI_REDBOOT_ROM_MONITOR
+ # ActiveIf: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+};
+
+# Diagnostic serial port baud rate
+# This option selects the baud rate used for the console port.
+# Note: this should match the value chosen for the GDB port if the
+# console and GDB port are the same.
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 115200
+ # value_source default
+ # Default value: 115200
+ # Legal values: 9600 19200 38400 57600 115200
+};
+
+# GDB serial port baud rate
+# This option selects the baud rate used for the GDB port.
+# Note: this should match the value chosen for the console port if the
+# console and GDB port are the same.
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 115200
+ # value_source default
+ # Default value: 115200
+ # Legal values: 9600 19200 38400 57600 115200
+};
+
+# Number of communication channels on the TX27
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ # Calculated value: 3
+ # Flavor: data
+ # Current_value: 3
+
+ # The following properties are affected by this value
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+ # LegalValues: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ # LegalValues: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL
+ # LegalValues: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+};
+
+# Debug serial port
+# The TX27 provides access to three serial ports. This option
+# chooses which port will be used to connect to a host
+# running GDB.
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ # ActiveIf constraint: CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ # CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE == 1
+ # --> 1
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ # CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS == 3
+};
+
+# Default console channel.
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+ # Calculated value: 0
+ # Flavor: data
+ # Current_value: 0
+ # Legal values: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ # CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS == 3
+
+ # The following properties are affected by this value
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL
+ # DefaultValue: CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+};
+
+# Console serial port
+# The TX27 provides access to three serial ports. This option
+# chooses which port will be used for console output.
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ # ActiveIf constraint: CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ # CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE == 1
+ # --> 1
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ # CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT == 0
+ # --> 0
+ # Legal values: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ # CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS == 3
+};
+
+# Ka-Ro electronics TX27 module build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_HAL_ARM_TX27_OPTIONS {
+ # There is no associated value.
+ # Requires: CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0
+ # CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0
+ # --> 1
+};
+
+# >
+# SDRAM size
+# This option specifies the SDRAM size of the TX27 module.
+#
+cdl_option CYGNUM_HAL_ARM_TX27_SDRAM_SIZE {
+ # Flavor: data
+ user_value 0x08000000
+ # value_source user
+ # Default value: 0x04000000
+ # Legal values: 0x04000000 0x08000000
+};
+
+# Enable low level debugging with LED
+# This option enables low level debugging by blink codes
+# of the LED on STK5.
+#
+cdl_option CYGOPT_HAL_ARM_TX27_DEBUG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: false
+ # false (unknown) == 0
+ # --> 0
+};
+
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the TX27 HAL. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_HAL_ARM_TX27_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the TX27 HAL. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_HAL_ARM_TX27_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# <
+# Memory layout
+#
+cdl_component CYGHWR_MEMORY_LAYOUT {
+ # Calculated value: "arm_tx27_romram"
+ # Flavor: data
+ # Current_value: arm_tx27_romram
+};
+
+# >
+# Memory layout linker script fragment
+#
+cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ # Calculated value: "<pkgconf/mlt_arm_tx27_romram.ldi>"
+ # Flavor: data
+ # Current_value: <pkgconf/mlt_arm_tx27_romram.ldi>
+};
+
+# Memory layout header file
+#
+cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ # Calculated value: "<pkgconf/mlt_arm_tx27_romram.h>"
+ # Flavor: data
+ # Current_value: <pkgconf/mlt_arm_tx27_romram.h>
+};
+
+# <
+# <
+# <
+# <
+# <
+# Infrastructure
+# Common types and useful macros.
+# Tracing and assertion facilities.
+# Package startup options.
+#
+cdl_package CYGPKG_INFRA {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # package CYGPKG_HAL
+ # Requires: CYGPKG_INFRA
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGPKG_INFRA
+};
+
+# >
+# Asserts & Tracing
+# The eCos source code contains a significant amount of
+# internal debugging support, in the form of assertions and
+# tracing.
+# Assertions check at runtime that various conditions are as
+# expected; if not, execution is halted.
+# Tracing takes the form of text messages that are output
+# whenever certain events occur, or whenever functions are
+# called or return.
+# The most important property of these checks and messages is
+# that they are not required for the program to run.
+# It is prudent to develop software with assertions enabled,
+# but disable them when making a product release, thus
+# removing the overhead of that checking.
+# It is possible to enable assertions and tracing
+# independently.
+# There are also options controlling the exact behaviour of
+# the assertion and tracing facilities, thus giving users
+# finer control over the code and data size requirements.
+#
+cdl_component CYGPKG_INFRA_DEBUG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGNUM_INFRA_EMPTY_DELETE_THRESHOLD
+ # ActiveIf: CYGPKG_INFRA_DEBUG
+};
+
+# >
+# Use asserts
+# If this option is defined, asserts in the code are tested.
+# Assert functions (CYG_ASSERT()) are defined in
+# 'include/cyg/infra/cyg_ass.h' within the 'install' tree.
+# If it is not defined, these result in no additional
+# object code and no checking of the asserted conditions.
+#
+cdl_component CYGDBG_USE_ASSERTS {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: 1 == CYGINT_INFRA_DEBUG_TRACE_IMPL
+ # CYGINT_INFRA_DEBUG_TRACE_IMPL == 0
+ # --> 0
+
+ # The following properties are affected by this value
+ # option CYGDBG_MEMALLOC_ALLOCATOR_DLMALLOC_DEBUG
+ # Requires: CYGDBG_USE_ASSERTS
+ # option CYGDBG_MEMALLOC_ALLOCATOR_DLMALLOC_DEBUG
+ # DefaultValue: 0 != CYGDBG_USE_ASSERTS
+};
+
+# >
+# Preconditions
+# This option allows individual control of preconditions.
+# A precondition is one type of assert, which it is
+# useful to control separately from more general asserts.
+# The function is CYG_PRECONDITION(condition,msg).
+#
+cdl_option CYGDBG_INFRA_DEBUG_PRECONDITIONS {
+ # This option is not active
+ # The parent CYGDBG_USE_ASSERTS is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Postconditions
+# This option allows individual control of postconditions.
+# A postcondition is one type of assert, which it is
+# useful to control separately from more general asserts.
+# The function is CYG_POSTCONDITION(condition,msg).
+#
+cdl_option CYGDBG_INFRA_DEBUG_POSTCONDITIONS {
+ # This option is not active
+ # The parent CYGDBG_USE_ASSERTS is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Loop invariants
+# This option allows individual control of loop invariants.
+# A loop invariant is one type of assert, which it is
+# useful to control separately from more general asserts,
+# particularly since a loop invariant is typically evaluated
+# a great many times when used correctly.
+# The function is CYG_LOOP_INVARIANT(condition,msg).
+#
+cdl_option CYGDBG_INFRA_DEBUG_LOOP_INVARIANTS {
+ # This option is not active
+ # The parent CYGDBG_USE_ASSERTS is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Use assert text
+# All assertions within eCos contain a text message
+# which should give some information about the condition
+# being tested.
+# These text messages will end up being embedded in the
+# application image and hence there is a significant penalty
+# in terms of image size.
+# It is possible to suppress the use of these messages by
+# disabling this option.
+# This results in smaller code size, but there is less
+# human-readable information if an assertion actually gets
+# triggered.
+#
+cdl_option CYGDBG_INFRA_DEBUG_ASSERT_MESSAGE {
+ # This option is not active
+ # The parent CYGDBG_USE_ASSERTS is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Use tracing
+# If this option is defined, tracing operations
+# result in output or logging, depending on other options.
+# This may have adverse effects on performance, if the time
+# taken to output message overwhelms the available CPU
+# power or output bandwidth.
+# Trace functions (CYG_TRACE()) are defined in
+# 'include/cyg/infra/cyg_trac.h' within the 'install' tree.
+# If it is not defined, these result in no additional
+# object code and no trace information.
+#
+cdl_component CYGDBG_USE_TRACING {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: 1 == CYGINT_INFRA_DEBUG_TRACE_IMPL
+ # CYGINT_INFRA_DEBUG_TRACE_IMPL == 0
+ # --> 0
+
+ # The following properties are affected by this value
+ # option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_SIZE
+ # ActiveIf: CYGDBG_USE_TRACING
+ # option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_WRAP
+ # ActiveIf: CYGDBG_USE_TRACING
+ # option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_HALT
+ # ActiveIf: CYGDBG_USE_TRACING
+ # option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_PRINT
+ # ActiveIf: CYGDBG_USE_TRACING
+ # option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_PRINT_ON_ASSERT
+ # ActiveIf: CYGDBG_USE_TRACING
+};
+
+# >
+# Trace function reports
+# This option allows individual control of
+# function entry/exit tracing, independent of
+# more general tracing output.
+# This may be useful to remove clutter from a
+# trace log.
+#
+cdl_option CYGDBG_INFRA_DEBUG_FUNCTION_REPORTS {
+ # This option is not active
+ # The parent CYGDBG_USE_TRACING is not active
+ # The parent CYGDBG_USE_TRACING is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Use trace text
+# All trace calls within eCos contain a text message
+# which should give some information about the circumstances.
+# These text messages will end up being embedded in the
+# application image and hence there is a significant penalty
+# in terms of image size.
+# It is possible to suppress the use of these messages by
+# disabling this option.
+# This results in smaller code size, but there is less
+# human-readable information available in the trace output,
+# possibly only filenames and line numbers.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_MESSAGE {
+ # This option is not active
+ # The parent CYGDBG_USE_TRACING is not active
+ # The parent CYGDBG_USE_TRACING is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Trace output implementations
+#
+cdl_interface CYGINT_INFRA_DEBUG_TRACE_IMPL {
+ # Implemented by CYGDBG_INFRA_DEBUG_TRACE_ASSERT_NULL, inactive, disabled
+ # Implemented by CYGDBG_INFRA_DEBUG_TRACE_ASSERT_SIMPLE, inactive, disabled
+ # Implemented by CYGDBG_INFRA_DEBUG_TRACE_ASSERT_FANCY, inactive, disabled
+ # Implemented by CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER, inactive, enabled
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # component CYGDBG_USE_ASSERTS
+ # Requires: 1 == CYGINT_INFRA_DEBUG_TRACE_IMPL
+ # component CYGDBG_USE_TRACING
+ # Requires: 1 == CYGINT_INFRA_DEBUG_TRACE_IMPL
+};
+
+# Null output
+# A null output module which is useful when
+# debugging interactively; the output routines
+# can be breakpointed rather than have them actually
+# 'print' something.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_ASSERT_NULL {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Simple output
+# An output module which produces simple output
+# from tracing and assertion events.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_ASSERT_SIMPLE {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Fancy output
+# An output module which produces fancy output
+# from tracing and assertion events.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_ASSERT_FANCY {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Buffered tracing
+# An output module which buffers output
+# from tracing and assertion events. The stored
+# messages are output when an assert fires, or
+# CYG_TRACE_PRINT() (defined in <cyg/infra/cyg_trac.h>)
+# is called.
+# Of course, there will only be stored messages
+# if tracing per se (CYGDBG_USE_TRACING)
+# is enabled above.
+#
+cdl_component CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Trace buffer size
+# The size of the trace buffer. This counts the number
+# of trace records stored. When the buffer fills it
+# either wraps, stops recording, or generates output.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_SIZE {
+ # This option is not active
+ # The parent CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER is not active
+ # ActiveIf constraint: CYGDBG_USE_TRACING
+ # CYGDBG_USE_TRACING == 0
+ # --> 0
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 32
+ # value_source default
+ # Default value: 32
+ # Legal values: 5 to 65535
+};
+
+# Wrap trace buffer when full
+# When the trace buffer has filled with records it
+# starts again at the beginning. Hence only the last
+# CYGDBG_INFRA_DEBUG_TRACE_BUFFER_SIZE messages will
+# be recorded.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_WRAP {
+ # This option is not active
+ # The parent CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER is not active
+ # ActiveIf constraint: CYGDBG_USE_TRACING
+ # CYGDBG_USE_TRACING == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Halt trace buffer when full
+# When the trace buffer has filled with records it
+# stops recording. Hence only the first
+# CYGDBG_INFRA_DEBUG_TRACE_BUFFER_SIZE messages will
+# be recorded.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_HALT {
+ # This option is not active
+ # The parent CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER is not active
+ # ActiveIf constraint: CYGDBG_USE_TRACING
+ # CYGDBG_USE_TRACING == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Print trace buffer when full
+# When the trace buffer has filled with records it
+# prints the contents of the buffer. The buffer is then
+# emptied and the system continues.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_PRINT {
+ # This option is not active
+ # The parent CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER is not active
+ # ActiveIf constraint: CYGDBG_USE_TRACING
+ # CYGDBG_USE_TRACING == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Print trace buffer on assert fail
+# When an assertion fails the trace buffer will be
+# printed to the default diagnostic device.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_PRINT_ON_ASSERT {
+ # This option is not active
+ # The parent CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER is not active
+ # ActiveIf constraint: CYGDBG_USE_TRACING
+ # CYGDBG_USE_TRACING == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Use function names
+# All trace and assert calls within eCos contain a
+# reference to the builtin macro '__PRETTY_FUNCTION__',
+# which evaluates to a string containing
+# the name of the current function.
+# This is useful when reading a trace log.
+# It is possible to suppress the use of the function name
+# by disabling this option.
+# This results in smaller code size, but there is less
+# human-readable information available in the trace output,
+# possibly only filenames and line numbers.
+#
+cdl_option CYGDBG_INFRA_DEBUG_FUNCTION_PSEUDOMACRO {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Startup options
+# Some packages require a startup routine to be called.
+# This can be carried out by application code, by supplying
+# a routine called cyg_package_start() which calls the
+# appropriate package startup routine(s).
+# Alternatively, this routine can be constructed automatically
+# and configured to call the startup routines of your choice.
+#
+cdl_component CYGPKG_INFRA_STARTUP {
+ # There is no associated value.
+};
+
+# >
+# Start uITRON subsystem
+# Generate a call to initialize the
+# uITRON compatibility subsystem
+# within the system version of cyg_package_start().
+# This enables compatibility with uITRON.
+# You must configure uITRON with the correct tasks before
+# starting the uItron subsystem.
+# If this is disabled, and you want to use uITRON,
+# you must call cyg_uitron_start() from your own
+# cyg_package_start() or cyg_userstart().
+#
+cdl_option CYGSEM_START_UITRON_COMPATIBILITY {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_UITRON
+ # CYGPKG_UITRON (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGPKG_UITRON
+ # CYGPKG_UITRON (unknown) == 0
+ # --> 0
+};
+
+# <
+# Smaller slower memcpy()
+# Enabling this option causes the implementation of
+# the standard memcpy() routine to reduce code
+# size at the expense of execution speed. This
+# option is automatically enabled with the use of
+# the -Os option to the compiler. Also note that
+# the compiler will try to use its own builtin
+# version of memcpy() if possible, ignoring the
+# implementation in this package, unless given
+# the -fno-builtin compiler option.
+#
+cdl_option CYGIMP_INFRA_PREFER_SMALL_TO_FAST_MEMCPY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Smaller slower memset()
+# Enabling this option causes the implementation of
+# the standard memset() routine to reduce code
+# size at the expense of execution speed. This
+# option is automatically enabled with the use of
+# the -Os option to the compiler. Also note that
+# the compiler will try to use its own builtin
+# version of memset() if possible, ignoring the
+# implementation in this package, unless given
+# the -fno-builtin compiler option.
+#
+cdl_option CYGIMP_INFRA_PREFER_SMALL_TO_FAST_MEMSET {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Provide empty C++ delete functions
+# To deal with virtual destructors, where the correct delete()
+# function must be called for the derived class in question, the
+# underlying delete is called when needed, from destructors. This
+# is regardless of whether the destructor is called by delete itself.
+# So there is a reference to delete() from all destructors. The
+# default builtin delete() attempts to call free() if there is
+# one defined. So, if you have destructors, and you have free(),
+# as in malloc() and free(), any destructor counts as a reference
+# to free(). So the dynamic memory allocation code is linked
+# in regardless of whether it gets explicitly called. This
+# increases code and data size needlessly.
+# To defeat this undesirable behaviour, we define empty versions
+# of delete and delete. But doing this prevents proper use
+# of dynamic memory in C++ programs via C++'s new and delete
+# operators.
+# Therefore, this option is provided
+# for explicitly disabling the provision of these empty functions,
+# so that new and delete can be used, if that is what is required.
+#
+cdl_option CYGFUN_INFRA_EMPTY_DELETE_FUNCTIONS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Threshold for valid number of delete calls
+# Some users don't know about the empty delete function and then
+# wonder why their C++ classes are leaking memory. If
+# INFRA_DEBUG is enabled we keep a counter for the number of
+# times delete is called. If it goes above this threshold we throw
+# an assertion failure. This should point heavy users of
+# delete in the right direction without upsetting those who want
+# an empty delete function.
+#
+cdl_option CYGNUM_INFRA_EMPTY_DELETE_THRESHOLD {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_INFRA_DEBUG
+ # CYGPKG_INFRA_DEBUG == 0
+ # --> 0
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 100
+ # value_source default
+ # Default value: 100
+};
+
+# Provide dummy abort() function
+# This option controls the inclusion of a dummy abort() function.
+# Parts of the C and C++ compiler runtime systems contain references
+# to abort(), particulary in the C++ exception handling code. It is
+# not possible to eliminate these references, so this dummy function
+# in included to satisfy them. It is not expected that this function
+# will ever be called, so its current behaviour is to simply loop.
+#
+cdl_option CYGFUN_INFRA_DUMMY_ABORT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGINT_ISO_EXIT == 0
+ # CYGINT_ISO_EXIT == 0
+ # --> 1
+ # Requires: !CYGINT_ISO_EXIT
+ # CYGINT_ISO_EXIT == 0
+ # --> 1
+};
+
+# Reset platform at end of test case execution
+# If this option is set then test case programs will reset the platform
+# when they terminate, as opposed to the default which is to just hang
+# in a loop.
+#
+cdl_option CYGSEM_INFRA_RESET_ON_TEST_EXIT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Provide dummy strlen() function
+# This option controls the inclusion of a dummy strlen() function.
+# Parts of the C and C++ compiler runtime systems contain references
+# to strlen(), particulary in the C++ exception handling code. It is
+# not possible to eliminate these references, so this dummy function
+# in included to satisfy them. While it is not expected that this function
+# will ever be called, it is functional but uses the simplest, smallest
+# algorithm. There is a faster version of strlen() in the C library.
+#
+cdl_option CYGFUN_INFRA_DUMMY_STRLEN {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGINT_ISO_STRING_STRFUNCS == 0
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 0
+ # Requires: !CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 0
+};
+
+# Make all compiler warnings show as errors
+# Enabling this option will cause all compiler warnings to show
+# as errors and bring the library build to a halt. This is used
+# to ensure that the code base is warning free, and thus ensure
+# that newly introduced warnings stand out and get fixed before
+# they show up as weird run-time behavior.
+#
+cdl_option CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS {
+ # Flavor: bool
+ user_value 1
+ # value_source user
+ # Default value: 0
+ # Requires: is_substr(CYGBLD_GLOBAL_CFLAGS, " -Werror")
+ # CYGBLD_GLOBAL_CFLAGS == "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe"
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGBLD_GLOBAL_CFLAGS
+ # Requires: CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS
+};
+
+# Make compiler and assembler communicate by pipe
+# Enabling this option will cause the compiler to feed the
+# assembly output the the assembler via a pipe instead of
+# via a temporary file. This normally reduces the build
+# time.
+#
+cdl_option CYGBLD_INFRA_CFLAGS_PIPE {
+ # Flavor: bool
+ user_value 1
+ # value_source user
+ # Default value: 0
+ # Requires: is_substr(CYGBLD_GLOBAL_CFLAGS, " -pipe")
+ # CYGBLD_GLOBAL_CFLAGS == "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe"
+ # --> 1
+};
+
+# Infra build options
+# Package specific build options including control over
+# compiler flags used only in building this package.
+#
+cdl_component CYGPKG_INFRA_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the eCos infra package. These flags are used
+# in addition to the set of global flags.
+#
+cdl_option CYGPKG_INFRA_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-fno-rtti -Woverloaded-virtual"
+ # value_source default
+ # Default value: "-fno-rtti -Woverloaded-virtual"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the eCos infra package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_INFRA_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wno-pointer-sign
+ # value_source default
+ # Default value: -Wno-pointer-sign
+};
+
+# Suppressed linker flags
+# This option modifies the set of linker flags for
+# building the eCos infra package tests. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_INFRA_LDFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wl,--gc-sections
+ # value_source default
+ # Default value: -Wl,--gc-sections
+};
+
+# Additional linker flags
+# This option modifies the set of linker flags for
+# building the eCos infra package tests. These flags are added to
+# the set of global flags if present.
+#
+cdl_option CYGPKG_INFRA_LDFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wl,--fatal-warnings
+ # value_source default
+ # Default value: -Wl,--fatal-warnings
+};
+
+# Infra package tests
+#
+cdl_component CYGPKG_INFRA_TESTS {
+ # Calculated value: "tests/cxxsupp tests/diag_sprintf1 tests/diag_sprintf2"
+ # Flavor: data
+ # Current_value: tests/cxxsupp tests/diag_sprintf1 tests/diag_sprintf2
+};
+
+# >
+# Number of times a test runs
+# This option controls the number of times tests will execute their
+# basic function. Not all tests will honor this setting, but those
+# that do will execute the test N times before terminating. A value
+# less than 0 indicates to run forever.
+#
+cdl_option CYGNUM_TESTS_RUN_COUNT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# <
+# <
+# Redboot ROM monitor
+# doc: ref/redboot.html
+# This package supports the Redboot [stand-alone debug monitor]
+# using eCos as the underlying board support mechanism.
+#
+cdl_package CYGPKG_REDBOOT {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK == 0
+ # CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGPKG_REDBOOT_ARM_OPTIONS
+ # ActiveIf: CYGPKG_REDBOOT
+ # component CYGPKG_REDBOOT_HAL_OPTIONS
+ # ActiveIf: CYGPKG_REDBOOT
+ # component CYGPKG_REDBOOT_HAL_TX27_OPTIONS
+ # ActiveIf: CYGPKG_REDBOOT
+ # option CYGSEM_IO_ETH_DRIVERS_WARN
+ # ActiveIf: CYGPKG_REDBOOT
+};
+
+# >
+# Include support for ELF file format
+#
+cdl_component CYGSEM_REDBOOT_ELF {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Use the virtual address in the ELF headers
+# The ELF headers contain both a virtual and a physical address
+# for where code/data should be loaded. By default the physical
+# address is used but sometimes it is necassary to use the
+# virtual address because of bugy toolchains
+#
+cdl_option CYGOPT_REDBOOT_ELF_VIRTUAL_ADDRESS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Methods of loading images using redboot
+#
+cdl_interface CYGINT_REDBOOT_LOAD_METHOD {
+ # Implemented by CYGBLD_BUILD_REDBOOT_WITH_XYZMODEM, active, enabled
+ # Implemented by CYGPKG_REDBOOT_NETWORKING, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 2
+
+ # The following properties are affected by this value
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGINT_REDBOOT_LOAD_METHOD
+};
+
+# Build Redboot ROM ELF image
+# This option enables the building of the Redboot ELF image.
+# The image may require further relocation or symbol
+# stripping before being converted to a binary image.
+# This is handled by a rule in the target CDL.
+#
+cdl_component CYGBLD_BUILD_REDBOOT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+ # Requires: CYGPKG_INFRA
+ # CYGPKG_INFRA == current
+ # --> 1
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+ # Requires: ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT == 0
+ # --> 1
+ # Requires: ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ # CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT == 0
+ # --> 1
+ # Requires: ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ # CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM == 0
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT == 1
+ # --> 1
+ # Requires: CYGINT_ISO_STRING_MEMFUNCS
+ # CYGINT_ISO_STRING_MEMFUNCS == 1
+ # --> 1
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+ # Requires: CYGINT_REDBOOT_LOAD_METHOD
+ # CYGINT_REDBOOT_LOAD_METHOD == 2
+ # --> 1
+
+ # The following properties are affected by this value
+ # package CYGPKG_HAL_ARM_TX27KARO
+ # Requires: CYGBLD_BUILD_REDBOOT == 1
+ # option CYGBLD_BUILD_REDBOOT_BIN
+ # ActiveIf: CYGBLD_BUILD_REDBOOT
+};
+
+# >
+# Include GDB support in RedBoot
+# RedBoot normally includes support for the GDB debugging
+# protocols. This option allows this to be disabled which
+# may yield a substantial savings in terms of code and memory
+# usage by RedBoot.
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_GDB {
+ # ActiveIf constraint: CYGINT_HAL_DEBUG_GDB_STUBS
+ # CYGINT_HAL_DEBUG_GDB_STUBS == 1
+ # --> 1
+
+ # Flavor: bool
+ user_value 0
+ # value_source user
+ # Default value: 1
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT == 0
+ # --> 0
+};
+
+# Threads debugging support
+# Enabling this option will include special code in the
+# GDB stubs to support debugging of threaded programs. In
+# the case of eCos programs, this support allows GDB to
+# have complete access to the eCos threads in the
+# program.
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_THREADS {
+ # ActiveIf constraint: CYG_HAL_STARTUP != "RAM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT == 1
+ # --> 1
+};
+
+# Customized version string
+# Use this option to define a customized version "string" for
+# RedBoot. Note: this value is only cosmetic, displayed by the
+# "version" command, but is useful for providing site specific
+# information about the RedBoot configuration.
+#
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 "Ka-Ro 2009-06-10"
+ # value_source inferred
+ # Default value: 0 0
+};
+
+# Enable command line editing
+# If this option is non-zero, RedBoot will remember the
+# last N command lines. These lines may be reused.
+# Enabling this history will also enable rudimentary
+# editting of the lines themselves.
+#
+cdl_option CYGNUM_REDBOOT_CMD_LINE_EDITING {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 16
+ # value_source default
+ # Default value: 16
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_CMD_LINE_ANSI_SEQUENCES
+ # ActiveIf: CYGNUM_REDBOOT_CMD_LINE_EDITING != 0
+ # option CYGBLD_REDBOOT_CMD_LINE_HISTORY
+ # Requires: CYGNUM_REDBOOT_CMD_LINE_EDITING > 0
+};
+
+# Enable command line editing using ANSI arrows, etc
+# If this option is enabled, RedBoot will accept standard ANSI key
+# sequences for cursor movement (along with the emacs style keys).
+#
+cdl_option CYGSEM_REDBOOT_CMD_LINE_ANSI_SEQUENCES {
+ # ActiveIf constraint: CYGNUM_REDBOOT_CMD_LINE_EDITING != 0
+ # CYGNUM_REDBOOT_CMD_LINE_EDITING == 16
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Enable history command and expansion
+# Enabling this option will allow RedBoot to provide a
+# history command to list previous commands. Also enables
+# history expansion via '!' character similar to bash
+# shell.
+#
+cdl_option CYGBLD_REDBOOT_CMD_LINE_HISTORY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGNUM_REDBOOT_CMD_LINE_EDITING > 0
+ # CYGNUM_REDBOOT_CMD_LINE_EDITING == 16
+ # --> 1
+};
+
+# Number of unique RAM segments on platform
+# Change this option to be the number of memory segments which are
+# supported by the platform. If the value is greater than 1, then
+# a platform specific function must provide information about the
+# additional segments.
+#
+cdl_option CYGBLD_REDBOOT_MAX_MEM_SEGMENTS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include support gzip/zlib decompression
+#
+cdl_component CYGBLD_BUILD_REDBOOT_WITH_ZLIB {
+ # ActiveIf constraint: CYGPKG_COMPRESS_ZLIB
+ # CYGPKG_COMPRESS_ZLIB == current
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGOPT_REDBOOT_FIS_ZLIB_COMMON_BUFFER
+ # ActiveIf: CYGBLD_BUILD_REDBOOT_WITH_ZLIB && CYGOPT_REDBOOT_FIS
+};
+
+# >
+# Size of zlib decompression buffer
+# This is the size of the buffer filled with incoming data
+# during load before calls are made to the decompressor
+# function. For ethernet downloads this can be made bigger
+# (at the cost of memory), but for serial downloads on slow
+# processors it may be necessary to reduce the size to
+# avoid serial overruns. zlib appears to bail out if less
+# than five bytes are available initially so this is the
+# minimum.
+#
+cdl_option CYGNUM_REDBOOT_LOAD_ZLIB_BUFFER {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 64
+ # value_source default
+ # Default value: 64
+ # Legal values: 5 to 256
+};
+
+# Support compression of Flash images
+# This CDL indicates whether flash images can
+# be decompressed from gzip/zlib format into RAM.
+#
+cdl_option CYGPRI_REDBOOT_ZLIB_FLASH {
+ # ActiveIf constraint: CYGPKG_REDBOOT_FLASH
+ # CYGPKG_REDBOOT_FLASH == 1
+ # --> 1
+ # ActiveIf constraint: (!CYGSEM_IO_FLASH_READ_INDIRECT) || CYGPRI_REDBOOT_ZLIB_FLASH_FORCE
+ # CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # CYGPRI_REDBOOT_ZLIB_FLASH_FORCE == 1
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+};
+
+# Include GZIP uncompress command
+# Enable this option to include a 'gunzip' command
+# to uncompress GZIP compressed data.
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_GUNZIP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Turn on CYGPRI_REDBOOT_ZLIB_FLASH
+# Force CYGPRI_REDBOOT_ZLIB_FLASH to be chosen
+#
+cdl_option CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGPRI_REDBOOT_ZLIB_FLASH
+ # ActiveIf: (!CYGSEM_IO_FLASH_READ_INDIRECT) || CYGPRI_REDBOOT_ZLIB_FLASH_FORCE
+};
+
+# <
+# Include support for xyzModem downloads
+# doc: ref/download-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_XYZMODEM {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Allow the load-command write into Flash.
+# Write images direct to Flash via the load command.
+# We assume anything which is invalid RAM is flash, hence
+# the requires statement
+#
+cdl_option CYGBLD_REDBOOT_LOAD_INTO_FLASH {
+ # ActiveIf constraint: CYGPKG_REDBOOT_FLASH
+ # CYGPKG_REDBOOT_FLASH == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS
+ # CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS == 1
+ # --> 1
+};
+
+# Include MS Windows CE support
+# doc: ref/wince.html
+# This option enables MS Windows CE EShell support
+# and Windows CE .BIN images support
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_WINCE_SUPPORT {
+ # Flavor: bool
+ user_value 1
+ # value_source user
+ # Default value: 0
+};
+
+# Include support for MXC USB downloads
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_MXCUSB {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Include support for i.MX USB OTG downloads
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_IMXOTG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Include POSIX checksum command
+# doc: ref/cksum-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_CKSUM {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include memory fill command
+# doc: ref/mfill-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_MFILL {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include memory compare command
+# doc: ref/mcmp-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_MCMP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include memory copy command
+# doc: ref/mcopy-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_MCOPY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include memory dump command
+# doc: ref/dump-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_DUMP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include cache command
+# doc: ref/cache-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include exec command
+# doc: ref/exec-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGPKG_REDBOOT_ARM_LINUX_EXEC
+ # ActiveIf: CYGBLD_BUILD_REDBOOT_WITH_EXEC
+};
+
+# Include I/O Memory commands 'iopeek' and 'iopoke'
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_IOMEM {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Granularity of timer/ticks
+# This option controls the granularity of the timers.
+# Faster CPUs can afford higher granularity (lower values)
+# which should give higher network performance since the stack
+# is purely polled.
+#
+cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 250
+ # value_source default
+ # Default value: 250
+ # Legal values: 10 25 50 100 250 500 1000
+};
+
+# Redboot Networking
+# This option includes networking support in RedBoot.
+#
+cdl_component CYGPKG_REDBOOT_NETWORKING {
+ # ActiveIf constraint: CYGPKG_IO_ETH_DRIVERS
+ # CYGPKG_IO_ETH_DRIVERS == current
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_IO_ETH_DRIVERS_PASS_PACKETS
+ # DefaultValue: 0 != CYGPKG_REDBOOT_NETWORKING
+};
+
+# >
+# Print net debug information
+# This option is overriden by the configuration stored
+# in flash.
+#
+cdl_option CYGDBG_REDBOOT_NET_DEBUG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Support TFTP for download
+# This option enables the use of the TFTP protocol for
+# download
+#
+cdl_option CYGSEM_REDBOOT_NET_TFTP_DOWNLOAD {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Support HTTP for download
+# This option enables the use of the HTTP protocol for
+# download
+#
+cdl_option CYGSEM_REDBOOT_NET_HTTP_DOWNLOAD {
+ # Flavor: bool
+ user_value 0
+ # value_source user
+ # Default value: 1
+};
+
+# Default IP address
+# This IP address is the default used by RedBoot if
+# a BOOTP/DHCP server does not respond. The numbers
+# should be separated by *commas*, and not dots. If
+# an IP address is configured into the Flash
+# configuration, that will be used in preference.
+#
+cdl_component CYGDAT_REDBOOT_DEFAULT_IP_ADDR {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 0 0
+};
+
+# >
+# Do not try to use BOOTP
+# By default Redboot tries to use BOOTP to get an IP
+# address. If there's no BOOTP server on your network
+# use this option to avoid to wait until the
+# timeout. This option is overriden by the
+# configuration stored in flash.
+#
+cdl_option CYGSEM_REDBOOT_DEFAULT_NO_BOOTP {
+ # This option is not active
+ # The parent CYGDAT_REDBOOT_DEFAULT_IP_ADDR is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Default bootp server
+# This IP address is the default server
+# address used by RedBoot if a BOOTP/DHCP
+# server does not respond. The numbers should
+# be separated by *commas*, and not dots. If
+# an IP address is configured into the Flash
+# configuration, that will be used in
+# preference.
+#
+cdl_option CYGDAT_REDBOOT_DEFAULT_BOOTP_SERVER_IP_ADDR {
+ # This option is not active
+ # The parent CYGDAT_REDBOOT_DEFAULT_IP_ADDR is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 0 0
+};
+
+# <
+# Use DHCP to get IP information
+# Use DHCP protocol to obtain pertinent IP addresses, such
+# as the client, server, gateway, etc.
+#
+cdl_component CYGSEM_REDBOOT_NETWORKING_DHCP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGSEM_REDBOOT_NETWORKING_USE_GATEWAY
+ # Requires: CYGSEM_REDBOOT_NETWORKING_DHCP
+};
+
+# Use a gateway for non-local IP traffic
+# Enabling this option will allow the RedBoot networking
+# stack to use a [single] gateway to reach a non-local
+# IP address. If disabled, RedBoot will only be able to
+# reach nodes on the same subnet.
+#
+cdl_component CYGSEM_REDBOOT_NETWORKING_USE_GATEWAY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGSEM_REDBOOT_NETWORKING_DHCP
+ # CYGSEM_REDBOOT_NETWORKING_DHCP == 1
+ # --> 1
+};
+
+# >
+# Default gateway IP address
+# This IP address is the default used by RedBoot
+# if a BOOTP/DHCP server does not respond. The
+# numbers should be separated by *commas*, and
+# not dots. If an IP address is configured into
+# the Flash configuration, that will be used in
+# preference.
+#
+cdl_component CYGDAT_REDBOOT_DEFAULT_GATEWAY_IP_ADDR {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 0 0
+};
+
+# Default IP address mask
+# This IP address mask is the default used by
+# RedBoot if a BOOTP/DHCP server does not
+# respond. The numbers should be separated by
+# *commas*, and not dots. If an IP address is
+# configured into the Flash configuration, that
+# will be used in preference.
+#
+cdl_component CYGDAT_REDBOOT_DEFAULT_IP_ADDR_MASK {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "255, 255, 255, 0"
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 0 0
+};
+
+# <
+# TCP port to listen for incoming connections
+# RedBoot will 'listen' on this port for incoming TCP
+# connections. This allows outside connections to be made
+# to the platform, either for GDB or RedBoot commands.
+#
+cdl_option CYGNUM_REDBOOT_NETWORKING_TCP_PORT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 9000
+ # value_source default
+ # Default value: 9000
+};
+
+# Number of [network] packet buffers
+# RedBoot may need to buffer network data to support
+# various connections. This option allows control
+# over the number of such buffered packets, and in
+# turn, controls the amount of memory used by RedBoot
+# (which is not available to user applications).
+# Each packet buffer takes up about 1514 bytes.
+# Note: there is little need to make this larger than
+# the default.
+#
+cdl_option CYGNUM_REDBOOT_NETWORKING_MAX_PKTBUF {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 4
+ # value_source default
+ # Default value: 4
+ # Legal values: 3 to 8
+};
+
+# DNS support
+# When this option is enabled, RedBoot will be built with
+# support for DNS, allowing use of hostnames on the command
+# line.
+#
+cdl_component CYGPKG_REDBOOT_NETWORKING_DNS {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_NS_DNS
+ # CYGPKG_NS_DNS (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: !CYGPKG_NS_DNS_BUILD
+ # CYGPKG_NS_DNS_BUILD (unknown) == 0
+ # --> 1
+};
+
+# >
+# Default DNS IP
+# This option sets the IP of the default DNS. The IP can be
+# changed at runtime as well.
+#
+cdl_option CYGPKG_REDBOOT_NETWORKING_DNS_IP {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS is not active
+ # ActiveIf constraint: !CYGSEM_REDBOOT_FLASH_CONFIG
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 0
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0.0.0.0
+ # value_source default
+ # Default value: 0.0.0.0
+};
+
+# Timeout in DNS lookup
+# This option sets the timeout used when looking up an
+# address via the DNS. Default is 10 seconds.
+#
+cdl_option CYGNUM_REDBOOT_NETWORKING_DNS_TIMEOUT {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS is not active
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 10
+ # value_source default
+ # Default value: 10
+};
+
+# Support the use of a domain name
+# This option controls if Redboot supports domain
+# names when performing DNS lookups
+#
+cdl_component CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# >
+# Default DNS domain
+# This option sets the default DNS domain name.
+# This value will be overwritten by the value in
+# flash or a domain returned by DHCP
+#
+cdl_option CYGPKG_REDBOOT_NETWORKING_DNS_DEFAULT_DOMAIN {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Get DNS domain from Flash
+# This option enables getting the domain name
+# from the flash configuration. This can later be
+# overwritten by a value learnt from DHCP
+#
+cdl_option CYGPKG_REDBOOT_NETWORKING_DNS_FCONFIG_DOMAIN {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is disabled
+ # ActiveIf constraint: CYGSEM_REDBOOT_FLASH_CONFIG
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Use DNS domain from DHCP
+# This option enables the use of the domain name
+# returned by DHCP.
+#
+cdl_option CYGPKG_REDBOOT_NETWORKING_DNS_DHCP_DOMAIN {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# BOOTP/DHCP DNS domain buffer size
+# This options sets the size of the static
+# buffer used by BOOTP/DHCP to store the DNS
+# domain name. The domain name will not be
+# set if the buffer is too small to hold it.
+#
+cdl_option CYGNUM_REDBOOT_NETWORK_DNS_DOMAIN_BUFSIZE {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 32
+ # value_source default
+ # Default value: 32
+};
+
+# <
+# <
+# Default network device driver
+# This is the name of the default network device to use.
+#
+cdl_option CYGDAT_REDBOOT_DEFAULT_NETWORK_DEVICE {
+ # This option is not active
+ # ActiveIf constraint: CYGHWR_NET_DRIVERS > 1
+ # CYGHWR_NET_DRIVERS == 1
+ # --> 0
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "\"\""
+ # value_source default
+ # Default value: "\"\""
+};
+
+# Initialize only one net device
+# This option tells RedBoot to stop initializing network
+# devices when it finds the first device which is
+# successfully initialized. The default behavior causes
+# all network devices to be initialized.
+#
+cdl_option CYGSEM_REDBOOT_NETWORK_INIT_ONE_DEVICE {
+ # This option is not active
+ # ActiveIf constraint: CYGHWR_NET_DRIVERS > 1
+ # CYGHWR_NET_DRIVERS == 1
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Let RedBoot use any I/O channel for its console.
+# If this option is enabled then RedBoot will attempt to use all
+# defined serial I/O channels for its console device. Once input
+# arrives at one of these channels then the console will use only
+# that port.
+#
+cdl_option CYGPKG_REDBOOT_ANY_CONSOLE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+};
+
+# Let RedBoot adjust the baud rate of the serial console.
+# If this option is enabled then RedBoot will support commands
+# to set and query the baud rate on the selected console.
+#
+cdl_option CYGSEM_REDBOOT_VARIABLE_BAUD_RATE {
+ # ActiveIf constraint: CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+ # CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Run a platform specific startup function.
+# If this option is enabled then RedBoot will execute a platform
+# specific startup function before entering into its command line
+# processing. This allows the platform to perform any special
+# setups before RedBoot actually starts running. Note: the entire
+# RedBoot environment will already be initialized at this point.
+#
+cdl_option CYGSEM_REDBOOT_PLF_STARTUP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Run a platform specific ESA validation function.
+# If this option is enabled then RedBoot will execute a platform
+# specific function to validate an ethernet ESA. This would be
+# useful if the address must conform to standards set by the
+# hardware manufacturer, etc.
+#
+cdl_option CYGSEM_REDBOOT_PLF_ESA_VALIDATE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # component CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
+ # Requires: CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ # option CYGDAT_DEVS_ETH_ARM_TX27KARO_OUI
+ # ActiveIf: CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+};
+
+# Maximum command line length
+# This option allows control over how long the CLI command line
+# should be. This space will be allocated statically
+# rather than from RedBoot's stack.
+#
+cdl_option CYGPKG_REDBOOT_MAX_CMD_LINE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 256
+ # The inferred value should not be edited directly.
+ inferred_value 1024
+ # value_source inferred
+ # Default value: 256
+};
+
+# Command processing idle timeout (ms)
+# This option controls the timeout period before the
+# command processing is considered 'idle'. Making this
+# number smaller will cause idle processing to take place
+# more often, etc. The default value of 10ms is a reasonable
+# tradeoff between responsiveness and overhead.
+#
+cdl_option CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 10
+ # value_source default
+ # Default value: 10
+};
+
+# Validate RAM addresses during load
+# This option controls whether or not RedBoot will make
+# sure that memory being used by the "load" command is
+# in fact in user RAM. Leaving the option enabled makes
+# for a safer environment, but this check may not be valid
+# on all platforms, thus the ability to disable it.
+# ** Disable this only with great care **
+#
+cdl_option CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ # Requires: CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS
+};
+
+# Allow RedBoot to support FLASH programming
+# If this option is enabled then RedBoot will provide commands
+# to manage images in FLASH memory. These images can be loaded
+# into memory for execution or executed in place.
+#
+cdl_component CYGPKG_REDBOOT_FLASH {
+ # ActiveIf constraint: CYGHWR_IO_FLASH_DEVICE
+ # CYGHWR_IO_FLASH_DEVICE == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGPRI_REDBOOT_ZLIB_FLASH
+ # ActiveIf: CYGPKG_REDBOOT_FLASH
+ # option CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ # ActiveIf: CYGPKG_REDBOOT_FLASH
+};
+
+# >
+# Byte order used to store info in flash.
+# This option controls the byte ordering used to store
+# the FIS directory info and flash config info.
+#
+cdl_option CYGOPT_REDBOOT_FLASH_BYTEORDER {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value NATURAL
+ # value_source default
+ # Default value: NATURAL
+ # Legal values: "NATURAL" "MSBFIRST" "LSBFIRST"
+};
+
+# RedBoot Flash Image System support
+# doc: ref/flash-image-system.html
+# This option enables the Flash Image System commands
+# and support within RedBoot. If disabled, simple Flash
+# access commands such as "fis write" will still exist.
+# This option would be disabled for targets that need simple
+# FLASH manipulation, but do not have the need or space for
+# complete image management.
+#
+cdl_option CYGOPT_REDBOOT_FIS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGPKG_REDBOOT_FIS_CONTENTS
+ # ActiveIf: CYGOPT_REDBOOT_FIS
+ # option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
+ # ActiveIf: CYGOPT_REDBOOT_FIS && (CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == "FLASH")
+ # component CYGOPT_REDBOOT_FIS_ZLIB_COMMON_BUFFER
+ # ActiveIf: CYGBLD_BUILD_REDBOOT_WITH_ZLIB && CYGOPT_REDBOOT_FIS
+};
+
+# Max number of chunks of free space to manage
+# If this option is defined then "fis free" will
+# rely on the FIS directory to determine what space is
+# free within the FLASH. This option controls the
+# maximum number of free segment which can be handled
+# (typically this number is small). If this option is
+# not enabled, the the archaic behaviour of actually
+# scanning the FLASH for erased sectors (unreliable)
+# will be used to determine what's free and what's
+# not.
+#
+cdl_option CYGDAT_REDBOOT_FIS_MAX_FREE_CHUNKS {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 1 32
+ # value_source default
+ # Default value: 1 32
+};
+
+# Flash Image System default directory contents
+#
+cdl_component CYGPKG_REDBOOT_FIS_CONTENTS {
+ # ActiveIf constraint: CYGOPT_REDBOOT_FIS
+ # CYGOPT_REDBOOT_FIS == 1
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+};
+
+# >
+# Flash block containing the Directory
+# Which block of flash should hold the directory
+# information. Positive numbers are absolute block
+# numbers. Negative block numbers count backwards
+# from the last block. eg 2 means block 2, -2
+# means the last but one block.
+#
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -1
+ # value_source default
+ # Default value: -1
+
+ # The following properties are affected by this value
+ # option CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK
+ # Requires: CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK !=
+ # CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK
+};
+
+# Redundant Flash Image System Directory Support
+# This option enables the use of a redundant FIS
+# directory within RedBoot. If enabled a flash block
+# will be reserved for a second copy of the fis
+# directory. Doing this allow for power failure safe
+# updates of the directory by the application.
+#
+cdl_component CYGOPT_REDBOOT_REDUNDANT_FIS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: 0 == CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
+ # CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG == 1
+ # --> 0
+};
+
+# >
+# Flash block containing the backup Directory
+# Which block of flash should hold the redundant
+# directory information. Positive numbers are
+# absolute block numbers. Negative block numbers
+# count backwards from the last block. eg 2 means
+# block 2, -2 means the last but one block.
+#
+cdl_option CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK {
+ # This option is not active
+ # The parent CYGOPT_REDBOOT_REDUNDANT_FIS is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -3
+ # value_source default
+ # Default value: -3
+ # Requires: CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK !=
+ # CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK
+ # CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK == 0
+ # CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK == -1
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK
+ # Requires: CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK !=
+ # CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK
+};
+
+# <
+# Pseudo-file to describe reserved area
+# If an area of FLASH is reserved, it is informative to
+# have a fis entry describing it. This option controls
+# creation of such an entry by default in the fis init
+# command.
+#
+cdl_option CYGOPT_REDBOOT_FIS_RESERVED_BASE {
+ # This option is not active
+ # ActiveIf constraint: 0 != CYGNUM_REDBOOT_FLASH_RESERVED_BASE
+ # CYGNUM_REDBOOT_FLASH_RESERVED_BASE == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# File to describe RedBoot boot image
+# Normally a ROM-startup RedBoot image is first in the
+# FLASH, and the system boots using that image. This
+# option controls creation of an entry describing it in
+# the fis init command. It might be disabled if a
+# platform has an immutable boot image of its own, where
+# we use a POST-startup RedBoot instead, which performs
+# less board initialization.
+#
+cdl_option CYGOPT_REDBOOT_FIS_REDBOOT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGOPT_REDBOOT_FIS_REDBOOT_POST
+ # DefaultValue: !CYGOPT_REDBOOT_FIS_REDBOOT
+ # option CYGBLD_REDBOOT_MIN_IMAGE_SIZE
+ # DefaultValue: CYGOPT_REDBOOT_FIS_REDBOOT ? 0x20000 : 0
+};
+
+# File to describe RedBoot POST-compatible image
+# This option controls creation of an entry describing a
+# POST-startup RedBoot image in the fis init command.
+# Not all platforms support POST-startup. A platform
+# might have both for testing purposes, where the
+# eventual user would substitute their own POST code for
+# the initial ROM-startup RedBoot, and then jump to the
+# POST-compatible RedBoot immediately following.
+#
+cdl_component CYGOPT_REDBOOT_FIS_REDBOOT_POST {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: !CYGOPT_REDBOOT_FIS_REDBOOT
+ # CYGOPT_REDBOOT_FIS_REDBOOT == 1
+ # --> 0
+};
+
+# >
+# Offset of POST image from FLASH start
+# This option specifies the offset for a POST image from
+# the start of FLASH. If unset, then the fis entry
+# describing the POST image will be placed where
+# convenient.
+#
+cdl_option CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET {
+ # This option is not active
+ # The parent CYGOPT_REDBOOT_FIS_REDBOOT_POST is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+ # Requires: CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET >= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET == 0
+ # CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET
+ # Requires: CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET >= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+};
+
+# <
+# File to describe RedBoot backup image
+# This option controls creation of an entry describing a
+# backup RedBoot image in the fis init command.
+# Conventionally a RAM-startup RedBoot image is kept
+# under this name for use in updating the ROM-based
+# RedBoot that boots the board.
+#
+cdl_option CYGOPT_REDBOOT_FIS_REDBOOT_BACKUP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Include ARM SIB ID in FIS
+# If set, this option will cause the last 5 words of
+# the FIS to include the special ID needed for the
+# flash to be recognized as a reserved area for RedBoot
+# by an ARM BootRom monitor.
+#
+cdl_option CYGOPT_REDBOOT_FIS_DIRECTORY_ARM_SIB_ID {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Size of FIS directory entry
+# The FIS directory is limited to one single flash
+# sector. If your flash has tiny sectors, you may wish
+# to reduce this value in order to get more slots in
+# the FIS directory.
+#
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 256
+ # value_source default
+ # Default value: 256
+};
+
+# Number of FIS directory entries
+# The FIS directory normally occupies a single flash
+# sector. Adjusting this value can allow for more than
+# one flash sector to be used, which is useful if your
+# sectors are very small.
+#
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_COUNT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 8
+ # value_source default
+ # Default value: 8
+};
+
+# Maximum RedBoot image size
+# This option controls the maximum length reserved
+# for the RedBoot boot image in the FIS table.
+# This should be a multiple of the flash's erase
+# block size.
+#
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00020000
+ # The inferred value should not be edited directly.
+ inferred_value 0x00040000
+ # value_source inferred
+ # Default value: CYGOPT_REDBOOT_FIS_REDBOOT ? 0x20000 : 0
+ # CYGOPT_REDBOOT_FIS_REDBOOT == 1
+ # --> 0x00020000
+};
+
+# Offset from start of FLASH to RedBoot boot image
+# This option controls where the RedBoot boot image is
+# located relative to the start of FLASH.
+#
+cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGNUM_REDBOOT_FLASH_RESERVED_BASE
+ # CYGNUM_REDBOOT_FLASH_RESERVED_BASE == 0
+ # --> 0
+ # Requires: CYGNUM_REDBOOT_FLASH_RESERVED_BASE <= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # CYGNUM_REDBOOT_FLASH_RESERVED_BASE == 0
+ # CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET
+ # Requires: CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET >= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # Requires: CYGNUM_REDBOOT_FLASH_RESERVED_BASE <= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # component CYGPKG_HAL_ARM_TX27_OPTIONS
+ # Requires: CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0
+};
+
+# Size of reserved area at start of FLASH
+# This option reserves an area at the start of
+# FLASH where RedBoot will never interfere; it is
+# expected that this area contains
+# (non-RedBoot-based) POST code or some other boot
+# monitor that executes before RedBoot.
+#
+cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGOPT_REDBOOT_FIS_RESERVED_BASE
+ # ActiveIf: 0 != CYGNUM_REDBOOT_FLASH_RESERVED_BASE
+ # option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # DefaultValue: CYGNUM_REDBOOT_FLASH_RESERVED_BASE
+ # option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # Requires: CYGNUM_REDBOOT_FLASH_RESERVED_BASE <= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+};
+
+# <
+# Keep all RedBoot FLASH data blocks locked.
+# When this option is enabled, RedBoot will keep configuration
+# data and the FIS directory blocks implicitly locked. While
+# this is somewhat safer, it does add overhead during updates.
+#
+cdl_option CYGSEM_REDBOOT_FLASH_LOCK_SPECIAL {
+ # This option is not active
+ # ActiveIf constraint: CYGHWR_IO_FLASH_BLOCK_LOCKING != 0
+ # CYGHWR_IO_FLASH_BLOCK_LOCKING == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Use CRC checksums on FIS images.
+# When this option is enabled, RedBoot will use CRC checksums
+# when reading and writing flash images.
+#
+cdl_option CYGSEM_REDBOOT_FIS_CRC_CHECK {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# ARM FLASH drivers support SIB flash block structure
+# This interface is implemented by a flash driver
+# to indicate that it supports the ARM SIB flash
+# block structure
+#
+cdl_interface CYGINT_REDBOOT_ARM_FLASH_SIB_SUPPORTED {
+ # No options implement this inferface
+ # ActiveIf constraint: CYGPKG_HAL_ARM
+ # CYGPKG_HAL_ARM == current
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_REDBOOT_ARM_FLASH_SIB
+ # ActiveIf: CYGINT_REDBOOT_ARM_FLASH_SIB_SUPPORTED
+};
+
+# Use ARM SIB flash block structure
+# This option is used to interpret ARM Flash System
+# information blocks.
+#
+cdl_option CYGHWR_REDBOOT_ARM_FLASH_SIB {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_REDBOOT_ARM_FLASH_SIB_SUPPORTED
+ # CYGINT_REDBOOT_ARM_FLASH_SIB_SUPPORTED == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Keep RedBoot configuration data in FLASH
+# When this option is enabled, RedBoot will keep configuration
+# data in a separate block of FLASH memory. This data will
+# include such items as the node IP address or startup scripts.
+#
+cdl_component CYGSEM_REDBOOT_FLASH_CONFIG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGPKG_IO_FLASH != 0
+ # CYGPKG_IO_FLASH == current
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGDAT_REDBOOT_DEFAULT_IP_ADDR
+ # DefaultValue: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # option CYGDAT_REDBOOT_DEFAULT_BOOTP_SERVER_IP_ADDR
+ # DefaultValue: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # component CYGDAT_REDBOOT_DEFAULT_GATEWAY_IP_ADDR
+ # DefaultValue: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # component CYGDAT_REDBOOT_DEFAULT_IP_ADDR_MASK
+ # DefaultValue: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "255, 255, 255, 0"
+ # option CYGPKG_REDBOOT_NETWORKING_DNS_IP
+ # ActiveIf: !CYGSEM_REDBOOT_FLASH_CONFIG
+ # option CYGPKG_REDBOOT_NETWORKING_DNS_FCONFIG_DOMAIN
+ # ActiveIf: CYGSEM_REDBOOT_FLASH_CONFIG
+ # option CYGFUN_REDBOOT_BOOT_SCRIPT
+ # ActiveIf: CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT || CYGSEM_REDBOOT_FLASH_CONFIG
+};
+
+# >
+# Length of configuration data in FLASH
+# This option is used to control the amount of memory and FLASH
+# to be used for configuration options (persistent storage).
+#
+cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 4096
+ # value_source default
+ # Default value: 4096
+};
+
+# Style of media used for persistent data storage
+# Persistent data storage can either be held in 'norma' FLASH
+# or some other device (represented by the 'EEPROM' choice).
+# The different styles utilize different access methods.
+#
+cdl_option CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value FLASH
+ # value_source default
+ # Default value: FLASH
+ # Legal values: "FLASH" "EEPROM"
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
+ # ActiveIf: CYGOPT_REDBOOT_FIS && (CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == "FLASH")
+ # option CYGSEM_REDBOOT_FLASH_CONFIG_READONLY_FALLBACK
+ # DefaultValue: (CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == "FLASH")
+};
+
+# Merged config data and FIS directory
+# If this option is set, then the FIS directory and FLASH
+# configuration database will be stored in the same physical
+# FLASH block.
+#
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+ # ActiveIf constraint: CYGOPT_REDBOOT_FIS && (CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == "FLASH")
+ # CYGOPT_REDBOOT_FIS == 1
+ # CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == FLASH
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGOPT_REDBOOT_REDUNDANT_FIS
+ # Requires: 0 == CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
+};
+
+# Which block of flash to use
+# Which block of flash should hold the configuration
+# information. Positive numbers are absolute block numbers.
+# Negative block numbers count backwards from the last block.
+# eg 2 means block 2, -2 means the last but one block.
+#
+cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -2
+ # value_source default
+ # Default value: -2
+};
+
+# Support simple macros/aliases in FLASH
+# This option is used to allow support for simple text-based
+# macros (aliases). These aliases are kept in the FLASH
+# configuration data (persistent storage).
+#
+cdl_option CYGSEM_REDBOOT_FLASH_ALIASES {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Length of strings in FLASH configuration data
+# This option is used to control the amount of memory
+# and FLASH to be used for string configuration
+# options (persistent storage).
+#
+cdl_option CYGNUM_REDBOOT_FLASH_STRING_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 128
+ # value_source default
+ # Default value: 128
+};
+
+# Length of configuration script(s) in FLASH
+# This option is used to control the amount of memory and
+# FLASH to be used for configuration options (persistent
+# storage).
+#
+cdl_option CYGNUM_REDBOOT_FLASH_SCRIPT_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 512
+ # The inferred value should not be edited directly.
+ inferred_value 2048
+ # value_source inferred
+ # Default value: 512
+};
+
+# Fallback to read-only FLASH configuration
+# This option will cause the configuration information to
+# revert to the readonly information stored in the FLASH.
+# The option only takes effect after
+# 1) the config_ok flag has been set to be true,
+# indicating that at one time the copy in RAM was valid;
+# and
+# 2) the information in RAM has been verified to be invalid
+#
+cdl_option CYGSEM_REDBOOT_FLASH_CONFIG_READONLY_FALLBACK {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: (CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == "FLASH")
+ # CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == FLASH
+ # --> 1
+};
+
+# <
+# Allow RedBoot to support fileio
+# If this option is enabled then RedBoot will provide commands
+# to load files from fileio file systems such as JFFS2.
+#
+cdl_component CYGPKG_REDBOOT_FILEIO {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_IO_FILEIO
+ # CYGPKG_IO_FILEIO (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_REDBOOT_GETC_BUFFER
+ # DefaultValue: CYGPKG_REDBOOT_FILEIO ? 4096 : 256
+};
+
+# >
+# Include an ls command
+# If this option is enabled a simple ls command will be
+# included in redboot so the contents of a directory
+# can be listed
+#
+cdl_option CYGBLD_REDBOOT_FILEIO_WITH_LS {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_FILEIO is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Allow RedBoot to support disks
+# If this option is enabled then RedBoot will provide commands
+# to load disk files.
+#
+cdl_component CYGPKG_REDBOOT_DISK {
+ # Flavor: bool
+ user_value 0
+ # value_source user
+ # Default value: 1
+};
+
+# >
+# Include Redboot commands for disk access
+#
+cdl_option CYGSEM_REDBOOT_DISK {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGINT_REDBOOT_DISK_DRIVERS != 0
+ # CYGINT_REDBOOT_DISK_DRIVERS == 0
+ # --> 0
+};
+
+# Hardware drivers for disk-type devices
+#
+cdl_interface CYGINT_REDBOOT_DISK_DRIVERS {
+ # Implemented by CYGSEM_REDBOOT_DISK_IDE, inactive, enabled
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_DISK
+ # DefaultValue: CYGINT_REDBOOT_DISK_DRIVERS != 0
+};
+
+# Maximum number of supported disks
+# This option controls the number of disks supported by
+# RedBoot.
+#
+cdl_option CYGNUM_REDBOOT_MAX_DISKS {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 4
+ # value_source default
+ # Default value: 4
+};
+
+# Maximum number of partitions per disk
+# This option controls the maximum number of supported
+# partitions per disk.
+#
+cdl_option CYGNUM_REDBOOT_MAX_PARTITIONS {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 8
+ # value_source default
+ # Default value: 8
+};
+
+# Support IDE disks.
+# When this option is enabled, RedBoot will support IDE disks.
+#
+cdl_component CYGSEM_REDBOOT_DISK_IDE {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+ # ActiveIf constraint: CYGINT_HAL_PLF_IF_IDE != 0
+ # CYGINT_HAL_PLF_IF_IDE == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Work with VMware virtual disks
+# This option controls the disk driver behavior at
+# ide-init
+#
+cdl_option CYGSEM_REDBOOT_DISK_IDE_VMWARE {
+ # This option is not active
+ # The parent CYGSEM_REDBOOT_DISK_IDE is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Support Linux second extended filesystems.
+# When this option is enabled, RedBoot will support EXT2
+# filesystems.
+#
+cdl_component CYGSEM_REDBOOT_DISK_EXT2FS {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Support ISO9660 filesystems.
+# When this option is enabled, RedBoot will support ISO9660
+# filesystems.
+#
+cdl_component CYGSEM_REDBOOT_DISK_ISO9660 {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # Calculated value: 0
+ # Flavor: bool
+ # Current value: 0
+};
+
+# <
+# Boot scripting
+# doc: ref/persistent-state-flash.html
+# This contains options related to RedBoot's boot script
+# functionality.
+#
+cdl_component CYGPKG_REDBOOT_BOOT_SCRIPT {
+ # There is no associated value.
+};
+
+# >
+# Boot scripting enabled
+# This option controls whether RedBoot boot script
+# functionality is enabled.
+#
+cdl_option CYGFUN_REDBOOT_BOOT_SCRIPT {
+ # ActiveIf constraint: CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT || CYGSEM_REDBOOT_FLASH_CONFIG
+ # CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT == 0
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+};
+
+# Use default RedBoot boot script
+# If enabled, this option will tell RedBoot to use the
+# value of this option as a default boot script.
+#
+cdl_option CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 0 0
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGFUN_REDBOOT_BOOT_SCRIPT
+ # ActiveIf: CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT || CYGSEM_REDBOOT_FLASH_CONFIG
+};
+
+# Resolution (in ms) for script timeout value.
+# This option controls the resolution of the script
+# timeout. The value is specified in milliseconds
+# (ms), thus to have the script timeout be defined in
+# terms of tenths of seconds, use 100.
+#
+cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_TIMEOUT_RESOLUTION {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 1000
+ # The inferred value should not be edited directly.
+ inferred_value 10
+ # value_source inferred
+ # Default value: 1000
+};
+
+# Script default timeout value
+# This option is used to set the default timeout for startup
+# scripts, when they are enabled.
+#
+cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_DEFAULT_TIMEOUT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 10
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 10
+};
+
+# <
+# Support RTC for time & date functions
+# When this option is enabled, RedBoot will support commands to
+# query and set the real time clock (time and date)
+#
+cdl_option CYGSEM_REDBOOT_RTC {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_IO_WALLCLOCK
+ # CYGPKG_IO_WALLCLOCK (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Behave like a ROM monitor
+# Enabling this option will allow RedBoot to provide ROM
+# monitor-style services to programs which it executes.
+#
+cdl_option CYGPRI_REDBOOT_ROM_MONITOR {
+ # ActiveIf constraint: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+ # Requires: CYGSEM_HAL_ROM_MONITOR
+ # CYGSEM_HAL_ROM_MONITOR == 1
+ # --> 1
+};
+
+# Allow RedBoot to handle GNUPro application 'syscalls'.
+# If this option is enabled then RedBoot will install a
+# syscall handler to support debugging of applications
+# based on GNUPro newlib/bsp.
+#
+cdl_component CYGSEM_REDBOOT_BSP_SYSCALLS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGOPT_HAL_ARM_SYSCALL_GPROF_SUPPORT
+ # ActiveIf: CYGSEM_REDBOOT_BSP_SYSCALLS
+ # option CYGPKG_HAL_GDB_FILEIO
+ # ActiveIf: CYGSEM_REDBOOT_BSP_SYSCALLS
+};
+
+# >
+# Support additional syscalls for 'gprof' profiling
+# Support additional syscalls to support a periodic callback
+# function for histogram-style profiling, and an enquire/set
+# of the tick rate.
+# The application must use the GNUPro newlib facilities
+# to set this up.
+#
+cdl_option CYGSEM_REDBOOT_BSP_SYSCALLS_GPROF {
+ # This option is not active
+ # The parent CYGSEM_REDBOOT_BSP_SYSCALLS is disabled
+ # ActiveIf constraint: 0 < CYGINT_REDBOOT_BSP_SYSCALLS_GPROF_SUPPORT
+ # CYGINT_REDBOOT_BSP_SYSCALLS_GPROF_SUPPORT == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Does the HAL support 'gprof' profiling?
+#
+cdl_interface CYGINT_REDBOOT_BSP_SYSCALLS_GPROF_SUPPORT {
+ # Implemented by CYGOPT_HAL_ARM_SYSCALL_GPROF_SUPPORT, inactive, enabled
+ # This option is not active
+ # The parent CYGSEM_REDBOOT_BSP_SYSCALLS is disabled
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_BSP_SYSCALLS_GPROF
+ # ActiveIf: 0 < CYGINT_REDBOOT_BSP_SYSCALLS_GPROF_SUPPORT
+};
+
+# Do not raise SIGTRAP when program exits
+# For some (single shot) newlib based programs,
+# exiting and returning a termination status may be
+# the normal expected behavior.
+#
+cdl_option CYGOPT_REDBOOT_BSP_SYSCALLS_EXIT_WITHOUT_TRAP {
+ # This option is not active
+ # The parent CYGSEM_REDBOOT_BSP_SYSCALLS is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Use a common buffer for Zlib and FIS
+# Use a common memory buffer for both the zlib workspace
+# and FIS directory operations. This can save a substantial
+# amount of RAM, especially when flash sectors are large.
+#
+cdl_component CYGOPT_REDBOOT_FIS_ZLIB_COMMON_BUFFER {
+ # ActiveIf constraint: CYGBLD_BUILD_REDBOOT_WITH_ZLIB && CYGOPT_REDBOOT_FIS
+ # CYGBLD_BUILD_REDBOOT_WITH_ZLIB == 1
+ # CYGOPT_REDBOOT_FIS == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# >
+# Size of Zlib/FIS common buffer
+# Size of common buffer to allocate. Must be at least the
+# size of one flash sector.
+#
+cdl_option CYGNUM_REDBOOT_FIS_ZLIB_COMMON_BUFFER_SIZE {
+ # This option is not active
+ # The parent CYGOPT_REDBOOT_FIS_ZLIB_COMMON_BUFFER is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x0000C000
+ # value_source default
+ # Default value: 0x0000C000
+ # Legal values: 0x4000 to 0x80000000
+};
+
+# <
+# Buffer size in getc when loading images
+# When loading images a buffer is used between redboot and the
+# underlying storage medium, eg a filesystem, or a socket etc.
+# The size of this buffer can have a big impart on load speed.
+#
+cdl_option CYGNUM_REDBOOT_GETC_BUFFER {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 256
+ # value_source default
+ # Default value: CYGPKG_REDBOOT_FILEIO ? 4096 : 256
+ # CYGPKG_REDBOOT_FILEIO == 0
+ # --> 256
+};
+
+# <
+# Redboot for ARM options
+# This option lists the target's requirements for a valid Redboot
+# configuration.
+#
+cdl_component CYGPKG_REDBOOT_ARM_OPTIONS {
+ # ActiveIf constraint: CYGPKG_REDBOOT
+ # CYGPKG_REDBOOT == current
+ # --> 1
+
+ # There is no associated value.
+
+ # The following properties are affected by this value
+};
+
+# >
+# Provide the exec command in RedBoot
+# This option contains requirements for booting linux
+# from RedBoot. The component is enabled/disabled from
+# RedBoots CDL.
+#
+cdl_component CYGPKG_REDBOOT_ARM_LINUX_EXEC {
+ # ActiveIf constraint: CYGBLD_BUILD_REDBOOT_WITH_EXEC
+ # CYGBLD_BUILD_REDBOOT_WITH_EXEC == 1
+ # --> 1
+
+ # There is no associated value.
+};
+
+# >
+# Enable -x switch for exec command.
+# This option allows bi-endian platforms to launch kernels
+# built for an endianess different than the RedBoot endianess
+#
+cdl_option CYGHWR_REDBOOT_LINUX_EXEC_X_SWITCH {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Physical base address of linux kernel
+# This is the physical address of the base of the
+# Linux kernel image.
+#
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0xA0108000
+ # value_source default
+ # Default value: CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT
+ # CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0xA0108000
+ # --> 0xA0108000
+};
+
+# Default physical base address of linux kernel
+# This is the physical address of the base of the
+# Linux kernel image. This option gets set by the
+# platform CDL.
+#
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00008000
+ # The inferred value should not be edited directly.
+ inferred_value 0xA0108000
+ # value_source inferred
+ # Default value: 0x00008000
+
+ # The following properties are affected by this value
+ # option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS
+ # DefaultValue: CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT
+ # component CYGPKG_REDBOOT_HAL_TX27_OPTIONS
+ # Requires: CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0xA0108000
+};
+
+# Base address of linux kernel parameter tags
+# This is the base address of the area of memory used to
+# pass parameters to the Linux kernel. This should be chosen
+# to avoid overlap with the kernel and any ramdisk image.
+#
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_TAGS_ADDRESS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00000100
+ # value_source default
+ # Default value: 0x00000100
+};
+
+# <
+# <
+# Redboot HAL options
+# This option lists the target's requirements for a valid Redboot
+# configuration.
+#
+cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ # ActiveIf constraint: CYGPKG_REDBOOT
+ # CYGPKG_REDBOOT == current
+ # --> 1
+
+ # There is no associated value.
+};
+
+# >
+# Build Redboot ROM binary image
+# This option enables the conversion of the Redboot ELF
+# image to a binary image suitable for ROM programming.
+#
+cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ # ActiveIf constraint: CYGBLD_BUILD_REDBOOT
+ # CYGBLD_BUILD_REDBOOT == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Redboot HAL variant options
+#
+cdl_component CYGPKG_REDBOOT_HAL_TX27_OPTIONS {
+ # ActiveIf constraint: CYGPKG_REDBOOT
+ # CYGPKG_REDBOOT == current
+ # --> 1
+
+ # There is no associated value.
+ # Requires: CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0xA0108000
+ # CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0xA0108000
+ # --> 1
+};
+
+# <
+# ISO C and POSIX infrastructure
+# eCos supports implementations of ISO C libraries and POSIX
+# implementations. This package provides infrastructure used by
+# all such implementations.
+#
+cdl_package CYGPKG_ISOINFRA {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGPKG_ISOINFRA
+ # package CYGPKG_LIBC_STRING
+ # Requires: CYGPKG_ISOINFRA
+ # package CYGPKG_COMPRESS_ZLIB
+ # Requires: CYGPKG_ISOINFRA
+ # package CYGPKG_IO_FLASH
+ # Requires: CYGPKG_ISOINFRA
+ # option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_USE_MEMCPY
+ # Requires: CYGPKG_ISOINFRA
+ # option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_USE_MEMCPY
+ # DefaultValue: 0 != CYGPKG_ISOINFRA
+ # component CYGPKG_MEMALLOC_MALLOC_ALLOCATORS
+ # ActiveIf: CYGPKG_ISOINFRA
+ # package CYGPKG_LIBC_I18N
+ # Requires: CYGPKG_ISOINFRA
+ # package CYGPKG_LIBC_STDLIB
+ # Requires: CYGPKG_ISOINFRA
+};
+
+# >
+# Startup and termination
+#
+cdl_component CYGPKG_ISO_STARTUP {
+ # There is no associated value.
+};
+
+# >
+# main() startup implementations
+# Implementations of this interface arrange for a user-supplied
+# main() to be called in an ISO compatible environment.
+#
+cdl_interface CYGINT_ISO_MAIN_STARTUP {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_MAIN_STARTUP
+ # CYGINT_ISO_MAIN_STARTUP == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_MAIN_STARTUP
+ # Requires: 1 >= CYGINT_ISO_MAIN_STARTUP
+};
+
+# environ implementations
+# Implementations of this interface provide the environ
+# variable required by POSIX.
+#
+cdl_interface CYGINT_ISO_ENVIRON {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_ENVIRON
+ # CYGINT_ISO_ENVIRON == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_ENVIRON
+ # Requires: 1 >= CYGINT_ISO_ENVIRON
+};
+
+# <
+# ctype.h functions
+#
+cdl_component CYGPKG_ISO_CTYPE_H {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of ctype functions
+#
+cdl_interface CYGINT_ISO_CTYPE {
+ # Implemented by CYGPKG_LIBC_I18N, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_CTYPE
+ # CYGINT_ISO_CTYPE == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_CTYPE
+ # Requires: 1 >= CYGINT_ISO_CTYPE
+ # package CYGPKG_HAL_ARM_TX27KARO
+ # Requires: CYGINT_ISO_CTYPE
+ # option CYGFUN_LIBC_STRING_BSD_FUNCS
+ # Requires: CYGINT_ISO_CTYPE
+ # package CYGPKG_LIBC_STDLIB
+ # Requires: CYGINT_ISO_CTYPE
+};
+
+# Ctype implementation header
+#
+cdl_option CYGBLD_ISO_CTYPE_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/i18n/ctype.inl>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGPKG_LIBC_I18N_NEWLIB_CTYPE
+ # Requires: CYGBLD_ISO_CTYPE_HEADER == "<cyg/libc/i18n/newlibctype.h>"
+ # option CYGIMP_LIBC_I18N_CTYPE_INLINES
+ # Requires: CYGBLD_ISO_CTYPE_HEADER == "<cyg/libc/i18n/ctype.inl>"
+};
+
+# <
+# Error handling
+#
+cdl_component CYGPKG_ISO_ERRNO {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of error codes
+#
+cdl_interface CYGINT_ISO_ERRNO_CODES {
+ # Implemented by CYGPKG_ERROR, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_ERRNO_CODES
+ # CYGINT_ISO_ERRNO_CODES == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_ERRNO_CODES
+ # Requires: 1 >= CYGINT_ISO_ERRNO_CODES
+};
+
+# Error codes implementation header
+#
+cdl_option CYGBLD_ISO_ERRNO_CODES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/error/codes.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # package CYGPKG_ERROR
+ # Requires: CYGBLD_ISO_ERRNO_CODES_HEADER == "<cyg/error/codes.h>"
+};
+
+# Number of implementations of errno variable
+#
+cdl_interface CYGINT_ISO_ERRNO {
+ # Implemented by CYGPKG_ERROR_ERRNO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_ERRNO
+ # CYGINT_ISO_ERRNO == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_ERRNO
+ # Requires: 1 >= CYGINT_ISO_ERRNO
+};
+
+# errno variable implementation header
+#
+cdl_option CYGBLD_ISO_ERRNO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/error/errno.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # component CYGPKG_ERROR_ERRNO
+ # Requires: CYGBLD_ISO_ERRNO_HEADER == "<cyg/error/errno.h>"
+};
+
+# <
+# Locale-related functions
+#
+cdl_component CYGPKG_ISO_LOCALE {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of locale functions
+#
+cdl_interface CYGINT_ISO_LOCALE {
+ # Implemented by CYGPKG_LIBC_I18N, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_LOCALE
+ # CYGINT_ISO_LOCALE == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_LOCALE
+ # Requires: 1 >= CYGINT_ISO_LOCALE
+};
+
+# Locale implementation header
+#
+cdl_option CYGBLD_ISO_LOCALE_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Standard I/O-related functionality
+#
+cdl_component CYGPKG_ISO_STDIO {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of stdio file types
+#
+cdl_interface CYGINT_ISO_STDIO_FILETYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILETYPES
+ # CYGINT_ISO_STDIO_FILETYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_FILETYPES
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILETYPES
+};
+
+# Stdio file types implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_FILETYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Stdio standard streams implementations
+#
+cdl_interface CYGINT_ISO_STDIO_STREAMS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_STREAMS
+ # CYGINT_ISO_STDIO_STREAMS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_STREAMS
+ # Requires: 1 >= CYGINT_ISO_STDIO_STREAMS
+};
+
+# Stdio standard streams implementation header
+# This header file must define stdin, stdout
+# and stderr.
+#
+cdl_option CYGBLD_ISO_STDIO_STREAMS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio file operations
+#
+cdl_interface CYGINT_ISO_STDIO_FILEOPS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEOPS
+ # CYGINT_ISO_STDIO_FILEOPS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_FILEOPS
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEOPS
+};
+
+# Stdio file operations implementation header
+# This header controls the file system operations on a file
+# such as remove(), rename(), tmpfile(), tmpnam() and associated
+# constants.
+#
+cdl_option CYGBLD_ISO_STDIO_FILEOPS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio file access functionals
+#
+cdl_interface CYGINT_ISO_STDIO_FILEACCESS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEACCESS
+ # CYGINT_ISO_STDIO_FILEACCESS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_FILEACCESS
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEACCESS
+ # option CYGFUN_COMPRESS_ZLIB_GZIO
+ # Requires: CYGINT_ISO_STDIO_FILEACCESS
+};
+
+# Stdio file access implementation header
+# This header controls the file access operations
+# such as fclose(), fflush(), fopen(), freopen(), setbuf(),
+# setvbuf(), and associated constants.
+#
+cdl_option CYGBLD_ISO_STDIO_FILEACCESS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio formatted I/O
+#
+cdl_interface CYGINT_ISO_STDIO_FORMATTED_IO {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_FORMATTED_IO
+ # CYGINT_ISO_STDIO_FORMATTED_IO == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_FORMATTED_IO
+ # Requires: 1 >= CYGINT_ISO_STDIO_FORMATTED_IO
+ # option CYGFUN_COMPRESS_ZLIB_GZIO
+ # Requires: CYGINT_ISO_STDIO_FORMATTED_IO
+};
+
+# Stdio formatted I/O implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_FORMATTED_IO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio character I/O
+#
+cdl_interface CYGINT_ISO_STDIO_CHAR_IO {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_CHAR_IO
+ # CYGINT_ISO_STDIO_CHAR_IO == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_CHAR_IO
+ # Requires: 1 >= CYGINT_ISO_STDIO_CHAR_IO
+};
+
+# Stdio character I/O implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_CHAR_IO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio direct I/O
+#
+cdl_interface CYGINT_ISO_STDIO_DIRECT_IO {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_DIRECT_IO
+ # CYGINT_ISO_STDIO_DIRECT_IO == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_DIRECT_IO
+ # Requires: 1 >= CYGINT_ISO_STDIO_DIRECT_IO
+};
+
+# Stdio direct I/O implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_DIRECT_IO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio file positioning
+#
+cdl_interface CYGINT_ISO_STDIO_FILEPOS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEPOS
+ # CYGINT_ISO_STDIO_FILEPOS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_FILEPOS
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEPOS
+ # option CYGFUN_COMPRESS_ZLIB_GZIO
+ # Requires: CYGINT_ISO_STDIO_FILEPOS
+};
+
+# Stdio file positioning implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_FILEPOS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio error handling
+#
+cdl_interface CYGINT_ISO_STDIO_ERROR {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_ERROR
+ # CYGINT_ISO_STDIO_ERROR == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_ERROR
+ # Requires: 1 >= CYGINT_ISO_STDIO_ERROR
+};
+
+# Stdio error handling implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_ERROR_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX fd-related function implementations
+#
+cdl_interface CYGINT_ISO_STDIO_POSIX_FDFUNCS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_POSIX_FDFUNCS
+ # CYGINT_ISO_STDIO_POSIX_FDFUNCS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_POSIX_FDFUNCS
+ # Requires: 1 >= CYGINT_ISO_STDIO_POSIX_FDFUNCS
+};
+
+# POSIX fd-related function implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_POSIX_FDFUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Standard general utility functions
+#
+cdl_component CYGPKG_ISO_STDLIB {
+ # There is no associated value.
+};
+
+# >
+# String conversion function implementations
+#
+cdl_interface CYGINT_ISO_STDLIB_STRCONV {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_STRCONV
+ # CYGINT_ISO_STDLIB_STRCONV == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDLIB_STRCONV
+ # Requires: 1 >= CYGINT_ISO_STDLIB_STRCONV
+};
+
+# String conversion function implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_STRCONV_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/stdlib/atox.inl>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGIMP_LIBC_STDLIB_INLINE_ATOX
+ # Requires: CYGBLD_ISO_STDLIB_STRCONV_HEADER == "<cyg/libc/stdlib/atox.inl>"
+};
+
+# String to FP conversion function implementations
+#
+cdl_interface CYGINT_ISO_STDLIB_STRCONV_FLOAT {
+ # Implemented by CYGFUN_LIBC_strtod, active, disabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_STDLIB_STRCONV_FLOAT
+ # CYGINT_ISO_STDLIB_STRCONV_FLOAT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDLIB_STRCONV_FLOAT
+ # Requires: 1 >= CYGINT_ISO_STDLIB_STRCONV_FLOAT
+};
+
+# String to FP conversion function implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_STRCONV_FLOAT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Random number generator implementations
+#
+cdl_interface CYGINT_ISO_RAND {
+ # Implemented by CYGIMP_LIBC_RAND_SIMPLEST, active, disabled
+ # Implemented by CYGIMP_LIBC_RAND_SIMPLE1, active, disabled
+ # Implemented by CYGIMP_LIBC_RAND_KNUTH1, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_RAND
+ # CYGINT_ISO_RAND == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_RAND
+ # Requires: 1 >= CYGINT_ISO_RAND
+};
+
+# Random number generator implementation header
+#
+cdl_option CYGBLD_ISO_RAND_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Malloc implementations
+#
+cdl_interface CYGINT_ISO_MALLOC {
+ # Implemented by CYGPKG_MEMALLOC_MALLOC_ALLOCATORS, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_MALLOC
+ # CYGINT_ISO_MALLOC == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_MALLOC
+ # Requires: 1 >= CYGINT_ISO_MALLOC
+ # option CYGFUN_LIBC_STRING_STRDUP
+ # ActiveIf: CYGINT_ISO_MALLOC
+};
+
+# Malloc implementation header
+#
+cdl_option CYGBLD_ISO_MALLOC_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Mallinfo() implementations
+#
+cdl_interface CYGINT_ISO_MALLINFO {
+ # Implemented by CYGPKG_MEMALLOC_MALLOC_ALLOCATORS, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_MALLINFO
+ # CYGINT_ISO_MALLINFO == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_MALLINFO
+ # Requires: 1 >= CYGINT_ISO_MALLINFO
+};
+
+# Mallinfo() implementation header
+#
+cdl_option CYGBLD_ISO_MALLINFO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Program exit functionality implementations
+#
+cdl_interface CYGINT_ISO_EXIT {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_EXIT
+ # CYGINT_ISO_EXIT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_EXIT
+ # Requires: 1 >= CYGINT_ISO_EXIT
+ # option CYGFUN_INFRA_DUMMY_ABORT
+ # Requires: !CYGINT_ISO_EXIT
+ # option CYGFUN_INFRA_DUMMY_ABORT
+ # DefaultValue: CYGINT_ISO_EXIT == 0
+};
+
+# Program exit functionality implementation header
+#
+cdl_option CYGBLD_ISO_EXIT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Program environment implementations
+#
+cdl_interface CYGINT_ISO_STDLIB_ENVIRON {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_ENVIRON
+ # CYGINT_ISO_STDLIB_ENVIRON == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDLIB_ENVIRON
+ # Requires: 1 >= CYGINT_ISO_STDLIB_ENVIRON
+};
+
+# Program environment implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_ENVIRON_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# system() implementations
+#
+cdl_interface CYGINT_ISO_STDLIB_SYSTEM {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_SYSTEM
+ # CYGINT_ISO_STDLIB_SYSTEM == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDLIB_SYSTEM
+ # Requires: 1 >= CYGINT_ISO_STDLIB_SYSTEM
+};
+
+# system() implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_SYSTEM_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# bsearch() implementations
+#
+cdl_interface CYGINT_ISO_BSEARCH {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_BSEARCH
+ # CYGINT_ISO_BSEARCH == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_BSEARCH
+ # Requires: 1 >= CYGINT_ISO_BSEARCH
+};
+
+# bsearch() implementation header
+#
+cdl_option CYGBLD_ISO_BSEARCH_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# qsort() implementations
+#
+cdl_interface CYGINT_ISO_QSORT {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_QSORT
+ # CYGINT_ISO_STDLIB_QSORT (unknown) == 0
+ # --> 1
+
+ # The following properties are affected by this value
+};
+
+# qsort() implementation header
+#
+cdl_option CYGBLD_ISO_QSORT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# abs()/labs() implementations
+#
+cdl_interface CYGINT_ISO_ABS {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_ABS
+ # CYGINT_ISO_STDLIB_ABS (unknown) == 0
+ # --> 1
+
+ # The following properties are affected by this value
+};
+
+# abs()/labs() implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_ABS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/stdlib/abs.inl>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGIMP_LIBC_STDLIB_INLINE_ABS
+ # Requires: CYGBLD_ISO_STDLIB_ABS_HEADER == "<cyg/libc/stdlib/abs.inl>"
+};
+
+# div()/ldiv() implementations
+#
+cdl_interface CYGINT_ISO_DIV {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_DIV
+ # CYGINT_ISO_STDLIB_DIV (unknown) == 0
+ # --> 1
+
+ # The following properties are affected by this value
+};
+
+# div()/ldiv() implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_DIV_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/stdlib/div.inl>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGIMP_LIBC_STDLIB_INLINE_DIV
+ # Requires: CYGBLD_ISO_STDLIB_DIV_HEADER == "<cyg/libc/stdlib/div.inl>"
+};
+
+# Header defining the implementation's MB_CUR_MAX
+#
+cdl_option CYGBLD_ISO_STDLIB_MB_CUR_MAX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # interface CYGINT_LIBC_I18N_MB_REQUIRED
+ # Requires: CYGBLD_ISO_STDLIB_MB_CUR_MAX_HEADER == "<cyg/libc/i18n/mb.h>"
+};
+
+# Multibyte character implementations
+#
+cdl_interface CYGINT_ISO_STDLIB_MULTIBYTE {
+ # Implemented by CYGPKG_LIBC_I18N, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_MULTIBYTE
+ # CYGINT_ISO_STDLIB_MULTIBYTE == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDLIB_MULTIBYTE
+ # Requires: 1 >= CYGINT_ISO_STDLIB_MULTIBYTE
+};
+
+# Multibyte character implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_MULTIBYTE_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# String functions
+#
+cdl_component CYGPKG_ISO_STRING {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of strerror() function
+#
+cdl_interface CYGINT_ISO_STRERROR {
+ # Implemented by CYGPKG_ERROR_STRERROR, active, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 1
+ # Requires: 1 >= CYGINT_ISO_STRERROR
+ # CYGINT_ISO_STRERROR == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRERROR
+ # Requires: 1 >= CYGINT_ISO_STRERROR
+};
+
+# strerror() implementation header
+#
+cdl_option CYGBLD_ISO_STRERROR_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/error/strerror.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGPKG_ERROR_STRERROR
+ # Requires: CYGBLD_ISO_STRERROR_HEADER == "<cyg/error/strerror.h>"
+};
+
+# memcpy() implementation header
+#
+cdl_option CYGBLD_ISO_MEMCPY_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# memset() implementation header
+#
+cdl_option CYGBLD_ISO_MEMSET_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of strtok_r() function
+#
+cdl_interface CYGINT_ISO_STRTOK_R {
+ # Implemented by CYGPKG_LIBC_STRING, active, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 1
+ # Requires: 1 >= CYGINT_ISO_STRTOK_R
+ # CYGINT_ISO_STRTOK_R == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRTOK_R
+ # Requires: 1 >= CYGINT_ISO_STRTOK_R
+};
+
+# strtok_r() implementation header
+#
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/string/string.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # package CYGPKG_LIBC_STRING
+ # Requires: CYGBLD_ISO_STRTOK_R_HEADER == "<cyg/libc/string/string.h>"
+};
+
+# Number of implementations of locale-specific string functions
+# This covers locale-dependent string functions such as strcoll()
+# and strxfrm().
+#
+cdl_interface CYGINT_ISO_STRING_LOCALE_FUNCS {
+ # Implemented by CYGPKG_LIBC_STRING, active, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 1
+ # Requires: 1 >= CYGINT_ISO_STRING_LOCALE_FUNCS
+ # CYGINT_ISO_STRING_LOCALE_FUNCS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRING_LOCALE_FUNCS
+ # Requires: 1 >= CYGINT_ISO_STRING_LOCALE_FUNCS
+};
+
+# Locale-specific string functions' implementation header
+# This covers locale-dependent string functions such as strcoll()
+# and strxfrm().
+#
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/string/string.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # package CYGPKG_LIBC_STRING
+ # Requires: CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER == "<cyg/libc/string/string.h>"
+};
+
+# Number of implementations of BSD string functions
+#
+cdl_interface CYGINT_ISO_STRING_BSD_FUNCS {
+ # Implemented by CYGFUN_LIBC_STRING_BSD_FUNCS, active, disabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STRING_BSD_FUNCS
+ # CYGINT_ISO_STRING_BSD_FUNCS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRING_BSD_FUNCS
+ # Requires: 1 >= CYGINT_ISO_STRING_BSD_FUNCS
+};
+
+# BSD string functions' implementation header
+#
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGFUN_LIBC_STRING_BSD_FUNCS
+ # Requires: CYGBLD_ISO_STRING_BSD_FUNCS_HEADER == "<cyg/libc/string/bsdstring.h>"
+};
+
+# Number of implementations of other mem*() functions
+#
+cdl_interface CYGINT_ISO_STRING_MEMFUNCS {
+ # Implemented by CYGPKG_LIBC_STRING, active, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 1
+ # Requires: 1 >= CYGINT_ISO_STRING_MEMFUNCS
+ # CYGINT_ISO_STRING_MEMFUNCS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRING_MEMFUNCS
+ # Requires: 1 >= CYGINT_ISO_STRING_MEMFUNCS
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGINT_ISO_STRING_MEMFUNCS
+ # component CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
+ # Requires: CYGINT_ISO_STRING_MEMFUNCS
+};
+
+# Other mem*() functions' implementation header
+#
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/string/string.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # package CYGPKG_LIBC_STRING
+ # Requires: CYGBLD_ISO_STRING_MEMFUNCS_HEADER == "<cyg/libc/string/string.h>"
+};
+
+# Number of implementations of other ISO C str*() functions
+# This covers the other str*() functions defined by ISO C.
+#
+cdl_interface CYGINT_ISO_STRING_STRFUNCS {
+ # Implemented by CYGPKG_LIBC_STRING, active, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 1
+ # Requires: 1 >= CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRING_STRFUNCS
+ # Requires: 1 >= CYGINT_ISO_STRING_STRFUNCS
+ # option CYGFUN_INFRA_DUMMY_STRLEN
+ # Requires: !CYGINT_ISO_STRING_STRFUNCS
+ # option CYGFUN_INFRA_DUMMY_STRLEN
+ # DefaultValue: CYGINT_ISO_STRING_STRFUNCS == 0
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # component CYGPKG_IO_ETH_DRIVERS_NET
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # option CYGFUN_COMPRESS_ZLIB_GZIO
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # package CYGPKG_IO_FLASH
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # package CYGPKG_LIBC_STDLIB
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+};
+
+# Other ISO C str*() functions' implementation header
+# This covers the other str*() functions defined by ISO C.
+#
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/string/string.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # package CYGPKG_LIBC_STRING
+ # Requires: CYGBLD_ISO_STRING_STRFUNCS_HEADER == "<cyg/libc/string/string.h>"
+};
+
+# <
+# Clock and time functionality
+#
+cdl_component CYGPKG_ISO_TIME {
+ # There is no associated value.
+};
+
+# >
+# time_t implementation header
+#
+cdl_option CYGBLD_ISO_TIME_T_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# clock_t implementation header
+#
+cdl_option CYGBLD_ISO_CLOCK_T_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# struct timeval implementation header
+#
+cdl_option CYGBLD_ISO_STRUCTTIMEVAL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# fnmatch implementation header
+#
+cdl_option CYGBLD_ISO_FNMATCH_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of POSIX timer types
+#
+cdl_interface CYGINT_ISO_POSIX_TIMER_TYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMER_TYPES
+ # CYGINT_ISO_POSIX_TIMER_TYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_TIMER_TYPES
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMER_TYPES
+};
+
+# POSIX timer types implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_TIMER_TYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of POSIX clock types
+#
+cdl_interface CYGINT_ISO_POSIX_CLOCK_TYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_CLOCK_TYPES
+ # CYGINT_ISO_POSIX_CLOCK_TYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_CLOCK_TYPES
+ # Requires: 1 >= CYGINT_ISO_POSIX_CLOCK_TYPES
+};
+
+# POSIX clock types implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_CLOCK_TYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of ISO C types
+#
+cdl_interface CYGINT_ISO_C_TIME_TYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_C_TIME_TYPES
+ # CYGINT_ISO_C_TIME_TYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_C_TIME_TYPES
+ # Requires: 1 >= CYGINT_ISO_C_TIME_TYPES
+};
+
+# ISO C time types implementation header
+#
+cdl_option CYGBLD_ISO_C_TIME_TYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of POSIX timers
+#
+cdl_interface CYGINT_ISO_POSIX_TIMERS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMERS
+ # CYGINT_ISO_POSIX_TIMERS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_TIMERS
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMERS
+};
+
+# POSIX timer implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_TIMERS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of POSIX clocks
+#
+cdl_interface CYGINT_ISO_POSIX_CLOCKS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_CLOCKS
+ # CYGINT_ISO_POSIX_CLOCKS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_CLOCKS
+ # Requires: 1 >= CYGINT_ISO_POSIX_CLOCKS
+};
+
+# POSIX clocks implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_CLOCKS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of ISO C clock functions
+#
+cdl_interface CYGINT_ISO_C_CLOCK_FUNCS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_C_CLOCK_FUNCS
+ # CYGINT_ISO_C_CLOCK_FUNCS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_C_CLOCK_FUNCS
+ # Requires: 1 >= CYGINT_ISO_C_CLOCK_FUNCS
+};
+
+# ISO C clock functions' implementation header
+#
+cdl_option CYGBLD_ISO_C_CLOCK_FUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of tzset() function
+#
+cdl_interface CYGINT_ISO_TZSET {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_TZSET
+ # CYGINT_ISO_TZSET == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_TZSET
+ # Requires: 1 >= CYGINT_ISO_TZSET
+};
+
+# tzset() implementation header
+#
+cdl_option CYGBLD_ISO_TZSET_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Signal functionality
+#
+cdl_component CYGPKG_ISO_SIGNAL {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of signal numbers
+#
+cdl_interface CYGINT_ISO_SIGNAL_NUMBERS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SIGNAL_NUMBERS
+ # CYGINT_ISO_SIGNAL_NUMBERS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SIGNAL_NUMBERS
+ # Requires: 1 >= CYGINT_ISO_SIGNAL_NUMBERS
+};
+
+# Signal numbering implementation header
+# This header provides the mapping of signal
+# names (e.g. SIGBUS) to numbers.
+#
+cdl_option CYGBLD_ISO_SIGNAL_NUMBERS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of signal implementations
+#
+cdl_interface CYGINT_ISO_SIGNAL_IMPL {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SIGNAL_IMPL
+ # CYGINT_ISO_SIGNAL_IMPL == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SIGNAL_IMPL
+ # Requires: 1 >= CYGINT_ISO_SIGNAL_IMPL
+};
+
+# Signals implementation header
+#
+cdl_option CYGBLD_ISO_SIGNAL_IMPL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX real time signals feature test macro
+# This defines the POSIX feature test macro
+# that indicates that the POSIX real time signals
+# are present.
+#
+cdl_interface CYGINT_POSIX_REALTIME_SIGNALS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_POSIX_REALTIME_SIGNALS
+ # CYGINT_POSIX_REALTIME_SIGNALS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_POSIX_REALTIME_SIGNALS
+ # Requires: 1 >= CYGINT_POSIX_REALTIME_SIGNALS
+};
+
+# <
+# Non-local jumps functionality
+#
+cdl_component CYGPKG_ISO_SETJMP {
+ # There is no associated value.
+};
+
+# >
+# setjmp() / longjmp() implementations
+#
+cdl_interface CYGINT_ISO_SETJMP {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SETJMP
+ # CYGINT_ISO_SETJMP == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SETJMP
+ # Requires: 1 >= CYGINT_ISO_SETJMP
+};
+
+# setjmp() / longjmp() implementation header
+#
+cdl_option CYGBLD_ISO_SETJMP_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# sigsetjmp() / siglongjmp() implementations
+#
+cdl_interface CYGINT_ISO_SIGSETJMP {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SIGSETJMP
+ # CYGINT_ISO_SIGSETJMP == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SIGSETJMP
+ # Requires: 1 >= CYGINT_ISO_SIGSETJMP
+};
+
+# sigsetjmp() / siglongjmp() implementation header
+#
+cdl_option CYGBLD_ISO_SIGSETJMP_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Assertions implementation header
+#
+cdl_option CYGBLD_ISO_ASSERT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX file control
+# This covers the POSIX file control definitions,
+# normally found in <fcntl.h>
+#
+cdl_component CYGPKG_ISO_POSIX_FCNTL {
+ # There is no associated value.
+};
+
+# >
+# POSIX open flags implementation header
+#
+cdl_option CYGBLD_ISO_OFLAG_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX fcntl() implementations
+#
+cdl_interface CYGINT_ISO_FCNTL {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_FCNTL
+ # CYGINT_ISO_FCNTL == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_FCNTL
+ # Requires: 1 >= CYGINT_ISO_FCNTL
+};
+
+# POSIX fcntl() implementation header
+#
+cdl_option CYGBLD_ISO_FCNTL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX file open implementations
+#
+cdl_interface CYGINT_ISO_OPEN {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_OPEN
+ # CYGINT_ISO_OPEN == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_OPEN
+ # Requires: 1 >= CYGINT_ISO_OPEN
+};
+
+# POSIX file open implementation header
+#
+cdl_option CYGBLD_ISO_OPEN_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# <sys/stat.h> definitions implementation header
+#
+cdl_option CYGBLD_ISO_STAT_DEFS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX directory reading implementation
+#
+cdl_interface CYGINT_ISO_DIRENT {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_DIRENT
+ # CYGINT_ISO_DIRENT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_DIRENT
+ # Requires: 1 >= CYGINT_ISO_DIRENT
+};
+
+# <dirent.h> definitions implementation header
+#
+cdl_option CYGBLD_ISO_DIRENT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX <sys/types.h> contents
+# This covers the types required by POSIX to be in
+# <sys/types.h>
+#
+cdl_component CYGPKG_ISO_POSIX_TYPES {
+ # There is no associated value.
+};
+
+# >
+# POSIX thread types implementations
+#
+cdl_interface CYGINT_ISO_PTHREADTYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_PTHREADTYPES
+ # CYGINT_ISO_PTHREADTYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_PTHREADTYPES
+ # Requires: 1 >= CYGINT_ISO_PTHREADTYPES
+ # interface CYGINT_ISO_PMUTEXTYPES
+ # Requires: 1 >= CYGINT_ISO_PTHREADTYPES
+};
+
+# POSIX thread types implementation header
+#
+cdl_option CYGBLD_ISO_PTHREADTYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX mutex types implementations
+#
+cdl_interface CYGINT_ISO_PMUTEXTYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_PTHREADTYPES
+ # CYGINT_ISO_PTHREADTYPES == 0
+ # --> 1
+};
+
+# POSIX mutex types implementation header
+#
+cdl_option CYGBLD_ISO_PMUTEXTYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# ssize_t implementation header
+#
+cdl_option CYGBLD_ISO_SSIZE_T_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Filesystem types implementation header
+#
+cdl_option CYGBLD_ISO_FSTYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# gid_t, pid_t, uid_t implementation header
+#
+cdl_option CYGBLD_ISO_SCHEDTYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Non-POSIX <sys/types.h> contents
+# This covers the extra types required by non-POSIX
+# packages to be in <sys/types.h>. These would normally
+# only be visible if _POSIX_SOURCE is not defined.
+#
+cdl_component CYGPKG_ISO_EXTRA_TYPES {
+ # There is no associated value.
+};
+
+# >
+# BSD compatible types
+#
+cdl_interface CYGINT_ISO_BSDTYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_BSDTYPES
+ # CYGINT_ISO_BSDTYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_BSDTYPES
+ # Requires: 1 >= CYGINT_ISO_BSDTYPES
+};
+
+# BSD types header
+#
+cdl_option CYGBLD_ISO_BSDTYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Utsname structure
+#
+cdl_component CYGPKG_ISO_UTSNAME {
+ # There is no associated value.
+};
+
+# >
+# Utsname header
+#
+cdl_option CYGBLD_ISO_UTSNAME_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# POSIX scheduler
+#
+cdl_component CYGPKG_ISO_SCHED {
+ # There is no associated value.
+};
+
+# >
+# POSIX scheduler implementations
+#
+cdl_interface CYGINT_ISO_SCHED_IMPL {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SCHED_IMPL
+ # CYGINT_ISO_SCHED_IMPL == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SCHED_IMPL
+ # Requires: 1 >= CYGINT_ISO_SCHED_IMPL
+};
+
+# POSIX scheduler implementation header
+#
+cdl_option CYGBLD_ISO_SCHED_IMPL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# POSIX semaphores
+#
+cdl_component CYGPKG_ISO_SEMAPHORES {
+ # There is no associated value.
+};
+
+# >
+# POSIX semaphore implementations
+#
+cdl_interface CYGINT_ISO_SEMAPHORES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SEMAPHORES
+ # CYGINT_ISO_SEMAPHORES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SEMAPHORES
+ # Requires: 1 >= CYGINT_ISO_SEMAPHORES
+};
+
+# POSIX semaphore implementation header
+#
+cdl_option CYGBLD_ISO_SEMAPHORES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# POSIX message queues
+#
+cdl_component CYGPKG_ISO_MQUEUE {
+ # There is no associated value.
+};
+
+# >
+# Implementations
+#
+cdl_interface CYGINT_ISO_MQUEUE {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_MQUEUE
+ # CYGINT_ISO_MQUEUE == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_MQUEUE
+ # Requires: 1 >= CYGINT_ISO_MQUEUE
+ # option CYGNUM_ISO_MQUEUE_OPEN_MAX
+ # ActiveIf: CYGINT_ISO_MQUEUE
+ # option CYGNUM_ISO_MQUEUE_PRIO_MAX
+ # ActiveIf: CYGINT_ISO_MQUEUE
+};
+
+# Implementation header
+#
+cdl_option CYGBLD_ISO_MQUEUE_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Maximum number of open message queues
+#
+cdl_option CYGNUM_ISO_MQUEUE_OPEN_MAX {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_ISO_MQUEUE
+ # CYGINT_ISO_MQUEUE == 0
+ # --> 0
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYGNUM_POSIX_MQUEUE_OPEN_MAX > 0 ? CYGNUM_POSIX_MQUEUE_OPEN_MAX : 0
+ # CYGNUM_POSIX_MQUEUE_OPEN_MAX (unknown) == 0
+ # CYGNUM_POSIX_MQUEUE_OPEN_MAX (unknown) == 0
+ # --> 0 0
+};
+
+# Maximum number of message priorities
+#
+cdl_option CYGNUM_ISO_MQUEUE_PRIO_MAX {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_ISO_MQUEUE
+ # CYGINT_ISO_MQUEUE == 0
+ # --> 0
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 1 65535
+ # value_source default
+ # Default value: 1 65535
+};
+
+# <
+# POSIX threads
+#
+cdl_component CYGPKG_ISO_PTHREAD {
+ # There is no associated value.
+};
+
+# >
+# POSIX pthread implementations
+#
+cdl_interface CYGINT_ISO_PTHREAD_IMPL {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_PTHREAD_IMPL
+ # CYGINT_ISO_PTHREAD_IMPL == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_PTHREAD_IMPL
+ # Requires: 1 >= CYGINT_ISO_PTHREAD_IMPL
+};
+
+# POSIX pthread implementation header
+#
+cdl_option CYGBLD_ISO_PTHREAD_IMPL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX mutex/cond var implementations
+#
+cdl_interface CYGINT_ISO_PTHREAD_MUTEX {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_PTHREAD_MUTEX
+ # CYGINT_ISO_PTHREAD_MUTEX == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_PTHREAD_MUTEX
+ # Requires: 1 >= CYGINT_ISO_PTHREAD_MUTEX
+};
+
+# POSIX mutex/cond var implementation header
+#
+cdl_option CYGBLD_ISO_PTHREAD_MUTEX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Limits
+#
+cdl_component CYGPKG_ISO_LIMITS {
+ # There is no associated value.
+};
+
+# >
+# POSIX pthread limits implementations
+#
+cdl_interface CYGINT_ISO_POSIX_LIMITS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_LIMITS
+ # CYGINT_ISO_POSIX_LIMITS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_LIMITS
+ # Requires: 1 >= CYGINT_ISO_POSIX_LIMITS
+};
+
+# POSIX pthread limits implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_LIMITS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# OPEN_MAX implementation header
+#
+cdl_option CYGBLD_ISO_OPEN_MAX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# LINK_MAX implementation header
+#
+cdl_option CYGBLD_ISO_LINK_MAX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# NAME_MAX implementation header
+#
+cdl_option CYGBLD_ISO_NAME_MAX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# PATH_MAX implementation header
+#
+cdl_option CYGBLD_ISO_PATH_MAX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# POSIX termios
+#
+cdl_component CYGPKG_ISO_TERMIOS {
+ # There is no associated value.
+};
+
+# >
+# POSIX termios implementations
+#
+cdl_interface CYGINT_ISO_TERMIOS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_TERMIOS
+ # CYGINT_ISO_TERMIOS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_TERMIOS
+ # Requires: 1 >= CYGINT_ISO_TERMIOS
+};
+
+# POSIX termios implementation header
+#
+cdl_option CYGBLD_ISO_TERMIOS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Dynamic load API
+#
+cdl_component CYGPKG_ISO_DLFCN {
+ # There is no associated value.
+};
+
+# >
+# Dynamic load implementations
+#
+cdl_interface CYGINT_ISO_DLFCN {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_DLFCN
+ # CYGINT_ISO_DLFCN == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_DLFCN
+ # Requires: 1 >= CYGINT_ISO_DLFCN
+};
+
+# Dynamic load implementation header
+#
+cdl_option CYGBLD_ISO_DLFCN_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# UNIX standard functions
+#
+cdl_component CYGPKG_ISO_UNISTD {
+ # There is no associated value.
+};
+
+# >
+# POSIX timer operations implementations
+#
+cdl_interface CYGINT_ISO_POSIX_TIMER_OPS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMER_OPS
+ # CYGINT_ISO_POSIX_TIMER_OPS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_TIMER_OPS
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMER_OPS
+};
+
+# POSIX timer operations implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_TIMER_OPS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX sleep() implementations
+#
+cdl_interface CYGINT_ISO_POSIX_SLEEP {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_SLEEP
+ # CYGINT_ISO_POSIX_SLEEP == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_SLEEP
+ # Requires: 1 >= CYGINT_ISO_POSIX_SLEEP
+};
+
+# POSIX sleep() implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_SLEEP_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# select()/poll() functions
+#
+cdl_component CYGPKG_ISO_SELECT {
+ # There is no associated value.
+};
+
+# >
+# select() implementations
+#
+cdl_interface CYGINT_ISO_SELECT {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_SELECT
+ # CYGINT_ISO_SELECT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SELECT
+ # Requires: 1 >= CYGINT_ISO_SELECT
+};
+
+# select() implementation header
+#
+cdl_option CYGBLD_ISO_SELECT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# poll() implementations
+#
+cdl_interface CYGINT_ISO_POLL {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POLL
+ # CYGINT_ISO_POLL == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POLL
+ # Requires: 1 >= CYGINT_ISO_POLL
+};
+
+# poll() implementation header
+#
+cdl_option CYGBLD_ISO_POLL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# NetDB utility functions
+#
+cdl_component CYGPKG_ISO_NETDB {
+ # There is no associated value.
+};
+
+# >
+# DNS implementations
+#
+cdl_interface CYGINT_ISO_DNS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: bool
+ # Current value: 0
+ # Requires: 1 >= CYGINT_ISO_DNS
+ # CYGINT_ISO_DNS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_DNS
+ # Requires: 1 >= CYGINT_ISO_DNS
+};
+
+# DNS implementation header
+#
+cdl_option CYGBLD_ISO_DNS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Protocol network database implementations
+#
+cdl_interface CYGINT_ISO_NETDB_PROTO {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: bool
+ # Current value: 0
+ # Requires: 1 >= CYGINT_ISO_NETDB_PROTO
+ # CYGINT_ISO_NETDB_PROTO == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_NETDB_PROTO
+ # Requires: 1 >= CYGINT_ISO_NETDB_PROTO
+};
+
+# Protocol network database implementation header
+#
+cdl_option CYGBLD_ISO_NETDB_PROTO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Services network database implementations
+#
+cdl_interface CYGINT_ISO_NETDB_SERV {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: bool
+ # Current value: 0
+ # Requires: 1 >= CYGINT_ISO_NETDB_SERV
+ # CYGINT_ISO_NETDB_SERV == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_NETDB_SERV
+ # Requires: 1 >= CYGINT_ISO_NETDB_SERV
+};
+
+# Services network database implementation header
+#
+cdl_option CYGBLD_ISO_NETDB_SERV_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_ISOINFRA_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the ISO C and POSIX infrastructure package.
+# These flags are used in addition to the set of global flags.
+#
+cdl_option CYGPKG_ISOINFRA_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the ISO C and POSIX infrastructure package.
+# These flags are removed from the set of global flags
+# if present.
+#
+cdl_option CYGPKG_ISOINFRA_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# <
+# <
+# Compute CRCs
+# doc: ref/services-crc.html
+# This package provides support for CRC calculation. Currently
+# this is the POSIX 1003 defined CRC algorithm, a 32 CRC by
+# Gary S. Brown, and a 16 bit CRC.
+#
+cdl_package CYGPKG_CRC {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # package CYGPKG_COMPRESS_ZLIB
+ # Requires: CYGPKG_CRC
+};
+
+# >
+# POSIX CRC tests
+#
+cdl_option CYGPKG_CRC_TESTS {
+ # Calculated value: "tests/crc_test"
+ # Flavor: data
+ # Current_value: tests/crc_test
+};
+
+# <
+# Zlib compress and decompress package
+# This package provides support for compression and
+# decompression.
+#
+cdl_package CYGPKG_COMPRESS_ZLIB {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+ # Requires: CYGPKG_CRC
+ # CYGPKG_CRC == current
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGBLD_BUILD_REDBOOT_WITH_ZLIB
+ # ActiveIf: CYGPKG_COMPRESS_ZLIB
+};
+
+# >
+# Override memory allocation routines.
+#
+cdl_interface CYGINT_COMPRESS_ZLIB_LOCAL_ALLOC {
+ # Implemented by CYGBLD_BUILD_REDBOOT_WITH_ZLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_COMPRESS_ZLIB_NEEDS_MALLOC
+ # ActiveIf: CYGINT_COMPRESS_ZLIB_LOCAL_ALLOC == 0
+};
+
+# Should deflate() produce 'gzip' compatible output?
+# If this option is set then the output of calling deflate()
+# will be wrapped up as a 'gzip' compatible file.
+#
+cdl_option CYGSEM_COMPRESS_ZLIB_DEFLATE_MAKES_GZIP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Does this library need malloc?
+# This pseudo-option will force the memalloc library to be
+# required iff the application does not provide it's own
+# infrastructure.
+#
+cdl_option CYGSEM_COMPRESS_ZLIB_NEEDS_MALLOC {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_COMPRESS_ZLIB_LOCAL_ALLOC == 0
+ # CYGINT_COMPRESS_ZLIB_LOCAL_ALLOC == 1
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGPKG_MEMALLOC
+ # CYGPKG_MEMALLOC == current
+ # --> 1
+};
+
+# Include stdio-like utility functions
+# This option enables the stdio-like zlib utility functions
+# (gzread/gzwrite and friends) provided in gzio.c.
+#
+cdl_option CYGFUN_COMPRESS_ZLIB_GZIO {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGPKG_LIBC_STDIO_OPEN ? 1 : 0
+ # CYGPKG_LIBC_STDIO_OPEN (unknown) == 0
+ # --> 0
+ # Requires: CYGINT_ISO_STDIO_FILEPOS
+ # CYGINT_ISO_STDIO_FILEPOS == 0
+ # --> 0
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+ # Requires: CYGINT_ISO_STDIO_FORMATTED_IO
+ # CYGINT_ISO_STDIO_FORMATTED_IO == 0
+ # --> 0
+ # Requires: CYGINT_ISO_STDIO_FILEACCESS
+ # CYGINT_ISO_STDIO_FILEACCESS == 0
+ # --> 0
+};
+
+# Zlib compress and decompress package build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_COMPRESS_ZLIB_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_COMPRESS_ZLIB_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-D__ECOS__ -DNO_ERRNO_H"
+ # value_source default
+ # Default value: "-D__ECOS__ -DNO_ERRNO_H"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_COMPRESS_ZLIB_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wstrict-prototypes
+ # value_source default
+ # Default value: -Wstrict-prototypes
+};
+
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_COMPRESS_ZLIB_LDFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_COMPRESS_ZLIB_LDFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# <
+# zlib tests
+#
+cdl_option CYGPKG_COMPRESS_ZLIB_TESTS {
+ # Calculated value: "tests/zlib1.c tests/zlib2.c"
+ # Flavor: data
+ # Current_value: tests/zlib1.c tests/zlib2.c
+};
+
+# <
+# FLASH device drivers
+# doc: ref/flash.html
+# This option enables drivers for basic I/O services on
+# flash devices.
+#
+cdl_package CYGPKG_IO_FLASH {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGSEM_REDBOOT_FLASH_CONFIG
+ # DefaultValue: CYGPKG_IO_FLASH != 0
+ # package CYGPKG_DEVS_FLASH_ONMXC
+ # ActiveIf: CYGPKG_IO_FLASH
+};
+
+# >
+# Hardware FLASH device drivers
+# This option enables the hardware device drivers
+# for the current platform.
+#
+cdl_interface CYGHWR_IO_FLASH_DEVICE {
+ # Implemented by CYGPKG_DEVS_FLASH_ONMXC, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # component CYGPKG_REDBOOT_FLASH
+ # ActiveIf: CYGHWR_IO_FLASH_DEVICE
+};
+
+# Hardware FLASH device drivers are not in RAM
+# Use of this interface is deprecated.
+# Drivers should make sure that the functions are
+# linked to RAM by putting them in .2ram sections.
+#
+cdl_interface CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: !CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM
+ # CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM
+ # Requires: !CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM
+};
+
+# Hardware can support block locking
+# This option will be enabled by devices which can support
+# locking (write-protection) of individual blocks.
+#
+cdl_interface CYGHWR_IO_FLASH_BLOCK_LOCKING {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_FLASH_LOCK_SPECIAL
+ # ActiveIf: CYGHWR_IO_FLASH_BLOCK_LOCKING != 0
+};
+
+# Hardware cannot support direct access to FLASH memory
+# This option will be asserted by devices which cannot support
+# direct access to the FLASH memory contents (e.g. EEPROM or NAND
+# devices). In these cases, the driver must provide an appropriate
+# hardware access function.
+#
+cdl_option CYGSEM_IO_FLASH_READ_INDIRECT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+ # Requires: !CYGSEM_IO_FLASH_VERIFY_PROGRAM
+ # CYGSEM_IO_FLASH_VERIFY_PROGRAM == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGPRI_REDBOOT_ZLIB_FLASH
+ # ActiveIf: (!CYGSEM_IO_FLASH_READ_INDIRECT) || CYGPRI_REDBOOT_ZLIB_FLASH_FORCE
+ # component CYGHWR_DEVS_FLASH_MMC
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # option CYGHWR_DEVS_FLASH_MMC_ESDHC
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # option CYGHWR_DEVS_FLASH_MMC_SD
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # option CYGHWR_DEVS_FLASH_MXC_NAND
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+};
+
+# Display status messages during flash operations
+# Selecting this option will cause the drivers to print status
+# messages as various flash operations are undertaken.
+#
+cdl_option CYGSEM_IO_FLASH_CHATTER {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Verify data programmed to flash
+# Selecting this option will cause verification of data
+# programmed to flash.
+#
+cdl_option CYGSEM_IO_FLASH_VERIFY_PROGRAM {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_IO_FLASH_READ_INDIRECT
+ # Requires: !CYGSEM_IO_FLASH_VERIFY_PROGRAM
+};
+
+# Platform has flash soft DIP switch write-protect
+# Selecting this option will cause the state of a hardware jumper or
+# dipswitch to be read by software to determine whether the flash is
+# write-protected or not.
+#
+cdl_option CYGSEM_IO_FLASH_SOFT_WRITE_PROTECT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Instantiate in I/O block device API
+# Provides a block device accessible using the standard I/O
+# API ( cyg_io_read() etc. )
+#
+cdl_component CYGPKG_IO_FLASH_BLOCK_DEVICE {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_IO
+ # CYGPKG_IO (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# >
+# Name of flash device 1 block device
+#
+cdl_component CYGDAT_IO_FLASH_BLOCK_DEVICE_NAME_1 {
+ # This option is not active
+ # The parent CYGPKG_IO_FLASH_BLOCK_DEVICE is not active
+ # The parent CYGPKG_IO_FLASH_BLOCK_DEVICE is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "\"/dev/flash1\""
+ # value_source default
+ # Default value: "\"/dev/flash1\""
+};
+
+# >
+#
+cdl_interface CYGINT_IO_FLASH_BLOCK_CFG_1 {
+ # Implemented by CYGNUM_IO_FLASH_BLOCK_CFG_STATIC_1, inactive, enabled
+ # Implemented by CYGNUM_IO_FLASH_BLOCK_CFG_FIS_1, inactive, disabled
+ # This option is not active
+ # The parent CYGDAT_IO_FLASH_BLOCK_DEVICE_NAME_1 is not active
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 == CYGINT_IO_FLASH_BLOCK_CFG_1
+ # CYGINT_IO_FLASH_BLOCK_CFG_1 == 0
+ # --> 0
+
+ # The following properties are affected by this value
+ # interface CYGINT_IO_FLASH_BLOCK_CFG_1
+ # Requires: 1 == CYGINT_IO_FLASH_BLOCK_CFG_1
+};
+
+# Static configuration
+# This configures the flash device 1 block device
+# with static base and length
+#
+cdl_component CYGNUM_IO_FLASH_BLOCK_CFG_STATIC_1 {
+ # This option is not active
+ # The parent CYGDAT_IO_FLASH_BLOCK_DEVICE_NAME_1 is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Start offset from flash base
+# This gives the offset from the base of flash which this
+# block device corresponds to.
+#
+cdl_option CYGNUM_IO_FLASH_BLOCK_OFFSET_1 {
+ # This option is not active
+ # The parent CYGNUM_IO_FLASH_BLOCK_CFG_STATIC_1 is not active
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00100000
+ # value_source default
+ # Default value: 0x00100000
+};
+
+# Length
+# This gives the length of the region of flash given over
+# to this block device.
+#
+cdl_option CYGNUM_IO_FLASH_BLOCK_LENGTH_1 {
+ # This option is not active
+ # The parent CYGNUM_IO_FLASH_BLOCK_CFG_STATIC_1 is not active
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00100000
+ # value_source default
+ # Default value: 0x00100000
+};
+
+# <
+# Configuration from FIS
+# This configures the flash device 1 block device
+# from Redboot FIS
+#
+cdl_component CYGNUM_IO_FLASH_BLOCK_CFG_FIS_1 {
+ # This option is not active
+ # The parent CYGDAT_IO_FLASH_BLOCK_DEVICE_NAME_1 is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# >
+# Name of FIS entry
+#
+cdl_component CYGDAT_IO_FLASH_BLOCK_FIS_NAME_1 {
+ # This option is not active
+ # The parent CYGNUM_IO_FLASH_BLOCK_CFG_FIS_1 is not active
+ # The parent CYGNUM_IO_FLASH_BLOCK_CFG_FIS_1 is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "\"jffs2\""
+ # value_source default
+ # Default value: "\"jffs2\""
+};
+
+# <
+# <
+# <
+# Flash device driver build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_IO_FLASH_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the flash device drivers. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_IO_FLASH_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the flash device drivers. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_IO_FLASH_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Flash device driver tests
+# This option specifies the set of tests for the flash device drivers.
+#
+cdl_component CYGPKG_IO_FLASH_TESTS {
+ # Calculated value: "tests/flash1"
+ # Flavor: data
+ # Current_value: tests/flash1
+};
+
+# >
+# Start offset from flash base
+# This gives the offset from the base of flash where tests
+# can be run. It is important to set this correctly, as an
+# incorrect value could allow the tests to write over critical
+# portions of the FLASH device and possibly render the target
+# board totally non-functional.
+#
+cdl_option CYGNUM_IO_FLASH_TEST_OFFSET {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00100000
+ # value_source default
+ # Default value: 0x00100000
+};
+
+# Length
+# This gives the length of the region of flash used for testing.
+#
+cdl_option CYGNUM_IO_FLASH_TEST_LENGTH {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00100000
+ # value_source default
+ # Default value: 0x00100000
+};
+
+# <
+# <
+# Support FLASH memory on Freescale MXC platforms
+#
+cdl_package CYGPKG_DEVS_FLASH_ONMXC {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # ActiveIf constraint: CYGPKG_IO_FLASH
+ # CYGPKG_IO_FLASH == current
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+};
+
+# >
+# MXC platform MMC card support
+# When this option is enabled, it indicates MMC card is
+# supported on the MXC platforms
+#
+cdl_component CYGHWR_DEVS_FLASH_MMC {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+};
+
+# >
+# MXC platform MMC card for newer SDHC controllers
+#
+cdl_option CYGHWR_DEVS_FLASH_MMC_ESDHC {
+ # This option is not active
+ # The parent CYGHWR_DEVS_FLASH_MMC is disabled
+ # ActiveIf constraint: CYGPKG_HAL_ARM_MX37_3STACK || CYGPKG_HAL_ARM_MX35_3STACK || CYGPKG_HAL_ARM_MX25_3STACK || CYGPKG_HAL_ARM_MX51
+ # CYGPKG_HAL_ARM_MX37_3STACK (unknown) == 0
+ # CYGPKG_HAL_ARM_MX35_3STACK (unknown) == 0
+ # CYGPKG_HAL_ARM_MX25_3STACK (unknown) == 0
+ # CYGPKG_HAL_ARM_MX51 (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # --> 1
+};
+
+# MXC platform MMC card for older MMC/SD controllers
+#
+cdl_option CYGHWR_DEVS_FLASH_MMC_SD {
+ # This option is not active
+ # The parent CYGHWR_DEVS_FLASH_MMC is disabled
+ # ActiveIf constraint: CYGPKG_HAL_ARM_MX31_3STACK || CYGPKG_HAL_ARM_MX31ADS
+ # CYGPKG_HAL_ARM_MX31_3STACK (unknown) == 0
+ # CYGPKG_HAL_ARM_MX31ADS (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # --> 1
+};
+
+# <
+# MXC platform NOR flash memory support
+# When this option is enabled, it indicates NOR flash is
+# supported on the MXC platforms
+#
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_DEVS_FLASH_IMX_SPI_NOR
+ # Requires: CYGHWR_DEVS_FLASH_MXC_NOR == 1
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+};
+
+# MXC platform NAND flash memory support
+# When this option is enabled, it indicates NAND flash is
+# supported on the MXC platforms
+#
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGPKG_DEVS_FLASH_NAND_BBT_IN_FLASH
+ # ActiveIf: CYGHWR_DEVS_FLASH_MXC_NAND
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+ # interface CYGHWR_DEVS_FLASH_MXC_NAND_RESET_WORKAROUND
+ # ActiveIf: CYGHWR_DEVS_FLASH_MXC_NAND
+};
+
+# i.MX platform SPI NOR flash memory support
+# When this option is enabled, it indicates SPI NOR flash is
+# supported on the i.MX platforms
+#
+cdl_option CYGHWR_DEVS_FLASH_IMX_SPI_NOR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGHWR_DEVS_FLASH_MXC_NOR == 1
+ # CYGHWR_DEVS_FLASH_MXC_NOR == 0
+ # --> 0
+};
+
+# MXC platform ATA support
+# When this option is enabled, it indicates ATA is
+# supported on the MXC platforms
+#
+cdl_option CYGHWR_DEVS_FLASH_MXC_ATA {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Use a flash based Bad Block Table
+#
+cdl_component CYGPKG_DEVS_FLASH_NAND_BBT_IN_FLASH {
+ # ActiveIf constraint: CYGHWR_DEVS_FLASH_MXC_NAND
+ # CYGHWR_DEVS_FLASH_MXC_NAND == 1
+ # --> 1
+
+ # There is no associated value.
+};
+
+# >
+# When this option is enabled, the driver will search for a flash
+# based bad block table
+#
+cdl_option CYGHWR_DEVS_FLASH_MXC_BBT_IN_FLASH {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# header file defining the NAND BBT descriptor
+# defines the name of the header file that describes the BBT layout
+#
+cdl_component CYGHWR_FLASH_NAND_BBT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/io/tx27_nand_bbt.h>
+ # value_source inferred
+ # Default value: 0 0
+};
+
+# Number of blocks to reserve for BBT
+# Number of blocks to reserve for BBT
+#
+cdl_option CYGNUM_FLASH_NAND_BBT_BLOCKS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 4
+ # value_source default
+ # Default value: 4
+};
+
+# <
+# MXC platform multi flash memory support
+# When this option is enabled, it indicates multi flashes are
+# supported on the MXC platforms (like NAND and NOR)
+#
+cdl_option CYGHWR_DEVS_FLASH_MXC_MULTI {
+ # This option is not active
+ # ActiveIf constraint: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+ # CYGHWR_DEVS_FLASH_MXC_NAND == 1
+ # CYGHWR_DEVS_FLASH_MXC_NOR == 0
+ # CYGHWR_DEVS_FLASH_MXC_NAND == 1
+ # CYGHWR_DEVS_FLASH_MMC == 0
+ # CYGHWR_DEVS_FLASH_MXC_NOR == 0
+ # CYGHWR_DEVS_FLASH_MMC == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+};
+
+# MXC platform NAND flash reset workaround support
+# When this option is enabled, it indicates 0xFFFF is used for
+# the NAND reset command instead of 0xFF.
+#
+cdl_interface CYGHWR_DEVS_FLASH_MXC_NAND_RESET_WORKAROUND {
+ # No options implement this inferface
+ # ActiveIf constraint: CYGHWR_DEVS_FLASH_MXC_NAND
+ # CYGHWR_DEVS_FLASH_MXC_NAND == 1
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+};
+
+# <
+# <
+# Dynamic memory allocation
+# doc: ref/memalloc.html
+# This package provides memory allocator infrastructure required for
+# dynamic memory allocators, including the ISO standard malloc
+# interface. It also contains some sample implementations.
+#
+cdl_package CYGPKG_MEMALLOC {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # option CYGSEM_COMPRESS_ZLIB_NEEDS_MALLOC
+ # Requires: CYGPKG_MEMALLOC
+};
+
+# >
+# Memory allocator implementations
+# This component contains configuration options related to the
+# various memory allocators available.
+#
+cdl_component CYGPKG_MEMALLOC_ALLOCATORS {
+ # There is no associated value.
+};
+
+# >
+# Fixed block allocator
+# This component contains configuration options related to the
+# fixed block memory allocator.
+#
+cdl_component CYGPKG_MEMALLOC_ALLOCATOR_FIXED {
+ # There is no associated value.
+};
+
+# >
+# Make thread safe
+# With this option enabled, this allocator will be
+# made thread-safe. Additionally allocation functions
+# are made available that allow a thread to wait
+# until memory is available.
+#
+cdl_option CYGSEM_MEMALLOC_ALLOCATOR_FIXED_THREADAWARE {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Simple variable block allocator
+# This component contains configuration options related to the
+# simple variable block memory allocator. This allocator is not
+# very fast, and in particular does not scale well with large
+# numbers of allocations. It is however very compact in terms of
+# code size and does not have very much overhead per allocation.
+#
+cdl_component CYGPKG_MEMALLOC_ALLOCATOR_VARIABLE {
+ # There is no associated value.
+};
+
+# >
+# Make thread safe
+# With this option enabled, this allocator will be
+# made thread-safe. Additionally allocation functions
+# are added that allow a thread to wait until memory
+# are made available that allow a thread to wait
+# until memory is available.
+#
+cdl_option CYGSEM_MEMALLOC_ALLOCATOR_VARIABLE_THREADAWARE {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Coalesce memory
+# The variable-block memory allocator can perform coalescing
+# of memory whenever the application code releases memory back
+# to the pool. This coalescing reduces the possibility of
+# memory fragmentation problems, but involves extra code and
+# processor cycles.
+#
+cdl_option CYGSEM_MEMALLOC_ALLOCATOR_VARIABLE_COALESCE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGIMP_MEMALLOC_MALLOC_VARIABLE_SIMPLE
+ # Requires: CYGSEM_MEMALLOC_ALLOCATOR_VARIABLE_COALESCE
+};
+
+# <
+# Doug Lea's malloc
+# This component contains configuration options related to the
+# port of Doug Lea's memory allocator, normally known as
+# dlmalloc. dlmalloc has a reputation for being both fast
+# and space-conserving, as well as resisting fragmentation well.
+# It is a common choice for a general purpose allocator and
+# has been used in both newlib and Linux glibc.
+#
+cdl_component CYGPKG_MEMALLOC_ALLOCATOR_DLMALLOC {
+ # There is no associated value.
+};
+
+# >
+# Debug build
+# Doug Lea's malloc implementation has substantial amounts
+# of internal checking in order to verify the operation
+# and consistency of the allocator. However this imposes
+# substantial overhead on each operation. Therefore this
+# checking may be individually disabled.
+#
+cdl_option CYGDBG_MEMALLOC_ALLOCATOR_DLMALLOC_DEBUG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0 != CYGDBG_USE_ASSERTS
+ # CYGDBG_USE_ASSERTS == 0
+ # --> 0
+ # Requires: CYGDBG_USE_ASSERTS
+ # CYGDBG_USE_ASSERTS == 0
+ # --> 0
+};
+
+# Make thread safe
+# With this option enabled, this allocator will be
+# made thread-safe. Additionally allocation functions
+# are made available that allow a thread to wait
+# until memory is available.
+#
+cdl_option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_THREADAWARE {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+};
+
+# Support more than one instance
+# Having this option disabled allows important
+# implementation structures to be declared as a single
+# static instance, allowing faster access. However this
+# would fail if there is more than one instance of
+# the dlmalloc allocator class. Therefore this option can
+# be enabled if multiple instances are required. Note: as
+# a special case, if this allocator is used as the
+# implementation of malloc, and it can be determined there
+# is more than one malloc pool, then this option will be
+# silently enabled.
+#
+cdl_option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_SAFE_MULTIPLE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Use system memmove() and memset()
+# This may be used to control whether memset() and memmove()
+# are used within the implementation. The alternative is
+# to use some macro equivalents, which some people report
+# are faster in some circumstances.
+#
+cdl_option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_USE_MEMCPY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 0 != CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+};
+
+# Minimum alignment of allocated blocks
+# This option controls the minimum alignment that the
+# allocated memory blocks are aligned on, specified as
+# 2^N. Note that using large mininum alignments can lead
+# to excessive memory wastage.
+#
+cdl_option CYGNUM_MEMALLOC_ALLOCATOR_DLMALLOC_ALIGNMENT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 3
+ # value_source default
+ # Default value: 3
+ # Legal values: 3 to 10
+};
+
+# <
+# Variable block allocator with separate metadata
+# This component contains configuration options related to the
+# variable block memory allocator with separate metadata.
+#
+cdl_component CYGPKG_MEMALLOC_ALLOCATOR_SEPMETA {
+ # There is no associated value.
+};
+
+# >
+# Make thread safe
+# With this option enabled, this allocator will be
+# made thread-safe. Additionally allocation functions
+# are made available that allow a thread to wait
+# until memory is available.
+#
+cdl_option CYGSEM_MEMALLOC_ALLOCATOR_SEPMETA_THREADAWARE {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# <
+# Kernel C API support for memory allocation
+# This option must be enabled to provide the extensions required
+# to support integration into the kernel C API.
+#
+cdl_option CYGFUN_MEMALLOC_KAPI {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGFUN_KERNEL_API_C
+ # CYGFUN_KERNEL_API_C (unknown) == 0
+ # --> 0
+};
+
+# malloc(0) returns NULL
+# This option controls the behavior of malloc(0) ( or calloc with
+# either argument 0 ). It is permitted by the standard to return
+# either a NULL pointer or a unique pointer. Enabling this option
+# forces a NULL pointer to be returned.
+#
+cdl_option CYGSEM_MEMALLOC_MALLOC_ZERO_RETURNS_NULL {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Breakpoint site when running out of memory
+# Whenever the system runs out of memory, it invokes this function
+# before either going to sleep waiting for memory to become
+# available or returning failure.
+#
+cdl_option CYGSEM_MEMALLOC_INVOKE_OUT_OF_MEMORY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# malloc() and supporting allocators
+# This component enables support for dynamic memory
+# allocation as supplied by the functions malloc(),
+# free(), calloc() and realloc(). As these
+# functions are often used, but can have quite an
+# overhead, disabling them here can ensure they
+# cannot even be used accidentally when static
+# allocation is preferred. Within this component are
+# various allocators that can be selected for use
+# as the underlying implementation of the dynamic
+# allocation functions.
+#
+cdl_component CYGPKG_MEMALLOC_MALLOC_ALLOCATORS {
+ # ActiveIf constraint: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Use external heap definition
+# This option allows other components in the
+# system to override the default system
+# provision of heap memory pools. This should
+# be set to a header which provides the equivalent
+# definitions to <pkgconf/heaps.hxx>.
+#
+cdl_component CYGBLD_MEMALLOC_MALLOC_EXTERNAL_HEAP_H {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Use external implementation of joining multiple heaps
+# The default implementation of joining multiple heaps
+# is fine for the case where there are multiple disjoint
+# memory regions of the same type. However, in a system
+# there might be e.g. a small amount of internal SRAM and
+# a large amount of external DRAM. The SRAM is faster and
+# the DRAM is slower. An application can implement some
+# heuristic to choose which pool to allocate from. This
+# heuristic can be highly application specific.
+#
+cdl_component CYGBLD_MEMALLOC_MALLOC_EXTERNAL_JOIN_H {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# malloc() allocator implementations
+#
+cdl_interface CYGINT_MEMALLOC_MALLOC_ALLOCATORS {
+ # Implemented by CYGIMP_MEMALLOC_MALLOC_VARIABLE_SIMPLE, active, disabled
+ # Implemented by CYGIMP_MEMALLOC_MALLOC_DLMALLOC, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: CYGINT_MEMALLOC_MALLOC_ALLOCATORS == 1
+ # CYGINT_MEMALLOC_MALLOC_ALLOCATORS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_MEMALLOC_MALLOC_ALLOCATORS
+ # Requires: CYGINT_MEMALLOC_MALLOC_ALLOCATORS == 1
+};
+
+# malloc() implementation instantiation data
+# Memory allocator implementations that are capable of being
+# used underneath malloc() must be instantiated. The code
+# to do this is set in this option. It is only intended to
+# be set by the implementation, not the user.
+#
+cdl_option CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value <cyg/memalloc/dlmalloc.hxx>
+ # value_source default
+ # Default value: <cyg/memalloc/dlmalloc.hxx>
+
+ # The following properties are affected by this value
+ # option CYGIMP_MEMALLOC_MALLOC_VARIABLE_SIMPLE
+ # Requires: CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == "<cyg/memalloc/memvar.hxx>"
+ # option CYGIMP_MEMALLOC_MALLOC_DLMALLOC
+ # Requires: CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == "<cyg/memalloc/dlmalloc.hxx>"
+};
+
+# Simple variable block implementation
+# This causes malloc() to use the simple
+# variable block allocator.
+#
+cdl_option CYGIMP_MEMALLOC_MALLOC_VARIABLE_SIMPLE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == "<cyg/memalloc/memvar.hxx>"
+ # CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == <cyg/memalloc/dlmalloc.hxx>
+ # --> 0
+ # Requires: CYGSEM_MEMALLOC_ALLOCATOR_VARIABLE_COALESCE
+ # CYGSEM_MEMALLOC_ALLOCATOR_VARIABLE_COALESCE == 1
+ # --> 1
+};
+
+# Doug Lea's malloc implementation
+# This causes malloc() to use a version of Doug Lea's
+# malloc (dlmalloc) as the underlying implementation.
+#
+cdl_option CYGIMP_MEMALLOC_MALLOC_DLMALLOC {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == "<cyg/memalloc/dlmalloc.hxx>"
+ # CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == <cyg/memalloc/dlmalloc.hxx>
+ # --> 1
+};
+
+# <
+# Size of the fallback dynamic memory pool in bytes
+# If *no* heaps are configured in your memory layout,
+# dynamic memory allocation by
+# malloc() and calloc() must be from a fixed-size,
+# contiguous memory pool (note here that it is the
+# pool that is of a fixed size, but malloc() is still
+# able to allocate variable sized chunks of memory
+# from it). This option is the size
+# of that pool, in bytes. Note that not all of
+# this is available for programs to
+# use - some is needed for internal information
+# about memory regions, and some may be lost to
+# ensure that memory allocation only returns
+# memory aligned on word (or double word)
+# boundaries - a very common architecture
+# constraint.
+#
+cdl_option CYGNUM_MEMALLOC_FALLBACK_MALLOC_POOL_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 16384
+ # value_source default
+ # Default value: 16384
+ # Legal values: 32 to 0x7fffffff
+};
+
+# Common memory allocator package build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_MEMALLOC_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_MEMALLOC_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-fno-rtti -Woverloaded-virtual"
+ # value_source default
+ # Default value: "-fno-rtti -Woverloaded-virtual"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_MEMALLOC_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wno-pointer-sign
+ # value_source default
+ # Default value: -Wno-pointer-sign
+};
+
+# Tests
+# This option specifies the set of tests for this package.
+#
+cdl_option CYGPKG_MEMALLOC_TESTS {
+ # Calculated value: "tests/dlmalloc1 tests/dlmalloc2 tests/heaptest tests/kmemfix1 tests/kmemvar1 tests/malloc1 tests/malloc2 tests/malloc3 tests/malloc4 tests/memfix1 tests/memfix2 tests/memvar1 tests/memvar2 tests/realloc tests/sepmeta1 tests/sepmeta2"
+ # Flavor: data
+ # Current_value: tests/dlmalloc1 tests/dlmalloc2 tests/heaptest tests/kmemfix1 tests/kmemvar1 tests/malloc1 tests/malloc2 tests/malloc3 tests/malloc4 tests/memfix1 tests/memfix2 tests/memvar1 tests/memvar2 tests/realloc tests/sepmeta1 tests/sepmeta2
+};
+
+# <
+# <
+# Common error code support
+# This package contains the common list of error and
+# status codes. It is held centrally to allow
+# packages to interchange error codes and status
+# codes in a common way, rather than each package
+# having its own conventions for error/status
+# reporting. The error codes are modelled on the
+# POSIX style naming e.g. EINVAL etc. This package
+# also provides the standard strerror() function to
+# convert error codes to textual representation, as
+# well as an implementation of the errno idiom.
+#
+cdl_package CYGPKG_ERROR {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGBLD_ISO_ERRNO_CODES_HEADER == "<cyg/error/codes.h>"
+ # CYGBLD_ISO_ERRNO_CODES_HEADER == <cyg/error/codes.h>
+ # --> 1
+};
+
+# >
+# errno variable
+# This package controls the behaviour of the
+# errno variable (or more strictly, expression)
+# from <errno.h>.
+#
+cdl_component CYGPKG_ERROR_ERRNO {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_ERRNO_HEADER == "<cyg/error/errno.h>"
+ # CYGBLD_ISO_ERRNO_HEADER == <cyg/error/errno.h>
+ # --> 1
+};
+
+# >
+# Per-thread errno
+# This option controls whether the standard error
+# code reporting variable errno is a per-thread
+# variable, rather than global.
+#
+cdl_option CYGSEM_ERROR_PER_THREAD_ERRNO {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+ # Requires: CYGVAR_KERNEL_THREADS_DATA
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+};
+
+# Tracing level
+# Trace verbosity level for debugging the errno
+# retrieval mechanism in errno.cxx. Increase this
+# value to get additional trace output.
+#
+cdl_option CYGNUM_ERROR_ERRNO_TRACE_LEVEL {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to 1
+};
+
+# <
+# strerror function
+# This package controls the presence and behaviour of the
+# strerror() function from <string.h>
+#
+cdl_option CYGPKG_ERROR_STRERROR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_STRERROR_HEADER == "<cyg/error/strerror.h>"
+ # CYGBLD_ISO_STRERROR_HEADER == <cyg/error/strerror.h>
+ # --> 1
+};
+
+# Error package build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_ERROR_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the error package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_ERROR_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the error package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_ERROR_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# <
+# <
+# <
+
--- /dev/null
+# eCos saved configuration
+
+# ---- commands --------------------------------------------------------
+# This section contains information about the savefile format.
+# It should not be edited. Any modifications made to this section
+# may make it impossible for the configuration tools to read
+# the savefile.
+
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+# ---- toplevel --------------------------------------------------------
+# This section defines the toplevel configuration object. The only
+# values that can be changed are the name of the configuration and
+# the description field. It is not possible to modify the target,
+# the template or the set of packages simply by editing the lines
+# below because these changes have wide-ranging effects. Instead
+# the appropriate tools should be used to make such modifications.
+
+cdl_configuration eCos {
+ description "" ;
+
+ # These fields should not be modified.
+ hardware tx37karo ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM current ;
+ package -hardware CYGPKG_HAL_ARM_MX37 current ;
+ package -hardware CYGPKG_HAL_ARM_TX37KARO current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_TX37 current ;
+ package -hardware CYGPKG_DEVS_ETH_FEC current ;
+ package -hardware CYGPKG_COMPRESS_ZLIB current ;
+ package -hardware CYGPKG_IO_FLASH current ;
+ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+ package -template CYGPKG_MEMALLOC current ;
+ package -template CYGPKG_DEVS_ETH_PHY current ;
+ package -template CYGPKG_LIBC_I18N current ;
+ package -template CYGPKG_LIBC_STDLIB current ;
+ package -template CYGPKG_ERROR current ;
+};
+
+# ---- conflicts -------------------------------------------------------
+# There are no conflicts.
+
+# ---- contents --------------------------------------------------------
+# >
+# >
+# Global build options
+# Global build options including control over
+# compiler flags, linker flags and choice of toolchain.
+#
+cdl_component CYGBLD_GLOBAL_OPTIONS {
+ # There is no associated value.
+
+ # The following properties are affected by this value
+};
+
+# >
+# Global command prefix
+# This option specifies the command prefix used when
+# invoking the build tools.
+#
+cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value arm-1136jfs-linux-gnu
+ # value_source default
+ # Default value: arm-1136jfs-linux-gnu
+};
+
+# Global compiler flags
+# This option controls the global compiler flags which are used to
+# compile all packages by default. Individual packages may define
+# options which override these global flags.
+#
+cdl_option CYGBLD_GLOBAL_CFLAGS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe"
+ # value_source default
+ # Default value: "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe"
+ # Requires: CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS
+ # CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS
+ # Requires: is_substr(CYGBLD_GLOBAL_CFLAGS, " -Werror")
+ # option CYGBLD_INFRA_CFLAGS_PIPE
+ # Requires: is_substr(CYGBLD_GLOBAL_CFLAGS, " -pipe")
+};
+
+# Global linker flags
+# This option controls the global linker flags. Individual
+# packages may define options which override these global flags.
+#
+cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-Wl,--gc-sections -Wl,-static -O2 -nostdlib"
+ # value_source default
+ # Default value: "-Wl,--gc-sections -Wl,-static -O2 -nostdlib"
+};
+
+# Build common GDB stub ROM image
+# Unless a target board has specific requirements to the
+# stub implementation, it can use a simple common stub.
+# This option, which gets enabled by platform HALs as
+# appropriate, controls the building of the common stub.
+#
+cdl_option CYGBLD_BUILD_COMMON_GDB_STUBS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+};
+
+# <
+# ISO C library string functions
+# doc: ref/libc.html
+# This package provides string functions specified by the
+# ISO C standard - ISO/IEC 9899:1990.
+#
+cdl_package CYGPKG_LIBC_STRING {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER == "<cyg/libc/string/string.h>"
+ # CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER == <cyg/libc/string/string.h>
+ # --> 1
+ # Requires: CYGBLD_ISO_STRING_MEMFUNCS_HEADER == "<cyg/libc/string/string.h>"
+ # CYGBLD_ISO_STRING_MEMFUNCS_HEADER == <cyg/libc/string/string.h>
+ # --> 1
+ # Requires: CYGBLD_ISO_STRING_STRFUNCS_HEADER == "<cyg/libc/string/string.h>"
+ # CYGBLD_ISO_STRING_STRFUNCS_HEADER == <cyg/libc/string/string.h>
+ # --> 1
+ # Requires: CYGBLD_ISO_STRTOK_R_HEADER == "<cyg/libc/string/string.h>"
+ # CYGBLD_ISO_STRTOK_R_HEADER == <cyg/libc/string/string.h>
+ # --> 1
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+};
+
+# >
+# Inline versions of <string.h> functions
+# This option chooses whether some of the
+# particularly simple string functions from
+# <string.h> are available as inline
+# functions. This may improve performance, and as
+# the functions are small, may even improve code
+# size.
+#
+cdl_option CYGIMP_LIBC_STRING_INLINES {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Optimize string functions for code size
+# This option tries to reduce string function
+# code size at the expense of execution speed. The
+# same effect can be produced if the code is
+# compiled with the -Os option to the compiler.
+#
+cdl_option CYGIMP_LIBC_STRING_PREFER_SMALL_TO_FAST {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Provide BSD compatibility functions
+# Enabling this option causes various compatibility functions
+# commonly found in the BSD UNIX operating system to be included.
+# These are functions such as bzero, bcmp, bcopy, bzero, strcasecmp,
+# strncasecmp, index, rindex and swab.
+#
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+ # Requires: CYGBLD_ISO_STRING_BSD_FUNCS_HEADER == "<cyg/libc/string/bsdstring.h>"
+ # CYGBLD_ISO_STRING_BSD_FUNCS_HEADER == <cyg/libc/string/bsdstring.h>
+ # --> 1
+ # Requires: CYGINT_ISO_CTYPE
+ # CYGINT_ISO_CTYPE == 1
+ # --> 1
+};
+
+# strtok
+# These options control the behaviour of the
+# strtok() and strtok_r() string tokenization
+# functions.
+#
+cdl_component CYGPKG_LIBC_STRING_STRTOK {
+ # There is no associated value.
+};
+
+# >
+# Per-thread strtok()
+# This option controls whether the string function
+# strtok() has its state recorded on a per-thread
+# basis rather than global. If this option is
+# disabled, some per-thread space can be saved.
+# Note there is also a POSIX-standard strtok_r()
+# function to achieve a similar effect with user
+# support. Enabling this option will use one slot
+# of kernel per-thread data. You should ensure you
+# have enough slots configured for all your
+# per-thread data.
+#
+cdl_option CYGSEM_LIBC_STRING_PER_THREAD_STRTOK {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGVAR_KERNEL_THREADS_DATA
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+ # Requires: CYGVAR_KERNEL_THREADS_DATA
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+};
+
+# Tracing level
+# Trace verbosity level for debugging the <string.h>
+# functions strtok() and strtok_r(). Increase this
+# value to get additional trace output.
+#
+cdl_option CYGNUM_LIBC_STRING_STRTOK_TRACE_LEVEL {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to 1
+};
+
+# <
+# strdup
+# This option indicates whether strdup() is to be supported.
+#
+cdl_option CYGFUN_LIBC_STRING_STRDUP {
+ # ActiveIf constraint: CYGINT_ISO_MALLOC
+ # CYGINT_ISO_MALLOC == 1
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+};
+
+# C library string functions build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_LIBC_STRING_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the C library. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_LIBC_STRING_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-fno-rtti -Woverloaded-virtual"
+ # value_source default
+ # Default value: "-fno-rtti -Woverloaded-virtual"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the C library. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_LIBC_STRING_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wno-pointer-sign
+ # value_source default
+ # Default value: -Wno-pointer-sign
+};
+
+# C library string function tests
+# This option specifies the set of tests for the C library
+# string functions.
+#
+cdl_option CYGPKG_LIBC_STRING_TESTS {
+ # Calculated value: "tests/memchr tests/memcmp1 tests/memcmp2 tests/memcpy1 tests/memcpy2 tests/memmove1 tests/memmove2 tests/memset tests/strcat1 tests/strcat2 tests/strchr tests/strcmp1 tests/strcmp2 tests/strcoll1 tests/strcoll2 tests/strcpy1 tests/strcpy2 tests/strcspn tests/strcspn tests/strlen tests/strncat1 tests/strncat2 tests/strncpy1 tests/strncpy2 tests/strpbrk tests/strrchr tests/strspn tests/strstr tests/strtok tests/strxfrm1 tests/strxfrm2"
+ # Flavor: data
+ # Current_value: tests/memchr tests/memcmp1 tests/memcmp2 tests/memcpy1 tests/memcpy2 tests/memmove1 tests/memmove2 tests/memset tests/strcat1 tests/strcat2 tests/strchr tests/strcmp1 tests/strcmp2 tests/strcoll1 tests/strcoll2 tests/strcpy1 tests/strcpy2 tests/strcspn tests/strcspn tests/strlen tests/strncat1 tests/strncat2 tests/strncpy1 tests/strncpy2 tests/strpbrk tests/strrchr tests/strspn tests/strstr tests/strtok tests/strxfrm1 tests/strxfrm2
+};
+
+# <
+# <
+# Common ethernet support
+# doc: ref/io-eth-drv-generic.html
+# Platform independent ethernet drivers
+#
+cdl_package CYGPKG_IO_ETH_DRIVERS {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # component CYGPKG_REDBOOT_NETWORKING
+ # ActiveIf: CYGPKG_IO_ETH_DRIVERS
+ # package CYGPKG_DEVS_ETH_ARM_TX37
+ # ActiveIf: CYGPKG_IO_ETH_DRIVERS
+ # package CYGPKG_DEVS_ETH_FEC
+ # ActiveIf: CYGPKG_IO_ETH_DRIVERS
+ # package CYGPKG_DEVS_ETH_PHY
+ # ActiveIf: CYGPKG_IO_ETH_DRIVERS
+};
+
+# >
+# Network drivers
+#
+cdl_interface CYGHWR_NET_DRIVERS {
+ # Implemented by CYGPKG_DEVS_ETH_FEC, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGDAT_REDBOOT_DEFAULT_NETWORK_DEVICE
+ # ActiveIf: CYGHWR_NET_DRIVERS > 1
+ # option CYGSEM_REDBOOT_NETWORK_INIT_ONE_DEVICE
+ # ActiveIf: CYGHWR_NET_DRIVERS > 1
+};
+
+# Driver supports multicast addressing
+# This interface defines whether or not a driver can handle
+# requests for multicast addressing.
+#
+cdl_interface CYGINT_IO_ETH_MULTICAST {
+ # Implemented by CYGPKG_DEVS_ETH_FEC, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+};
+
+# Support printing driver debug information
+# Selecting this option will include code to allow the driver to
+# print lots of information on diagnostic output such as full
+# packet dumps.
+#
+cdl_component CYGDBG_IO_ETH_DRIVERS_DEBUG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Driver debug output verbosity
+# The value of this option indicates the default verbosity
+# level of debugging output. 0 means no debugging output
+# is made by default. Higher values indicate higher verbosity.
+# The verbosity level may also be changed at run time by
+# changing the variable cyg_io_eth_net_debug.
+#
+cdl_option CYGDBG_IO_ETH_DRIVERS_DEBUG_VERBOSITY {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Size of scatter-gather I/O lists
+# A scatter-gather list is used to pass requests to/from
+# the physical device driver. This list can typically be
+# small, as the data is normally already packed into reasonable
+# chunks.
+#
+cdl_option CYGNUM_IO_ETH_DRIVERS_SG_LIST_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 32
+ # value_source default
+ # Default value: 32
+};
+
+# Support for standard eCos TCP/IP stack.
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_NET {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_NET
+ # CYGPKG_NET (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+};
+
+# >
+# Warn when there are no more mbufs
+# Warnings about running out of mbufs are printed to the
+# diagnostic output channel via diag_printf() if this option
+# is enabled. Mbufs are the network stack's basic dynamic
+# memory objects that hold all packets in transit; running
+# out is bad for performance but not fatal, not a crash.
+# You might want to turn off the warnings to preserve realtime
+# properties of the system even in extremis.
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_WARN_NO_MBUFS {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_NET is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Simulate network failures for testing
+# This package contains a suite of simulated failure modes
+# for the ethernet device layer, including dropping and/or
+# corrupting received packets, dropping packets queued for
+# transmission, and simulating a complete network break.
+# It requires the kernel as a source of time information.
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_NET is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# >
+# Drop incoming packets (percentage)
+#
+cdl_option CYGPKG_IO_ETH_DRIVERS_SIMULATE_DROP_RX {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 1 10
+ # value_source default
+ # Default value: 1 10
+ # Legal values: 10 50 80
+};
+
+# Corrupt incoming packets (percentage)
+#
+cdl_option CYGPKG_IO_ETH_DRIVERS_SIMULATE_CORRUPT_RX {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 1 10
+ # value_source default
+ # Default value: 1 10
+ # Legal values: 10 50 80
+};
+
+# Drop outgoing packets (percentage)
+#
+cdl_option CYGPKG_IO_ETH_DRIVERS_SIMULATE_DROP_TX {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 1 10
+ # value_source default
+ # Default value: 1 10
+ # Legal values: 10 50 80
+};
+
+# Simulate a line cut from time to time
+# This option causes the system to drop all packets for a
+# short random period (10s of seconds), and then act
+# normally for up to 4 times that long. This simulates your
+# sysadmin fiddling with plugs in the network switch
+# cupboard.
+#
+cdl_option CYGPKG_IO_ETH_DRIVERS_SIMULATE_LINE_CUT {
+ # This option is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is not active
+ # The parent CYGPKG_IO_ETH_DRIVERS_SIMULATED_FAILURES is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# <
+# Support for stand-alone network stack.
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_STAND_ALONE {
+ # ActiveIf constraint: !CYGPKG_NET
+ # CYGPKG_NET (unknown) == 0
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGINT_ISO_STRING_MEMFUNCS
+ # CYGINT_ISO_STRING_MEMFUNCS == 1
+ # --> 1
+};
+
+# >
+# Pass packets to an alternate stack
+# Define this to allow packets seen by this layer to be
+# passed on to the previous logical layer, i.e. when
+# stand-alone processing replaces system (eCos) processing.
+#
+cdl_option CYGSEM_IO_ETH_DRIVERS_PASS_PACKETS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 0 != CYGPKG_REDBOOT_NETWORKING
+ # CYGPKG_REDBOOT_NETWORKING == 1
+ # --> 1
+};
+
+# Number of [network] buffers
+# This option is used to allocate space to buffer incoming network
+# packets. These buffers are used to hold data until they can be
+# logically processed by higher layers.
+#
+cdl_option CYGNUM_IO_ETH_DRIVERS_NUM_PKT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 4
+ # value_source default
+ # Default value: 4
+ # Legal values: 2 to 32
+};
+
+# Show driver warnings
+# Selecting this option will allows the stand-alone ethernet driver
+# to display warnings on the system console when incoming network
+# packets are being discarded due to lack of buffer space.
+#
+cdl_option CYGSEM_IO_ETH_DRIVERS_WARN {
+ # ActiveIf constraint: CYGPKG_REDBOOT
+ # CYGPKG_REDBOOT == current
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Support for lwIP network stack.
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_LWIP {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_NET_LWIP
+ # CYGPKG_NET_LWIP (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: !CYGPKG_NET
+ # CYGPKG_NET (unknown) == 0
+ # --> 1
+};
+
+# Interrupt support required
+# This interface is used to indicate to the low
+# level device drivers that interrupt driven operation
+# is required by higher layers.
+#
+cdl_interface CYGINT_IO_ETH_INT_SUPPORT_REQUIRED {
+ # Implemented by CYGPKG_IO_ETH_DRIVERS_NET, inactive, enabled
+ # Implemented by CYGPKG_IO_ETH_DRIVERS_LWIP, inactive, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+
+ # The following properties are affected by this value
+};
+
+# Common ethernet support build options
+#
+cdl_component CYGPKG_IO_ETH_DRIVERS_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the common ethernet support package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_IO_ETH_DRIVERS_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-D_KERNEL -D__ECOS"
+ # value_source default
+ # Default value: "-D_KERNEL -D__ECOS"
+};
+
+# <
+# Ethernet driver for Ka-Ro electronics TX37 processor module
+#
+cdl_package CYGPKG_DEVS_ETH_ARM_TX37 {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # ActiveIf constraint: CYGPKG_IO_ETH_DRIVERS
+ # CYGPKG_IO_ETH_DRIVERS == current
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+};
+
+# >
+# FEC ethernet driver required
+#
+cdl_interface CYGINT_DEVS_ETH_FEC_REQUIRED {
+ # Implemented by CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # package CYGPKG_DEVS_ETH_FEC
+ # ActiveIf: CYGINT_DEVS_ETH_FEC_REQUIRED
+};
+
+# Ka-Ro TX37 ethernet port driver
+# This option includes the ethernet device driver for the
+# MXC Board port.
+#
+cdl_component CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ # CYGSEM_REDBOOT_PLF_ESA_VALIDATE == 1
+ # --> 1
+ # Requires: CYGHWR_DEVS_ETH_PHY_LAN8700
+ # CYGHWR_DEVS_ETH_PHY_LAN8700 == 1
+ # --> 1
+};
+
+# >
+# Device name for the ETH0 ethernet driver
+# This option sets the name of the ethernet device.
+#
+cdl_option CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "\"eth0\""
+ # value_source default
+ # Default value: "\"eth0\""
+};
+
+# OUI part of MAC address
+# This option sets OUI part (manufacturer ID) of the MAC address
+# for validation.
+#
+cdl_option CYGDAT_DEVS_ETH_ARM_TX37KARO_OUI {
+ # ActiveIf constraint: CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ # CYGSEM_REDBOOT_PLF_ESA_VALIDATE == 1
+ # --> 1
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "{ 0x00, 0x0c, 0xc6 }"
+ # value_source default
+ # Default value: "{ 0x00, 0x0c, 0xc6 }"
+};
+
+# <
+# <
+# Driver for fast ethernet controller.
+# Driver for fast ethernet controller.
+#
+cdl_package CYGPKG_DEVS_ETH_FEC {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # ActiveIf constraint: CYGPKG_IO_ETH_DRIVERS
+ # CYGPKG_IO_ETH_DRIVERS == current
+ # --> 1
+ # ActiveIf constraint: CYGINT_DEVS_ETH_FEC_REQUIRED
+ # CYGINT_DEVS_ETH_FEC_REQUIRED == 1
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+};
+
+# >
+# MXC FEC ethernet driver build options
+#
+cdl_component CYGPKG_DEVS_ETH_FEC_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the Cirrus Logic ethernet driver package.
+# These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_DEVS_ETH_FEC_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-D_KERNEL -D__ECOS"
+ # value_source default
+ # Default value: "-D_KERNEL -D__ECOS"
+};
+
+# <
+# <
+# Ethernet transceiver (PHY) support
+# API for ethernet PHY devices
+#
+cdl_package CYGPKG_DEVS_ETH_PHY {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # ActiveIf constraint: CYGPKG_IO_ETH_DRIVERS
+ # CYGPKG_IO_ETH_DRIVERS == current
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT == 1
+ # --> 1
+};
+
+# >
+# Enable driver debugging
+# Enables the diagnostic debug messages on the
+# console device.
+#
+cdl_option CYGDBG_DEVS_ETH_PHY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Time period (seconds) to wait for auto-negotiation
+# The length of time to wait for auto-negotiation to complete
+# before giving up and declaring the link dead/missing.
+#
+cdl_option CYGINT_DEVS_ETH_PHY_AUTO_NEGOTIATION_TIME {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 5
+ # value_source default
+ # Default value: 5
+};
+
+# NSDP83847
+# Include support for National Semiconductor DP83847 DsPHYTER II
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_DP83847 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# AMD 79C874
+# Include support for AMD 79C874 NetPHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_AM79C874 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Intel LXT972
+# Include support for Intel LXT972xxx PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_INLXT972 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# ICS 1890
+# Include support for ICS 1890 PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_ICS1890 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# ICS 1892
+# Include support for ICS 1892 PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_ICS1892 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# ICS 1893
+# Include support for ICS 1893 and 1893AF PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_ICS1893 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Davicom DM9161A
+# Include support for the Davicom DM9161A PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_DM9161A {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Micrel KS8721
+# Include support for the Micrel KS8721 PHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_KS8721 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# SMSC LAN8700
+# Include support for SMSC LAN8700 NetPHY
+#
+cdl_option CYGHWR_DEVS_ETH_PHY_LAN8700 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # component CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
+ # Requires: CYGHWR_DEVS_ETH_PHY_LAN8700
+};
+
+# <
+# <
+# ISO C library internationalization functions
+# doc: ref/libc.html
+# This package provides internationalization functions specified by the
+# ISO C standard - ISO/IEC 9899:1990. These include locale-related
+# functionality and <ctype.h> functionality.
+#
+cdl_package CYGPKG_LIBC_I18N {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+};
+
+# >
+# Supported locales
+# These options determine which locales other than the "C" locale
+# are supported and hence contribute to the size of the executable.
+#
+cdl_component CYGPKG_LIBC_I18N_LOCALES {
+ # There is no associated value.
+};
+
+# >
+# Support for multiple locales required
+#
+cdl_interface CYGINT_LIBC_I18N_MB_REQUIRED {
+ # Implemented by CYGFUN_LIBC_I18N_LOCALE_C_SJIS, active, disabled
+ # Implemented by CYGFUN_LIBC_I18N_LOCALE_C_JIS, active, disabled
+ # Implemented by CYGFUN_LIBC_I18N_LOCALE_C_EUCJP, active, disabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: CYGBLD_ISO_STDLIB_MB_CUR_MAX_HEADER == "<cyg/libc/i18n/mb.h>"
+ # CYGBLD_ISO_STDLIB_MB_CUR_MAX_HEADER == 0
+ # --> 0
+
+ # The following properties are affected by this value
+};
+
+# C-SJIS locale support
+# This option controls if the "C-SJIS" locale will be
+# supported by setlocale(). The locale is a hybrid locale
+# that is mostly the "C" locale with Japanese SJIS multibyte
+# support added.
+#
+cdl_option CYGFUN_LIBC_I18N_LOCALE_C_SJIS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # LegalValues: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2))) to 0x7fffffff
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # DefaultValue: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2)))
+};
+
+# C-JIS locale support
+# This option controls if the "C-JIS" locale will be
+# supported by setlocale(). The locale is a hybrid locale
+# that is mostly the "C" locale with Japanese JIS multibyte
+# support added.
+#
+cdl_option CYGFUN_LIBC_I18N_LOCALE_C_JIS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # LegalValues: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2))) to 0x7fffffff
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # DefaultValue: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2)))
+};
+
+# C-EUCJP locale support
+# This option controls if the "C-EUCJP" locale will be
+# supported by setlocale(). The locale is a hybrid locale
+# that is mostly the "C" locale with Japanese EUCJP multibyte
+# support added.
+#
+cdl_option CYGFUN_LIBC_I18N_LOCALE_C_EUCJP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # LegalValues: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2))) to 0x7fffffff
+ # option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE
+ # DefaultValue: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2)))
+};
+
+# <
+# Newlib's ctype implementation
+# This option enables the implementation of the ctype functions
+# that comes with newlib. It is table driven and therefore
+# exhibits different performance characteristics. It also offers
+# a limited amount of binary compatibility
+# with newlib so that programs linked against newlib ctype/locale
+# do not need to be recompiled when linked with eCos.
+#
+cdl_option CYGPKG_LIBC_I18N_NEWLIB_CTYPE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGBLD_ISO_CTYPE_HEADER == "<cyg/libc/i18n/newlibctype.h>"
+ # CYGBLD_ISO_CTYPE_HEADER == <cyg/libc/i18n/ctype.inl>
+ # --> 0
+};
+
+# Per-thread multibyte state
+# This option controls whether the multibyte character
+# handling functions mblen(), mbtowc(), and wctomb(),
+# have their state recorded on a per-thread
+# basis rather than global. If this option is
+# disabled, some per-thread space can be saved.
+# Enabling this option will use three slots
+# of kernel per-thread data. You should ensure you
+# have enough slots configured for all your
+# per-thread data.
+#
+cdl_option CYGSEM_LIBC_I18N_PER_THREAD_MB {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGVAR_KERNEL_THREADS_DATA != 0
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+ # Requires: CYGVAR_KERNEL_THREADS_DATA
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+};
+
+# Size of locale name strings
+# This option controls the maximum size of
+# locale names and is used, among other things
+# to instantiate a static string used
+# as a return value from the
+# setlocale() function. When requesting the
+# current locale settings with LC_ALL, a string
+# must be constructed to contain this data, rather
+# than just returning a constant string. This
+# string data is stored in the static string.
+# This depends on the length of locale names,
+# hence this option. If just the C locale is
+# present, this option can be set as low as 2.
+#
+cdl_option CYGNUM_LIBC_I18N_MAX_LOCALE_NAME_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 2
+ # value_source default
+ # Default value: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2)))
+ # CYGFUN_LIBC_I18N_LOCALE_C_EUCJP == 0
+ # CYGFUN_LIBC_I18N_LOCALE_C_SJIS == 0
+ # CYGFUN_LIBC_I18N_LOCALE_C_JIS == 0
+ # --> 2
+ # Legal values: (CYGFUN_LIBC_I18N_LOCALE_C_EUCJP ? 8 : (CYGFUN_LIBC_I18N_LOCALE_C_SJIS ? 7 : (CYGFUN_LIBC_I18N_LOCALE_C_JIS ? 6 : 2))) to 0x7fffffff
+ # CYGFUN_LIBC_I18N_LOCALE_C_EUCJP == 0
+ # CYGFUN_LIBC_I18N_LOCALE_C_SJIS == 0
+ # CYGFUN_LIBC_I18N_LOCALE_C_JIS == 0
+};
+
+# Inline versions of <ctype.h> functions
+# This option chooses whether the simple character
+# classification and conversion functions (e.g.
+# isupper(), isalpha(), toupper(), etc.)
+# from <ctype.h> are available as inline
+# functions. This may improve performance and as
+# the functions are small, may even improve code
+# size.
+#
+cdl_option CYGIMP_LIBC_I18N_CTYPE_INLINES {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_CTYPE_HEADER == "<cyg/libc/i18n/ctype.inl>"
+ # CYGBLD_ISO_CTYPE_HEADER == <cyg/libc/i18n/ctype.inl>
+ # --> 1
+};
+
+# C library i18n functions build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_LIBC_I18N_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the C library. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_LIBC_I18N_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-fno-rtti -Woverloaded-virtual"
+ # value_source default
+ # Default value: "-fno-rtti -Woverloaded-virtual"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the C library. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_LIBC_I18N_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wno-pointer-sign
+ # value_source default
+ # Default value: -Wno-pointer-sign
+};
+
+# C library i18n function tests
+# This option specifies the set of tests for the C library
+# i18n functions.
+#
+cdl_option CYGPKG_LIBC_I18N_TESTS {
+ # Calculated value: "tests/ctype tests/setlocale tests/i18nmb"
+ # Flavor: data
+ # Current_value: tests/ctype tests/setlocale tests/i18nmb
+};
+
+# <
+# <
+# ISO C library general utility functions
+# doc: ref/libc.html
+# This package provides general utility functions in <stdlib.h>
+# as specified by the ISO C standard - ISO/IEC 9899:1990.
+#
+cdl_package CYGPKG_LIBC_STDLIB {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+ # Requires: CYGINT_ISO_CTYPE
+ # CYGINT_ISO_CTYPE == 1
+ # --> 1
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+};
+
+# >
+# Inline versions of <stdlib.h> functions
+# This option chooses whether some of the
+# particularly simple standard utility functions
+# from <stdlib.h> are available as inline
+# functions. This may improve performance, and as
+# the functions are small, may even improve code
+# size.
+#
+cdl_component CYGIMP_LIBC_STDLIB_INLINES {
+ # There is no associated value.
+};
+
+# >
+# abs() / labs()
+#
+cdl_option CYGIMP_LIBC_STDLIB_INLINE_ABS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_STDLIB_ABS_HEADER == "<cyg/libc/stdlib/abs.inl>"
+ # CYGBLD_ISO_STDLIB_ABS_HEADER == <cyg/libc/stdlib/abs.inl>
+ # --> 1
+};
+
+# div() / ldiv()
+#
+cdl_option CYGIMP_LIBC_STDLIB_INLINE_DIV {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_STDLIB_DIV_HEADER == "<cyg/libc/stdlib/div.inl>"
+ # CYGBLD_ISO_STDLIB_DIV_HEADER == <cyg/libc/stdlib/div.inl>
+ # --> 1
+};
+
+# atof() / atoi() / atol()
+#
+cdl_option CYGIMP_LIBC_STDLIB_INLINE_ATOX {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_STDLIB_STRCONV_HEADER == "<cyg/libc/stdlib/atox.inl>"
+ # CYGBLD_ISO_STDLIB_STRCONV_HEADER == <cyg/libc/stdlib/atox.inl>
+ # --> 1
+};
+
+# <
+# Random number generation
+# These options control the behaviour of the
+# functions rand(), srand() and rand_r()
+#
+cdl_component CYGPKG_LIBC_RAND {
+ # There is no associated value.
+};
+
+# >
+# Per-thread random seed
+# doc: ref/libc-thread-safety.html
+# This option controls whether the pseudo-random
+# number generation functions rand() and srand()
+# have their state recorded on a per-thread
+# basis rather than global. If this option is
+# disabled, some per-thread space can be saved.
+# Note there is also a POSIX-standard rand_r()
+# function to achieve a similar effect with user
+# support. Enabling this option will use one slot
+# of kernel per-thread data. You should ensure you
+# have enough slots configured for all your
+# per-thread data.
+#
+cdl_option CYGSEM_LIBC_PER_THREAD_RAND {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGVAR_KERNEL_THREADS_DATA
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+};
+
+# Random number seed
+# This selects the initial random number seed for
+# rand()'s pseudo-random number generator. For
+# strict ISO standard compliance, this should be 1,
+# as per section 7.10.2.2 of the standard.
+#
+cdl_option CYGNUM_LIBC_RAND_SEED {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Legal values: 0 to 0x7fffffff
+};
+
+# Tracing level
+# Trace verbosity level for debugging the rand(),
+# srand() and rand_r() functions. Increase this
+# value to get additional trace output.
+#
+cdl_option CYGNUM_LIBC_RAND_TRACE_LEVEL {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to 1
+};
+
+# Simplest implementation
+# This provides a very simple implementation of rand()
+# that does not perform well with randomness in the
+# lower significant bits. However it is exceptionally
+# fast. It uses the sample algorithm from the ISO C
+# standard itself.
+#
+cdl_option CYGIMP_LIBC_RAND_SIMPLEST {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Simple implementation #1
+# This provides a very simple implementation of rand()
+# based on the simplest implementation above. However
+# it does try to work around the lack of randomness
+# in the lower significant bits, at the expense of a
+# little speed.
+#
+cdl_option CYGIMP_LIBC_RAND_SIMPLE1 {
+ # Flavor: bool
+ user_value 0
+ # value_source user
+ # Default value: 1
+};
+
+# Knuth implementation #1
+# This implements a slightly more complex algorithm
+# published in Donald E. Knuth's Art of Computer
+# Programming Vol.2 section 3.6 (p.185 in the 3rd ed.).
+# This produces better random numbers than the
+# simplest approach but is slower.
+#
+cdl_option CYGIMP_LIBC_RAND_KNUTH1 {
+ # Flavor: bool
+ user_value 1
+ # value_source user
+ # Default value: 0
+};
+
+# <
+# Provides strtod()
+# This option allows use of the utility function
+# strtod() (and consequently atof()) to convert
+# from string to double precision floating point
+# numbers. Disabling this option removes the
+# dependency on the math library package.
+#
+cdl_option CYGFUN_LIBC_strtod {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0 != CYGPKG_LIBM
+ # CYGPKG_LIBM (unknown) == 0
+ # --> 0
+ # Requires: CYGPKG_LIBM
+ # CYGPKG_LIBM (unknown) == 0
+ # --> 0
+};
+
+# Provides long long conversion functions
+# Enabling this option will provide support for the strtoll(),
+# strtoull() and atoll() conversion functions, which are
+# the long long variants of the standard versions of these
+# functions. Supporting this requires extra code and compile
+# time.
+#
+cdl_option CYGFUN_LIBC_STDLIB_CONV_LONGLONG {
+ # Flavor: bool
+ user_value 0
+ # value_source user
+ # Default value: 1
+};
+
+# bsearch() tracing level
+# Trace verbosity level for debugging the <stdlib.h>
+# binary search function bsearch(). Increase this
+# value to get additional trace output.
+#
+cdl_option CYGNUM_LIBC_BSEARCH_TRACE_LEVEL {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to 1
+};
+
+# qsort() tracing level
+# Trace verbosity level for debugging the <stdlib.h>
+# quicksort function qsort(). Increase this value
+# to get additional trace output.
+#
+cdl_option CYGNUM_LIBC_QSORT_TRACE_LEVEL {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to 1
+};
+
+# C library stdlib build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_LIBC_STDLIB_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_LIBC_STDLIB_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-fno-rtti -Woverloaded-virtual"
+ # value_source default
+ # Default value: "-fno-rtti -Woverloaded-virtual"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_LIBC_STDLIB_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wno-pointer-sign
+ # value_source default
+ # Default value: -Wno-pointer-sign
+};
+
+# C library stdlib tests
+# This option specifies the set of tests for this package.
+#
+cdl_option CYGPKG_LIBC_STDLIB_TESTS {
+ # Calculated value: "tests/abs tests/atoi tests/atol tests/bsearch tests/div tests/getenv tests/labs tests/ldiv tests/qsort tests/rand1 tests/rand2 tests/rand3 tests/rand4 tests/srand tests/strtol tests/strtoul"
+ # Flavor: data
+ # Current_value: tests/abs tests/atoi tests/atol tests/bsearch tests/div tests/getenv tests/labs tests/ldiv tests/qsort tests/rand1 tests/rand2 tests/rand3 tests/rand4 tests/srand tests/strtol tests/strtoul
+};
+
+# <
+# <
+# <
+# eCos HAL
+# doc: ref/the-ecos-hardware-abstraction-layer.html
+# The eCos HAL package provide a porting layer for
+# higher-level parts of the system such as the kernel and the
+# C library. Each installation should have HAL packages for
+# one or more architectures, and for each architecture there
+# may be one or more supported platforms. It is necessary to
+# select one target architecture and one platform for that
+# architecture. There are also a number of configuration
+# options that are common to all HAL packages.
+#
+cdl_package CYGPKG_HAL {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGPKG_INFRA
+ # CYGPKG_INFRA == current
+ # --> 1
+
+ # The following properties are affected by this value
+};
+
+# >
+# Platform-independent HAL options
+# A number of configuration options are common to most or all
+# HAL packages, for example options controlling how much state
+# should be saved during a context switch. The implementations
+# of these options will vary from architecture to architecture.
+#
+cdl_component CYGPKG_HAL_COMMON {
+ # There is no associated value.
+};
+
+# >
+# Provide eCos kernel support
+# The HAL can be configured to either support the full eCos
+# kernel, or to support only very simple applications which do
+# not require a full kernel. If kernel support is not required
+# then some of the startup, exception, and interrupt handling
+# code can be eliminated.
+#
+cdl_option CYGFUN_HAL_COMMON_KERNEL_SUPPORT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+ # Requires: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+};
+
+# HAL exception support
+# When a processor exception occurs, for example an attempt to
+# execute an illegal instruction or to perform a divide by
+# zero, this exception may be handled in a number of different
+# ways. If the target system has gdb support then typically
+# the exception will be handled by gdb code. Otherwise if the
+# HAL exception support is enabled then the HAL will invoke a
+# routine deliver_exception(). Typically this routine will be
+# provided by the eCos kernel, but it is possible for
+# application code to provide its own implementation. If the
+# HAL exception support is not enabled and a processor
+# exception occurs then the behaviour of the system is
+# undefined.
+#
+cdl_option CYGPKG_HAL_EXCEPTIONS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGPKG_KERNEL_EXCEPTIONS
+ # CYGPKG_KERNEL_EXCEPTIONS (unknown) == 0
+ # --> 0
+ # Requires: CYGPKG_KERNEL_EXCEPTIONS
+ # CYGPKG_KERNEL_EXCEPTIONS (unknown) == 0
+ # --> 0
+};
+
+# Stop calling constructors early
+# This option supports environments where some constructors
+# must be run in the context of a thread rather than at
+# simple system startup time. A boolean flag named
+# cyg_hal_stop_constructors is set to 1 when constructors
+# should no longer be invoked. It is up to some other
+# package to deal with the rest of the constructors.
+# In the current version this is only possible with the
+# C library.
+#
+cdl_option CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGSEM_LIBC_INVOKE_DEFAULT_STATIC_CONSTRUCTORS
+ # CYGSEM_LIBC_INVOKE_DEFAULT_STATIC_CONSTRUCTORS (unknown) == 0
+ # --> 0
+};
+
+# HAL uses the MMU and allows for CDL manipulation of it's use
+#
+cdl_interface CYGINT_HAL_SUPPORTS_MMU_TABLES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_INSTALL_MMU_TABLES
+ # ActiveIf: CYGINT_HAL_SUPPORTS_MMU_TABLES
+};
+
+# Install MMU tables.
+# This option controls whether this application installs
+# its own Memory Management Unit (MMU) tables, or relies on the
+# existing environment to run.
+#
+cdl_option CYGSEM_HAL_INSTALL_MMU_TABLES {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_HAL_SUPPORTS_MMU_TABLES
+ # CYGINT_HAL_SUPPORTS_MMU_TABLES == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYG_HAL_STARTUP != "RAM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_STATIC_MMU_TABLES
+ # Requires: CYGSEM_HAL_INSTALL_MMU_TABLES
+};
+
+# Use static MMU tables.
+# This option defines an environment where any Memory
+# Management Unit (MMU) tables are constant. Normally used by ROM
+# based environments, this provides a way to save RAM usage which
+# would otherwise be required for these tables.
+#
+cdl_option CYGSEM_HAL_STATIC_MMU_TABLES {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGSEM_HAL_INSTALL_MMU_TABLES
+ # CYGSEM_HAL_INSTALL_MMU_TABLES == 0
+ # --> 0
+};
+
+# Route diagnostic output to debug channel
+# If not inheriting the console setup from the ROM monitor,
+# it is possible to redirect diagnostic output to the debug
+# channel by enabling this option. Depending on the debugger
+# used it may also be necessary to select a mangler for the
+# output to be displayed by the debugger.
+#
+cdl_component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN {
+ # ActiveIf constraint: !CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE == 0
+ # --> 1
+ # ActiveIf constraint: CYGPKG_HAL_ARM || CYGPKG_HAL_POWERPC_MPC8xx || CYGPKG_HAL_V85X_V850 || CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+ # CYGPKG_HAL_ARM == current
+ # CYGPKG_HAL_POWERPC_MPC8xx (unknown) == 0
+ # CYGPKG_HAL_V85X_V850 (unknown) == 0
+ # CYGSEM_HAL_VIRTUAL_VECTOR_DIAG == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: (CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS || CYG_HAL_STARTUP == "RAM") ? 1 : 0
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 0
+
+ # The following properties are affected by this value
+ # option CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ # Calculated: !CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE && !CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+};
+
+# >
+# Mangler used on diag output
+# It is sometimes necessary to mangle (encode) the
+# diag ASCII text output in order for it to show up at the
+# other end. In particular, GDB may silently ignore raw
+# ASCII text.
+#
+cdl_option CYGSEM_HAL_DIAG_MANGLER {
+ # This option is not active
+ # The parent CYGDBG_HAL_DIAG_TO_DEBUG_CHAN is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value GDB
+ # value_source default
+ # Default value: GDB
+ # Legal values: "GDB" "None"
+};
+
+# <
+# <
+# HAL interrupt handling
+# A number of configuration options related to interrupt
+# handling are common to most or all HAL packages, even though
+# the implementations will vary from architecture to
+# architecture.
+#
+cdl_component CYGPKG_HAL_COMMON_INTERRUPTS {
+ # There is no associated value.
+};
+
+# >
+# Use separate stack for interrupts
+# When an interrupt occurs this interrupt can be handled either
+# on the current stack or on a separate stack maintained by the
+# HAL. Using a separate stack requires a small number of extra
+# instructions in the interrupt handling code, but it has the
+# advantage that it is no longer necessary to allow extra space
+# in every thread stack for the interrupt handlers. The amount
+# of extra space required depends on the interrupt handlers
+# that are being used.
+#
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # package CYGPKG_REDBOOT
+ # Requires: CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK == 0
+};
+
+# Interrupt stack size
+# This configuration option specifies the stack size in bytes
+# for the interrupt stack. Typically this should be a multiple
+# of 16, but the exact requirements will vary from architecture
+# to architecture. The interrupt stack serves two separate
+# purposes. It is used as the stack during system
+# initialization. In addition, if the interrupt system is
+# configured to use a separate stack then all interrupts will
+# be processed on this stack. The exact memory requirements
+# will vary from application to application, and will depend
+# heavily on whether or not other interrupt-related options,
+# for example nested interrupts, are enabled. On most targets,
+# in a configuration with no kernel this stack will also be
+# the stack used to invoke the application, and must obviously
+# be appropriately large in that case.
+#
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 32768
+ # value_source default
+ # Default value: CYGPKG_KERNEL ? 4096 : 32768
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 32768
+ # Legal values: 128 to 1048576
+};
+
+# Allow nested interrupts
+# When an interrupt occurs the HAL interrupt handling code can
+# either leave interrupts disabled for the duration of the
+# interrupt handling code, or by doing some extra work it can
+# reenable interrupts before invoking the interrupt handler and
+# thus allow nested interrupts to happen. If all the interrupt
+# handlers being used are small and do not involve any loops
+# then it is usually better to disallow nested interrupts.
+# However if any of the interrupt handlers are more complicated
+# than nested interrupts will usually be required.
+#
+cdl_option CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Save minimum context on interrupt
+# The HAL interrupt handling code can exploit the calling conventions
+# defined for a given architecture to reduce the amount of state
+# that has to be saved. Generally this improves performance and
+# reduces code size. However it can make source-level debugging
+# more difficult.
+#
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # Requires: ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+};
+
+# Chain all interrupts together
+# Interrupts can be attached to vectors either singly, or be
+# chained together. The latter is necessary if there is no way
+# of discovering which device has interrupted without
+# inspecting the device itself. It can also reduce the amount
+# of RAM needed for interrupt decoding tables and code.
+#
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Ignore spurious [fleeting] interrupts
+# On some hardware, interrupt sources may not be de-bounced or
+# de-glitched. Rather than try to handle these interrupts (no
+# handling may be possible), this option allows the HAL to simply
+# ignore them. In most cases, if the interrupt is real it will
+# reoccur in a detectable form.
+#
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# HAL context switch support
+# A number of configuration options related to thread contexts
+# are common to most or all HAL packages, even though the
+# implementations will vary from architecture to architecture.
+#
+cdl_component CYGPKG_HAL_COMMON_CONTEXT {
+ # There is no associated value.
+
+ # The following properties are affected by this value
+};
+
+# >
+# Use minimum thread context
+# The thread context switch code can exploit the calling
+# conventions defined for a given architecture to reduce the
+# amount of state that has to be saved during a context
+# switch. Generally this improves performance and reduces
+# code size. However it can make source-level debugging more
+# difficult.
+#
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # Requires: ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+};
+
+# <
+# Explicit control over cache behaviour
+# These options let the default behaviour of the caches
+# be easily configurable.
+#
+cdl_component CYGPKG_HAL_CACHE_CONTROL {
+ # There is no associated value.
+};
+
+# >
+# Enable DATA cache on startup
+# Enabling this option will cause the data cache to be enabled
+# as soon as practicable when eCos starts up. One would choose
+# to disable this if the data cache cannot safely be turned on,
+# such as a case where the cache(s) require additional platform
+# specific setup.
+#
+cdl_component CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# DATA cache mode on startup
+# This option controls the mode the cache will be set to
+# when enabled on startup.
+#
+cdl_option CYGSEM_HAL_DCACHE_STARTUP_MODE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value COPYBACK
+ # value_source default
+ # Default value: COPYBACK
+ # Legal values: "COPYBACK" "WRITETHRU"
+};
+
+# <
+# Enable INSTRUCTION cache on startup
+# Enabling this option will cause the instruction cache to be enabled
+# as soon as practicable when eCos starts up. One would choose
+# to disable this if the instruction cache cannot safely be turned on,
+# such as a case where the cache(s) require additional platform
+# specific setup.
+#
+cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Source-level debugging support
+# If the source level debugger gdb is to be used for debugging
+# application code then it may be necessary to configure in support
+# for this in the HAL.
+#
+cdl_component CYGPKG_HAL_DEBUG {
+ # There is no associated value.
+};
+
+# >
+# Support for GDB stubs
+# The HAL implements GDB stubs for the target.
+#
+cdl_interface CYGINT_HAL_DEBUG_GDB_STUBS {
+ # Implemented by CYGPKG_HAL_ARM_TX37KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # ActiveIf: CYGINT_HAL_DEBUG_GDB_STUBS
+ # option CYGBLD_BUILD_REDBOOT_WITH_GDB
+ # ActiveIf: CYGINT_HAL_DEBUG_GDB_STUBS
+};
+
+# Include GDB stubs in HAL
+# This option causes a set of GDB stubs to be included into the
+# system. On some target systems the GDB support will be
+# provided by other means, for example by a ROM monitor. On
+# other targets, especially when building a ROM-booting system,
+# the necessary support has to go into the target library
+# itself. When GDB stubs are include in a configuration, HAL
+# serial drivers must also be included.
+#
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ # ActiveIf constraint: CYGINT_HAL_DEBUG_GDB_STUBS
+ # CYGINT_HAL_DEBUG_GDB_STUBS == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 0
+ # Requires: ! CYGSEM_HAL_USE_ROM_MONITOR
+ # CYGSEM_HAL_USE_ROM_MONITOR == 0
+ # --> 1
+ # Requires: ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ # CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT == 0
+ # --> 1
+ # Requires: ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ # CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM == 0
+ # --> 1
+ # Requires: !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # CYGSEM_HAL_VIRTUAL_VECTOR_DIAG == 1
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # DefaultValue: (CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS || CYG_HAL_STARTUP == "RAM") ? 1 : 0
+ # option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # DefaultValue: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # ActiveIf: CYGSEM_HAL_USE_ROM_MONITOR || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # DefaultValue: !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGBLD_BUILD_COMMON_GDB_STUBS
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGPKG_HAL_GDB_FILEIO
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGHWR_HAL_ARM_DUMP_EXCEPTIONS
+ # Requires: !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGBLD_BUILD_REDBOOT_WITH_GDB
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+};
+
+# Support for external break support in GDB stubs
+# The HAL implements external break (or asynchronous interrupt)
+# in the GDB stubs for the target.
+#
+cdl_interface CYGINT_HAL_DEBUG_GDB_STUBS_BREAK {
+ # Implemented by CYGPKG_HAL_ARM_TX37KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # ActiveIf: CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+};
+
+# Include GDB external break support for stubs
+# This option causes the GDB stub to add a serial interrupt handler
+# which will listen for GDB break packets. This lets you stop the
+# target asynchronously when using GDB, usually by hitting Control+C
+# or pressing the STOP button. This option differs from
+# CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT in that it is used when
+# GDB stubs are present.
+#
+cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT {
+ # ActiveIf constraint: CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+ # CYGINT_HAL_DEBUG_GDB_STUBS_BREAK == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # Requires: !CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # option CYGOPT_HAL_ARM_SYSCALL_GPROF_SUPPORT
+ # ActiveIf: CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT || CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # option CYGBLD_BUILD_REDBOOT_WITH_GDB
+ # Requires: CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+};
+
+# Platform does not support CTRLC
+#
+cdl_interface CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # ActiveIf: CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED == 0
+};
+
+# Include GDB external break support when no stubs
+# This option adds an interrupt handler for the GDB serial line
+# which will listen for GDB break packets. This lets you stop the
+# target asynchronously when using GDB, usually by hitting Control+C
+# or pressing the STOP button. This option differs from
+# CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT in that it is used when the GDB
+# stubs are NOT present.
+#
+cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT {
+ # This option is not active
+ # ActiveIf constraint: CYGSEM_HAL_USE_ROM_MONITOR || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGSEM_HAL_USE_ROM_MONITOR == 0
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+ # ActiveIf constraint: CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED == 0
+ # CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED == 0
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 1
+ # Requires: !CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGOPT_HAL_ARM_SYSCALL_GPROF_SUPPORT
+ # ActiveIf: CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT || CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+};
+
+# Include GDB multi-threading debug support
+# This option enables some extra HAL code which is needed
+# to support multi-threaded source level debugging.
+#
+cdl_option CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT {
+ # ActiveIf constraint: CYGSEM_HAL_ROM_MONITOR || CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT
+ # CYGSEM_HAL_ROM_MONITOR == 1
+ # CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT (unknown) == 0
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT
+ # Requires: CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ # option CYGBLD_BUILD_REDBOOT_WITH_THREADS
+ # Requires: CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+};
+
+# Number of times to retry sending a $O packet
+# This option controls the number of attempts that eCos programs
+# will make to send a $O packet to a host GDB process. If it is
+# set non-zero, then the target process will attempt to resend the
+# $O packet data up to this number of retries. Caution: use of
+# this option is not recommended as it can thoroughly confuse the
+# host GDB process.
+#
+cdl_option CYGNUM_HAL_DEBUG_GDB_PROTOCOL_RETRIES {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Timeout period for GDB packets
+# This option controls the time (in milliseconds) that eCos programs
+# will wait for a response when sending packets to a host GDB process.
+# If this time elapses, then the packet will be resent, up to some
+# maximum number of times (CYGNUM_HAL_DEBUG_GDB_PROTOCOL_RETRIES).
+#
+cdl_option CYGNUM_HAL_DEBUG_GDB_PROTOCOL_TIMEOUT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 500
+ # value_source default
+ # Default value: 500
+};
+
+# Location of CRC32 table
+# The stubs use a 1 kilobyte CRC table that can either be pregenerated
+# and placed in ROM, or generated at runtime in RAM. Depending on
+# your memory constraints, one of these options may be better.
+#
+cdl_option CYGDBG_HAL_CRCTABLE_LOCATION {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value RAM
+ # value_source default
+ # Default value: RAM
+ # Legal values: "ROM" "RAM"
+};
+
+# <
+# ROM monitor support
+# Support for ROM monitors can be built in to your application.
+# It may also be relevant to build your application as a ROM monitor
+# itself. Such options are contained here if relevant for your chosen
+# platform. The options and ROM monitors available to choose are
+# platform-dependent.
+#
+cdl_component CYGPKG_HAL_ROM_MONITOR {
+ # There is no associated value.
+
+ # The following properties are affected by this value
+};
+
+# >
+# Target has virtual vector support
+#
+cdl_interface CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT {
+ # Implemented by CYGPKG_HAL_ARM_TX37KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # component CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+ # ActiveIf: CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+};
+
+# Target supports baud rate control via vectors
+# Whether this target supports the __COMMCTL_GETBAUD
+# and __COMMCTL_SETBAUD virtual vector comm control operations.
+#
+cdl_interface CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT {
+ # Implemented by CYGPKG_HAL_ARM_MX37, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_VARIABLE_BAUD_RATE
+ # ActiveIf: CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+};
+
+# Enable use of virtual vector calling interface
+# Virtual vector support allows the HAL to let the ROM
+# monitor handle certain operations. The virtual vector table
+# defines a calling interface between applications running in
+# RAM and the ROM monitor.
+#
+cdl_component CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT {
+ # ActiveIf constraint: CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+ # CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT == 1
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+
+ # The following properties are affected by this value
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+ # package CYGPKG_DEVS_ETH_PHY
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+};
+
+# >
+# Inherit console settings from ROM monitor
+# When this option is set, the application will inherit
+# the console as set up by the ROM monitor. This means
+# that the application will use whatever channel and
+# mangling style was used by the ROM monitor when
+# the application was launched.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE {
+ # This option is not active
+ # ActiveIf constraint: CYGSEM_HAL_USE_ROM_MONITOR
+ # CYGSEM_HAL_USE_ROM_MONITOR == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: !CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS == 1
+ # --> 0
+
+ # The following properties are affected by this value
+ # component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # ActiveIf: !CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE
+ # option CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ # Calculated: !CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE && !CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+};
+
+# Debug channel is configurable
+# This option is a configuration hint - it is enabled
+# when the HAL initialization code will make use
+# of the debug channel configuration option.
+#
+cdl_option CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE {
+ # Calculated value: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS == 1
+ # Flavor: bool
+ # Current value: 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+ # ActiveIf: CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+};
+
+# Console channel is configurable
+# This option is a configuration hint - it is enabled
+# when the HAL initialization code will make use
+# of the console channel configuration option.
+#
+cdl_option CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE {
+ # Calculated value: !CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE && !CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE == 0
+ # CYGDBG_HAL_DIAG_TO_DEBUG_CHAN == 0
+ # Flavor: bool
+ # Current value: 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL
+ # ActiveIf: CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+};
+
+# Initialize whole of virtual vector table
+# This option will cause the whole of the virtual
+# vector table to be initialized with dummy values on
+# startup. When this option is enabled, all the
+# options below must also be enabled - or the
+# table would be empty when the application
+# launches.
+# On targets where older ROM monitors without
+# virtual vector support may still be in use, it is
+# necessary for RAM applictions to initialize the
+# table (since all HAL diagnostics and debug IO
+# happens via the table).
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYG_HAL_STARTUP != "RAM" || !CYGSEM_HAL_USE_ROM_MONITOR
+ # CYG_HAL_STARTUP == ROMRAM
+ # CYGSEM_HAL_USE_ROM_MONITOR == 0
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET == 1
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US == 1
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE == 1
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA == 1
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # ActiveIf: !CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_VERSION
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+};
+
+# Claim virtual vector table entries by default
+# By default most virtual vectors will be claimed by
+# RAM startup configurations, meaning that the RAM
+# application will provide the services. The
+# exception is COMMS support (HAL
+# diagnostics/debugging IO) which is left in the
+# control of the ROM monitor.
+# The reasoning behind this is to get as much of the
+# code exercised during regular development so it
+# is known to be working the few times a new ROM
+# monitor or a ROM production configuration is used
+# - COMMS are excluded only by necessity in order to
+# avoid breaking an existing debugger connections
+# (there may be ways around this).
+# For production RAM configurations this option can
+# be switched off, causing the appliction to rely on
+# the ROM monitor for these services, thus
+# saving some space.
+# Individual vectors may also be left unclaimed,
+# controlled by the below options (meaning that the
+# associated service provided by the ROM monitor
+# will be used).
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT {
+ # This option is not active
+ # ActiveIf constraint: !CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA
+ # DefaultValue: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+};
+
+# Claim reset virtual vectors
+# This option will cause the reset and kill_by_reset
+# virtual vectors to be claimed.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET
+};
+
+# Claim version virtual vectors
+# This option will cause the version
+# virtual vectors to be claimed.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_VERSION {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # --> 1
+};
+
+# Claim delay_us virtual vector
+# This option will cause the delay_us
+# virtual vector to be claimed.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US
+};
+
+# Claim cache virtual vectors
+# This option will cause the cache virtual vectors
+# to be claimed.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE
+};
+
+# Claim data virtual vectors
+# This option will cause the data virtual vectors
+# to be claimed. At present there is only one, used
+# by the RedBoot ethernet driver to share diag output.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DEFAULT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA
+};
+
+# Claim comms virtual vectors
+# This option will cause the communication tables
+# that are part of the virtual vectors mechanism to
+# be claimed. Note that doing this may cause an
+# existing ROM monitor communication connection to
+# be closed. For this reason, the option is disabled
+# per default for normal application
+# configurations.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE == 1
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # Requires: !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE
+ # DefaultValue: !CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # option CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ # Calculated: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+};
+
+# Do diagnostic IO via virtual vector table
+# All HAL IO happens via the virtual vector table / comm
+# tables when those tables are supported by the HAL.
+# If so desired, the low-level IO functions can
+# still be provided by the RAM application by
+# enabling the CLAIM_COMMS option.
+#
+cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_DIAG {
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+
+ # The following properties are affected by this value
+ # component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # ActiveIf: CYGPKG_HAL_ARM || CYGPKG_HAL_POWERPC_MPC8xx || CYGPKG_HAL_V85X_V850 || CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # Requires: !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
+};
+
+# <
+# Behave as a ROM monitor
+# Enable this option if this program is to be used as a ROM monitor,
+# i.e. applications will be loaded into RAM on the TX37 module, and this
+# ROM monitor may process exceptions or interrupts generated from the
+# application. This enables features such as utilizing a separate
+# interrupt stack when exceptions are generated.
+#
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+ # Requires: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGBLD_ARM_ENABLE_THUMB_INTERWORK
+ # DefaultValue: (CYGHWR_THUMB || CYGSEM_HAL_ROM_MONITOR)
+ # option CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ # ActiveIf: CYGSEM_HAL_ROM_MONITOR || CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT
+ # option CYGPRI_REDBOOT_ROM_MONITOR
+ # Requires: CYGSEM_HAL_ROM_MONITOR
+};
+
+# Work with a ROM monitor
+# Support can be enabled for different varieties of ROM monitor.
+# This support changes various eCos semantics such as the encoding
+# of diagnostic output, or the overriding of hardware interrupt
+# vectors.
+# Firstly there is "Generic" support which prevents the HAL
+# from overriding the hardware vectors that it does not use, to
+# instead allow an installed ROM monitor to handle them. This is
+# the most basic support which is likely to be common to most
+# implementations of ROM monitor.
+# "GDB_stubs" provides support when GDB stubs are included in
+# the ROM monitor or boot ROM.
+#
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 0 0
+ # Legal values: "Generic" "GDB_stubs"
+ # Requires: CYG_HAL_STARTUP == "RAM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 0
+
+ # The following properties are affected by this value
+ # option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # Requires: ! CYGSEM_HAL_USE_ROM_MONITOR
+ # option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # ActiveIf: CYGSEM_HAL_USE_ROM_MONITOR || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE
+ # ActiveIf: CYGSEM_HAL_USE_ROM_MONITOR
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # DefaultValue: CYG_HAL_STARTUP != "RAM" || !CYGSEM_HAL_USE_ROM_MONITOR
+};
+
+# <
+# Platform defined I/O channels.
+# Platforms which provide additional I/O channels can implement
+# this interface, indicating that the function plf_if_init()
+# needs to be called.
+#
+cdl_interface CYGINT_HAL_PLF_IF_INIT {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+};
+
+# Platform IDE I/O support.
+# Platforms which provide IDE controllers can implement
+# this interface, indicating that IDE I/O macros are
+# available.
+#
+cdl_interface CYGINT_HAL_PLF_IF_IDE {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # component CYGSEM_REDBOOT_DISK_IDE
+ # ActiveIf: CYGINT_HAL_PLF_IF_IDE != 0
+};
+
+# File I/O operations via GDB
+# This option enables support for various file I/O
+# operations using the GDB remote protocol to communicate
+# with GDB. The operations are then performed on the
+# debugging host by proxy. These operations are only
+# currently available by using a system call interface
+# to RedBoot. This may change in the future.
+#
+cdl_option CYGPKG_HAL_GDB_FILEIO {
+ # This option is not active
+ # ActiveIf constraint: CYGSEM_REDBOOT_BSP_SYSCALLS
+ # CYGSEM_REDBOOT_BSP_SYSCALLS == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+};
+
+# Build Compiler sanity checking tests
+# Enabling this option causes compiler tests to be built.
+#
+cdl_option CYGPKG_HAL_BUILD_COMPILER_TESTS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # component CYGPKG_HAL_TESTS
+ # Calculated: "tests/context tests/basic"
+ # . ((!CYGINT_HAL_TESTS_NO_CACHES) ? " tests/cache" : "")
+ # . ((CYGPKG_HAL_BUILD_COMPILER_TESTS) ? " tests/cpp1 tests/vaargs" : "")
+ # . ((!CYGVAR_KERNEL_COUNTERS_CLOCK) ? " tests/intr" : "")
+};
+
+# Common HAL tests
+# This option specifies the set of tests for the common HAL.
+#
+cdl_component CYGPKG_HAL_TESTS {
+ # Calculated value: "tests/context tests/basic"
+ # . ((!CYGINT_HAL_TESTS_NO_CACHES) ? " tests/cache" : "")
+ # . ((CYGPKG_HAL_BUILD_COMPILER_TESTS) ? " tests/cpp1 tests/vaargs" : "")
+ # . ((!CYGVAR_KERNEL_COUNTERS_CLOCK) ? " tests/intr" : "")
+ # CYGINT_HAL_TESTS_NO_CACHES == 0
+ # CYGPKG_HAL_BUILD_COMPILER_TESTS == 0
+ # CYGVAR_KERNEL_COUNTERS_CLOCK (unknown) == 0
+ # Flavor: data
+ # Current_value: tests/context tests/basic tests/cache tests/intr
+};
+
+# >
+# Interface for cache presence
+# Some architectures and/or platforms do not have caches. By
+# implementing this interface, these can disable the various
+# cache-related tests.
+#
+cdl_interface CYGINT_HAL_TESTS_NO_CACHES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+
+ # The following properties are affected by this value
+ # component CYGPKG_HAL_TESTS
+ # Calculated: "tests/context tests/basic"
+ # . ((!CYGINT_HAL_TESTS_NO_CACHES) ? " tests/cache" : "")
+ # . ((CYGPKG_HAL_BUILD_COMPILER_TESTS) ? " tests/cpp1 tests/vaargs" : "")
+ # . ((!CYGVAR_KERNEL_COUNTERS_CLOCK) ? " tests/intr" : "")
+};
+
+# <
+# ARM architecture
+# The ARM architecture HAL package provides generic
+# support for this processor architecture. It is also
+# necessary to select a specific target platform HAL
+# package.
+#
+cdl_package CYGPKG_HAL_ARM {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # ActiveIf: CYGPKG_HAL_ARM || CYGPKG_HAL_POWERPC_MPC8xx || CYGPKG_HAL_V85X_V850 || CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+ # interface CYGINT_REDBOOT_ARM_FLASH_SIB_SUPPORTED
+ # ActiveIf: CYGPKG_HAL_ARM
+};
+
+# >
+# The CPU architecture supports THUMB mode
+#
+cdl_interface CYGINT_HAL_ARM_THUMB_ARCH {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_THUMB
+ # ActiveIf: CYGINT_HAL_ARM_THUMB_ARCH != 0
+ # option CYGBLD_ARM_ENABLE_THUMB_INTERWORK
+ # ActiveIf: CYGINT_HAL_ARM_THUMB_ARCH != 0
+};
+
+# Enable Thumb instruction set
+# Enable use of the Thumb instruction set.
+#
+cdl_option CYGHWR_THUMB {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_HAL_ARM_THUMB_ARCH != 0
+ # CYGINT_HAL_ARM_THUMB_ARCH == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGBLD_ARM_ENABLE_THUMB_INTERWORK
+ # DefaultValue: (CYGHWR_THUMB || CYGSEM_HAL_ROM_MONITOR)
+};
+
+# Enable Thumb interworking compiler option
+# This option controls the use of -mthumb-interwork in the
+# compiler flags. It defaults enabled in Thumb or ROM monitor
+# configurations, but can be overridden for reduced memory
+# footprint where interworking is not a requirement.
+#
+cdl_option CYGBLD_ARM_ENABLE_THUMB_INTERWORK {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_HAL_ARM_THUMB_ARCH != 0
+ # CYGINT_HAL_ARM_THUMB_ARCH == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: (CYGHWR_THUMB || CYGSEM_HAL_ROM_MONITOR)
+ # CYGHWR_THUMB == 0
+ # CYGSEM_HAL_ROM_MONITOR == 1
+ # --> 1
+};
+
+# The platform and architecture supports Big Endian operation
+#
+cdl_interface CYGINT_HAL_ARM_BIGENDIAN {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_BIGENDIAN
+ # ActiveIf: CYGINT_HAL_ARM_BIGENDIAN != 0
+};
+
+# Use big-endian mode
+# Use the CPU in big-endian mode.
+#
+cdl_option CYGHWR_HAL_ARM_BIGENDIAN {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_HAL_ARM_BIGENDIAN != 0
+ # CYGINT_HAL_ARM_BIGENDIAN == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# The platform uses a processor with an ARM7 core
+#
+cdl_interface CYGINT_HAL_ARM_ARCH_ARM7 {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # LegalValues: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" : ""
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" : ""
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" : ""
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" : ""
+ # ""
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # DefaultValue: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" :
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" :
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" :
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" :
+ # "unknown"
+};
+
+# The platform uses a processor with an ARM9 core
+#
+cdl_interface CYGINT_HAL_ARM_ARCH_ARM9 {
+ # Implemented by CYGPKG_HAL_ARM_MX37, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # LegalValues: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" : ""
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" : ""
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" : ""
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" : ""
+ # ""
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # DefaultValue: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" :
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" :
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" :
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" :
+ # "unknown"
+};
+
+# The platform uses a processor with a StrongARM core
+#
+cdl_interface CYGINT_HAL_ARM_ARCH_STRONGARM {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # LegalValues: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" : ""
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" : ""
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" : ""
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" : ""
+ # ""
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # DefaultValue: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" :
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" :
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" :
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" :
+ # "unknown"
+};
+
+# The platform uses a processor with a XScale core
+#
+cdl_interface CYGINT_HAL_ARM_ARCH_XSCALE {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # LegalValues: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" : ""
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" : ""
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" : ""
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" : ""
+ # ""
+ # option CYGHWR_HAL_ARM_CPU_FAMILY
+ # DefaultValue: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" :
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" :
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" :
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" :
+ # "unknown"
+};
+
+# ARM CPU family
+# It is possible to optimize code for different
+# ARM CPU families. This option selects which CPU to
+# optimize for on boards that support multiple CPU types.
+#
+cdl_option CYGHWR_HAL_ARM_CPU_FAMILY {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ARM9
+ # value_source default
+ # Default value: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" :
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" :
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" :
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" :
+ # "unknown"
+ # CYGINT_HAL_ARM_ARCH_ARM7 == 0
+ # CYGINT_HAL_ARM_ARCH_ARM9 == 1
+ # CYGINT_HAL_ARM_ARCH_STRONGARM == 0
+ # CYGINT_HAL_ARM_ARCH_XSCALE == 0
+ # --> ARM9
+ # Legal values: (CYGINT_HAL_ARM_ARCH_ARM7 != 0) ? "ARM7" : ""
+ # (CYGINT_HAL_ARM_ARCH_ARM9 != 0) ? "ARM9" : ""
+ # (CYGINT_HAL_ARM_ARCH_STRONGARM != 0) ? "StrongARM" : ""
+ # (CYGINT_HAL_ARM_ARCH_XSCALE != 0) ? "XScale" : ""
+ # ""
+ # CYGINT_HAL_ARM_ARCH_ARM7 == 0
+ # CYGINT_HAL_ARM_ARCH_ARM9 == 1
+ # CYGINT_HAL_ARM_ARCH_STRONGARM == 0
+ # CYGINT_HAL_ARM_ARCH_XSCALE == 0
+};
+
+# Provide diagnostic dump for exceptions
+# Print messages about hardware exceptions, including
+# raw exception frame dump and register contents.
+#
+cdl_option CYGHWR_HAL_ARM_DUMP_EXCEPTIONS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 1
+};
+
+# Process all exceptions with the eCos application
+# Normal RAM-based programs which do not include GDB stubs
+# defer processing of the illegal instruction exception to GDB.
+# Setting this options allows the program to explicitly handle
+# the illegal instruction exception itself. Note: this will
+# prevent the use of GDB to debug the application as breakpoints
+# will no longer work.
+#
+cdl_option CYGIMP_HAL_PROCESS_ALL_EXCEPTIONS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Support GDB thread operations via ICE/Multi-ICE
+# Allow GDB to get thread information via the ICE/Multi-ICE
+# connection.
+#
+cdl_option CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT == 1
+ # --> 1
+ # Requires: CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT
+ # CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT (unknown) == 0
+ # --> 0
+};
+
+# Support for 'gprof' callbacks
+# The ARM HAL provides the macro for 'gprof' callbacks from RedBoot
+# to acquire the interrupt-context PC and SP, when this option is
+# active.
+#
+cdl_option CYGOPT_HAL_ARM_SYSCALL_GPROF_SUPPORT {
+ # This option is not active
+ # ActiveIf constraint: CYGSEM_REDBOOT_BSP_SYSCALLS
+ # CYGSEM_REDBOOT_BSP_SYSCALLS == 0
+ # --> 0
+ # ActiveIf constraint: CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT || CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT == 0
+ # CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT == 0
+ # --> 0
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+};
+
+# Accept exceptions and irq's occurring in user mode
+# For standalone Redboot based programs running in user mode.
+#
+cdl_option CYGOPT_HAL_ARM_WITH_USER_MODE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Preserve svc spsr before returning to svc mode
+# This option secures exception and breakpoint processing
+# triggered during execution of application specific SWI
+# handlers.
+#
+cdl_option CYGOPT_HAL_ARM_PRESERVE_SVC_SPSR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Linker script
+#
+cdl_option CYGBLD_LINKER_SCRIPT {
+ # Calculated value: "src/arm.ld"
+ # Flavor: data
+ # Current_value: src/arm.ld
+};
+
+# Implementations of hal_arm_mem_real_region_top()
+#
+cdl_interface CYGINT_HAL_ARM_MEM_REAL_REGION_TOP {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+};
+
+# Freescale SoC architecture
+# This HAL variant package provides generic
+# support for the Freescale SoC. It is also
+# necessary to select a specific target platform HAL
+# package.
+#
+cdl_package CYGPKG_HAL_ARM_MX37 {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+};
+
+# >
+# Processor clock rate
+# The processor can run at various frequencies.
+# These values are expressed in KHz. Note that there are
+# several steppings of the rate to run at different
+# maximum frequencies. Check the specs to make sure that your
+# particular processor can run at the rate you select here.
+#
+cdl_option CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK {
+ # This option is not active
+ # ActiveIf constraint: CYG_HAL_STARTUP == "ROM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 0
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 150000
+ # value_source default
+ # Default value: CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT ?
+ # CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT : 150000
+ # CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT (unknown) == 0
+ # CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT (unknown) == 0
+ # --> 150000
+ # Legal values: 150000 200000
+};
+
+# Real-time clock constants
+#
+cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+ # There is no associated value.
+};
+
+# >
+# Real-time clock numerator
+#
+cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+ # Calculated value: 1000000000
+ # Flavor: data
+ # Current_value: 1000000000
+};
+
+# Real-time clock denominator
+# This option selects the heartbeat rate for the real-time clock.
+# The rate is specified in ticks per second. Change this value
+# with caution - too high and your system will become saturated
+# just handling clock interrupts, too low and some operations
+# such as thread scheduling may become sluggish.
+#
+cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 100
+ # value_source default
+ # Default value: 100
+
+ # The following properties are affected by this value
+ # option CYGNUM_HAL_RTC_PERIOD
+ # Calculated: (3686400/CYGNUM_HAL_RTC_DENOMINATOR)
+};
+
+# Real-time clock period
+#
+cdl_option CYGNUM_HAL_RTC_PERIOD {
+ # Calculated value: (3686400/CYGNUM_HAL_RTC_DENOMINATOR)
+ # CYGNUM_HAL_RTC_DENOMINATOR == 100
+ # Flavor: data
+ # Current_value: 36864
+};
+
+# <
+# UART1 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART1 {
+ # Implemented by CYGPKG_HAL_ARM_TX37KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+};
+
+# UART2 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART2 {
+ # Implemented by CYGPKG_HAL_ARM_TX37KARO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+};
+
+# UART3 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART3 {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+};
+
+# UART4 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART4 {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+};
+
+# UART5 available as diagnostic/debug channel
+# The chip has multiple serial channels which may be
+# used for different things on different platforms. This
+# interface allows a platform to indicate that the specified
+# serial port can be used as a diagnostic and/or debug channel.
+#
+cdl_interface CYGHWR_HAL_ARM_SOC_UART5 {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+};
+
+# Ka-Ro TX37 module
+# This HAL platform package provides generic
+# support for the Ka-Ro electronics TX37 module.
+#
+cdl_package CYGPKG_HAL_ARM_TX37KARO {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGINT_ISO_CTYPE
+ # CYGINT_ISO_CTYPE == 1
+ # --> 1
+ # Requires: CYGBLD_BUILD_REDBOOT == 1
+ # CYGBLD_BUILD_REDBOOT == 1
+ # --> 1
+};
+
+# >
+# Startup type
+# The only startup type allowed is ROMRAM, since this will allow
+# the program to exist in ROM, but be copied to RAM during startup
+# which is required to boot from NAND flash.
+#
+cdl_component CYG_HAL_STARTUP {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ROMRAM
+ # value_source default
+ # Default value: ROMRAM
+ # Legal values: "ROMRAM"
+
+ # The following properties are affected by this value
+ # option CYGSEM_HAL_ROM_MONITOR
+ # Requires: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+ # option CYGSEM_HAL_ROM_MONITOR
+ # Requires: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+ # option CYGSEM_HAL_USE_ROM_MONITOR
+ # DefaultValue: CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0
+ # option CYGSEM_HAL_USE_ROM_MONITOR
+ # Requires: CYG_HAL_STARTUP == "RAM"
+ # option CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK
+ # ActiveIf: CYG_HAL_STARTUP == "ROM"
+ # option CYGSEM_HAL_INSTALL_MMU_TABLES
+ # DefaultValue: CYG_HAL_STARTUP != "RAM"
+ # component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
+ # DefaultValue: (CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS || CYG_HAL_STARTUP == "RAM") ? 1 : 0
+ # option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
+ # DefaultValue: CYG_HAL_STARTUP != "RAM" || !CYGSEM_HAL_USE_ROM_MONITOR
+ # option CYGBLD_BUILD_REDBOOT_WITH_THREADS
+ # ActiveIf: CYG_HAL_STARTUP != "RAM"
+ # option CYGPRI_REDBOOT_ROM_MONITOR
+ # ActiveIf: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+ # option CYGPRI_REDBOOT_ROM_MONITOR
+ # ActiveIf: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+};
+
+# Diagnostic serial port baud rate
+# This option selects the baud rate used for the console port.
+# Note: this should match the value chosen for the GDB port if the
+# console and GDB port are the same.
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 115200
+ # value_source default
+ # Default value: 115200
+ # Legal values: 9600 19200 38400 57600 115200
+};
+
+# GDB serial port baud rate
+# This option selects the baud rate used for the GDB port.
+# Note: this should match the value chosen for the console port if the
+# console and GDB port are the same.
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 115200
+ # value_source default
+ # Default value: 115200
+ # Legal values: 9600 19200 38400 57600 115200
+};
+
+# Number of communication channels on the TX37
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ # Calculated value: 2
+ # Flavor: data
+ # Current_value: 2
+
+ # The following properties are affected by this value
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+ # LegalValues: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ # LegalValues: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL
+ # LegalValues: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+};
+
+# Debug serial port
+# The TX37 provides access to two serial ports. This option
+# chooses which port will be used to connect to a host
+# running GDB.
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ # ActiveIf constraint: CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ # CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE == 1
+ # --> 1
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ # CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS == 2
+};
+
+# Default console channel.
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+ # Calculated value: 0
+ # Flavor: data
+ # Current_value: 0
+ # Legal values: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ # CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS == 2
+
+ # The following properties are affected by this value
+ # option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL
+ # DefaultValue: CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+};
+
+# Console serial port
+# The TX37 provides access to two serial ports. This option
+# chooses which port will be used for console output.
+#
+cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ # ActiveIf constraint: CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ # CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE == 1
+ # --> 1
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ # CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT == 0
+ # --> 0
+ # Legal values: 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ # CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS == 2
+};
+
+# Ka-Ro electronics TX37 module build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_HAL_ARM_TX37_OPTIONS {
+ # There is no associated value.
+ # Requires: CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0
+ # CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0
+ # --> 1
+};
+
+# >
+# SDRAM size
+# This option specifies the SDRAM size of the TX37 module.
+#
+cdl_option CYGNUM_HAL_ARM_TX37_SDRAM_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x08000000
+ # value_source default
+ # Default value: 0x08000000
+ # Legal values: 0x08000000 0x04000000
+};
+
+# Enable low level debugging with LED
+# This option enables low level debugging by blink codes
+# of the LED on STK5.
+#
+cdl_option CYGOPT_HAL_ARM_TX37_DEBUG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: false
+ # false (unknown) == 0
+ # --> 0
+};
+
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the TX37 HAL. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_HAL_ARM_TX37_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the TX37 HAL. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_HAL_ARM_TX37_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# <
+# Memory layout
+#
+cdl_component CYGHWR_MEMORY_LAYOUT {
+ # Calculated value: "arm_tx37_romram"
+ # Flavor: data
+ # Current_value: arm_tx37_romram
+};
+
+# >
+# Memory layout linker script fragment
+#
+cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ # Calculated value: "<pkgconf/mlt_arm_tx37_romram.ldi>"
+ # Flavor: data
+ # Current_value: <pkgconf/mlt_arm_tx37_romram.ldi>
+};
+
+# Memory layout header file
+#
+cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ # Calculated value: "<pkgconf/mlt_arm_tx37_romram.h>"
+ # Flavor: data
+ # Current_value: <pkgconf/mlt_arm_tx37_romram.h>
+};
+
+# <
+# <
+# <
+# <
+# <
+# Infrastructure
+# Common types and useful macros.
+# Tracing and assertion facilities.
+# Package startup options.
+#
+cdl_package CYGPKG_INFRA {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # package CYGPKG_HAL
+ # Requires: CYGPKG_INFRA
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGPKG_INFRA
+};
+
+# >
+# Asserts & Tracing
+# The eCos source code contains a significant amount of
+# internal debugging support, in the form of assertions and
+# tracing.
+# Assertions check at runtime that various conditions are as
+# expected; if not, execution is halted.
+# Tracing takes the form of text messages that are output
+# whenever certain events occur, or whenever functions are
+# called or return.
+# The most important property of these checks and messages is
+# that they are not required for the program to run.
+# It is prudent to develop software with assertions enabled,
+# but disable them when making a product release, thus
+# removing the overhead of that checking.
+# It is possible to enable assertions and tracing
+# independently.
+# There are also options controlling the exact behaviour of
+# the assertion and tracing facilities, thus giving users
+# finer control over the code and data size requirements.
+#
+cdl_component CYGPKG_INFRA_DEBUG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGNUM_INFRA_EMPTY_DELETE_THRESHOLD
+ # ActiveIf: CYGPKG_INFRA_DEBUG
+};
+
+# >
+# Use asserts
+# If this option is defined, asserts in the code are tested.
+# Assert functions (CYG_ASSERT()) are defined in
+# 'include/cyg/infra/cyg_ass.h' within the 'install' tree.
+# If it is not defined, these result in no additional
+# object code and no checking of the asserted conditions.
+#
+cdl_component CYGDBG_USE_ASSERTS {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: 1 == CYGINT_INFRA_DEBUG_TRACE_IMPL
+ # CYGINT_INFRA_DEBUG_TRACE_IMPL == 0
+ # --> 0
+
+ # The following properties are affected by this value
+ # option CYGDBG_MEMALLOC_ALLOCATOR_DLMALLOC_DEBUG
+ # Requires: CYGDBG_USE_ASSERTS
+ # option CYGDBG_MEMALLOC_ALLOCATOR_DLMALLOC_DEBUG
+ # DefaultValue: 0 != CYGDBG_USE_ASSERTS
+};
+
+# >
+# Preconditions
+# This option allows individual control of preconditions.
+# A precondition is one type of assert, which it is
+# useful to control separately from more general asserts.
+# The function is CYG_PRECONDITION(condition,msg).
+#
+cdl_option CYGDBG_INFRA_DEBUG_PRECONDITIONS {
+ # This option is not active
+ # The parent CYGDBG_USE_ASSERTS is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Postconditions
+# This option allows individual control of postconditions.
+# A postcondition is one type of assert, which it is
+# useful to control separately from more general asserts.
+# The function is CYG_POSTCONDITION(condition,msg).
+#
+cdl_option CYGDBG_INFRA_DEBUG_POSTCONDITIONS {
+ # This option is not active
+ # The parent CYGDBG_USE_ASSERTS is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Loop invariants
+# This option allows individual control of loop invariants.
+# A loop invariant is one type of assert, which it is
+# useful to control separately from more general asserts,
+# particularly since a loop invariant is typically evaluated
+# a great many times when used correctly.
+# The function is CYG_LOOP_INVARIANT(condition,msg).
+#
+cdl_option CYGDBG_INFRA_DEBUG_LOOP_INVARIANTS {
+ # This option is not active
+ # The parent CYGDBG_USE_ASSERTS is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Use assert text
+# All assertions within eCos contain a text message
+# which should give some information about the condition
+# being tested.
+# These text messages will end up being embedded in the
+# application image and hence there is a significant penalty
+# in terms of image size.
+# It is possible to suppress the use of these messages by
+# disabling this option.
+# This results in smaller code size, but there is less
+# human-readable information if an assertion actually gets
+# triggered.
+#
+cdl_option CYGDBG_INFRA_DEBUG_ASSERT_MESSAGE {
+ # This option is not active
+ # The parent CYGDBG_USE_ASSERTS is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Use tracing
+# If this option is defined, tracing operations
+# result in output or logging, depending on other options.
+# This may have adverse effects on performance, if the time
+# taken to output message overwhelms the available CPU
+# power or output bandwidth.
+# Trace functions (CYG_TRACE()) are defined in
+# 'include/cyg/infra/cyg_trac.h' within the 'install' tree.
+# If it is not defined, these result in no additional
+# object code and no trace information.
+#
+cdl_component CYGDBG_USE_TRACING {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: 1 == CYGINT_INFRA_DEBUG_TRACE_IMPL
+ # CYGINT_INFRA_DEBUG_TRACE_IMPL == 0
+ # --> 0
+
+ # The following properties are affected by this value
+ # option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_SIZE
+ # ActiveIf: CYGDBG_USE_TRACING
+ # option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_WRAP
+ # ActiveIf: CYGDBG_USE_TRACING
+ # option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_HALT
+ # ActiveIf: CYGDBG_USE_TRACING
+ # option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_PRINT
+ # ActiveIf: CYGDBG_USE_TRACING
+ # option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_PRINT_ON_ASSERT
+ # ActiveIf: CYGDBG_USE_TRACING
+};
+
+# >
+# Trace function reports
+# This option allows individual control of
+# function entry/exit tracing, independent of
+# more general tracing output.
+# This may be useful to remove clutter from a
+# trace log.
+#
+cdl_option CYGDBG_INFRA_DEBUG_FUNCTION_REPORTS {
+ # This option is not active
+ # The parent CYGDBG_USE_TRACING is not active
+ # The parent CYGDBG_USE_TRACING is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Use trace text
+# All trace calls within eCos contain a text message
+# which should give some information about the circumstances.
+# These text messages will end up being embedded in the
+# application image and hence there is a significant penalty
+# in terms of image size.
+# It is possible to suppress the use of these messages by
+# disabling this option.
+# This results in smaller code size, but there is less
+# human-readable information available in the trace output,
+# possibly only filenames and line numbers.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_MESSAGE {
+ # This option is not active
+ # The parent CYGDBG_USE_TRACING is not active
+ # The parent CYGDBG_USE_TRACING is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Trace output implementations
+#
+cdl_interface CYGINT_INFRA_DEBUG_TRACE_IMPL {
+ # Implemented by CYGDBG_INFRA_DEBUG_TRACE_ASSERT_NULL, inactive, disabled
+ # Implemented by CYGDBG_INFRA_DEBUG_TRACE_ASSERT_SIMPLE, inactive, disabled
+ # Implemented by CYGDBG_INFRA_DEBUG_TRACE_ASSERT_FANCY, inactive, disabled
+ # Implemented by CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER, inactive, enabled
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # component CYGDBG_USE_ASSERTS
+ # Requires: 1 == CYGINT_INFRA_DEBUG_TRACE_IMPL
+ # component CYGDBG_USE_TRACING
+ # Requires: 1 == CYGINT_INFRA_DEBUG_TRACE_IMPL
+};
+
+# Null output
+# A null output module which is useful when
+# debugging interactively; the output routines
+# can be breakpointed rather than have them actually
+# 'print' something.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_ASSERT_NULL {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Simple output
+# An output module which produces simple output
+# from tracing and assertion events.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_ASSERT_SIMPLE {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Fancy output
+# An output module which produces fancy output
+# from tracing and assertion events.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_ASSERT_FANCY {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Buffered tracing
+# An output module which buffers output
+# from tracing and assertion events. The stored
+# messages are output when an assert fires, or
+# CYG_TRACE_PRINT() (defined in <cyg/infra/cyg_trac.h>)
+# is called.
+# Of course, there will only be stored messages
+# if tracing per se (CYGDBG_USE_TRACING)
+# is enabled above.
+#
+cdl_component CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Trace buffer size
+# The size of the trace buffer. This counts the number
+# of trace records stored. When the buffer fills it
+# either wraps, stops recording, or generates output.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_SIZE {
+ # This option is not active
+ # The parent CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER is not active
+ # ActiveIf constraint: CYGDBG_USE_TRACING
+ # CYGDBG_USE_TRACING == 0
+ # --> 0
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 32
+ # value_source default
+ # Default value: 32
+ # Legal values: 5 to 65535
+};
+
+# Wrap trace buffer when full
+# When the trace buffer has filled with records it
+# starts again at the beginning. Hence only the last
+# CYGDBG_INFRA_DEBUG_TRACE_BUFFER_SIZE messages will
+# be recorded.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_WRAP {
+ # This option is not active
+ # The parent CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER is not active
+ # ActiveIf constraint: CYGDBG_USE_TRACING
+ # CYGDBG_USE_TRACING == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Halt trace buffer when full
+# When the trace buffer has filled with records it
+# stops recording. Hence only the first
+# CYGDBG_INFRA_DEBUG_TRACE_BUFFER_SIZE messages will
+# be recorded.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_HALT {
+ # This option is not active
+ # The parent CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER is not active
+ # ActiveIf constraint: CYGDBG_USE_TRACING
+ # CYGDBG_USE_TRACING == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Print trace buffer when full
+# When the trace buffer has filled with records it
+# prints the contents of the buffer. The buffer is then
+# emptied and the system continues.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_PRINT {
+ # This option is not active
+ # The parent CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER is not active
+ # ActiveIf constraint: CYGDBG_USE_TRACING
+ # CYGDBG_USE_TRACING == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Print trace buffer on assert fail
+# When an assertion fails the trace buffer will be
+# printed to the default diagnostic device.
+#
+cdl_option CYGDBG_INFRA_DEBUG_TRACE_BUFFER_PRINT_ON_ASSERT {
+ # This option is not active
+ # The parent CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER is not active
+ # ActiveIf constraint: CYGDBG_USE_TRACING
+ # CYGDBG_USE_TRACING == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Use function names
+# All trace and assert calls within eCos contain a
+# reference to the builtin macro '__PRETTY_FUNCTION__',
+# which evaluates to a string containing
+# the name of the current function.
+# This is useful when reading a trace log.
+# It is possible to suppress the use of the function name
+# by disabling this option.
+# This results in smaller code size, but there is less
+# human-readable information available in the trace output,
+# possibly only filenames and line numbers.
+#
+cdl_option CYGDBG_INFRA_DEBUG_FUNCTION_PSEUDOMACRO {
+ # This option is not active
+ # The parent CYGPKG_INFRA_DEBUG is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Startup options
+# Some packages require a startup routine to be called.
+# This can be carried out by application code, by supplying
+# a routine called cyg_package_start() which calls the
+# appropriate package startup routine(s).
+# Alternatively, this routine can be constructed automatically
+# and configured to call the startup routines of your choice.
+#
+cdl_component CYGPKG_INFRA_STARTUP {
+ # There is no associated value.
+};
+
+# >
+# Start uITRON subsystem
+# Generate a call to initialize the
+# uITRON compatibility subsystem
+# within the system version of cyg_package_start().
+# This enables compatibility with uITRON.
+# You must configure uITRON with the correct tasks before
+# starting the uItron subsystem.
+# If this is disabled, and you want to use uITRON,
+# you must call cyg_uitron_start() from your own
+# cyg_package_start() or cyg_userstart().
+#
+cdl_option CYGSEM_START_UITRON_COMPATIBILITY {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_UITRON
+ # CYGPKG_UITRON (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGPKG_UITRON
+ # CYGPKG_UITRON (unknown) == 0
+ # --> 0
+};
+
+# <
+# Smaller slower memcpy()
+# Enabling this option causes the implementation of
+# the standard memcpy() routine to reduce code
+# size at the expense of execution speed. This
+# option is automatically enabled with the use of
+# the -Os option to the compiler. Also note that
+# the compiler will try to use its own builtin
+# version of memcpy() if possible, ignoring the
+# implementation in this package, unless given
+# the -fno-builtin compiler option.
+#
+cdl_option CYGIMP_INFRA_PREFER_SMALL_TO_FAST_MEMCPY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Smaller slower memset()
+# Enabling this option causes the implementation of
+# the standard memset() routine to reduce code
+# size at the expense of execution speed. This
+# option is automatically enabled with the use of
+# the -Os option to the compiler. Also note that
+# the compiler will try to use its own builtin
+# version of memset() if possible, ignoring the
+# implementation in this package, unless given
+# the -fno-builtin compiler option.
+#
+cdl_option CYGIMP_INFRA_PREFER_SMALL_TO_FAST_MEMSET {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Provide empty C++ delete functions
+# To deal with virtual destructors, where the correct delete()
+# function must be called for the derived class in question, the
+# underlying delete is called when needed, from destructors. This
+# is regardless of whether the destructor is called by delete itself.
+# So there is a reference to delete() from all destructors. The
+# default builtin delete() attempts to call free() if there is
+# one defined. So, if you have destructors, and you have free(),
+# as in malloc() and free(), any destructor counts as a reference
+# to free(). So the dynamic memory allocation code is linked
+# in regardless of whether it gets explicitly called. This
+# increases code and data size needlessly.
+# To defeat this undesirable behaviour, we define empty versions
+# of delete and delete. But doing this prevents proper use
+# of dynamic memory in C++ programs via C++'s new and delete
+# operators.
+# Therefore, this option is provided
+# for explicitly disabling the provision of these empty functions,
+# so that new and delete can be used, if that is what is required.
+#
+cdl_option CYGFUN_INFRA_EMPTY_DELETE_FUNCTIONS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Threshold for valid number of delete calls
+# Some users don't know about the empty delete function and then
+# wonder why their C++ classes are leaking memory. If
+# INFRA_DEBUG is enabled we keep a counter for the number of
+# times delete is called. If it goes above this threshold we throw
+# an assertion failure. This should point heavy users of
+# delete in the right direction without upsetting those who want
+# an empty delete function.
+#
+cdl_option CYGNUM_INFRA_EMPTY_DELETE_THRESHOLD {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_INFRA_DEBUG
+ # CYGPKG_INFRA_DEBUG == 0
+ # --> 0
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 100
+ # value_source default
+ # Default value: 100
+};
+
+# Provide dummy abort() function
+# This option controls the inclusion of a dummy abort() function.
+# Parts of the C and C++ compiler runtime systems contain references
+# to abort(), particulary in the C++ exception handling code. It is
+# not possible to eliminate these references, so this dummy function
+# in included to satisfy them. It is not expected that this function
+# will ever be called, so its current behaviour is to simply loop.
+#
+cdl_option CYGFUN_INFRA_DUMMY_ABORT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGINT_ISO_EXIT == 0
+ # CYGINT_ISO_EXIT == 0
+ # --> 1
+ # Requires: !CYGINT_ISO_EXIT
+ # CYGINT_ISO_EXIT == 0
+ # --> 1
+};
+
+# Reset platform at end of test case execution
+# If this option is set then test case programs will reset the platform
+# when they terminate, as opposed to the default which is to just hang
+# in a loop.
+#
+cdl_option CYGSEM_INFRA_RESET_ON_TEST_EXIT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Provide dummy strlen() function
+# This option controls the inclusion of a dummy strlen() function.
+# Parts of the C and C++ compiler runtime systems contain references
+# to strlen(), particulary in the C++ exception handling code. It is
+# not possible to eliminate these references, so this dummy function
+# in included to satisfy them. While it is not expected that this function
+# will ever be called, it is functional but uses the simplest, smallest
+# algorithm. There is a faster version of strlen() in the C library.
+#
+cdl_option CYGFUN_INFRA_DUMMY_STRLEN {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGINT_ISO_STRING_STRFUNCS == 0
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 0
+ # Requires: !CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 0
+};
+
+# Make all compiler warnings show as errors
+# Enabling this option will cause all compiler warnings to show
+# as errors and bring the library build to a halt. This is used
+# to ensure that the code base is warning free, and thus ensure
+# that newly introduced warnings stand out and get fixed before
+# they show up as weird run-time behavior.
+#
+cdl_option CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+ # Requires: is_substr(CYGBLD_GLOBAL_CFLAGS, " -Werror")
+ # CYGBLD_GLOBAL_CFLAGS == "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe"
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGBLD_GLOBAL_CFLAGS
+ # Requires: CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS
+};
+
+# Make compiler and assembler communicate by pipe
+# Enabling this option will cause the compiler to feed the
+# assembly output the the assembler via a pipe instead of
+# via a temporary file. This normally reduces the build
+# time.
+#
+cdl_option CYGBLD_INFRA_CFLAGS_PIPE {
+ # Flavor: bool
+ user_value 1
+ # value_source user
+ # Default value: 0
+ # Requires: is_substr(CYGBLD_GLOBAL_CFLAGS, " -pipe")
+ # CYGBLD_GLOBAL_CFLAGS == "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe"
+ # --> 1
+};
+
+# Infra build options
+# Package specific build options including control over
+# compiler flags used only in building this package.
+#
+cdl_component CYGPKG_INFRA_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the eCos infra package. These flags are used
+# in addition to the set of global flags.
+#
+cdl_option CYGPKG_INFRA_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-fno-rtti -Woverloaded-virtual"
+ # value_source default
+ # Default value: "-fno-rtti -Woverloaded-virtual"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the eCos infra package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_INFRA_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wno-pointer-sign
+ # value_source default
+ # Default value: -Wno-pointer-sign
+};
+
+# Suppressed linker flags
+# This option modifies the set of linker flags for
+# building the eCos infra package tests. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_INFRA_LDFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wl,--gc-sections
+ # value_source default
+ # Default value: -Wl,--gc-sections
+};
+
+# Additional linker flags
+# This option modifies the set of linker flags for
+# building the eCos infra package tests. These flags are added to
+# the set of global flags if present.
+#
+cdl_option CYGPKG_INFRA_LDFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wl,--fatal-warnings
+ # value_source default
+ # Default value: -Wl,--fatal-warnings
+};
+
+# Infra package tests
+#
+cdl_component CYGPKG_INFRA_TESTS {
+ # Calculated value: "tests/cxxsupp tests/diag_sprintf1 tests/diag_sprintf2"
+ # Flavor: data
+ # Current_value: tests/cxxsupp tests/diag_sprintf1 tests/diag_sprintf2
+};
+
+# >
+# Number of times a test runs
+# This option controls the number of times tests will execute their
+# basic function. Not all tests will honor this setting, but those
+# that do will execute the test N times before terminating. A value
+# less than 0 indicates to run forever.
+#
+cdl_option CYGNUM_TESTS_RUN_COUNT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# <
+# <
+# Redboot ROM monitor
+# doc: ref/redboot.html
+# This package supports the Redboot [stand-alone debug monitor]
+# using eCos as the underlying board support mechanism.
+#
+cdl_package CYGPKG_REDBOOT {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK == 0
+ # CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGPKG_REDBOOT_ARM_OPTIONS
+ # ActiveIf: CYGPKG_REDBOOT
+ # component CYGPKG_REDBOOT_HAL_OPTIONS
+ # ActiveIf: CYGPKG_REDBOOT
+ # component CYGPKG_REDBOOT_HAL_TX37_OPTIONS
+ # ActiveIf: CYGPKG_REDBOOT
+ # option CYGSEM_IO_ETH_DRIVERS_WARN
+ # ActiveIf: CYGPKG_REDBOOT
+};
+
+# >
+# Include support for ELF file format
+#
+cdl_component CYGSEM_REDBOOT_ELF {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Use the virtual address in the ELF headers
+# The ELF headers contain both a virtual and a physical address
+# for where code/data should be loaded. By default the physical
+# address is used but sometimes it is necassary to use the
+# virtual address because of bugy toolchains
+#
+cdl_option CYGOPT_REDBOOT_ELF_VIRTUAL_ADDRESS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Methods of loading images using redboot
+#
+cdl_interface CYGINT_REDBOOT_LOAD_METHOD {
+ # Implemented by CYGBLD_BUILD_REDBOOT_WITH_XYZMODEM, active, enabled
+ # Implemented by CYGPKG_REDBOOT_NETWORKING, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 2
+
+ # The following properties are affected by this value
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGINT_REDBOOT_LOAD_METHOD
+};
+
+# Build Redboot ROM ELF image
+# This option enables the building of the Redboot ELF image.
+# The image may require further relocation or symbol
+# stripping before being converted to a binary image.
+# This is handled by a rule in the target CDL.
+#
+cdl_component CYGBLD_BUILD_REDBOOT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+ # Requires: CYGPKG_INFRA
+ # CYGPKG_INFRA == current
+ # --> 1
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+ # Requires: ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT == 0
+ # --> 1
+ # Requires: ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ # CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT == 0
+ # --> 1
+ # Requires: ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ # CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM == 0
+ # --> 1
+ # Requires: CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+ # CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT == 1
+ # --> 1
+ # Requires: CYGINT_ISO_STRING_MEMFUNCS
+ # CYGINT_ISO_STRING_MEMFUNCS == 1
+ # --> 1
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+ # Requires: CYGINT_REDBOOT_LOAD_METHOD
+ # CYGINT_REDBOOT_LOAD_METHOD == 2
+ # --> 1
+
+ # The following properties are affected by this value
+ # package CYGPKG_HAL_ARM_TX37KARO
+ # Requires: CYGBLD_BUILD_REDBOOT == 1
+ # option CYGBLD_BUILD_REDBOOT_BIN
+ # ActiveIf: CYGBLD_BUILD_REDBOOT
+};
+
+# >
+# Include GDB support in RedBoot
+# RedBoot normally includes support for the GDB debugging
+# protocols. This option allows this to be disabled which
+# may yield a substantial savings in terms of code and memory
+# usage by RedBoot.
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_GDB {
+ # ActiveIf constraint: CYGINT_HAL_DEBUG_GDB_STUBS
+ # CYGINT_HAL_DEBUG_GDB_STUBS == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+ # Requires: CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ # CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
+ # --> 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT == 0
+ # --> 0
+};
+
+# Threads debugging support
+# Enabling this option will include special code in the
+# GDB stubs to support debugging of threaded programs. In
+# the case of eCos programs, this support allows GDB to
+# have complete access to the eCos threads in the
+# program.
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_THREADS {
+ # ActiveIf constraint: CYG_HAL_STARTUP != "RAM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ # CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT == 1
+ # --> 1
+};
+
+# Customized version string
+# Use this option to define a customized version "string" for
+# RedBoot. Note: this value is only cosmetic, displayed by the
+# "version" command, but is useful for providing site specific
+# information about the RedBoot configuration.
+#
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 "Ka-Ro 2009-06-10"
+ # value_source inferred
+ # Default value: 0 0
+};
+
+# Enable command line editing
+# If this option is non-zero, RedBoot will remember the
+# last N command lines. These lines may be reused.
+# Enabling this history will also enable rudimentary
+# editting of the lines themselves.
+#
+cdl_option CYGNUM_REDBOOT_CMD_LINE_EDITING {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 16
+ # value_source default
+ # Default value: 16
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_CMD_LINE_ANSI_SEQUENCES
+ # ActiveIf: CYGNUM_REDBOOT_CMD_LINE_EDITING != 0
+ # option CYGBLD_REDBOOT_CMD_LINE_HISTORY
+ # Requires: CYGNUM_REDBOOT_CMD_LINE_EDITING > 0
+};
+
+# Enable command line editing using ANSI arrows, etc
+# If this option is enabled, RedBoot will accept standard ANSI key
+# sequences for cursor movement (along with the emacs style keys).
+#
+cdl_option CYGSEM_REDBOOT_CMD_LINE_ANSI_SEQUENCES {
+ # ActiveIf constraint: CYGNUM_REDBOOT_CMD_LINE_EDITING != 0
+ # CYGNUM_REDBOOT_CMD_LINE_EDITING == 16
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Enable history command and expansion
+# Enabling this option will allow RedBoot to provide a
+# history command to list previous commands. Also enables
+# history expansion via '!' character similar to bash
+# shell.
+#
+cdl_option CYGBLD_REDBOOT_CMD_LINE_HISTORY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGNUM_REDBOOT_CMD_LINE_EDITING > 0
+ # CYGNUM_REDBOOT_CMD_LINE_EDITING == 16
+ # --> 1
+};
+
+# Number of unique RAM segments on platform
+# Change this option to be the number of memory segments which are
+# supported by the platform. If the value is greater than 1, then
+# a platform specific function must provide information about the
+# additional segments.
+#
+cdl_option CYGBLD_REDBOOT_MAX_MEM_SEGMENTS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include support gzip/zlib decompression
+#
+cdl_component CYGBLD_BUILD_REDBOOT_WITH_ZLIB {
+ # ActiveIf constraint: CYGPKG_COMPRESS_ZLIB
+ # CYGPKG_COMPRESS_ZLIB == current
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGOPT_REDBOOT_FIS_ZLIB_COMMON_BUFFER
+ # ActiveIf: CYGBLD_BUILD_REDBOOT_WITH_ZLIB && CYGOPT_REDBOOT_FIS
+};
+
+# >
+# Size of zlib decompression buffer
+# This is the size of the buffer filled with incoming data
+# during load before calls are made to the decompressor
+# function. For ethernet downloads this can be made bigger
+# (at the cost of memory), but for serial downloads on slow
+# processors it may be necessary to reduce the size to
+# avoid serial overruns. zlib appears to bail out if less
+# than five bytes are available initially so this is the
+# minimum.
+#
+cdl_option CYGNUM_REDBOOT_LOAD_ZLIB_BUFFER {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 64
+ # value_source default
+ # Default value: 64
+ # Legal values: 5 to 256
+};
+
+# Support compression of Flash images
+# This CDL indicates whether flash images can
+# be decompressed from gzip/zlib format into RAM.
+#
+cdl_option CYGPRI_REDBOOT_ZLIB_FLASH {
+ # ActiveIf constraint: CYGPKG_REDBOOT_FLASH
+ # CYGPKG_REDBOOT_FLASH == 1
+ # --> 1
+ # ActiveIf constraint: (!CYGSEM_IO_FLASH_READ_INDIRECT) || CYGPRI_REDBOOT_ZLIB_FLASH_FORCE
+ # CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # CYGPRI_REDBOOT_ZLIB_FLASH_FORCE == 1
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+};
+
+# Include GZIP uncompress command
+# Enable this option to include a 'gunzip' command
+# to uncompress GZIP compressed data.
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_GUNZIP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Turn on CYGPRI_REDBOOT_ZLIB_FLASH
+# Force CYGPRI_REDBOOT_ZLIB_FLASH to be chosen
+#
+cdl_option CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGPRI_REDBOOT_ZLIB_FLASH
+ # ActiveIf: (!CYGSEM_IO_FLASH_READ_INDIRECT) || CYGPRI_REDBOOT_ZLIB_FLASH_FORCE
+};
+
+# <
+# Include support for xyzModem downloads
+# doc: ref/download-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_XYZMODEM {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Allow the load-command write into Flash.
+# Write images direct to Flash via the load command.
+# We assume anything which is invalid RAM is flash, hence
+# the requires statement
+#
+cdl_option CYGBLD_REDBOOT_LOAD_INTO_FLASH {
+ # ActiveIf constraint: CYGPKG_REDBOOT_FLASH
+ # CYGPKG_REDBOOT_FLASH == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS
+ # CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS == 1
+ # --> 1
+};
+
+# Include MS Windows CE support
+# doc: ref/wince.html
+# This option enables MS Windows CE EShell support
+# and Windows CE .BIN images support
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_WINCE_SUPPORT {
+ # Flavor: bool
+ user_value 1
+ # value_source user
+ # Default value: 0
+};
+
+# Include support for MXC USB downloads
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_MXCUSB {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Include support for i.MX USB OTG downloads
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_IMXOTG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Include POSIX checksum command
+# doc: ref/cksum-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_CKSUM {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include memory fill command
+# doc: ref/mfill-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_MFILL {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include memory compare command
+# doc: ref/mcmp-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_MCMP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include memory copy command
+# doc: ref/mcopy-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_MCOPY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include memory dump command
+# doc: ref/dump-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_DUMP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include cache command
+# doc: ref/cache-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Include exec command
+# doc: ref/exec-command.html
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGPKG_REDBOOT_ARM_LINUX_EXEC
+ # ActiveIf: CYGBLD_BUILD_REDBOOT_WITH_EXEC
+};
+
+# Include I/O Memory commands 'iopeek' and 'iopoke'
+#
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_IOMEM {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Granularity of timer/ticks
+# This option controls the granularity of the timers.
+# Faster CPUs can afford higher granularity (lower values)
+# which should give higher network performance since the stack
+# is purely polled.
+#
+cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 250
+ # value_source default
+ # Default value: 250
+ # Legal values: 10 25 50 100 250 500 1000
+};
+
+# Redboot Networking
+# This option includes networking support in RedBoot.
+#
+cdl_component CYGPKG_REDBOOT_NETWORKING {
+ # ActiveIf constraint: CYGPKG_IO_ETH_DRIVERS
+ # CYGPKG_IO_ETH_DRIVERS == current
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_IO_ETH_DRIVERS_PASS_PACKETS
+ # DefaultValue: 0 != CYGPKG_REDBOOT_NETWORKING
+};
+
+# >
+# Print net debug information
+# This option is overriden by the configuration stored
+# in flash.
+#
+cdl_option CYGDBG_REDBOOT_NET_DEBUG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Support TFTP for download
+# This option enables the use of the TFTP protocol for
+# download
+#
+cdl_option CYGSEM_REDBOOT_NET_TFTP_DOWNLOAD {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Support HTTP for download
+# This option enables the use of the HTTP protocol for
+# download
+#
+cdl_option CYGSEM_REDBOOT_NET_HTTP_DOWNLOAD {
+ # Flavor: bool
+ user_value 0
+ # value_source user
+ # Default value: 1
+};
+
+# Default IP address
+# This IP address is the default used by RedBoot if
+# a BOOTP/DHCP server does not respond. The numbers
+# should be separated by *commas*, and not dots. If
+# an IP address is configured into the Flash
+# configuration, that will be used in preference.
+#
+cdl_component CYGDAT_REDBOOT_DEFAULT_IP_ADDR {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 0 0
+};
+
+# >
+# Do not try to use BOOTP
+# By default Redboot tries to use BOOTP to get an IP
+# address. If there's no BOOTP server on your network
+# use this option to avoid to wait until the
+# timeout. This option is overriden by the
+# configuration stored in flash.
+#
+cdl_option CYGSEM_REDBOOT_DEFAULT_NO_BOOTP {
+ # This option is not active
+ # The parent CYGDAT_REDBOOT_DEFAULT_IP_ADDR is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Default bootp server
+# This IP address is the default server
+# address used by RedBoot if a BOOTP/DHCP
+# server does not respond. The numbers should
+# be separated by *commas*, and not dots. If
+# an IP address is configured into the Flash
+# configuration, that will be used in
+# preference.
+#
+cdl_option CYGDAT_REDBOOT_DEFAULT_BOOTP_SERVER_IP_ADDR {
+ # This option is not active
+ # The parent CYGDAT_REDBOOT_DEFAULT_IP_ADDR is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 0 0
+};
+
+# <
+# Use DHCP to get IP information
+# Use DHCP protocol to obtain pertinent IP addresses, such
+# as the client, server, gateway, etc.
+#
+cdl_component CYGSEM_REDBOOT_NETWORKING_DHCP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGSEM_REDBOOT_NETWORKING_USE_GATEWAY
+ # Requires: CYGSEM_REDBOOT_NETWORKING_DHCP
+};
+
+# Use a gateway for non-local IP traffic
+# Enabling this option will allow the RedBoot networking
+# stack to use a [single] gateway to reach a non-local
+# IP address. If disabled, RedBoot will only be able to
+# reach nodes on the same subnet.
+#
+cdl_component CYGSEM_REDBOOT_NETWORKING_USE_GATEWAY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGSEM_REDBOOT_NETWORKING_DHCP
+ # CYGSEM_REDBOOT_NETWORKING_DHCP == 1
+ # --> 1
+};
+
+# >
+# Default gateway IP address
+# This IP address is the default used by RedBoot
+# if a BOOTP/DHCP server does not respond. The
+# numbers should be separated by *commas*, and
+# not dots. If an IP address is configured into
+# the Flash configuration, that will be used in
+# preference.
+#
+cdl_component CYGDAT_REDBOOT_DEFAULT_GATEWAY_IP_ADDR {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 0 0
+};
+
+# Default IP address mask
+# This IP address mask is the default used by
+# RedBoot if a BOOTP/DHCP server does not
+# respond. The numbers should be separated by
+# *commas*, and not dots. If an IP address is
+# configured into the Flash configuration, that
+# will be used in preference.
+#
+cdl_component CYGDAT_REDBOOT_DEFAULT_IP_ADDR_MASK {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "255, 255, 255, 0"
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 0 0
+};
+
+# <
+# TCP port to listen for incoming connections
+# RedBoot will 'listen' on this port for incoming TCP
+# connections. This allows outside connections to be made
+# to the platform, either for GDB or RedBoot commands.
+#
+cdl_option CYGNUM_REDBOOT_NETWORKING_TCP_PORT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 9000
+ # value_source default
+ # Default value: 9000
+};
+
+# Number of [network] packet buffers
+# RedBoot may need to buffer network data to support
+# various connections. This option allows control
+# over the number of such buffered packets, and in
+# turn, controls the amount of memory used by RedBoot
+# (which is not available to user applications).
+# Each packet buffer takes up about 1514 bytes.
+# Note: there is little need to make this larger than
+# the default.
+#
+cdl_option CYGNUM_REDBOOT_NETWORKING_MAX_PKTBUF {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 4
+ # value_source default
+ # Default value: 4
+ # Legal values: 3 to 8
+};
+
+# DNS support
+# When this option is enabled, RedBoot will be built with
+# support for DNS, allowing use of hostnames on the command
+# line.
+#
+cdl_component CYGPKG_REDBOOT_NETWORKING_DNS {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_NS_DNS
+ # CYGPKG_NS_DNS (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: !CYGPKG_NS_DNS_BUILD
+ # CYGPKG_NS_DNS_BUILD (unknown) == 0
+ # --> 1
+};
+
+# >
+# Default DNS IP
+# This option sets the IP of the default DNS. The IP can be
+# changed at runtime as well.
+#
+cdl_option CYGPKG_REDBOOT_NETWORKING_DNS_IP {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS is not active
+ # ActiveIf constraint: !CYGSEM_REDBOOT_FLASH_CONFIG
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 0
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0.0.0.0
+ # value_source default
+ # Default value: 0.0.0.0
+};
+
+# Timeout in DNS lookup
+# This option sets the timeout used when looking up an
+# address via the DNS. Default is 10 seconds.
+#
+cdl_option CYGNUM_REDBOOT_NETWORKING_DNS_TIMEOUT {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS is not active
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 10
+ # value_source default
+ # Default value: 10
+};
+
+# Support the use of a domain name
+# This option controls if Redboot supports domain
+# names when performing DNS lookups
+#
+cdl_component CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# >
+# Default DNS domain
+# This option sets the default DNS domain name.
+# This value will be overwritten by the value in
+# flash or a domain returned by DHCP
+#
+cdl_option CYGPKG_REDBOOT_NETWORKING_DNS_DEFAULT_DOMAIN {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Get DNS domain from Flash
+# This option enables getting the domain name
+# from the flash configuration. This can later be
+# overwritten by a value learnt from DHCP
+#
+cdl_option CYGPKG_REDBOOT_NETWORKING_DNS_FCONFIG_DOMAIN {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is disabled
+ # ActiveIf constraint: CYGSEM_REDBOOT_FLASH_CONFIG
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Use DNS domain from DHCP
+# This option enables the use of the domain name
+# returned by DHCP.
+#
+cdl_option CYGPKG_REDBOOT_NETWORKING_DNS_DHCP_DOMAIN {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# BOOTP/DHCP DNS domain buffer size
+# This options sets the size of the static
+# buffer used by BOOTP/DHCP to store the DNS
+# domain name. The domain name will not be
+# set if the buffer is too small to hold it.
+#
+cdl_option CYGNUM_REDBOOT_NETWORK_DNS_DOMAIN_BUFSIZE {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is not active
+ # The parent CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 32
+ # value_source default
+ # Default value: 32
+};
+
+# <
+# <
+# Default network device driver
+# This is the name of the default network device to use.
+#
+cdl_option CYGDAT_REDBOOT_DEFAULT_NETWORK_DEVICE {
+ # This option is not active
+ # ActiveIf constraint: CYGHWR_NET_DRIVERS > 1
+ # CYGHWR_NET_DRIVERS == 1
+ # --> 0
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "\"\""
+ # value_source default
+ # Default value: "\"\""
+};
+
+# Initialize only one net device
+# This option tells RedBoot to stop initializing network
+# devices when it finds the first device which is
+# successfully initialized. The default behavior causes
+# all network devices to be initialized.
+#
+cdl_option CYGSEM_REDBOOT_NETWORK_INIT_ONE_DEVICE {
+ # This option is not active
+ # ActiveIf constraint: CYGHWR_NET_DRIVERS > 1
+ # CYGHWR_NET_DRIVERS == 1
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Let RedBoot use any I/O channel for its console.
+# If this option is enabled then RedBoot will attempt to use all
+# defined serial I/O channels for its console device. Once input
+# arrives at one of these channels then the console will use only
+# that port.
+#
+cdl_option CYGPKG_REDBOOT_ANY_CONSOLE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+};
+
+# Let RedBoot adjust the baud rate of the serial console.
+# If this option is enabled then RedBoot will support commands
+# to set and query the baud rate on the selected console.
+#
+cdl_option CYGSEM_REDBOOT_VARIABLE_BAUD_RATE {
+ # ActiveIf constraint: CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+ # CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Run a platform specific startup function.
+# If this option is enabled then RedBoot will execute a platform
+# specific startup function before entering into its command line
+# processing. This allows the platform to perform any special
+# setups before RedBoot actually starts running. Note: the entire
+# RedBoot environment will already be initialized at this point.
+#
+cdl_option CYGSEM_REDBOOT_PLF_STARTUP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Run a platform specific ESA validation function.
+# If this option is enabled then RedBoot will execute a platform
+# specific function to validate an ethernet ESA. This would be
+# useful if the address must conform to standards set by the
+# hardware manufacturer, etc.
+#
+cdl_option CYGSEM_REDBOOT_PLF_ESA_VALIDATE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # component CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
+ # Requires: CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ # option CYGDAT_DEVS_ETH_ARM_TX37KARO_OUI
+ # ActiveIf: CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+};
+
+# Maximum command line length
+# This option allows control over how long the CLI command line
+# should be. This space will be allocated statically
+# rather than from RedBoot's stack.
+#
+cdl_option CYGPKG_REDBOOT_MAX_CMD_LINE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 256
+ # The inferred value should not be edited directly.
+ inferred_value 1024
+ # value_source inferred
+ # Default value: 256
+};
+
+# Command processing idle timeout (ms)
+# This option controls the timeout period before the
+# command processing is considered 'idle'. Making this
+# number smaller will cause idle processing to take place
+# more often, etc. The default value of 10ms is a reasonable
+# tradeoff between responsiveness and overhead.
+#
+cdl_option CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 10
+ # value_source default
+ # Default value: 10
+};
+
+# Validate RAM addresses during load
+# This option controls whether or not RedBoot will make
+# sure that memory being used by the "load" command is
+# in fact in user RAM. Leaving the option enabled makes
+# for a safer environment, but this check may not be valid
+# on all platforms, thus the ability to disable it.
+# ** Disable this only with great care **
+#
+cdl_option CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ # Requires: CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS
+};
+
+# Allow RedBoot to support FLASH programming
+# If this option is enabled then RedBoot will provide commands
+# to manage images in FLASH memory. These images can be loaded
+# into memory for execution or executed in place.
+#
+cdl_component CYGPKG_REDBOOT_FLASH {
+ # ActiveIf constraint: CYGHWR_IO_FLASH_DEVICE
+ # CYGHWR_IO_FLASH_DEVICE == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGPRI_REDBOOT_ZLIB_FLASH
+ # ActiveIf: CYGPKG_REDBOOT_FLASH
+ # option CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ # ActiveIf: CYGPKG_REDBOOT_FLASH
+};
+
+# >
+# Byte order used to store info in flash.
+# This option controls the byte ordering used to store
+# the FIS directory info and flash config info.
+#
+cdl_option CYGOPT_REDBOOT_FLASH_BYTEORDER {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value NATURAL
+ # value_source default
+ # Default value: NATURAL
+ # Legal values: "NATURAL" "MSBFIRST" "LSBFIRST"
+};
+
+# RedBoot Flash Image System support
+# doc: ref/flash-image-system.html
+# This option enables the Flash Image System commands
+# and support within RedBoot. If disabled, simple Flash
+# access commands such as "fis write" will still exist.
+# This option would be disabled for targets that need simple
+# FLASH manipulation, but do not have the need or space for
+# complete image management.
+#
+cdl_option CYGOPT_REDBOOT_FIS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGPKG_REDBOOT_FIS_CONTENTS
+ # ActiveIf: CYGOPT_REDBOOT_FIS
+ # option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
+ # ActiveIf: CYGOPT_REDBOOT_FIS && (CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == "FLASH")
+ # component CYGOPT_REDBOOT_FIS_ZLIB_COMMON_BUFFER
+ # ActiveIf: CYGBLD_BUILD_REDBOOT_WITH_ZLIB && CYGOPT_REDBOOT_FIS
+};
+
+# Max number of chunks of free space to manage
+# If this option is defined then "fis free" will
+# rely on the FIS directory to determine what space is
+# free within the FLASH. This option controls the
+# maximum number of free segment which can be handled
+# (typically this number is small). If this option is
+# not enabled, the the archaic behaviour of actually
+# scanning the FLASH for erased sectors (unreliable)
+# will be used to determine what's free and what's
+# not.
+#
+cdl_option CYGDAT_REDBOOT_FIS_MAX_FREE_CHUNKS {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 1 32
+ # value_source default
+ # Default value: 1 32
+};
+
+# Flash Image System default directory contents
+#
+cdl_component CYGPKG_REDBOOT_FIS_CONTENTS {
+ # ActiveIf constraint: CYGOPT_REDBOOT_FIS
+ # CYGOPT_REDBOOT_FIS == 1
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+};
+
+# >
+# Flash block containing the Directory
+# Which block of flash should hold the directory
+# information. Positive numbers are absolute block
+# numbers. Negative block numbers count backwards
+# from the last block. eg 2 means block 2, -2
+# means the last but one block.
+#
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -1
+ # value_source default
+ # Default value: -1
+
+ # The following properties are affected by this value
+ # option CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK
+ # Requires: CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK !=
+ # CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK
+};
+
+# Redundant Flash Image System Directory Support
+# This option enables the use of a redundant FIS
+# directory within RedBoot. If enabled a flash block
+# will be reserved for a second copy of the fis
+# directory. Doing this allow for power failure safe
+# updates of the directory by the application.
+#
+cdl_component CYGOPT_REDBOOT_REDUNDANT_FIS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: 0 == CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
+ # CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG == 1
+ # --> 0
+};
+
+# >
+# Flash block containing the backup Directory
+# Which block of flash should hold the redundant
+# directory information. Positive numbers are
+# absolute block numbers. Negative block numbers
+# count backwards from the last block. eg 2 means
+# block 2, -2 means the last but one block.
+#
+cdl_option CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK {
+ # This option is not active
+ # The parent CYGOPT_REDBOOT_REDUNDANT_FIS is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -3
+ # value_source default
+ # Default value: -3
+ # Requires: CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK !=
+ # CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK
+ # CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK == 0
+ # CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK == -1
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK
+ # Requires: CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK !=
+ # CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK
+};
+
+# <
+# Pseudo-file to describe reserved area
+# If an area of FLASH is reserved, it is informative to
+# have a fis entry describing it. This option controls
+# creation of such an entry by default in the fis init
+# command.
+#
+cdl_option CYGOPT_REDBOOT_FIS_RESERVED_BASE {
+ # This option is not active
+ # ActiveIf constraint: 0 != CYGNUM_REDBOOT_FLASH_RESERVED_BASE
+ # CYGNUM_REDBOOT_FLASH_RESERVED_BASE == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# File to describe RedBoot boot image
+# Normally a ROM-startup RedBoot image is first in the
+# FLASH, and the system boots using that image. This
+# option controls creation of an entry describing it in
+# the fis init command. It might be disabled if a
+# platform has an immutable boot image of its own, where
+# we use a POST-startup RedBoot instead, which performs
+# less board initialization.
+#
+cdl_option CYGOPT_REDBOOT_FIS_REDBOOT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGOPT_REDBOOT_FIS_REDBOOT_POST
+ # DefaultValue: !CYGOPT_REDBOOT_FIS_REDBOOT
+ # option CYGBLD_REDBOOT_MIN_IMAGE_SIZE
+ # DefaultValue: CYGOPT_REDBOOT_FIS_REDBOOT ? 0x20000 : 0
+};
+
+# File to describe RedBoot POST-compatible image
+# This option controls creation of an entry describing a
+# POST-startup RedBoot image in the fis init command.
+# Not all platforms support POST-startup. A platform
+# might have both for testing purposes, where the
+# eventual user would substitute their own POST code for
+# the initial ROM-startup RedBoot, and then jump to the
+# POST-compatible RedBoot immediately following.
+#
+cdl_component CYGOPT_REDBOOT_FIS_REDBOOT_POST {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: !CYGOPT_REDBOOT_FIS_REDBOOT
+ # CYGOPT_REDBOOT_FIS_REDBOOT == 1
+ # --> 0
+};
+
+# >
+# Offset of POST image from FLASH start
+# This option specifies the offset for a POST image from
+# the start of FLASH. If unset, then the fis entry
+# describing the POST image will be placed where
+# convenient.
+#
+cdl_option CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET {
+ # This option is not active
+ # The parent CYGOPT_REDBOOT_FIS_REDBOOT_POST is disabled
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+ # Requires: CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET >= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET == 0
+ # CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET
+ # Requires: CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET >= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+};
+
+# <
+# File to describe RedBoot backup image
+# This option controls creation of an entry describing a
+# backup RedBoot image in the fis init command.
+# Conventionally a RAM-startup RedBoot image is kept
+# under this name for use in updating the ROM-based
+# RedBoot that boots the board.
+#
+cdl_option CYGOPT_REDBOOT_FIS_REDBOOT_BACKUP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Include ARM SIB ID in FIS
+# If set, this option will cause the last 5 words of
+# the FIS to include the special ID needed for the
+# flash to be recognized as a reserved area for RedBoot
+# by an ARM BootRom monitor.
+#
+cdl_option CYGOPT_REDBOOT_FIS_DIRECTORY_ARM_SIB_ID {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Size of FIS directory entry
+# The FIS directory is limited to one single flash
+# sector. If your flash has tiny sectors, you may wish
+# to reduce this value in order to get more slots in
+# the FIS directory.
+#
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 256
+ # value_source default
+ # Default value: 256
+};
+
+# Number of FIS directory entries
+# The FIS directory normally occupies a single flash
+# sector. Adjusting this value can allow for more than
+# one flash sector to be used, which is useful if your
+# sectors are very small.
+#
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_COUNT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 8
+ # value_source default
+ # Default value: 8
+};
+
+# Maximum RedBoot image size
+# This option controls the maximum length reserved
+# for the RedBoot boot image in the FIS table.
+# This should be a multiple of the flash's erase
+# block size.
+#
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00020000
+ # The inferred value should not be edited directly.
+ inferred_value 0x00040000
+ # value_source inferred
+ # Default value: CYGOPT_REDBOOT_FIS_REDBOOT ? 0x20000 : 0
+ # CYGOPT_REDBOOT_FIS_REDBOOT == 1
+ # --> 0x00020000
+};
+
+# Offset from start of FLASH to RedBoot boot image
+# This option controls where the RedBoot boot image is
+# located relative to the start of FLASH.
+#
+cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGNUM_REDBOOT_FLASH_RESERVED_BASE
+ # CYGNUM_REDBOOT_FLASH_RESERVED_BASE == 0
+ # --> 0
+ # Requires: CYGNUM_REDBOOT_FLASH_RESERVED_BASE <= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # CYGNUM_REDBOOT_FLASH_RESERVED_BASE == 0
+ # CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET
+ # Requires: CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET >= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # Requires: CYGNUM_REDBOOT_FLASH_RESERVED_BASE <= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # component CYGPKG_HAL_ARM_TX37_OPTIONS
+ # Requires: CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0
+};
+
+# Size of reserved area at start of FLASH
+# This option reserves an area at the start of
+# FLASH where RedBoot will never interfere; it is
+# expected that this area contains
+# (non-RedBoot-based) POST code or some other boot
+# monitor that executes before RedBoot.
+#
+cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGOPT_REDBOOT_FIS_RESERVED_BASE
+ # ActiveIf: 0 != CYGNUM_REDBOOT_FLASH_RESERVED_BASE
+ # option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # DefaultValue: CYGNUM_REDBOOT_FLASH_RESERVED_BASE
+ # option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+ # Requires: CYGNUM_REDBOOT_FLASH_RESERVED_BASE <= CYGBLD_REDBOOT_FLASH_BOOT_OFFSET
+};
+
+# <
+# Keep all RedBoot FLASH data blocks locked.
+# When this option is enabled, RedBoot will keep configuration
+# data and the FIS directory blocks implicitly locked. While
+# this is somewhat safer, it does add overhead during updates.
+#
+cdl_option CYGSEM_REDBOOT_FLASH_LOCK_SPECIAL {
+ # This option is not active
+ # ActiveIf constraint: CYGHWR_IO_FLASH_BLOCK_LOCKING != 0
+ # CYGHWR_IO_FLASH_BLOCK_LOCKING == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Use CRC checksums on FIS images.
+# When this option is enabled, RedBoot will use CRC checksums
+# when reading and writing flash images.
+#
+cdl_option CYGSEM_REDBOOT_FIS_CRC_CHECK {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# ARM FLASH drivers support SIB flash block structure
+# This interface is implemented by a flash driver
+# to indicate that it supports the ARM SIB flash
+# block structure
+#
+cdl_interface CYGINT_REDBOOT_ARM_FLASH_SIB_SUPPORTED {
+ # No options implement this inferface
+ # ActiveIf constraint: CYGPKG_HAL_ARM
+ # CYGPKG_HAL_ARM == current
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_REDBOOT_ARM_FLASH_SIB
+ # ActiveIf: CYGINT_REDBOOT_ARM_FLASH_SIB_SUPPORTED
+};
+
+# Use ARM SIB flash block structure
+# This option is used to interpret ARM Flash System
+# information blocks.
+#
+cdl_option CYGHWR_REDBOOT_ARM_FLASH_SIB {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_REDBOOT_ARM_FLASH_SIB_SUPPORTED
+ # CYGINT_REDBOOT_ARM_FLASH_SIB_SUPPORTED == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Keep RedBoot configuration data in FLASH
+# When this option is enabled, RedBoot will keep configuration
+# data in a separate block of FLASH memory. This data will
+# include such items as the node IP address or startup scripts.
+#
+cdl_component CYGSEM_REDBOOT_FLASH_CONFIG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: CYGPKG_IO_FLASH != 0
+ # CYGPKG_IO_FLASH == current
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGDAT_REDBOOT_DEFAULT_IP_ADDR
+ # DefaultValue: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # option CYGDAT_REDBOOT_DEFAULT_BOOTP_SERVER_IP_ADDR
+ # DefaultValue: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # component CYGDAT_REDBOOT_DEFAULT_GATEWAY_IP_ADDR
+ # DefaultValue: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "0, 0, 0, 0"
+ # component CYGDAT_REDBOOT_DEFAULT_IP_ADDR_MASK
+ # DefaultValue: CYGSEM_REDBOOT_FLASH_CONFIG ? 0 : "255, 255, 255, 0"
+ # option CYGPKG_REDBOOT_NETWORKING_DNS_IP
+ # ActiveIf: !CYGSEM_REDBOOT_FLASH_CONFIG
+ # option CYGPKG_REDBOOT_NETWORKING_DNS_FCONFIG_DOMAIN
+ # ActiveIf: CYGSEM_REDBOOT_FLASH_CONFIG
+ # option CYGFUN_REDBOOT_BOOT_SCRIPT
+ # ActiveIf: CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT || CYGSEM_REDBOOT_FLASH_CONFIG
+};
+
+# >
+# Length of configuration data in FLASH
+# This option is used to control the amount of memory and FLASH
+# to be used for configuration options (persistent storage).
+#
+cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 4096
+ # value_source default
+ # Default value: 4096
+};
+
+# Style of media used for persistent data storage
+# Persistent data storage can either be held in 'norma' FLASH
+# or some other device (represented by the 'EEPROM' choice).
+# The different styles utilize different access methods.
+#
+cdl_option CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value FLASH
+ # value_source default
+ # Default value: FLASH
+ # Legal values: "FLASH" "EEPROM"
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
+ # ActiveIf: CYGOPT_REDBOOT_FIS && (CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == "FLASH")
+ # option CYGSEM_REDBOOT_FLASH_CONFIG_READONLY_FALLBACK
+ # DefaultValue: (CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == "FLASH")
+};
+
+# Merged config data and FIS directory
+# If this option is set, then the FIS directory and FLASH
+# configuration database will be stored in the same physical
+# FLASH block.
+#
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+ # ActiveIf constraint: CYGOPT_REDBOOT_FIS && (CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == "FLASH")
+ # CYGOPT_REDBOOT_FIS == 1
+ # CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == FLASH
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # component CYGOPT_REDBOOT_REDUNDANT_FIS
+ # Requires: 0 == CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
+};
+
+# Which block of flash to use
+# Which block of flash should hold the configuration
+# information. Positive numbers are absolute block numbers.
+# Negative block numbers count backwards from the last block.
+# eg 2 means block 2, -2 means the last but one block.
+#
+cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -2
+ # value_source default
+ # Default value: -2
+};
+
+# Support simple macros/aliases in FLASH
+# This option is used to allow support for simple text-based
+# macros (aliases). These aliases are kept in the FLASH
+# configuration data (persistent storage).
+#
+cdl_option CYGSEM_REDBOOT_FLASH_ALIASES {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Length of strings in FLASH configuration data
+# This option is used to control the amount of memory
+# and FLASH to be used for string configuration
+# options (persistent storage).
+#
+cdl_option CYGNUM_REDBOOT_FLASH_STRING_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 128
+ # value_source default
+ # Default value: 128
+};
+
+# Length of configuration script(s) in FLASH
+# This option is used to control the amount of memory and
+# FLASH to be used for configuration options (persistent
+# storage).
+#
+cdl_option CYGNUM_REDBOOT_FLASH_SCRIPT_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 512
+ # The inferred value should not be edited directly.
+ inferred_value 2048
+ # value_source inferred
+ # Default value: 512
+};
+
+# Fallback to read-only FLASH configuration
+# This option will cause the configuration information to
+# revert to the readonly information stored in the FLASH.
+# The option only takes effect after
+# 1) the config_ok flag has been set to be true,
+# indicating that at one time the copy in RAM was valid;
+# and
+# 2) the information in RAM has been verified to be invalid
+#
+cdl_option CYGSEM_REDBOOT_FLASH_CONFIG_READONLY_FALLBACK {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: (CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == "FLASH")
+ # CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA == FLASH
+ # --> 1
+};
+
+# <
+# Allow RedBoot to support fileio
+# If this option is enabled then RedBoot will provide commands
+# to load files from fileio file systems such as JFFS2.
+#
+cdl_component CYGPKG_REDBOOT_FILEIO {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_IO_FILEIO
+ # CYGPKG_IO_FILEIO (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGNUM_REDBOOT_GETC_BUFFER
+ # DefaultValue: CYGPKG_REDBOOT_FILEIO ? 4096 : 256
+};
+
+# >
+# Include an ls command
+# If this option is enabled a simple ls command will be
+# included in redboot so the contents of a directory
+# can be listed
+#
+cdl_option CYGBLD_REDBOOT_FILEIO_WITH_LS {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_FILEIO is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Allow RedBoot to support disks
+# If this option is enabled then RedBoot will provide commands
+# to load disk files.
+#
+cdl_component CYGPKG_REDBOOT_DISK {
+ # Flavor: bool
+ user_value 0
+ # value_source user
+ # Default value: 1
+};
+
+# >
+# Include Redboot commands for disk access
+#
+cdl_option CYGSEM_REDBOOT_DISK {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGINT_REDBOOT_DISK_DRIVERS != 0
+ # CYGINT_REDBOOT_DISK_DRIVERS == 0
+ # --> 0
+};
+
+# Hardware drivers for disk-type devices
+#
+cdl_interface CYGINT_REDBOOT_DISK_DRIVERS {
+ # Implemented by CYGSEM_REDBOOT_DISK_IDE, inactive, enabled
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_DISK
+ # DefaultValue: CYGINT_REDBOOT_DISK_DRIVERS != 0
+};
+
+# Maximum number of supported disks
+# This option controls the number of disks supported by
+# RedBoot.
+#
+cdl_option CYGNUM_REDBOOT_MAX_DISKS {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 4
+ # value_source default
+ # Default value: 4
+};
+
+# Maximum number of partitions per disk
+# This option controls the maximum number of supported
+# partitions per disk.
+#
+cdl_option CYGNUM_REDBOOT_MAX_PARTITIONS {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 8
+ # value_source default
+ # Default value: 8
+};
+
+# Support IDE disks.
+# When this option is enabled, RedBoot will support IDE disks.
+#
+cdl_component CYGSEM_REDBOOT_DISK_IDE {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+ # ActiveIf constraint: CYGINT_HAL_PLF_IF_IDE != 0
+ # CYGINT_HAL_PLF_IF_IDE == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Work with VMware virtual disks
+# This option controls the disk driver behavior at
+# ide-init
+#
+cdl_option CYGSEM_REDBOOT_DISK_IDE_VMWARE {
+ # This option is not active
+ # The parent CYGSEM_REDBOOT_DISK_IDE is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Support Linux second extended filesystems.
+# When this option is enabled, RedBoot will support EXT2
+# filesystems.
+#
+cdl_component CYGSEM_REDBOOT_DISK_EXT2FS {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Support ISO9660 filesystems.
+# When this option is enabled, RedBoot will support ISO9660
+# filesystems.
+#
+cdl_component CYGSEM_REDBOOT_DISK_ISO9660 {
+ # This option is not active
+ # The parent CYGPKG_REDBOOT_DISK is disabled
+
+ # Calculated value: 0
+ # Flavor: bool
+ # Current value: 0
+};
+
+# <
+# Boot scripting
+# doc: ref/persistent-state-flash.html
+# This contains options related to RedBoot's boot script
+# functionality.
+#
+cdl_component CYGPKG_REDBOOT_BOOT_SCRIPT {
+ # There is no associated value.
+};
+
+# >
+# Boot scripting enabled
+# This option controls whether RedBoot boot script
+# functionality is enabled.
+#
+cdl_option CYGFUN_REDBOOT_BOOT_SCRIPT {
+ # ActiveIf constraint: CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT || CYGSEM_REDBOOT_FLASH_CONFIG
+ # CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT == 0
+ # CYGSEM_REDBOOT_FLASH_CONFIG == 1
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+};
+
+# Use default RedBoot boot script
+# If enabled, this option will tell RedBoot to use the
+# value of this option as a default boot script.
+#
+cdl_option CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGFUN_REDBOOT_BOOT_SCRIPT
+ # ActiveIf: CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT || CYGSEM_REDBOOT_FLASH_CONFIG
+};
+
+# Resolution (in ms) for script timeout value.
+# This option controls the resolution of the script
+# timeout. The value is specified in milliseconds
+# (ms), thus to have the script timeout be defined in
+# terms of tenths of seconds, use 100.
+#
+cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_TIMEOUT_RESOLUTION {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 1000
+ # The inferred value should not be edited directly.
+ inferred_value 10
+ # value_source inferred
+ # Default value: 1000
+};
+
+# Script default timeout value
+# This option is used to set the default timeout for startup
+# scripts, when they are enabled.
+#
+cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_DEFAULT_TIMEOUT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 10
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 10
+};
+
+# <
+# Support RTC for time & date functions
+# When this option is enabled, RedBoot will support commands to
+# query and set the real time clock (time and date)
+#
+cdl_option CYGSEM_REDBOOT_RTC {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_IO_WALLCLOCK
+ # CYGPKG_IO_WALLCLOCK (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Behave like a ROM monitor
+# Enabling this option will allow RedBoot to provide ROM
+# monitor-style services to programs which it executes.
+#
+cdl_option CYGPRI_REDBOOT_ROM_MONITOR {
+ # ActiveIf constraint: CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"
+ # CYG_HAL_STARTUP == ROMRAM
+ # CYG_HAL_STARTUP == ROMRAM
+ # --> 1
+
+ # Calculated value: 1
+ # Flavor: bool
+ # Current value: 1
+ # Requires: CYGSEM_HAL_ROM_MONITOR
+ # CYGSEM_HAL_ROM_MONITOR == 1
+ # --> 1
+};
+
+# Allow RedBoot to handle GNUPro application 'syscalls'.
+# If this option is enabled then RedBoot will install a
+# syscall handler to support debugging of applications
+# based on GNUPro newlib/bsp.
+#
+cdl_component CYGSEM_REDBOOT_BSP_SYSCALLS {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGOPT_HAL_ARM_SYSCALL_GPROF_SUPPORT
+ # ActiveIf: CYGSEM_REDBOOT_BSP_SYSCALLS
+ # option CYGPKG_HAL_GDB_FILEIO
+ # ActiveIf: CYGSEM_REDBOOT_BSP_SYSCALLS
+};
+
+# >
+# Support additional syscalls for 'gprof' profiling
+# Support additional syscalls to support a periodic callback
+# function for histogram-style profiling, and an enquire/set
+# of the tick rate.
+# The application must use the GNUPro newlib facilities
+# to set this up.
+#
+cdl_option CYGSEM_REDBOOT_BSP_SYSCALLS_GPROF {
+ # This option is not active
+ # The parent CYGSEM_REDBOOT_BSP_SYSCALLS is disabled
+ # ActiveIf constraint: 0 < CYGINT_REDBOOT_BSP_SYSCALLS_GPROF_SUPPORT
+ # CYGINT_REDBOOT_BSP_SYSCALLS_GPROF_SUPPORT == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Does the HAL support 'gprof' profiling?
+#
+cdl_interface CYGINT_REDBOOT_BSP_SYSCALLS_GPROF_SUPPORT {
+ # Implemented by CYGOPT_HAL_ARM_SYSCALL_GPROF_SUPPORT, inactive, enabled
+ # This option is not active
+ # The parent CYGSEM_REDBOOT_BSP_SYSCALLS is disabled
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_BSP_SYSCALLS_GPROF
+ # ActiveIf: 0 < CYGINT_REDBOOT_BSP_SYSCALLS_GPROF_SUPPORT
+};
+
+# Do not raise SIGTRAP when program exits
+# For some (single shot) newlib based programs,
+# exiting and returning a termination status may be
+# the normal expected behavior.
+#
+cdl_option CYGOPT_REDBOOT_BSP_SYSCALLS_EXIT_WITHOUT_TRAP {
+ # This option is not active
+ # The parent CYGSEM_REDBOOT_BSP_SYSCALLS is disabled
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# <
+# Use a common buffer for Zlib and FIS
+# Use a common memory buffer for both the zlib workspace
+# and FIS directory operations. This can save a substantial
+# amount of RAM, especially when flash sectors are large.
+#
+cdl_component CYGOPT_REDBOOT_FIS_ZLIB_COMMON_BUFFER {
+ # ActiveIf constraint: CYGBLD_BUILD_REDBOOT_WITH_ZLIB && CYGOPT_REDBOOT_FIS
+ # CYGBLD_BUILD_REDBOOT_WITH_ZLIB == 1
+ # CYGOPT_REDBOOT_FIS == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# >
+# Size of Zlib/FIS common buffer
+# Size of common buffer to allocate. Must be at least the
+# size of one flash sector.
+#
+cdl_option CYGNUM_REDBOOT_FIS_ZLIB_COMMON_BUFFER_SIZE {
+ # This option is not active
+ # The parent CYGOPT_REDBOOT_FIS_ZLIB_COMMON_BUFFER is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x0000C000
+ # value_source default
+ # Default value: 0x0000C000
+ # Legal values: 0x4000 to 0x80000000
+};
+
+# <
+# Buffer size in getc when loading images
+# When loading images a buffer is used between redboot and the
+# underlying storage medium, eg a filesystem, or a socket etc.
+# The size of this buffer can have a big impart on load speed.
+#
+cdl_option CYGNUM_REDBOOT_GETC_BUFFER {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 256
+ # value_source default
+ # Default value: CYGPKG_REDBOOT_FILEIO ? 4096 : 256
+ # CYGPKG_REDBOOT_FILEIO == 0
+ # --> 256
+};
+
+# <
+# Redboot for ARM options
+# This option lists the target's requirements for a valid Redboot
+# configuration.
+#
+cdl_component CYGPKG_REDBOOT_ARM_OPTIONS {
+ # ActiveIf constraint: CYGPKG_REDBOOT
+ # CYGPKG_REDBOOT == current
+ # --> 1
+
+ # There is no associated value.
+
+ # The following properties are affected by this value
+};
+
+# >
+# Provide the exec command in RedBoot
+# This option contains requirements for booting linux
+# from RedBoot. The component is enabled/disabled from
+# RedBoots CDL.
+#
+cdl_component CYGPKG_REDBOOT_ARM_LINUX_EXEC {
+ # ActiveIf constraint: CYGBLD_BUILD_REDBOOT_WITH_EXEC
+ # CYGBLD_BUILD_REDBOOT_WITH_EXEC == 1
+ # --> 1
+
+ # There is no associated value.
+};
+
+# >
+# Enable -x switch for exec command.
+# This option allows bi-endian platforms to launch kernels
+# built for an endianess different than the RedBoot endianess
+#
+cdl_option CYGHWR_REDBOOT_LINUX_EXEC_X_SWITCH {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Physical base address of linux kernel
+# This is the physical address of the base of the
+# Linux kernel image.
+#
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x40108000
+ # The inferred value should not be edited directly.
+ inferred_value 0x40108000
+ # value_source inferred
+ # Default value: CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT
+ # CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x40108000
+ # --> 0x40108000
+};
+
+# Default physical base address of linux kernel
+# This is the physical address of the base of the
+# Linux kernel image. This option gets set by the
+# platform CDL.
+#
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00008000
+ # The inferred value should not be edited directly.
+ inferred_value 0x40108000
+ # value_source inferred
+ # Default value: 0x00008000
+
+ # The following properties are affected by this value
+ # option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS
+ # DefaultValue: CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT
+ # component CYGPKG_REDBOOT_HAL_TX37_OPTIONS
+ # Requires: CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x40108000
+};
+
+# Base address of linux kernel parameter tags
+# This is the base address of the area of memory used to
+# pass parameters to the Linux kernel. This should be chosen
+# to avoid overlap with the kernel and any ramdisk image.
+#
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_TAGS_ADDRESS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00000100
+ # value_source default
+ # Default value: 0x00000100
+};
+
+# <
+# <
+# Redboot HAL options
+# This option lists the target's requirements for a valid Redboot
+# configuration.
+#
+cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ # ActiveIf constraint: CYGPKG_REDBOOT
+ # CYGPKG_REDBOOT == current
+ # --> 1
+
+ # There is no associated value.
+};
+
+# >
+# Build Redboot ROM binary image
+# This option enables the conversion of the Redboot ELF
+# image to a binary image suitable for ROM programming.
+#
+cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ # ActiveIf constraint: CYGBLD_BUILD_REDBOOT
+ # CYGBLD_BUILD_REDBOOT == 1
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Redboot HAL variant options
+#
+cdl_component CYGPKG_REDBOOT_HAL_TX37_OPTIONS {
+ # ActiveIf constraint: CYGPKG_REDBOOT
+ # CYGPKG_REDBOOT == current
+ # --> 1
+
+ # There is no associated value.
+ # Requires: CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x40108000
+ # CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x40108000
+ # --> 1
+};
+
+# <
+# ISO C and POSIX infrastructure
+# eCos supports implementations of ISO C libraries and POSIX
+# implementations. This package provides infrastructure used by
+# all such implementations.
+#
+cdl_package CYGPKG_ISOINFRA {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGPKG_ISOINFRA
+ # package CYGPKG_LIBC_STRING
+ # Requires: CYGPKG_ISOINFRA
+ # package CYGPKG_COMPRESS_ZLIB
+ # Requires: CYGPKG_ISOINFRA
+ # package CYGPKG_IO_FLASH
+ # Requires: CYGPKG_ISOINFRA
+ # option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_USE_MEMCPY
+ # Requires: CYGPKG_ISOINFRA
+ # option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_USE_MEMCPY
+ # DefaultValue: 0 != CYGPKG_ISOINFRA
+ # component CYGPKG_MEMALLOC_MALLOC_ALLOCATORS
+ # ActiveIf: CYGPKG_ISOINFRA
+ # package CYGPKG_LIBC_I18N
+ # Requires: CYGPKG_ISOINFRA
+ # package CYGPKG_LIBC_STDLIB
+ # Requires: CYGPKG_ISOINFRA
+};
+
+# >
+# Startup and termination
+#
+cdl_component CYGPKG_ISO_STARTUP {
+ # There is no associated value.
+};
+
+# >
+# main() startup implementations
+# Implementations of this interface arrange for a user-supplied
+# main() to be called in an ISO compatible environment.
+#
+cdl_interface CYGINT_ISO_MAIN_STARTUP {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_MAIN_STARTUP
+ # CYGINT_ISO_MAIN_STARTUP == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_MAIN_STARTUP
+ # Requires: 1 >= CYGINT_ISO_MAIN_STARTUP
+};
+
+# environ implementations
+# Implementations of this interface provide the environ
+# variable required by POSIX.
+#
+cdl_interface CYGINT_ISO_ENVIRON {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_ENVIRON
+ # CYGINT_ISO_ENVIRON == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_ENVIRON
+ # Requires: 1 >= CYGINT_ISO_ENVIRON
+};
+
+# <
+# ctype.h functions
+#
+cdl_component CYGPKG_ISO_CTYPE_H {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of ctype functions
+#
+cdl_interface CYGINT_ISO_CTYPE {
+ # Implemented by CYGPKG_LIBC_I18N, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_CTYPE
+ # CYGINT_ISO_CTYPE == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_CTYPE
+ # Requires: 1 >= CYGINT_ISO_CTYPE
+ # package CYGPKG_HAL_ARM_TX37KARO
+ # Requires: CYGINT_ISO_CTYPE
+ # option CYGFUN_LIBC_STRING_BSD_FUNCS
+ # Requires: CYGINT_ISO_CTYPE
+ # package CYGPKG_LIBC_STDLIB
+ # Requires: CYGINT_ISO_CTYPE
+};
+
+# Ctype implementation header
+#
+cdl_option CYGBLD_ISO_CTYPE_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/i18n/ctype.inl>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGPKG_LIBC_I18N_NEWLIB_CTYPE
+ # Requires: CYGBLD_ISO_CTYPE_HEADER == "<cyg/libc/i18n/newlibctype.h>"
+ # option CYGIMP_LIBC_I18N_CTYPE_INLINES
+ # Requires: CYGBLD_ISO_CTYPE_HEADER == "<cyg/libc/i18n/ctype.inl>"
+};
+
+# <
+# Error handling
+#
+cdl_component CYGPKG_ISO_ERRNO {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of error codes
+#
+cdl_interface CYGINT_ISO_ERRNO_CODES {
+ # Implemented by CYGPKG_ERROR, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_ERRNO_CODES
+ # CYGINT_ISO_ERRNO_CODES == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_ERRNO_CODES
+ # Requires: 1 >= CYGINT_ISO_ERRNO_CODES
+};
+
+# Error codes implementation header
+#
+cdl_option CYGBLD_ISO_ERRNO_CODES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/error/codes.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # package CYGPKG_ERROR
+ # Requires: CYGBLD_ISO_ERRNO_CODES_HEADER == "<cyg/error/codes.h>"
+};
+
+# Number of implementations of errno variable
+#
+cdl_interface CYGINT_ISO_ERRNO {
+ # Implemented by CYGPKG_ERROR_ERRNO, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_ERRNO
+ # CYGINT_ISO_ERRNO == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_ERRNO
+ # Requires: 1 >= CYGINT_ISO_ERRNO
+};
+
+# errno variable implementation header
+#
+cdl_option CYGBLD_ISO_ERRNO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/error/errno.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # component CYGPKG_ERROR_ERRNO
+ # Requires: CYGBLD_ISO_ERRNO_HEADER == "<cyg/error/errno.h>"
+};
+
+# <
+# Locale-related functions
+#
+cdl_component CYGPKG_ISO_LOCALE {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of locale functions
+#
+cdl_interface CYGINT_ISO_LOCALE {
+ # Implemented by CYGPKG_LIBC_I18N, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_LOCALE
+ # CYGINT_ISO_LOCALE == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_LOCALE
+ # Requires: 1 >= CYGINT_ISO_LOCALE
+};
+
+# Locale implementation header
+#
+cdl_option CYGBLD_ISO_LOCALE_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Standard I/O-related functionality
+#
+cdl_component CYGPKG_ISO_STDIO {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of stdio file types
+#
+cdl_interface CYGINT_ISO_STDIO_FILETYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILETYPES
+ # CYGINT_ISO_STDIO_FILETYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_FILETYPES
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILETYPES
+};
+
+# Stdio file types implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_FILETYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Stdio standard streams implementations
+#
+cdl_interface CYGINT_ISO_STDIO_STREAMS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_STREAMS
+ # CYGINT_ISO_STDIO_STREAMS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_STREAMS
+ # Requires: 1 >= CYGINT_ISO_STDIO_STREAMS
+};
+
+# Stdio standard streams implementation header
+# This header file must define stdin, stdout
+# and stderr.
+#
+cdl_option CYGBLD_ISO_STDIO_STREAMS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio file operations
+#
+cdl_interface CYGINT_ISO_STDIO_FILEOPS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEOPS
+ # CYGINT_ISO_STDIO_FILEOPS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_FILEOPS
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEOPS
+};
+
+# Stdio file operations implementation header
+# This header controls the file system operations on a file
+# such as remove(), rename(), tmpfile(), tmpnam() and associated
+# constants.
+#
+cdl_option CYGBLD_ISO_STDIO_FILEOPS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio file access functionals
+#
+cdl_interface CYGINT_ISO_STDIO_FILEACCESS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEACCESS
+ # CYGINT_ISO_STDIO_FILEACCESS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_FILEACCESS
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEACCESS
+ # option CYGFUN_COMPRESS_ZLIB_GZIO
+ # Requires: CYGINT_ISO_STDIO_FILEACCESS
+};
+
+# Stdio file access implementation header
+# This header controls the file access operations
+# such as fclose(), fflush(), fopen(), freopen(), setbuf(),
+# setvbuf(), and associated constants.
+#
+cdl_option CYGBLD_ISO_STDIO_FILEACCESS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio formatted I/O
+#
+cdl_interface CYGINT_ISO_STDIO_FORMATTED_IO {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_FORMATTED_IO
+ # CYGINT_ISO_STDIO_FORMATTED_IO == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_FORMATTED_IO
+ # Requires: 1 >= CYGINT_ISO_STDIO_FORMATTED_IO
+ # option CYGFUN_COMPRESS_ZLIB_GZIO
+ # Requires: CYGINT_ISO_STDIO_FORMATTED_IO
+};
+
+# Stdio formatted I/O implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_FORMATTED_IO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio character I/O
+#
+cdl_interface CYGINT_ISO_STDIO_CHAR_IO {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_CHAR_IO
+ # CYGINT_ISO_STDIO_CHAR_IO == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_CHAR_IO
+ # Requires: 1 >= CYGINT_ISO_STDIO_CHAR_IO
+};
+
+# Stdio character I/O implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_CHAR_IO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio direct I/O
+#
+cdl_interface CYGINT_ISO_STDIO_DIRECT_IO {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_DIRECT_IO
+ # CYGINT_ISO_STDIO_DIRECT_IO == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_DIRECT_IO
+ # Requires: 1 >= CYGINT_ISO_STDIO_DIRECT_IO
+};
+
+# Stdio direct I/O implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_DIRECT_IO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio file positioning
+#
+cdl_interface CYGINT_ISO_STDIO_FILEPOS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEPOS
+ # CYGINT_ISO_STDIO_FILEPOS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_FILEPOS
+ # Requires: 1 >= CYGINT_ISO_STDIO_FILEPOS
+ # option CYGFUN_COMPRESS_ZLIB_GZIO
+ # Requires: CYGINT_ISO_STDIO_FILEPOS
+};
+
+# Stdio file positioning implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_FILEPOS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of stdio error handling
+#
+cdl_interface CYGINT_ISO_STDIO_ERROR {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_ERROR
+ # CYGINT_ISO_STDIO_ERROR == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_ERROR
+ # Requires: 1 >= CYGINT_ISO_STDIO_ERROR
+};
+
+# Stdio error handling implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_ERROR_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX fd-related function implementations
+#
+cdl_interface CYGINT_ISO_STDIO_POSIX_FDFUNCS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STDIO_POSIX_FDFUNCS
+ # CYGINT_ISO_STDIO_POSIX_FDFUNCS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDIO_POSIX_FDFUNCS
+ # Requires: 1 >= CYGINT_ISO_STDIO_POSIX_FDFUNCS
+};
+
+# POSIX fd-related function implementation header
+#
+cdl_option CYGBLD_ISO_STDIO_POSIX_FDFUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Standard general utility functions
+#
+cdl_component CYGPKG_ISO_STDLIB {
+ # There is no associated value.
+};
+
+# >
+# String conversion function implementations
+#
+cdl_interface CYGINT_ISO_STDLIB_STRCONV {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_STRCONV
+ # CYGINT_ISO_STDLIB_STRCONV == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDLIB_STRCONV
+ # Requires: 1 >= CYGINT_ISO_STDLIB_STRCONV
+};
+
+# String conversion function implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_STRCONV_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/stdlib/atox.inl>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGIMP_LIBC_STDLIB_INLINE_ATOX
+ # Requires: CYGBLD_ISO_STDLIB_STRCONV_HEADER == "<cyg/libc/stdlib/atox.inl>"
+};
+
+# String to FP conversion function implementations
+#
+cdl_interface CYGINT_ISO_STDLIB_STRCONV_FLOAT {
+ # Implemented by CYGFUN_LIBC_strtod, active, disabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_STDLIB_STRCONV_FLOAT
+ # CYGINT_ISO_STDLIB_STRCONV_FLOAT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDLIB_STRCONV_FLOAT
+ # Requires: 1 >= CYGINT_ISO_STDLIB_STRCONV_FLOAT
+};
+
+# String to FP conversion function implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_STRCONV_FLOAT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Random number generator implementations
+#
+cdl_interface CYGINT_ISO_RAND {
+ # Implemented by CYGIMP_LIBC_RAND_SIMPLEST, active, disabled
+ # Implemented by CYGIMP_LIBC_RAND_SIMPLE1, active, disabled
+ # Implemented by CYGIMP_LIBC_RAND_KNUTH1, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_RAND
+ # CYGINT_ISO_RAND == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_RAND
+ # Requires: 1 >= CYGINT_ISO_RAND
+};
+
+# Random number generator implementation header
+#
+cdl_option CYGBLD_ISO_RAND_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Malloc implementations
+#
+cdl_interface CYGINT_ISO_MALLOC {
+ # Implemented by CYGPKG_MEMALLOC_MALLOC_ALLOCATORS, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_MALLOC
+ # CYGINT_ISO_MALLOC == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_MALLOC
+ # Requires: 1 >= CYGINT_ISO_MALLOC
+ # option CYGFUN_LIBC_STRING_STRDUP
+ # ActiveIf: CYGINT_ISO_MALLOC
+};
+
+# Malloc implementation header
+#
+cdl_option CYGBLD_ISO_MALLOC_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Mallinfo() implementations
+#
+cdl_interface CYGINT_ISO_MALLINFO {
+ # Implemented by CYGPKG_MEMALLOC_MALLOC_ALLOCATORS, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_MALLINFO
+ # CYGINT_ISO_MALLINFO == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_MALLINFO
+ # Requires: 1 >= CYGINT_ISO_MALLINFO
+};
+
+# Mallinfo() implementation header
+#
+cdl_option CYGBLD_ISO_MALLINFO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Program exit functionality implementations
+#
+cdl_interface CYGINT_ISO_EXIT {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_EXIT
+ # CYGINT_ISO_EXIT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_EXIT
+ # Requires: 1 >= CYGINT_ISO_EXIT
+ # option CYGFUN_INFRA_DUMMY_ABORT
+ # Requires: !CYGINT_ISO_EXIT
+ # option CYGFUN_INFRA_DUMMY_ABORT
+ # DefaultValue: CYGINT_ISO_EXIT == 0
+};
+
+# Program exit functionality implementation header
+#
+cdl_option CYGBLD_ISO_EXIT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Program environment implementations
+#
+cdl_interface CYGINT_ISO_STDLIB_ENVIRON {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_ENVIRON
+ # CYGINT_ISO_STDLIB_ENVIRON == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDLIB_ENVIRON
+ # Requires: 1 >= CYGINT_ISO_STDLIB_ENVIRON
+};
+
+# Program environment implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_ENVIRON_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# system() implementations
+#
+cdl_interface CYGINT_ISO_STDLIB_SYSTEM {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_SYSTEM
+ # CYGINT_ISO_STDLIB_SYSTEM == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDLIB_SYSTEM
+ # Requires: 1 >= CYGINT_ISO_STDLIB_SYSTEM
+};
+
+# system() implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_SYSTEM_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# bsearch() implementations
+#
+cdl_interface CYGINT_ISO_BSEARCH {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_BSEARCH
+ # CYGINT_ISO_BSEARCH == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_BSEARCH
+ # Requires: 1 >= CYGINT_ISO_BSEARCH
+};
+
+# bsearch() implementation header
+#
+cdl_option CYGBLD_ISO_BSEARCH_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# qsort() implementations
+#
+cdl_interface CYGINT_ISO_QSORT {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_QSORT
+ # CYGINT_ISO_STDLIB_QSORT (unknown) == 0
+ # --> 1
+
+ # The following properties are affected by this value
+};
+
+# qsort() implementation header
+#
+cdl_option CYGBLD_ISO_QSORT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# abs()/labs() implementations
+#
+cdl_interface CYGINT_ISO_ABS {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_ABS
+ # CYGINT_ISO_STDLIB_ABS (unknown) == 0
+ # --> 1
+
+ # The following properties are affected by this value
+};
+
+# abs()/labs() implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_ABS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/stdlib/abs.inl>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGIMP_LIBC_STDLIB_INLINE_ABS
+ # Requires: CYGBLD_ISO_STDLIB_ABS_HEADER == "<cyg/libc/stdlib/abs.inl>"
+};
+
+# div()/ldiv() implementations
+#
+cdl_interface CYGINT_ISO_DIV {
+ # Implemented by CYGPKG_LIBC_STDLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_DIV
+ # CYGINT_ISO_STDLIB_DIV (unknown) == 0
+ # --> 1
+
+ # The following properties are affected by this value
+};
+
+# div()/ldiv() implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_DIV_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/stdlib/div.inl>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGIMP_LIBC_STDLIB_INLINE_DIV
+ # Requires: CYGBLD_ISO_STDLIB_DIV_HEADER == "<cyg/libc/stdlib/div.inl>"
+};
+
+# Header defining the implementation's MB_CUR_MAX
+#
+cdl_option CYGBLD_ISO_STDLIB_MB_CUR_MAX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # interface CYGINT_LIBC_I18N_MB_REQUIRED
+ # Requires: CYGBLD_ISO_STDLIB_MB_CUR_MAX_HEADER == "<cyg/libc/i18n/mb.h>"
+};
+
+# Multibyte character implementations
+#
+cdl_interface CYGINT_ISO_STDLIB_MULTIBYTE {
+ # Implemented by CYGPKG_LIBC_I18N, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: 1 >= CYGINT_ISO_STDLIB_MULTIBYTE
+ # CYGINT_ISO_STDLIB_MULTIBYTE == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STDLIB_MULTIBYTE
+ # Requires: 1 >= CYGINT_ISO_STDLIB_MULTIBYTE
+};
+
+# Multibyte character implementation header
+#
+cdl_option CYGBLD_ISO_STDLIB_MULTIBYTE_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# String functions
+#
+cdl_component CYGPKG_ISO_STRING {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of strerror() function
+#
+cdl_interface CYGINT_ISO_STRERROR {
+ # Implemented by CYGPKG_ERROR_STRERROR, active, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 1
+ # Requires: 1 >= CYGINT_ISO_STRERROR
+ # CYGINT_ISO_STRERROR == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRERROR
+ # Requires: 1 >= CYGINT_ISO_STRERROR
+};
+
+# strerror() implementation header
+#
+cdl_option CYGBLD_ISO_STRERROR_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/error/strerror.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGPKG_ERROR_STRERROR
+ # Requires: CYGBLD_ISO_STRERROR_HEADER == "<cyg/error/strerror.h>"
+};
+
+# memcpy() implementation header
+#
+cdl_option CYGBLD_ISO_MEMCPY_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# memset() implementation header
+#
+cdl_option CYGBLD_ISO_MEMSET_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of strtok_r() function
+#
+cdl_interface CYGINT_ISO_STRTOK_R {
+ # Implemented by CYGPKG_LIBC_STRING, active, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 1
+ # Requires: 1 >= CYGINT_ISO_STRTOK_R
+ # CYGINT_ISO_STRTOK_R == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRTOK_R
+ # Requires: 1 >= CYGINT_ISO_STRTOK_R
+};
+
+# strtok_r() implementation header
+#
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/string/string.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # package CYGPKG_LIBC_STRING
+ # Requires: CYGBLD_ISO_STRTOK_R_HEADER == "<cyg/libc/string/string.h>"
+};
+
+# Number of implementations of locale-specific string functions
+# This covers locale-dependent string functions such as strcoll()
+# and strxfrm().
+#
+cdl_interface CYGINT_ISO_STRING_LOCALE_FUNCS {
+ # Implemented by CYGPKG_LIBC_STRING, active, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 1
+ # Requires: 1 >= CYGINT_ISO_STRING_LOCALE_FUNCS
+ # CYGINT_ISO_STRING_LOCALE_FUNCS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRING_LOCALE_FUNCS
+ # Requires: 1 >= CYGINT_ISO_STRING_LOCALE_FUNCS
+};
+
+# Locale-specific string functions' implementation header
+# This covers locale-dependent string functions such as strcoll()
+# and strxfrm().
+#
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/string/string.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # package CYGPKG_LIBC_STRING
+ # Requires: CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER == "<cyg/libc/string/string.h>"
+};
+
+# Number of implementations of BSD string functions
+#
+cdl_interface CYGINT_ISO_STRING_BSD_FUNCS {
+ # Implemented by CYGFUN_LIBC_STRING_BSD_FUNCS, active, disabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_STRING_BSD_FUNCS
+ # CYGINT_ISO_STRING_BSD_FUNCS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRING_BSD_FUNCS
+ # Requires: 1 >= CYGINT_ISO_STRING_BSD_FUNCS
+};
+
+# BSD string functions' implementation header
+#
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGFUN_LIBC_STRING_BSD_FUNCS
+ # Requires: CYGBLD_ISO_STRING_BSD_FUNCS_HEADER == "<cyg/libc/string/bsdstring.h>"
+};
+
+# Number of implementations of other mem*() functions
+#
+cdl_interface CYGINT_ISO_STRING_MEMFUNCS {
+ # Implemented by CYGPKG_LIBC_STRING, active, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 1
+ # Requires: 1 >= CYGINT_ISO_STRING_MEMFUNCS
+ # CYGINT_ISO_STRING_MEMFUNCS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRING_MEMFUNCS
+ # Requires: 1 >= CYGINT_ISO_STRING_MEMFUNCS
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGINT_ISO_STRING_MEMFUNCS
+ # component CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
+ # Requires: CYGINT_ISO_STRING_MEMFUNCS
+};
+
+# Other mem*() functions' implementation header
+#
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/string/string.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # package CYGPKG_LIBC_STRING
+ # Requires: CYGBLD_ISO_STRING_MEMFUNCS_HEADER == "<cyg/libc/string/string.h>"
+};
+
+# Number of implementations of other ISO C str*() functions
+# This covers the other str*() functions defined by ISO C.
+#
+cdl_interface CYGINT_ISO_STRING_STRFUNCS {
+ # Implemented by CYGPKG_LIBC_STRING, active, enabled
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 1
+ # Requires: 1 >= CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_STRING_STRFUNCS
+ # Requires: 1 >= CYGINT_ISO_STRING_STRFUNCS
+ # option CYGFUN_INFRA_DUMMY_STRLEN
+ # Requires: !CYGINT_ISO_STRING_STRFUNCS
+ # option CYGFUN_INFRA_DUMMY_STRLEN
+ # DefaultValue: CYGINT_ISO_STRING_STRFUNCS == 0
+ # component CYGBLD_BUILD_REDBOOT
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # component CYGPKG_IO_ETH_DRIVERS_NET
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # option CYGFUN_COMPRESS_ZLIB_GZIO
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # package CYGPKG_IO_FLASH
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # package CYGPKG_LIBC_STDLIB
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+};
+
+# Other ISO C str*() functions' implementation header
+# This covers the other str*() functions defined by ISO C.
+#
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/libc/string/string.h>
+ # value_source inferred
+ # Default value: 0 0
+
+ # The following properties are affected by this value
+ # package CYGPKG_LIBC_STRING
+ # Requires: CYGBLD_ISO_STRING_STRFUNCS_HEADER == "<cyg/libc/string/string.h>"
+};
+
+# <
+# Clock and time functionality
+#
+cdl_component CYGPKG_ISO_TIME {
+ # There is no associated value.
+};
+
+# >
+# time_t implementation header
+#
+cdl_option CYGBLD_ISO_TIME_T_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# clock_t implementation header
+#
+cdl_option CYGBLD_ISO_CLOCK_T_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# struct timeval implementation header
+#
+cdl_option CYGBLD_ISO_STRUCTTIMEVAL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# fnmatch implementation header
+#
+cdl_option CYGBLD_ISO_FNMATCH_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of POSIX timer types
+#
+cdl_interface CYGINT_ISO_POSIX_TIMER_TYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMER_TYPES
+ # CYGINT_ISO_POSIX_TIMER_TYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_TIMER_TYPES
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMER_TYPES
+};
+
+# POSIX timer types implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_TIMER_TYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of POSIX clock types
+#
+cdl_interface CYGINT_ISO_POSIX_CLOCK_TYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_CLOCK_TYPES
+ # CYGINT_ISO_POSIX_CLOCK_TYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_CLOCK_TYPES
+ # Requires: 1 >= CYGINT_ISO_POSIX_CLOCK_TYPES
+};
+
+# POSIX clock types implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_CLOCK_TYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of ISO C types
+#
+cdl_interface CYGINT_ISO_C_TIME_TYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_C_TIME_TYPES
+ # CYGINT_ISO_C_TIME_TYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_C_TIME_TYPES
+ # Requires: 1 >= CYGINT_ISO_C_TIME_TYPES
+};
+
+# ISO C time types implementation header
+#
+cdl_option CYGBLD_ISO_C_TIME_TYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of POSIX timers
+#
+cdl_interface CYGINT_ISO_POSIX_TIMERS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMERS
+ # CYGINT_ISO_POSIX_TIMERS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_TIMERS
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMERS
+};
+
+# POSIX timer implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_TIMERS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of POSIX clocks
+#
+cdl_interface CYGINT_ISO_POSIX_CLOCKS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_CLOCKS
+ # CYGINT_ISO_POSIX_CLOCKS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_CLOCKS
+ # Requires: 1 >= CYGINT_ISO_POSIX_CLOCKS
+};
+
+# POSIX clocks implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_CLOCKS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of ISO C clock functions
+#
+cdl_interface CYGINT_ISO_C_CLOCK_FUNCS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_C_CLOCK_FUNCS
+ # CYGINT_ISO_C_CLOCK_FUNCS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_C_CLOCK_FUNCS
+ # Requires: 1 >= CYGINT_ISO_C_CLOCK_FUNCS
+};
+
+# ISO C clock functions' implementation header
+#
+cdl_option CYGBLD_ISO_C_CLOCK_FUNCS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of implementations of tzset() function
+#
+cdl_interface CYGINT_ISO_TZSET {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_TZSET
+ # CYGINT_ISO_TZSET == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_TZSET
+ # Requires: 1 >= CYGINT_ISO_TZSET
+};
+
+# tzset() implementation header
+#
+cdl_option CYGBLD_ISO_TZSET_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Signal functionality
+#
+cdl_component CYGPKG_ISO_SIGNAL {
+ # There is no associated value.
+};
+
+# >
+# Number of implementations of signal numbers
+#
+cdl_interface CYGINT_ISO_SIGNAL_NUMBERS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SIGNAL_NUMBERS
+ # CYGINT_ISO_SIGNAL_NUMBERS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SIGNAL_NUMBERS
+ # Requires: 1 >= CYGINT_ISO_SIGNAL_NUMBERS
+};
+
+# Signal numbering implementation header
+# This header provides the mapping of signal
+# names (e.g. SIGBUS) to numbers.
+#
+cdl_option CYGBLD_ISO_SIGNAL_NUMBERS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Number of signal implementations
+#
+cdl_interface CYGINT_ISO_SIGNAL_IMPL {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SIGNAL_IMPL
+ # CYGINT_ISO_SIGNAL_IMPL == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SIGNAL_IMPL
+ # Requires: 1 >= CYGINT_ISO_SIGNAL_IMPL
+};
+
+# Signals implementation header
+#
+cdl_option CYGBLD_ISO_SIGNAL_IMPL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX real time signals feature test macro
+# This defines the POSIX feature test macro
+# that indicates that the POSIX real time signals
+# are present.
+#
+cdl_interface CYGINT_POSIX_REALTIME_SIGNALS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_POSIX_REALTIME_SIGNALS
+ # CYGINT_POSIX_REALTIME_SIGNALS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_POSIX_REALTIME_SIGNALS
+ # Requires: 1 >= CYGINT_POSIX_REALTIME_SIGNALS
+};
+
+# <
+# Non-local jumps functionality
+#
+cdl_component CYGPKG_ISO_SETJMP {
+ # There is no associated value.
+};
+
+# >
+# setjmp() / longjmp() implementations
+#
+cdl_interface CYGINT_ISO_SETJMP {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SETJMP
+ # CYGINT_ISO_SETJMP == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SETJMP
+ # Requires: 1 >= CYGINT_ISO_SETJMP
+};
+
+# setjmp() / longjmp() implementation header
+#
+cdl_option CYGBLD_ISO_SETJMP_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# sigsetjmp() / siglongjmp() implementations
+#
+cdl_interface CYGINT_ISO_SIGSETJMP {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SIGSETJMP
+ # CYGINT_ISO_SIGSETJMP == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SIGSETJMP
+ # Requires: 1 >= CYGINT_ISO_SIGSETJMP
+};
+
+# sigsetjmp() / siglongjmp() implementation header
+#
+cdl_option CYGBLD_ISO_SIGSETJMP_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Assertions implementation header
+#
+cdl_option CYGBLD_ISO_ASSERT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX file control
+# This covers the POSIX file control definitions,
+# normally found in <fcntl.h>
+#
+cdl_component CYGPKG_ISO_POSIX_FCNTL {
+ # There is no associated value.
+};
+
+# >
+# POSIX open flags implementation header
+#
+cdl_option CYGBLD_ISO_OFLAG_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX fcntl() implementations
+#
+cdl_interface CYGINT_ISO_FCNTL {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_FCNTL
+ # CYGINT_ISO_FCNTL == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_FCNTL
+ # Requires: 1 >= CYGINT_ISO_FCNTL
+};
+
+# POSIX fcntl() implementation header
+#
+cdl_option CYGBLD_ISO_FCNTL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX file open implementations
+#
+cdl_interface CYGINT_ISO_OPEN {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_OPEN
+ # CYGINT_ISO_OPEN == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_OPEN
+ # Requires: 1 >= CYGINT_ISO_OPEN
+};
+
+# POSIX file open implementation header
+#
+cdl_option CYGBLD_ISO_OPEN_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# <sys/stat.h> definitions implementation header
+#
+cdl_option CYGBLD_ISO_STAT_DEFS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX directory reading implementation
+#
+cdl_interface CYGINT_ISO_DIRENT {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_DIRENT
+ # CYGINT_ISO_DIRENT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_DIRENT
+ # Requires: 1 >= CYGINT_ISO_DIRENT
+};
+
+# <dirent.h> definitions implementation header
+#
+cdl_option CYGBLD_ISO_DIRENT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX <sys/types.h> contents
+# This covers the types required by POSIX to be in
+# <sys/types.h>
+#
+cdl_component CYGPKG_ISO_POSIX_TYPES {
+ # There is no associated value.
+};
+
+# >
+# POSIX thread types implementations
+#
+cdl_interface CYGINT_ISO_PTHREADTYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_PTHREADTYPES
+ # CYGINT_ISO_PTHREADTYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_PTHREADTYPES
+ # Requires: 1 >= CYGINT_ISO_PTHREADTYPES
+ # interface CYGINT_ISO_PMUTEXTYPES
+ # Requires: 1 >= CYGINT_ISO_PTHREADTYPES
+};
+
+# POSIX thread types implementation header
+#
+cdl_option CYGBLD_ISO_PTHREADTYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX mutex types implementations
+#
+cdl_interface CYGINT_ISO_PMUTEXTYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_PTHREADTYPES
+ # CYGINT_ISO_PTHREADTYPES == 0
+ # --> 1
+};
+
+# POSIX mutex types implementation header
+#
+cdl_option CYGBLD_ISO_PMUTEXTYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# ssize_t implementation header
+#
+cdl_option CYGBLD_ISO_SSIZE_T_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Filesystem types implementation header
+#
+cdl_option CYGBLD_ISO_FSTYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# gid_t, pid_t, uid_t implementation header
+#
+cdl_option CYGBLD_ISO_SCHEDTYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Non-POSIX <sys/types.h> contents
+# This covers the extra types required by non-POSIX
+# packages to be in <sys/types.h>. These would normally
+# only be visible if _POSIX_SOURCE is not defined.
+#
+cdl_component CYGPKG_ISO_EXTRA_TYPES {
+ # There is no associated value.
+};
+
+# >
+# BSD compatible types
+#
+cdl_interface CYGINT_ISO_BSDTYPES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_BSDTYPES
+ # CYGINT_ISO_BSDTYPES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_BSDTYPES
+ # Requires: 1 >= CYGINT_ISO_BSDTYPES
+};
+
+# BSD types header
+#
+cdl_option CYGBLD_ISO_BSDTYPES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Utsname structure
+#
+cdl_component CYGPKG_ISO_UTSNAME {
+ # There is no associated value.
+};
+
+# >
+# Utsname header
+#
+cdl_option CYGBLD_ISO_UTSNAME_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# POSIX scheduler
+#
+cdl_component CYGPKG_ISO_SCHED {
+ # There is no associated value.
+};
+
+# >
+# POSIX scheduler implementations
+#
+cdl_interface CYGINT_ISO_SCHED_IMPL {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SCHED_IMPL
+ # CYGINT_ISO_SCHED_IMPL == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SCHED_IMPL
+ # Requires: 1 >= CYGINT_ISO_SCHED_IMPL
+};
+
+# POSIX scheduler implementation header
+#
+cdl_option CYGBLD_ISO_SCHED_IMPL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# POSIX semaphores
+#
+cdl_component CYGPKG_ISO_SEMAPHORES {
+ # There is no associated value.
+};
+
+# >
+# POSIX semaphore implementations
+#
+cdl_interface CYGINT_ISO_SEMAPHORES {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_SEMAPHORES
+ # CYGINT_ISO_SEMAPHORES == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SEMAPHORES
+ # Requires: 1 >= CYGINT_ISO_SEMAPHORES
+};
+
+# POSIX semaphore implementation header
+#
+cdl_option CYGBLD_ISO_SEMAPHORES_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# POSIX message queues
+#
+cdl_component CYGPKG_ISO_MQUEUE {
+ # There is no associated value.
+};
+
+# >
+# Implementations
+#
+cdl_interface CYGINT_ISO_MQUEUE {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_MQUEUE
+ # CYGINT_ISO_MQUEUE == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_MQUEUE
+ # Requires: 1 >= CYGINT_ISO_MQUEUE
+ # option CYGNUM_ISO_MQUEUE_OPEN_MAX
+ # ActiveIf: CYGINT_ISO_MQUEUE
+ # option CYGNUM_ISO_MQUEUE_PRIO_MAX
+ # ActiveIf: CYGINT_ISO_MQUEUE
+};
+
+# Implementation header
+#
+cdl_option CYGBLD_ISO_MQUEUE_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Maximum number of open message queues
+#
+cdl_option CYGNUM_ISO_MQUEUE_OPEN_MAX {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_ISO_MQUEUE
+ # CYGINT_ISO_MQUEUE == 0
+ # --> 0
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: CYGNUM_POSIX_MQUEUE_OPEN_MAX > 0 ? CYGNUM_POSIX_MQUEUE_OPEN_MAX : 0
+ # CYGNUM_POSIX_MQUEUE_OPEN_MAX (unknown) == 0
+ # CYGNUM_POSIX_MQUEUE_OPEN_MAX (unknown) == 0
+ # --> 0 0
+};
+
+# Maximum number of message priorities
+#
+cdl_option CYGNUM_ISO_MQUEUE_PRIO_MAX {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_ISO_MQUEUE
+ # CYGINT_ISO_MQUEUE == 0
+ # --> 0
+
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 1 65535
+ # value_source default
+ # Default value: 1 65535
+};
+
+# <
+# POSIX threads
+#
+cdl_component CYGPKG_ISO_PTHREAD {
+ # There is no associated value.
+};
+
+# >
+# POSIX pthread implementations
+#
+cdl_interface CYGINT_ISO_PTHREAD_IMPL {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_PTHREAD_IMPL
+ # CYGINT_ISO_PTHREAD_IMPL == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_PTHREAD_IMPL
+ # Requires: 1 >= CYGINT_ISO_PTHREAD_IMPL
+};
+
+# POSIX pthread implementation header
+#
+cdl_option CYGBLD_ISO_PTHREAD_IMPL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX mutex/cond var implementations
+#
+cdl_interface CYGINT_ISO_PTHREAD_MUTEX {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_PTHREAD_MUTEX
+ # CYGINT_ISO_PTHREAD_MUTEX == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_PTHREAD_MUTEX
+ # Requires: 1 >= CYGINT_ISO_PTHREAD_MUTEX
+};
+
+# POSIX mutex/cond var implementation header
+#
+cdl_option CYGBLD_ISO_PTHREAD_MUTEX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Limits
+#
+cdl_component CYGPKG_ISO_LIMITS {
+ # There is no associated value.
+};
+
+# >
+# POSIX pthread limits implementations
+#
+cdl_interface CYGINT_ISO_POSIX_LIMITS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_LIMITS
+ # CYGINT_ISO_POSIX_LIMITS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_LIMITS
+ # Requires: 1 >= CYGINT_ISO_POSIX_LIMITS
+};
+
+# POSIX pthread limits implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_LIMITS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# OPEN_MAX implementation header
+#
+cdl_option CYGBLD_ISO_OPEN_MAX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# LINK_MAX implementation header
+#
+cdl_option CYGBLD_ISO_LINK_MAX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# NAME_MAX implementation header
+#
+cdl_option CYGBLD_ISO_NAME_MAX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# PATH_MAX implementation header
+#
+cdl_option CYGBLD_ISO_PATH_MAX_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# POSIX termios
+#
+cdl_component CYGPKG_ISO_TERMIOS {
+ # There is no associated value.
+};
+
+# >
+# POSIX termios implementations
+#
+cdl_interface CYGINT_ISO_TERMIOS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_TERMIOS
+ # CYGINT_ISO_TERMIOS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_TERMIOS
+ # Requires: 1 >= CYGINT_ISO_TERMIOS
+};
+
+# POSIX termios implementation header
+#
+cdl_option CYGBLD_ISO_TERMIOS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Dynamic load API
+#
+cdl_component CYGPKG_ISO_DLFCN {
+ # There is no associated value.
+};
+
+# >
+# Dynamic load implementations
+#
+cdl_interface CYGINT_ISO_DLFCN {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 >= CYGINT_ISO_DLFCN
+ # CYGINT_ISO_DLFCN == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_DLFCN
+ # Requires: 1 >= CYGINT_ISO_DLFCN
+};
+
+# Dynamic load implementation header
+#
+cdl_option CYGBLD_ISO_DLFCN_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# UNIX standard functions
+#
+cdl_component CYGPKG_ISO_UNISTD {
+ # There is no associated value.
+};
+
+# >
+# POSIX timer operations implementations
+#
+cdl_interface CYGINT_ISO_POSIX_TIMER_OPS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMER_OPS
+ # CYGINT_ISO_POSIX_TIMER_OPS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_TIMER_OPS
+ # Requires: 1 >= CYGINT_ISO_POSIX_TIMER_OPS
+};
+
+# POSIX timer operations implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_TIMER_OPS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# POSIX sleep() implementations
+#
+cdl_interface CYGINT_ISO_POSIX_SLEEP {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POSIX_SLEEP
+ # CYGINT_ISO_POSIX_SLEEP == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POSIX_SLEEP
+ # Requires: 1 >= CYGINT_ISO_POSIX_SLEEP
+};
+
+# POSIX sleep() implementation header
+#
+cdl_option CYGBLD_ISO_POSIX_SLEEP_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# select()/poll() functions
+#
+cdl_component CYGPKG_ISO_SELECT {
+ # There is no associated value.
+};
+
+# >
+# select() implementations
+#
+cdl_interface CYGINT_ISO_SELECT {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_SELECT
+ # CYGINT_ISO_SELECT == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_SELECT
+ # Requires: 1 >= CYGINT_ISO_SELECT
+};
+
+# select() implementation header
+#
+cdl_option CYGBLD_ISO_SELECT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# poll() implementations
+#
+cdl_interface CYGINT_ISO_POLL {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: 1 >= CYGINT_ISO_POLL
+ # CYGINT_ISO_POLL == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_POLL
+ # Requires: 1 >= CYGINT_ISO_POLL
+};
+
+# poll() implementation header
+#
+cdl_option CYGBLD_ISO_POLL_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# NetDB utility functions
+#
+cdl_component CYGPKG_ISO_NETDB {
+ # There is no associated value.
+};
+
+# >
+# DNS implementations
+#
+cdl_interface CYGINT_ISO_DNS {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: bool
+ # Current value: 0
+ # Requires: 1 >= CYGINT_ISO_DNS
+ # CYGINT_ISO_DNS == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_DNS
+ # Requires: 1 >= CYGINT_ISO_DNS
+};
+
+# DNS implementation header
+#
+cdl_option CYGBLD_ISO_DNS_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Protocol network database implementations
+#
+cdl_interface CYGINT_ISO_NETDB_PROTO {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: bool
+ # Current value: 0
+ # Requires: 1 >= CYGINT_ISO_NETDB_PROTO
+ # CYGINT_ISO_NETDB_PROTO == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_NETDB_PROTO
+ # Requires: 1 >= CYGINT_ISO_NETDB_PROTO
+};
+
+# Protocol network database implementation header
+#
+cdl_option CYGBLD_ISO_NETDB_PROTO_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Services network database implementations
+#
+cdl_interface CYGINT_ISO_NETDB_SERV {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: bool
+ # Current value: 0
+ # Requires: 1 >= CYGINT_ISO_NETDB_SERV
+ # CYGINT_ISO_NETDB_SERV == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_ISO_NETDB_SERV
+ # Requires: 1 >= CYGINT_ISO_NETDB_SERV
+};
+
+# Services network database implementation header
+#
+cdl_option CYGBLD_ISO_NETDB_SERV_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# <
+# Build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_ISOINFRA_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the ISO C and POSIX infrastructure package.
+# These flags are used in addition to the set of global flags.
+#
+cdl_option CYGPKG_ISOINFRA_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the ISO C and POSIX infrastructure package.
+# These flags are removed from the set of global flags
+# if present.
+#
+cdl_option CYGPKG_ISOINFRA_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# <
+# <
+# Compute CRCs
+# doc: ref/services-crc.html
+# This package provides support for CRC calculation. Currently
+# this is the POSIX 1003 defined CRC algorithm, a 32 CRC by
+# Gary S. Brown, and a 16 bit CRC.
+#
+cdl_package CYGPKG_CRC {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # package CYGPKG_COMPRESS_ZLIB
+ # Requires: CYGPKG_CRC
+};
+
+# >
+# POSIX CRC tests
+#
+cdl_option CYGPKG_CRC_TESTS {
+ # Calculated value: "tests/crc_test"
+ # Flavor: data
+ # Current_value: tests/crc_test
+};
+
+# <
+# Zlib compress and decompress package
+# This package provides support for compression and
+# decompression.
+#
+cdl_package CYGPKG_COMPRESS_ZLIB {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+ # Requires: CYGPKG_CRC
+ # CYGPKG_CRC == current
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGBLD_BUILD_REDBOOT_WITH_ZLIB
+ # ActiveIf: CYGPKG_COMPRESS_ZLIB
+};
+
+# >
+# Override memory allocation routines.
+#
+cdl_interface CYGINT_COMPRESS_ZLIB_LOCAL_ALLOC {
+ # Implemented by CYGBLD_BUILD_REDBOOT_WITH_ZLIB, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_COMPRESS_ZLIB_NEEDS_MALLOC
+ # ActiveIf: CYGINT_COMPRESS_ZLIB_LOCAL_ALLOC == 0
+};
+
+# Should deflate() produce 'gzip' compatible output?
+# If this option is set then the output of calling deflate()
+# will be wrapped up as a 'gzip' compatible file.
+#
+cdl_option CYGSEM_COMPRESS_ZLIB_DEFLATE_MAKES_GZIP {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Does this library need malloc?
+# This pseudo-option will force the memalloc library to be
+# required iff the application does not provide it's own
+# infrastructure.
+#
+cdl_option CYGSEM_COMPRESS_ZLIB_NEEDS_MALLOC {
+ # This option is not active
+ # ActiveIf constraint: CYGINT_COMPRESS_ZLIB_LOCAL_ALLOC == 0
+ # CYGINT_COMPRESS_ZLIB_LOCAL_ALLOC == 1
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGPKG_MEMALLOC
+ # CYGPKG_MEMALLOC == current
+ # --> 1
+};
+
+# Include stdio-like utility functions
+# This option enables the stdio-like zlib utility functions
+# (gzread/gzwrite and friends) provided in gzio.c.
+#
+cdl_option CYGFUN_COMPRESS_ZLIB_GZIO {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGPKG_LIBC_STDIO_OPEN ? 1 : 0
+ # CYGPKG_LIBC_STDIO_OPEN (unknown) == 0
+ # --> 0
+ # Requires: CYGINT_ISO_STDIO_FILEPOS
+ # CYGINT_ISO_STDIO_FILEPOS == 0
+ # --> 0
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+ # Requires: CYGINT_ISO_STDIO_FORMATTED_IO
+ # CYGINT_ISO_STDIO_FORMATTED_IO == 0
+ # --> 0
+ # Requires: CYGINT_ISO_STDIO_FILEACCESS
+ # CYGINT_ISO_STDIO_FILEACCESS == 0
+ # --> 0
+};
+
+# Zlib compress and decompress package build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_COMPRESS_ZLIB_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_COMPRESS_ZLIB_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-D__ECOS__ -DNO_ERRNO_H"
+ # value_source default
+ # Default value: "-D__ECOS__ -DNO_ERRNO_H"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_COMPRESS_ZLIB_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wstrict-prototypes
+ # value_source default
+ # Default value: -Wstrict-prototypes
+};
+
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_COMPRESS_ZLIB_LDFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_COMPRESS_ZLIB_LDFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# <
+# zlib tests
+#
+cdl_option CYGPKG_COMPRESS_ZLIB_TESTS {
+ # Calculated value: "tests/zlib1.c tests/zlib2.c"
+ # Flavor: data
+ # Current_value: tests/zlib1.c tests/zlib2.c
+};
+
+# <
+# FLASH device drivers
+# doc: ref/flash.html
+# This option enables drivers for basic I/O services on
+# flash devices.
+#
+cdl_package CYGPKG_IO_FLASH {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+ # Requires: CYGINT_ISO_STRING_STRFUNCS
+ # CYGINT_ISO_STRING_STRFUNCS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGSEM_REDBOOT_FLASH_CONFIG
+ # DefaultValue: CYGPKG_IO_FLASH != 0
+ # package CYGPKG_DEVS_FLASH_ONMXC
+ # ActiveIf: CYGPKG_IO_FLASH
+};
+
+# >
+# Hardware FLASH device drivers
+# This option enables the hardware device drivers
+# for the current platform.
+#
+cdl_interface CYGHWR_IO_FLASH_DEVICE {
+ # Implemented by CYGPKG_DEVS_FLASH_ONMXC, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+
+ # The following properties are affected by this value
+ # component CYGPKG_REDBOOT_FLASH
+ # ActiveIf: CYGHWR_IO_FLASH_DEVICE
+};
+
+# Hardware FLASH device drivers are not in RAM
+# Use of this interface is deprecated.
+# Drivers should make sure that the functions are
+# linked to RAM by putting them in .2ram sections.
+#
+cdl_interface CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+ # Requires: !CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM
+ # CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM
+ # Requires: !CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM
+};
+
+# Hardware can support block locking
+# This option will be enabled by devices which can support
+# locking (write-protection) of individual blocks.
+#
+cdl_interface CYGHWR_IO_FLASH_BLOCK_LOCKING {
+ # No options implement this inferface
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 0 0
+
+ # The following properties are affected by this value
+ # option CYGSEM_REDBOOT_FLASH_LOCK_SPECIAL
+ # ActiveIf: CYGHWR_IO_FLASH_BLOCK_LOCKING != 0
+};
+
+# Hardware cannot support direct access to FLASH memory
+# This option will be asserted by devices which cannot support
+# direct access to the FLASH memory contents (e.g. EEPROM or NAND
+# devices). In these cases, the driver must provide an appropriate
+# hardware access function.
+#
+cdl_option CYGSEM_IO_FLASH_READ_INDIRECT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+ # Requires: !CYGSEM_IO_FLASH_VERIFY_PROGRAM
+ # CYGSEM_IO_FLASH_VERIFY_PROGRAM == 0
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGPRI_REDBOOT_ZLIB_FLASH
+ # ActiveIf: (!CYGSEM_IO_FLASH_READ_INDIRECT) || CYGPRI_REDBOOT_ZLIB_FLASH_FORCE
+ # component CYGHWR_DEVS_FLASH_MMC
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # option CYGHWR_DEVS_FLASH_MMC_ESDHC
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # option CYGHWR_DEVS_FLASH_MMC_SD
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # option CYGHWR_DEVS_FLASH_MXC_NAND
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+};
+
+# Display status messages during flash operations
+# Selecting this option will cause the drivers to print status
+# messages as various flash operations are undertaken.
+#
+cdl_option CYGSEM_IO_FLASH_CHATTER {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Verify data programmed to flash
+# Selecting this option will cause verification of data
+# programmed to flash.
+#
+cdl_option CYGSEM_IO_FLASH_VERIFY_PROGRAM {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGSEM_IO_FLASH_READ_INDIRECT
+ # Requires: !CYGSEM_IO_FLASH_VERIFY_PROGRAM
+};
+
+# Platform has flash soft DIP switch write-protect
+# Selecting this option will cause the state of a hardware jumper or
+# dipswitch to be read by software to determine whether the flash is
+# write-protected or not.
+#
+cdl_option CYGSEM_IO_FLASH_SOFT_WRITE_PROTECT {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Instantiate in I/O block device API
+# Provides a block device accessible using the standard I/O
+# API ( cyg_io_read() etc. )
+#
+cdl_component CYGPKG_IO_FLASH_BLOCK_DEVICE {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_IO
+ # CYGPKG_IO (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# >
+# Name of flash device 1 block device
+#
+cdl_component CYGDAT_IO_FLASH_BLOCK_DEVICE_NAME_1 {
+ # This option is not active
+ # The parent CYGPKG_IO_FLASH_BLOCK_DEVICE is not active
+ # The parent CYGPKG_IO_FLASH_BLOCK_DEVICE is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "\"/dev/flash1\""
+ # value_source default
+ # Default value: "\"/dev/flash1\""
+};
+
+# >
+#
+cdl_interface CYGINT_IO_FLASH_BLOCK_CFG_1 {
+ # Implemented by CYGNUM_IO_FLASH_BLOCK_CFG_STATIC_1, inactive, enabled
+ # Implemented by CYGNUM_IO_FLASH_BLOCK_CFG_FIS_1, inactive, disabled
+ # This option is not active
+ # The parent CYGDAT_IO_FLASH_BLOCK_DEVICE_NAME_1 is not active
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+ # Requires: 1 == CYGINT_IO_FLASH_BLOCK_CFG_1
+ # CYGINT_IO_FLASH_BLOCK_CFG_1 == 0
+ # --> 0
+
+ # The following properties are affected by this value
+ # interface CYGINT_IO_FLASH_BLOCK_CFG_1
+ # Requires: 1 == CYGINT_IO_FLASH_BLOCK_CFG_1
+};
+
+# Static configuration
+# This configures the flash device 1 block device
+# with static base and length
+#
+cdl_component CYGNUM_IO_FLASH_BLOCK_CFG_STATIC_1 {
+ # This option is not active
+ # The parent CYGDAT_IO_FLASH_BLOCK_DEVICE_NAME_1 is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Start offset from flash base
+# This gives the offset from the base of flash which this
+# block device corresponds to.
+#
+cdl_option CYGNUM_IO_FLASH_BLOCK_OFFSET_1 {
+ # This option is not active
+ # The parent CYGNUM_IO_FLASH_BLOCK_CFG_STATIC_1 is not active
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00100000
+ # value_source default
+ # Default value: 0x00100000
+};
+
+# Length
+# This gives the length of the region of flash given over
+# to this block device.
+#
+cdl_option CYGNUM_IO_FLASH_BLOCK_LENGTH_1 {
+ # This option is not active
+ # The parent CYGNUM_IO_FLASH_BLOCK_CFG_STATIC_1 is not active
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00100000
+ # value_source default
+ # Default value: 0x00100000
+};
+
+# <
+# Configuration from FIS
+# This configures the flash device 1 block device
+# from Redboot FIS
+#
+cdl_component CYGNUM_IO_FLASH_BLOCK_CFG_FIS_1 {
+ # This option is not active
+ # The parent CYGDAT_IO_FLASH_BLOCK_DEVICE_NAME_1 is not active
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# >
+# Name of FIS entry
+#
+cdl_component CYGDAT_IO_FLASH_BLOCK_FIS_NAME_1 {
+ # This option is not active
+ # The parent CYGNUM_IO_FLASH_BLOCK_CFG_FIS_1 is not active
+ # The parent CYGNUM_IO_FLASH_BLOCK_CFG_FIS_1 is disabled
+
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "\"jffs2\""
+ # value_source default
+ # Default value: "\"jffs2\""
+};
+
+# <
+# <
+# <
+# Flash device driver build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_IO_FLASH_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the flash device drivers. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_IO_FLASH_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the flash device drivers. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_IO_FLASH_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Flash device driver tests
+# This option specifies the set of tests for the flash device drivers.
+#
+cdl_component CYGPKG_IO_FLASH_TESTS {
+ # Calculated value: "tests/flash1"
+ # Flavor: data
+ # Current_value: tests/flash1
+};
+
+# >
+# Start offset from flash base
+# This gives the offset from the base of flash where tests
+# can be run. It is important to set this correctly, as an
+# incorrect value could allow the tests to write over critical
+# portions of the FLASH device and possibly render the target
+# board totally non-functional.
+#
+cdl_option CYGNUM_IO_FLASH_TEST_OFFSET {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00100000
+ # value_source default
+ # Default value: 0x00100000
+};
+
+# Length
+# This gives the length of the region of flash used for testing.
+#
+cdl_option CYGNUM_IO_FLASH_TEST_LENGTH {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0x00100000
+ # value_source default
+ # Default value: 0x00100000
+};
+
+# <
+# <
+# Support FLASH memory on Freescale MXC platforms
+#
+cdl_package CYGPKG_DEVS_FLASH_ONMXC {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # ActiveIf constraint: CYGPKG_IO_FLASH
+ # CYGPKG_IO_FLASH == current
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+};
+
+# >
+# MXC platform MMC card support
+# When this option is enabled, it indicates MMC card is
+# supported on the MXC platforms
+#
+cdl_component CYGHWR_DEVS_FLASH_MMC {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+};
+
+# >
+# MXC platform MMC card for newer SDHC controllers
+#
+cdl_option CYGHWR_DEVS_FLASH_MMC_ESDHC {
+ # This option is not active
+ # The parent CYGHWR_DEVS_FLASH_MMC is disabled
+ # ActiveIf constraint: CYGPKG_HAL_ARM_MX37_3STACK || CYGPKG_HAL_ARM_MX35_3STACK || CYGPKG_HAL_ARM_MX25_3STACK || CYGPKG_HAL_ARM_MX51
+ # CYGPKG_HAL_ARM_MX37_3STACK (unknown) == 0
+ # CYGPKG_HAL_ARM_MX35_3STACK (unknown) == 0
+ # CYGPKG_HAL_ARM_MX25_3STACK (unknown) == 0
+ # CYGPKG_HAL_ARM_MX51 (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # --> 1
+};
+
+# MXC platform MMC card for older MMC/SD controllers
+#
+cdl_option CYGHWR_DEVS_FLASH_MMC_SD {
+ # This option is not active
+ # The parent CYGHWR_DEVS_FLASH_MMC is disabled
+ # ActiveIf constraint: CYGPKG_HAL_ARM_MX31_3STACK || CYGPKG_HAL_ARM_MX31ADS
+ # CYGPKG_HAL_ARM_MX31_3STACK (unknown) == 0
+ # CYGPKG_HAL_ARM_MX31ADS (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # --> 1
+};
+
+# <
+# MXC platform NOR flash memory support
+# When this option is enabled, it indicates NOR flash is
+# supported on the MXC platforms
+#
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 0
+
+ # The following properties are affected by this value
+ # option CYGHWR_DEVS_FLASH_IMX_SPI_NOR
+ # Requires: CYGHWR_DEVS_FLASH_MXC_NOR == 1
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+};
+
+# MXC platform NAND flash memory support
+# When this option is enabled, it indicates NAND flash is
+# supported on the MXC platforms
+#
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # The inferred value should not be edited directly.
+ inferred_value 1
+ # value_source inferred
+ # Default value: 0
+ # Requires: CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # CYGSEM_IO_FLASH_READ_INDIRECT == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # component CYGPKG_DEVS_FLASH_NAND_BBT_IN_FLASH
+ # ActiveIf: CYGHWR_DEVS_FLASH_MXC_NAND
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+ # option CYGHWR_DEVS_FLASH_MXC_MULTI
+ # ActiveIf: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+ # interface CYGHWR_DEVS_FLASH_MXC_NAND_RESET_WORKAROUND
+ # ActiveIf: CYGHWR_DEVS_FLASH_MXC_NAND
+};
+
+# i.MX platform SPI NOR flash memory support
+# When this option is enabled, it indicates SPI NOR flash is
+# supported on the i.MX platforms
+#
+cdl_option CYGHWR_DEVS_FLASH_IMX_SPI_NOR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGHWR_DEVS_FLASH_MXC_NOR == 1
+ # CYGHWR_DEVS_FLASH_MXC_NOR == 0
+ # --> 0
+};
+
+# MXC platform ATA support
+# When this option is enabled, it indicates ATA is
+# supported on the MXC platforms
+#
+cdl_option CYGHWR_DEVS_FLASH_MXC_ATA {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Use a flash based Bad Block Table
+#
+cdl_component CYGPKG_DEVS_FLASH_NAND_BBT_IN_FLASH {
+ # ActiveIf constraint: CYGHWR_DEVS_FLASH_MXC_NAND
+ # CYGHWR_DEVS_FLASH_MXC_NAND == 1
+ # --> 1
+
+ # There is no associated value.
+};
+
+# >
+# When this option is enabled, the driver will search for a flash
+# based bad block table
+#
+cdl_option CYGHWR_DEVS_FLASH_MXC_BBT_IN_FLASH {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# header file defining the NAND BBT descriptor
+# defines the name of the header file that describes the BBT layout
+#
+cdl_component CYGHWR_FLASH_NAND_BBT_HEADER {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # The inferred value should not be edited directly.
+ inferred_value 1 <cyg/io/tx37_nand_bbt.h>
+ # value_source inferred
+ # Default value: 0 0
+};
+
+# Number of blocks to reserve for BBT
+# Number of blocks to reserve for BBT
+#
+cdl_option CYGNUM_FLASH_NAND_BBT_BLOCKS {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 4
+ # value_source default
+ # Default value: 4
+};
+
+# <
+# MXC platform multi flash memory support
+# When this option is enabled, it indicates multi flashes are
+# supported on the MXC platforms (like NAND and NOR)
+#
+cdl_option CYGHWR_DEVS_FLASH_MXC_MULTI {
+ # This option is not active
+ # ActiveIf constraint: (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ # (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)
+ # CYGHWR_DEVS_FLASH_MXC_NAND == 1
+ # CYGHWR_DEVS_FLASH_MXC_NOR == 0
+ # CYGHWR_DEVS_FLASH_MXC_NAND == 1
+ # CYGHWR_DEVS_FLASH_MMC == 0
+ # CYGHWR_DEVS_FLASH_MXC_NOR == 0
+ # CYGHWR_DEVS_FLASH_MMC == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+};
+
+# MXC platform NAND flash reset workaround support
+# When this option is enabled, it indicates 0xFFFF is used for
+# the NAND reset command instead of 0xFF.
+#
+cdl_interface CYGHWR_DEVS_FLASH_MXC_NAND_RESET_WORKAROUND {
+ # No options implement this inferface
+ # ActiveIf constraint: CYGHWR_DEVS_FLASH_MXC_NAND
+ # CYGHWR_DEVS_FLASH_MXC_NAND == 1
+ # --> 1
+
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 0
+};
+
+# <
+# <
+# Dynamic memory allocation
+# doc: ref/memalloc.html
+# This package provides memory allocator infrastructure required for
+# dynamic memory allocators, including the ISO standard malloc
+# interface. It also contains some sample implementations.
+#
+cdl_package CYGPKG_MEMALLOC {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+
+ # The following properties are affected by this value
+ # option CYGSEM_COMPRESS_ZLIB_NEEDS_MALLOC
+ # Requires: CYGPKG_MEMALLOC
+};
+
+# >
+# Memory allocator implementations
+# This component contains configuration options related to the
+# various memory allocators available.
+#
+cdl_component CYGPKG_MEMALLOC_ALLOCATORS {
+ # There is no associated value.
+};
+
+# >
+# Fixed block allocator
+# This component contains configuration options related to the
+# fixed block memory allocator.
+#
+cdl_component CYGPKG_MEMALLOC_ALLOCATOR_FIXED {
+ # There is no associated value.
+};
+
+# >
+# Make thread safe
+# With this option enabled, this allocator will be
+# made thread-safe. Additionally allocation functions
+# are made available that allow a thread to wait
+# until memory is available.
+#
+cdl_option CYGSEM_MEMALLOC_ALLOCATOR_FIXED_THREADAWARE {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# Simple variable block allocator
+# This component contains configuration options related to the
+# simple variable block memory allocator. This allocator is not
+# very fast, and in particular does not scale well with large
+# numbers of allocations. It is however very compact in terms of
+# code size and does not have very much overhead per allocation.
+#
+cdl_component CYGPKG_MEMALLOC_ALLOCATOR_VARIABLE {
+ # There is no associated value.
+};
+
+# >
+# Make thread safe
+# With this option enabled, this allocator will be
+# made thread-safe. Additionally allocation functions
+# are added that allow a thread to wait until memory
+# are made available that allow a thread to wait
+# until memory is available.
+#
+cdl_option CYGSEM_MEMALLOC_ALLOCATOR_VARIABLE_THREADAWARE {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Coalesce memory
+# The variable-block memory allocator can perform coalescing
+# of memory whenever the application code releases memory back
+# to the pool. This coalescing reduces the possibility of
+# memory fragmentation problems, but involves extra code and
+# processor cycles.
+#
+cdl_option CYGSEM_MEMALLOC_ALLOCATOR_VARIABLE_COALESCE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+
+ # The following properties are affected by this value
+ # option CYGIMP_MEMALLOC_MALLOC_VARIABLE_SIMPLE
+ # Requires: CYGSEM_MEMALLOC_ALLOCATOR_VARIABLE_COALESCE
+};
+
+# <
+# Doug Lea's malloc
+# This component contains configuration options related to the
+# port of Doug Lea's memory allocator, normally known as
+# dlmalloc. dlmalloc has a reputation for being both fast
+# and space-conserving, as well as resisting fragmentation well.
+# It is a common choice for a general purpose allocator and
+# has been used in both newlib and Linux glibc.
+#
+cdl_component CYGPKG_MEMALLOC_ALLOCATOR_DLMALLOC {
+ # There is no associated value.
+};
+
+# >
+# Debug build
+# Doug Lea's malloc implementation has substantial amounts
+# of internal checking in order to verify the operation
+# and consistency of the allocator. However this imposes
+# substantial overhead on each operation. Therefore this
+# checking may be individually disabled.
+#
+cdl_option CYGDBG_MEMALLOC_ALLOCATOR_DLMALLOC_DEBUG {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0 != CYGDBG_USE_ASSERTS
+ # CYGDBG_USE_ASSERTS == 0
+ # --> 0
+ # Requires: CYGDBG_USE_ASSERTS
+ # CYGDBG_USE_ASSERTS == 0
+ # --> 0
+};
+
+# Make thread safe
+# With this option enabled, this allocator will be
+# made thread-safe. Additionally allocation functions
+# are made available that allow a thread to wait
+# until memory is available.
+#
+cdl_option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_THREADAWARE {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+};
+
+# Support more than one instance
+# Having this option disabled allows important
+# implementation structures to be declared as a single
+# static instance, allowing faster access. However this
+# would fail if there is more than one instance of
+# the dlmalloc allocator class. Therefore this option can
+# be enabled if multiple instances are required. Note: as
+# a special case, if this allocator is used as the
+# implementation of malloc, and it can be determined there
+# is more than one malloc pool, then this option will be
+# silently enabled.
+#
+cdl_option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_SAFE_MULTIPLE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# Use system memmove() and memset()
+# This may be used to control whether memset() and memmove()
+# are used within the implementation. The alternative is
+# to use some macro equivalents, which some people report
+# are faster in some circumstances.
+#
+cdl_option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_USE_MEMCPY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 0 != CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+ # Requires: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+};
+
+# Minimum alignment of allocated blocks
+# This option controls the minimum alignment that the
+# allocated memory blocks are aligned on, specified as
+# 2^N. Note that using large mininum alignments can lead
+# to excessive memory wastage.
+#
+cdl_option CYGNUM_MEMALLOC_ALLOCATOR_DLMALLOC_ALIGNMENT {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 3
+ # value_source default
+ # Default value: 3
+ # Legal values: 3 to 10
+};
+
+# <
+# Variable block allocator with separate metadata
+# This component contains configuration options related to the
+# variable block memory allocator with separate metadata.
+#
+cdl_component CYGPKG_MEMALLOC_ALLOCATOR_SEPMETA {
+ # There is no associated value.
+};
+
+# >
+# Make thread safe
+# With this option enabled, this allocator will be
+# made thread-safe. Additionally allocation functions
+# are made available that allow a thread to wait
+# until memory is available.
+#
+cdl_option CYGSEM_MEMALLOC_ALLOCATOR_SEPMETA_THREADAWARE {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# <
+# <
+# Kernel C API support for memory allocation
+# This option must be enabled to provide the extensions required
+# to support integration into the kernel C API.
+#
+cdl_option CYGFUN_MEMALLOC_KAPI {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_KERNEL
+ # CYGPKG_KERNEL (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: CYGFUN_KERNEL_API_C
+ # CYGFUN_KERNEL_API_C (unknown) == 0
+ # --> 0
+};
+
+# malloc(0) returns NULL
+# This option controls the behavior of malloc(0) ( or calloc with
+# either argument 0 ). It is permitted by the standard to return
+# either a NULL pointer or a unique pointer. Enabling this option
+# forces a NULL pointer to be returned.
+#
+cdl_option CYGSEM_MEMALLOC_MALLOC_ZERO_RETURNS_NULL {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# Breakpoint site when running out of memory
+# Whenever the system runs out of memory, it invokes this function
+# before either going to sleep waiting for memory to become
+# available or returning failure.
+#
+cdl_option CYGSEM_MEMALLOC_INVOKE_OUT_OF_MEMORY {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+};
+
+# malloc() and supporting allocators
+# This component enables support for dynamic memory
+# allocation as supplied by the functions malloc(),
+# free(), calloc() and realloc(). As these
+# functions are often used, but can have quite an
+# overhead, disabling them here can ensure they
+# cannot even be used accidentally when static
+# allocation is preferred. Within this component are
+# various allocators that can be selected for use
+# as the underlying implementation of the dynamic
+# allocation functions.
+#
+cdl_component CYGPKG_MEMALLOC_MALLOC_ALLOCATORS {
+ # ActiveIf constraint: CYGPKG_ISOINFRA
+ # CYGPKG_ISOINFRA == current
+ # --> 1
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
+# >
+# Use external heap definition
+# This option allows other components in the
+# system to override the default system
+# provision of heap memory pools. This should
+# be set to a header which provides the equivalent
+# definitions to <pkgconf/heaps.hxx>.
+#
+cdl_component CYGBLD_MEMALLOC_MALLOC_EXTERNAL_HEAP_H {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# Use external implementation of joining multiple heaps
+# The default implementation of joining multiple heaps
+# is fine for the case where there are multiple disjoint
+# memory regions of the same type. However, in a system
+# there might be e.g. a small amount of internal SRAM and
+# a large amount of external DRAM. The SRAM is faster and
+# the DRAM is slower. An application can implement some
+# heuristic to choose which pool to allocate from. This
+# heuristic can be highly application specific.
+#
+cdl_component CYGBLD_MEMALLOC_MALLOC_EXTERNAL_JOIN_H {
+ # Flavor: booldata
+ # No user value, uncomment the following line to provide one.
+ # user_value 0 0
+ # value_source default
+ # Default value: 0 0
+};
+
+# malloc() allocator implementations
+#
+cdl_interface CYGINT_MEMALLOC_MALLOC_ALLOCATORS {
+ # Implemented by CYGIMP_MEMALLOC_MALLOC_VARIABLE_SIMPLE, active, disabled
+ # Implemented by CYGIMP_MEMALLOC_MALLOC_DLMALLOC, active, enabled
+ # This value cannot be modified here.
+ # Flavor: data
+ # Current_value: 1
+ # Requires: CYGINT_MEMALLOC_MALLOC_ALLOCATORS == 1
+ # CYGINT_MEMALLOC_MALLOC_ALLOCATORS == 1
+ # --> 1
+
+ # The following properties are affected by this value
+ # interface CYGINT_MEMALLOC_MALLOC_ALLOCATORS
+ # Requires: CYGINT_MEMALLOC_MALLOC_ALLOCATORS == 1
+};
+
+# malloc() implementation instantiation data
+# Memory allocator implementations that are capable of being
+# used underneath malloc() must be instantiated. The code
+# to do this is set in this option. It is only intended to
+# be set by the implementation, not the user.
+#
+cdl_option CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value <cyg/memalloc/dlmalloc.hxx>
+ # value_source default
+ # Default value: <cyg/memalloc/dlmalloc.hxx>
+
+ # The following properties are affected by this value
+ # option CYGIMP_MEMALLOC_MALLOC_VARIABLE_SIMPLE
+ # Requires: CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == "<cyg/memalloc/memvar.hxx>"
+ # option CYGIMP_MEMALLOC_MALLOC_DLMALLOC
+ # Requires: CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == "<cyg/memalloc/dlmalloc.hxx>"
+};
+
+# Simple variable block implementation
+# This causes malloc() to use the simple
+# variable block allocator.
+#
+cdl_option CYGIMP_MEMALLOC_MALLOC_VARIABLE_SIMPLE {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Requires: CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == "<cyg/memalloc/memvar.hxx>"
+ # CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == <cyg/memalloc/dlmalloc.hxx>
+ # --> 0
+ # Requires: CYGSEM_MEMALLOC_ALLOCATOR_VARIABLE_COALESCE
+ # CYGSEM_MEMALLOC_ALLOCATOR_VARIABLE_COALESCE == 1
+ # --> 1
+};
+
+# Doug Lea's malloc implementation
+# This causes malloc() to use a version of Doug Lea's
+# malloc (dlmalloc) as the underlying implementation.
+#
+cdl_option CYGIMP_MEMALLOC_MALLOC_DLMALLOC {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == "<cyg/memalloc/dlmalloc.hxx>"
+ # CYGBLD_MEMALLOC_MALLOC_IMPLEMENTATION_HEADER == <cyg/memalloc/dlmalloc.hxx>
+ # --> 1
+};
+
+# <
+# Size of the fallback dynamic memory pool in bytes
+# If *no* heaps are configured in your memory layout,
+# dynamic memory allocation by
+# malloc() and calloc() must be from a fixed-size,
+# contiguous memory pool (note here that it is the
+# pool that is of a fixed size, but malloc() is still
+# able to allocate variable sized chunks of memory
+# from it). This option is the size
+# of that pool, in bytes. Note that not all of
+# this is available for programs to
+# use - some is needed for internal information
+# about memory regions, and some may be lost to
+# ensure that memory allocation only returns
+# memory aligned on word (or double word)
+# boundaries - a very common architecture
+# constraint.
+#
+cdl_option CYGNUM_MEMALLOC_FALLBACK_MALLOC_POOL_SIZE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 16384
+ # value_source default
+ # Default value: 16384
+ # Legal values: 32 to 0x7fffffff
+};
+
+# Common memory allocator package build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_MEMALLOC_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_MEMALLOC_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value "-fno-rtti -Woverloaded-virtual"
+ # value_source default
+ # Default value: "-fno-rtti -Woverloaded-virtual"
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building this package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_MEMALLOC_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value -Wno-pointer-sign
+ # value_source default
+ # Default value: -Wno-pointer-sign
+};
+
+# Tests
+# This option specifies the set of tests for this package.
+#
+cdl_option CYGPKG_MEMALLOC_TESTS {
+ # Calculated value: "tests/dlmalloc1 tests/dlmalloc2 tests/heaptest tests/kmemfix1 tests/kmemvar1 tests/malloc1 tests/malloc2 tests/malloc3 tests/malloc4 tests/memfix1 tests/memfix2 tests/memvar1 tests/memvar2 tests/realloc tests/sepmeta1 tests/sepmeta2"
+ # Flavor: data
+ # Current_value: tests/dlmalloc1 tests/dlmalloc2 tests/heaptest tests/kmemfix1 tests/kmemvar1 tests/malloc1 tests/malloc2 tests/malloc3 tests/malloc4 tests/memfix1 tests/memfix2 tests/memvar1 tests/memvar2 tests/realloc tests/sepmeta1 tests/sepmeta2
+};
+
+# <
+# <
+# Common error code support
+# This package contains the common list of error and
+# status codes. It is held centrally to allow
+# packages to interchange error codes and status
+# codes in a common way, rather than each package
+# having its own conventions for error/status
+# reporting. The error codes are modelled on the
+# POSIX style naming e.g. EINVAL etc. This package
+# also provides the standard strerror() function to
+# convert error codes to textual representation, as
+# well as an implementation of the errno idiom.
+#
+cdl_package CYGPKG_ERROR {
+ # Packages cannot be added or removed, nor can their version be changed,
+ # simply by editing their value. Instead the appropriate configuration
+ # should be used to perform these actions.
+
+ # This value cannot be modified here.
+ # Flavor: booldata
+ # Current value: 1 current
+ # Requires: CYGBLD_ISO_ERRNO_CODES_HEADER == "<cyg/error/codes.h>"
+ # CYGBLD_ISO_ERRNO_CODES_HEADER == <cyg/error/codes.h>
+ # --> 1
+};
+
+# >
+# errno variable
+# This package controls the behaviour of the
+# errno variable (or more strictly, expression)
+# from <errno.h>.
+#
+cdl_component CYGPKG_ERROR_ERRNO {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_ERRNO_HEADER == "<cyg/error/errno.h>"
+ # CYGBLD_ISO_ERRNO_HEADER == <cyg/error/errno.h>
+ # --> 1
+};
+
+# >
+# Per-thread errno
+# This option controls whether the standard error
+# code reporting variable errno is a per-thread
+# variable, rather than global.
+#
+cdl_option CYGSEM_ERROR_PER_THREAD_ERRNO {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
+ # Default value: 1
+ # Requires: CYGVAR_KERNEL_THREADS_DATA
+ # CYGVAR_KERNEL_THREADS_DATA (unknown) == 0
+ # --> 0
+};
+
+# Tracing level
+# Trace verbosity level for debugging the errno
+# retrieval mechanism in errno.cxx. Increase this
+# value to get additional trace output.
+#
+cdl_option CYGNUM_ERROR_ERRNO_TRACE_LEVEL {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
+ # Default value: 0
+ # Legal values: 0 to 1
+};
+
+# <
+# strerror function
+# This package controls the presence and behaviour of the
+# strerror() function from <string.h>
+#
+cdl_option CYGPKG_ERROR_STRERROR {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGBLD_ISO_STRERROR_HEADER == "<cyg/error/strerror.h>"
+ # CYGBLD_ISO_STRERROR_HEADER == <cyg/error/strerror.h>
+ # --> 1
+};
+
+# Error package build options
+# Package specific build options including control over
+# compiler flags used only in building this package,
+# and details of which tests are built.
+#
+cdl_component CYGPKG_ERROR_OPTIONS {
+ # There is no associated value.
+};
+
+# >
+# Additional compiler flags
+# This option modifies the set of compiler flags for
+# building the error package. These flags are used in addition
+# to the set of global flags.
+#
+cdl_option CYGPKG_ERROR_CFLAGS_ADD {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# Suppressed compiler flags
+# This option modifies the set of compiler flags for
+# building the error package. These flags are removed from
+# the set of global flags if present.
+#
+cdl_option CYGPKG_ERROR_CFLAGS_REMOVE {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value ""
+ # value_source default
+ # Default value: ""
+};
+
+# <
+# <
+# <
+
+2008-07-12 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * sgml/doclist: added USB Serial documentation
+
+2006-12-16 Uwe.Kindler <uwe.kindler@cetoni.de>
+
+ * sgml/doclist: Added CAN documentation.
+
+2006-09-25 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * sgml/doclist: added MMC disk documentation
+
+2006-06-16 Anthony Tonizzo <atonizzo@gmail.com>
+
+ * sgml/doclist: add ATHTTPD documentation
+
2005-04-21 Bart Veer <bartv@ecoscentric.com>
* sgml/doclist: add I2C and DS1307 documentation
io/flash/current/doc/flash.sgml
io/spi/current/doc/spi.sgml
io/i2c/current/doc/i2c.sgml
+io/can/current/doc/can.sgml
compat/posix/current/doc/posix.sgml
compat/uitron/current/doc/uitron.sgml
net/common/current/doc/tcpip.sgml
net/httpd/current/doc/httpd.sgml
net/ftpclient/current/doc/ftpclient.sgml
net/sntp/current/doc/sntp.sgml
+net/athttpd/current/doc/athttpd.sgml
services/memalloc/common/current/doc/memalloc.sgml
services/crc/current/doc/crc.sgml
services/cpuload/current/doc/cpuload.sgml
services/power/common/current/doc/power.sgml
io/usb/slave/current/doc/usbs.sgml
io/usb/eth/slave/current/doc/usbseth.sgml
+io/usb/serial/slave/current/doc/usbs_serial.sgml
hal/synth/arch/current/doc/synth.sgml
devs/usb/sa11x0/current/doc/usbs_sa11x0.sgml
devs/usb/nec_upd985xx/current/doc/usbs_upd985xx.sgml
devs/eth/synth/ecosynth/current/doc/syntheth.sgml
devs/watchdog/synth/current/doc/synth_watchdog.sgml
devs/wallclock/dallas/ds1307/current/doc/ds1307.sgml
+devs/disk/generic/mmc/current/doc/disk_mmc.sgml
\ No newline at end of file
cat ${ECOS_INSTALL_DIR}/include/pkgconf/ecos.mak >>Make.params
+#
+# Add CFLAGS manipulation - this should match <ecos>/packages/pkgconf/rules.mak
+#
+
+cat <<EOF >>Make.params
+
+#
+# Modify CFLAGS to match newer compilers
+#
+ACTUAL_CFLAGS = \$(ECOS_GLOBAL_CFLAGS)
+ACTUAL_CXXFLAGS = \$(ECOS_GLOBAL_CFLAGS)
+ACTUAL_LDFLAGS = \$(ECOS_GLOBAL_LDFLAGS)
+# GCC since 2.95 does -finit-priority by default so remove it from old HALs
+ACTUAL_CFLAGS := \$(subst -finit-priority,,\$(ACTUAL_CFLAGS))
+
+# -fvtable-gc is known to be broken in all recent GCC.
+ACTUAL_CFLAGS := \$(subst -fvtable-gc,,\$(ACTUAL_CFLAGS))
+
+# Expand inline functions
+ACTUAL_CFLAGS := -finline-limit=7000 \$(ACTUAL_CFLAGS)
+
+# Separate C++ flags out from C flags.
+ACTUAL_CFLAGS := \$(subst -fno-rtti,,\$(ACTUAL_CFLAGS))
+ACTUAL_CFLAGS := \$(subst -frtti,,\$(ACTUAL_CFLAGS))
+ACTUAL_CFLAGS := \$(subst -Woverloaded-virtual,,\$(ACTUAL_CFLAGS))
+ACTUAL_CFLAGS := \$(subst -fvtable-gc,,\$(ACTUAL_CFLAGS))
+
+ACTUAL_CXXFLAGS := \$(subst -Wstrict-prototypes,,\$(ACTUAL_CXXFLAGS))
+
+EOF
# Simple build rules
.c.o:
- \$(CC) -c \$(ECOS_GLOBAL_CFLAGS) -I\$(PREFIX)/include \$*.c
+ \$(CC) -c \$(ACTUAL_CFLAGS) -I\$(PREFIX)/include \$*.c
.o:
- \$(CC) \$(ECOS_GLOBAL_LDFLAGS) -L\$(PREFIX)/lib -Ttarget.ld \$*.o -o \$@
+ \$(CC) \$(ACTUAL_LDFLAGS) -L\$(PREFIX)/lib -Ttarget.ld \$*.o -o \$@
SRCS=${SRCS-source_file.c}
OBJS=\${SRCS:%.c=%.o}
+2008-07-08 Uwe Kindler <uwe_kindler@web.de>
+
+ * NEWS:
+ * ecos.db: Add EA LPC2468 OEM board, target, flash driver,
+ LPC24XXX variant + serial driver
+
+2008-06-07 Frank Pagliughi <fpagliughi@mindspring.com>
+
+ * NEWS:
+ * ecos.db: Add USB serial class driver.
+
+2008-01-06 Lars Poeschel <larsi@wh2.tu-dresden.de>
+
+ * NEWS
+ * ecos.db: Add FR30, skmb91302 board from Fujitsu
+
+2008-01-04 Uwe Kindler <uwe_kindler@web.de>
+
+ * NEWS:
+ * ecos.db: Add phyCORE229x platform, target, ethernet driver and
+ flash driver
+
+2007-07-02 uwe.kindler <uwe.kindler@cetoni.de>
+
+ * ecos.db CAN driver for LPC2xxx. Updated entry for loop
+ CAN device driver.
+
+2007-04-08 uwe.kindler <uwe.kindler@cetoni.de>
+
+ * ecos.db Ethernet driver for Olimex SAM7-EX256
+
+2007-03-26 uwe.kindler <uwe.kindler@cetoni.de>
+
+ * ecos.db CAN driver for AT91.
+
+2007-02-13 John Eigelaar <jeigelaar@mweb.co.za>
+ Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * ecos.db: Ethernet device driver for AT91 EMAC.
+
+2007-01-10 Ilija Koco <ilijak@siva.com.mk>
+
+ * ecos.db: Splitted esci directory in esci/drv and esci/hdr
+
+2007-01-02 Uwe Kindler <uwe_kindler@web.de>
+
+ * ecos.db Add Olimex SAM7-EX256 platform and target
+
+2006-11-21 Alexander Neundorf <alexander.neundorf@jenoptik.com>
+
+ * ecos.db: add generic interrupt driven serial IO driver
+ for PXA 2X0 platforms
+
+2006-10-16 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * ecos.db: Comment out CYGPKG_DEVS_ETH_ARM_AT91 for now - it's still
+ work in progress apparently.
+
+2006-09-21 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * ecos.db: add MMC/SPI device driver.
+
+2006-08-06 Bart Veer <bartv@ecoscentric.com>
+
+ * ecos.db: add M68K/MCF52xx ColdFire I2C driver
+
+2006-07-18 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * ecos.db: Add AT-HTTPD package from Anthony Tonizzo.
+
+2006-06-19 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * ecos.db: Remove entries for none existing packages.
+
+2006-06-08 Ilija Koco <ilijak@siva.com.mk>
+
+ * ecos.db: Add Freescale MAC7100EVB platform and target
+
+2006-06-09 Frank Pagliughi <fpagliughi@mindspring.com>
+
+ * ecos.db: Add Philips D12 USB device driver and hardware specific
+ package for i386.
+
+2006-06-06 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * ecos.db: Remove the hardware property from the USB and USB slave
+ package. They themselves are not hardware dependent.
+
+2006-06-02 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * ecos.db: Add AT91SAM7SEK and AT91SAM7XEK packages and targets
+
+2006-05-24 Ilija Koco <ilijak@siva.com.mk>
+
+ * ecos.db: Add Freescale MAC7100 variant, SIvA MACE1 platform
+ and Freescale ESCI serial driver
+
+2006-05-09 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * ecos.db: Add the Coldfire architecture HAL, the mcf5272 varient
+ HAL and the m5272c3 platform HAL.
+
+2006-05-07 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * ecos.db: Add AT91 USB device driver.
+
+2006-02-22 Mark Salter <msalter@redhat.com>
+
+ * ecos.db: Added net autotest.
+
+2006-01-01 Andrew Lunn <andrew.lunn@ascom.ch>
+ Oliver Munz <munz@speag.ch>
+
+ * ecos.db: Added support for the AT91SAM7S. This includes a new
+ flash driver, watchdog driver, minor changes to the AT91 USART
+ driver, and extensions to the AT91 variant HAL in addition to the
+ AT91SAM7S HAL.
+
2005-06-28 Nick Garnett <nickg@ecoscentric.com>
* ecos.db: Added Object Loader package.
+* Port to Embedded Artists LPC2468 OEM board by Uwe Kindler.
+* USB serial class driver by Frank Pagliughi.
+* FR30 arch, mb91301 variant and skmb91302 platform by Lars Poeschel.
+* phyCORE-LPC2294/92 port including flash and CAN by Uwe Kindler.
+* AT91 CAN driver by Uwe Kindler.
+* AT91 Ethernet device driver for EMAC by John Eigelaar and Andrew Lunn.
+* MMC/SPI driver provided by eCosCentric Ltd.
+* USB device driver for Philips D12.
+* Port to ATMEL AT91SAM7X by John Eigelaar
+* Freescale MAC7100 varient and SIva MACE1 platfrom by Ilija Koco.
+* Coldfire architecture HAL, the mcf5272 varient HAL and the m5272c3
+ platform HAL. Contributed by Enrico Piria.
+* AT91 USB device driver by Oliver Munz and Andrew Lunn
+* Port to the ATMEL AT91SAM7S by Oliver Munz and Andrew Lunn
+* Improved varient support for the AT91
* Support for the Ethenet device on the NETARM devices.
* Added support for the AT91 based PhyCore.
* Added support for Exys XSEngine (PXA255) based system.
+2005-09-21 Steven_cheng <05071@alphanetworks.com>
+
+ * include/linux/types.h: Added unsigned types.
+
2005-03-27 Andrew Lunn <andrew.lunn@ascom.ch>
* include/linux/kernel.h (PTR_ERR): Should be an unsigned long,
#define uint8_t cyg_uint8
#define uint16_t cyg_uint16
#define uint32_t cyg_uint32
+
+#define int8_t cyg_int8
+#define int16_t cyg_int16
+#define int32_t cyg_int32
+
#define loff_t off_t
+
#define kvec iovec
#endif /* __LINUX_TYPES_H__ */
+2008-03-28 John Dallaway <jld@ecoscentric.com>
+
+ * tests/tm_basic.cxx: Rename test to tm_posix.cxx.
+ * tests/mqueue1.c: Rename test to pmqueue1.c.
+ * tests/mqueue2.c: Rename test to pmqueue2.c.
+ * tests/mutex3.c: Rename test to pmutex3.c.
+ * cdl/posix.cdl: Accommodate the above renaming. Test names must be
+ globally unique.
+
+2007-06-12 Richard.Yuan <lemonskin@tom.com>
+
+ * src/except.cxx (install_handlers): Fixed typo. Bug #1000373
+
+2006-07-18 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * src/signal.cxx (pause): Although already POSIX compliant, if we wait
+ for all signals, behaviour is more Linux-like.
+
+2006-06-13 Dan Jakubiec <dan.jakubiec@systech.com>
+
+ * src/time.cxx: (nanosleep): Fixed to return EINTR when it is
+ interrupted by a signal. This in turn fixed sleep() to return the
+ number of unelapsed seconds when interrupted by a signal.
+
+2006-06-12 Klaas Gadeyne <klaas.gadeyne@fmtc.be>
+
+ * src/pthread.cxx (pthread_create): name is only defined if
+ CYGVAR_KERNEL_THREADS_NAME is set to 1
+
+2005-10-23 Andrew Lunn <andrew.lunn@ascom.ch>
+2005-10-18 Alexander Neundorf <neundorf@kde.org>
+
+ * src/time.cxx: add gettimeofday() implementation
+ * cdl/posix.cdl: make some descriptions a bit more verbose. move
+ mutex.cxx into its own component (CYGPKG_POSIX_PTHREAD_MUTEX).
+ move compilation of mqueue.cxx into the CYGPKG_POSIX_MQUEUES
+ component. Fixed the tests so that only the ones which stand a
+ chance of compling are compiled.
+ * include/sys/time.h (new): Header file which implements sys/time.h
+ * include/pthread.h: Include time.h for struct timespec
+ * include/mutex.h: Include time.h for struct timespec
+
2004-10-01 Oyvind Harboe <oyvind.harboe@zylin.com>
* src/signal.cxx: place the CYGBLD_ATTRIB_INIT_PRI such that it
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2008 eCosCentric Limited
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
display "POSIX compatibility layer"
description "This package enables the POSIX compatibility
layer that implements IEEE 1003.1."
+
doc ref/posix-compatibility.html
include_dir cyg/posix
requires CYGINT_ISO_ERRNO_CODES
requires CYGIMP_KERNEL_SCHED_SORTED_QUEUES
- implements CYGINT_ISO_SCHED_IMPL
implements CYGINT_ISO_POSIX_LIMITS
- implements CYGINT_ISO_PMUTEXTYPES
- implements CYGINT_ISO_PTHREAD_MUTEX
requires { CYGBLD_ISO_POSIX_LIMITS_HEADER == \
"<cyg/posix/limits.h>" }
requires { CYGBLD_ISO_PMUTEXTYPES_HEADER == \
requires { CYGBLD_ISO_PTHREAD_MUTEX_HEADER == \
"<cyg/posix/mutex.h>" }
- compile mqueue.cxx mutex.cxx misc.cxx
+ compile misc.cxx
compile -library=libextras.a startup.cxx
- cdl_option _POSIX_THREAD_PRIO_INHERIT {
- display "POSIX mutex priority inheritance feature test macro"
- flavor bool
- default_value 1
- requires CYGSEM_KERNEL_SYNCH_MUTEX_PRIORITY_INVERSION_PROTOCOL_INHERIT
- description "This option defines the POSIX feature test macro
- for supporting priority inheritance protocol in
- mutexes."
- }
+ cdl_component CYGPKG_POSIX_PTHREAD_MUTEX {
+
+ display "POSIX pthread mutexes"
+ flavor bool
+ default_value 1
+ implements CYGINT_ISO_PMUTEXTYPES
+ implements CYGINT_ISO_PTHREAD_MUTEX
+ description "
+ This component provides support for POSIX pthreads
+ mutexes."
+
+ compile mutex.cxx
+
+ cdl_option _POSIX_THREAD_PRIO_INHERIT {
+ display "POSIX mutex priority inheritance feature test macro"
+ flavor bool
+ default_value 1
+ requires CYGSEM_KERNEL_SYNCH_MUTEX_PRIORITY_INVERSION_PROTOCOL_INHERIT
+ description "
+ This option defines the POSIX feature test macro for
+ supporting priority inheritance protocol in mutexes."
+ }
- cdl_option _POSIX_THREAD_PRIO_PROTECT {
- display "POSIX mutex priority ceiling feature test macro"
- flavor bool
- default_value 1
- requires CYGSEM_KERNEL_SYNCH_MUTEX_PRIORITY_INVERSION_PROTOCOL_CEILING
- description "This option defines the POSIX feature test macro
- for supporting priority ceiling protocol in mutexes."
+ cdl_option _POSIX_THREAD_PRIO_PROTECT {
+ display "POSIX mutex priority ceiling feature test macro"
+ flavor bool
+ default_value 1
+ requires CYGSEM_KERNEL_SYNCH_MUTEX_PRIORITY_INVERSION_PROTOCOL_CEILING
+ description "
+ This option defines the POSIX feature test macro for
+ supporting priority ceiling protocol in mutexes."
+ }
}
# ----------------------------------------------------------------
display "POSIX scheduling configuration"
flavor bool
default_value 1
- description "This component provides controls over scheduling
- in POSIX."
+ implements CYGINT_ISO_SCHED_IMPL
requires CYGPKG_POSIX_CLOCKS
+
+ description "
+ This component provides controls over scheduling in POSIX."
+
compile sched.cxx
cdl_option _POSIX_PRIORITY_SCHEDULING {
flavor bool
calculated 1
requires CYGSEM_KERNEL_SCHED_MLQUEUE
- description "This option defines the POSIX feature test macro
- that indicates that priority scheduling is present.
- This should not be undefined."
+ description "
+ This option defines the POSIX feature test macro that
+ indicates that priority scheduling is present. This
+ should not be undefined."
}
}
display "POSIX pthread configuration"
flavor bool
default_value 1
- description "This component provides configuration controls for
- the POSIX pthreads package."
- compile pthread.cxx
+ description "
+ This component provides configuration controls for the
+ POSIX pthreads package."
+
script pthread.cdl
+ compile pthread.cxx
+
}
# ----------------------------------------------------------------
- # Timers component
+ # Clock component
cdl_option CYGPKG_POSIX_CLOCKS {
display "POSIX clocks"
"<cyg/posix/time.h>" }
requires { CYGBLD_ISO_POSIX_CLOCKS_HEADER == \
"<cyg/posix/time.h>" }
+ requires { CYGBLD_ISO_STRUCTTIMEVAL_HEADER == \
+ "<cyg/posix/sys/time.h>" }
requires CYGPKG_KERNEL
requires CYGVAR_KERNEL_COUNTERS_CLOCK
+
+ description "
+ This component provides configuration controls for
+ the POSIX clocks and the sleep(), nanosleep() and
+ gettimeofday() functions."
+
compile time.cxx
- description "This component provides configuration controls for
- the POSIX clocks."
+
}
# ----------------------------------------------------------------
requires CYGPKG_KERNEL
requires CYGVAR_KERNEL_COUNTERS_CLOCK
requires CYGPKG_POSIX_PTHREAD
- requires CYGPKG_POSIX_CLOCKS
requires CYGPKG_POSIX_SIGNALS
- description "This component provides configuration controls for
- the POSIX timers."
+ requires CYGINT_ISO_POSIX_CLOCKS
+ description "
+ This component provides configuration controls for
+ the POSIX timers."
}
# ----------------------------------------------------------------
display "POSIX message queues"
flavor bool
default_value 1
+ compile mqueue.cxx
implements CYGINT_ISO_MQUEUE
requires CYGPKG_KERNEL
requires CYGINT_ISO_MALLOC
requires CYGINT_ISO_ERRNO
requires CYGINT_ISO_STRING_STRFUNCS
+ requires CYGINT_ISO_PTHREAD_MUTEX
+ requires CYGPKG_POSIX_CLOCKS
description "This component provides configuration controls for
POSIX message queues."
"<cyg/posix/signal.h>" }
requires { CYGBLD_ISO_SIGNAL_IMPL_HEADER == \
"<cyg/posix/signal.h>" }
- description "This component provides configuration controls for
- the POSIX signals."
+ description "
+ This component provides configuration controls for
+ the POSIX signals."
+
compile signal.cxx except.cxx
}
default_value 1
requires { CYGBLD_ISO_UTSNAME_HEADER == \
"<cyg/posix/utsname.h>" }
- description "This component provides configuration controls for
- the POSIX utsname structure and the uname() function."
+ description "
+ This component provides configuration controls for
+ the POSIX utsname structure and the uname() function."
cdl_option CYG_POSIX_UTSNAME_LENGTH {
display "Length of name strings in utsname structure"
# ----------------------------------------------------------------
# Tests
- cdl_option CYGPKG_POSIX_TESTS {
- display "POSIX tests"
- flavor data
- no_define
- calculated {
- "tests/pthread1 tests/pthread2 tests/pthread3 tests/mutex3 tests/mqueue2"
- . ((CYGPKG_POSIX_SIGNALS) ? " tests/mqueue1 tests/signal1 tests/signal2 tests/signal3 tests/sigsetjmp tests/timer1 tests/tm_basic" : "")
+ cdl_option CYGPKG_POSIX_TESTS {
+ display "POSIX tests"
+ flavor data
+ no_define
+ calculated {
+ (CYGPKG_POSIX_PTHREAD ? "tests/pthread1 tests/pthread2 tests/pthread3 "
+ : "") .
+ (CYGPKG_POSIX_PTHREAD_MUTEX ? "tests/pmutex3 " : "") .
+ (CYGPKG_POSIX_MQUEUES ? "tests/pmqueue1 tests/pmqueue2 " : "") .
+ (CYGPKG_POSIX_SIGNALS ? "tests/signal1 tests/signal2 tests/signal3 \
+ tests/sigsetjmp " : "") .
+ ((CYGPKG_POSIX_SIGNALS &&
+ CYGPKG_POSIX_TIMERS &&
+ CYGPKG_POSIX_SEMAPHORES) ? "tests/timer1 " : "") .
+ ((CYGPKG_POSIX_SIGNALS &&
+ CYGPKG_POSIX_TIMERS &&
+ CYGPKG_POSIX_PTHREAD &&
+ CYGPKG_POSIX_SEMAPHORES) ? "tests/tm_posix " : "")
}
description "
This option specifies the set of tests for the POSIX package."
# ====================================================================
cdl_option CYGPKG_POSIX_PTHREAD_REQUIREMENTS {
- display "Generic requirements of pthread package"
- flavor bool
- calculated 1
+ display "Generic requirements of pthread package"
+ flavor bool
+ calculated 1
implements CYGINT_ISO_PTHREADTYPES
implements CYGINT_ISO_PTHREAD_IMPL
- requires CYGPKG_POSIX_SCHED
- requires CYGSEM_KERNEL_SCHED_TIMESLICE_ENABLE
- requires CYGSEM_KERNEL_SCHED_ASR_SUPPORT
- requires CYGSEM_KERNEL_SCHED_ASR_GLOBAL
- requires !CYGSEM_KERNEL_SCHED_ASR_DATA_GLOBAL
- requires CYGFUN_KERNEL_THREADS_STACK_LIMIT
+ requires CYGPKG_POSIX_SCHED
+ requires CYGSEM_KERNEL_SCHED_TIMESLICE_ENABLE
+ requires CYGSEM_KERNEL_SCHED_ASR_SUPPORT
+ requires CYGSEM_KERNEL_SCHED_ASR_GLOBAL
+ requires !CYGSEM_KERNEL_SCHED_ASR_DATA_GLOBAL
+ requires CYGFUN_KERNEL_THREADS_STACK_LIMIT
requires { CYGBLD_ISO_PTHREADTYPES_HEADER == \
"<cyg/posix/types.h>" }
requires { CYGBLD_ISO_PTHREAD_IMPL_HEADER == \
"<cyg/posix/pthread.h>" }
- description "This option exists merely to carry the pthread
+ description "This option exists merely to carry the pthread
package requirements."
}
cdl_component CYGPKG_POSIX_PTHREAD_VALUES {
display "Constant values used in pthread package"
flavor bool
- calculated 1
+ calculated 1
description "These are values that are either configurable, or derived
from system parameters."
cdl_option CYGNUM_POSIX_PTHREAD_DESTRUCTOR_ITERATIONS {
- display "Maximum number of iterations of key destructors"
- flavor data
- legal_values 4 to 100
- default_value 4
- description "Maximum number of iterations of key destructors allowed."
+ display "Maximum number of iterations of key destructors"
+ flavor data
+ legal_values 4 to 100
+ default_value 4
+ description "Maximum number of iterations of key destructors allowed."
}
cdl_option CYGNUM_POSIX_PTHREAD_KEYS_MAX {
- display "Maximum number of per-thread data keys allowed"
- flavor data
- legal_values 128 to 65535
- default_value 128
- description "Number of per-thread data keys supported."
+ display "Maximum number of per-thread data keys allowed"
+ flavor data
+ legal_values 128 to 65535
+ default_value 128
+ description "Number of per-thread data keys supported."
}
cdl_option CYGNUM_POSIX_PTHREAD_THREADS_MAX {
- display "Maximum number of threads allowed"
- flavor data
- legal_values 64 to 1024
- default_value 64
- description "Maximum number of threads supported."
+ display "Maximum number of threads allowed"
+ flavor data
+ legal_values 64 to 1024
+ default_value 64
+ description "Maximum number of threads supported."
}
}
# ====================================================================
cdl_component CYGPKG_POSIX_PTHREAD_FEATURES {
- display "Fixed Feature test macros for POSIX"
- flavor bool
- calculated 1
- description "These options define POSIX feature test macros that
- describe the eCos implementation of pthreads. These
- are not changeable configuration options."
+ display "Fixed Feature test macros for POSIX"
+ flavor bool
+ calculated 1
+ description "These options define POSIX feature test macros that
+ describe the eCos implementation of pthreads. These
+ are not changeable configuration options."
cdl_option _POSIX_THREADS {
- display "POSIX thread support feature test macro"
- flavor bool
- calculated 1
- requires CYGSEM_KERNEL_SCHED_TIMESLICE
- requires CYGVAR_KERNEL_THREADS_DATA
- description "This option defines the POSIX feature test macro
- for thread support."
+ display "POSIX thread support feature test macro"
+ flavor bool
+ calculated 1
+ requires CYGSEM_KERNEL_SCHED_TIMESLICE
+ requires CYGVAR_KERNEL_THREADS_DATA
+ description "This option defines the POSIX feature test macro
+ for thread support."
}
cdl_option _POSIX_THREAD_PRIORITY_SCHEDULING {
- display "POSIX thread priority scheduling feature test macro"
- flavor bool
- calculated 1
- requires CYGSEM_KERNEL_SCHED_MLQUEUE
+ display "POSIX thread priority scheduling feature test macro"
+ flavor bool
+ calculated 1
+ requires CYGSEM_KERNEL_SCHED_MLQUEUE
requires _POSIX_THREADS
- description "This option defines the POSIX feature test macro
- for thread priority scheduling support."
+ description "This option defines the POSIX feature test macro
+ for thread priority scheduling support."
}
cdl_option _POSIX_THREAD_ATTR_STACKADDR {
- display "POSIX stack address attribute feature test macro"
- flavor bool
- calculated 1
- description "This option defines the POSIX feature test macro
- for supporting the thread stack address in the thread
- attribute object."
+ display "POSIX stack address attribute feature test macro"
+ flavor bool
+ calculated 1
+ description "This option defines the POSIX feature test macro
+ for supporting the thread stack address in the thread
+ attribute object."
}
cdl_option _POSIX_THREAD_ATTR_STACKSIZE {
- display "POSIX stack size attribute feature test macro"
- flavor bool
- calculated 1
- description "This option defines the POSIX feature test macro
- for supporting the thread stack size in the thread
- attribute object."
+ display "POSIX stack size attribute feature test macro"
+ flavor bool
+ calculated 1
+ description "This option defines the POSIX feature test macro
+ for supporting the thread stack size in the thread
+ attribute object."
}
cdl_option _POSIX_THREAD_PROCESS_SHARED {
- display "POSIX process shared attribute feature test macro"
- flavor bool
- calculated 0
- description "This option defines the POSIX feature test macro
- for supporting process shared mutexes. Since eCos
- does not have processes, this attribute is undefined."
+ display "POSIX process shared attribute feature test macro"
+ flavor bool
+ calculated 0
+ description "This option defines the POSIX feature test macro
+ for supporting process shared mutexes. Since eCos
+ does not have processes, this attribute is undefined."
}
}
# ====================================================================
cdl_component CYGPKG_POSIX_MAIN_THREAD {
- display "Main thread configuration"
- flavor bool
- calculated 1
- requires { 0 != CYGPKG_LIBC_STARTUP }
- requires CYGSEM_LIBC_STARTUP_MAIN_OTHER
+ display "Main thread configuration"
+ flavor bool
+ calculated 1
+ requires { 0 != CYGPKG_LIBC_STARTUP }
+ requires CYGSEM_LIBC_STARTUP_MAIN_OTHER
implements CYGINT_LIBC_STARTUP_EXTERNAL_INVOKE_MAIN_POSSIBLE
- description "These options control the thread used to
+ description "These options control the thread used to
run the main() application entry routine."
-
- cdl_option CYGNUM_POSIX_MAIN_DEFAULT_PRIORITY {
- display "main()'s default thread priority"
- flavor data
- legal_values 0 to 31
- default_value 16
- description "
+
+ cdl_option CYGNUM_POSIX_MAIN_DEFAULT_PRIORITY {
+ display "main()'s default thread priority"
+ flavor data
+ legal_values 0 to 31
+ default_value 16
+ description "
POSIX compatibility requires that the application's
main() function be invoked in a thread.
- This option controls the priority of that thread. This
+ This option controls the priority of that thread. This
priority is the POSIX priority and is NOT the same as
an eCos thread priority. With POSIX thread priorities,
lower numbers are lower priority, and higher numbers are
higher priority."
- }
+ }
}
# ====================================================================
# End of pthread.cdl
-
-
int timer_gettime( timer_t timerid, struct itimerspec *value );
int timer_getoverrun( timer_t timerid );
int nanosleep( const struct timespec *rqtp, struct timespec *rmtp);
+int gettimeofday(struct timeval *tv, struct timezone* tz);
</screen>
</sect2>
#include <pkgconf/posix.h>
#include <sys/types.h> // pthread_* types
-
+#include <time.h>
//=============================================================================
// Mutexes
#include <sys/types.h>
#include <sched.h> // SCHED_*
-
+#include <time.h>
//=============================================================================
// General thread operations
{
thread->register_exception( exception_signal_mapping[i].exception,
cyg_posix_exception_handler,
- exception_signal_mapping[i].signal,,
+ exception_signal_mapping[i].signal,
NULL,
NULL);
}
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
#include "pprivate.h" // POSIX private header
#include <unistd.h>
+#ifdef CYGPKG_POSIX_UTSNAME
#include <sys/utsname.h> // My header
+#endif
#include <string.h> // strcpy
#include <limits.h>
#include <time.h>
// -------------------------------------------------------------------------
// uname()
+#ifdef CYGPKG_POSIX_UTSNAME
__externC int uname( struct utsname *name )
{
CYG_REPORT_FUNCTYPE( "returning %d" );
CYG_REPORT_RETVAL(0);
return 0;
}
+#endif
// -------------------------------------------------------------------------
// sysconf()
SC_CASE( _SC_GETGR_R_SIZE_MAX, 0 );
SC_CASE( _SC_GETPW_R_SIZE_MAX, 0 );
SC_CASE( _SC_LOGIN_NAME_MAX, LOGIN_NAME_MAX );
+#ifdef CYGPKG_POSIX_MQUEUES
SC_CASE( _SC_MQ_OPEN_MAX, MQ_OPEN_MAX );
SC_CASE( _SC_MQ_PRIO_MAX, MQ_PRIO_MAX );
+#endif
SC_CASE( _SC_NGROUPS_MAX, NGROUPS_MAX );
SC_CASE( _SC_OPEN_MAX, OPEN_MAX );
SC_CASE( _SC_PAGESIZE, PAGESIZE );
SC_CASE( _SC_RTSIG_MAX, RTSIG_MAX );
+#ifdef CYGPKG_POSIX_SEMAPHORES
SC_CASE( _SC_SEM_NSEMS_MAX, SEM_NSEMS_MAX );
SC_CASE( _SC_SEM_VALUE_MAX, SEM_VALUE_MAX );
+#endif
SC_CASE( _SC_SIGQUEUE_MAX, SIGQUEUE_MAX );
SC_CASE( _SC_STREAM_MAX, STREAM_MAX );
#ifdef CYGPKG_POSIX_PTHREAD
#include <pkgconf/posix.h>
-#ifdef CYGPKG_POSIX_MQUEUES
-
#include <pkgconf/kernel.h>
/* INCLUDES */
//------------------------------------------------------------------------
-#endif // ifdef CYGPKG_POSIX_MQUEUES
-
/* EOF mqueue.cxx */
Cyg_Thread ( PTHREAD_ECOS_PRIORITY(use_attr.schedparam.sched_priority),
pthread_entry,
(CYG_ADDRWORD)nthread,
+#ifdef CYGVAR_KERNEL_THREADS_NAME
name,
+#else
+ NULL,
+#endif
stackbase,
stacksize);
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2002 Nick Garnett
+// Copyright (C) 2004 eCosCentric Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Check for any pending signals that can be delivered and
// if there are none, wait for a signal to be generated
- if( !cyg_deliver_signals() )
+ while( !cyg_deliver_signals() )
signal_sigwait.wait();
- // Now check again for some signals to deliver
- cyg_deliver_signals();
-
signal_mutex.unlock();
SIGNAL_RETURN(EINTR);
#include <pkgconf/posix.h>
-#ifdef CYGPKG_POSIX_CLOCKS
-
#include <pkgconf/hal.h>
#include <pkgconf/kernel.h>
#include "pprivate.h" // POSIX private header
#include <time.h> // our header
+#include <sys/time.h>
#include <cyg/kernel/thread.hxx>
#include <cyg/kernel/clock.hxx>
+#include <cyg/kernel/kapi.h>
#include <cyg/kernel/thread.inl>
#include <cyg/kernel/clock.inl>
ticks -= (now-then);
cyg_ticks_to_timespec( ticks, rmtp );
+
+ // Check for cancellation and then notify the caller that we
+ // were interrupted.
+ PTHREAD_TESTCANCEL();
+ TIME_RETURN(EINTR);
}
// check if we were woken up because we were cancelled.
TIME_RETURN(0);
}
-#endif // ifdef CYGPKG_POSIX_CLOCKS
+// -------------------------------------------------------------------------
+// gettimeofday()
+// Get the current time in a struct timeval
+externC int gettimeofday(struct timeval* tv, struct timezone* tz)
+{
+ int ticks_per_second = 1000000000/
+ (CYGNUM_HAL_RTC_NUMERATOR/CYGNUM_HAL_RTC_DENOMINATOR);
+ cyg_tick_count_t cur_time = cyg_current_time();
+ int tix = cur_time % ticks_per_second;
+ tv->tv_sec = cur_time / ticks_per_second;
+ tv->tv_usec = (tix * 1000000)/ticks_per_second;
+ return 0;
+}
+
// -------------------------------------------------------------------------
// EOF time.cxx
#define NA_MSG "POSIX signals not enabled"
#elif !defined(CYGPKG_POSIX_PTHREAD)
#define NA_MSG "POSIX threads not enabled"
+#elif !defined(CYGPKG_POSIX_SEMAPHORES)
+#define NA_MSG "POSIX semaphores not enabled"
#endif
#ifdef NA_MSG
#define NA_MSG "POSIX signals not enabled"
#elif !defined(CYGPKG_POSIX_PTHREAD)
#define NA_MSG "POSIX threads not enabled"
+#elif !defined(CYGPKG_POSIX_SEMAPHORES)
+#define NA_MSG "POSIX semaphores not enabled"
#endif
#ifdef NA_MSG
#define NA_MSG "No POSIX signals"
#elif !defined(CYGPKG_POSIX_TIMERS)
#define NA_MSG "No POSIX timers"
+#elif !defined(CYGPKG_POSIX_SEMAPHORES)
+#define NA_MSG "POSIX semaphores not enabled"
#endif
#ifdef NA_MSG
+2006-10-12 Nick Garnett <nickg@ecoscentric.com>
+
+ * cdl/uitron.cdl: Add reqirement for UITRON conformant mailbox
+ implementation to CYGIMP_UITRON_STRICT_CONFORMANCE.
+
2005-08-02 Andrew Lunn <andrew.lunn@ascom.ch>
* tests/test2.c (task1): Cast to fix compiler warning.
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2006 eCosCentric Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2006 eCosCentric Ltd.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
-##
-## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
requires CYGSEM_KERNEL_SCHED_MLQUEUE
requires !CYGSEM_KERNEL_SCHED_TIMESLICE
requires CYGFUN_KERNEL_THREADS_TIMER
+ requires !CYGIMP_MBOX_USE_MBOXT_PLAIN
implements CYGINT_UITRON_CONFORMANCE
description "
Require the rest of the system configuration
+2007-08-28 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * tests/can_overrun1.c (can0_thread): Fix the length of the data
+ in the message. Add a delay to allow the CAN device to process
+ the packets.
+ * test/can_txcevent.c: (can0_thread): Add a delay to allow the CAN device
+ to process the packet.s
+ * src/loop_can.c (FIFO_SIZE): Changed to one more than the TX
+ queue size. If it is less, the loopback tests don't pass because
+ packets don't get transmitted.
+
+2007-08-24 Andrew Lunn <andrew.lunn>
+
+ * doc/synth_test.ecm: Import file for running the tests on synth.
+
+2007-08-24 Alexey Shusharin <mrfinch@mail.ru>
+
+ * tests/can_callback.c: Added test of CAN callback on event
+ * cdl/can_loop.cdl: Added can_callback.c into tests list
+
+2007-08-09 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/loop_can.c: Change all CYGPKG_IO_CAN_* to CYGPKG_DEVS_CAN_*
+ so that the loopback driver gets compiled. It looks like
+ at some point in its life it used to live in io/can instead
+ of its current location in dev/can/loop.
+
+2007-03-23 Uwe Kindler <uwe_kindler@web.de>
+
+ * cdl/can_loop.cd: Changed naming of various options from
+ xxx_IO_CAN_LOOP into xxx_DEVS_CAN_LOOP
+
+2007-03-23 Uwe Kindler <uwe_kindler@web.de>
+
+ * cdl/can_loop.cdl: Driver now implements the interfaces
+ CYGINT_IO_CAN_TX_EVENTS, CYGINT_IO_CAN_STD_CAN_ID,
+ CYGINT_IO_CAN_EXT_CAN_ID.
+ Removed CYGPKG_IO_CAN_LOOP_CFLAGS_ADD and
+ CYGPKG_IO_CAN_LOOP_CFLAGS_REMOVE because they had no function.
+
+ * src/loop_can.c: Added missing function loop_can_get_config
+ to make the driver build properly.
+
+ * tests: Did some fixes and cleanups for all test cases to make them
+ work properly with the changes in the CAN I/O layer.
+
2005-08-15 Uwe Kindler <uwe_kindler@web.de>
* Loopback CAN driver created
#
# ====================================================================
-cdl_package CYGPKG_IO_CAN_LOOP {
+cdl_package CYGPKG_DEVS_CAN_LOOP {
display "Loop CAN device drivers"
parent CYGPKG_IO_CAN_DEVICES
# Support up to two CAN loop device.
for { set ::loopcan 0 } { $::loopcan < 2 } { incr ::loopcan } {
- cdl_component CYGPKG_IO_CAN_LOOP_CAN[set ::loopcan] {
+ cdl_component CYGPKG_DEVS_CAN_LOOP_CAN[set ::loopcan] {
display "LOOP CAN channel [set ::loopcan] driver"
flavor bool
default_value 0
implements CYGINT_IO_CAN_TIMESTAMP
+ implements CYGINT_IO_CAN_TX_EVENTS
+ implements CYGINT_IO_CAN_STD_CAN_ID
+ implements CYGINT_IO_CAN_EXT_CAN_ID
description "
This option includes the CAN loop device driver for channel [set ::loopcan]."
}
- cdl_component CYGPKG_IO_CAN_LOOP_OPTIONS {
+ cdl_component CYGPKG_DEVS_CAN_LOOP_OPTIONS {
display "CAN device driver build options"
flavor none
description "
compiler flags used only in building this package,
and details of which tests are built."
-
- cdl_option CYGPKG_IO_CAN_LOOP_CFLAGS_ADD {
- display "Additional compiler flags"
- flavor data
- no_define
- default_value { "" }
- description "
- This option modifies the set of compiler flags for
- building these CAN device drivers. These flags
- are used in addition to the set of global flags."
- }
-
- cdl_option CYGPKG_IO_CAN_LOOP_CFLAGS_REMOVE {
- display "Suppressed compiler flags"
- flavor data
- no_define
- default_value { "" }
- description "
- This option modifies the set of compiler flags for
- building these CAN device drivers. These flags are
- removed from the set of global flags if present."
- }
- cdl_option CYGPKG_IO_CAN_LOOP_TESTS {
+ cdl_option CYGPKG_DEVS_CAN_LOOP_TESTS {
display "CAN loop device driver tests"
flavor data
- calculated { "tests/can_rdwr tests/can_timeout tests/can_txevent tests/can_overrun1 tests/can_overrun2 tests/can_nonblock"}
+ calculated { "tests/can_rdwr tests/can_timeout tests/can_txevent tests/can_overrun1 tests/can_overrun2 tests/can_nonblock tests/can_callback" }
description "
This option specifies the set of tests for the CAN loop device drivers."
}
#include <pkgconf/hal.h>
#include <pkgconf/io_can.h>
-#include <pkgconf/io_can_loop.h>
+#include <pkgconf/devs_can_loop.h>
#include <cyg/hal/hal_io.h>
#include <cyg/io/io.h>
#include <cyg/hal/hal_intr.h>
#include <cyg/kernel/kapi.h>
-#ifdef CYGPKG_IO_CAN_LOOP
+#ifdef CYGPKG_DEVS_CAN_LOOP
//-------------------------------------------------------------------------
static bool loop_can_getevent(can_channel *priv, cyg_can_event *pevent, void *pdata);
static Cyg_ErrNo loop_can_set_config(can_channel *chan, cyg_uint32 key,
const void *xbuf, cyg_uint32 *len);
+static Cyg_ErrNo loop_can_get_config(can_channel *chan, cyg_uint32 key,
+ const void* buf, cyg_uint32* len);
static void loop_can_start_xmit(can_channel *chan);
static void loop_can_stop_xmit(can_channel *chan);
//-------------------------------------------------------------------------
// Transfer FIFOs
-#define FIFO_SIZE 16
+#define FIFO_SIZE 33
struct fifo
{
CAN_LOWLEVEL_FUNS(loop_can_lowlevel_funs,
loop_can_putmsg,
loop_can_getevent,
+ loop_can_get_config,
loop_can_set_config,
loop_can_start_xmit,
loop_can_stop_xmit
//-------------------------------------------------------------------------
// Hardware info for each serial line
-#ifdef CYGPKG_IO_CAN_LOOP_CAN0
+#ifdef CYGPKG_DEVS_CAN_LOOP_CAN0
static loop_can_info loop_can_info0 = {
&fifo0,
&fifo1
static cyg_can_event loop_can_rxbuf0[CYGNUM_DEVS_CAN_LOOP_CAN0_QUEUESIZE_RX];
#endif // CYGPKG_IO_SERIAL_LOOP_SERIAL0
-#ifdef CYGPKG_IO_CAN_LOOP_CAN1
+#ifdef CYGPKG_DEVS_CAN_LOOP_CAN1
static loop_can_info loop_can_info1 = {
&fifo1,
&fifo0
//-------------------------------------------------------------------------
// Channel descriptions:
//
-#ifdef CYGPKG_IO_CAN_LOOP_CAN0
+#ifdef CYGPKG_DEVS_CAN_LOOP_CAN0
CAN_CHANNEL_USING_INTERRUPTS(loop_can0_chan,
loop_can_lowlevel_funs,
loop_can_info0,
loop_can_txbuf0, CYGNUM_DEVS_CAN_LOOP_CAN0_QUEUESIZE_TX,
loop_can_rxbuf0, CYGNUM_DEVS_CAN_LOOP_CAN0_QUEUESIZE_RX
);
-#endif // CYGPKG_IO_CAN_LOOP_CAN1
+#endif // CYGPKG_DEVS_CAN_LOOP_CAN1
-#ifdef CYGPKG_IO_CAN_LOOP_CAN1
+#ifdef CYGPKG_DEVS_CAN_LOOP_CAN1
CAN_CHANNEL_USING_INTERRUPTS(loop_can1_chan,
loop_can_lowlevel_funs,
loop_can_info1,
loop_can_txbuf1, CYGNUM_DEVS_CAN_LOOP_CAN1_QUEUESIZE_TX,
loop_can_rxbuf1, CYGNUM_DEVS_CAN_LOOP_CAN1_QUEUESIZE_RX
);
-#endif // CYGPKG_IO_CAN_LOOP_CAN1
+#endif // CYGPKG_DEVS_CAN_LOOP_CAN1
//-------------------------------------------------------------------------
// And finally, the device table entries:
//
-#ifdef CYGPKG_IO_CAN_LOOP_CAN0
+#ifdef CYGPKG_DEVS_CAN_LOOP_CAN0
DEVTAB_ENTRY(loop_can_io0,
CYGDAT_DEVS_CAN_LOOP_CAN0_NAME,
0, // Does not depend on a lower level interface
loop_can_lookup, // CAN driver may need initializing
&loop_can0_chan
);
-#endif // CYGPKG_IO_CAN_LOOP_CAN0
+#endif // CYGPKG_DEVS_CAN_LOOP_CAN0
-#ifdef CYGPKG_IO_CAN_LOOP_CAN1
+#ifdef CYGPKG_DEVS_CAN_LOOP_CAN1
DEVTAB_ENTRY(loop_can_io1,
CYGDAT_DEVS_CAN_LOOP_CAN1_NAME,
0, // Does not depend on a lower level interface
loop_can_lookup, // CAN driver may need initializing
&loop_can1_chan
);
-#endif // CYGPKG_IO_CAN_LOOP_CAN1
+#endif // CYGPKG_DEVS_CAN_LOOP_CAN1
//-------------------------------------------------------------------------
loop_can_info *loop_chan = (loop_can_info *)chan->dev_priv;
struct fifo *fwr = loop_chan->write_fifo;
+#ifdef CYGOPT_IO_CAN_TX_EVENT_SUPPORT
struct fifo *frd = loop_chan->read_fifo;
+#endif
if( fwr->num == FIFO_SIZE )
{
return ENOERR;
}
+//-------------------------------------------------------------------------
+// Query device configuration
+
+static Cyg_ErrNo
+loop_can_get_config(can_channel *chan, cyg_uint32 key,
+ const void* buf, cyg_uint32* len)
+{
+ return ENOERR;
+}
+
//-------------------------------------------------------------------------
// Enable the transmitter on the device
//==========================================================================
//
-// flexcan_load.c
+// can_nonblock.c
//
-// FlexCAN load test
+// CAN driver test of nonblocking calls
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// Author(s): Uwe Kindler
// Contributors: Uwe Kindler
// Date: 2005-08-14
-// Description: FlexCAN load test
+// Description: CAN driver test of nonblocking callst
//####DESCRIPTIONEND####
#include <cyg/kernel/kapi.h>
// Package option requirements
-#if defined(CYGOPT_IO_CAN_SUPPORT_NONBLOCKING) && !defined(CYGOPT_IO_CAN_SUPPORT_TIMEOUTS)
+#if defined(CYGOPT_IO_CAN_SUPPORT_NONBLOCKING)
//===========================================================================
// DATA TYPES
cyg_uint32 len;
cyg_uint32 blocking;
cyg_can_event rx_event;
+ Cyg_ErrNo res;
blocking = 0;
len = sizeof(blocking);
CYG_TEST_FAIL_FINISH("Error writing config of /dev/can0");
}
- len = sizeof(rx_event);
+ len = sizeof(rx_event);
+ res = cyg_io_read(hDrvFlexCAN, &rx_event, &len);
- if (-EAGAIN == cyg_io_read(hDrvFlexCAN, &rx_event, &len))
+ if (-EAGAIN == res)
{
CYG_TEST_PASS_FINISH("can_test1 test OK");
}
+ else if (-EINTR == res)
+ {
+ CYG_TEST_PASS_FINISH("can_test1 test OK");
+ }
else
{
CYG_TEST_FAIL_FINISH("Error reading from /dev/can0");
}
//
- // create the two threads which access the CAN device driver
- // a reader thread with a higher priority and a writer thread
- // with a lower priority
+ // create the main thread
//
cyg_thread_create(4, can0_thread,
(cyg_addrword_t) 0,
cyg_scheduler_start();
}
-#else // #if defined(CYGOPT_IO_CAN_SUPPORT_NONBLOCKING) && !defined(CYGOPT_IO_CAN_SUPPORT_TIMEOUTS
-#define N_A_MSG "Needs nonblocking calls and disabled timeouts"
+#else // #if defined(CYGOPT_IO_CAN_SUPPORT_NONBLOCKING)
+#define N_A_MSG "Needs nonblocking calls"
#endif
#else // CYGFUN_KERNEL_API_C
}
#endif // N_A_MSG
-// EOF flexcan_load.c
+// EOF can_nonblock.c
cyg_can_message tx_msg =
{
0x000, // CAN identifier
- {0x00, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7}, // 8 data bytes
+ data :
+ {
+ {0x00, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }// 8 data bytes
+ },
CYGNUM_CAN_ID_STD, // standard frame
CYGNUM_CAN_FRAME_DATA, // data frame
- 0, // data length code
+ 1, // data length code
};
if (ENOERR != cyg_io_lookup("/dev/can0", &hCAN0))
diag_printf("Sending %d CAN messages to /dev/can0\n", buf_info.rx_bufsize + 1);
for (i = 0; i <= buf_info.rx_bufsize; ++i)
{
- tx_msg.id = 0x000 + i;
- tx_msg.data[0] = i;
+ CYG_CAN_MSG_SET_STD_ID(tx_msg, 0x000 + i);
+ CYG_CAN_MSG_SET_DATA(tx_msg, 0, i);
len = sizeof(tx_msg);
if (ENOERR != cyg_io_write(hCAN0, &tx_msg, &len))
print_can_msg(&tx_msg, "");
}
}
+
+ //
+ // Give the loop back driver time to process all those messages.
+ //
+ cyg_thread_delay(10);
//
// now check if receive queue is completely filled - that means number of rx events should
if (rx_event.flags & CYGNUM_CAN_EVENT_TX)
{
print_can_msg(&rx_event.msg, "");
- if (rx_event.msg.data[0] != (i + 1))
+ if (rx_event.msg.data.bytes[0] != (i + 1))
{
CYG_TEST_FAIL_FINISH("Received /dev/can0 TX event contains invalid data");
}
cyg_can_message tx_msg =
{
0x000, // CAN identifier
- {0x00, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7}, // 8 data bytes
+ data :
+ {
+ {0x00, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }// 8 data bytes
+ },
CYGNUM_CAN_ID_STD, // standard frame
CYGNUM_CAN_FRAME_DATA, // data frame
2, // data length code
CYG_TEST_FAIL_FINISH("Unexpected RX event for /dev/can0");
}
- rx_bufsize = *((cyg_uint32 *)rx_event.msg.data);
+ rx_bufsize = *((cyg_uint32 *)rx_event.msg.data.bytes);
//
// now we send exactly one CAN message more than there is space in the receive buffer
// we store the message number as CAN id and in first data byte so
// a receiver can check this later
//
- tx_msg.id = 0x000 + i;
- tx_msg.data[0] = i;
+ CYG_CAN_MSG_SET_STD_ID(tx_msg, 0x000 + i);
+ CYG_CAN_MSG_SET_DATA(tx_msg, 0, i);
len = sizeof(tx_msg);
if (ENOERR != cyg_io_write(hCAN0, &tx_msg, &len))
// endianess here because this is a loopback driver test and we will receive
// our own messages
//
- *((cyg_uint32 *)tx_msg.data) = rx_buf_info.rx_bufsize;
+ *((cyg_uint32 *)tx_msg.data.bytes) = rx_buf_info.rx_bufsize;
len = sizeof(tx_msg);
//
if (rx_event.flags & CYGNUM_CAN_EVENT_RX)
{
print_can_msg(&rx_event.msg, "");
- if (rx_event.msg.data[0] != (i + 1))
+ if (rx_event.msg.data.bytes[0] != (i + 1))
{
CYG_TEST_FAIL_FINISH("Received /dev/can1 RX event contains invalid data");
}
cyg_thread_entry_t can1_thread;
thread_data_t can1_thread_data;
+cyg_sem_t sem_wait;
+
//===========================================================================
// LOCAL FUNCTIONS
cyg_can_buf_info_t tx_buf_info;
cyg_can_message tx_msg =
{
- 0x000, // CAN identifier
- {0x00, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7}, // 8 data bytes
- CYGNUM_CAN_ID_STD, // standard frame
- CYGNUM_CAN_FRAME_DATA, // data frame
- 8, // data length code
+ 0x000, // CAN identifier
+ data :
+ {
+ {0x00, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7}, // 8 data bytes
+ },
+ CYGNUM_CAN_ID_STD, // standard frame
+ CYGNUM_CAN_FRAME_DATA, // data frame
+ 8, // data length code
};
if (ENOERR != cyg_io_lookup("/dev/can0", &hCAN0))
// we store the message number as CAN id and in first data byte so
// a receiver can check this later
//
- tx_msg.id = 0x000 + i;
- tx_msg.data[0] = i;
+ CYG_CAN_MSG_SET_STD_ID(tx_msg, 0x000 + i);
+ CYG_CAN_MSG_SET_DATA(tx_msg, 0, i);
len = sizeof(tx_msg);
if (ENOERR != cyg_io_write(hCAN0, &tx_msg, &len))
{
print_can_msg(&tx_msg, "");
}
- }
+ } // for (i = 0; i < 10; ++i)
//
- // Now we we give the reader thread a chance to run and to read
- // the messages
+ // Give reader thread 200 ticks time for readung all messages. The reader thread
+ // signals the semaphore if it received all transmitted messages
//
- cyg_thread_delay(100);
- CYG_TEST_FAIL_FINISH("Error reading from /dev/can0");
- }
+ if (!cyg_semaphore_timed_wait( &sem_wait, cyg_current_time( ) + 200 ))
+ {
+ CYG_TEST_FAIL_FINISH("Waiting for reader thread timed out.");
+ }
+ else
+ {
+ CYG_TEST_PASS_FINISH("can_rdwr test OK");
+ }
+ } // while (1)
}
// The writer thread stored the message number in CAN id and first
// data byte so we can check now if we received valid data
//
- if ((rx_event.msg.id != i) || (rx_event.msg.data[0] != i))
+ if ((rx_event.msg.id != i) || (rx_event.msg.data.bytes[0] != i))
{
CYG_TEST_FAIL_FINISH("Received CAN message contains unexpected data");
}
}
} //for (i = 0; i < 10; ++i)
- CYG_TEST_PASS_FINISH("can_rdwr test OK");
+ //
+ // signal successfull reception of all messages
+ //
+ cyg_semaphore_post(&sem_wait);
} // while (1)
}
{
CYG_TEST_INIT();
+ //
+ // Initialize the wait semaphore to 0
+ //
+ cyg_semaphore_init( &sem_wait, 0 );
+
//
// create the two threads which access the CAN device driver
//
if (pmsg->rtr)
{
- diag_printf("%s [ID:%03X] [RTR:%d] [EXT:%d]\n",
+ diag_printf("%s [ID:%03X] [RTR:%d] [EXT:%d] [DLC:%d]\n",
pMsg,
pmsg->id,
pmsg->rtr,
- pmsg->ext);
+ pmsg->ext,
+ pmsg->dlc);
return;
}
pmsg->id,
pmsg->rtr,
pmsg->ext,
- pmsg->data[0],
- pmsg->data[1],
- pmsg->data[2],
- pmsg->data[3],
- pmsg->data[4],
- pmsg->data[5],
- pmsg->data[6],
- pmsg->data[7]);
+ pmsg->data.bytes[0],
+ pmsg->data.bytes[1],
+ pmsg->data.bytes[2],
+ pmsg->data.bytes[3],
+ pmsg->data.bytes[4],
+ pmsg->data.bytes[5],
+ pmsg->data.bytes[6],
+ pmsg->data.bytes[7]);
}
"ESTY ",
"ALOS ",
"DEVC ",
+ "PHYF ",
+ "PHYH ",
+ "PHYL "
};
i = 0;
while (flags && (i < 16))
timeout_info.tx_timeout = timeout;
timeout_info.rx_timeout = timeout;
+ len = sizeof(timeout_info);
if (ENOERR != cyg_io_set_config(hCAN, CYG_IO_SET_CONFIG_CAN_TIMEOUT ,&timeout_info, &len))
{
CYG_TEST_FAIL_FINISH("Error writing config of /dev/can0");
cyg_can_message tx_msg =
{
0x000, // CAN identifier
- {0x00, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7}, // 8 data bytes
+ data :
+ {
+ {0x00, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }// 8 data bytes
+ },
CYGNUM_CAN_ID_STD, // standard frame
CYGNUM_CAN_FRAME_DATA, // data frame
4, // data length code
diag_printf("Sending %d CAN messages to /dev/can0 \n", buf_info.rx_bufsize);
for (i = 0; i < buf_info.rx_bufsize; ++i)
{
- tx_msg.id = i;
- tx_msg.data[0] = i;
+ CYG_CAN_MSG_SET_STD_ID(tx_msg, 0x000 + i);
+ CYG_CAN_MSG_SET_DATA(tx_msg, 0, i);
len = sizeof(tx_msg);
if (ENOERR != cyg_io_write(hCAN0, &tx_msg, &len))
}
}
+ //
+ // Give the loop back driver time to process all those messages.
+ //
+ cyg_thread_delay(10);
+
//
// now we read the buffer info - we expect a completely filled recieve queue
//
// Now check if TX events contain valid data - we know that the ID and the first
// data byte contain the message number
//
- if ((rx_event.msg.id != i) || (rx_event.msg.data[0] != i))
+ if ((rx_event.msg.id != i) || (rx_event.msg.data.bytes[0] != i))
{
CYG_TEST_FAIL_FINISH("Received invalid data in TX event");
}
+2007-03-23 Uwe Kindler <uwe_kindler@web.de>
+
+ * cdl/can_mcf52xx.cdl Removed interfaces
+ CYGINT_DEVS_CAN_MCF52xx_FLEXCAN_SUPP_STD_CAN_ID and
+ CYGINT_DEVS_CAN_MCF52xx_FLEXCAN_SUPP_EXT_CAN_ID. The generic
+ CAN I/O layer provides some similar interfaces now.
+ Driver now implements the new CAN I/O interfaces
+ CYGINT_IO_CAN_TIMESTAMP, CYGINT_IO_CAN_RUNTIME_MBOX_CFG
+ CYGINT_IO_CAN_REMOTE_BUF and CYGINT_IO_CAN_TX_EVENTS,
+ CYGINT_IO_CAN_STD_CAN_ID, CYGINT_IO_CAN_EXT_CAN_ID
+ Removed make commands for removed test cases.
+ Removed cdl component CYGPKG_DEVS_CAN_MCF52xx_FLEXCAN_OPTIONS
+ because it did not have any functionality.
+
+ * src/can_mcf52xx.c Replaced
+ CYGINT_DEVS_CAN_MCF52xx_FLEXCAN_SUPP_EXT_CAN_ID with
+ generic CAN I/O option CYGOPT_IO_CAN_EXT_CAN_ID and
+ CYGINT_DEVS_CAN_MCF52xx_FLEXCAN_SUPP_STD_CAN_ID with
+ generic CAN I/O option CYGOPT_IO_CAN_STD_CAN_ID
+ Implemented CAN mode CYGNUM_CAN_MODE_CONFIG.
+ Changed old access to CAN data (byte array) to access
+ to new cyg_can_msg_data type.
+
+ * tests/flexcan_filter: removed. This tast case is now part of
+ generic CAN I/O layer.
+
+ * tests/flexcan_load: removed. This tast case is now part of
+ generic CAN I/O layer.
+
+ * tests/flexcan_remote: removed. This tast case is now part of
+ generic CAN I/O layer.
+
+ * tets/flexcan_wake: Did some code cleaning.
+
+2006-02-15 Uwe Kindler <uwe_kindler@web.de>
+
+ * cdl/can_mcf52xx.cdl Added two interfaces
+ CYGINT_DEVS_CAN_MCF52xx_FLEXCAN_SUPP_STD_CAN_ID and
+ CYGINT_DEVS_CAN_MCF52xx_FLEXCAN_SUPP_EXT_CAN_ID.
+ The number of standard and extended message boxes is now
+ configurable:
+ CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]_STD_MBOXES
+ CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]_EXT_MBOXES
+ Channged default TX buffer to 15.
+
+ * src/can_mcf52xx.c Added initialisation macro for second
+ FlexCAN modul. Driver partly rewritten - support of up to
+ 15 message buffers when reception of all CAN frames is
+ configured - improves performance when "bursts" of CAN
+ messages arrive. Changed message buffer configuration -
+ only the config key CYG_IO_SET_CONFIG_CAN_MSGBUF is
+ supported now. The exact configuration option is defined
+ in new data field cyg_can_msgbuf_cfg_id in cyg_can_msgbuf_cfg
+ structure.
+
+ * tests/flexcan_filter.c
+ * tests/flexcan_wake.c
+ * tests/flexcan_remote.c
+ * tests/flexcan_load.c
+ Changed message buffer configuration to support of new
+ config key CYG_IO_SET_CONFIG_CAN_MSGBUF. Removed baudrate
+ runtime configuration of 250 kBaud - now default
+ value is used.
+
+2005-09-20 Uwe Kindler <uwe_kindler@web.de>
+
+ * src/can_mcf52xx.c Only support events of tx message buffers
+ in flexcan_getevent() if CYGOPT_IO_CAN_TX_EVENT_SUPPORT is
+ active.
+
+2005-09-11 Uwe Kindler <uwe_kindler@web.de>
+
+ * cdl/can_mcf52xx.cdl Default message buffer configuration
+ changed. Message buffer 13 now is transmit message buffer.
+ Message buffers 14 and 15 are no receive message buffers
+ for all standard and extended frames.
+
+ * src/can_mcf52xx.c Driver partly rewritten. Support for message
+ filtering added. Message buffer handling added. Several bugs
+ fixed. Support added for configuration options
+ CYG_IO_SET_CONFIG_CAN_REMOTE_BUF
+ CYG_IO_SET_CONFIG_CAN_FILTER_MSG
+ CYG_IO_SET_CONFIG_CAN_FILTER_ALL
+ CYG_IO_SET_CONFIG_CAN_MODE
+ CYG_IO_GET_CONFIG_CAN_STATE
+ CYG_IO_GET_CONFIG_CAN_MSGBUF_INFO
+ CYG_IO_GET_CONFIG_CAN_HDI
+
+ * tests/flexcan_filter.c Test of message filtering addded
+ * tests/flexcan_wake.c Test of mode setting and standby mode of
+ FlexCAN module added.
+
2005-05-24 Uwe Kindler <uwe_kindler@web.de>
* mcf52xx FlexCAN driver package created
puts $::cdl_system_header "/***** CAN driver proc output end *****/"
}
+
# Support up to two on-chip FlexCAN modules. The number varies between
# processor variants
for { set ::flexcan 0 } { $::flexcan < 2 } { incr ::flexcan } {
flavor bool
active_if CYGINT_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]
default_value 1
- implements CYGINT_IO_CAN_TIMESTAMP
+ implements CYGINT_IO_CAN_TIMESTAMP
+ implements CYGINT_IO_CAN_RUNTIME_MBOX_CFG
+ implements CYGINT_IO_CAN_REMOTE_BUF
+ implements CYGINT_IO_CAN_TX_EVENTS
description "
If the application needs to access the on-chip FlexCAN[set ::flexcan]
cdl_option CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]_QUEUESIZE_TX {
display "Size of TX Queue for the FlexCAN [set ::flexcan] driver"
flavor data
- default_value 32
- legal_values 16 to 512
+ default_value 64
+ legal_values 16 to 1024
description "
The CAN device driver will run in interrupt mode and will
perform buffering of outgoing data. This option controls the number
cdl_option CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]_QUEUESIZE_RX {
display "Size of RX Queue for the FlexCAN [set ::flexcan] driver"
flavor data
- default_value 32
- legal_values 16 to 512
+ default_value 128
+ legal_values 16 to 1024
description "
The CAN device driver will run in interrupt mode and will
perform buffering of incoming data. This option controls the number
of CAN events the RX queue can store."
}
- cdl_option CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]_RXMASK_GLOBAL {
- display "Receive mask for message buffers 0 - 13"
- flavor data
- default_value 0x1FFFFFFF
- description "
- The global RX-mask is composed of 4 bytes. The mask bits are
- applied to all Rx-Identifiers excluding Rx-buffers 14-15, that
- have their specific Rx-mask. (0 corresponding incoming ID bit is
- \"don\92t care\". 1 corresponding ID bit is checked against the incoming
- ID bit, to see if a match exists). By default the message buffers
- should only receive messages that exactly match the configured
- message buffer CAN identifier - that means alle bits are 1."
- }
-
- cdl_option CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]_RXMASK_14 {
- display "Receive mask for message buffer 14"
- flavor data
- default_value 0x0
- description "
- The RX-mask for message buffer 14 is composed of 4 bytes. The mask
- bits are applied to message buffer 14. (0 corresponding incoming ID
- bit is \"don\92t care\". 1 corresponding ID bit is checked against the
- incoming ID bit, to see if a match exists). Message buffer 14 is
- the receive message buffer and should receive all available CAN
- messages - all bits are 0."
- }
-
- cdl_option CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]_RXMASK_15 {
- display "Receive mask for message buffer 15"
- flavor data
- default_value 0x1FFFFFFF
- description "
- The RX-mask for message buffer 15 is composed of 4 bytes. The mask
- bits are applied to message buffer 15. (0 corresponding incoming ID
- bit is \"don\92t care\". 1 corresponding ID bit is checked against the
- incoming ID bit, to see if a match exists)."
- }
-
cdl_option CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN[set ::flexcan]_WAKEINT {
display "Wake interrupt priority"
flavor data
Interrupt priority for bus off interrupt."
}
- cdl_option CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]_DEFAULT_RX_MBOX {
- display "Default receive message buffer"
- flavor data
- calculated 14
- legal_values 0 to 15
- description "
- By default one message buffer will be used for reception of
- all CAN messages. This option selects one of the 16 message
- buffers for reception."
- }
-
cdl_option CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]_DEFAULT_TX_MBOX {
- display "Default transmit message buffer"
+ display "Default TX buffer"
flavor data
calculated 15
- legal_values 0 to 15
description "
By default one message buffer will be used for message transmission.
This option selects one of the 16 FlexCAN message buffers for
transmission."
}
+ cdl_option CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]_STD_MBOXES {
+ display "11 Bit standard ID msg. buffers"
+ flavor booldata
+ requires CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]_STD_MBOXES + CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]_EXT_MBOXES < 16
+ implements CYGINT_IO_CAN_STD_CAN_ID
+ default_value 7
+ legal_values 1 to 15
+ description "
+ The FlexCAN module contains 16 message buffers. One message buffer
+ is reserved for message transmission. The remaining 15 buffers are
+ available for reception of messages. This configuration option
+ defines the number of message boxes for reception of CAN messages
+ with standard identifier. This configuration option does not matter
+ when you configure message filters at runtime. Only if the FlexCAN
+ modul is configured to receive all available standard CAN identifiers
+ (0 - 0x7FF), then this configuration option is important. If you get
+ RX overrun events, you should raise the number of message boxes or
+ lower the CAN baud rate."
+ }
+
+ cdl_option CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]_EXT_MBOXES {
+ display "29 Bit extended ID msg. buffers"
+ flavor booldata
+ requires CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]_STD_MBOXES + CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]_EXT_MBOXES < 16
+ implements CYGINT_IO_CAN_EXT_CAN_ID
+ default_value 8
+ legal_values 1 to 15
+ description "
+ The FlexCAN module contain 16 message buffers. One message buffer
+ is reserved for message transmission. The remaining 15 buffers are
+ available for reception of messages. This configuration option
+ defines the number of message boxes for reception of CAN messages
+ with extended identifier. This configuration option does not matter
+ when you configure message filters at runtime. Only if the FlexCAN
+ modul is configured to receive all available standard CAN identifiers
+ (0 - 0x7FF), then this configuration option is important. If you get
+ RX overrun events, you should raise the number of message boxes or
+ lower the CAN baud rate."
+ }
+
cdl_component CYGPKG_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]_MBOXCFG {
display "Message buffer configuration"
flavor none
data length, each configurable as Rx or Tx, all supporting standard and
extended messages. At the moment a fixed configuration is used for
TX and RX message buffers but in future this may be configurable."
-
- cdl_component CYGPKG_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]_MBOX14_CFG {
- display "Message buffer 14 configuration"
- flavor none
- active_if CYGINT_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]
- description "
- Configuration of FlexCAN message buffer 14."
-
- cdl_option CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN[set ::flexcan]_MBOX14 {
- display "Interrupt priority."
- flavor data
- default_value is_loaded(CYGNUM_HAL_M68K_MCF52xx_ISR_DEFAULT_PRIORITY_FLEXCAN[set ::flexcan]_MBOX14) ? \
- CYGNUM_HAL_M68K_MCF52xx_ISR_DEFAULT_PRIORITY_FLEXCAN[set ::flexcan]_MBOX14 : \
- CYGNUM_HAL_M68K_MCF52xx_ISR_PRIORITY_MIN
- legal_values CYGNUM_HAL_M68K_MCF52xx_ISR_PRIORITY_MIN to CYGNUM_HAL_M68K_MCF52xx_ISR_PRIORITY_MAX
- description "
- Interrupt priority for message buffer 14"
- }
- cdl_option CYGPKG_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]_MBOX14_IS_TX {
- display "Use for transmit"
- flavor bool
- active_if CYGINT_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]
- calculated 0
- description "
- This option controls if this message buffer is used for sending
- or receiving messages. Currently this option is not configurable
- and message box 14 is used for reception of CAN messages."
-
- }
- }
-
- cdl_component CYGPKG_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]_MBOX15_CFG {
- display "Message buffer 15 configuration"
- flavor none
- active_if CYGINT_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]
- description "
- Configuration of FlexCAN message buffer 15."
-
- cdl_option CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN[set ::flexcan]_MBOX15 {
- display "Interrupt priority."
+
+ # Support all 16 message buffers.
+ for { set ::mbox 0 } { $::mbox < 16 } { incr ::mbox } {
+
+ cdl_option CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN[set ::flexcan]_MBOX[set ::mbox] {
+ display "Interrupt priority for message buffer [set ::mbox]"
flavor data
- default_value is_loaded(CYGNUM_HAL_M68K_MCF52xx_ISR_DEFAULT_PRIORITY_FLEXCAN[set ::flexcan]_MBOX15) ? \
- CYGNUM_HAL_M68K_MCF52xx_ISR_DEFAULT_PRIORITY_FLEXCAN[set ::flexcan]_MBOX15 : \
+ default_value is_loaded(CYGNUM_HAL_M68K_MCF52xx_ISR_DEFAULT_PRIORITY_FLEXCAN[set ::flexcan]_MBOX[set ::mbox]) ? \
+ CYGNUM_HAL_M68K_MCF52xx_ISR_DEFAULT_PRIORITY_FLEXCAN[set ::flexcan]_MBOX[set ::mbox] : \
CYGNUM_HAL_M68K_MCF52xx_ISR_PRIORITY_MIN
legal_values CYGNUM_HAL_M68K_MCF52xx_ISR_PRIORITY_MIN to CYGNUM_HAL_M68K_MCF52xx_ISR_PRIORITY_MAX
description "
- Interrupt priority for message buffer 15"
+ Interrupt priority for message buffer [set ::mbox]. Normally this should be
+ the default interrupt priority provided by HAL."
}
-
- cdl_option CYGOPT_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]_MBOX15_IS_TX {
- display "Use for transmit"
- flavor bool
- active_if CYGINT_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]
- calculated 1
- description "
- This option controls if this message buffer is used for sending
- or receiving messages. Currently this option is not configurable
- and message box 15 is used for transmission of CAN messages."
-
- }
- }
+ }
}
}
}
testing infrastructure. All tests require a properly configured
CAN network with a second CAN node that can send and receive
CAN messages."
-
- make -priority 320 {
- <PREFIX>/bin/flexcan_load : <PACKAGE>/tests/flexcan_load.c
- @sh -c "mkdir -p tests $(dir $@)"
- $(CC) -c $(INCLUDE_PATH) -Wp,-MD,deps.tmp -I$(dir $<) $(CFLAGS) -o tests/flexcan_load.o $<
- @echo $@ ": \\" > $(notdir $@).deps
- @echo $(wildcard $(PREFIX)/lib/*) " \\" >> $(notdir $@).deps
- @tail -n +2 deps.tmp >> $(notdir $@).deps
- @echo >> $(notdir $@).deps
- @rm deps.tmp
- $(CC) $(LDFLAGS) -L$(PREFIX)/lib -Ttarget.ld -o $@ tests/flexcan_load.o
- }
-
+
make -priority 320 {
- <PREFIX>/bin/flexcan_remote : <PACKAGE>/tests/flexcan_remote.c
+ <PREFIX>/bin/flexcan_wake : <PACKAGE>/tests/flexcan_wake.c
@sh -c "mkdir -p tests $(dir $@)"
- $(CC) -c $(INCLUDE_PATH) -Wp,-MD,deps.tmp -I$(dir $<) $(CFLAGS) -o tests/flexcan_remote.o $<
+ $(CC) -c $(INCLUDE_PATH) -Wp,-MD,deps.tmp -I$(dir $<) $(CFLAGS) -o tests/flexcan_wake.o $<
@echo $@ ": \\" > $(notdir $@).deps
@echo $(wildcard $(PREFIX)/lib/*) " \\" >> $(notdir $@).deps
@tail -n +2 deps.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm deps.tmp
- $(CC) $(LDFLAGS) -L$(PREFIX)/lib -Ttarget.ld -o $@ tests/flexcan_remote.o
- }
- }
-
-
-
- cdl_component CYGPKG_DEVS_CAN_MCF52xx_FLEXCAN_OPTIONS {
- display "FlexCAN device driver build options"
- flavor none
- description "
- Package specific build options including control over
- compiler flags used only in building this package,
- and details of which tests are built."
-
- cdl_option CYGPKG_DEVS_CAN_MCF52xx_FLEXCAN_CFLAGS_ADD {
- display "Additional compiler flags"
- flavor data
- no_define
- default_value { "" }
- description "
- This option modifies the set of compiler flags for
- building these CAN device drivers. These flags are
- used in addition to the set of global flags."
- }
-
- cdl_option CYGPKG_DEVS_CAN_MCF52xx_FLEXCAN_CFLAGS_REMOVE {
- display "Suppressed compiler flags"
- flavor data
- no_define
- default_value { "" }
- description "
- This option modifies the set of compiler flags for
- building these CAN device drivers. These flags are
- removed from the set of global flags if present."
+ $(CC) $(LDFLAGS) -L$(PREFIX)/lib -Ttarget.ld -o $@ tests/flexcan_wake.o
}
}
}
//
#define FLEXCAN_ERR_EVENT 16
#define FLEXCAN_BUSOFF_EVENT 17
+#define FLEXCAN_WAKE_EVENT 18
+
+//
+// Acceptance mask
+//
+#define FLEXCAN_ACCEPTANCE_MASK_RX_ALL 0x00 // receive all messages - mbox ID does not matter
+#define FLEXCAN_ACCEPTANCE_MASK_RX_ID 0x1FFFFFFF // receive only messages where ID exactly matches mbox ID
//---------------------------------------------------------------------------
#define MBOX_CFG_STAT_MASK 0xF0
+//---------------------------------------------------------------------------
+// flexcan message buffer configuration
+//
+#define FLEXCAN_MBOX_MIN 0
+#define FLEXCAN_MBOX_MAX 15
+#define FLEXCAN_MBOX_CNT 16
+#define FLEXCAN_MBOX_TX CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN0_DEFAULT_TX_MBOX
+#define FLEXCAN_MBOX_RX_MIN 0
+#define FLEXCAN_MBOX_RX_MAX (FLEXCAN_MBOX_MAX - 1) // one msg box is tx
+#define FLEXCAN_MBOX_RX_CNT (FLEXCAN_MBOX_CNT - 1) // one msg box is tx
+
+
+#define FLEXCAN_CTRLSTAT_NOT_READ 0 // indicates that control status register is not read
+
+
//===========================================================================
// DATA TYPES
//===========================================================================
+//
+// Type of message buffer - required for function getevent in order to
+// identify the type of message box that cause event
+//
+typedef enum
+{
+ MBOX_STATE_DISABLED, // message box unused (free)
+ MBOX_STATE_TX, // TX message box
+ MBOX_STATE_REMOTE_TX, // remote TX msaage box (data will be sent on reception of rtr frame)
+ MBOX_STATE_RX_ALL_STD, // RX message box for standard IDs
+ MBOX_STATE_RX_ALL_EXT, // RX message box for standard IDs
+ MBOX_STATE_RX_FILT // RX message box for filter mboxes
+} flexcan_mbox_state;
+
+
//
// configuration info for flexcan message buffer
//
typedef struct flexcan_mbox_info_st
{
- cyg_vector_t isr_vec;
- int isr_priority;
- cyg_interrupt interrupt;
- cyg_handle_t interrupt_handle;
- cyg_uint8 num;
+ cyg_vector_t isr_vec; // isr vector
+ int isr_priority; // isr priority
+ cyg_interrupt interrupt; // stores interrupt data
+ cyg_handle_t interrupt_handle; // stores interrupt number
+ cyg_uint8 num; // number of message buffer
+ bool busy; // if true, then transmission or reception is in progress
+ flexcan_mbox_state state; // message box state
+ cyg_uint8 ctrlstat_shadow; // shadow register of message box ctrlstat register
} flexcan_mbox_info;
//
-// flexcan interrupt (busoff, err, wake) data
+// Between ISR and DSR handling there is some kind of circular buffer.
+// A DSR is only invoked if no other message box invoked a DSR before
+// the DSR will read all available message buffers. This structure
+// is for exchange of information between ISR and DSR
+//
+typedef struct st_rxmbox_circbuf
+{
+ cyg_uint8 idx_rd; // the message box the DSR will read from
+ cyg_uint8 idx_wr; // the message box that will receive the next message
+ cyg_uint8 count; // the number of received message before DSR starts (number of ISR nesting)
+} flexcan_rxmbox_circbuf;
+
+//
+// flexcan interrupt (busoff, err, wake) data - stores interrupt data for
+// a non message box interrupt (bus off, err or wake interrupt)
//
typedef struct flexcan_int_st
{
#define FLEXCAN_MBOX_INIT(_mbox0_vec, _prio, _mbox_no) { \
isr_vec : (_mbox0_vec) + (_mbox_no), \
isr_priority : (_prio), \
- num : (_mbox_no) \
+ num : (_mbox_no), \
+ busy : false \
}
//
//
typedef struct flexcan_info
{
- cyg_uint8 *base; // base address of flexcan modul
- cyg_vector_t isr_vec_mbox0; // vector number of ISR vector of first message box
- flexcan_mbox_info rx_mbox; // rx message box interrupt
- flexcan_mbox_info tx_mbox; // tx message box interrupt
- cyg_uint32 last_tx_id; // last transmitted message
- bool tx_busy; // indicates if transmit process ic currently running
-
- cyg_uint32 rxgmask; // acceptance filter for message box 0 - 13
- cyg_uint32 rx14mask; // acceptance filter for message box 14
- cyg_uint32 rx15mask; // acceptance filter for message box 15
-
- flexcan_int boff_int; // bus off interrupt data
- flexcan_int err_int; // error interrupt data
-
- cyg_uint32 timeout_rd;
- cyg_uint32 timeout_wr;
- cyg_uint16 mbox_alloc_flags;// these bits are used to indicate which message buffers are already alloceted and which ones are free
+ cyg_uint8 *base; // base address of flexcan modul
+ cyg_vector_t isr_vec_mbox0; // vector number of ISR vector of first message box
+ flexcan_mbox_info mboxes[FLEXCAN_MBOX_CNT];// message boxes
+ cyg_uint32 last_tx_id; // last transmitted message identifier
+
+ flexcan_int boff_int; // bus off interrupt data
+ flexcan_int err_int; // error interrupt data
+ flexcan_int wake_int; // wake interrupt data
+
+ cyg_uint8 tx_all_mbox; // number of message box for all transmit messages
+ cyg_uint8 free_mboxes; // number of free message boxes for msg filters and rtr buffers
+ cyg_can_state state; // state of CAN controller
+
+ flexcan_rxmbox_circbuf rxmbox_std_circbuf;
+ flexcan_rxmbox_circbuf rxmbox_ext_circbuf;
+
+ cyg_uint8 mboxes_std_cnt; // contains number of standard message boxes available
+ cyg_uint8 mboxes_ext_cnt; // number of message boxes with ext id
+ cyg_uint8 mboxes_rx_all_cnt;// number of all available mboxes
+
+ bool rx_all; // true if reception of call can messages is active
+ cyg_uint16 imask_shadow; // interrupt mask shadow register
+#ifdef CYGOPT_IO_CAN_TX_EVENT_SUPPORT
+ cyg_can_message last_tx_msg; // stores last transmitted message for TX events
+#endif
+
#ifdef FLEXCAN_CAN_STATS
cyg_uint32 isr_count;
cyg_uint32 dsr_count;
#define FLEXCAN_INFO(_l, \
_baseaddr, \
_isr_vec_mbox0, \
- _rx_mbox_no, _rx_isr_prio, \
- _tx_mbox_no, _tx_isr_prio, \
+ _mbox0_isr_prio, \
+ _mbox1_isr_prio, \
+ _mbox2_isr_prio, \
+ _mbox3_isr_prio, \
+ _mbox4_isr_prio, \
+ _mbox5_isr_prio, \
+ _mbox6_isr_prio, \
+ _mbox7_isr_prio, \
+ _mbox8_isr_prio, \
+ _mbox9_isr_prio, \
+ _mbox10_isr_prio, \
+ _mbox11_isr_prio, \
+ _mbox12_isr_prio, \
+ _mbox13_isr_prio, \
+ _mbox14_isr_prio, \
+ _mbox15_isr_prio, \
_boff_isr_vec, _boff_isr_prio, \
- _err_isr_vec, _err_isr_prio) \
+ _err_isr_vec, _err_isr_prio, \
+ _wake_isr_vec, _wake_isr_prio, \
+ _tx_all_mbox, \
+ _std_mboxes, _ext_mboxes) \
flexcan_info _l = { \
(void *)( _baseaddr), \
(_isr_vec_mbox0), \
- FLEXCAN_MBOX_INIT((_isr_vec_mbox0), (_rx_isr_prio), (_rx_mbox_no)), \
- FLEXCAN_MBOX_INIT((_isr_vec_mbox0), (_tx_isr_prio), (_tx_mbox_no)), \
- 0xFFFFFFFF, \
- false, \
- rxgmask : CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN0_RXMASK_GLOBAL, \
- rx14mask : CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN0_RXMASK_14, \
- rx15mask : CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN0_RXMASK_15, \
- boff_int : FLEXCAN_INT_INIT(_boff_isr_vec, _boff_isr_prio), \
- err_int : FLEXCAN_INT_INIT(_err_isr_vec, _err_isr_prio) \
+ mboxes : { \
+ FLEXCAN_MBOX_INIT((_isr_vec_mbox0), (_mbox0_isr_prio), 0), \
+ FLEXCAN_MBOX_INIT((_isr_vec_mbox0), (_mbox1_isr_prio), 1), \
+ FLEXCAN_MBOX_INIT((_isr_vec_mbox0), (_mbox2_isr_prio), 2), \
+ FLEXCAN_MBOX_INIT((_isr_vec_mbox0), (_mbox3_isr_prio), 3), \
+ FLEXCAN_MBOX_INIT((_isr_vec_mbox0), (_mbox4_isr_prio), 4), \
+ FLEXCAN_MBOX_INIT((_isr_vec_mbox0), (_mbox5_isr_prio), 5), \
+ FLEXCAN_MBOX_INIT((_isr_vec_mbox0), (_mbox6_isr_prio), 6), \
+ FLEXCAN_MBOX_INIT((_isr_vec_mbox0), (_mbox7_isr_prio), 7), \
+ FLEXCAN_MBOX_INIT((_isr_vec_mbox0), (_mbox8_isr_prio), 8), \
+ FLEXCAN_MBOX_INIT((_isr_vec_mbox0), (_mbox9_isr_prio), 9), \
+ FLEXCAN_MBOX_INIT((_isr_vec_mbox0), (_mbox10_isr_prio),10), \
+ FLEXCAN_MBOX_INIT((_isr_vec_mbox0), (_mbox11_isr_prio),11), \
+ FLEXCAN_MBOX_INIT((_isr_vec_mbox0), (_mbox12_isr_prio),12), \
+ FLEXCAN_MBOX_INIT((_isr_vec_mbox0), (_mbox13_isr_prio),13), \
+ FLEXCAN_MBOX_INIT((_isr_vec_mbox0), (_mbox14_isr_prio),14), \
+ FLEXCAN_MBOX_INIT((_isr_vec_mbox0), (_mbox15_isr_prio),15), \
+ }, \
+ last_tx_id : 0xFFFFFFFF, \
+ boff_int : FLEXCAN_INT_INIT(_boff_isr_vec, _boff_isr_prio), \
+ err_int : FLEXCAN_INT_INIT(_err_isr_vec, _err_isr_prio), \
+ wake_int : FLEXCAN_INT_INIT(_wake_isr_vec, _wake_isr_prio), \
+ tx_all_mbox : _tx_all_mbox, \
+ free_mboxes : ((_std_mboxes) + (_ext_mboxes)), \
+ state : CYGNUM_CAN_STATE_ACTIVE, \
+ rx_all : true, \
+ mboxes_std_cnt : _std_mboxes, \
+ mboxes_ext_cnt : _ext_mboxes, \
+ mboxes_rx_all_cnt : ((_std_mboxes) + (_ext_mboxes)) \
};
#define FLEXCAN_MBOX_INTPRIO(n) _FLEXCAN_MBOX_INTPRIO(n)
//
-// FlexCAN channel initialisation
+// Define number of message boxes if they are not defined yet
+//
+#ifndef CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN0_STD_MBOXES
+#define CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN0_STD_MBOXES 0
+#endif
+#ifndef CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN0_EXT_MBOXES
+#define CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN0_EXT_MBOXES 0
+#endif
+#ifndef CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN1_STD_MBOXES
+#define CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN1_STD_MBOXES 0
+#endif
+#ifndef CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN1_EXT_MBOXES
+#define CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN1_EXT_MBOXES 0
+#endif
+
+
+#ifdef CYGPKG_DEVS_CAN_MCF52xx_FLEXCAN0
+//
+// FlexCAN channel initialisation for FlexCAN channel 0
//
FLEXCAN_INFO(flexcan_can0_info,
HAL_MCF52xx_MBAR + HAL_MCF52xx_FLEXCAN0_BASE,
HAL_MCF52xx_FLEXCAN0_MBOX0_ISRVEC,
- CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN0_DEFAULT_RX_MBOX,
- FLEXCAN_MBOX_INTPRIO(CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN0_DEFAULT_RX_MBOX),
- CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN0_DEFAULT_TX_MBOX,
- FLEXCAN_MBOX_INTPRIO(CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN0_DEFAULT_TX_MBOX),
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN0_MBOX0,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN0_MBOX1,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN0_MBOX2,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN0_MBOX3,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN0_MBOX4,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN0_MBOX5,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN0_MBOX6,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN0_MBOX7,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN0_MBOX8,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN0_MBOX9,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN0_MBOX10,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN0_MBOX11,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN0_MBOX12,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN0_MBOX13,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN0_MBOX14,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN0_MBOX15,
HAL_MCF52xx_FLEXCAN0_BOFF_ISRVEC,
CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN0_BOFFINT,
HAL_MCF52xx_FLEXCAN0_ERR_ISRVEC,
- CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN0_ERRINT);
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN0_ERRINT,
+ HAL_MCF52xx_FLEXCAN0_WAKE_ISRVEC,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN0_WAKEINT,
+ CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN0_DEFAULT_TX_MBOX,
+ CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN0_STD_MBOXES,
+ CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN0_EXT_MBOXES);
+#endif // CYGPKG_DEVS_CAN_MCF52xx_FLEXCAN[set ::flexcan]
+
+#ifdef CYGPKG_DEVS_CAN_MCF52xx_FLEXCAN1
+//
+// FlexCAN channel initialisation for FlexCAN channel 1
+//
+FLEXCAN_INFO(flexcan_can0_info,
+ HAL_MCF52xx_MBAR + HAL_MCF52xx_FLEXCAN0_BASE,
+ HAL_MCF52xx_FLEXCAN1_MBOX0_ISRVEC,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN1_MBOX0,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN1_MBOX1,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN1_MBOX2,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN1_MBOX3,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN1_MBOX4,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN1_MBOX5,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN1_MBOX6,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN1_MBOX7,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN1_MBOX8,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN1_MBOX9,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN1_MBOX10,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN1_MBOX11,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN1_MBOX12,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN1_MBOX13,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN1_MBOX14,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN1_MBOX15,
+ HAL_MCF52xx_FLEXCAN1_BOFF_ISRVEC,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN1_BOFFINT,
+ HAL_MCF52xx_FLEXCAN1_ERR_ISRVEC,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN1_ERRINT,
+ HAL_MCF52xx_FLEXCAN1_WAKE_ISRVEC,
+ CYGNUM_DEVS_CAN_MCF52xx_ISR_PRIORITY_FLEXCAN1_WAKEINT,
+ CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN1_DEFAULT_TX_MBOX,
+ CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN1_STD_MBOXES,
+ CYGNUM_DEVS_CAN_MCF52xx_FLEXCAN1_EXT_MBOXES);
+#endif // CYGPKG_DEVS_CAN_MCF52xx_FLEXCAN1
//
-// message box structure
+// message box structure for hardware access of message box
//
typedef struct flexcan_mbox
{
- cyg_uint8 timestamp;
+ cyg_uint8 timestamp;
cyg_uint8 ctrlstat;
cyg_uint16 id_hi;
cyg_uint16 id_lo;
} flexcan_mbox;
//
-// flexcan register layout
+// flexcan register layout for hardware register access of FlexCAN modul
//
typedef struct flexcan_regs
{
static bool flexcan_init(struct cyg_devtab_entry* devtab_entry);
static Cyg_ErrNo flexcan_lookup(struct cyg_devtab_entry** tab, struct cyg_devtab_entry* sub_tab, const char* name);
static Cyg_ErrNo flexcan_set_config(can_channel *chan, cyg_uint32 key, const void* buf, cyg_uint32* len);
+static Cyg_ErrNo flexcan_get_config(can_channel *chan, cyg_uint32 key, const void* buf, cyg_uint32* len);
static bool flexcan_putmsg(can_channel *priv, cyg_can_message *pmsg, void *pdata);
static bool flexcan_getevent(can_channel *priv, cyg_can_event *pevent, void *pdata);
static void flexcan_start_xmit(can_channel* chan);
//
// TX and RX ISRs and DSRs
//
-static cyg_uint32 flexcan_mbox_rx_isr(cyg_vector_t, cyg_addrword_t);
-static void flexcan_mbox_rx_dsr(cyg_vector_t, cyg_ucount32, cyg_addrword_t);
+#ifdef CYGOPT_IO_CAN_STD_CAN_ID
+static cyg_uint32 flexcan_mbox_rx_std_isr(cyg_vector_t, cyg_addrword_t);
+static void flexcan_mbox_rx_std_dsr(cyg_vector_t, cyg_ucount32, cyg_addrword_t);
+#endif // CYGOPT_IO_CAN_STD_CAN_ID
+#ifdef CYGOPT_IO_CAN_EXT_CAN_ID
+static cyg_uint32 flexcan_mbox_rx_ext_isr(cyg_vector_t, cyg_addrword_t);
+static void flexcan_mbox_rx_ext_dsr(cyg_vector_t, cyg_ucount32, cyg_addrword_t);
+#endif // CYGOPT_IO_CAN_EXT_CAN_ID
+static cyg_uint32 flexcan_mbox_rx_filt_isr(cyg_vector_t, cyg_addrword_t);
static cyg_uint32 flexcan_mbox_tx_isr(cyg_vector_t, cyg_addrword_t);
static void flexcan_mbox_tx_dsr(cyg_vector_t, cyg_ucount32, cyg_addrword_t);
+static void flexcan_mbox_rx_filt_dsr(cyg_vector_t, cyg_ucount32, cyg_addrword_t );
//
// All other flexcan interrupt handlers
static void flexcan_err_dsr(cyg_vector_t, cyg_ucount32, cyg_addrword_t);
static cyg_uint32 flexcan_busoff_isr(cyg_vector_t, cyg_addrword_t);
static void flexcan_busoff_dsr(cyg_vector_t, cyg_ucount32, cyg_addrword_t);
+static cyg_uint32 flexcan_wake_isr(cyg_vector_t, cyg_addrword_t);
+static void flexcan_wake_dsr(cyg_vector_t, cyg_ucount32, cyg_addrword_t);
-
+//
+// Flexcan utility functions
+//
static bool flexcan_cfg_mbox_tx(flexcan_mbox *pmbox, cyg_can_message *pmsg, bool rtr);
-static void flexcan_cfg_mbox_rx(flexcan_mbox *pmbox, cyg_uint32 canid, cyg_uint8 ext);
+static void flexcan_cfg_mbox_rx(flexcan_mbox *pmbox, cyg_can_message *pmsg, bool enable);
static void flexcan_read_from_mbox(can_channel *chan, cyg_uint8 mbox, cyg_can_event *pevent, cyg_uint8 *ctrlstat);
-static void flexcan_set_acceptance_mask(cyg_uint16 *rxmask_reg, cyg_uint32 mask, cyg_uint8 ext);
+static void flexcan_set_acceptance_mask(cyg_uint16 *rxmask_reg, cyg_uint32 mask, cyg_can_id_type ext);
static void flexcan_start_chip(can_channel *chan);
+static void flexcan_enter_standby(can_channel *chan, bool selfwake);
+static void flexcan_stop_chip(can_channel *chan);
+static void flexcan_leave_standby(can_channel *chan);
static bool flexcan_set_baud(can_channel *chan, cyg_uint16 baudrate);
static bool flexcan_config(can_channel* chan, cyg_can_info_t* config, cyg_bool init);
+static cyg_int8 flexcan_alloc_mbox(flexcan_info *info);
+static void flexcan_disable_mbox(can_channel *chan, cyg_uint32 mbox_id);
+static void flexcan_setup_rxmbox(can_channel *chan, cyg_uint32 mbox_id, cyg_ISR_t *isr, cyg_can_message *pmsg, bool enable, bool int_enable);
+static void flexcan_setup_txmbox(can_channel *chan, cyg_uint32 mbox_id, cyg_can_message *pmsg);
+static void flexcan_setup_rtrmbox(can_channel *chan, cyg_uint32 mbox_id, cyg_can_message *pmsg);
+static void flexcan_mboxint_enable(flexcan_info *info, cyg_uint32 mbox_id);
+static void flexcan_mboxint_disable(flexcan_info *info, cyg_uint32 mbox_id);
+static void flexcan_config_rx_all(can_channel *chan);
+static void flexcan_enable_rxmbox(can_channel *chan, cyg_uint32 mbox_id);
CAN_LOWLEVEL_FUNS(flexcan_lowlevel_funs,
flexcan_putmsg,
flexcan_getevent,
+ flexcan_get_config,
flexcan_set_config,
flexcan_start_xmit,
flexcan_stop_xmit
//===========================================================================
-// Set device configuration
+// Enable hardware message box for reception
//===========================================================================
-static Cyg_ErrNo
-flexcan_set_config(can_channel *chan, cyg_uint32 key, const void* buf, cyg_uint32* len)
+static __inline__ void flexcan_hwmbox_enable_rx(flexcan_regs *flexcan, cyg_uint32 mbox_id)
{
- Cyg_ErrNo res = ENOERR;
+ HAL_WRITE_UINT8(&(flexcan->mbox[mbox_id].ctrlstat), MBOX_RXCODE_EMPTY);
+}
+
+
+//===========================================================================
+// Disable hardware message box
+//===========================================================================
+static __inline__ void flexcan_hwmbox_disable(flexcan_regs *flexcan, cyg_uint32 mbox_id)
+{
+ HAL_WRITE_UINT8(&(flexcan->mbox[mbox_id].ctrlstat), MBOX_RXCODE_NOT_ACTIVE);
+}
+
+
+//===========================================================================
+// lock mbox by reading control status register
+//===========================================================================
+static __inline__ void flexcan_hwmbox_lock(flexcan_regs *flexcan, cyg_uint32 mbox_id, cyg_uint8 *pctrlstat)
+{
+ HAL_READ_UINT8(&(flexcan->mbox[mbox_id].ctrlstat), *pctrlstat); // this read will lock the mbox
+}
+
+
+//===========================================================================
+// Enable message box interrupt for one message box
+//===========================================================================
+static void flexcan_mboxint_enable(flexcan_info *info, cyg_uint32 mbox_id)
+{
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+
+ info->imask_shadow |= (0x0001 << mbox_id);
+ HAL_WRITE_UINT16(&flexcan->IMASK, info->imask_shadow);
+}
+
+
+//===========================================================================
+// Disable message box interrupt for one message box
+//===========================================================================
+static void flexcan_mboxint_disable(flexcan_info *info, cyg_uint32 mbox_id)
+{
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
- switch(key)
+ info->imask_shadow &= ~(0x0001 << mbox_id);
+ HAL_WRITE_UINT16(&flexcan->IMASK, info->imask_shadow);
+}
+
+
+//===========================================================================
+// Allocate message box
+// Try to find a free message box and return its ID
+//===========================================================================
+static cyg_int8 flexcan_alloc_mbox(flexcan_info *info)
+{
+ cyg_uint8 i;
+ cyg_int8 res = CYGNUM_CAN_MSGBUF_NA;
+
+ if (info->free_mboxes)
+ {
+ for (i = (FLEXCAN_MBOX_RX_CNT - info->free_mboxes); i <= FLEXCAN_MBOX_RX_MAX; ++i)
+ {
+ if (MBOX_STATE_DISABLED == info->mboxes[i].state)
+ {
+ info->free_mboxes--;
+ res = i;
+ break;
+ }
+ }
+ } // if (info->free_mboxes)
+
+ return res;
+}
+
+
+//===========================================================================
+// Enable a previously configured rx mbox - a mbox ready to recive
+//===========================================================================
+static void flexcan_enable_rxmbox(can_channel *chan,
+ cyg_uint32 mbox_id)
+{
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+
+ flexcan_hwmbox_enable_rx(flexcan, mbox_id);
+ flexcan_mboxint_enable(info, mbox_id);
+}
+
+//===========================================================================
+// Prepare message buffer filter
+// Setup a RX message box for reception of a certain CAN identifier but do
+// not enable it
+//===========================================================================
+static void flexcan_setup_rxmbox(can_channel *chan,
+ cyg_uint32 mbox_id,
+ cyg_ISR_t *isr,
+ cyg_can_message *pmsg,
+ bool enable,
+ bool int_enable)
+{
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+ flexcan_mbox_info *pmbox;
+ cyg_DSR_t *dsr_func = &flexcan_mbox_rx_filt_dsr;
+
+ //
+ // Set state of message buffer accoring to ISR function that
+ // will be registered
+ //
+#ifdef CYGOPT_IO_CAN_STD_CAN_ID
+ if (*isr == flexcan_mbox_rx_std_isr)
{
- case CYG_IO_SET_CONFIG_CAN_INFO:
+ //
+ // If we have only one single RX all message box then we use
+ // the filter ISR instead of RX all standard ISR because it
+ // is better suited for a single RX mbox
+ //
+ if (info->mboxes_std_cnt > 1)
+ {
+ info->mboxes[mbox_id].state = MBOX_STATE_RX_ALL_STD;
+ dsr_func = &flexcan_mbox_rx_std_dsr;
+ }
+ else
+ {
+ info->mboxes[mbox_id].state = MBOX_STATE_RX_FILT;
+ isr = flexcan_mbox_rx_filt_isr;
+ }
+ }
+ else
+#endif // CYGOPT_IO_CAN_STD_CAN_ID
+#ifdef CYGOPT_IO_CAN_EXT_CAN_ID
+ if (*isr == flexcan_mbox_rx_ext_isr)
+ {
+ //
+ // If we have only one single RX all message box then we use
+ // the filter ISR instead of RX all standard ISR because it
+ // is better suited for a single RX mbox
+ //
+ if (info->mboxes_ext_cnt > 1)
+ {
+ info->mboxes[mbox_id].state = MBOX_STATE_RX_ALL_EXT;
+ dsr_func = &flexcan_mbox_rx_ext_dsr;
+ }
+ else
+ {
+ info->mboxes[mbox_id].state = MBOX_STATE_RX_FILT;
+ isr = flexcan_mbox_rx_filt_isr;
+ }
+ }
+ else
+#endif // CYGOPT_IO_CAN_EXT_CAN_ID
+ if (*isr == flexcan_mbox_rx_filt_isr)
+ {
+ info->mboxes[mbox_id].state = MBOX_STATE_RX_FILT;
+ }
+ else
+ {
+ CYG_ASSERT(0, "Invalid ISR function pointer");
+ }
+
+ pmbox = &info->mboxes[mbox_id];
+ flexcan_cfg_mbox_rx(&flexcan->mbox[mbox_id], pmsg, enable);
+
+ cyg_drv_interrupt_create(pmbox->isr_vec,
+ pmbox->isr_priority,
+ (cyg_addrword_t) chan,
+ isr,
+ dsr_func,
+ &(pmbox->interrupt_handle),
+ &(pmbox->interrupt));
+ cyg_drv_interrupt_attach(pmbox->interrupt_handle);
+ cyg_drv_interrupt_unmask(pmbox->isr_vec);
+
+ //
+ // now enable interrupt for this message box - but only if we
+ // really should do it
+ //
+ if (int_enable)
+ {
+ flexcan_mboxint_enable(info, mbox_id);
+ }
+}
+
+
+//===========================================================================
+// Disable a message box - after this call a message box is available
+// again for message filters or remote buffers
+//===========================================================================
+static void flexcan_disable_mbox(can_channel *chan, cyg_uint32 mbox_id)
+{
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+ flexcan_mbox_info *pmbox;
+
+ //
+ // if message box is already disabled we do not need to disable it
+ // here
+ //
+ if (MBOX_STATE_DISABLED == info->mboxes[mbox_id].state)
+ {
+ return;
+ }
+
+ HAL_WRITE_UINT8(&flexcan->mbox[mbox_id].ctrlstat, MBOX_RXCODE_NOT_ACTIVE);
+ info->mboxes[mbox_id].state = MBOX_STATE_DISABLED;
+ pmbox = &info->mboxes[mbox_id];
+
+ //
+ // now disable interrupts for this message box and free all
+ // interrupt resources
+ //
+ flexcan_mboxint_disable(info, mbox_id);
+ cyg_drv_interrupt_mask(pmbox->isr_vec);
+ cyg_drv_interrupt_detach(pmbox->interrupt_handle);
+ cyg_drv_interrupt_delete(pmbox->interrupt_handle);
+
+ info->free_mboxes++;
+}
+
+
+//===========================================================================
+// Setup a transmit message box
+//===========================================================================
+static void flexcan_setup_txmbox(can_channel *chan,
+ cyg_uint32 mbox_id,
+ cyg_can_message *pmsg)
+{
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+ flexcan_mbox_info *pmbox;
+
+ info->mboxes[mbox_id].state = MBOX_STATE_TX;
+ pmbox = &info->mboxes[mbox_id];
+ flexcan_cfg_mbox_tx(&flexcan->mbox[mbox_id], pmsg, false);
+
+ //
+ // prepare message box interrupt for message box
+ //
+ cyg_drv_interrupt_create(pmbox->isr_vec,
+ pmbox->isr_priority,
+ (cyg_addrword_t) chan,
+ &flexcan_mbox_tx_isr,
+ &flexcan_mbox_tx_dsr,
+ &(pmbox->interrupt_handle),
+ &(pmbox->interrupt));
+ cyg_drv_interrupt_attach(pmbox->interrupt_handle);
+ cyg_drv_interrupt_unmask(pmbox->isr_vec);
+
+ //
+ // now enable interrupt for this message box
+ //
+ flexcan_mboxint_enable(info, mbox_id);
+}
+
+
+//===========================================================================
+// Setup a RTR response message box
+//===========================================================================
+static void flexcan_setup_rtrmbox(can_channel *chan,
+ cyg_uint32 mbox_id,
+ cyg_can_message *pmsg)
+{
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+
+ info->mboxes[mbox_id].state = MBOX_STATE_REMOTE_TX;
+ flexcan_cfg_mbox_tx(&flexcan->mbox[mbox_id], pmsg, true);
+}
+
+
+//===========================================================================
+// Setup the list of message boxes ready to receive a message
+//===========================================================================
+static void flexcan_setup_rxmbox_circbuf(flexcan_rxmbox_circbuf *pbuf)
+{
+ pbuf->count = 0;
+ pbuf->idx_rd = 0;
+ pbuf->idx_wr = 0;
+}
+
+
+//===========================================================================
+// Setup flexCAN modul for reception of any kind of message
+//===========================================================================
+static void flexcan_config_rx_all(can_channel *chan)
+{
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+ cyg_int8 i;
+
+ //
+ // setup all available message boxes for reception of of messages
+ // All standard and extended message buffers will be configured
+ //
+ for (i = 0; i < info->mboxes_rx_all_cnt; ++i)
{
- cyg_can_info_t* config = (cyg_can_info_t*) buf;
- if (*len < sizeof(cyg_can_info_t))
+ cyg_can_message filter_param;
+ filter_param.id = 0;
+
+ //
+ // configure message buffers for standard frames
+ //
+#ifdef CYGOPT_IO_CAN_STD_CAN_ID
+ if (i < info->mboxes_std_cnt)
{
- return -EINVAL;
+ filter_param.ext = CYGNUM_CAN_ID_STD;
+ flexcan_setup_rxmbox(chan, i, &flexcan_mbox_rx_std_isr, &filter_param, false, true);
}
- *len = sizeof(cyg_can_info_t);
- if (!flexcan_config(chan, config, false))
+#endif // CYGOPT_IO_CAN_STD_CAN_ID
+
+ //
+ // configure message buffers for extended frames
+ //
+#ifdef CYGOPT_IO_CAN_EXT_CAN_ID
+ else
{
- return -EINVAL;
+ filter_param.ext = CYGNUM_CAN_ID_EXT;
+ flexcan_setup_rxmbox(chan, i, &flexcan_mbox_rx_ext_isr, &filter_param, false, true);
}
+#endif // CYGOPT_IO_CAN_EXT_CAN_ID
}
- break;
-
- case CYG_IO_SET_CONFIG_CAN_RTR_BUF:
+
+ //
+ // We need to receive all available CAN messages so we have to set the acceptance filter
+ // properly
+ //
+ flexcan_set_acceptance_mask(&flexcan->RXGMASK_HI, FLEXCAN_ACCEPTANCE_MASK_RX_ALL, CYGNUM_CAN_ID_EXT);
+ flexcan_set_acceptance_mask(&flexcan->RX14MASK_HI, FLEXCAN_ACCEPTANCE_MASK_RX_ALL, CYGNUM_CAN_ID_EXT);
+ info->free_mboxes = FLEXCAN_MBOX_RX_CNT - info->mboxes_rx_all_cnt;
+ info->rx_all = true;
+
+ //
+ // now finally setup the first active message boxes and enable ist
+ //
+#ifdef CYGOPT_IO_CAN_STD_CAN_ID
+ if (info->mboxes_std_cnt)
{
- cyg_uint8 i;
- cyg_uint16 alloc_mask = 0x0001;
- flexcan_info *info = (flexcan_info *)chan->dev_priv;
- flexcan_regs *flexcan = (flexcan_regs *)info->base;
- cyg_can_rtr_buf_t *rtr_buf = (cyg_can_rtr_buf_t*) buf;
-
-
- if (*len != sizeof(cyg_can_rtr_buf_t))
+ flexcan_setup_rxmbox_circbuf(&info->rxmbox_std_circbuf);
+ flexcan_enable_rxmbox(chan, 0);
+ }
+#endif // CYGOPT_IO_CAN_STD_CAN_ID
+
+#ifdef CYGOPT_IO_CAN_EXT_CAN_ID
+ if (info->mboxes_ext_cnt)
{
- return -EINVAL;
+ flexcan_setup_rxmbox_circbuf(&info->rxmbox_ext_circbuf);
+ flexcan_enable_rxmbox(chan, info->mboxes_std_cnt);
}
- *len = sizeof(cyg_can_rtr_buf_t);
+#endif // CYGOPT_IO_CAN_EXT_CAN_ID
+
+}
+
+//===========================================================================
+// Setup Flex CAN moduls in a state where all message boxes are disabled
+// After this call single message filters and buffers can be added
+//===========================================================================
+static void flexcan_config_rx_none(can_channel *chan)
+{
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+ cyg_int8 i;
//
- // If we need to create a new remote buffer then we check if there
- // is one message box free and then setup this box for remote frame
- // transmission
+ // setup all RX messages moxes into a disabled state
//
- if (CYGNUM_CAN_RTR_BUF_INIT == rtr_buf->handle)
+ for (i = 0; i < FLEXCAN_MBOX_RX_CNT; ++i)
{
- rtr_buf->handle = CYGNUM_CAN_RTR_BUF_NA;
- for (i = 0; i < 14; ++i)
- {
- if (!(info->mbox_alloc_flags & alloc_mask))
- {
- rtr_buf->handle = i;
- info->mbox_alloc_flags |= alloc_mask;
- break;
- }
- alloc_mask <<= 1;
+ flexcan_disable_mbox(chan, i);
+ }
+
+ //
+ // If we want to receive only certain CAN identiffiers then the ID does matter and
+ // we have to setup the acceptance mask properly
+ //
+ flexcan_set_acceptance_mask(&flexcan->RXGMASK_HI, FLEXCAN_ACCEPTANCE_MASK_RX_ID, CYGNUM_CAN_ID_EXT);
+ flexcan_set_acceptance_mask(&flexcan->RX14MASK_HI, FLEXCAN_ACCEPTANCE_MASK_RX_ID, CYGNUM_CAN_ID_EXT);
+ info->free_mboxes = FLEXCAN_MBOX_RX_CNT;
+ info->rx_all = false;
+}
+
+
+//===========================================================================
+// Configure message buffers
+//===========================================================================
+static Cyg_ErrNo flexcan_set_config_msgbuf(can_channel *chan, cyg_can_msgbuf_cfg *buf)
+{
+ Cyg_ErrNo res = ENOERR;
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+
+ switch (buf->cfg_id)
+ {
+ //
+ // clear all message filters and remote buffers - prepare for message buffer
+ // configuration
+ //
+ case CYGNUM_CAN_MSGBUF_RESET_ALL :
+ {
+ flexcan_config_rx_none(chan);
+ }
+ break;
+
+ //
+ // setup FlexCAN modul for reception of all standard and extended messages
+ //
+ case CYGNUM_CAN_MSGBUF_RX_FILTER_ALL :
+ {
+ if (!info->rx_all) // if rx_all is enabled we do not need to do anything
+ {
+ flexcan_config_rx_none(chan); // set into default state
+ flexcan_config_rx_all(chan); // setup RX all state
}
- } // if (CYGNUM_CAN_RTR_BUF_INIT == rtr_buf->handle)
+ }
+ break;
+
+ //
+ // add single message filter, message with filter ID will be received
+ //
+ case CYGNUM_CAN_MSGBUF_RX_FILTER_ADD :
+ {
+ cyg_can_filter *filter = (cyg_can_filter*) buf;
//
- // If we have a valid rtr buf handle then we can store data into
- // rtr message box
+ // if FlexCAN is configured to receive all messages then it is not
+ // allowed to add single message filters because then more than
+ // one message buffer would receive the same CAN id
+ //
+ if (info->rx_all)
+ {
+ return -EPERM;
+ }
+
+ //
+ // try to allocate a free message box - if we have a free one
+ // then we can prepare the message box for reception of the
+ // desired message id
+ //
+ filter->handle = flexcan_alloc_mbox(info);
+ if (filter->handle > CYGNUM_CAN_MSGBUF_NA)
+ {
+ flexcan_setup_rxmbox(chan, filter->handle, &flexcan_mbox_rx_filt_isr, &filter->msg, true, true);
+ }
+ }
+ break; //CYGNUM_CAN_MSGBUF_RX_FILTER_ADD
+
+ //
+ // Try to add a new RTR response message buffer for automatic transmisson
+ // of data frame on reception of a remote frame
+ //
+ case CYGNUM_CAN_MSGBUF_REMOTE_BUF_ADD :
+ {
+ cyg_can_remote_buf *rtr_buf = (cyg_can_remote_buf*) buf;
+ rtr_buf->handle = flexcan_alloc_mbox(info);
+
+ if (rtr_buf->handle > CYGNUM_CAN_MSGBUF_NA)
+ {
+ //
+ // if we have a free message buffer then we setup this buffer
+ // for remote frame reception
+ //
+ flexcan_setup_rtrmbox(chan, rtr_buf->handle, &rtr_buf->msg);
+ }
+ }
+ break;
+
+ //
+ // write data into remote response buffer
+ //
+ case CYGNUM_CAN_MSGBUF_REMOTE_BUF_WRITE :
+ {
+ cyg_can_remote_buf *rtr_buf = (cyg_can_remote_buf*) buf;
+
//
- if ((rtr_buf->handle >= 0) && (rtr_buf->handle < 14))
+ // If we have a valid rtr buf handle then we can store data into
+ // rtr message box
+ //
+ if ((rtr_buf->handle >= 0) && (rtr_buf->handle <= FLEXCAN_MBOX_RX_MAX))
{
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
flexcan_cfg_mbox_tx(&flexcan->mbox[rtr_buf->handle], &rtr_buf->msg, true);
}
else
{
return -EINVAL;
+ }
+ }
+ break;
+ } // switch (buf->cfg_id)
+
+ return res;
+}
+
+//===========================================================================
+// Set device configuration
+//===========================================================================
+static Cyg_ErrNo
+flexcan_set_config(can_channel *chan, cyg_uint32 key, const void* buf, cyg_uint32* len)
+{
+ Cyg_ErrNo res = ENOERR;
+
+ switch(key)
+ {
+ //
+ //Setup a new CAN configuration. This will i.e. setup a new baud rate
+ //
+ case CYG_IO_SET_CONFIG_CAN_INFO:
+ {
+ cyg_can_info_t* config = (cyg_can_info_t*) buf;
+ if (*len < sizeof(cyg_can_info_t))
+ {
+ return -EINVAL;
+ }
+ *len = sizeof(cyg_can_info_t);
+ if (!flexcan_config(chan, config, false))
+ {
+ return -EINVAL;
+ }
}
+ break;
+ //
+ // configure message buffers
+ //
+ case CYG_IO_SET_CONFIG_CAN_MSGBUF :
+ {
+ cyg_can_msgbuf_cfg *msg_buf = (cyg_can_msgbuf_cfg *) buf;
+
+ if (*len != sizeof(cyg_can_msgbuf_cfg))
+ {
+ return -EINVAL;
+ }
+
+ flexcan_set_config_msgbuf(chan, msg_buf);
}
break;
-
+
+ //
+ // Change CAN state of FlexCAN modul. This function will set the FlexCAN
+ // modul into STOPPED, ACTIVE or STANDBY state
+ //
+ case CYG_IO_SET_CONFIG_CAN_MODE :
+ {
+ cyg_can_mode *can_mode = (cyg_can_mode*) buf;
+
+ if (*len != sizeof(cyg_can_mode))
+ {
+ return -EINVAL;
+ }
+ *len = sizeof(cyg_can_mode);
+
+ //
+ // decide what to do acording to mode
+ //
+ switch (*can_mode)
+ {
+ case CYGNUM_CAN_MODE_STOP : // stop FlexCANm modul
+ flexcan_stop_chip(chan);
+ break;
+
+ case CYGNUM_CAN_MODE_START : // start FlexCAN modul
+ flexcan_leave_standby(chan);
+ break;
+
+ case CYGNUM_CAN_MODE_STANDBY : // set FlexCAN modul into standby state
+ flexcan_enter_standby(chan, true);
+ break;
+
+ case CYGNUM_CAN_MODE_CONFIG : // stop FlexCAN modul for configuration
+ flexcan_stop_chip(chan);
+ break;
+ }
+ }
+ break; // case CYG_IO_SET_CONFIG_CAN_MODE :
} // switch (key)
return res;
//===========================================================================
-// Read one event from can hardware
+// Query device configuration
//===========================================================================
-static bool flexcan_getevent(can_channel *chan, cyg_can_event *pevent, void *pdata)
+static Cyg_ErrNo
+flexcan_get_config(can_channel *chan, cyg_uint32 key, const void* buf, cyg_uint32* len)
{
- flexcan_info *info = (flexcan_info *)chan->dev_priv;
- flexcan_regs *flexcan = (flexcan_regs *)info->base;
- cyg_uint8 mbox_ctrlstat;
- bool res = true;
- cyg_uint8 event_id = *((cyg_uint8 *)pdata);
- cyg_uint16 estat;
-
- //
- // if event_id is 0 - 15 the we have a message box event - if is
- //
- if (event_id < FLEXCAN_ERR_EVENT)
- {
+ Cyg_ErrNo res = ENOERR;
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+
+ switch(key)
+ {
//
- // read data from message box - during processing of this function
- // the message box is locked and cannot receive further messages
+ // query state of CAN controller
//
- flexcan_read_from_mbox(chan, event_id, pevent, &mbox_ctrlstat);
-
-#ifdef CYGOPT_IO_CAN_TX_EVENT_SUPPORT
- if (pevent->msg.id == info->last_tx_id)
- {
- pevent->flags = CYGNUM_CAN_EVENT_TX;
- }
- else
- {
- pevent->flags = CYGNUM_CAN_EVENT_RX;
- }
-#else // !CYGOPT_IO_CAN_TX_EVENT_SUPPORT
+ case CYG_IO_GET_CONFIG_CAN_STATE :
+ {
+ cyg_can_state *can_state = (cyg_can_state*) buf;
+
+ if (*len != sizeof(cyg_can_state))
+ {
+ return -EINVAL;
+ }
+ *len = sizeof(cyg_can_state);
+ *can_state = info->state;
+ }
+ break;
+
//
- // If tx events are not supported and we received a self transmitted frame
- // then this is not really an rx event and we return false. We rely on the
- // fact here that two devices in network do not send the same identifier
+ // Query message box information - returns available and free message
+ // boxes
+ //
+ case CYG_IO_GET_CONFIG_CAN_MSGBUF_INFO :
+ {
+ cyg_can_msgbuf_info *mbox_info = (cyg_can_msgbuf_info*) buf;
+
+ if (*len != sizeof(cyg_can_msgbuf_info))
+ {
+ return -EINVAL;
+ }
+ *len = sizeof(cyg_can_msgbuf_info);
+
+ mbox_info->count = FLEXCAN_MBOX_RX_CNT;
+ mbox_info->free = info->free_mboxes;
+ }
+ break;
+
//
- if (pevent->msg.id == info->last_tx_id) {
- info->last_tx_id = 0xFFFFFFFF; // set last received ID to an invalid value
- res = false;
- }
-
- pevent->flags = CYGNUM_CAN_EVENT_RX;
+ // Query hardware description of FlexCAN device driver
+ //
+ case CYG_IO_GET_CONFIG_CAN_HDI :
+ {
+ cyg_can_hdi *hdi = (cyg_can_hdi *)buf;
+ //
+ // comes from high level driver so we do not need to
+ // check buffer size here
+ //
+ hdi->support_flags = CYGNUM_CAN_HDI_FRAMETYPE_EXT_ACTIVE
+ | CYGNUM_CAN_HDI_FULLCAN;
+#ifdef CYGOPT_IO_CAN_SUPPORT_TIMESTAMP
+ hdi->support_flags |= CYGNUM_CAN_HDI_TIMESTAMP;
#endif
+ }
+ break;
+
+ default :
+ res = -EINVAL;
+ }// switch(key)
+ return res;
+}
+
+
+//===========================================================================
+// Check if we received self transmitted frame
+//===========================================================================
+static bool flexcan_is_no_self_tx(cyg_can_event *pevent, flexcan_info *info, flexcan_mbox_info *pmbox)
+{
+ //
+ // If we received a self transmitted frame
+ // then this is not really an rx event and we return false. We rely on the
+ // fact here that two devices in network do not send the same identifier
+ //
+ if (pevent->msg.id == info->last_tx_id)
+ {
+ info->last_tx_id = 0xFFFFFFFF; // set last received ID to an invalid value
+ return false;
+ }
+ else
+ {
+ pevent->flags |= CYGNUM_CAN_EVENT_RX;
+
//
// check if an overun occured in this message box
//
- if ((mbox_ctrlstat & MBOX_RXCODE_OVERRUN) == MBOX_RXCODE_OVERRUN)
+ if ((pmbox->ctrlstat_shadow & MBOX_RXCODE_OVERRUN) == MBOX_RXCODE_OVERRUN)
{
pevent->flags |= CYGNUM_CAN_EVENT_OVERRUN_RX;
}
+
+ return true;
+ }
+}
+
+
+//===========================================================================
+// Read one event from can hardware - called from high level I/O CAN driver
+//===========================================================================
+static bool flexcan_getevent(can_channel *chan, cyg_can_event *pevent, void *pdata)
+{
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+ bool res = true;
+ cyg_uint16 estat;
+ cyg_uint8 event_id = *((cyg_uint8 *)pdata);
+
+ //
+ // if event_id is 0 - 15 the we have a message box event
+ //
+ if (event_id < FLEXCAN_ERR_EVENT)
+ {
+ flexcan_mbox_info *pmbox_info;
+ pmbox_info = &info->mboxes[event_id];
+
+ //
+ // Deceide what to do according to type of message box that caused this event
+ //
+ switch (pmbox_info->state)
+ {
+ //
+ // If we have an RX event then we need to read the received data from
+ // message box that caused this event and fill it into message queue of
+ // high level I/O CAN driver. We could handle this stuff in a function
+ // because it is the same like MBOX_STATE_RX_ALL_EXT but speed is more
+ // important here than codesize
+ //
+ case MBOX_STATE_RX_ALL_STD:
+ case MBOX_STATE_RX_ALL_EXT:
+ case MBOX_STATE_RX_FILT:
+ {
+ //
+ // read data from message box - during processing of this function
+ // the message box is locked and cannot receive further messages
+ //
+ flexcan_read_from_mbox(chan, event_id, pevent, &(pmbox_info->ctrlstat_shadow));
+ res = flexcan_is_no_self_tx(pevent, info, pmbox_info);
+ }
+ break;
+
+#ifdef CYGOPT_IO_CAN_TX_EVENT_SUPPORT
+ //
+ // If a TX message box cause the event then we store the last transmitted
+ // message into the receive message queue
+ //
+ case MBOX_STATE_TX:
+ pevent->flags = CYGNUM_CAN_EVENT_TX;
+ pevent->msg = info->last_tx_msg;
+ break;
+#endif // CYGOPT_IO_CAN_TX_EVENT_SUPPORT
+
+ case MBOX_STATE_REMOTE_TX:
+ break;
+
+ default:
+ res = false;
+ } // switch (pmbox->state)
}
else // (event_id >= FLEXCAN_ERR_EVENT)
{
// error interrupt and provide error information to upper layer
//
HAL_READ_UINT16(&flexcan->ESTAT, estat);
- pevent->msg.data[0] = estat & 0xFF;
- pevent->msg.data[1] = (estat >> 8) & 0xFF;
- HAL_READ_UINT8(&flexcan->RXERRCNT, pevent->msg.data[2]);
- HAL_READ_UINT8(&flexcan->TXERRCNT, pevent->msg.data[3]);
+ pevent->msg.data.bytes[0] = estat & 0xFF;
+ pevent->msg.data.bytes[1] = (estat >> 8) & 0xFF;
+ HAL_READ_UINT8(&flexcan->RXERRCNT, pevent->msg.data.bytes[2]);
+ HAL_READ_UINT8(&flexcan->TXERRCNT, pevent->msg.data.bytes[3]);
switch (event_id)
{
case FLEXCAN_ERR_EVENT :
case FLEXCAN_BUSOFF_EVENT:
pevent->flags = CYGNUM_CAN_EVENT_BUS_OFF;
break;
+
+ case FLEXCAN_WAKE_EVENT:
+ pevent->flags = CYGNUM_CAN_EVENT_LEAVING_STANDBY;
+ break;
} // switch (event_id)
}
-
+
return res;
}
//===========================================================================
static bool flexcan_putmsg(can_channel *chan, cyg_can_message *pmsg, void *pdata)
{
- flexcan_info *info = (flexcan_info *)chan->dev_priv;
- flexcan_regs *flexcan = (flexcan_regs *)info->base;
- cyg_uint8 mbox = *((cyg_uint8 *)pdata);
- cyg_uint16 iflag;
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+ cyg_uint8 mbox = *((cyg_uint8 *)pdata);
+ flexcan_mbox_info *pmbox = &info->mboxes[mbox];
+ cyg_uint16 iflag;
HAL_READ_UINT16(&flexcan->IFLAG, iflag);
//
// check if device is busy sending a message
//
- if (info->tx_busy)
+ if (pmbox->busy)
{
//
- // if devise is busy and the interrupt flag is set, then we know
- // that device is not busy any longer - if more message boxes are
- // used for transmitting then tx_busy should be part of a message box
- // structure to keep track of the state of different message boxes
+ // if device is busy and the interrupt flag is set, then we know
+ // that device is not busy any longer
//
if (iflag & (0x0001 << mbox))
{
}
}
- info->tx_busy = true; // mark transmitter as busy
- info->last_tx_id = pmsg->id; // store message in order to identify self recieved frames
- flexcan_cfg_mbox_tx(&flexcan->mbox[mbox], pmsg, false);
+ pmbox->busy = true; // mark transmitter as busy
+ info->last_tx_id = pmsg->id; // store message in order to identify self recieved frames
+
+#ifdef CYGOPT_IO_CAN_TX_EVENT_SUPPORT
+ info->last_tx_msg = *pmsg; // store the transmitted message for TX events
+#endif
+
+ flexcan_cfg_mbox_tx(&flexcan->mbox[mbox], pmsg, false); // send message
return true;
}
//===========================================================================
-// Flexcan start xmit
+// Flexcan start xmit - If the chip is in standby mode then a call to this
+// function will cause the FlexCAN modul to leave the standby mode. So
+// the output queue should be empty before entering stadby mode
//===========================================================================
static void flexcan_start_xmit(can_channel* chan)
{
- flexcan_info *info = (flexcan_info *)chan->dev_priv;
- flexcan_regs *flexcan = (flexcan_regs *)info->base;
- cyg_uint16 imask;
- CYG_INTERRUPT_STATE saved_state;
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ CYG_INTERRUPT_STATE saved_state;
HAL_DISABLE_INTERRUPTS(saved_state);
+ //
+ // if we are in standby state the we leave standby state now. This is
+ // the reason that the user should wait until the TX queue is empty before
+ // entering standby mode- or he should drain or flush the TX queue
+ //
+ if (CYGNUM_CAN_STATE_STANDBY == info->state)
+ {
+ flexcan_leave_standby(chan);
+ }
+
//
// Now enable message box 15 interrupts
//
- HAL_READ_UINT16(&flexcan->IMASK, imask);
- HAL_WRITE_UINT16(&flexcan->IMASK, imask | (0x0001 << info->tx_mbox.num));
+ flexcan_mboxint_enable(info, info->tx_all_mbox);
//
// kick transmitter
//
- chan->callbacks->xmt_msg(chan, &info->tx_mbox.num); // Kick transmitter (if necessary)
+ chan->callbacks->xmt_msg(chan, &info->tx_all_mbox); // Kick transmitter (if necessary)
HAL_RESTORE_INTERRUPTS(saved_state);
}
//===========================================================================
-// Flexcan start xmit
+// Flexcan stop transmission
//===========================================================================
static void flexcan_stop_xmit(can_channel* chan)
{
- flexcan_info *info = (flexcan_info *)chan->dev_priv;
- flexcan_regs *flexcan = (flexcan_regs *)info->base;
- cyg_uint16 imask;
- CYG_INTERRUPT_STATE saved_state;
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ CYG_INTERRUPT_STATE saved_state;
HAL_DISABLE_INTERRUPTS(saved_state);
//
// Now disable message box 15 interrupts
//
- HAL_READ_UINT16(&flexcan->IMASK, imask);
- HAL_WRITE_UINT16(&flexcan->IMASK, imask & ~(0x0001 << info->tx_mbox.num));
+ flexcan_mboxint_disable(info, info->tx_all_mbox);
HAL_RESTORE_INTERRUPTS(saved_state);
}
//===========================================================================
static bool flexcan_config(can_channel* chan, cyg_can_info_t* config, cyg_bool init)
{
- flexcan_info *info = (flexcan_info *)chan->dev_priv;
- flexcan_regs *flexcan = (flexcan_regs *)info->base;
- cyg_uint16 tmp16;
- cyg_uint8 tmp8;
- cyg_uint8 i;
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+ cyg_uint16 tmp16;
+ cyg_uint8 tmp8;
+ cyg_uint8 i;
+
+ //
+ // the first thing we need to do is to stop the chip
+ //
+ flexcan_stop_chip(chan);
+ //
+ // if this is the first initialisation of the FlexCAN modul we need to execute
+ // some extra steps here
+ //
if (init)
{
#if defined(CYGPKG_DEVS_CAN_MCF52xx_FLEXCAN0) && defined(HAL_MCF52xx_FLEXCAN0_PROC_INIT)
& ~FLEXCAN_CTRL0_ERRMASK);
//
- // setup message box acceptance filter
+ // deactivate all message buffers - this is mandatory for configuration
+ // of message buffers
//
- flexcan_set_acceptance_mask(&flexcan->RXGMASK_HI, info->rxgmask, 0);
- flexcan_set_acceptance_mask(&flexcan->RX14MASK_HI, info->rx14mask, 0);
- flexcan_set_acceptance_mask(&flexcan->RX15MASK_HI, info->rx15mask, 0);
- } // if (init)
-
- //
- // stop chip
- //
- HAL_READ_UINT16(&flexcan->CANMCR, tmp16);
- HAL_WRITE_UINT16(&flexcan->CANMCR, tmp16 | FLEXCAN_MCR_HALT);
-
- //
- // deactivate all message buffers - this is mandatory for configuration
- // of message buffers
- //
- for (i = 0; i < 16; ++i)
- {
- HAL_WRITE_UINT16(&flexcan->mbox[i], MBOX_RXCODE_NOT_ACTIVE);
- }
- //
- // mask all interrupts
- //
- HAL_WRITE_UINT16(&flexcan->IMASK, 0x0000);
- HAL_READ_UINT8(&flexcan->CANCTRL0, tmp8);
- HAL_WRITE_UINT8(&flexcan->CANCTRL0, tmp8 & ~(FLEXCAN_CTRL0_BOFFMSK | FLEXCAN_CTRL0_ERRMASK));
-
- flexcan_set_baud(chan, config->baud);
-
- //
- // setup bus arbitration mode - the LBUF bit defines the
- // transmit-first scheme 0 = message buffer with lowest ID
- // 1 = message buffer with lowest number. We use lowest ID here
- //
- HAL_READ_UINT8(&flexcan->CANCTRL1, tmp8);
- HAL_WRITE_UINT8(&flexcan->CANCTRL1, (tmp8 & ~FLEXCAN_CTRL1_LBUF));
+ for (i = FLEXCAN_MBOX_MIN; i <= FLEXCAN_MBOX_MAX; ++i)
+ {
+ HAL_WRITE_UINT16(&flexcan->mbox[i], MBOX_RXCODE_NOT_ACTIVE);
+ }
- info->mbox_alloc_flags = 0; // no buffers used yet
-
- //
- // Message box 14 is our receiv message box. We configure it for
- // reception of any message
- //
- flexcan_cfg_mbox_rx(&flexcan->mbox[info->rx_mbox.num], 0x100, 0);
- flexcan_set_acceptance_mask(&flexcan->RX14MASK_HI, 0, 0);
- info->mbox_alloc_flags |= (0x0001 << info->rx_mbox.num); // mark rx mbox flag as used
- info->mbox_alloc_flags |= (0x0001 << info->tx_mbox.num); // mark tx mbox flag as used
-
- //
- // enable the rx interrupt for mbox 0 (tx interrupt are enabled in start xmit)
- // bus off interrupt and error interrupt
- //
- HAL_WRITE_UINT16(&flexcan->IMASK, (0x0001 << info->rx_mbox.num));
- HAL_READ_UINT8(&flexcan->CANCTRL0, tmp8);
- HAL_WRITE_UINT8(&flexcan->CANCTRL0, tmp8 | (FLEXCAN_CTRL0_BOFFMSK | FLEXCAN_CTRL0_ERRMASK));
+ //
+ // mask all interrupts
+ //
+ info->imask_shadow = 0x0000;
+ HAL_WRITE_UINT16(&flexcan->IMASK, info->imask_shadow);
+ HAL_READ_UINT8(&flexcan->CANCTRL0, tmp8);
+ HAL_WRITE_UINT8(&flexcan->CANCTRL0, tmp8 & ~(FLEXCAN_CTRL0_BOFFMSK | FLEXCAN_CTRL0_ERRMASK));
+
+ //
+ // setup bus arbitration mode - the LBUF bit defines the
+ // transmit-first scheme 0 = message buffer with lowest ID
+ // 1 = message buffer with lowest number. We use lowest ID here
+ //
+ HAL_READ_UINT8(&flexcan->CANCTRL1, tmp8);
+ HAL_WRITE_UINT8(&flexcan->CANCTRL1, (tmp8 & ~FLEXCAN_CTRL1_LBUF));
+
+ //
+ // setup all rx message buffers
+ //
+ flexcan_config_rx_all(chan);
- //
- // now we can start the chip
- //
- flexcan_start_chip(chan);
+ //
+ // bus off interrupt and error interrupt
+ //
+ HAL_READ_UINT8(&flexcan->CANCTRL0, tmp8);
+ HAL_WRITE_UINT8(&flexcan->CANCTRL0, tmp8 | (FLEXCAN_CTRL0_BOFFMSK | FLEXCAN_CTRL0_ERRMASK));
+ } // if (init)
+
+ flexcan_set_baud(chan, config->baud); // setup baud rate
//
// store new config values
{
chan->config = *config;
}
+ flexcan_start_chip(chan); // now we can start the chip again
return true;
}
//===========================================================================
-// CAN INIT
-//
/// First initialisation and reset of CAN modul.
//===========================================================================
static bool flexcan_init(struct cyg_devtab_entry* devtab_entry)
{
- can_channel *chan = (can_channel*)devtab_entry->priv;
- flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ can_channel *chan = (can_channel*)devtab_entry->priv;
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_mbox_info *pmbox;
if (!flexcan_config(chan, &chan->config, true))
{
return false;
}
-
- //
- // prepare message box interrupt for message box 0 - the rx message box
- //
- cyg_drv_interrupt_create(info->rx_mbox.isr_vec,
- info->rx_mbox.isr_priority,
- (cyg_addrword_t) chan,
- &flexcan_mbox_rx_isr,
- &flexcan_mbox_rx_dsr,
- &(info->rx_mbox.interrupt_handle),
- &(info->rx_mbox.interrupt));
- cyg_drv_interrupt_attach(info->rx_mbox.interrupt_handle);
- cyg_drv_interrupt_unmask(info->rx_mbox.isr_vec);
-
+
//
// prepare message box interrupt for message box 15 - the tx message box
//
- cyg_drv_interrupt_create(info->tx_mbox.isr_vec,
- info->tx_mbox.isr_priority,
+ pmbox = &info->mboxes[info->tx_all_mbox];
+ cyg_drv_interrupt_create(pmbox->isr_vec,
+ pmbox->isr_priority,
(cyg_addrword_t) chan,
&flexcan_mbox_tx_isr,
&flexcan_mbox_tx_dsr,
- &(info->tx_mbox.interrupt_handle),
- &(info->tx_mbox.interrupt));
- cyg_drv_interrupt_attach(info->tx_mbox.interrupt_handle);
- cyg_drv_interrupt_unmask(info->tx_mbox.isr_vec);
+ &(pmbox->interrupt_handle),
+ &(pmbox->interrupt));
+ cyg_drv_interrupt_attach(pmbox->interrupt_handle);
+ cyg_drv_interrupt_unmask(pmbox->isr_vec);
//
// prepare error interrupt
&(info->boff_int.interrupt));
cyg_drv_interrupt_attach(info->boff_int.interrupt_handle);
cyg_drv_interrupt_unmask(info->boff_int.isr_vec);
+
+ //
+ // prepare wake interrupt
+ //
+ cyg_drv_interrupt_create(info->wake_int.isr_vec,
+ info->wake_int.isr_priority,
+ (cyg_addrword_t) chan,
+ &flexcan_wake_isr,
+ &flexcan_wake_dsr,
+ &(info->wake_int.interrupt_handle),
+ &(info->wake_int.interrupt));
+ cyg_drv_interrupt_attach(info->wake_int.interrupt_handle);
+ cyg_drv_interrupt_unmask(info->wake_int.isr_vec);
return true;
}
//===========================================================================
// Bus off interrupt handler
//===========================================================================
-static cyg_uint32 flexcan_busoff_isr(cyg_vector_t vec, cyg_addrword_t data)
+static cyg_uint32 flexcan_busoff_isr(cyg_vector_t vec, cyg_addrword_t data)
+{
+ can_channel *chan = (can_channel *)data;
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+ cyg_uint8 ctrl0;
+ cyg_uint16 estat;
+
+ //
+ // first we disable bus off interrupts - DSR will reenable it later
+ //
+ HAL_READ_UINT8(&flexcan->CANCTRL0, ctrl0);
+ HAL_WRITE_UINT8(&flexcan->CANCTRL0, ctrl0 & ~FLEXCAN_CTRL0_BOFFMSK);
+
+ //
+ // for clearing the interrupt we first read the flag register as 1
+ // and then write it as 1 (and not as zero like the manual stated)
+ // we clear only the flag of this interrupt and leave all other
+ // message box interrupts untouched
+ //
+ HAL_READ_UINT16(&flexcan->ESTAT, estat);
+ HAL_WRITE_UINT16(&flexcan->ESTAT, FLEXCAN_ESTAT_BOFFINT);
+
+ //
+ // On the mcf5272 there is no need to acknowledge internal
+ // interrupts, only external ones.
+ // cyg_drv_interrupt_acknowledge(vec);
+ //
+ return CYG_ISR_CALL_DSR;
+}
+
+
+//===========================================================================
+// DSR for all interrupts that are no message box interrupts
+//===========================================================================
+static void flexcan_busoff_dsr(cyg_vector_t vec, cyg_ucount32 count, cyg_addrword_t data)
+{
+ can_channel *chan = (can_channel *)data;
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+ cyg_uint8 ctrl0;
+ cyg_uint8 event_id = FLEXCAN_BUSOFF_EVENT;
+
+ //
+ // signal CAN event to generic IO CAN driver - it will do any further
+ // processing
+ //
+ chan->callbacks->rcv_event(chan, &event_id);
+
+ //
+ // reenable bus off interrupts
+ //
+ HAL_READ_UINT8(&flexcan->CANCTRL0, ctrl0);
+ HAL_WRITE_UINT8(&flexcan->CANCTRL0, ctrl0 | FLEXCAN_CTRL0_BOFFMSK);
+}
+
+
+//===========================================================================
+// Bus off interrupt handler
+//===========================================================================
+static cyg_uint32 flexcan_wake_isr(cyg_vector_t vec, cyg_addrword_t data)
{
can_channel *chan = (can_channel *)data;
flexcan_info *info = (flexcan_info *)chan->dev_priv;
flexcan_regs *flexcan = (flexcan_regs *)info->base;
- cyg_uint8 ctrl0;
cyg_uint16 estat;
//
- // first we disable bus off interrupts - DSR will reenable it later
+ // first we disable wake interrupts - we set the mcr register to
+ // zero in order to bring it back to normal state
//
- HAL_READ_UINT8(&flexcan->CANCTRL0, ctrl0);
- HAL_WRITE_UINT8(&flexcan->CANCTRL0, ctrl0 & ~FLEXCAN_CTRL0_BOFFMSK);
+ HAL_WRITE_UINT16(&flexcan->CANMCR, 0);
//
// for clearing the interrupt we first read the flag register as 1
// message box interrupts untouched
//
HAL_READ_UINT16(&flexcan->ESTAT, estat);
- HAL_WRITE_UINT16(&flexcan->ESTAT, FLEXCAN_ESTAT_BOFFINT);
-
+ HAL_WRITE_UINT16(&flexcan->ESTAT, FLEXCAN_ESTAT_WAKEINT);
+
//
// On the mcf5272 there is no need to acknowledge internal
// interrupts, only external ones.
//===========================================================================
// DSR for all interrupts that are no message box interrupts
//===========================================================================
-static void flexcan_busoff_dsr(cyg_vector_t vec, cyg_ucount32 count, cyg_addrword_t data)
+static void flexcan_wake_dsr(cyg_vector_t vec, cyg_ucount32 count, cyg_addrword_t data)
{
can_channel *chan = (can_channel *)data;
flexcan_info *info = (flexcan_info *)chan->dev_priv;
flexcan_regs *flexcan = (flexcan_regs *)info->base;
+ cyg_uint8 event_id = FLEXCAN_WAKE_EVENT;
cyg_uint8 ctrl0;
- cyg_uint8 event_id = FLEXCAN_BUSOFF_EVENT;
//
// signal CAN event to generic IO CAN driver - it will do any further
- // processing
+ // processing we will enable all other interrupts after the call to
+ // rcv_event because the user should receive this event as the first
+ // event after FlexCAN leaves standby.
//
chan->callbacks->rcv_event(chan, &event_id);
//
- // reenable bus off interrupts
+ // for standby we disabled all interrut source so we have to enable
+ // it here again for normal operation
//
+ HAL_WRITE_UINT16(&flexcan->IMASK, info->imask_shadow);
HAL_READ_UINT8(&flexcan->CANCTRL0, ctrl0);
- HAL_WRITE_UINT8(&flexcan->CANCTRL0, ctrl0 | FLEXCAN_CTRL0_BOFFMSK);
+ HAL_WRITE_UINT8(&flexcan->CANCTRL0, ctrl0 |(FLEXCAN_CTRL0_BOFFMSK | FLEXCAN_CTRL0_ERRMASK));
}
//===========================================================================
-// Flexcan message box isr
+// Flexcan message box isr for rx messages if message filtering is
+// enabled
//===========================================================================
-static cyg_uint32 flexcan_mbox_rx_isr(cyg_vector_t vec, cyg_addrword_t data)
+static cyg_uint32 flexcan_mbox_rx_filt_isr(cyg_vector_t vec, cyg_addrword_t data)
{
can_channel *chan = (can_channel *)data;
flexcan_info *info = (flexcan_info *)chan->dev_priv;
flexcan_regs *flexcan = (flexcan_regs *)info->base;
cyg_uint16 iflag;
- cyg_uint16 imask;
//
// number of message box can be calculated from vector that cause
// first we disable interrupts of this message box - the DSR will
// reenable it later
//
- HAL_READ_UINT16(&flexcan->IMASK, imask);
- HAL_WRITE_UINT16(&flexcan->IMASK, imask & ~(0x0001 << mbox));
+ flexcan_mboxint_disable(info, mbox);
+ info->mboxes[mbox].ctrlstat_shadow = FLEXCAN_CTRLSTAT_NOT_READ;
//
// for clearing the interrupt we first read the flag register as 1
}
+#ifdef CYGOPT_IO_CAN_EXT_CAN_ID
//===========================================================================
-// Flexcan message box dsr
+// Flexcan message box isr for extended identifiers if reception of all
+// available messages is enabled
+//===========================================================================
+static cyg_uint32 flexcan_mbox_rx_ext_isr(cyg_vector_t vec, cyg_addrword_t data)
+{
+ can_channel *chan = (can_channel *)data;
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+ cyg_uint16 iflag;
+ flexcan_rxmbox_circbuf *prx_mbox_list = &(info->rxmbox_ext_circbuf);
+
+ //
+ // number of message box can be calculated from vector that caused
+ // interrupt - we pass this message box number as additional data to the
+ // callback because it is required in the receive event function later
+ //
+ cyg_uint8 mbox = vec - info->isr_vec_mbox0;
+ if (++prx_mbox_list->count < info->mboxes_ext_cnt)
+ {
+ prx_mbox_list->idx_wr = (prx_mbox_list->idx_wr + 1) % info->mboxes_ext_cnt;
+ flexcan_hwmbox_enable_rx(flexcan, prx_mbox_list->idx_wr + info->mboxes_std_cnt);
+ flexcan_hwmbox_lock(flexcan, mbox, &(info->mboxes[mbox].ctrlstat_shadow));
+ flexcan_hwmbox_disable(flexcan, mbox); // now disable this message box - it is already locked
+ //
+ // first we disable interrupts of this message box - the DSR will
+ // reenable it later
+ //
+ flexcan_mboxint_disable(info, mbox);
+ }
+ else
+ {
+ prx_mbox_list->count = info->mboxes_ext_cnt;
+ info->mboxes[mbox].ctrlstat_shadow = FLEXCAN_CTRLSTAT_NOT_READ;
+ }
+
+ //
+ // for clearing the interrupt we first read the flag register as 1
+ // and then write it as 1 (and not as zero like the manual stated)
+ // we clear only the flag of this interrupt and leave all other
+ // message box interrupts untouched
+ //
+ HAL_READ_UINT16(&flexcan->IFLAG, iflag);
+ HAL_WRITE_UINT16(&flexcan->IFLAG, (0x0001 << mbox));
+
+ //
+ // On the mcf5272 there is no need to acknowledge internal
+ // interrupts, only external ones.
+ // cyg_drv_interrupt_acknowledge(vec); If counter of mbox list is > 1
+ // then we know that there is already a DSR running and we do not
+ // need to invoke one
+ //
+ if (prx_mbox_list->count > 1)
+ {
+ return CYG_ISR_HANDLED;
+ }
+ else
+ {
+ return CYG_ISR_CALL_DSR;
+ }
+}
+
+
+//===========================================================================
+// FlexCAN message box DSR for extended CAN frames
+//===========================================================================
+static void flexcan_mbox_rx_ext_dsr(cyg_vector_t vec, cyg_ucount32 count, cyg_addrword_t data)
+{
+ can_channel * chan = (can_channel *)data;
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_rxmbox_circbuf *prx_mbox_list = &(info->rxmbox_ext_circbuf);
+ cyg_uint8 mbox;
+ cyg_uint8 mbox_cnt;
+
+ //
+ // we do not process the message box we received as event_id
+ // we take the message boxes from the ring buffer
+ //
+ do
+ {
+ cyg_drv_isr_lock();
+ mbox_cnt = --prx_mbox_list->count;
+ cyg_drv_isr_unlock();
+
+ mbox = prx_mbox_list->idx_rd + info->mboxes_std_cnt;
+ prx_mbox_list->idx_rd = (prx_mbox_list->idx_rd + 1) % info->mboxes_ext_cnt;
+ chan->callbacks->rcv_event(chan, &mbox);
+ flexcan_mboxint_enable(info, mbox);
+
+ //
+ // if the last message box is enabled, then we have to enable
+ // another one now because the last message box is filled already
+ //
+ if (mbox_cnt == (info->mboxes_ext_cnt - 1))
+ {
+ cyg_uint8 active_mbox;
+ cyg_uint8 next_mbox;
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+
+ cyg_drv_isr_lock();
+ active_mbox = prx_mbox_list->idx_wr;
+ next_mbox = prx_mbox_list->idx_wr = (prx_mbox_list->idx_wr + 1) % info->mboxes_ext_cnt;
+ cyg_drv_isr_unlock();
+
+ active_mbox += info->mboxes_std_cnt;
+ next_mbox += info->mboxes_std_cnt;
+ flexcan_hwmbox_lock(flexcan, active_mbox, &(info->mboxes[active_mbox].ctrlstat_shadow));
+ flexcan_hwmbox_disable(flexcan, active_mbox); // now disable this message box - it is already locked
+ flexcan_hwmbox_enable_rx(flexcan, next_mbox);
+ }
+ }
+ while (mbox_cnt);
+}
+
+#endif // #ifdef CYGOPT_IO_CAN_EXT_CAN_ID
+
+
+#ifdef CYGOPT_IO_CAN_STD_CAN_ID
+//===========================================================================
+// Flexcan message box isr for standard identifiers if reception of all
+// available messages is enabled
+//===========================================================================
+static cyg_uint32 flexcan_mbox_rx_std_isr(cyg_vector_t vec, cyg_addrword_t data)
+{
+ can_channel *chan = (can_channel *)data;
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+ cyg_uint16 iflag;
+ flexcan_rxmbox_circbuf *prx_mbox_list = &(info->rxmbox_std_circbuf);
+
+ //
+ // number of message box can be calculated from vector that caused
+ // interrupt - we pass this message box number as additional data to the
+ // callback because it is required in the receive event function later
+ //
+ cyg_uint8 mbox = vec - info->isr_vec_mbox0;
+ if (++prx_mbox_list->count < info->mboxes_std_cnt)
+ {
+ prx_mbox_list->idx_wr = (prx_mbox_list->idx_wr + 1) % info->mboxes_std_cnt;
+ flexcan_hwmbox_enable_rx(flexcan, prx_mbox_list->idx_wr);
+ flexcan_hwmbox_lock(flexcan, mbox, &(info->mboxes[mbox].ctrlstat_shadow));
+ flexcan_hwmbox_disable(flexcan, mbox); // now disable this message box - it is already locked
+ //
+ // first we disable interrupts of this message box - the DSR will
+ // reenable it later
+ //
+ flexcan_mboxint_disable(info, mbox);
+ }
+ else
+ {
+ prx_mbox_list->count = info->mboxes_std_cnt;
+ info->mboxes[mbox].ctrlstat_shadow = FLEXCAN_CTRLSTAT_NOT_READ;
+ }
+
+ //
+ // for clearing the interrupt we first read the flag register as 1
+ // and then write it as 1 (and not as zero like the manual stated)
+ // we clear only the flag of this interrupt and leave all other
+ // message box interrupts untouched
+ //
+ HAL_READ_UINT16(&flexcan->IFLAG, iflag);
+ HAL_WRITE_UINT16(&flexcan->IFLAG, (0x0001 << mbox));
+
+ //
+ // On the mcf5272 there is no need to acknowledge internal
+ // interrupts, only external ones.
+ // cyg_drv_interrupt_acknowledge(vec); If counter of mbox list is > 1
+ // then we know that there is already a DSR running and we do not
+ // need to invoke one
+ //
+ if (prx_mbox_list->count > 1)
+ {
+ return CYG_ISR_HANDLED;
+ }
+ else
+ {
+ return CYG_ISR_CALL_DSR;
+ }
+}
+
+
+//===========================================================================
+// Flexcan message box dsr for standard CAN frames
+//===========================================================================
+static void flexcan_mbox_rx_std_dsr(cyg_vector_t vec, cyg_ucount32 count, cyg_addrword_t data)
+{
+ can_channel * chan = (can_channel *)data;
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_rxmbox_circbuf *prx_mbox_list = &(info->rxmbox_std_circbuf);
+ cyg_uint8 mbox;
+ cyg_uint8 mbox_cnt;
+
+ //
+ // we do not process the message box we received as event_id
+ // we take the message boxes from the ring buffer
+ //
+ do
+ {
+ cyg_drv_isr_lock();
+ mbox_cnt = --prx_mbox_list->count;
+ cyg_drv_isr_unlock();
+
+ mbox = prx_mbox_list->idx_rd;
+ prx_mbox_list->idx_rd = (prx_mbox_list->idx_rd + 1) % info->mboxes_std_cnt;
+ chan->callbacks->rcv_event(chan, &mbox);
+ flexcan_mboxint_enable(info, mbox);
+
+ //
+ // if the last message box is enabled, then we have to enable
+ // another one now because the last message box is filled already
+ //
+ if (mbox_cnt == (info->mboxes_std_cnt - 1))
+ {
+ cyg_uint8 active_mbox;
+ cyg_uint8 next_mbox;
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+
+ cyg_drv_isr_lock();
+ active_mbox = prx_mbox_list->idx_wr;
+ next_mbox = prx_mbox_list->idx_wr = (prx_mbox_list->idx_wr + 1) % info->mboxes_ext_cnt;
+ cyg_drv_isr_unlock();
+
+ flexcan_hwmbox_lock(flexcan, active_mbox, &(info->mboxes[active_mbox].ctrlstat_shadow));
+ flexcan_hwmbox_disable(flexcan, active_mbox); // now disable this message box - it is already locked
+ flexcan_hwmbox_enable_rx(flexcan, next_mbox);
+ }
+ }
+ while (mbox_cnt);
+}
+#endif // CYGOPT_IO_CAN_STD_CAN_ID
+
+
//===========================================================================
-static void flexcan_mbox_rx_dsr(cyg_vector_t vec, cyg_ucount32 count, cyg_addrword_t data)
+// FlexCAN DSR for message filters
+//===========================================================================
+static void flexcan_mbox_rx_filt_dsr(cyg_vector_t vec, cyg_ucount32 count, cyg_addrword_t data)
{
can_channel *chan = (can_channel *)data;
flexcan_info *info = (flexcan_info *)chan->dev_priv;
- flexcan_regs *flexcan = (flexcan_regs *)info->base;
- cyg_uint16 imask;
//
// number of message box can be calculated from vector that caused
// processing
//
chan->callbacks->rcv_event(chan, &mbox);
-
+
//
// reenable interrupts for the message box that caused the DSR to run
//
- HAL_READ_UINT16(&flexcan->IMASK, imask);
- HAL_WRITE_UINT16(&flexcan->IMASK, imask | (0x0001 << mbox));
+ flexcan_mboxint_enable(info, mbox);
}
//===========================================================================
//===========================================================================
static cyg_uint32 flexcan_mbox_tx_isr(cyg_vector_t vec, cyg_addrword_t data)
{
- can_channel *chan = (can_channel *)data;
- flexcan_info *info = (flexcan_info *)chan->dev_priv;
- flexcan_regs *flexcan = (flexcan_regs *)info->base;
- cyg_uint16 iflag;
- cyg_uint16 imask;
+ can_channel *chan = (can_channel *)data;
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+ cyg_uint16 iflag;
// number of message box can be calculated from vector that cause
// interrupt - we pass this message box number as additional data to the
// first we disable interrupts of this message box - the DSR will
// reenable it later
//
- HAL_READ_UINT16(&flexcan->IMASK, imask);
- HAL_WRITE_UINT16(&flexcan->IMASK, imask & ~(0x0001 << mbox));
+ flexcan_mboxint_disable(info, mbox);
//
// for clearing the interrupt we first read the flag register as 1
// message box interrupts untouched
//
HAL_READ_UINT16(&flexcan->IFLAG, iflag);
- HAL_WRITE_UINT16(&flexcan->IFLAG, (0x0001 << mbox));
- info->tx_busy = false;
+ HAL_WRITE_UINT16(&flexcan->IFLAG, (0x0001 << mbox));
//
// On the mcf5272 there is no need to acknowledge internal
//===========================================================================
static void flexcan_mbox_tx_dsr(cyg_vector_t vec, cyg_ucount32 count, cyg_addrword_t data)
{
- can_channel *chan = (can_channel *)data;
- flexcan_info *info = (flexcan_info *)chan->dev_priv;
- flexcan_regs *flexcan = (flexcan_regs *)info->base;
- cyg_uint16 imask;
+ can_channel *chan = (can_channel *)data;
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_mbox_info *pmbox;
//
// number of message box can be calculated from vector that caused
// interrupt - we pass this message box number as additional data to the
// callback
//
- cyg_uint8 mbox = vec - info->isr_vec_mbox0;
+ cyg_uint8 mbox = vec - info->isr_vec_mbox0;
+ pmbox = &info->mboxes[mbox];
+
+#ifdef CYGOPT_IO_CAN_TX_EVENT_SUPPORT
+ //
+ // signal CAN TX event to generic IO CAN driver - it will do any further
+ // processing
+ //
+ chan->callbacks->rcv_event(chan, &mbox);
+#endif
+ pmbox->busy = false;
+
//
// send next message
//
//
// reenable interrupts for the message box that caused the DSR to run
//
- HAL_READ_UINT16(&flexcan->IMASK, imask);
- HAL_WRITE_UINT16(&flexcan->IMASK, imask | (0x0001 << mbox));
+ flexcan_mboxint_enable(info, mbox);
}
//===========================================================================
-// START FLEXCAN MODUL
+// Start FlexCAN modul
//===========================================================================
static void flexcan_start_chip(can_channel *chan)
{
flexcan_regs *flexcan = (flexcan_regs *)info->base;
cyg_uint16 tmp16;
+
+ info->state = CYGNUM_CAN_STATE_ACTIVE;
HAL_READ_UINT16(&flexcan->CANMCR, tmp16);
HAL_WRITE_UINT16(&flexcan->CANMCR, tmp16
& ~(FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT));
//===========================================================================
-// SET ACCEPTANCE MASK
+// Stop FlexCAN modul
+//===========================================================================
+static void flexcan_stop_chip(can_channel *chan)
+{
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+ cyg_uint16 tmp16;
+
+ info->state = CYGNUM_CAN_STATE_STOPPED;
+ HAL_READ_UINT16(&flexcan->CANMCR, tmp16);
+ HAL_WRITE_UINT16(&flexcan->CANMCR, tmp16 | FLEXCAN_MCR_HALT);
+}
+
+
+//===========================================================================
+// Set FlexCAN modul into standby mode
+// If the flag selfwake is active then the FlexCAN modul will be set into
+// standby mode with selwake. This means the FlexCAN modul will leave
+// standby as soon as a message box will receive a message
+//===========================================================================
+static void flexcan_enter_standby(can_channel *chan, bool selfwake)
+{
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+ cyg_uint16 tmp16;
+ cyg_uint8 tmp8;
+ cyg_uint8 i;
+
+ //
+ // The CPU should disable all interrupts in the FlexCAN before entering low-power
+ // stop mode. Otherwise it may be interrupted while in STOP mode upon a non
+ // wake-up condition; If desired, the WAKEMASK bit should be set to enable the
+ // WAKEINT.
+ //
+ HAL_READ_UINT8(&flexcan->CANCTRL0, tmp8);
+ HAL_WRITE_UINT8(&flexcan->CANCTRL0, tmp8 & ~(FLEXCAN_CTRL0_BOFFMSK | FLEXCAN_CTRL0_ERRMASK));
+
+ //
+ // We disable all message box interrupts. The WAKE DSR will reenable it later
+ // after processing the WAKE event. This ensures that the wake event will be the
+ // first event if a message arrives
+ //
+ HAL_WRITE_UINT16(&flexcan->IMASK, 0);
+
+ HAL_READ_UINT16(&flexcan->CANMCR, tmp16);
+
+ tmp16 |= FLEXCAN_MCR_STOP;
+
+ //
+ // if we should go to standby then we activate the SELWAKE bit so that a received
+ // frame will bring us back to live
+ //
+ if (selfwake)
+ {
+ tmp16 |= FLEXCAN_MCR_SELFWAKE;
+ }
+
+ HAL_WRITE_UINT16(&flexcan->CANMCR, tmp16);
+
+ //
+ // we have to poll the STOPACK bit in order to determine if chip
+ // has entered stop mode. We poll 10 times - se we spent a maximum
+ // of 2 ms here
+ //
+ for (i = 0; i < 10; ++i)
+ {
+ HAL_READ_UINT16(&flexcan->CANMCR, tmp16);
+
+ if (tmp16 & FLEXCAN_MCR_STOPACK)
+ {
+ info->state = CYGNUM_CAN_STATE_STANDBY;
+ break;
+ }
+ HAL_DELAY_US(200);
+ }
+
+ //
+ // if we are not in low power stop mode then we have to reenable interrupts
+ //
+ if (10 == i)
+ {
+ HAL_READ_UINT8(&flexcan->CANCTRL0, tmp8);
+ HAL_WRITE_UINT8(&flexcan->CANCTRL0, tmp8 | (FLEXCAN_CTRL0_BOFFMSK | FLEXCAN_CTRL0_ERRMASK));
+ }
+ else
+ {
+ //
+ // if we go into standby then we activate the wake interrupt so we will receive
+ // a wake interrupt if we leave standby and can reenable interrups
+ //
+ if (selfwake)
+ {
+ HAL_READ_UINT16(&flexcan->CANMCR, tmp16);
+ HAL_WRITE_UINT16(&flexcan->CANMCR, tmp16 | FLEXCAN_MCR_WAKEMSK);
+ }
+ }
+}
+
+
+//===========================================================================
+// Leave standby mode
+//===========================================================================
+static void flexcan_leave_standby(can_channel *chan)
+{
+ flexcan_info *info = (flexcan_info *)chan->dev_priv;
+ flexcan_regs *flexcan = (flexcan_regs *)info->base;
+ cyg_uint16 tmp16;
+ cyg_uint8 i;
+
+ HAL_READ_UINT16(&flexcan->CANMCR, tmp16);
+ HAL_WRITE_UINT16(&flexcan->CANMCR, tmp16 & ~(FLEXCAN_MCR_STOP | FLEXCAN_MCR_SELFWAKE));
+
+ //
+ // we have to poll the STOPACK bit in order to determine if chip
+ // has leaved stop mode. We poll 10 times - se we spent a maximum
+ // of 2 ms here
+ //
+ for (i = 0; i < 10; ++i)
+ {
+ HAL_READ_UINT16(&flexcan->CANMCR, tmp16);
+
+ if (!(tmp16 & FLEXCAN_MCR_STOPACK))
+ {
+ HAL_WRITE_UINT16(&flexcan->IMASK, info->imask_shadow);
+ info->state = CYGNUM_CAN_STATE_ACTIVE;
+ break;
+ }
+ HAL_DELAY_US(200);
+ } // for (i = 0; i < 10; ++i)
+}
+
+
+//===========================================================================
+// Set acceptance mask for message buffer
//===========================================================================
-static void flexcan_set_acceptance_mask(cyg_uint16 *rxmask_reg, cyg_uint32 mask, cyg_uint8 ext)
+static void flexcan_set_acceptance_mask(cyg_uint16 *rxmask_reg, cyg_uint32 mask, cyg_can_id_type ext)
{
cyg_uint16 id;
//
// 32 bit access to RXMASK filters is broken so we use 16 Bit
// access here
//
- if (ext != 0)
+ if (CYGNUM_CAN_ID_EXT == ext)
{
id = ((mask >> 13) & 0xFFE0); // set mask bits 18 - 28
id |= ((mask >> 15) & 0x7); // set mask bits 15 -17
id = (mask << 1) & 0xFFFE;
HAL_WRITE_UINT16(&rxmask_reg[1], id);
}
- else
+ else // (CYGNUM_CAN_ID_STD == ext)
{
id = ((mask << 5) & 0xFFE0);
HAL_WRITE_UINT16(&rxmask_reg[0], id);
//===========================================================================
-// CONFIGURE MESSAGE BOX FOR TRANSMISSION
+// Configure message box for transmission
//===========================================================================
static bool flexcan_cfg_mbox_tx(flexcan_mbox *pmbox,
cyg_can_message *pmsg,
HAL_WRITE_UINT8(&pmbox->ctrlstat, MBOX_TXCODE_NOT_READY);
- if (pmsg->ext != 0)
+ if (CYGNUM_CAN_ID_EXT == pmsg->ext)
{
id = ((pmsg->id >> 13) & 0xFFE0); // setup id bits 18 - 28
id |= (MBOX_CFG_IDE | MBOX_CFG_SSR); // set SSR and IDE bit to 1
//
// Now copy data bytes into buffer and start transmission
//
- HAL_WRITE_UINT8_VECTOR(&pmbox->data, pmsg->data, pmsg->dlc, 1);
+ HAL_WRITE_UINT8_VECTOR(&pmbox->data, pmsg->data.bytes, pmsg->dlc, 1);
+
if (rtr)
{
HAL_WRITE_UINT8(&pmbox->ctrlstat, MBOX_TXCODE_RESPONSE | pmsg->dlc);
//===========================================================================
-// CONFIGURE MESSAGE BOX FOR RECEPTION OF FRAMES
+// Configure message box for reception of a certain CAN identifier
//===========================================================================
-static void flexcan_cfg_mbox_rx(flexcan_mbox *pmbox,
- cyg_uint32 canid,
- cyg_uint8 ext)
+static void flexcan_cfg_mbox_rx(flexcan_mbox *pmbox,
+ cyg_can_message *pmsg,
+ bool enable)
{
cyg_uint16 id;
HAL_WRITE_UINT8(&pmbox->ctrlstat, MBOX_RXCODE_NOT_ACTIVE);
- if (ext != 0)
+ if (CYGNUM_CAN_ID_EXT == pmsg->ext)
{
- id = ((canid >> 13) & 0xFFE0); // setup id bits 18 - 28
- id |= (MBOX_CFG_IDE | MBOX_CFG_SSR); // set SSR and IDE bit to 1
- id |= ((canid >> 15) & 0x7); // set id bits 15 - 17
- HAL_WRITE_UINT16(&pmbox->id_hi, id); // write ID high
+ id = ((pmsg->id >> 13) & 0xFFE0); // setup id bits 18 - 28
+ id |= (MBOX_CFG_IDE | MBOX_CFG_SSR); // set SSR and IDE bit to 1
+ id |= ((pmsg->id >> 15) & 0x7); // set id bits 15 - 17
+ HAL_WRITE_UINT16(&pmbox->id_hi, id); // write ID high
- id = ((canid << 1) & 0xFFFE);
+ id = ((pmsg->id << 1) & 0xFFFE);
HAL_WRITE_UINT16(&pmbox->id_lo, id);// write ID low
}
else
{
- id = ((canid << 5) & 0xFFE0);
+ id = ((pmsg->id << 5) & 0xFFE0);
HAL_WRITE_UINT16(&pmbox->id_hi, id);
HAL_WRITE_UINT16(&pmbox->id_lo, 0);
}
+ if (enable)
+ {
HAL_WRITE_UINT8(&pmbox->ctrlstat, MBOX_RXCODE_EMPTY);
+ }
}
//===========================================================================
-// READ DATA FROM MESSAGE BOX
+// Read date from a message box
//==========================================================================
static void flexcan_read_from_mbox(can_channel *chan,
cyg_uint8 mbox,
flexcan_mbox *pmbox = &flexcan->mbox[mbox];
cyg_can_message *pmsg = &pevent->msg;
cyg_uint16 id;
- cyg_uint8 i;
+ bool enable_mbox = false;
+ //
+ // If controlstat was not read, then read it now
+ //
+ if (FLEXCAN_CTRLSTAT_NOT_READ == *ctrlstat)
+ {
HAL_READ_UINT8(&pmbox->ctrlstat, *ctrlstat); // this read will lock the mbox
+ enable_mbox = true;
+ }
//
// If message buffer is busy then it is now beeing filled with a new message
- // This condition will be cleared within 20 cycles - wi simply do a 20 us
+ // This condition will be cleared within 20 cycles - we simply do a 20 µs
// delay here, that should be enougth
//
if (*ctrlstat & MBOX_RXCODE_BUSY)
}
pmsg->dlc = (*ctrlstat & MBOX_CFG_DLC_MASK); // store received data len
- pmsg->rtr = 0;
- HAL_READ_UINT16(&pmbox->id_hi, id); // read ID high
+ HAL_READ_UINT16(&pmbox->id_hi, id); // read ID high
if (id & MBOX_CFG_IDE)
{
- pmsg->ext = 1;
+ pmsg->ext = CYGNUM_CAN_ID_EXT;
pmsg->id = (id & 0xFFE0) << 13;
+ pmsg->id |= (id & 0x07) << 15;
HAL_READ_UINT16(&pmbox->id_lo, id);
pmsg->id |= (id & 0xFFFE) >> 1;
+
+ if (id & MBOX_CFG_RTR_EXT)
+ {
+ pmsg->rtr = CYGNUM_CAN_FRAME_RTR;
+ }
+ else
+ {
+ pmsg->rtr = CYGNUM_CAN_FRAME_DATA;
+ }
}
else
{
- pmsg->ext = 0;
+ pmsg->ext = CYGNUM_CAN_ID_STD;
pmsg->id = (id & 0xFFE0) >> 5;
+
+ if (id & MBOX_CFG_RTR_STD)
+ {
+ pmsg->rtr = CYGNUM_CAN_FRAME_RTR;
+ }
+ else
+ {
+ pmsg->rtr = CYGNUM_CAN_FRAME_DATA;
+ }
}
//
// now finally copy data
//
- HAL_READ_UINT8_VECTOR(&pmbox->data, pmsg->data, pmsg->dlc, 1);
+ HAL_READ_UINT8_VECTOR(&pmbox->data, pmsg->data.bytes, pmsg->dlc, 1);
- //
- // now zero out the remaining bytes in can message in order
- // to deliver a defined state
- //
- for (i = pmsg->dlc; i < 8; ++i)
- {
- pmsg->data[i] = 0;
- }
-
//
// now mark this mbox as empty and read the free running timer
// to unlock this mbox
//
+ if (enable_mbox)
+ {
HAL_WRITE_UINT8(&pmbox->ctrlstat, MBOX_RXCODE_EMPTY);
HAL_READ_UINT16(&flexcan->TIMER, id);
+ }
#ifdef CYGOPT_IO_CAN_SUPPORT_TIMESTAMP
pevent->timestamp = id;
#endif
if (pmsg->rtr)
{
- diag_printf("%s [ID:%03X] [RTR:%d] [EXT:%d]\n",
+ diag_printf("%s [ID:%03X] [RTR:%d] [EXT:%d] [DLC:%d]\n",
pMsg,
pmsg->id,
pmsg->rtr,
- pmsg->ext);
+ pmsg->ext,
+ pmsg->dlc);
return;
}
pmsg->id,
pmsg->rtr,
pmsg->ext,
- pmsg->data[0],
- pmsg->data[1],
- pmsg->data[2],
- pmsg->data[3],
- pmsg->data[4],
- pmsg->data[5],
- pmsg->data[6],
- pmsg->data[7]);
+ pmsg->data.bytes[0],
+ pmsg->data.bytes[1],
+ pmsg->data.bytes[2],
+ pmsg->data.bytes[3],
+ pmsg->data.bytes[4],
+ pmsg->data.bytes[5],
+ pmsg->data.bytes[6],
+ pmsg->data.bytes[7]);
}
"ESTY ",
"ALOS ",
"DEVC ",
+ "PHYF ",
+ "PHYH ",
+ "PHYL "
};
i = 0;
while (flags && (i < 16))
+2006-11-17 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * src/ide_disk.c (ide_read_sector, ide_write_sector): Length
+ is counted in sectors now, not bytes (due to change in io/disk
+ API).
+
+2006-09-21 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * src/ide_disk.h: DISK_FUNS is now implicitly static.
+ (IDE_DISK_INSTANCE): Reflect updated io/disk API by using
+ ide_disk_controller.
+ * src/ide_disk.c: Define ide_disk_controller (even though unused
+ in practice).
+ (ide_disk_init): Provide phys_block_size and max_transfer disk ident
+ members.
+
2005-02-02 Knud Woehler <knud.woehler@microplex.de>
* src/ide_disk.c: Check the device is not busy before sending a
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Red Hat, Inc.
-// Copyright (C) 2004 eCosCentric, Ltd.
+// Copyright (C) 2004, 2006 eCosCentric, Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Red Hat, Inc.
-// Copyright (C) 2004 eCosCentric, Ltd.
+// Copyright (C) 2004, 2006 eCosCentric, Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// ----------------------------------------------------------------------------
+// No h/w controller structure is needed in this driver, but the address of the
+// second argument is taken anyway.
+DISK_CONTROLLER(ide_disk_controller, ide_disk_controller);
+
#ifdef CYGVAR_DEVS_DISK_IDE_DISK0
IDE_DISK_INSTANCE(0, 0, 0, true, CYGDAT_IO_DISK_IDE_DISK0_NAME);
#endif
for (j = 0, c=0 ; j < (CYGDAT_DEVS_DISK_IDE_SECTOR_SIZE / sizeof(cyg_uint16));
j++) {
HAL_IDE_READ_UINT16(ctlr, IDE_REG_DATA, p);
- if (c++<len) *b++=p&0xff;
- if (c++<len) *b++=(p>>8)&0xff;
+ if (c++<(len*512)) *b++=p&0xff;
+ if (c++<(len*512)) *b++=(p>>8)&0xff;
}
return 1;
}
//
for (j = 0, c=0 ; j < (CYGDAT_DEVS_DISK_IDE_SECTOR_SIZE / sizeof(cyg_uint16));
j++) {
- p = (c++<len) ? *b++ : 0;
- p |= (c++<len) ? (*b++<<8) : 0;
+ p = (c++<(len*512)) ? *b++ : 0;
+ p |= (c++<(len*512)) ? (*b++<<8) : 0;
HAL_IDE_WRITE_UINT16(ctlr, IDE_REG_DATA, p);
}
return 1;
ident.sectors_num = ide_idData->num_sectors;
ident.lba_sectors_num = ide_idData->lba_total_sectors[1] << 16 |
ide_idData->lba_total_sectors[0];
+ ident.phys_block_size = 1;
+ ident.max_transfer = 512;
D("\tSerial : %s\n", ident.serial);
D("\tFirmware rev. : %s\n", ident.firmware_rev);
struct cyg_devtab_entry *sub_tab,
const char *name);
-static DISK_FUNS(ide_disk_funs,
- ide_disk_read,
- ide_disk_write,
- ide_disk_get_config,
- ide_disk_set_config
+DISK_FUNS(ide_disk_funs,
+ ide_disk_read,
+ ide_disk_write,
+ ide_disk_get_config,
+ ide_disk_set_config
);
// ----------------------------------------------------------------------------
DISK_CHANNEL(ide_disk_channel##_number_, \
ide_disk_funs, \
ide_disk_info##_number_, \
+ ide_disk_controller, \
_mbr_supp_, \
4 \
); \
+2006-02-03 Nick Garnett <nickg@ecoscentric.com>
+
+ * src/synthdisk.c: Updated to match changes in io/disk package.
+
2004-07-01 Savin Zlobec <savin@elatec.si>
* src/synthdisk.c:
Updated to work with the new DISK_CHANNEL macro definition.
-2004-01-15 Nick Garnett <nickg@calivar.com>
+2004-04-15 Nick Garnett <nickg@ecoscentric.com>
+
+ * src/synthdisk.c: Mildly reorganized to support changeable
+ media. Added synth_disk_change() function to allow us to fake a
+ disk change for testing purposes.
+
+2004-02-05 Nick Garnett <nickg@ecoscentric.com>
+
+ * cdl/synthdisk.cdl: Added testing config options, plus
+ define_proc to export CYGDAT_DEVS_DISK_CFG include file name.
+
+2004-01-30 Nick Garnett <nickg@ecoscentric.com>
+
+ * src/synthdisk.c: Updated to latest disk device specification.
+
+2004-01-15 Nick Garnett <nickg@ecoscentric.com>
* cdl/synthdisk.cdl:
* src/synthdisk.c:
Added _FILENAME option for disk instances to map device to an
- arbitrary cinfigured file.
+ arbitrary configured file.
* src/synthdisk.c: Removed block_pos arguments from read
and write calls: it is not necessary.
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 2003 Savin Zlobec
+// Copyright (C) 2003 Savin Zlobec
+// Copyright (C) 2004, 2006 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
-## Copyright (C) 2003 Savin Zlobec
+## Copyright (C) 2003 Savin Zlobec
+## Copyright (C) 2004 eCosCentric Limited
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
active_if CYGPKG_IO_DISK
active_if CYGPKG_HAL_SYNTH
+ define_proc {
+ puts $::cdl_system_header "/***** Synthdisk driver proc output start *****/"
+ puts $::cdl_system_header "#define CYGDAT_DEVS_DISK_CFG <pkgconf/devs_disk_ecosynth.h>"
+ puts $::cdl_system_header "/***** Synthdisk driver proc output end *****/"
+ }
+
cdl_component CYGVAR_DEVS_DISK_ECOSYNTH_DISK0 {
display "Provide disk 0 device"
flavor bool
cdl_option CYGDAT_IO_DISK_ECOSYNTH_DISK0_NAME {
display "Device name for ecosynth disk 0 device"
flavor data
- default_value {"\"/dev/disk0/\""}
+ default_value {"\"/dev/hd0/\""}
description "This is the device name used to access this
device in eCos. Note that the trailing slash
character must be present."
the set of global flags if present."
}
}
+
+ cdl_component CYGPKG_DEVS_DISK_ECOSYNTH_TESTING {
+ display "Testing configuration"
+ default_value 1
+
+ cdl_option CYGDAT_DEVS_DISK_TEST_DEVICE {
+ display "Test device driver"
+ flavor data
+ default_value {"\"/dev/hd0/1\"" }
+ }
+
+ cdl_option CYGDAT_DEVS_DISK_TEST_MOUNTPOINT {
+ display "Test filesystem mountpoint"
+ flavor data
+ default_value {"\"/dosfs\"" }
+ }
+
+ cdl_option CYGDAT_DEVS_DISK_TEST_DIRECTORY {
+ display "Test directory on test device"
+ flavor data
+ default_value {"\"/test\"" }
+ }
+
+
+ cdl_option CYGDAT_DEVS_DISK_TEST_DEVICE2 {
+ display "Second Test device driver"
+ flavor data
+ default_value {"\"/dev/hd0/2\"" }
+ }
+
+ cdl_option CYGDAT_DEVS_DISK_TEST_MOUNTPOINT2 {
+ display "Second Test filesystem mountpoint"
+ flavor data
+ default_value {"\"/dosfs2\"" }
+ }
+
+ cdl_option CYGDAT_DEVS_DISK_TEST_DIRECTORY2 {
+ display "Test directory on second test device"
+ flavor data
+ default_value {"\"/test\"" }
+ }
+
+ }
+
}
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 2003 Savin Zlobec.
+// Copyright (C) 2003 Savin Zlobec
+// Copyright (C) 2004, 2006 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
char *filename;
} synth_disk_info_t;
+typedef struct { int dummy; } synth_controller_t;
+
// ----------------------------------------------------------------------------
static cyg_bool synth_disk_init(struct cyg_devtab_entry *tab);
struct cyg_devtab_entry *sub_tab,
const char *name);
-static DISK_FUNS(synth_disk_funs,
- synth_disk_read,
- synth_disk_write,
- synth_disk_get_config,
- synth_disk_set_config
+DISK_FUNS(synth_disk_funs,
+ synth_disk_read,
+ synth_disk_write,
+ synth_disk_get_config,
+ synth_disk_set_config
);
// ----------------------------------------------------------------------------
-#define SYNTH_DISK_INSTANCE(_number_,_mbr_supp_, _cyl_,_hpt_,_spt_) \
-static synth_disk_info_t synth_disk_info##_number_ = { \
- num: _number_, \
- cylinders_num: _cyl_, \
- heads_num: _hpt_, \
- sectors_num: _spt_, \
- size: CYGNUM_IO_DISK_ECOSYNTH_DISK##_number_##_SIZE, \
- filefd: -1, \
- filename: CYGDAT_IO_DISK_ECOSYNTH_DISK##_number_##_FILENAME \
-}; \
-DISK_CHANNEL(synth_disk_channel##_number_, \
- synth_disk_funs, \
- synth_disk_info##_number_, \
- _mbr_supp_, \
- 4 \
-); \
-BLOCK_DEVTAB_ENTRY(synth_disk_io##_number_, \
- CYGDAT_IO_DISK_ECOSYNTH_DISK##_number_##_NAME, \
- 0, \
- &cyg_io_disk_devio, \
- synth_disk_init, \
- synth_disk_lookup, \
- &synth_disk_channel##_number_ \
+
+#define SYNTH_DISK_INSTANCE(_number_,_mbr_supp_, _cyl_,_hpt_,_spt_) \
+static synth_disk_info_t synth_disk_info##_number_ = { \
+ num: _number_, \
+ cylinders_num: _cyl_, \
+ heads_num: _hpt_, \
+ sectors_num: _spt_, \
+ size: CYGNUM_IO_DISK_ECOSYNTH_DISK##_number_##_SIZE, \
+ filefd: -1, \
+ filename: CYGDAT_IO_DISK_ECOSYNTH_DISK##_number_##_FILENAME \
+}; \
+static synth_controller_t synth_controller_##_number_; \
+DISK_CONTROLLER( synth_disk_controller_##_number_, synth_controller_##_number_ ); \
+DISK_CHANNEL(synth_disk_channel##_number_, \
+ synth_disk_funs, \
+ synth_disk_info##_number_, \
+ synth_disk_controller_##_number_, \
+ _mbr_supp_, \
+ 4 \
+); \
+BLOCK_DEVTAB_ENTRY(synth_disk_io##_number_, \
+ CYGDAT_IO_DISK_ECOSYNTH_DISK##_number_##_NAME, \
+ 0, \
+ &cyg_io_disk_devio, \
+ synth_disk_init, \
+ synth_disk_lookup, \
+ &synth_disk_channel##_number_ \
);
// ----------------------------------------------------------------------------
if (result)
{
- cyg_disk_identify_t ident;
-
- ident.serial[0] = '\0';
- ident.firmware_rev[0] = '\0';
- ident.model_num[0] = '\0';
- ident.lba_sectors_num = synth_info->size / 512;
- ident.cylinders_num = synth_info->cylinders_num;
- ident.heads_num = synth_info->heads_num;
- ident.sectors_num = synth_info->sectors_num;
if (!(chan->callbacks->disk_init)(tab))
return false;
- if (ENOERR != (chan->callbacks->disk_connected)(tab, &ident))
- return false;
}
return result;
}
+// ----------------------------------------------------------------------------
+
static Cyg_ErrNo
-synth_disk_lookup(struct cyg_devtab_entry **tab,
+synth_disk_lookup(struct cyg_devtab_entry **tab,
struct cyg_devtab_entry *sub_tab,
const char *name)
{
+ Cyg_ErrNo res;
disk_channel *chan = (disk_channel *) (*tab)->priv;
- return (chan->callbacks->disk_lookup(tab, sub_tab, name));
+ synth_disk_info_t *synth_info = (synth_disk_info_t *) chan->dev_priv;
+ cyg_disk_identify_t ident;
+
+ ident.serial[0] = '\0';
+ ident.firmware_rev[0] = '\0';
+ ident.model_num[0] = '\0';
+ ident.lba_sectors_num = synth_info->size / 512;
+ ident.cylinders_num = synth_info->cylinders_num;
+ ident.heads_num = synth_info->heads_num;
+ ident.sectors_num = synth_info->sectors_num;
+ ident.phys_block_size = 1;
+ ident.max_transfer = 2048;
+
+ res = (chan->callbacks->disk_connected)(*tab, &ident);
+
+ if( res == ENOERR )
+ res = (chan->callbacks->disk_lookup(tab, sub_tab, name));
+
+ return res;
}
+// ----------------------------------------------------------------------------
+
static Cyg_ErrNo
synth_disk_read(disk_channel *chan,
void *buf,
cyg_hal_sys_lseek(synth_info->filefd,
block_num * chan->info->block_size,
CYG_HAL_SYS_SEEK_SET);
- cyg_hal_sys_read(synth_info->filefd, buf, len);
+ cyg_hal_sys_read(synth_info->filefd, buf, len*512);
return ENOERR;
}
return -EIO;
}
+// ----------------------------------------------------------------------------
+
static Cyg_ErrNo
synth_disk_write(disk_channel *chan,
const void *buf,
cyg_hal_sys_lseek(synth_info->filefd,
block_num * chan->info->block_size,
CYG_HAL_SYS_SEEK_SET);
- cyg_hal_sys_write(synth_info->filefd, buf, len);
+ cyg_hal_sys_write(synth_info->filefd, buf, len*512);
// cyg_hal_sys_fdatasync(synth_info->filefd);
return ENOERR;
}
return -EIO;
}
+// ----------------------------------------------------------------------------
+
static Cyg_ErrNo
synth_disk_get_config(disk_channel *chan,
cyg_uint32 key,
return -EINVAL;
}
+// ----------------------------------------------------------------------------
+
static Cyg_ErrNo
synth_disk_set_config(disk_channel *chan,
cyg_uint32 key,
const void *xbuf,
cyg_uint32 *len)
{
-
+ Cyg_ErrNo res = ENOERR;
#ifdef DEBUG
diag_printf("synth disk set config\n");
#endif
-
- return -EINVAL;
+
+ switch ( key )
+ {
+ case CYG_IO_SET_CONFIG_DISK_MOUNT:
+ // We have nothing to do here for this option.
+ break;
+
+ case CYG_IO_SET_CONFIG_DISK_UMOUNT:
+ if( chan->info->mounts == 0 )
+ {
+ // If this is the last unmount of this disk, then disconnect it from
+ // the driver system so the user can swap it out if he wants.
+ res = (chan->callbacks->disk_disconnected)(chan);
+ }
+ break;
+
+ default:
+ res = -EINVAL;
+ break;
+ }
+
+ return res;
+}
+
+// ----------------------------------------------------------------------------
+
+externC cyg_bool synth_disk_change( int unit, char *filename, int size,
+ int cyls, int heads, int sectors)
+{
+ struct cyg_devtab_entry *tab = &synth_disk_io0;
+ disk_channel *chan = (disk_channel *) tab->priv;
+ synth_disk_info_t *synth_info = (synth_disk_info_t *) chan->dev_priv;
+ int err = 0;
+
+ if (!chan->init)
+ return false;
+
+ synth_info->filename = filename;
+ synth_info->size = size;
+ synth_info->cylinders_num = cyls;
+ synth_info->heads_num = heads;
+ synth_info->sectors_num = sectors;
+
+#ifdef DEBUG
+ diag_printf("synth disk %d change size=%d\n",
+ synth_info->num, synth_info->size);
+#endif
+
+ err = cyg_hal_sys_close( synth_info->filefd );
+
+#ifdef DEBUG
+ if( err != 0 )
+ {
+ diag_printf("synth disk change, failed to close old image: %d\n",err);
+ }
+#endif
+
+ synth_info->filefd = cyg_hal_sys_open(synth_info->filename,
+ CYG_HAL_SYS_O_RDWR,
+ CYG_HAL_SYS_S_IRWXU|CYG_HAL_SYS_S_IRWXG|CYG_HAL_SYS_S_IRWXO);
+
+ if (-ENOENT == synth_info->filefd)
+ {
+ synth_info->filefd = cyg_hal_sys_open(synth_info->filename,
+ CYG_HAL_SYS_O_RDWR|CYG_HAL_SYS_O_CREAT, 0644);
+
+ if (synth_info->filefd >= 0)
+ {
+ unsigned char b = 0x00;
+ int i;
+
+ for (i = 0; i < synth_info->size; i++)
+ cyg_hal_sys_write(synth_info->filefd, &b, 1);
+ }
+ }
+
+ if (synth_info->filefd < 0)
+ {
+ CYG_ASSERT(false, "Can't open/create disk image file");
+ return false;
+ }
+
+ return true;
}
// ----------------------------------------------------------------------------
+2006-09-21 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * src/v85x_edb_v850_disk.c (cf_disk_init): Provide phys_block_size
+ and max_transfer disk ident members.
+
+2006-09-20 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * src/v85x_edb_v850_disk.c:
+ DISK_CHANNEL and DISK_FUNS are now implicitly static.
+ Update DISK_CHANNEL for new io/disk macro.
+
2004-07-02 Savin Zlobec <savin@elatec.si>
* src/v85x_edb_v850_disk.c:
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2006 eCosCentric Ltd.
// Copyright (C) 2003 Savin Zlobec
//
// eCos is free software; you can redistribute it and/or modify it under
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 2003 Savin Zlobec.
+// Copyright (C) 2006 eCosCentric Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
struct cyg_devtab_entry *sub_tab,
const char *name);
-static DISK_FUNS(cf_disk_funs,
- cf_disk_read,
- cf_disk_write,
- cf_disk_get_config,
- cf_disk_set_config
+DISK_FUNS(cf_disk_funs,
+ cf_disk_read,
+ cf_disk_write,
+ cf_disk_get_config,
+ cf_disk_set_config
);
// ----------------------------------------------------------------------------
+// No h/w controller structure is needed, but the address of the
+// second argument is taken anyway.
+DISK_CONTROLLER(cf_disk_controller, cf_disk_controller);
+
#define CF_DISK_INSTANCE(_number_,_base_,_mbr_supp_,_name_) \
static cf_disk_info_t cf_disk_info##_number_ = { \
base: (volatile cyg_uint16 *)_base_, \
DISK_CHANNEL(cf_disk_channel##_number_, \
cf_disk_funs, \
cf_disk_info##_number_, \
+ cf_disk_controller, \
_mbr_supp_, \
4 \
); \
ident.sectors_num = ata_id->num_sectors;
ident.lba_sectors_num = ata_id->lba_total_sectors[1] << 16 |
ata_id->lba_total_sectors[0];
-
+ ident.phys_block_size = 1;
+ ident.max_transfer = 512;
if (!(chan->callbacks->disk_init)(tab))
return false;
cdl_interface CYGINT_DEVS_ETH_CL_CS8900A_REQUIRED {
display "Cirrus Logic CS8900A ethernet driver required"
}
-
- cdl_interface CYGINT_DEVS_ETH_FEC_REQUIRED {
- display "FEC ethernet driver required"
- }
-
+
define_proc {
puts $::cdl_system_header "/***** ethernet driver proc output start *****/"
puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_CL_CS8900A_INL <cyg/io/devs_eth_arm_board.inl>"
implements CYGHWR_NET_DRIVER_ETH0
implements CYGINT_DEVS_ETH_CL_CS8900A_REQUIRED
- implements CYGINT_DEVS_ETH_FEC_REQUIRED
-
cdl_option CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME {
display "Device name for the ETH0 ethernet driver"
flavor data
"eth0_esa", true,
CONFIG_ESA, 0
);
-RedBoot_config_option("Set FEC network hardware address [MAC]",
- fec_esa,
- ALWAYS_ENABLED, true,
- CONFIG_BOOL, false
- );
-RedBoot_config_option("FEC network hardware address [MAC]",
- fec_esa_data,
- "fec_esa", true,
- CONFIG_ESA, 0
- );
#endif // CYGPKG_REDBOOT && CYGSEM_REDBOOT_FLASH_CONFIG
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
return ok && set_esa;
}
-void _board_provide_fec_esa(void)
-{
- cyg_bool set_esa;
- cyg_uint8 addr[6];
- int ok;
-
- ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,
- "fec_esa", &set_esa, CONFIG_BOOL);
- diag_printf("Ethernet FEC MAC address: ");
- if (ok && set_esa) {
- CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,
- "fec_esa_data", addr, CONFIG_ESA);
- //diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
- // addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
- if(sys_ver == SOC_SILICONID_Rev1_0) {
- writel(addr[5], SOC_FEC_MAC_BASE + 0x0);
- writel(addr[4], SOC_FEC_MAC_BASE + 0x4);
- writel(addr[3], SOC_FEC_MAC_BASE + 0x8);
- writel(addr[2], SOC_FEC_MAC_BASE + 0xC);
- writel(addr[1], SOC_FEC_MAC_BASE + 0x10);
- writel(addr[0], SOC_FEC_MAC_BASE + 0x14);
- addr[5] = readl(SOC_FEC_MAC_BASE + 0x0);
- addr[4] = readl(SOC_FEC_MAC_BASE + 0x4);
- addr[3] = readl(SOC_FEC_MAC_BASE + 0x8);
- addr[2] = readl(SOC_FEC_MAC_BASE + 0xC);
- addr[1] = readl(SOC_FEC_MAC_BASE + 0x10);
- addr[0] = readl(SOC_FEC_MAC_BASE + 0x14);
- } else {
- writel(addr[5], SOC_FEC_MAC_BASE2 + 0x0);
- writel(addr[4], SOC_FEC_MAC_BASE2 + 0x4);
- writel(addr[3], SOC_FEC_MAC_BASE2 + 0x8);
- writel(addr[2], SOC_FEC_MAC_BASE2 + 0xC);
- writel(addr[1], SOC_FEC_MAC_BASE2 + 0x10);
- writel(addr[0], SOC_FEC_MAC_BASE2 + 0x14);
- addr[5] = readl(SOC_FEC_MAC_BASE2 + 0x0);
- addr[4] = readl(SOC_FEC_MAC_BASE2 + 0x4);
- addr[3] = readl(SOC_FEC_MAC_BASE2 + 0x8);
- addr[2] = readl(SOC_FEC_MAC_BASE2 + 0xC);
- addr[1] = readl(SOC_FEC_MAC_BASE2 + 0x10);
- addr[0] = readl(SOC_FEC_MAC_BASE2 + 0x14);
- }
- diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
- addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
- } else {
- diag_printf("is not set\n");
- }
-}
-
-RedBoot_init(_board_provide_fec_esa, RedBoot_INIT_LAST);
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+2005-11-17 Harald Brandl <Harald.Brandl@fh-joanneum.at>
+
+ * Fixed data alignment problems. Cleaned up the naming of
+ functions to avoid name space pollution. Us the HAL macros to
+ access the hardware.
+
2005-06-12 Harald Brandl <Harald.Brandl@fh-joanneum.at>
* First import of an ethernet device driver for the NETARM
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-## Copyright (C) 2005 eCosCentric LTD
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
active_if CYGPKG_IO_ETH_DRIVERS
+
compile -library=libextras.a MII.c netarm_eth_drv.c eeprom.c
define_proc {
-
diff -Naur orig/hal/arm/netarm/current/include/hal_platform_setup.h new/hal/arm/netarm/current/include/hal_platform_setup.h
--- orig/hal/arm/netarm/current/include/hal_platform_setup.h 2004-11-29 17:35:46.000000000 +0100
-+++ new/hal/arm/netarm/current/include/hal_platform_setup.h 2005-03-14 17:10:01.542675500 +0100
++++ new/hal/arm/netarm/current/include/hal_platform_setup.h 2005-03-15 12:20:27.760534400 +0100
@@ -19,7 +19,7 @@
// Usage: #include <cyg/hal/hal_platform_setup.h>
//
ldr r0,=0x4004a800 /* System control register */
str r0,[r1]
-+#ifdef CYG_HAL_STARTUP_ROM
- mov r0,#0 /* PLL config */
+- mov r0,#0 /* PLL config */
++#ifdef CYG_HAL_STARTUP_ROM /* PLL config */
++ mov r0,#0
+#else
+ ldr r0,=0x09000e1e
+#endif
/* Configure SDRAM */
- ldr r0,=0xf38000b0 /* CS1 Option register, BLEN=11 */
-+ ldr r0,=0xf3000070 /* CS1 Option register, BLEN=11 (0xf38000b0)*/
++ ldr r0,=0xf3000070 /* CS1 Option register, BLEN=11 */
str r0,[r1,#0x24]
ldr r0,=0x0000022d /* CS1 Base Address register */
}
-
-
+diff -Naur orig/hal/arm/netarm/current/include/plf_mmap.h new/hal/arm/netarm/current/include/plf_mmap.h
+--- orig/hal/arm/netarm/current/include/plf_mmap.h 1970-01-01 01:00:00.000000000 +0100
++++ new/hal/arm/netarm/current/include/plf_mmap.h 2005-04-01 11:13:23.378304500 +0200
+@@ -0,0 +1,62 @@
++#ifndef CYGONCE_HAL_NETARM_PLATFORM_PLF_MMAP_H
++#define CYGONCE_HAL_NETARM_PLATFORM_PLF_MMAP_H
++//==========================================================================
++//
++// plf_mmap.h
++//
++// Platform specific memory map support
++//
++//==========================================================================
++//####ECOSGPLCOPYRIGHTBEGIN####
++// -------------------------------------------
++// This file is part of eCos, the Embedded Configurable Operating System
++// Copyright (C) 2005 eCosCentric Ltd.
++//
++// eCos is free software; you can redistribute it and/or modify it under
++// the terms of the GNU General Public License as published by the Free
++// Software Foundation; either version 2 or (at your option) any later version.
++//
++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
++// WARRANTY; without even the implied warranty of MERCHANTABILITY or
++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++// for more details.
++//
++// You should have received a copy of the GNU General Public License along
++// with eCos; if not, write to the Free Software Foundation, Inc.,
++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
++//
++// As a special exception, if other files instantiate templates or use macros
++// or inline functions from this file, or you compile this file and link it
++// with other works to produce a work based on this file, this file does not
++// by itself cause the resulting work to be covered by the GNU General Public
++// License. However the source code for this file must still be made available
++// in accordance with section (3) of the GNU General Public License.
++//
++// This exception does not invalidate any other reasons why a work based on
++// this file might be covered by the GNU General Public License.
++//
++// -------------------------------------------
++//####ECOSGPLCOPYRIGHTEND####
++//==========================================================================
++//#####DESCRIPTIONBEGIN####
++//
++// Author(s): Harald Brandl (harald.brandl@fh-joanneum.at)
++// Contributors: Harald Brandl
++// Date: 01.04.2005
++// Purpose: NET+ARM memory map macro
++// Description:
++//
++//####DESCRIPTIONEND####
++//
++//==========================================================================
++
++
++extern unsigned int _dataram;
++
++
++#define HAL_CACHED_TO_UNCACHED_ADDRESS( caddr, uaddr, type ) CYG_MACRO_START \
++ uaddr = (type)((cyg_uint32)caddr - (cyg_uint32)(&_dataram)); \
++CYG_MACRO_END
++
++//---------------------------------------------------------------------------
++#endif // CYGONCE_HAL_NETARM_PLATFORM_PLF_MMAP_H
diff -Naur orig/hal/arm/netarm/current/src/netarm_misc.c new/hal/arm/netarm/current/src/netarm_misc.c
--- orig/hal/arm/netarm/current/src/netarm_misc.c 2004-11-29 17:35:48.000000000 +0100
+++ new/hal/arm/netarm/current/src/netarm_misc.c 2005-02-22 11:57:58.296703200 +0100
The HAL for the ARM NET+50 can be downloaded at ftp.mind.be
-To support data and instruction caching I made some modification to
-the HAL that are available as a patch to be found in this
-directory. Applying this patch is optional, but should improve
-performance.
+To support data and instruction caching I made some modification
+to the HAL that are available as patch.
\ No newline at end of file
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 2005 eCosCentric LTD
+// Copyright (C) 2005 eCosCentric Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
+//
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
-// Author(s): Harald Brandl (harald.brandl@fh-joanneum.at)
-// Contributors: Harald Brandl
-// Date: 01.08.2004
-// Purpose: PHY chip configuration
+// Author(s): Harald Brandl (harald.brandl@fh-joanneum.at)
+// Contributors: Harald Brandl
+// Date: 01.08.2004
+// Purpose: PHY chip configuration
// Description:
//
//####DESCRIPTIONEND####
//
//==========================================================================
-#include <stdio.h>
-#include <pkgconf/devs_eth_arm_netarm.h>
-#include <cyg/hal/hal_diag.h>
-#include <cyg/hal/hal_io.h>
#include "eth_regs.h"
+
#define PHYS(_i_) (0x800 | _i_)
-#define SysReg (unsigned int*)0xffb00004 // System Status Register
+#define SysReg (unsigned *)0xffb00004 // System Status Register
-/* Function: void mii_poll_busy (void)
+/* Function: void cyg_netarm_mii_poll_busy (void)
*
* Description:
* This routine is responsible for waiting for the current PHY
* none
*/
-void mii_poll_busy(void)
+static void
+mii_poll_busy(void)
{
- /* check to see if PHY is busy with read or write */
- while (MIIIR & 1)
- HAL_DELAY_US(1);
+ unsigned reg;
+ /* check to see if PHY is busy with read or write */
+ do
+ {
+ HAL_READ_UINT32(MIIIR, reg);
+ }while (reg & 1);
}
-/* Function: void mii_reset (void)
+/* Function: void cyg_netarm_mii_reset (void)
*
* Description:
*
* none
*/
-void mii_reset(void)
+void
+cyg_netarm_mii_reset(void)
{
- MIIAR = PHYS(0); // select command register
- MIIWDR = 0x8000; // reset
- mii_poll_busy();
+ HAL_WRITE_UINT32(MIIAR, PHYS(0)); // select command register
+ HAL_WRITE_UINT32(MIIWDR, 0x8000); // reset
+ mii_poll_busy();
}
-/* Function: cyg_bool mii_negotiate (void)
+/* Function: cyg_bool cyg_netarm_mii_negotiate (void)
*
* Description:
* This routine is responsible for causing the external Ethernet PHY
* 1: ERROR
*/
-cyg_bool mii_negotiate(void)
+cyg_bool
+cyg_netarm_mii_negotiate(void)
{
- int timeout = 100000;
-
- MIIAR = PHYS(4);
-
- mii_poll_busy();
-
- MIIAR = PHYS(0);
- MIIWDR |= 0x1200;
-
- mii_poll_busy();
-
- while(timeout)
- {
- MIIAR = PHYS(1);
- MIICR = 1;
-
- mii_poll_busy();
-
- if(0x24 == (MIIRDR & 0x24))
- return 0;
- else
- timeout--;
- }
-
- return 1;
+ unsigned timeout = 100000, reg;
+
+ HAL_WRITE_UINT32(MIIAR, PHYS(4));
+
+ mii_poll_busy();
+
+ HAL_WRITE_UINT32(MIIAR, PHYS(0));
+ HAL_OR_UINT32(MIIWDR, 0x1200);
+
+ mii_poll_busy();
+
+ while(timeout)
+ {
+ HAL_WRITE_UINT32(MIIAR, PHYS(1));
+ HAL_WRITE_UINT32(MIICR, 1);
+
+ mii_poll_busy();
+
+ HAL_READ_UINT32(MIIRDR, reg);
+
+ if(0x24 == (reg & 0x24))
+ return 0;
+ else
+ timeout--;
+ }
+
+ return 1;
}
-/* Function: void mii_set_speed (cyg_bool speed, cyg_bool duplex)
+/* Function: void cyg_netarm_mii_set_speed (cyg_bool speed, cyg_bool duplex)
*
* Description:
*
* none
*/
-void mii_set_speed(cyg_bool speed, cyg_bool duplex)
+void
+cyg_netarm_mii_set_speed(cyg_uint32 speed, cyg_bool duplex)
{
- unsigned long int timeout = 1000000;
-
- MIIAR = PHYS(0); // select command register
- MIIWDR = (speed << 13) | (duplex << 8); // set speed and duplex
- mii_poll_busy();
-
-
- while(timeout)
- {
- MIIAR = PHYS(1); // select status register
- MIICR = 1;
- mii_poll_busy();
- if((MIIRDR) & 0x4)
- break;
- timeout--;
- }
+ unsigned timeout = 1000000, reg;
+
+ HAL_WRITE_UINT32(MIIAR, PHYS(0)); // select command register
+ HAL_WRITE_UINT32(MIIWDR, (speed << 13) | (duplex << 8)); // set speed and duplex
+ mii_poll_busy();
+
+ while(timeout)
+ {
+ HAL_WRITE_UINT32(MIIAR, PHYS(1)); // select status register
+ HAL_WRITE_UINT32(MIICR, 1);
+ mii_poll_busy();
+ HAL_READ_UINT32(MIIRDR, reg);
+ if(reg & 0x4)
+ break;
+ timeout--;
+ }
}
-/* Function: cyg_bool mii_check_speed
+/* Function: cyg_bool cyg_netarm_mii_check_speed
*
* Description:
*
* 1: 100Mbit Speed
*/
-cyg_bool mii_check_speed(void)
+cyg_uint32
+cyg_netarm_mii_check_speed(void)
{
- MIIAR = PHYS(17);
- MIICR = 1;
- mii_poll_busy();
- return (MIIRDR >> 14) & 1;
+ unsigned reg;
+
+ HAL_WRITE_UINT32(MIIAR, PHYS(17));
+ HAL_WRITE_UINT32(MIICR, 1);
+ mii_poll_busy();
+ HAL_READ_UINT32(MIIRDR, reg);
+ return (reg >> 14) & 1;
}
-/* Function: void mii_check_duplex
+/* Function: void cyg_netarm_mii_check_duplex
*
* Description:
*
* 1: Full Duplex
*/
-cyg_bool mii_check_duplex(void)
+cyg_bool
+cyg_netarm_mii_check_duplex(void)
{
- MIIAR = PHYS(17);
- MIICR = 1;
- mii_poll_busy();
- return (MIIRDR >> 9) & 1;
+ unsigned reg;
+
+ HAL_WRITE_UINT32(MIIAR, PHYS(17));
+ HAL_WRITE_UINT32(MIICR, 1);
+ mii_poll_busy();
+ HAL_READ_UINT32(MIIRDR, reg);
+ return (reg >> 9) & 1;
}
-#ifndef _NETARM_MII_
-#define _NETARM_MII_
+#ifndef CYGONCE_DEVS_ETH_ARM_NETARM_MII_H
+#define CYGONCE_DEVS_ETH_ARM_NETARM_MII_H
// ====================================================================
//
// MII.h
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 2005 eCosCentric LTD
+// Copyright (C) 2005 eCosCentric Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
+//
+//####ECOSGPLCOPYRIGHTEND####
// ====================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Harald Brandl (harald.brandl@fh-joanneum.at)
// Contributors: Harald Brandl
-// Date: 01.08.2004
-// Purpose: Functions for PHY control
+// Date: 01.08.2004
+// Purpose: Functions for PHY control
// Description:
//
//####DESCRIPTIONEND####
//
// ====================================================================
-void mii_reset(void);
-void mii_set_speed (cyg_bool speed, cyg_bool duplex);
-cyg_bool mii_check_speed(void);
-cyg_bool mii_check_duplex(void);
-cyg_bool mii_negotiate(void);
+void cyg_netarm_mii_reset(void);
+void cyg_netarm_mii_set_speed (cyg_uint32 speed, cyg_bool duplex);
+cyg_uint32 cyg_netarm_mii_check_speed(void);
+cyg_bool cyg_netarm_mii_check_duplex(void);
+cyg_bool cyg_netarm_mii_negotiate(void);
-#endif
+#endif // CYGONCE_DEVS_ETH_ARM_NETARM_MII_H
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 2005 eCosCentric LTD
+// Copyright (C) 2005 eCosCentric Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
+//
+//####ECOSGPLCOPYRIGHTEND####
// ====================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Harald Brandl (harald.brandl@fh-joanneum.at)
// Contributors: Harald Brandl
-// Date: 10.03.2005
-// Purpose: EEPROM I/O
+// Date: 10.03.2005
+// Purpose: EEPROM I/O
// Description:
//
//####DESCRIPTIONEND####
//
// ====================================================================
-#include <cyg/hal/hal_netarm.h>
-#include <sys/types.h>
+#include <cyg/hal/hal_modnet50.h>
+#include "eth_regs.h"
static void wait(int time)
{
- int i;
-
- for(i=0; i < time; i++);
+ int i;
+
+ for(i=0; i < time; i++);
}
+/* send i2c stop condition */
static void i2cStop(void)
{
- *PORTC |= 0x00c00000;
- *PORTC &= ~0x000000c0; // SDA = 0, SLK = 0
- wait(5);
- *PORTC |= 0x00000040; // SLK = 1
- wait(5);
- *PORTC |= 0x00000080; // SDA = 1
+ HAL_OR_UINT32(PORTC, 0x00c00000);
+ HAL_AND_UINT32(PORTC, ~0x000000c0); // SDA = 0, SLK = 0
+ wait(5);
+ HAL_OR_UINT32(PORTC, 0x00000040); // SLK = 1
+ wait(5);
+ HAL_OR_UINT32(PORTC, 0x00000080); // SDA = 1
}
+/* send i2c start condition */
static void i2cStart(void)
{
- *PORTC |= 0x00c000c0; // SDA = 1, SLK = 1
- wait(5);
- *PORTC &= ~0x00000080; // SDA = 0
- wait(5);
- *PORTC &= ~0x00000040; // SLK = 0
+ HAL_OR_UINT32(PORTC, 0x00c000c0); // SDA = 1, SLK = 1
+ wait(5);
+ HAL_AND_UINT32(PORTC, ~0x00000080); // SDA = 0
+ wait(5);
+ HAL_AND_UINT32(PORTC, ~0x00000040); // SLK = 0
}
static void i2cPutByte(char byte)
{
- int i, bit;
-
- *PORTC |= 0x00c00000;
-
- for(i=7; i >= 0; i--)
- {
- bit = (byte >> i) & 1;
- *PORTC = (*PORTC & ~0x80) | (bit << 7); // SDA = data
- *PORTC |= 0x00000040; // SLK = 1
- wait(5);
- *PORTC &= ~0x00000040; // SLK = 0
- wait(5);
- }
- *PORTC |= 0x00000080; // SDA = 1
+ int i, bit, reg;
+
+ HAL_OR_UINT32(PORTC, 0x00c00000);
+
+ for(i=7; i >= 0; i--)
+ {
+ bit = (byte >> i) & 1;
+ HAL_READ_UINT32(PORTC, reg);
+ HAL_WRITE_UINT32(PORTC, (reg & ~0x80) | (bit << 7)); // SDA = data
+ HAL_OR_UINT32(PORTC, 0x00000040); // SLK = 1
+ wait(5);
+ HAL_AND_UINT32(PORTC, ~0x00000040); // SLK = 0
+ wait(5);
+ }
+ HAL_OR_UINT32(PORTC, 0x00000080); // SDA = 1
}
static char i2cGetByte(void)
{
- int i;
- char byte = 0;
-
- *PORTC &= ~0x00800000;
- for(i=7; i >= 0; i--)
- {
- *PORTC |= 0x00000040; // SLK = 1
- byte |= ((*PORTC & 0x80) >> 7) << i; // data = SDA
- wait(5);
- *PORTC &= ~0x00000040; // SLK = 0
- wait(5);
- }
- *PORTC |= 0x00800080; // SDA = 1
- return byte;
+ int i, reg;
+ char byte = 0;
+
+ HAL_AND_UINT32(PORTC, ~0x00800000);
+ for(i=7; i >= 0; i--)
+ {
+ HAL_OR_UINT32(PORTC, 0x00000040); // SLK = 1
+ HAL_READ_UINT32(PORTC, reg);
+ byte |= ((reg & 0x80) >> 7) << i; // data = SDA
+ wait(5);
+ HAL_AND_UINT32(PORTC, ~0x00000040); // SLK = 0
+ wait(5);
+ }
+ HAL_OR_UINT32(PORTC, 0x00800080); // SDA = 1
+ return byte;
}
+/* acknowledge received bytes */
static void i2cGiveAck(void)
{
- *PORTC |= 0x00c00000;
- *PORTC &= ~0x00000080; // SDA = 0
- wait(5);
- *PORTC |= 0x00000040; // SLK = 1
- wait(5);
- *PORTC &= ~0x00000040; // SLK = 0
- wait(5);
- *PORTC |= 0x00000080; // SDA = 1
- wait(5);
+ HAL_OR_UINT32(PORTC, 0x00c00000);
+ HAL_AND_UINT32(PORTC, ~0x00000080); // SDA = 0
+ wait(5);
+ HAL_OR_UINT32(PORTC, 0x00000040); // SLK = 1
+ wait(5);
+ HAL_AND_UINT32(PORTC, ~0x00000040); // SLK = 0
+ wait(5);
+ HAL_OR_UINT32(PORTC, 0x00000080); // SDA = 1
+ wait(5);
}
+/* wait for acknowledge from slaves */
static void i2cGetAck(void)
{
- *PORTC &= ~0x00800000; // SDA in
- *PORTC |= 0x00400040; // SLK = 1
- while(*PORTC & 0x80); // wait for SDA = 1
- *PORTC &= ~0x00000040; // SLK = 0
+ unsigned reg;
+
+ HAL_AND_UINT32(PORTC, ~0x00800000); // SDA in
+ HAL_OR_UINT32(PORTC, 0x00400040); // SLK = 1
+ do
+ {
+ HAL_READ_UINT32(PORTC, reg);
+ }while(reg & 0x80); // wait for SDA = 1
+ HAL_AND_UINT32(PORTC, ~0x00000040); // SLK = 0
}
-void initI2C(void)
+void cyg_netarm_initI2C(void)
{
- *PORTC &= ~0xc0000000; // mode GPIO
- i2cStop();
+ HAL_AND_UINT32(PORTC, ~0xc0000000); // mode GPIO
+ i2cStop();
}
-void eepromPollAck(int deviceAddr)
+/* wait until eeprom's internal write cycle has finished */
+void cyg_netarm_eepromPollAck(int deviceAddr)
{
- deviceAddr <<= 1;
-
- *PORTC |= 0x00400040; // SLK = 1
- while(1)
- {
- i2cStart();
- i2cPutByte(deviceAddr);
- *PORTC &= ~0x00800000; // SDA in
- *PORTC |= 0x00400040; // SLK = 1
- if((*PORTC & 0x80) == 0)
- {
- *PORTC &= ~0x00000040; // SLK = 0
- break;
- }
- *PORTC &= ~0x00000040; // SLK = 0
- }
+ unsigned reg;
+
+ deviceAddr <<= 1;
+
+ HAL_OR_UINT32(PORTC, 0x00400040); // SLK = 1
+ while(1)
+ {
+ i2cStart();
+ i2cPutByte(deviceAddr);
+ HAL_AND_UINT32(PORTC, ~0x00800000); // SDA in
+ HAL_OR_UINT32(PORTC, 0x00400040); // SLK = 1
+ HAL_READ_UINT32(PORTC, reg);
+ if((reg & 0x80) == 0)
+ {
+ HAL_AND_UINT32(PORTC, ~0x00000040); // SLK = 0
+ break;
+ }
+ HAL_AND_UINT32(PORTC, ~0x00000040); // SLK = 0
+ }
}
-void eepromRead(int deviceAddr, int readAddr, char *buf, int numBytes)
+/* reads numBytes from eeprom starting at readAddr into buf */
+void cyg_netarm_eepromRead(int deviceAddr, int readAddr, char *buf, int numBytes)
{
- int i;
-
- deviceAddr <<= 1;
- i2cStart();
- i2cPutByte(deviceAddr);
- i2cGetAck();
- i2cPutByte(readAddr >> 8);
- i2cGetAck();
- i2cPutByte(readAddr & 0xff);
- i2cGetAck();
- i2cStart();
- i2cPutByte(deviceAddr | 1); // set read flag
- i2cGetAck();
-
- for(i=0;i<numBytes;i++)
- {
- buf[i] = i2cGetByte();
- if(i < numBytes - 1)
- i2cGiveAck();
- }
-
- i2cStop();
+ int i;
+
+ deviceAddr <<= 1;
+ i2cStart();
+ i2cPutByte(deviceAddr);
+ i2cGetAck();
+ i2cPutByte(readAddr >> 8);
+ i2cGetAck();
+ i2cPutByte(readAddr & 0xff);
+ i2cGetAck();
+ i2cStart();
+ i2cPutByte(deviceAddr | 1); // set read flag
+ i2cGetAck();
+
+ for(i=0;i<numBytes;i++)
+ {
+ buf[i] = i2cGetByte();
+ if(i < numBytes - 1)
+ i2cGiveAck();
+ }
+
+ i2cStop();
}
-void eepromWrite(int deviceAddr, int writeAddr, char *buf, int numBytes)
+/* writes up to a page of 32 bytes from buf into eeprom;
+max. number of bytes depends on the offset within a page, indexed by the
+lower 5 bits of writeAddr and equals 32 - offset */
+void cyg_netarm_eepromWrite(int deviceAddr, int writeAddr, char *buf, int numBytes)
{
- int i;
-
- deviceAddr <<= 1;
- i2cStart();
- i2cPutByte(deviceAddr);
- i2cGetAck();
- i2cPutByte(writeAddr >> 8);
- i2cGetAck();
- i2cPutByte(writeAddr & 0xff);
- i2cGetAck();
-
- for(i=0; i<numBytes; i++)
- {
- i2cPutByte(buf[i]);
- i2cGetAck();
- }
-
- i2cStop();
+ int i;
+
+ deviceAddr <<= 1;
+ i2cStart();
+ i2cPutByte(deviceAddr);
+ i2cGetAck();
+ i2cPutByte(writeAddr >> 8);
+ i2cGetAck();
+ i2cPutByte(writeAddr & 0xff);
+ i2cGetAck();
+
+ for(i=0; i<numBytes; i++)
+ {
+ i2cPutByte(buf[i]);
+ i2cGetAck();
+ }
+
+ i2cStop();
}
-#ifndef _NETARM_EEPROM__
-#define _NETARM_EEPROM__
+#ifndef CYGONCE_DEVS_ETH_ARM_NETARM_ETH_DR_EEPROM_H
+#define CYGONCE_DEVS_ETH_ARM_NETARM_ETH_DR_EEPROM_H
// ====================================================================
//
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 2005 eCosCentric LTD
+// Copyright (C) 2005 eCosCentric Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
+//
+//####ECOSGPLCOPYRIGHTEND####
// ====================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Harald Brandl (harald.brandl@fh-joanneum.at)
// Contributors: Harald Brandl
-// Date: 10.03.2005
-// Purpose: EEPROM interface
+// Date: 10.03.2005
+// Purpose: EEPROM interface
// Description:
//
//####DESCRIPTIONEND####
//
// ====================================================================
+
/* a block of max. 32 bytes can be written at once */
-void eepromWrite(int deviceAddr, int writeAddr, char *buf, int numBytes);
+void cyg_netarm_eepromWrite(int deviceAddr, int writeAddr, char *buf, int numBytes);
/* reads out as many bytes as desired */
-void eepromRead(int deviceAddr, int readAddr, char *buf, int numBytes);
-/* blocks until the internal write cycle, initiated after eepromWrite,
- completes */
-void eepromPollAck(int deviceAddr);
-void initI2C(void);
+void cyg_netarm_eepromRead(int deviceAddr, int readAddr, char *buf, int numBytes);
+/* blocks until the internal write cycle, initiated after eepromWrite, completes */
+void cyg_netarm_eepromPollAck(int deviceAddr);
+void cyg_netarm_initI2C(void);
-#endif
+#endif // CYGONCE_DEVS_ETH_ARM_NETARM_ETH_DR_EEPROM_H
-#ifndef _NETARM_ethregs_
-#define _NETARM_ethregs_
+#ifndef CYGONCE_DEVS_ETH_ARM_NETARM_ETH_REGS_H
+#define CYGONCE_DEVS_ETH_ARM_NETARM_ETH_REGS_H
+
// ====================================================================
//
// eth_regs.h
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 2005 eCosCentric LTD
+// Copyright (C) 2005 eCosCentric Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
+//
+//####ECOSGPLCOPYRIGHTEND####
// ====================================================================
//#####DESCRIPTIONBEGIN####
//
//
// ====================================================================
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_io.h>
+
+
+#ifndef HAL_OR_UINT32
+#define HAL_OR_UINT32( _register_, _value_ ) \
+ CYG_MACRO_START \
+ cyg_uint32 _i_; \
+ HAL_READ_UINT32( _register_, _i_ ); \
+ _i_ |= _value_; \
+ HAL_WRITE_UINT32( _register_, _i_ ); \
+ CYG_MACRO_END
+#endif
+
+#ifndef HAL_AND_UINT32
+#define HAL_AND_UINT32( _register_, _value_ ) \
+ CYG_MACRO_START \
+ cyg_uint32 _i_; \
+ HAL_READ_UINT32( _register_, _i_ ); \
+ _i_ &= _value_; \
+ HAL_WRITE_UINT32( _register_, _i_ ); \
+ CYG_MACRO_END
+#endif
+
// Ethernet
-#define EthGenCR *(volatile unsigned *)0xff800000
-#define EthGenSR *(volatile unsigned *)0xff800004
-#define EthFIFODR *(volatile unsigned *)0xff800008
-#define EthFIFODRkickoff *(volatile unsigned *)0xff80000c
-#define EthTxSR *(volatile unsigned *)0xff800010
-#define EthRxSR *(volatile unsigned *)0xff800014
-#define MACCR *(volatile unsigned *)0xff800400
-#define MACTR *(volatile unsigned *)0xff800404
-#define PCSCR *(volatile unsigned *)0xff800408
-#define PCSTR *(volatile unsigned *)0xff80040c
-#define STLCR *(volatile unsigned *)0xff800410
-#define STLTR *(volatile unsigned *)0xff800414
-#define BtBIPGGapTimerR *(volatile unsigned *)0xff800440
-#define NonBtBIPGGapTimerR *(volatile unsigned *)0xff800444
-#define CollWinR *(volatile unsigned *)0xff800448
-#define TxPNCR *(volatile unsigned *)0xff800460
-#define TxBCR *(volatile unsigned *)0xff800464
-#define ReTxBCR *(volatile unsigned *)0xff800468
-#define TxRNG *(volatile unsigned *)0xff80046c
-#define TxMRN *(volatile unsigned *)0xff800470
-#define TxCDec *(volatile unsigned *)0xff800474
-#define TOTxC *(volatile unsigned *)0xff800478
-#define RxBC *(volatile unsigned *)0xff800480
-#define RxCDec *(volatile unsigned *)0xff800484
-#define TORxC *(volatile unsigned *)0xff800488
-#define LnFC *(volatile unsigned *)0xff8004c0
-#define JC10M *(volatile unsigned *)0xff800500
-#define LoCC10M *(volatile unsigned *)0xff800504
-#define MIICR *(volatile unsigned *)0xff800540
-#define MIIAR *(volatile unsigned *)0xff800544
-#define MIIWDR *(volatile unsigned *)0xff800548
-#define MIIRDR *(volatile unsigned *)0xff80054c
-#define MIIIR *(volatile unsigned *)0xff800550
-#define CRCEC *(volatile unsigned *)0xff800580
-#define AEC *(volatile unsigned *)0xff800584
-#define CEC *(volatile unsigned *)0xff800588
-#define LFC *(volatile unsigned *)0xff80058c
-#define SFC *(volatile unsigned *)0xff800590
-#define LCC *(volatile unsigned *)0xff800594
-#define EDC *(volatile unsigned *)0xff800598
-#define MCC *(volatile unsigned *)0xff80059c
-#define SAFR *(volatile unsigned *)0xff8005c0
-#define SAR1 *(volatile unsigned *)0xff8005c4
-#define SAR2 *(volatile unsigned *)0xff8005c8
-#define SAR3 *(volatile unsigned *)0xff8005cc
-#define SAMHT1 *(volatile unsigned *)0xff8005d0
-#define SAMHT2 *(volatile unsigned *)0xff8005d4
-#define SAMHT3 *(volatile unsigned *)0xff8005d8
-#define SAMHT4 *(volatile unsigned *)0xff8005dc
+#define EthGenCR (unsigned *)0xff800000
+#define EthGenSR (unsigned *)0xff800004
+#define EthFIFODR (unsigned *)0xff800008
+#define EthFIFODRkickoff (unsigned *)0xff80000c
+#define EthTxSR (unsigned *)0xff800010
+#define EthRxSR (unsigned *)0xff800014
+#define MACCR (unsigned *)0xff800400
+#define MACTR (unsigned *)0xff800404
+#define PCSCR (unsigned *)0xff800408
+#define PCSTR (unsigned *)0xff80040c
+#define STLCR (unsigned *)0xff800410
+#define STLTR (unsigned *)0xff800414
+#define BtBIPGGapTimerR (unsigned *)0xff800440
+#define NonBtBIPGGapTimerR (unsigned *)0xff800444
+#define CollWinR (unsigned *)0xff800448
+#define TxPNCR (unsigned *)0xff800460
+#define TxBCR (unsigned *)0xff800464
+#define ReTxBCR (unsigned *)0xff800468
+#define TxRNG (unsigned *)0xff80046c
+#define TxMRN (unsigned *)0xff800470
+#define TxCDec (unsigned *)0xff800474
+#define TOTxC (unsigned *)0xff800478
+#define RxBC (unsigned *)0xff800480
+#define RxCDec (unsigned *)0xff800484
+#define TORxC (unsigned *)0xff800488
+#define LnFC (unsigned *)0xff8004c0
+#define JC10M (unsigned *)0xff800500
+#define LoCC10M (unsigned *)0xff800504
+#define MIICR (unsigned *)0xff800540
+#define MIIAR (unsigned *)0xff800544
+#define MIIWDR (unsigned *)0xff800548
+#define MIIRDR (unsigned *)0xff80054c
+#define MIIIR (unsigned *)0xff800550
+#define CRCEC (unsigned *)0xff800580
+#define AEC (unsigned *)0xff800584
+#define CEC (unsigned *)0xff800588
+#define LFC (unsigned *)0xff80058c
+#define SFC (unsigned *)0xff800590
+#define LCC (unsigned *)0xff800594
+#define EDC (unsigned *)0xff800598
+#define MCC (unsigned *)0xff80059c
+#define SAFR (unsigned *)0xff8005c0
+#define SAR1 (unsigned *)0xff8005c4
+#define SAR2 (unsigned *)0xff8005c8
+#define SAR3 (unsigned *)0xff8005cc
+#define SAMHT1 (unsigned *)0xff8005d0
+#define SAMHT2 (unsigned *)0xff8005d4
+#define SAMHT3 (unsigned *)0xff8005d8
+#define SAMHT4 (unsigned *)0xff8005dc
// DMA
-#define DMA1A_BDP *(volatile unsigned *)0xff900000
-#define DMA1A_CR *(volatile unsigned *)0xff900010
-#define DMA1A_SR *(volatile unsigned *)0xff900014
-#define DMA1B_BDP *(volatile unsigned *)0xff900020
-#define DMA1B_CR *(volatile unsigned *)0xff900030
-#define DMA1B_SR *(volatile unsigned *)0xff900034
-#define DMA1C_BDP *(volatile unsigned *)0xff900040
-#define DMA1C_CR *(volatile unsigned *)0xff900050
-#define DMA1C_SR *(volatile unsigned *)0xff900054
-#define DMA1D_BDP *(volatile unsigned *)0xff900060
-#define DMA1D_CR *(volatile unsigned *)0xff900070
-#define DMA1D_SR *(volatile unsigned *)0xff900074
-#define DMA2_BDP *(volatile unsigned *)0xff900080
-#define DMA2_CR *(volatile unsigned *)0xff900090
-#define DMA2_SR *(volatile unsigned *)0xff900094
+#define DMA1A_BDP (unsigned *)0xff900000
+#define DMA1A_CR (unsigned *)0xff900010
+#define DMA1A_SR (unsigned *)0xff900014
+#define DMA1B_BDP (unsigned *)0xff900020
+#define DMA1B_CR (unsigned *)0xff900030
+#define DMA1B_SR (unsigned *)0xff900034
+#define DMA1C_BDP (unsigned *)0xff900040
+#define DMA1C_CR (unsigned *)0xff900050
+#define DMA1C_SR (unsigned *)0xff900054
+#define DMA1D_BDP (unsigned *)0xff900060
+#define DMA1D_CR (unsigned *)0xff900070
+#define DMA1D_SR (unsigned *)0xff900074
+#define DMA2_BDP (unsigned *)0xff900080
+#define DMA2_CR (unsigned *)0xff900090
+#define DMA2_SR (unsigned *)0xff900094
-#endif
+#endif // CYGONCE_DEVS_ETH_ARM_NETARM_ETH_REGS_H
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
-// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 2005 eCosCentric LTD
+// This file is part of eCos, the Embedded Configurable Operating System
+// Copyright (C) 2005 eCosCentric Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
+//
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
#include <pkgconf/devs_eth_arm_netarm.h>
#include <cyg/hal/hal_platform_ints.h>
+#include <cyg/hal/plf_mmap.h>
#include "eth_regs.h"
#include "MII.h"
#include "netarm_eth_drv.h"
#include "eeprom.h"
-#include <cyg/hal/hal_io.h>
-
-// FIXME: The HAL should provide this
-#define CYGNUM_HAL_INTERRUPT_DMA2 31
-#define CYGNUM_HAL_INTERRUPT_DMA1 32
-
-// FIXME: The HAL should provide this and it should handle more than
-// RAM addresses
-#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr ) (unsigned char *)vaddr - 0x8000000
#define BufferSizeA 128
#define BufferSizeB 512
#define NumB 8
#define NumC 8
-#define EEPROM_MAC 0 // location of MAC address inside eeprom
+#define EEPROM_MAC 0 // location of MAC address inside eeprom
+
static cyg_mutex_t Key_Mutex;
static private_data_t driver_private;
-static volatile unsigned char RxBufferA[NumA][BufferSizeA];
-static volatile unsigned char RxBufferB[NumB][BufferSizeB];
-static volatile unsigned char RxBufferC[NumC][BufferSizeC];
+static unsigned char RxBufferA[NumA][BufferSizeA] __attribute__ ((aligned (4)));
+static unsigned char RxBufferB[NumB][BufferSizeB] __attribute__ ((aligned (4)));
+static unsigned char RxBufferC[NumC][BufferSizeC] __attribute__ ((aligned (4)));
-static volatile unsigned char TxBuffer[1500];
-static volatile unsigned char TxHeader[14];
+static unsigned char TxBuffer[1518] __attribute__ ((aligned (4)));
-static volatile BDP_t RxBDP_A[NumA];
-static volatile BDP_t RxBDP_B[NumB];
-static volatile BDP_t RxBDP_C[NumC];
+static BDP_t RxBDP_A[NumA];
+static BDP_t RxBDP_B[NumB];
+static BDP_t RxBDP_C[NumC];
-static volatile BDP_t TxBDP[2];
+static BDP_t TxBDP;
// relocation pointer for data accessed by DMA to enable caching
-static volatile unsigned char *pRxBufferA, *pRxBufferB, *pRxBufferC;
-static volatile unsigned char *pTxHeader, *pTxBuffer;
-static volatile BDP_t *pRxBDP_A, *pRxBDP_B, *pRxBDP_C;
-static volatile BDP_t *pTxBDP;
+static unsigned char *pRxBufferA = (unsigned char *)RxBufferA,
+ *pRxBufferB = (unsigned char *)RxBufferB,
+ *pRxBufferC = (unsigned char *)RxBufferC;
+static unsigned char *pTxBuffer = TxBuffer;
+
+static BDP_t *pRxBDP_A = RxBDP_A, *pRxBDP_B = RxBDP_B, *pRxBDP_C = RxBDP_C;
+static BDP_t *pTxBDP = &TxBDP;
+
ETH_DRV_SC(netarm_sc,
- (void *)&driver_private, // driver specific data
- "eth0", // Name for this interface
+ (void *)&driver_private, // driver specific data
+ "eth0", // name for this interface
netarm_start,
netarm_stop,
netarm_control,
netarm_poll,
netarm_int_vector);
+
NETDEVTAB_ENTRY(netarm_netdev,
"ETH_DRV",
netarm_init,
&netarm_sc);
+
+#ifdef __thumb__
+ #define fastcopy memcpy
+#else
static void
fastcopy(void *buf, void *data, unsigned long len)
{
- asm volatile(
-
- "STMDB SP!, {R11};"
-
- "TST R1, #2;" // test if aligned
- "LDRNEH R3, [R1], #2;"
- "STRNEH R3, [R0], #2;"
- "SUBNE R2, R2, #2;"
- "TST R1, #1;"
- "LDRNEB R3, [R1], #1;"
- "STRNEB R3, [R0], #1;"
- "SUBNE R2, R2, #1;"
-
- ".START:"
-
- "CMP R2, #44;"
- "BLT .LASTBYTES;"
- "LDMIA R1!, {R3 - R12, R14};"
- "STMIA R0!, {R3 - R12, R14};"
- "SUB R2, R2, #44;"
-
- "CMP R2, #44;"
- "BLT .LASTBYTES;"
- "LDMIA R1!, {R3 - R12, R14};"
- "STMIA R0!, {R3 - R12, R14};"
- "SUB R2, R2, #44;"
-
- "CMP R2, #44;"
- "BLT .LASTBYTES;"
- "LDMIA R1!, {R3 - R12, R14};"
- "STMIA R0!, {R3 - R12, R14};"
- "SUB R2, R2, #44;"
-
- "CMP R2, #44;"
- "BLT .LASTBYTES;"
- "LDMIA R1!, {R3 - R12, R14};"
- "STMIA R0!, {R3 - R12, R14};"
- "SUB R2, R2, #44;"
-
- "CMP R2, #44;"
- "BLT .LASTBYTES;"
- "LDMIA R1!, {R3 - R12, R14};"
- "STMIA R0!, {R3 - R12, R14};"
- "SUB R2, R2, #44;"
-
- "CMP R2, #44;"
- "BLT .LASTBYTES;"
- "LDMIA R1!, {R3 - R12, R14};"
- "STMIA R0!, {R3 - R12, R14};"
- "SUB R2, R2, #44;"
-
- "CMP R2, #44;"
- "BLT .LASTBYTES;"
- "LDMIA R1!, {R3 - R12, R14};"
- "STMIA R0!, {R3 - R12, R14};"
- "SUB R2, R2, #44;"
-
- "CMP R2, #44;"
- "BLT .LASTBYTES;"
- "LDMIA R1!, {R3 - R12, R14};"
- "STMIA R0!, {R3 - R12, R14};"
- "SUB R2, R2, #44;"
-
- "CMP R2, #44;"
- "BLT .LASTBYTES;"
- "LDMIA R1!, {R3 - R12, R14};"
- "STMIA R0!, {R3 - R12, R14};"
- "SUB R2, R2, #44;"
-
- "CMP R2, #44;"
- "BLT .LASTBYTES;"
- "LDMIA R1!, {R3 - R12, R14};"
- "STMIA R0!, {R3 - R12, R14};"
- "SUB R2, R2, #44;"
-
- "BGE .START;"
-
-
- ".LASTBYTES:"
-
- "AND R14, R2, #0xfffffffc;"
- "LDR PC, [PC, R14];"
- "NOP;"
-
- ".SWITCH:"
- ".word .CASE0;"
- ".word .CASE1;"
- ".word .CASE2;"
- ".word .CASE3;"
- ".word .CASE4;"
- ".word .CASE5;"
- ".word .CASE6;"
- ".word .CASE7;"
- ".word .CASE8;"
- ".word .CASE9;"
- ".word .CASE10;"
-
- ".CASE0:"
- "B .END;"
-
- ".CASE1:"
- "LDR R3, [R1]!;"
- "STR R3, [R0]!;"
- "B .END;"
-
- ".CASE2:"
- "LDMIA R1!, {R3, R4};"
- "STMIA R0!, {R3, R4};"
- "B .END;"
-
- ".CASE3:"
- "LDMIA R1!, {R3 - R5};"
- "STMIA R0!, {R3 - R5};"
- "B .END;"
-
- ".CASE4:"
- "LDMIA R1!, {R3 - R6};"
- "STMIA R0!, {R3 - R6};"
- "B .END;"
-
- ".CASE5:"
- "LDMIA R1!, {R3 - R7};"
- "STMIA R0!, {R3 - R7};"
- "B .END;"
-
- ".CASE6:"
- "LDMIA R1!, {R3 - R8};"
- "STMIA R0!, {R3 - R8};"
- "B .END;"
-
- ".CASE7:"
- "LDMIA R1!, {R3 - R9};"
- "STMIA R0!, {R3 - R9};"
- "B .END;"
-
- ".CASE8:"
- "LDMIA R1!, {R3 - R10};"
- "STMIA R0!, {R3 - R10};"
- "B .END;"
-
- ".CASE9:"
- "LDMIA R1!, {R3 - R11};"
- "STMIA R0!, {R3 - R11};"
- "B .END;"
-
- ".CASE10:"
- "LDMIA R1!, {R3 - R12};"
- "STMIA R0!, {R3 - R12};"
-
- ".END:"
- "TST R2, #2;"
- "LDRNEH R3, [R1], #2;"
- "STRNEH R3, [R0], #2;"
- "TST R2, #1;"
- "LDRNEB R3, [R1], #1;"
- "STRNEB R3, [R0], #1;"
-
- "LDMIA SP!, {R11};"
-
- :
- : "r" (buf), "r" (data), "r" (len)
- : "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r14"
- );
+ asm volatile(
+
+ "STMDB SP!, {R11};"
+
+ "TST R1, #2;" // test if aligned
+ "LDRNEH R3, [R1], #2;"
+ "STRNEH R3, [R0], #2;"
+ "SUBNE R2, R2, #2;"
+ "TST R1, #1;"
+ "LDRNEB R3, [R1], #1;"
+ "STRNEB R3, [R0], #1;"
+ "SUBNE R2, R2, #1;"
+
+ ".START%=:"
+
+ "CMP R2, #44;"
+ "BLT .LASTBYTES%=;"
+ "LDMIA R1!, {R3 - R12, R14};"
+ "STMIA R0!, {R3 - R12, R14};"
+ "SUB R2, R2, #44;"
+
+ "CMP R2, #44;"
+ "BLT .LASTBYTES%=;"
+ "LDMIA R1!, {R3 - R12, R14};"
+ "STMIA R0!, {R3 - R12, R14};"
+ "SUB R2, R2, #44;"
+
+ "CMP R2, #44;"
+ "BLT .LASTBYTES%=;"
+ "LDMIA R1!, {R3 - R12, R14};"
+ "STMIA R0!, {R3 - R12, R14};"
+ "SUB R2, R2, #44;"
+
+ "CMP R2, #44;"
+ "BLT .LASTBYTES%=;"
+ "LDMIA R1!, {R3 - R12, R14};"
+ "STMIA R0!, {R3 - R12, R14};"
+ "SUB R2, R2, #44;"
+
+ "CMP R2, #44;"
+ "BLT .LASTBYTES%=;"
+ "LDMIA R1!, {R3 - R12, R14};"
+ "STMIA R0!, {R3 - R12, R14};"
+ "SUB R2, R2, #44;"
+
+ "CMP R2, #44;"
+ "BLT .LASTBYTES%=;"
+ "LDMIA R1!, {R3 - R12, R14};"
+ "STMIA R0!, {R3 - R12, R14};"
+ "SUB R2, R2, #44;"
+
+ "CMP R2, #44;"
+ "BLT .LASTBYTES%=;"
+ "LDMIA R1!, {R3 - R12, R14};"
+ "STMIA R0!, {R3 - R12, R14};"
+ "SUB R2, R2, #44;"
+
+ "CMP R2, #44;"
+ "BLT .LASTBYTES%=;"
+ "LDMIA R1!, {R3 - R12, R14};"
+ "STMIA R0!, {R3 - R12, R14};"
+ "SUB R2, R2, #44;"
+
+ "CMP R2, #44;"
+ "BLT .LASTBYTES%=;"
+ "LDMIA R1!, {R3 - R12, R14};"
+ "STMIA R0!, {R3 - R12, R14};"
+ "SUB R2, R2, #44;"
+
+ "CMP R2, #44;"
+ "BLT .LASTBYTES%=;"
+ "LDMIA R1!, {R3 - R12, R14};"
+ "STMIA R0!, {R3 - R12, R14};"
+ "SUB R2, R2, #44;"
+
+ "BGE .START%=;"
+
+
+ ".LASTBYTES%=:"
+
+ "AND R14, R2, #0xfffffffc;"
+ "LDR PC, [PC, R14];"
+ "NOP;"
+
+ ".SWITCH%=:"
+ ".word .CASE0%=;"
+ ".word .CASE1%=;"
+ ".word .CASE2%=;"
+ ".word .CASE3%=;"
+ ".word .CASE4%=;"
+ ".word .CASE5%=;"
+ ".word .CASE6%=;"
+ ".word .CASE7%=;"
+ ".word .CASE8%=;"
+ ".word .CASE9%=;"
+ ".word .CASE10%=;"
+
+ ".CASE0%=:"
+ "B .END%=;"
+
+ ".CASE1%=:"
+ "LDMIA R1!, {R3};"
+ "STMIA R0!, {R3};"
+ "B .END%=;"
+
+ ".CASE2%=:"
+ "LDMIA R1!, {R3, R4};"
+ "STMIA R0!, {R3, R4};"
+ "B .END%=;"
+
+ ".CASE3%=:"
+ "LDMIA R1!, {R3 - R5};"
+ "STMIA R0!, {R3 - R5};"
+ "B .END%=;"
+
+ ".CASE4%=:"
+ "LDMIA R1!, {R3 - R6};"
+ "STMIA R0!, {R3 - R6};"
+ "B .END%=;"
+
+ ".CASE5%=:"
+ "LDMIA R1!, {R3 - R7};"
+ "STMIA R0!, {R3 - R7};"
+ "B .END%=;"
+
+ ".CASE6%=:"
+ "LDMIA R1!, {R3 - R8};"
+ "STMIA R0!, {R3 - R8};"
+ "B .END%=;"
+
+ ".CASE7%=:"
+ "LDMIA R1!, {R3 - R9};"
+ "STMIA R0!, {R3 - R9};"
+ "B .END%=;"
+
+ ".CASE8%=:"
+ "LDMIA R1!, {R3 - R10};"
+ "STMIA R0!, {R3 - R10};"
+ "B .END%=;"
+
+ ".CASE9%=:"
+ "LDMIA R1!, {R3 - R11};"
+ "STMIA R0!, {R3 - R11};"
+ "B .END%=;"
+
+ ".CASE10%=:"
+ "LDMIA R1!, {R3 - R12};"
+ "STMIA R0!, {R3 - R12};"
+
+ ".END%=:"
+ "TST R2, #2;"
+ "LDRNEH R3, [R1], #2;"
+ "STRNEH R3, [R0], #2;"
+ "TST R2, #1;"
+ "LDRNEB R3, [R1], #1;"
+ "STRNEB R3, [R0], #1;"
+
+ "LDMIA SP!, {R11};"
+
+ :
+ : "r" (buf), "r" (data), "r" (len)
+ : "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r14"
+ );
}
+#endif
static bool
KeyBufferFull(private_data_t *pd)
{
- int tmp = 0;
-
- cyg_drv_mutex_lock(&Key_Mutex);
-
- if((pd->key_head + 1) % MaxKeys == pd->key_tail)
- {
- tmp = 1;
- }
-
- cyg_drv_mutex_unlock(&Key_Mutex);
-
- return tmp;
+ int tmp = 0;
+
+ cyg_drv_mutex_lock(&Key_Mutex);
+
+ if((pd->key_head + 1) % MaxKeys == pd->key_tail)
+ {
+ tmp = 1;
+ }
+
+ cyg_drv_mutex_unlock(&Key_Mutex);
+
+ return tmp;
}
+
static void
AddKey(unsigned long key, private_data_t *pd)
{
-
- cyg_drv_mutex_lock(&Key_Mutex);
-
- pd->KeyBuffer[pd->key_head] = key;
- pd->key_head = (pd->key_head + 1) % MaxKeys;
-
- cyg_drv_mutex_unlock(&Key_Mutex);
+
+ cyg_drv_mutex_lock(&Key_Mutex);
+
+ pd->KeyBuffer[pd->key_head] = key;
+ pd->key_head = (pd->key_head + 1) % MaxKeys;
+
+ cyg_drv_mutex_unlock(&Key_Mutex);
}
static unsigned
GetKey(private_data_t *pd)
{
- unsigned key = 0;
-
- cyg_drv_mutex_lock(&Key_Mutex);
-
- if(pd->key_tail != pd->key_head)
- {
- key = pd->KeyBuffer[pd->key_tail];
- pd->key_tail = (pd->key_tail + 1) % MaxKeys;
- }
-
- cyg_drv_mutex_unlock(&Key_Mutex);
-
- return key;
+ unsigned key = 0;
+
+ cyg_drv_mutex_lock(&Key_Mutex);
+
+ if(pd->key_tail != pd->key_head)
+ {
+ key = pd->KeyBuffer[pd->key_tail];
+ pd->key_tail = (pd->key_tail + 1) % MaxKeys;
+ }
+
+ cyg_drv_mutex_unlock(&Key_Mutex);
+
+ return key;
}
+
static cyg_uint32
dma_rx_isr(cyg_vector_t vector, cyg_addrword_t data)
{
-
- // block this interrupt until the dsr completes
- cyg_drv_interrupt_mask(vector);
-
- // tell ecos to allow further interrupt processing
- cyg_drv_interrupt_acknowledge(vector);
-
- return CYG_ISR_CALL_DSR; // call the dsr
+
+ // block this interrupt until the dsr completes
+ cyg_drv_interrupt_mask(vector);
+
+ // tell ecos to allow further interrupt processing
+ cyg_drv_interrupt_acknowledge(vector);
+
+ return CYG_ISR_CALL_DSR; // call the dsr
}
static void
dma_rx_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
-
- eth_drv_dsr( vector, count, data );
-
- DMA1A_SR = 0x80000000; // acknowledge and mask interrupts
- DMA1B_SR = 0x80000000;
- DMA1C_SR = 0x80000000;
-
- cyg_drv_interrupt_unmask(vector);
+
+ eth_drv_dsr( vector, count, data );
+
+ HAL_WRITE_UINT32(DMA1A_SR, 0x80000000); // acknowledge and mask interrupts
+ HAL_WRITE_UINT32(DMA1B_SR, 0x80000000);
+ HAL_WRITE_UINT32(DMA1C_SR, 0x80000000);
+
+ cyg_drv_interrupt_unmask(vector);
}
static cyg_uint32
dma_tx_isr(cyg_vector_t vector, cyg_addrword_t data)
{
-
- // block this interrupt until the dsr completes
- cyg_drv_interrupt_mask(vector);
-
- // tell ecos to allow further interrupt processing
- cyg_drv_interrupt_acknowledge(vector);
-
- return CYG_ISR_CALL_DSR; // invoke the dsr
+
+ // block this interrupt until the dsr completes
+ cyg_drv_interrupt_mask(vector);
+
+ // tell ecos to allow further interrupt processing
+ cyg_drv_interrupt_acknowledge(vector);
+
+ return CYG_ISR_CALL_DSR; // invoke the dsr
}
static void
dma_tx_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
-
- eth_drv_dsr( vector, count, data );
-
- DMA2_SR |= 0x80000000; // acknowledge interrupt
-
- cyg_drv_interrupt_unmask(vector);
+
+ eth_drv_dsr( vector, count, data );
+
+ HAL_OR_UINT32(DMA2_SR, 0x80000000); // acknowledge interrupt
+
+ cyg_drv_interrupt_unmask(vector);
}
static void
-SetupDMA(void)
+setupDMA(void)
{
- int i;
-
- pRxBufferA = (unsigned char *)HAL_VIRT_TO_PHYS_ADDRESS(RxBufferA);
- pRxBufferB = (unsigned char *)HAL_VIRT_TO_PHYS_ADDRESS(RxBufferB);
- pRxBufferC = (unsigned char *)HAL_VIRT_TO_PHYS_ADDRESS(RxBufferC);
-
- pTxBuffer = (unsigned char *)HAL_VIRT_TO_PHYS_ADDRESS(TxBuffer);
- pTxHeader = (unsigned char *)HAL_VIRT_TO_PHYS_ADDRESS(TxHeader);
-
- pRxBDP_A = (BDP_t *)HAL_VIRT_TO_PHYS_ADDRESS(RxBDP_A);
- pRxBDP_B = (BDP_t *)HAL_VIRT_TO_PHYS_ADDRESS(RxBDP_B);
- pRxBDP_C = (BDP_t *)HAL_VIRT_TO_PHYS_ADDRESS(RxBDP_C);
-
- pTxBDP = (BDP_t *)((unsigned char *)TxBDP);
-
- *SYSCON |= 0x40; // reset DMA module
-
- for(i = 0; i < NumA; i++)
- {
- pRxBDP_A[i].lo = ((unsigned)(pRxBufferA+i*BufferSizeA)) & 0x3fffffff;
- pRxBDP_A[i].hi = BufferSizeA;
- }
-
- pRxBDP_A[i - 1].lo |= 0x80000000; // set W bit
-
- for(i = 0; i < NumB; i++)
- {
- pRxBDP_B[i].lo = ((unsigned)(pRxBufferB+i*BufferSizeB)) & 0x3fffffff;
- pRxBDP_B[i].hi = BufferSizeB;
- }
-
- pRxBDP_B[i - 1].lo |= 0x80000000;
-
- for(i = 0; i < NumC; i++)
- {
- pRxBDP_C[i].lo = ((unsigned)(pRxBufferC+i*BufferSizeC)) & 0x3fffffff;
- pRxBDP_C[i].hi = BufferSizeC;
- }
-
- pRxBDP_C[i - 1].lo |= 0x80000000;
-
- *SYSCON &= ~0x40;
-
- DMA1A_BDP = (unsigned)pRxBDP_A;
- DMA1A_CR = 0x82000000; //burst transfer
- DMA1A_SR = 0xa00000;
-
- DMA1B_BDP = (unsigned)pRxBDP_B;
- DMA1B_CR = 0x82000000; //burst transfer
- DMA1B_SR = 0xa00000;
-
- DMA1C_BDP = (unsigned)pRxBDP_C;
- DMA1C_CR = 0x82000000; //burst transfer
- DMA1C_SR = 0xa00000;
-
-
- pTxBDP[0].lo = ((unsigned)pTxHeader) & 0x3fffffff;
- pTxBDP[1].lo = ((unsigned)pTxBuffer) & 0x3fffffff;
- pTxBDP[1].lo |= 0xa0000000; // set W and L bit
-
- DMA2_BDP = (unsigned)pTxBDP;
- DMA2_CR = 0x86000000; //burst transfer
- DMA2_SR = 0x800000;
-
+ int i;
+
+ /* map DMA shared data to non-cached ram */
+#ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
+ HAL_CACHED_TO_UNCACHED_ADDRESS(RxBufferA, pRxBufferA, unsigned char *);
+ HAL_CACHED_TO_UNCACHED_ADDRESS(RxBufferB, pRxBufferB, unsigned char *);
+ HAL_CACHED_TO_UNCACHED_ADDRESS(RxBufferC, pRxBufferC, unsigned char *);
+
+ HAL_CACHED_TO_UNCACHED_ADDRESS(TxBuffer, pTxBuffer, unsigned char *);
+
+ HAL_CACHED_TO_UNCACHED_ADDRESS(RxBDP_A, pRxBDP_A, BDP_t *);
+ HAL_CACHED_TO_UNCACHED_ADDRESS(RxBDP_B, pRxBDP_B, BDP_t *);
+ HAL_CACHED_TO_UNCACHED_ADDRESS(RxBDP_C, pRxBDP_C, BDP_t *);
+
+ HAL_CACHED_TO_UNCACHED_ADDRESS(TxBDP, pTxBDP, BDP_t * );
+#endif
+
+ HAL_OR_UINT32(SYSCON, 0x40); // reset DMA module
+
+ for(i = 0; i < NumA; i++)
+ {
+ pRxBDP_A[i].lo = ((unsigned)(pRxBufferA + i*BufferSizeA)) & 0x3fffffff;
+ pRxBDP_A[i].hi = BufferSizeA;
+ }
+
+ pRxBDP_A[i - 1].lo |= 0x80000000; // set W bit
+
+ for(i = 0; i < NumB; i++)
+ {
+ pRxBDP_B[i].lo = ((unsigned)(pRxBufferB + i*BufferSizeB)) & 0x3fffffff;
+ pRxBDP_B[i].hi = BufferSizeB;
+ }
+
+ pRxBDP_B[i - 1].lo |= 0x80000000;
+
+ for(i = 0; i < NumC; i++)
+ {
+ pRxBDP_C[i].lo = ((unsigned)(pRxBufferC + i*BufferSizeC)) & 0x3fffffff;
+ pRxBDP_C[i].hi = BufferSizeC;
+ }
+
+ pRxBDP_C[i - 1].lo |= 0x80000000;
+
+ HAL_AND_UINT32(SYSCON, ~0x40);
+
+ HAL_WRITE_UINT32(DMA1A_BDP, (unsigned)pRxBDP_A);
+ HAL_WRITE_UINT32(DMA1A_CR, 0x82000000); //burst transfer
+ HAL_WRITE_UINT32(DMA1A_SR, 0xa00000);
+
+ HAL_WRITE_UINT32(DMA1B_BDP, (unsigned)pRxBDP_B);
+ HAL_WRITE_UINT32(DMA1B_CR, 0x82000000); //burst transfer
+ HAL_WRITE_UINT32(DMA1B_SR, 0xa00000);
+
+ HAL_WRITE_UINT32(DMA1C_BDP, (unsigned)pRxBDP_C);
+ HAL_WRITE_UINT32(DMA1C_CR, 0x82000000); //burst transfer
+ HAL_WRITE_UINT32(DMA1C_SR, 0xa00000);
+
+
+ pTxBDP->lo = ((unsigned)pTxBuffer) & 0x3fffffff;
+ pTxBDP->lo |= 0xa0000000; // set W and L bit
+
+ HAL_WRITE_UINT32(DMA2_BDP, (unsigned)pTxBDP);
+ HAL_WRITE_UINT32(DMA2_CR, 0x86000000); //burst transfer
+ HAL_WRITE_UINT32(DMA2_SR, 0x800000);
}
+
static bool
netarm_init(struct cyg_netdevtab_entry *tab)
{
- struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
- cyg_bool duplex;
- static cyg_interrupt dma_rx_int_object, dma_tx_int_object;
- static cyg_handle_t dma_rx_int_handle, dma_tx_int_handle;
-
+ struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
+ cyg_bool duplex;
+ static cyg_interrupt dma_rx_int_object, dma_tx_int_object;
+ static cyg_handle_t dma_rx_int_handle, dma_tx_int_handle;
+
#ifdef CYGSEM_DEVS_ETH_ARM_NETARM_ETH0_SET_ESA
-
- unsigned char esa[6] = CYGDAT_DEVS_ETH_ARM_NETARM_ETH0_ESA;
+
+ unsigned char esa[6] = CYGDAT_DEVS_ETH_ARM_NETARM_ETH0_ESA;
#else
- unsigned char esa[6];
-
- initI2C();
- eepromRead(0x50, EEPROM_MAC, esa, 6);
+ unsigned char esa[6];
+
+ cyg_netarm_initI2C();
+ cyg_netarm_eepromRead(0x50, EEPROM_MAC, esa, 6);
#endif
-
- // setup dma receiver
- SetupDMA();
-
- mii_reset();
- mii_negotiate(); // initialize PHY
- duplex = mii_check_duplex();
-
- // Ethernet Controller Initializatition
-
- MACCR = (0x1c | (duplex << 1)); // auto CRC, late collision retry
- STLCR = 0x3; // insert MAC source address
- // into ethernet frame
- BtBIPGGapTimerR = 0x14; // standard values
- NonBtBIPGGapTimerR = ((0x9 << 7) | 0x11); // standard values
- CollWinR = ((0x37 << 8) | 0xf); // standard values
- SAFR = 0x1; // broadcast mode
- EthGenCR = (0x40400400 | (duplex << 16)); // dma mode, full duplex,
- // enable pNA mode(needed
- // for alignment)
-
- cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_DMA1, // Interrupt Vector
- 0, // Interrupt Priority
- (cyg_addrword_t)&netarm_sc, // Reference
- // to Driver
- // Instance
- dma_rx_isr,
- dma_rx_dsr,
- &dma_rx_int_handle,
- &dma_rx_int_object);
-
- cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_DMA2, // Interrupt Vector
- 0, // Interrupt Priority
- (cyg_addrword_t)&netarm_sc, // Reference
- // to Driver
- // Instance
- dma_tx_isr,
- dma_tx_dsr,
- &dma_tx_int_handle,
- &dma_tx_int_object);
-
- cyg_drv_interrupt_attach(dma_rx_int_handle);
- cyg_drv_interrupt_attach(dma_tx_int_handle);
-
- cyg_mutex_init(&Key_Mutex);
-
- sc->funs->eth_drv->init(sc, esa);
-
- return true;
+
+ // setup dma receiver
+ setupDMA();
+
+ cyg_netarm_mii_reset();
+ cyg_netarm_mii_negotiate(); // initialize PHY
+ duplex = cyg_netarm_mii_check_duplex();
+
+ // Ethernet Controller Initializatition
+
+ // auto CRC, late collision retry
+ HAL_WRITE_UINT32(MACCR, 0x1c | (duplex << 1));
+ // insert MAC source address into ethernet frame
+ HAL_WRITE_UINT32(STLCR, 0x3);
+ HAL_WRITE_UINT32(BtBIPGGapTimerR, 0x14); // standard values
+ HAL_WRITE_UINT32(NonBtBIPGGapTimerR, (0x9 << 7) | 0x11);// standard values
+ HAL_WRITE_UINT32(CollWinR, (0x37 << 8) | 0xf); // standard values
+ HAL_WRITE_UINT32(SAFR, 0x1); // broadcast mode
+ // dma mode, full duplex, enable pNA mode(needed for alignment)
+ HAL_WRITE_UINT32(EthGenCR, 0x40400400 | (duplex << 16));
+
+ cyg_drv_interrupt_create(
+ CYGNUM_HAL_INTERRUPT_DMA1, // Interrupt Vector
+ 0, // Interrupt Priority
+ (cyg_addrword_t)&netarm_sc, // Reference to Driver Instance
+ dma_rx_isr,
+ dma_rx_dsr,
+ &dma_rx_int_handle,
+ &dma_rx_int_object);
+
+ cyg_drv_interrupt_create(
+ CYGNUM_HAL_INTERRUPT_DMA2, // Interrupt Vector
+ 0, // Interrupt Priority
+ (cyg_addrword_t)&netarm_sc, // Reference to Driver Instance
+ dma_tx_isr,
+ dma_tx_dsr,
+ &dma_tx_int_handle,
+ &dma_tx_int_object);
+
+ cyg_drv_interrupt_attach(dma_rx_int_handle);
+
+ cyg_drv_interrupt_attach(dma_tx_int_handle);
+
+ cyg_mutex_init(&Key_Mutex);
+
+ sc->funs->eth_drv->init(sc, esa);
+
+ return true;
}
+
static void
netarm_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len)
{
- int i, len;
- private_data_t *pd = (private_data_t *)(sc->driver_private);
- unsigned char *data, *buf = pd->RxBuffer;
-
- for (i = 0; i < sg_len; i++) {
- data = (unsigned char *)(sg_list[i].buf);
- len = sg_list[i].len;
- if (len)
- {
- if(i == 1)
- {
- buf += 2;
- }
-
- fastcopy(data, buf, len);
- buf += len;
- }
- }
+ int i, len;
+ private_data_t *pd = (private_data_t *)(sc->driver_private);
+ unsigned char *data, *buf = pd->RxBuffer;
+
+ for (i = 0; i < sg_len; i++) {
+ data = (unsigned char *)(sg_list[i].buf);
+ len = sg_list[i].len;
+ if(len)
+ {
+ if(i == 1)
+ {
+ buf += 2;
+ }
+
+ fastcopy(data, buf, len);
+ buf += len;
+ }
+ }
}
+
static void
netarm_deliver(struct eth_drv_sc *sc)
{
- static int a = 0, b = 0, c = 0;
- unsigned long key;
- private_data_t *pd = (private_data_t *)(sc->driver_private);
-
- while((key = GetKey(pd)))
- {
- sc->funs->eth_drv->tx_done(sc, key, 0);
- }
-
- while(pRxBDP_A[a].hi & 0x8000)
- {
- pd->RxBuffer = (unsigned char *)(pRxBDP_A[a].lo & 0x1FFFFFFF);
- HAL_REORDER_BARRIER();
- sc->funs->eth_drv->recv(sc, pRxBDP_A[a].hi & 0x7FFF);
- HAL_REORDER_BARRIER();
- pRxBDP_A[a].hi = BufferSizeA;
- HAL_REORDER_BARRIER();
- a = (a + 1) % NumA;
- }
-
- while(pRxBDP_B[b].hi & 0x8000)
- {
- pd->RxBuffer = (unsigned char *)(pRxBDP_B[b].lo & 0x1FFFFFFF);
- HAL_REORDER_BARRIER();
- sc->funs->eth_drv->recv(sc, pRxBDP_B[b].hi & 0x7FFF);
- HAL_REORDER_BARRIER();
- pRxBDP_B[b].hi = BufferSizeB;
- HAL_REORDER_BARRIER();
- b = (b + 1) % NumB;
- }
-
- while(pRxBDP_C[c].hi & 0x8000)
- {
- pd->RxBuffer = (unsigned char *)(pRxBDP_C[c].lo & 0x1FFFFFFF);
- HAL_REORDER_BARRIER();
- sc->funs->eth_drv->recv(sc, pRxBDP_C[c].hi & 0x7FFF);
- HAL_REORDER_BARRIER();
- pRxBDP_C[c].hi = BufferSizeC;
- HAL_REORDER_BARRIER();
- c = (c + 1) % NumC;
- }
-
- if((DMA1A_SR & 0x20000000) || (DMA1B_SR & 0x20000000) || (DMA1C_SR & 0x20000000))
- {
- EthGenCR &= ~0xc0000000; // reset Rx FIFO
- EthGenCR |= 0xc0000000;
- }
-
- DMA1A_SR = 0x20a00000;
- DMA1B_SR = 0x20a00000;
- DMA1C_SR = 0x20a00000;
+ static int a = 0, b = 0, c = 0;
+ unsigned key, rega, regb, regc;
+ private_data_t *pd = (private_data_t *)(sc->driver_private);
+
+
+ while((key = GetKey(pd)))
+ {
+ sc->funs->eth_drv->tx_done(sc, key, 0);
+ }
+
+ while(pRxBDP_A[a].hi & 0x8000)
+ {
+ pd->RxBuffer = (unsigned char *)(pRxBDP_A[a].lo & 0x1FFFFFFF);
+ HAL_REORDER_BARRIER();
+ sc->funs->eth_drv->recv(sc, pRxBDP_A[a].hi & 0x7FFF);
+ HAL_REORDER_BARRIER();
+ pRxBDP_A[a].hi = BufferSizeA;
+ HAL_REORDER_BARRIER();
+ a = (a + 1) % NumA;
+ }
+
+ while(pRxBDP_B[b].hi & 0x8000)
+ {
+ pd->RxBuffer = (unsigned char *)(pRxBDP_B[b].lo & 0x1FFFFFFF);
+ HAL_REORDER_BARRIER();
+ sc->funs->eth_drv->recv(sc, pRxBDP_B[b].hi & 0x7FFF);
+ HAL_REORDER_BARRIER();
+ pRxBDP_B[b].hi = BufferSizeB;
+ HAL_REORDER_BARRIER();
+ b = (b + 1) % NumB;
+ }
+
+ while(pRxBDP_C[c].hi & 0x8000)
+ {
+ pd->RxBuffer = (unsigned char *)(pRxBDP_C[c].lo & 0x1FFFFFFF);
+ HAL_REORDER_BARRIER();
+ sc->funs->eth_drv->recv(sc, pRxBDP_C[c].hi & 0x7FFF);
+ HAL_REORDER_BARRIER();
+ pRxBDP_C[c].hi = BufferSizeC;
+ HAL_REORDER_BARRIER();
+ c = (c + 1) % NumC;
+ }
+
+ HAL_READ_UINT32(DMA1A_SR, rega);
+ HAL_READ_UINT32(DMA1B_SR, regb);
+ HAL_READ_UINT32(DMA1C_SR, regc);
+
+ if((rega & 0x20000000) || (regb & 0x20000000) || (regc & 0x20000000))
+ {
+ HAL_AND_UINT32(EthGenCR, ~0xc0000000); // reset Rx FIFO
+ HAL_OR_UINT32(EthGenCR, 0xc0000000);
+ }
+
+ HAL_WRITE_UINT32(DMA1A_SR, 0x20a00000);
+ HAL_WRITE_UINT32(DMA1B_SR, 0x20a00000);
+ HAL_WRITE_UINT32(DMA1C_SR, 0x20a00000);
}
+
static int
netarm_can_send(struct eth_drv_sc *sc)
{
- private_data_t *pd = (private_data_t *)(sc->driver_private);
-
- if((pTxBDP[0].hi & 0x8000) || (pTxBDP[1].hi & 0x8000) || KeyBufferFull(pd))
- return 0;
-
- return 1;
+ private_data_t *pd = (private_data_t *)(sc->driver_private);
+
+ if((pTxBDP->hi & 0x8000) || KeyBufferFull(pd))
+ return 0;
+
+ return 1;
}
static void
netarm_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list,
- int sg_len, int total_len, unsigned long key)
+ int sg_len, int total_len, unsigned long key)
{
- private_data_t *pd = (private_data_t *)(sc->driver_private);
- int i, len;
- unsigned char *data;
- volatile char *buf = pTxBuffer;
-
- AddKey(key, pd);
-
- // Put data into buffer
- for (i = 0; i < sg_len; i++) {
- data = (unsigned char *)sg_list[i].buf;
- len = sg_list[i].len;
-
- if(i == 0)
- {
- if((unsigned long)data & 0x3)
- {
- memcpy((unsigned char*)pTxHeader, data, 0xe);
- }
- else
- {
- fastcopy((unsigned char *)pTxHeader, data, 0xe);
- }
-
- len -= 0xe;
- data += 0xe;
- }
-
- if (len)
- {
- fastcopy((unsigned char *)buf, data, len);
- buf += len;
- }
- }
-
- cyg_drv_dsr_lock();
- pTxBDP[0].hi = 0x800e;
- HAL_REORDER_BARRIER();
- pTxBDP[1].hi = (total_len - 0xe) | 0x8000;
- HAL_REORDER_BARRIER();
- DMA2_SR |= 0xf0000000;
- cyg_drv_dsr_unlock();
+ private_data_t *pd = (private_data_t *)(sc->driver_private);
+ int i, len;
+ unsigned char *data, *buf = pTxBuffer;
+
+ AddKey(key, pd);
+
+ // Put data into buffer
+ for(i = 0; i < sg_len; i++) {
+ data = (unsigned char *)sg_list[i].buf;
+ len = sg_list[i].len;
+
+ if(len)
+ {
+ if(((unsigned)buf & 0x3) != ((unsigned)data & 0x3))
+ {
+ memcpy(buf, data, len);
+ }
+ else
+ {
+ fastcopy(buf, data, len);
+ }
+
+ buf += len;
+ }
+ }
+
+cyg_drv_dsr_lock();
+ pTxBDP->hi = total_len | 0x8000;
+HAL_REORDER_BARRIER();
+ HAL_OR_UINT32(DMA2_SR, 0xf0000000);
+cyg_drv_dsr_unlock();
}
+
static void
netarm_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags)
{
- SetMAC(enaddr); // set MAC address
- HAL_REORDER_BARRIER();
- EthGenCR |= 0x80800000; // enable Rx und Tx FIFO
- HAL_REORDER_BARRIER();
- cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_DMA1);
- cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_DMA2);
+ setMAC(enaddr); // set MAC address
+HAL_REORDER_BARRIER();
+ HAL_OR_UINT32(EthGenCR, 0x80800000); // enable Rx und Tx FIFO
+HAL_REORDER_BARRIER();
+ cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_DMA1);
+ cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_DMA2);
}
static void
netarm_stop(struct eth_drv_sc *sc)
{
- EthGenCR &= 0x7f7fffff;
- HAL_REORDER_BARRIER();
- cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_DMA1);
- cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_DMA2);
+ HAL_AND_UINT32(EthGenCR, 0x7f7fffff);
+HAL_REORDER_BARRIER();
+ cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_DMA1);
+ cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_DMA2);
}
static int
netarm_control(struct eth_drv_sc *sc, unsigned long key, void *data, int len)
{
- switch (key)
- {
- case ETH_DRV_SET_MAC_ADDRESS:
- return 0;
- break;
- case ETH_DRV_SET_MC_LIST:
- case ETH_DRV_SET_MC_ALL:
- return 0;
- default:
- return 1;
- break;
- }
+ return -1;
}
static void
static int
netarm_int_vector(struct eth_drv_sc *sc)
{
- return CYGNUM_HAL_INTERRUPT_DMA1;
+ return CYGNUM_HAL_INTERRUPT_DMA1;
}
static void
-SetMAC(unsigned char *esa)
+setMAC(unsigned char *esa)
{
- SAR1 = (esa[1] << 8) | esa[0]; // set MAC address
- SAR2 = (esa[3] << 8) | esa[2];
- SAR3 = (esa[5] << 8) | esa[4];
+ HAL_WRITE_UINT32(SAR1, (esa[1] << 8) | esa[0]); // set MAC address
+ HAL_WRITE_UINT32(SAR2, (esa[3] << 8) | esa[2]);
+ HAL_WRITE_UINT32(SAR3, (esa[5] << 8) | esa[4]);
}
-#ifndef NETARM_ETH_DRV_H
-#define NETARM_ETH_DRV_H
+#ifndef CYGONCE_DEVS_ETH_ARM_NETARM_ETH_DR_H
+#define CYGONCE_DEVS_ETH_ARM_NETARM_ETH_DR_H
-//====================================================================
+// ====================================================================
//
// netarm_eth_drv.h
//
// Device I/O - Description of NET+ARM ethernet hardware functions
-// and data structures
+// and data structures
//
// ====================================================================
+
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 2005 eCosCentric LTD
+// Copyright (C) 2005 eCosCentric Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
+//
+//####ECOSGPLCOPYRIGHTEND####
// ====================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Harald Brandl (harald.brandl@fh-joanneum.at)
// Contributors: Harald Brandl
-// Date: 01.08.2004
-// Purpose: Internal interfaces and data structures
+// Date: 01.08.2004
+// Purpose: Internal interfaces and data structures
// Description:
//
//####DESCRIPTIONEND####
typedef struct
{
- unsigned char *RxBuffer;
- unsigned short key_head, key_tail;
- unsigned KeyBuffer[MaxKeys];
+ unsigned char *RxBuffer;
+ unsigned short key_head, key_tail;
+ unsigned KeyBuffer[MaxKeys];
}private_data_t;
typedef struct
{
- unsigned lo;
- unsigned hi;
+ unsigned lo;
+ unsigned hi;
}BDP_t;
static bool netarm_init(struct cyg_netdevtab_entry *tab);
-static void netarm_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list,
- int sg_len);
+static void netarm_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len);
static void netarm_deliver(struct eth_drv_sc *sc);
-static int netarm_can_send(struct eth_drv_sc *sc);
-static void netarm_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list,
- int sg_len, int total_len, unsigned long key);
+static int netarm_can_send(struct eth_drv_sc *sc);
+static void netarm_send(
+ struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len, int total_len, unsigned long key);
static void netarm_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags);
static void netarm_stop(struct eth_drv_sc *sc);
-static int netarm_control(struct eth_drv_sc *sc, unsigned long key, void *data,
- int len);
+static int netarm_control(struct eth_drv_sc *sc, unsigned long key, void *data, int len);
static void netarm_poll(struct eth_drv_sc *sc);
-static int netarm_int_vector(struct eth_drv_sc *sc);
-
-static void SetMAC(unsigned char *esa);
+static int netarm_int_vector(struct eth_drv_sc *sc);
-#endif //NETARM__ETH_DRV_H
+static void setMAC(unsigned char *esa);
+#endif // CYGONCE_DEVS_ETH_ARM_NETARM_ETH_DR_H
--- /dev/null
+# ====================================================================
+#
+# tx25_eth_drivers.cdl
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+
+cdl_package CYGPKG_DEVS_ETH_ARM_TX25 {
+ display "Ethernet driver for Ka-Ro electronics TX25 processor module"
+
+ parent CYGPKG_IO_ETH_DRIVERS
+ active_if CYGPKG_IO_ETH_DRIVERS
+
+ include_dir cyg/io
+
+ cdl_interface CYGINT_DEVS_ETH_FEC_REQUIRED {
+ display "FEC ethernet driver required"
+ }
+
+ cdl_component CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0 {
+ display "Ka-Ro TX25 ethernet port driver"
+ flavor bool
+ default_value 1
+ description "
+ This option includes the ethernet device driver for the
+ MXC Board port."
+
+ implements CYGHWR_NET_DRIVER_ETH0
+ implements CYGINT_DEVS_ETH_FEC_REQUIRED
+ requires CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ requires CYGHWR_DEVS_ETH_PHY_LAN8700
+
+ cdl_option CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME {
+ display "Device name for the ETH0 ethernet driver"
+ flavor data
+ default_value {"\"eth0\""}
+ description "
+ This option sets the name of the ethernet device."
+ }
+
+ cdl_option CYGDAT_DEVS_ETH_ARM_TX25KARO_OUI {
+ display "OUI part of MAC address"
+ flavor data
+ active_if CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ default_value { "{ 0x00, 0x0c, 0xc6 }" }
+ description "
+ This option sets OUI part (manufacturer ID) of the MAC address
+ for validation."
+ }
+ }
+
+ define_proc {
+ puts $::cdl_system_header "/***** ethernet driver proc output start *****/"
+ puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_FEC_CFG <pkgconf/devs_eth_arm_tx25.h>"
+ puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_FEC_INL <cyg/io/devs_eth_arm_tx25.inl>"
+ puts $::cdl_system_header "/***** ethernet driver proc output end *****/"
+ }
+}
--- /dev/null
+//==========================================================================
+//
+// devs_eth_arm_tx25.inl
+//
+// Board ethernet I/O definitions.
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_intr.h> // CYGNUM_HAL_INTERRUPT_ETHR
+#include <cyg/hal/hal_if.h>
+
+#ifdef CYGPKG_REDBOOT
+#include <pkgconf/redboot.h>
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <redboot.h>
+#include <flash_config.h>
+#endif
+#endif
+
+
+#ifdef __WANT_DEVS
+
+#ifdef CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
+
+#ifdef CYGPKG_DEVS_ETH_PHY
+
+static char mxc_fec_name[] = "mxc_fec";
+
+#define OCR_SHIFT(bit) (((bit) * 2) % 32)
+#define OCR_MASK(bit) (3 << (OCR_SHIFT(bit)))
+#define OCR_VAL(bit,val) (((val) << (OCR_SHIFT(bit))) & (OCR_MASK(bit)))
+#define GPR_SHIFT(bit) (bit)
+#define GPR_MASK(bit) (1 << (GPR_SHIFT(bit)))
+#define GPR_VAL(bit,val) (((val) << (GPR_SHIFT(bit))) & (GPR_MASK(bit)))
+
+#ifdef CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+//
+// Verify that the given ESA is valid for this platform
+//
+static char oui[3] = CYGDAT_DEVS_ETH_ARM_TX25KARO_OUI;
+
+bool
+cyg_plf_redboot_esa_validate(unsigned char *val)
+{
+ return (val[0] == oui[0]) && (val[1] == oui[1]) && (val[2] == oui[2]);
+}
+#endif
+
+extern int tx25_mac_addr_program(unsigned char mac_addr[ETHER_ADDR_LEN]);
+
+static inline CYG_ADDRESS MX25_GPIO_ADDR(int bank)
+{
+ switch (bank) {
+ case 1:
+ return GPIO1_BASE_ADDR;
+ case 2:
+ return GPIO2_BASE_ADDR;
+ case 3:
+ return GPIO3_BASE_ADDR;
+ case 4:
+ return GPIO4_BASE_ADDR;
+ }
+ return ~0;
+}
+
+/*
+TX27 -> TX25 GPIO cross reference
+ TX27 GP Fkt GPIO Pad IOMUXC SW_PAD SW_PAD strap
+ GPIO ALT ALT OFFSET CTRL MUX option
+FEC_MDC PD9 5 0 GPIO3_5 FEC_MDC 0x1c8 0x3c0
+FEC_MDIO PD8 5 0 GPIO3_6 FEC_MDIO 0x1cc 0x3c4
+FEC_RX_CLK PD14 - - NC REGOFF: 0
+FEC_RX_DV PD13 - - NC
+FEC_RXD0 PD12 5 0 GPIO3_10 FEC_RDATA0 0x1dc 0x3d4 MODE0: 1
+FEC_RXD1 PD5 5 0 GPIO3_11 FEC_RDATA1 0x1e0 0x3d8 MODE1: 1
+FEC_RXD2 PD6 - - NC PULLUP MODE2: 1
+FEC_RXD3 PD7 - - NC INTSEL: 0
+FEC_RX_ER PD4 5 5 GPIO4_10 D10 0x09c 0x294
+FEC_TX_CLK PD11 5 0 GPIO3_13 FEC_TX_CLK 0x1e8 0x3e0
+FEC_TX_EN PF23 5 0 GPIO3_9 FEC_TX_EN 0x1d8 0x3d0
+FEC_TXD0 PD0 5 0 GPIO3_7 FEC_TDATA0 0x1d0 0x3c8
+FEC_TXD1 PD1 5 0 GPIO3_8 FEC_TDATA1 0x1d4 0x3cc
+FEC_TXD2 PD2 - - NC
+FEC_TXD3 PD3 - - NC
+FEC_COL PD15 5 0 GPIO3_12 FEC_RX_DV 0x1e4 0x3dc RMII: 1
+FEC_CRS PD10 - - NC PHYAD4: 0
+FEC_TX_ER PD16 5 5 GPIO4_8 D12 0x094 0x28c
+ GPIO2_5 A19 0x024 0x240 0x518 FEC_RX_ER
+FEC_RESET~ PB30 5 5 GPIO4_7 D13 0x090 0x288
+FEC_ENABLE PB27 5 5 GPIO4_9 D11 0x098 0x290
+*/
+
+static inline void tx25_write_reg(CYG_ADDRWORD base_addr, CYG_WORD32 offset, CYG_WORD32 val)
+{
+ if (net_debug) diag_printf("Writing %08x to reg %08x\n", val, base_addr + offset);
+ HAL_WRITE_UINT32(base_addr + offset, val);
+}
+
+static inline CYG_WORD32 tx25_read_reg(CYG_ADDRWORD base_addr, CYG_WORD32 offset)
+{
+ CYG_WORD32 val;
+ HAL_READ_UINT32(base_addr + offset, val);
+ if (net_debug) diag_printf("Read %08x from reg %08x\n", val, base_addr + offset);
+ return val;
+}
+
+static inline void tx25_set_reg(CYG_ADDRWORD base_addr, CYG_WORD32 offset,
+ CYG_WORD32 set_mask, CYG_WORD32 clr_mask)
+{
+ CYG_WORD32 val;
+ HAL_READ_UINT32(base_addr + offset, val);
+ if (net_debug) diag_printf("Changing reg %08x from %08x to %08x\n",
+ base_addr + offset, val,
+ (val & ~clr_mask) | set_mask);
+ val = (val & ~clr_mask) | set_mask;
+ HAL_WRITE_UINT32(base_addr + offset, val);
+}
+
+static struct tx25_gpio_setup {
+ cyg_uint16 iomux_addr;
+ cyg_uint8 on_func;
+ cyg_uint8 off_func;
+ cyg_uint8 grp;
+ cyg_uint8 shift;
+} tx25_fec_gpio_data[] = {
+ /* iomux, func, gpfn, gpgrp, gpshift */
+ { 0x1c8, 0, 0x15, 3, 5, },
+ { 0x1cc, 0, 0x15, 3, 6, },
+ { 0x1dc, 0, 0x15, 3, 10, },
+ { 0x1e0, 0, 0x15, 3, 11, },
+ { 0x09c, 0x85, 5, 4, 10, },
+ { 0x1e8, 0, 0x15, 3, 13, },
+ { 0x1d8, 0, 0x15, 3, 9, },
+ { 0x1d0, 0, 0x15, 3, 7, },
+ { 0x1d4, 0, 0x15, 3, 8, },
+ { 0x1e4, 0x80, 0x15, 3, 12, },
+ { 0x024, 0x05, 0x05, 2, 5, }, /* RX_ER signal; make sure it's a GPIO _without_ SION! */
+ { 0x094, 0x85, 5, 4, 8, },
+ { 0x090, 5, 5, 4, 7, },
+ { 0x098, 5, 5, 4, 9, },
+};
+
+static struct tx25_gpio_setup tx25_fec_strap_pins[] = {
+ { 0x1dc, 0, 0x15, 3, 10, },
+ { 0x1e0, 0, 0x15, 3, 11, },
+ { 0x1e4, 0, 0x15, 3, 12, },
+};
+
+static inline void tx25_phy_power_off(void)
+{
+ int i;
+
+ if (net_debug) diag_printf("Switching PHY POWER off\n");
+
+#if 1
+ for (i = 0; i < NUM_ELEMS(tx25_fec_gpio_data); i++) {
+ struct tx25_gpio_setup *gs = &tx25_fec_gpio_data[i];
+
+ if (net_debug) diag_printf("%s: GPIO%d_%d[%d] is %d\n", __FUNCTION__,
+ gs->grp, gs->shift, i,
+ gpio_tst_bit(gs->grp, gs->shift));
+ }
+#endif
+ /* deassert all pins attached to the PHY */
+ for (i = 0; i < NUM_ELEMS(tx25_fec_gpio_data); i++) {
+ struct tx25_gpio_setup *gs = &tx25_fec_gpio_data[i];
+
+ tx25_write_reg(IOMUXC_BASE_ADDR, gs->iomux_addr,
+ gs->off_func);
+ if (gs->on_func & 0x80) {
+ /* configure as input */
+ tx25_set_reg(MX25_GPIO_ADDR(gs->grp),
+ GPIO_GDIR, 0, 1 << gs->shift);
+ } else {
+ /* configure as output */
+ tx25_set_reg(MX25_GPIO_ADDR(gs->grp),
+ GPIO_DR, 0, 1 << gs->shift);
+ tx25_set_reg(MX25_GPIO_ADDR(gs->grp),
+ GPIO_GDIR, 1 << gs->shift, 0);
+ }
+ tx25_write_reg(IOMUXC_BASE_ADDR, gs->iomux_addr,
+ gs->off_func);
+ }
+ for (i = 0; i < NUM_ELEMS(tx25_fec_gpio_data); i++) {
+ struct tx25_gpio_setup *gs = &tx25_fec_gpio_data[i];
+
+ if (!(gs->on_func & 0x80) && gpio_tst_bit(gs->grp, gs->shift)) {
+ if (net_debug) diag_printf("%s: GPIO%d_%d[%d] is not low\n", __FUNCTION__,
+ gs->grp, gs->shift, i);
+ }
+ }
+ if (net_debug) diag_printf("PHY POWER off done\n");
+}
+
+static bool tx25_fec_init(struct cyg_netdevtab_entry *tab)
+{
+ cyg_bool esa_set;
+ int ok;
+
+ /* Check, whether MAC address is enabled */
+ ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+ "fec_esa", &esa_set, CONFIG_BOOL);
+ if (!(ok && esa_set)) {
+ diag_printf("FEC disabled; set fec_esa=true to enable networking\n");
+ tx25_phy_power_off();
+ return false;
+ }
+ /* call init function in devs/eth/fec/current/if_fec.c */
+ return mxc_fec_init(tab);
+}
+
+static void tx25_fec_phy_init(void)
+{
+ int i;
+ int phy_reset_delay = 100;
+
+ /*
+ * make sure the ETH PHY strap pins are pulled to the right voltage
+ * before deasserting the PHY reset GPIO
+ * REGOFF: PD14
+ * RMII: PD15
+ * nINTSEL: PD7
+ * MODE0: PD12
+ * MODE1: PD5
+ * MODE2: PD6
+ * PHYAD0: -
+ * PHYAD1: GND
+ * PHYAD2: GND
+ * PHYAD3: -
+ * PHYAD4: PD10
+ */
+ // assert FEC PHY Reset (PB30) and switch PHY power on
+ /* PB22, PB27, PB30 => GPIO out */
+#if 0
+ tx25_phy_power_off();
+#endif
+#if 0
+ tx25_write_reg(IOMUXC_BASE_ADDR, IOMUXC_GPIO1_7, 0x11);
+ tx25_write_reg(IOMUXC_BASE_ADDR, IOMUXC_NANDF_CS1, 0x14);
+#endif
+#if 0
+ while (1) {
+#if 0
+ gpio_set_bit(4, 9);
+#else
+ tx25_set_reg(MX25_GPIO_ADDR(4), GPIO_DR, 1 << 9, 0);
+#endif
+ tx25_read_reg(MX25_GPIO_ADDR(4), GPIO_DR);
+ HAL_DELAY_US(1000000);
+#if 0
+ gpio_clr_bit(4, 9);
+#else
+ tx25_set_reg(MX25_GPIO_ADDR(4), GPIO_DR, 0, 1 << 9);
+#endif
+ tx25_read_reg(MX25_GPIO_ADDR(4), GPIO_DR);
+ HAL_DELAY_US(1000000);
+ }
+#endif
+ /* Switch PHY power on and assert PHY reset */
+ if (net_debug) diag_printf("Switching PHY POWER on\n");
+ gpio_clr_bit(4, 7);
+ gpio_set_bit(4, 9);
+
+ /* wait for 22ms for LAN8700 to power up */
+ phy_reset_delay = 22000;
+
+ /* configure FEC strap pins to their required values */
+ for (i = 0; i < NUM_ELEMS(tx25_fec_strap_pins); i++) {
+ struct tx25_gpio_setup *gs = &tx25_fec_strap_pins[i];
+
+ if (net_debug) diag_printf("Asserting GPIO%d_%d\n", gs->grp,
+ gs->shift);
+#if 0
+ tx25_set_reg(MX25_GPIO_ADDR(gs->grp),
+ GPIO_GDIR, 1 << gs->shift, 0);
+ tx25_set_reg(MX25_GPIO_ADDR(gs->grp),
+ GPIO_DR, 1 << gs->shift, 0);
+ tx25_write_reg(IOMUXC_BASE_ADDR, gs->iomux_addr,
+ gs->off_func);
+#else
+ gpio_set_bit(gs->grp, gs->shift);
+#endif
+ }
+#if 0
+ for (i = 0; i < NUM_ELEMS(tx25_fec_gpio_data); i++) {
+ struct tx25_gpio_setup *gs = &tx25_fec_gpio_data[i];
+ int j;
+ int strap = 0;
+
+ for (j = 0; j < NUM_ELEMS(tx25_fec_strap_pins); j++) {
+ struct tx25_gpio_setup *sp = &tx25_fec_strap_pins[j];
+
+ if (gs->grp == sp->grp && gs->shift == sp->shift) {
+ strap = 1;
+ break;
+ }
+ }
+ if (strap || gs->on_func & 0x80) {
+ if (!gpio_tst_bit(gs->grp, gs->shift)) {
+ if (net_debug) diag_printf("GPIO%d_%d[%d] is low instead of high\n",
+ gs->grp, gs->shift, i);
+ }
+ } else {
+ if (gpio_tst_bit(gs->grp, gs->shift)) {
+ if (net_debug) diag_printf("GPIO%d_%d[%d] is high instead of low\n",
+ gs->grp, gs->shift, i);
+ }
+ }
+ }
+#endif
+ /* wait for 100us according to LAN8700 spec. before ... */
+ HAL_DELAY_US(phy_reset_delay);
+
+ /* ... deasserting FEC PHY reset */
+ if (net_debug) diag_printf("Releasing PHY RESET\n");
+ tx25_set_reg(MX25_GPIO_ADDR(4), GPIO_DR, 1 << 7, 0);
+#if 0
+ for (i = 0; i < NUM_ELEMS(tx25_fec_gpio_data); i++) {
+ struct tx25_gpio_setup *gs = &tx25_fec_gpio_data[i];
+ int j;
+ int strap = 0;
+
+ for (j = 0; j < NUM_ELEMS(tx25_fec_strap_pins); j++) {
+ struct tx25_gpio_setup *sp = &tx25_fec_strap_pins[j];
+
+ if (gs->grp == sp->grp && gs->shift == sp->shift) {
+ strap = 1;
+ break;
+ }
+ }
+ if (strap || gs->on_func & 0x80) {
+ if (!gpio_tst_bit(gs->grp, gs->shift)) {
+ if (net_debug) diag_printf("GPIO%d_%d[%d] is low instead of high\n",
+ gs->grp, gs->shift, i);
+ }
+ } else {
+ if (gpio_tst_bit(gs->grp, gs->shift)) {
+ if (net_debug) diag_printf("GPIO%d_%d[%d] is high instead of low\n",
+ gs->grp, gs->shift, i);
+ }
+ }
+ }
+#endif
+ /* configure all FEC pins to their required functions */
+ for (i = 0; i < NUM_ELEMS(tx25_fec_gpio_data); i++) {
+ struct tx25_gpio_setup *gs = &tx25_fec_gpio_data[i];
+
+ tx25_write_reg(IOMUXC_BASE_ADDR, gs->iomux_addr,
+ gs->on_func & ~0x80);
+ }
+}
+
+ETH_PHY_REG_LEVEL_ACCESS_FUNS(eth0_phy,
+ tx25_fec_phy_init,
+ mxc_fec_phy_reset,
+ mxc_fec_phy_write,
+ mxc_fec_phy_read);
+
+#define SOC_MAC_ADDR_LOCK_BIT 2
+
+cyg_bool _tx25_provide_fec_esa(unsigned char *addr)
+{
+ cyg_bool enabled;
+ int ok;
+
+ ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+ "fec_esa", &enabled, CONFIG_BOOL);
+ if (ok && enabled) {
+#ifdef CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ cyg_uint8 addr2[ETHER_ADDR_LEN];
+
+ addr[0] = readl(SOC_MAC_ADDR_BASE + 0x0);
+ addr[1] = readl(SOC_MAC_ADDR_BASE + 0x4);
+ addr[2] = readl(SOC_MAC_ADDR_BASE + 0x8);
+ addr[3] = readl(SOC_MAC_ADDR_BASE + 0xC);
+ addr[4] = readl(SOC_MAC_ADDR_BASE + 0x10);
+ addr[5] = readl(SOC_MAC_ADDR_BASE + 0x14);
+
+ if (cyg_plf_redboot_esa_validate(addr)) {
+ diag_printf("Ethernet FEC MAC address from fuse bank: ");
+ diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
+ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+ CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+ "fec_esa_data", addr2, CONFIG_ESA);
+ if (memcmp(addr, addr2, sizeof(addr)) != 0) {
+ CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_SET,
+ "fec_esa_data", addr, CONFIG_ESA);
+ }
+#ifdef SOC_MAC_ADDR_LOCK_BIT
+ if ((readl(SOC_MAC_ADDR_BASE - 0x68) & SOC_MAC_ADDR_LOCK_BIT) == 0) {
+ tx25_mac_addr_program(addr);
+ }
+#endif // SOC_MAC_ADDR_LOCK_BIT
+ return true;
+ }
+#endif // CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+
+ CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+ "fec_esa_data", addr, CONFIG_ESA);
+
+ diag_printf("Ethernet FEC MAC address from fconfig: ");
+ diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
+ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+
+#ifdef CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ if (cyg_plf_redboot_esa_validate(addr)) {
+ tx25_mac_addr_program(addr);
+ return true;
+ }
+
+ diag_printf("** Error: Invalid MAC address: ");
+ diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
+ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+
+#ifdef SOC_MAC_ADDR_LOCK_BIT
+ if ((readl(SOC_MAC_ADDR_BASE - 0x68) & SOC_MAC_ADDR_LOCK_BIT) == 0) {
+ diag_printf("Use 'fconfig fec_esa_data' to set the MAC address\n");
+ return false;
+ } else {
+ diag_printf("Using MAC address from fconfig\n");
+ }
+#else
+ diag_printf("Using MAC address from fconfig\n");
+#endif // SOC_MAC_ADDR_LOCK_BIT
+#endif // CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ return true;
+ }
+ return false;
+}
+
+static mxc_fec_priv_t mxc_fec_private = {
+ .phy = ð0_phy, // PHY access routines
+ .provide_esa = _tx25_provide_fec_esa,
+};
+
+ETH_DRV_SC(mxc_fec_sc,
+ &mxc_fec_private, // Driver specific data
+ mxc_fec_name,
+ mxc_fec_start,
+ mxc_fec_stop,
+ mxc_fec_control,
+ mxc_fec_can_send,
+ mxc_fec_send,
+ mxc_fec_recv,
+ mxc_fec_deliver, // "pseudoDSR" called from fast net thread
+ mxc_fec_poll, // poll function, encapsulates ISR and DSR
+ mxc_fec_int_vector);
+
+NETDEVTAB_ENTRY(mxc_fec_netdev,
+ mxc_fec_name,
+ tx25_fec_init,
+ &mxc_fec_sc);
+#endif
+
+#if defined(CYGPKG_REDBOOT) && defined(CYGSEM_REDBOOT_FLASH_CONFIG)
+RedBoot_config_option("Set FEC network hardware address [MAC]",
+ fec_esa,
+ ALWAYS_ENABLED, true,
+ CONFIG_BOOL, false
+ );
+RedBoot_config_option("FEC network hardware address [MAC]",
+ fec_esa_data,
+ "fec_esa", true,
+ CONFIG_ESA, 0
+ );
+#endif // CYGPKG_REDBOOT && CYGSEM_REDBOOT_FLASH_CONFIG
+
+#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+// Note that this section *is* active in an application, outside RedBoot,
+// where the above section is not included.
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+#endif // CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
+
+#endif // __WANT_DEVS
implements CYGHWR_NET_DRIVER_ETH0
implements CYGINT_DEVS_ETH_FEC_REQUIRED
+ requires CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ requires CYGHWR_DEVS_ETH_PHY_LAN8700
cdl_option CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME {
display "Device name for the ETH0 ethernet driver"
description "
This option sets the name of the ethernet device."
}
+
+ cdl_option CYGDAT_DEVS_ETH_ARM_TX27KARO_OUI {
+ display "OUI part of MAC address"
+ flavor data
+ active_if CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ default_value { "{ 0x00, 0x0c, 0xc6 }" }
+ description "
+ This option sets OUI part (manufacturer ID) of the MAC address
+ for validation."
+ }
}
define_proc {
#endif
#endif
-extern unsigned int sys_ver;
#ifdef __WANT_DEVS
#define GPR_MASK(bit) (1 << (GPR_SHIFT(bit)))
#define GPR_VAL(bit,val) (((val) << (GPR_SHIFT(bit))) & (GPR_MASK(bit)))
+#ifdef CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+//
+// Verify that the given ESA is valid for this platform
+//
+static char oui[3] = CYGDAT_DEVS_ETH_ARM_TX27KARO_OUI;
+
+bool
+cyg_plf_redboot_esa_validate(unsigned char *val)
+{
+ return (val[0] == oui[0]) && (val[1] == oui[1]) && (val[2] == oui[2]);
+}
+#endif
+
+extern int tx27_mac_addr_program(unsigned char mac_addr[ETHER_ADDR_LEN]);
+
static inline void tx27_set_reg(unsigned long addr, CYG_WORD32 set, CYG_WORD32 clr)
{
CYG_WORD32 val;
mxc_fec_phy_write,
mxc_fec_phy_read);
+cyg_bool _tx27_provide_fec_esa(unsigned char *addr)
+{
+ cyg_bool enabled;
+ int ok;
+
+ ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+ "fec_esa", &enabled, CONFIG_BOOL);
+ if (ok && enabled) {
+#ifdef CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ cyg_uint8 addr2[ETHER_ADDR_LEN];
+
+ addr[0] = readl(SOC_FEC_MAC_BASE2 + 0x0);
+ addr[1] = readl(SOC_FEC_MAC_BASE2 + 0x4);
+ addr[2] = readl(SOC_FEC_MAC_BASE2 + 0x8);
+ addr[3] = readl(SOC_FEC_MAC_BASE2 + 0xC);
+ addr[4] = readl(SOC_FEC_MAC_BASE2 + 0x10);
+ addr[5] = readl(SOC_FEC_MAC_BASE2 + 0x14);
+
+ if (cyg_plf_redboot_esa_validate(addr)) {
+ diag_printf("Ethernet FEC MAC address from fuse bank: ");
+ diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
+ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+ CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+ "fec_esa_data", addr2, CONFIG_ESA);
+ if (memcmp(addr, addr2, sizeof(addr)) != 0) {
+ CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_SET,
+ "fec_esa_data", addr, CONFIG_ESA);
+ }
+#ifdef SOC_MAC_ADDR_LOCK
+ if ((readl(SOC_FEC_MAC_BASE2 - 0x14) & SOC_MAC_ADDR_LOCK) == 0) {
+ tx27_mac_addr_program(addr);
+ }
+#endif // SOC_MAC_ADDR_LOCK
+ return true;
+ }
+#endif // CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+
+ CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+ "fec_esa_data", addr, CONFIG_ESA);
+
+ diag_printf("Ethernet FEC MAC address from fconfig: ");
+ diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
+ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+
+#ifdef CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ if (cyg_plf_redboot_esa_validate(addr)) {
+ tx27_mac_addr_program(addr);
+ return true;
+ }
+
+ diag_printf("** Error: Invalid MAC address: ");
+ diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
+ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+
+#ifdef SOC_MAC_ADDR_LOCK
+ if ((readl(SOC_FEC_MAC_BASE2 - 0x14) & SOC_MAC_ADDR_LOCK) == 0) {
+ diag_printf("Use 'fconfig fec_esa_data' to set the MAC address\n");
+ return false;
+ } else {
+ diag_printf("Using MAC address from fconfig\n");
+ }
+#else
+ diag_printf("Using MAC address from fconfig\n");
+#endif // SOC_MAC_ADDR_LOCK
+#endif // CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ return true;
+ }
+ return false;
+}
+
static mxc_fec_priv_t mxc_fec_private = {
.phy = ð0_phy, // PHY access routines
+ .provide_esa = _tx27_provide_fec_esa,
};
ETH_DRV_SC(mxc_fec_sc,
- &mxc_fec_private, // Driver specific data
+ &mxc_fec_private, // Driver specific data
mxc_fec_name,
mxc_fec_start,
mxc_fec_stop,
// Note that this section *is* active in an application, outside RedBoot,
// where the above section is not included.
-#include <cyg/hal/hal_if.h>
-
-#ifndef CONFIG_ESA
-#define CONFIG_ESA (6)
-#endif
-#ifndef CONFIG_BOOL
-#define CONFIG_BOOL (1)
-#endif
-
-#ifndef CYGSEM_REDBOOT_FLASH_CONFIG
-void _tx27_provide_fec_esa(void)
-{
- cyg_bool set_esa;
- cyg_uint8 addr[6];
- int ok;
-
- ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
- "fec_esa", &set_esa, CONFIG_BOOL);
- diag_printf("%s: Ethernet FEC MAC address from %p: ", __FUNCTION__, SOC_FEC_MAC_BASE2);
- if (ok && set_esa) {
- CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
- "fec_esa_data", addr, CONFIG_ESA);
- addr[0] = readl(SOC_FEC_MAC_BASE2 + 0x0);
- addr[1] = readl(SOC_FEC_MAC_BASE2 + 0x4);
- addr[2] = readl(SOC_FEC_MAC_BASE2 + 0x8);
- addr[3] = readl(SOC_FEC_MAC_BASE2 + 0xC);
- addr[4] = readl(SOC_FEC_MAC_BASE2 + 0x10);
- addr[5] = readl(SOC_FEC_MAC_BASE2 + 0x14);
-
- diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
- addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
- } else {
- diag_printf("is not set\n");
- }
-}
-
-RedBoot_init(_tx27_provide_fec_esa, RedBoot_INIT_LAST);
-#endif // CYGSEM_REDBOOT_FLASH_CONFIG
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
#endif // CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
--- /dev/null
+# ====================================================================
+#
+# tx37_eth_drivers.cdl
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+
+cdl_package CYGPKG_DEVS_ETH_ARM_TX37 {
+ display "Ethernet driver for Ka-Ro electronics TX37 processor module"
+
+ parent CYGPKG_IO_ETH_DRIVERS
+ active_if CYGPKG_IO_ETH_DRIVERS
+
+ include_dir cyg/io
+
+ cdl_interface CYGINT_DEVS_ETH_FEC_REQUIRED {
+ display "FEC ethernet driver required"
+ }
+
+ cdl_component CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0 {
+ display "Ka-Ro TX37 ethernet port driver"
+ flavor bool
+ default_value 1
+ description "
+ This option includes the ethernet device driver for the
+ MXC Board port."
+
+ implements CYGHWR_NET_DRIVER_ETH0
+ implements CYGINT_DEVS_ETH_FEC_REQUIRED
+ requires CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ requires CYGHWR_DEVS_ETH_PHY_LAN8700
+
+ cdl_option CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME {
+ display "Device name for the ETH0 ethernet driver"
+ flavor data
+ default_value {"\"eth0\""}
+ description "
+ This option sets the name of the ethernet device."
+ }
+
+ cdl_option CYGDAT_DEVS_ETH_ARM_TX37KARO_OUI {
+ display "OUI part of MAC address"
+ flavor data
+ active_if CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ default_value { "{ 0x00, 0x0c, 0xc6 }" }
+ description "
+ This option sets OUI part (manufacturer ID) of the MAC address
+ for validation."
+ }
+ }
+
+ define_proc {
+ puts $::cdl_system_header "/***** ethernet driver proc output start *****/"
+ puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_FEC_CFG <pkgconf/devs_eth_arm_tx37.h>"
+ puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_FEC_INL <cyg/io/devs_eth_arm_tx37.inl>"
+ puts $::cdl_system_header "/***** ethernet driver proc output end *****/"
+ }
+}
--- /dev/null
+//==========================================================================
+//
+// devs_eth_arm_tx37.inl
+//
+// Board ethernet I/O definitions.
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_intr.h> // CYGNUM_HAL_INTERRUPT_ETHR
+#include <cyg/hal/hal_if.h>
+
+#ifdef CYGPKG_REDBOOT
+#include <pkgconf/redboot.h>
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <redboot.h>
+#include <flash_config.h>
+#endif
+#endif
+
+
+#ifdef __WANT_DEVS
+
+#ifdef CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
+
+#ifdef CYGPKG_DEVS_ETH_PHY
+
+static char mxc_fec_name[] = "mxc_fec";
+
+#define IOMUXC_CSPI1_MISO 0x138
+#define IOMUXC_AUD5_WB_FS 0x130
+#define IOMUXC_EIM_CS1 0x058
+#define IOMUXC_EIM_BCLK 0x064
+#define IOMUXC_UART1_RI 0x174
+#define IOMUXC_CSPI1_SS1 0x140
+#define IOMUXC_CSPI2_MOSI 0x148
+#define IOMUXC_CSPI2_MISO 0x14c
+#define IOMUXC_CSPI1_MOSI 0x134
+#define IOMUXC_EIM_RW 0x068
+#define IOMUXC_EIM_OE 0x050
+#define IOMUXC_UART1_DCD 0x178
+#define IOMUXC_CSPI2_SS0 0x150
+#define IOMUXC_CSPI2_SS1 0x154
+#define IOMUXC_CSPI2_SCLK 0x158
+#define IOMUXC_EIM_CS0 0x054
+#define IOMUXC_CSPI1_SS0 0x13c
+#define IOMUXC_CSPI1_SCLK 0x144
+
+#define IOMUXC_GPIO1_7 0x22c
+#define IOMUXC_NANDF_CS1 0x088
+
+#define SW_PAD_CTL_CSPI1_MISO 0x398
+#define SW_PAD_CTL_AUD5_WB_FS 0x390
+#define SW_PAD_CTL_EIM_CS1 0x2b8
+#define SW_PAD_CTL_EIM_BCLK 0x2c4
+#define SW_PAD_CTL_UART1_RI 0x3d4
+#define SW_PAD_CTL_CSPI1_SS1 0x3a0
+#define SW_PAD_CTL_CSPI2_MOSI 0x3a8
+#define SW_PAD_CTL_CSPI2_MISO 0x3ac
+#define SW_PAD_CTL_CSPI1_MOSI 0x394
+#define SW_PAD_CTL_EIM_RW 0x2c8
+#define SW_PAD_CTL_EIM_OE 0x2b0
+#define SW_PAD_CTL_UART1_DCD 0x3d8
+#define SW_PAD_CTL_CSPI2_SS0 0x3b0
+#define SW_PAD_CTL_CSPI2_SS1 0x3b4
+#define SW_PAD_CTL_CSPI2_SCLK 0x3b8
+#define SW_PAD_CTL_EIM_CS0 0x2b4
+#define SW_PAD_CTL_CSPI1_SS0 0x39c
+#define SW_PAD_CTL_CSPI1_SCLK 0x3a4
+
+#define SW_PAD_CTL_GPIO1_7 0x484
+#define SW_PAD_CTL_NANDF_CS1 0x2e8
+
+#define SW_PAD_MUX_CSPI3_IPP_IND_MISO 0x518
+
+#define MX37_GPIO_ADDR(bank) (GPIO1_BASE_ADDR + (((bank) - 1) << 14))
+
+/*
+TX37 -> TX27 GPIO cross reference
+ TX27 Funktion GPIO Pad IOMUXC SW_PAD SW_PAD mode strap
+ GPIO ALT ALT OFFSET CTRL MUX option
+FEC_MDC PD9 5 4 GPIO3_1 CSPI1_MISO 0x138 0x398
+FEC_MDIO PD8 5 4 GPIO2_23 AUD5_WB_FS 0x130 0x390 0x5a8 0
+FEC_RX_CLK PD14 2 1 GPIO2_1 EIM_CS1 0x058 0x2b8 0x5b0 0 REGOFF: 0
+FEC_RX_DV PD13 2 3 GPIO1_10 EIM_BCLK 0x064 0x2c4 0x5b4 0
+FEC_RXD0 PD12 5 4 GPIO2_30 UART1_RI 0x174 0x3d4 0x5ac 1 MODE0: 1
+FEC_RXD1 PD5 2 4 GPIO3_3 CSPI1_SS1 0x140 0x3a0 MODE1: 1
+FEC_RXD2 PD6 2 4 GPIO3_5 CSPI2_MOSI 0x148 0x3a8 MODE2: 1
+FEC_RXD3 PD7 2 4 GPIO3_6 CSPI2_MISO 0x14c 0x3ac INTSEL: 0
+FEC_RX_ER PD4 5 4 GPIO3_0 CSPI1_MOSI 0x134 0x394 0x5b8 1
+FEC_TX_CLK PD11 2 3 GPIO1_9 EIM_RW 0x068 0x2c8 0x5bc 0
+FEC_TX_EN PF23 2 3 GPIO1_13 EIM_OE 0x050 0x2b0
+FEC_TXD0 PD0 5 4 GPIO2_31 UART1_DCD 0x178 0x3d8
+FEC_TXD1 PD1 2 4 GPIO3_7 CSPI2_SS0 0x150 0x3b0
+FEC_TXD2 PD2 2 4 GPIO3_8 CSPI2_SS1 0x154 0x3b4 :( reference Manual says: 0xBASE_
+FEC_TXD3 PD3 2 4 GPIO3_9 CSPI2_SCLK 0x158 0x3b8
+FEC_COL PD15 2 1 GPIO2_0 EIM_CS0 0x054 0x2b4 0x5a0 0 RMII: 0
+FEC_CRS PD10 5 4 GPIO3_2 CSPI1_SS0 0x13c 0x39c 0x5a4 1 PHYAD4: 0
+FEC_TX_ER PD16 5 4 GPIO3_4 CSPI1_SCLK 0x144 0x3a4
+
+OSC26M_ENABLE PB22 GPIO2 vom PMIC --- ---
+FEC_RESET~ PB30 1 GPIO1_7 GPIO1_7 0x22c 0x484
+FEC_ENABLE PB27 4 GPIO2_9 NANDF_CS1 0x088 0x2e8
+*/
+
+#ifdef CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+//
+// Verify that the given ESA is valid for this platform
+//
+static char oui[3] = CYGDAT_DEVS_ETH_ARM_TX37KARO_OUI;
+
+bool
+cyg_plf_redboot_esa_validate(unsigned char *val)
+{
+ return (val[0] == oui[0]) && (val[1] == oui[1]) && (val[2] == oui[2]);
+}
+#endif
+
+#ifdef SOC_MAC_ADDR_BASE
+extern int tx37_mac_addr_program(unsigned char mac_addr[ETHER_ADDR_LEN]);
+#else
+static inline int tx37_mac_addr_program(unsigned char mac_addr[ETHER_ADDR_LEN])
+{
+ return 0;
+}
+#endif // SOC_MAC_ADDR_BASE
+
+static inline void tx37_write_reg(CYG_ADDRWORD base_addr, CYG_WORD32 offset, CYG_WORD32 val)
+{
+ if (net_debug) {
+ diag_printf("Changing reg %08x from %08x to %08x\n",
+ base_addr + offset, readl(base_addr + offset), val);
+ }
+ HAL_WRITE_UINT32(base_addr + offset, val);
+}
+
+static inline CYG_WORD32 tx37_read_reg(CYG_ADDRWORD base_addr, CYG_WORD32 offset)
+{
+ CYG_WORD32 val;
+ HAL_READ_UINT32(base_addr + offset, val);
+ if (net_debug) diag_printf("Read %08x from reg %08x\n", val, base_addr + offset);
+ return val;
+}
+
+static inline void tx37_set_reg(CYG_ADDRWORD base_addr, CYG_WORD32 offset,
+ CYG_WORD32 set_mask, CYG_WORD32 clr_mask)
+{
+ CYG_WORD32 val;
+ HAL_READ_UINT32(base_addr + offset, val);
+ if (net_debug) diag_printf("Changing reg %08x from %08x to %08x\n", base_addr + offset, val,
+ (val & ~clr_mask) | set_mask);
+ val = (val & ~clr_mask) | set_mask;
+ HAL_WRITE_UINT32(base_addr + offset, val);
+}
+
+static struct tx37_gpio_setup {
+ cyg_uint16 iomux_addr;
+ cyg_uint8 on_func;
+ cyg_uint8 off_func;
+ cyg_uint8 grp;
+ cyg_uint8 shift;
+} tx37_fec_gpio_data[] = {
+ /* iomux reg offset, func, gpgrp */
+ /* gpiofn, gpshift */
+ { IOMUXC_CSPI1_MISO, 0x15, 0x14, 3, 1, },
+ { IOMUXC_AUD5_WB_FS, 0x15, 0x14, 2, 23, },
+ { IOMUXC_EIM_CS1, 0x12, 0x11, 2, 1, },
+ { IOMUXC_EIM_BCLK, 0x12, 0x13, 1, 10, },
+ { IOMUXC_UART1_RI, 0x15, 0x14, 2, 30, },
+ { IOMUXC_CSPI1_SS1, 0x12, 0x14, 3, 3, },
+ { IOMUXC_CSPI2_MOSI, 0x12, 0x14, 3, 5, },
+ { IOMUXC_CSPI2_MISO, 0x12, 0x14, 3, 6, },
+ { IOMUXC_CSPI1_MOSI, 0x15, 0x14, 3, 0, },
+ { IOMUXC_EIM_RW, 0x12, 0x13, 1, 9, },
+ { IOMUXC_EIM_OE, 0x12, 0x13, 1, 13, },
+ { IOMUXC_UART1_DCD, 0x15, 0x14, 2, 31, },
+ { IOMUXC_CSPI2_SS0, 0x12, 0x14, 3, 7, },
+ { IOMUXC_CSPI2_SS1, 0x12, 0x14, 3, 8, },
+ { IOMUXC_CSPI2_SCLK, 0x12, 0x14, 3, 9, },
+ { IOMUXC_EIM_CS0, 0x12, 0x11, 2, 0, },
+ { IOMUXC_CSPI1_SS0, 0x15, 0x14, 3, 2, },
+ { IOMUXC_CSPI1_SCLK, 0x15, 0x14, 3, 4, },
+ { IOMUXC_GPIO1_7, 0x11, 0x11, 1, 7, },
+ { IOMUXC_NANDF_CS1, 0x14, 0x14, 2, 9, },
+};
+
+static struct tx37_gpio_setup tx37_fec_strap_pins[] = {
+ { IOMUXC_NANDF_CS1, 0x14, 0x14, 2, 9, },
+ { IOMUXC_UART1_RI, 0x15, 0x14, 2, 30, },
+ { IOMUXC_CSPI1_SS1, 0x12, 0x14, 3, 3, },
+ { IOMUXC_CSPI2_MOSI, 0x12, 0x14, 3, 5, },
+};
+
+static struct tx37_gpio_setup tx37_fec_mux_table[] = {
+ { 0x5a0, 0, }, /* FEC_COL via EIM_CS0 */
+ { 0x5a4, 1, }, /* FEC_CRS via CSPI1_SS0 */
+ { 0x5a8, 0, }, /* FEC_MDIO via AUD5_WB_FS */
+ { 0x5ac, 1, }, /* FEC_RXD0 via UART1_RI */
+ { 0x5b0, 0, }, /* FEC_RX_CLK via EIM_CS1 */
+ { 0x5b4, 0, }, /* FEC_RX_DV via EIM_BCLK */
+ { 0x5b8, 1, }, /* FEC_RX_ER via CSPI1_MOSI */
+ { 0x5bc, 0, }, /* FEC_TX_CLK via EIM_RW */
+};
+
+static inline void tx37_phy_power_off(void)
+{
+ int i;
+
+ if (net_debug) diag_printf("Switching PHY POWER off\n");
+
+#if 1
+ for (i = 0; i < NUM_ELEMS(tx37_fec_gpio_data); i++) {
+ struct tx37_gpio_setup *gs = &tx37_fec_gpio_data[i];
+
+ if (net_debug) diag_printf("%s: GPIO%d_%d[%d] is %d\n", __FUNCTION__,
+ gs->grp, gs->shift, i,
+ gpio_tst_bit(gs->grp, gs->shift));
+ }
+#endif
+ /* deassert all pins attached to the PHY */
+ for (i = 0; i < NUM_ELEMS(tx37_fec_gpio_data); i++) {
+ struct tx37_gpio_setup *gs = &tx37_fec_gpio_data[i];
+
+ tx37_set_reg(MX37_GPIO_ADDR(gs->grp),
+ GPIO_DR, 0, 1 << gs->shift);
+ tx37_set_reg(MX37_GPIO_ADDR(gs->grp),
+ GPIO_GDIR, 1 << gs->shift, 0);
+ tx37_write_reg(IOMUXC_BASE_ADDR, gs->iomux_addr,
+ gs->off_func);
+ }
+ /* setup pin mux */
+ for (i = 0; i < NUM_ELEMS(tx37_fec_mux_table); i++) {
+ struct tx37_gpio_setup *gs = &tx37_fec_mux_table[i];
+
+ tx37_write_reg(IOMUXC_BASE_ADDR, gs->iomux_addr, gs->on_func);
+ }
+#ifdef DEBUG
+ for (i = 0; i < NUM_ELEMS(tx37_fec_gpio_data); i++) {
+ struct tx37_gpio_setup *gs = &tx37_fec_gpio_data[i];
+
+ if (gpio_tst_bit(gs->grp, gs->shift)) {
+ if (net_debug) diag_printf("%s: GPIO%d_%d[%d] is not low\n", __FUNCTION__,
+ gs->grp, gs->shift, i);
+ }
+ }
+#endif
+ if (net_debug) diag_printf("PHY POWER off done\n");
+}
+
+static bool mxc_fec_init(struct cyg_netdevtab_entry *tab);
+static bool tx37_fec_init(struct cyg_netdevtab_entry *tab)
+{
+ cyg_bool esa_set;
+ int ok;
+
+ /* Check, whether MAC address is enabled */
+ ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+ "fec_esa", &esa_set, CONFIG_BOOL);
+ if (!(ok && esa_set)) {
+ diag_printf("FEC disabled; set fec_esa=true to enable networking\n");
+ return false;
+ }
+ return mxc_fec_init(tab);
+}
+
+static void tx37_fec_phy_init(void)
+{
+ int i;
+ int phy_reset_delay = 100;
+
+ /*
+ * make sure the ETH PHY strap pins are pulled to the right voltage
+ * before deasserting the PHY reset GPIO
+ * REGOFF: PD14
+ * RMII: PD15
+ * nINTSEL: PD7
+ * MODE0: PD12
+ * MODE1: PD5
+ * MODE2: PD6
+ * PHYAD0: -
+ * PHYAD1: GND
+ * PHYAD2: GND
+ * PHYAD3: -
+ * PHYAD4: PD10
+ */
+ // assert FEC PHY Reset (PB30) and switch PHY power on
+ /* PB22, PB27, PB30 => GPIO out */
+#if 0
+ tx37_phy_power_off();
+#endif
+ if (!gpio_tst_bit(2, 9)) {
+ if (net_debug) diag_printf("Switching PHY POWER on\n");
+ /* switch FEC power off and assert FEC_RESET~ (low) */
+ tx37_read_reg(MX37_GPIO_ADDR(1), GPIO_PSR);
+ gpio_clr_bit(1, 7);
+ gpio_set_bit(2, 9);
+ tx37_read_reg(MX37_GPIO_ADDR(1), GPIO_PSR);
+
+ /* wait for 22ms for LAN8700 to power up */
+ phy_reset_delay = 22000 * 5;
+#if 1
+ if (!gpio_tst_bit(2, 9)) {
+ diag_printf("**Failed to switch PHY power on: GPIO2_PSR[%08lx]=%08x\n",
+ MX37_GPIO_ADDR(2) + GPIO_PSR,
+ tx37_read_reg(MX37_GPIO_ADDR(2), GPIO_PSR));
+ }
+#endif
+#if 1
+ if (gpio_tst_bit(1, 7)) {
+ diag_printf("**Failed to assert PHY reset: GPIO1_PSR[%08lx]=%08x\n",
+ MX37_GPIO_ADDR(1) + GPIO_PSR,
+ tx37_read_reg(MX37_GPIO_ADDR(1), GPIO_PSR));
+ }
+#endif
+ } else {
+ if (net_debug) diag_printf("Asserting PHY RESET\n");
+ tx37_read_reg(MX37_GPIO_ADDR(1), GPIO_PSR);
+ gpio_clr_bit(1, 7);
+ if (gpio_tst_bit(1, 7)) {
+ diag_printf("**Failed to assert PHY reset: GPIO1_PSR[%08lx]=%08x\n",
+ MX37_GPIO_ADDR(1) + GPIO_PSR,
+ tx37_read_reg(MX37_GPIO_ADDR(1), GPIO_PSR));
+ }
+ tx37_read_reg(MX37_GPIO_ADDR(1), GPIO_PSR);
+ }
+
+ /* configure FEC strap pins to their required values */
+ for (i = 0; i < NUM_ELEMS(tx37_fec_strap_pins); i++) {
+ struct tx37_gpio_setup *gs = &tx37_fec_strap_pins[i];
+
+ if (net_debug) diag_printf("Asserting GPIO%d_%d\n", gs->grp,
+ gs->shift);
+ tx37_set_reg(MX37_GPIO_ADDR(gs->grp),
+ GPIO_GDIR, 1 << gs->shift, 0);
+ tx37_set_reg(MX37_GPIO_ADDR(gs->grp),
+ GPIO_DR, 1 << gs->shift, 0);
+ tx37_write_reg(IOMUXC_BASE_ADDR, gs->iomux_addr,
+ gs->off_func);
+ gpio_set_bit(gs->grp, gs->shift);
+ if (!gpio_tst_bit(gs->grp, gs->shift)) {
+ diag_printf("**Failed to assert GPIO%d_%d: GPIO%d_PSR[%08lx]=%08x\n",
+ gs->grp, gs->shift, gs->grp,
+ MX37_GPIO_ADDR(gs->grp) + GPIO_PSR,
+ tx37_read_reg(MX37_GPIO_ADDR(gs->grp), GPIO_PSR));
+ }
+ }
+ for (i = 0; i < NUM_ELEMS(tx37_fec_gpio_data); i++) {
+ struct tx37_gpio_setup *gs = &tx37_fec_gpio_data[i];
+ int j;
+ int strap = 0;
+
+ for (j = 0; j < NUM_ELEMS(tx37_fec_strap_pins); j++) {
+ struct tx37_gpio_setup *sp = &tx37_fec_strap_pins[j];
+
+ if (gs->grp == sp->grp && gs->shift == sp->shift) {
+ strap = 1;
+ break;
+ }
+ }
+ if (strap) {
+ if (!gpio_tst_bit(gs->grp, gs->shift)) {
+ if (net_debug) diag_printf("GPIO%d_%d[%d] is low instead of high\n",
+ gs->grp, gs->shift, i);
+ }
+ } else {
+ if (gpio_tst_bit(gs->grp, gs->shift)) {
+ if (net_debug) diag_printf("GPIO%d_%d[%d] is high instead of low\n",
+ gs->grp, gs->shift, i);
+ }
+ }
+ }
+ /* wait for 100us according to LAN8700 spec. before ... */
+ HAL_DELAY_US(phy_reset_delay);
+
+ /* ... deasserting FEC PHY reset */
+ if (net_debug) diag_printf("Releasing PHY RESET\n");
+ gpio_set_bit(1, 7);
+ if (!gpio_tst_bit(1, 7)) {
+ diag_printf("**Failed to release PHY reset\n");
+ }
+
+ /* configure all FEC pins to their required functions */
+ for (i = 0; i < NUM_ELEMS(tx37_fec_gpio_data); i++) {
+ struct tx37_gpio_setup *gs = &tx37_fec_gpio_data[i];
+
+ tx37_write_reg(IOMUXC_BASE_ADDR, gs->iomux_addr,
+ gs->on_func);
+ }
+}
+
+ETH_PHY_REG_LEVEL_ACCESS_FUNS(eth0_phy,
+ tx37_fec_phy_init,
+ mxc_fec_phy_reset,
+ mxc_fec_phy_write,
+ mxc_fec_phy_read);
+
+cyg_bool _tx37_provide_fec_esa(unsigned char *addr)
+{
+ cyg_bool enabled;
+ int ok;
+
+#if 0
+ addr[0] = 0x00;
+ addr[1] = 0x0c;
+ addr[2] = 0xc6;
+ addr[3] = 0x76;
+ addr[4] = 0x6e;
+ addr[5] = 0x02;
+ return true;
+#endif
+
+ ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+ "fec_esa", &enabled, CONFIG_BOOL);
+ if (ok && enabled) {
+#ifdef CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+#ifdef SOC_MAC_ADDR_BASE
+ cyg_uint8 addr2[ETHER_ADDR_LEN];
+
+ addr[0] = readl(SOC_FEC_MAC_BASE2 + 0x0);
+ addr[1] = readl(SOC_FEC_MAC_BASE2 + 0x4);
+ addr[2] = readl(SOC_FEC_MAC_BASE2 + 0x8);
+ addr[3] = readl(SOC_FEC_MAC_BASE2 + 0xC);
+ addr[4] = readl(SOC_FEC_MAC_BASE2 + 0x10);
+ addr[5] = readl(SOC_FEC_MAC_BASE2 + 0x14);
+
+ if (cyg_plf_redboot_esa_validate(addr)) {
+ diag_printf("Ethernet FEC MAC address from fuse bank: ");
+ diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
+ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+ CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+ "fec_esa_data", addr2, CONFIG_ESA);
+ if (memcmp(addr, addr2, sizeof(addr)) != 0) {
+ CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_SET,
+ "fec_esa_data", addr, CONFIG_ESA);
+ }
+#ifdef SOC_MAC_ADDR_LOCK
+ if ((readl(SOC_FEC_MAC_BASE2 - 0x14) & SOC_MAC_ADDR_LOCK) == 0) {
+ tx37_mac_addr_program(addr);
+ }
+#endif // SOC_MAC_ADDR_LOCK
+ return true;
+ }
+#endif // SOC_MAC_ADDR_BASE
+#endif // CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+
+ CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+ "fec_esa_data", addr, CONFIG_ESA);
+#ifdef SOC_MAC_ADDR_BASE
+ writel(addr[0], SOC_FEC_MAC_BASE2 + 0x0);
+ writel(addr[1], SOC_FEC_MAC_BASE2 + 0x4);
+ writel(addr[2], SOC_FEC_MAC_BASE2 + 0x8);
+ writel(addr[3], SOC_FEC_MAC_BASE2 + 0xC);
+ writel(addr[4], SOC_FEC_MAC_BASE2 + 0x10);
+ writel(addr[5], SOC_FEC_MAC_BASE2 + 0x14);
+#endif // SOC_MAC_ADDR_BASE
+
+ diag_printf("Ethernet FEC MAC address from fconfig: ");
+ diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
+ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+
+#ifdef CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ if (cyg_plf_redboot_esa_validate(addr)) {
+ tx37_mac_addr_program(addr);
+ return true;
+ }
+ diag_printf("** Error: Invalid MAC address: ");
+ diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
+ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+
+#ifdef SOC_MAC_ADDR_LOCK
+ if ((readl(SOC_FEC_MAC_BASE2 - 0x14) & SOC_MAC_ADDR_LOCK) == 0) {
+ diag_printf("Use 'fconfig fec_esa_data' to set the MAC address\n");
+ return false;
+ } else {
+ diag_printf("Using MAC address from fconfig\n");
+ }
+#else
+ diag_printf("Using MAC address from fconfig\n");
+#endif // SOC_MAC_ADDR_LOCK
+#endif // CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+ return true;
+ }
+ return false;
+}
+
+static mxc_fec_priv_t mxc_fec_private = {
+ .phy = ð0_phy, // PHY access routines
+ .provide_esa = _tx37_provide_fec_esa,
+};
+
+ETH_DRV_SC(mxc_fec_sc,
+ &mxc_fec_private, // Driver specific data
+ mxc_fec_name,
+ mxc_fec_start,
+ mxc_fec_stop,
+ mxc_fec_control,
+ mxc_fec_can_send,
+ mxc_fec_send,
+ mxc_fec_recv,
+ mxc_fec_deliver, // "pseudoDSR" called from fast net thread
+ mxc_fec_poll, // poll function, encapsulates ISR and DSR
+ mxc_fec_int_vector);
+
+NETDEVTAB_ENTRY(mxc_fec_netdev,
+ mxc_fec_name,
+ tx37_fec_init,
+ &mxc_fec_sc);
+#endif
+
+#if defined(CYGPKG_REDBOOT) && defined(CYGSEM_REDBOOT_FLASH_CONFIG)
+RedBoot_config_option("Set FEC network hardware address [MAC]",
+ fec_esa,
+ ALWAYS_ENABLED, true,
+ CONFIG_BOOL, false
+ );
+RedBoot_config_option("FEC network hardware address [MAC]",
+ fec_esa_data,
+ "fec_esa", true,
+ CONFIG_ESA, 0
+ );
+#endif // CYGPKG_REDBOOT && CYGSEM_REDBOOT_FLASH_CONFIG
+
+#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+// Note that this section *is* active in an application, outside RedBoot,
+// where the above section is not included.
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+#endif // CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
+
+#endif // __WANT_DEVS
+2007-09-04 Stephen Finney <shf@pfinc.com>
+
+ * add timeout to potential infinite loop in cs8900a_send per
+ bugzilla report 1000281
+
+2005-11-10 Laurent Gonzalez <laurent.gonzalez@trango-systems.com>
+
+ * include/cs8900a.h:
+ * src/if_cs8900a.c: Added a priority field in cpd
+ that makes interrupt priority configurable
+
2005-05-04 Ian Campbell <icampbell@arcom.com>
* cdl/cl_cs8900a_eth_drivers.cdl: Added
cyg_uint8 esa[6];
provide_esa_t provide_esa;
cyg_vector_t interrupt; // Interrupt vector used by controller
+ int priority; // Priority level used by controller
cyg_handle_t interrupt_handle;
cyg_interrupt interrupt_object;
cyg_addrword_t base;
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
// Initialize environment, setup interrupt handler
cyg_drv_interrupt_create(cpd->interrupt,
- 0, // Priority - what goes here?
+ cpd->priority,
(cyg_addrword_t)cpd, // Data item passed to interrupt handler
(cyg_ISR_t *)cs8900a_isr,
(cyg_DSR_t *)cs8900a_dsr,
cyg_uint16 saved_data = 0, *sdata;
cyg_uint16 stat;
bool odd_byte = false;
- int timeout = 50000;
// Mark xmitter busy
cpd->txbusy = true;
HAL_WRITE_UINT16(cpd->base+CS8900A_TxLEN, total_len);
// Wait for controller ready signal
- do {
- stat = get_reg(base, PP_BusStat);
- if (timeout-- < 0) {
+ {
+ // add timeout per cs8900a bugzilla report 1000281 */
+ int timeout = 1000;
+
+ do {
+ stat = get_reg(base, PP_BusStat);
+#if DEBUG & 1
+ if( stat & PP_BusStat_TxBid )
+ diag_printf( "cs8900a_send: Bid error!\n" );
+#endif
+ } while (!(stat & PP_BusStat_TxRDY) && --timeout);
+
+ if( !timeout ) {
+ // we might as well just return, since if we write the data it will
+ // just get thrown away
+ diag_printf("if_cs8900a.c: PP_BusStat_TXRDY is not set. Cannot transmit packet\n");
return;
}
- } while (!(stat & PP_BusStat_TxRDY));
-
- if (timeout < 0) {
- diag_printf("if_cs8900a.c: PP_BusStat_TXRDY is not set. Cannot transmit packet\n");
- return;
}
+
// Put data into buffer
for (i = 0; i < sg_len; i++) {
data = (cyg_uint8 *)sg_list[i].buf;
+2005-11-07 David Vrabel <dvrabel@arcom.com>
+
+ * src/if_dm9000.c, include/dm9000_info.h: Support interrupts.
+ * cdl/davicom_dm9000_eth_drivers.cdl
+ (CYGPKG_DEVS_ETH_DAVICOM_DM9000_CFLAGS_ADD): Need _KERNEL and
+ __ECOS defined for non-stand-alone builds.
+
+2005-10-25 David Vrabel <dvrabel@arcom.com>
+
+ * src/if_dm9000.c (eeprom_read, eeprom_write, eeprom_reload):
+ Delay more when writing/reading eeprom (200 us isn't enough).
+ (phy_init): Turn on PHY before writing PHY registers. Wait for
+ auto negotiation to be complete.
+ (dm9000_send): Correctly write last words to Tx SRAM when using a
+ 8/16 bit device. Clarify and comment code.
+ (dm9000_poll): Parse Rx packet header correctly on 8/16 bit
+ devices.
+ (dm9000_ioctl): Handle ETH_DRV_GET_MAC_ADDRESS and
+ ETH_DRV_SET_MAC_ADDRESS.
+
+ * cdl/davicom_dm9000_eth_drivers.cdl: New option
+ CYGSEM_DEVS_ETH_DAVICOM_DM9000_WRITE_EEPROM to enable/disable
+ writing to EEPROM.
+
2004-09-05 Mark Salter <msalter@redhat.com>
Initial Checkin of DM9000 Ethernet driver (RedBoot only for now).
compile -library=libextras.a if_dm9000.c
+ cdl_option CYGSEM_DEVS_ETH_DAVICOM_DM9000_WRITE_EEPROM {
+ display "SIOCSIFHWADDR records ESA (MAC address) in EEPROM"
+ default_value 0
+ description "
+ The ioctl() socket call with operand SIOCSIFHWADDR sets the
+ interface hardware address - the MAC address or Ethernet Station
+ Address (ESA). This option causes the new MAC address to be
+ written into the EEPROM associated with the interface, so that the
+ new MAC address is permanently recorded. Doing this should be a
+ carefully chosen decision, hence this option."
+ }
+
cdl_option CYGNUM_DEVS_ETH_DAVICOM_DM9000_DEV_COUNT {
display "Number of supported interfaces."
calculated { CYGINT_DEVS_ETH_DAVICOM_DM9000_REQUIRED }
display "Additional compiler flags"
flavor data
no_define
- default_value { "" }
+ default_value { "-D_KERNEL -D__ECOS" }
description "
This option modifies the set of compiler flags for
building the Davicom DM9000 ethernet driver package.
unsigned long txkey;
volatile unsigned char *io_addr; // addr register
volatile unsigned char *io_data; // data register
+ cyg_vector_t interrupt; // Interrupt vector used by controller
int (*read_data)(struct dm9000 *p, cyg_uint8 *dest);
int (*write_data)(struct dm9000 *p, cyg_uint8 *src);
int buswidth;
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+ cyg_handle_t interrupt_handle;
+ cyg_interrupt interrupt_object;
+#endif
};
#define CYGDAT_DEVS_ETH_DESCRIPTION "Davicom DM9000 Ethernet"
#include <pkgconf/system.h>
#include <pkgconf/io_eth_drivers.h>
#include <pkgconf/devs_eth_davicom_dm9000.h>
+
#include <cyg/infra/cyg_type.h>
#include <cyg/infra/cyg_ass.h>
#include <cyg/hal/hal_arch.h>
#define DM9000_PKT_MAX 1536
+//#define DEBUG
+//#define DEBUG_DUMP
+
//
// Control and Status register offsets
//
#define IMR_PTM (1 << 1)
#define IMR_PRM (1 << 0)
+/* PHY registers */
+#define PHY_BMCR 0x00
+#define PHY_BMSR 0x01
+#define PHY_ANAR 0x04
+
+/* PHY BMCR (Basic Mode Control Register) */
+#define PHY_BMCR_AUTO_NEG_EN (1 << 12)
+#define PHY_BMCR_AUTO_NEG_START (1 << 12)
+
+/* PHY BMSR (Basic Mode Status Register) */
+#define PHY_BMSR_AUTO_NEG_COMPLETE (1 << 5)
// Read one datum from 8-bit bus
static int read_data_8(struct dm9000 *p, cyg_uint8 *dest)
putreg(p, DM_EPCR, EPCR_ERPRR);
while (getreg(p, DM_EPCR) & EPCR_ERRE)
;
- CYGACC_CALL_IF_DELAY_US(200);
+ CYGACC_CALL_IF_DELAY_US(8000);
putreg(p, DM_EPCR, 0);
return getreg(p, DM_EPDRL) | (getreg(p, DM_EPDRH) << 8);
}
putreg(p, DM_EPCR, EPCR_WEP | EPCR_ERPRW);
while (getreg(p, DM_EPCR) & EPCR_ERRE)
;
- CYGACC_CALL_IF_DELAY_US(200);
+ CYGACC_CALL_IF_DELAY_US(8000);
putreg(p, DM_EPCR, 0);
}
putreg(p, DM_EPCR, EPCR_REEP);
while (getreg(p, DM_EPCR) & EPCR_ERRE)
;
- CYGACC_CALL_IF_DELAY_US(200);
+ CYGACC_CALL_IF_DELAY_US(8000);
putreg(p, DM_EPCR, 0);
}
static void init_phy(struct dm9000 *p)
{
- phy_write(p, 4, 0x1e1); // Advertise 10/100 half/full duplex w/CSMA
- phy_write(p, 0, 0x1200); // enable autoneg
+ int t = 0;
+ cyg_uint16 r;
+
+ /* power on PHY */
+ putreg(p, DM_GPCR, 0x01);
+ putreg(p, DM_GPR, 0x00);
- // release reset
- putreg(p, DM_GPCR, 1);
- putreg(p, DM_GPR, 0);
+ phy_write(p, PHY_ANAR, 0x1e1); // Advertise 10/100 half/full duplex w/CSMA
+ phy_write(p, PHY_BMCR, PHY_BMCR_AUTO_NEG_EN | PHY_BMCR_AUTO_NEG_START);
+
+ /* wait for autonegotiation to complete */
+ do {
+ CYGACC_CALL_IF_DELAY_US(1000);
+ r = phy_read(p, PHY_BMSR);
+ } while (!(r & PHY_BMSR_AUTO_NEG_COMPLETE) && t++ < 2000);
}
return 1;
}
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+static cyg_uint32 dm9000_isr(cyg_vector_t vector, cyg_addrword_t data)
+{
+ struct eth_drv_sc *sc = (struct eth_drv_sc *)data;
+ struct dm9000 *priv = (struct dm9000 *)sc->driver_private;
+
+ cyg_drv_interrupt_mask(priv->interrupt);
+ cyg_drv_interrupt_acknowledge(priv->interrupt);
+
+ return CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
+}
+#endif
+
// ------------------------------------------------------------------------
//
if (id != 0x90000A46)
return 0;
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+ cyg_drv_interrupt_create(priv->interrupt,
+ 0,
+ (cyg_addrword_t)sc,
+ dm9000_isr,
+ eth_drv_dsr,
+ &priv->interrupt_handle,
+ &priv->interrupt_object);
+ cyg_drv_interrupt_attach(priv->interrupt_handle);
+ cyg_drv_interrupt_acknowledge(priv->interrupt);
+ cyg_drv_interrupt_unmask(priv->interrupt);
+#endif // !CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
+
for (i = 0; i < 64; i++)
u16tab[i] = eeprom_read(priv, i);
++sg;
} while (nread < total_len);
-#if 0
- // dump packet
+#ifdef DEBUG_DUMP
for (sg = sg_list; sg < (sg_list + sg_len); sg++) {
diag_printf("\n");
diag_dump_buf(sg->buf, sg->len);
int total_len, unsigned long key)
{
struct dm9000 *priv = (struct dm9000 *)sc->driver_private;
- struct eth_drv_sg *sg = sg_list;
+ struct eth_drv_sg *sg;
cyg_uint8 tmpbuf[4];
- int i, len, extra, n, save_len;
+ int i, len, n, save_len, tail_extra;
char *p;
- if (0) {
- diag_printf("dm9000_send: NCR[%02x] NSR[%02x] TPL[%02x]\n",
- getreg(priv, DM_NCR), getreg(priv, DM_NSR),
- getreg(priv, DM_TRPAL) | (getreg(priv, DM_TRPAH) << 8)
- );
+#ifdef DEBUG
+ diag_printf("dm9000_send: NCR[%02x] NSR[%02x] TRPA[%04x]\n",
+ getreg(priv, DM_NCR), getreg(priv, DM_NSR),
+ getreg(priv, DM_TRPAL) | (getreg(priv, DM_TRPAH) << 8)
+ );
+#endif
+#ifdef DEBUG_DUMP
+ for (sg = sg_list; sg < (sg_list + sg_len); sg++) {
+ diag_printf("\n");
+ diag_dump_buf(sg->buf, sg->len);
}
+#endif
priv->txbusy = 1;
+ sg = sg_list;
save_len = total_len;
- extra = 0;
+ tail_extra = 0;
+
+ /* Disable all interrupts */
+ putreg(priv, DM_IMR, IMR_PAR);
HAL_WRITE_UINT8(priv->io_addr, DM_MWCMD);
len = total_len;
p = (char *)sg->buf;
- if (extra) {
- n = sizeof(tmpbuf) - extra;
- memcpy(tmpbuf + extra, p, n);
- p += n;
- len -= n;
+ /* write any left over partial words by combining them with the start
+ * of this sg block */
+ if (tail_extra) {
+ int head_extra = sizeof(tmpbuf) - tail_extra;
+ memcpy(tmpbuf + tail_extra, p, head_extra);
+ p += head_extra;
+ len -= head_extra;
for (i = 0; i < sizeof(tmpbuf) && total_len > 0; i += n) {
n = priv->write_data(priv, tmpbuf + i);
total_len -= n;
}
- extra = 0;
- }
-
- while (len >= sizeof(tmpbuf) && total_len > 0) {
- n = priv->write_data(priv, p);
- len -= n;
- total_len -= n;
- p += n;
- }
+ tail_extra = 0;
+ }
- if (len > 0 && total_len > 0) {
- extra = len;
- memcpy(tmpbuf, p, extra);
-
- if ((total_len - extra) <= 0) {
- // go ahead and write it now
- for (i = 0; total_len > 0; i += n, total_len -= n) {
- n = priv->write_data(priv, tmpbuf + i);
- total_len = 0;
- }
- break;
- }
- }
- sg++;
+ /* write out whole words */
+ while (len >= priv->buswidth) {
+ n = priv->write_data(priv, p);
+ len -= n;
+ total_len -= n;
+ p += n;
+ }
+
+ /* if we have some left over partial words... */
+ if (len > 0) {
+ /* combine them with the next sg block if available */
+ if (total_len > len ) {
+ tail_extra = len;
+ memcpy(tmpbuf, p, tail_extra);
+ } else {
+ /* otherwise just write this last partial word */
+ n = priv->write_data(priv, p);
+ total_len -= n;
+ }
+ }
+ sg++;
}
priv->txkey = key;
putreg(priv, DM_TCR, TCR_TXREQ);
- return;
+ /* Re-enable interrupt */
+ putreg(priv, DM_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
}
// ------------------------------------------------------------------------
dm9000_poll(struct eth_drv_sc *sc)
{
struct dm9000 *priv = (struct dm9000 *)sc->driver_private;
- cyg_uint8 status, rxstat, rx1;
+ cyg_uint8 status, rxstat;
cyg_uint16 pkt_stat, pkt_len;
int i;
// check for rx done
if (1 /*status & ISR_PRS*/) {
+ cyg_uint8 hdr[4]; /* 4 byte Rx pkt hdr */
+
+ getreg(priv, DM_MRCMDX); /* dummy read */
- rx1 = getreg(priv, DM_MRCMDX);
- HAL_READ_UINT8(priv->io_data, rxstat);
+ HAL_READ_UINT8(priv->io_data, rxstat);
// check for packet ready
if (rxstat == 1) {
- cyg_uint16 u16[2];
- cyg_uint8 *cp;
-
- HAL_WRITE_UINT8(priv->io_addr, DM_MRCMD);
- for (i = 0, cp = (cyg_uint8 *)u16; i < 4; )
- i += priv->read_data(priv, cp + i);
-
- u16[0] = CYG_LE16_TO_CPU(u16[0]);
- u16[1] = CYG_LE16_TO_CPU(u16[1]);
+ HAL_WRITE_UINT8(priv->io_addr, DM_MRCMD);
+ for (i = 0; i < 4;)
+ i += priv->read_data(priv, hdr + i);
-#if (CYG_BYTEORDER == CYG_MSBFIRST)
- pkt_stat = u16[0];
- pkt_len = u16[1];
-#else
- pkt_stat = u16[1];
- pkt_len = u16[0];
-#endif
+ pkt_stat = hdr[0] | (hdr[1] << 8);
+ pkt_len = hdr[2] | (hdr[3] << 8);
#ifdef DEBUG
diag_printf("pkt_stat=%04x pkt_len=%04x\n", pkt_stat, pkt_len);
diag_printf("packet too short: %d (0x%04x)\n", pkt_len, pkt_len);
i = 0;
while (i < pkt_len)
- i += priv->read_data(priv, cp);
+ i += priv->read_data(priv, hdr);
} else if (pkt_len > 1536) {
priv->reset_pending = 1;
diag_printf("packet too long: %d (0x%04x)\n", pkt_len, pkt_len);
diag_printf("bad packet status: 0x%04x\n", pkt_stat);
i = 0;
while (i < pkt_len)
- i += priv->read_data(priv, cp);
+ i += priv->read_data(priv, hdr);
} else {
// receive packet
priv->rxlen = pkt_len;
static void
dm9000_deliver(struct eth_drv_sc *sc)
{
+ struct dm9000 *priv = (struct dm9000 *)sc->driver_private;
+
dm9000_poll(sc);
+
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+ cyg_drv_interrupt_unmask(priv->interrupt);
+#endif
}
// ------------------------------------------------------------------------
static int
dm9000_int_vector(struct eth_drv_sc *sc)
{
- struct dm9000 *priv;
- priv = (struct dm9000 *)sc->driver_private;
+ struct dm9000 *priv = (struct dm9000 *)sc->driver_private;
- return -1;
+ return priv->interrupt;
}
dm9000_ioctl(struct eth_drv_sc *sc, unsigned long key,
void *data, int data_length)
{
+ struct dm9000 *priv = (struct dm9000 *)sc->driver_private;
+ cyg_uint8 *esa = (cyg_uint8 *)data;
+ int i;
+
+ switch (key) {
+#ifdef ETH_DRV_GET_MAC_ADDRESS
+ case ETH_DRV_GET_MAC_ADDRESS:
+ memcpy(esa, priv->mac_address, sizeof(priv->mac_address));
+ return 0;
+#endif
+#ifdef ETH_DRV_SET_MAC_ADDRESS
+ case ETH_DRV_SET_MAC_ADDRESS:
+ for (i = 0; i < sizeof(priv->mac_address); i++) {
+ priv->mac_address[i] = esa[i];
+ putreg(priv, DM_PAR + i, priv->mac_address[i]);
+ }
+#if defined(CYGSEM_DEVS_ETH_DAVICOM_DM9000_WRITE_EEPROM)
+ for (i = 0; i < sizeof(priv->mac_address) / 2; i++)
+ eeprom_write(priv, i, priv->mac_address[2*i] | (priv->mac_address[2*i+1] << 8));
+#else
+ diag_printf("dm9000: eeprom write disabled\n");
+#endif
+ return 0;
+#endif
+ }
+
return -1;
}
//#####DESCRIPTIONBEGIN####
//
// Author(s): Fred Fan
-// Contributors:
+// Contributors:
// Date: 2006-08-23
-// Purpose:
-// Description:
+// Purpose:
+// Description:
//
//####DESCRIPTIONEND####
//
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/hal_io.h>
-
/* The defines of event bits */
#define FEC_EVENT_HBERR 0x80000000
#define FEC_EVENT_BABR 0x40000000
#define FEC_RESET 0x00000001
#define FEC_ETHER_EN 0x00000002
-/* the defins of MII operation */
+/* the defins of MII operation */
#define FEC_MII_ST 0x40000000
#define FEC_MII_OP_OFF 28
#define FEC_MII_OP_MASK 0x03
#define FEC_MII_DATA_OFF 0
#define FEC_MII_DATA_MASK 0x0000FFFF
-#define FEC_MII_FRAME ( FEC_MII_ST | FEC_MII_TA )
+#define FEC_MII_FRAME ( FEC_MII_ST | FEC_MII_TA )
#define FEC_MII_OP(x) ( ((x) & FEC_MII_OP_MASK) << FEC_MII_OP_OFF )
#define FEC_MII_PA(pa) (((pa)& FEC_MII_PA_MASK) << FEC_MII_PA_OFF)
#define FEC_MII_RA(ra) (((ra)& FEC_MII_RA_MASK) << FEC_MII_RA_OFF)
#define FEC_TCR_FDEN 0x00000004
/*the defines of buffer description*/
-#define FEC_BD_RX_NUM 32
+#define FEC_BD_RX_NUM 256
#define FEC_BD_TX_NUM 2
-typedef struct mxc_fec_reg_s
+#ifdef CYGPKG_HAL_ARM_MX25
+/*the defines for MIIGSK */
+
+/* RMII frequency control: 0=50MHz, 1=5MHz */
+#define MIIGSK_CFGR_FRCONT (1 << 6)
+
+/* loopback mode */
+#define MIIGSK_CFGR_LBMODE (1 << 4)
+
+/* echo mode */
+#define MIIGSK_CFGR_EMODE (1 << 3)
+
+/* MII gasket mode field */
+#define MIIGSK_CFGR_IF_MODE_MASK (3 << 0)
+
+/* MMI/7-Wire mode */
+#define MIIGSK_CFGR_IF_MODE_MII (0 << 0)
+
+/* RMII mode */
+#define MIIGSK_CFGR_IF_MODE_RMII (1 << 0)
+
+/* reflects MIIGSK Enable bit (RO) */
+#define MIIGSK_ENR_READY (1 << 2)
+
+/* enable MIGSK (set by default) */
+#define MIIGSK_ENR_EN (1 << 1)
+#endif
+
+typedef struct mxc_fec_reg_s
{
unsigned long res1;
/*0x004*/ unsigned long eir; /* Interrupt Event Register */
/*0x180*/ unsigned long erdsr; /*Pointer to Receive Descriptor Ring*/
/*0x184*/ unsigned long etdsr; /*Pointer to Transmit Descriptor Ring*/
/*0x188*/ unsigned long emrbr; /*Maximum Receive Buffer size*/
+#ifdef CYGPKG_HAL_ARM_MX25
+ unsigned long res13[93];
+/*0x300*/ unsigned short miigsk_cfgr; /* MIIGSK Configuration Register */
+ unsigned short res14[3];
+/*0x308*/ unsigned short miigsk_enr; /* MIIGSK Enable Register */
+#endif
} mxc_fec_reg_t;
#define BD_RX_ST_EMPTY 0x8000
{
unsigned short int length; /*packet size*/
unsigned short int status; /*control & statue of this buffer description*/
- unsigned char * data; /*frame buffer address*/
+ unsigned char *data; /*frame buffer address*/
} mxc_fec_bd_t;
-typedef struct mxc_fec_priv_s
+typedef struct mxc_fec_priv_s
{
- mxc_fec_reg_t * hw_reg; /*the register base address of FEC*/
+ mxc_fec_reg_t *hw_reg; /*the register base address of FEC*/
#ifdef CYGPKG_DEVS_ETH_PHY
eth_phy_access_t *phy;
#else
unsigned char res[2];
unsigned long status; /*the status of FEC device:link-status etc.*/
unsigned long tx_key; /*save the key delivered from send function*/
- mxc_fec_bd_t * rx_bd; /*the receive buffer description ring*/
- mxc_fec_bd_t * rx_cur; /*the next recveive buffer description*/
- mxc_fec_bd_t * tx_bd; /*the transmit buffer description rign*/
- mxc_fec_bd_t * tx_cur; /*the next transmit buffer description*/
- /*TODO: Add interrupt about fields*/
- /*TODO: Add timer about fields*/
+ mxc_fec_bd_t *rx_bd; /*the receive buffer description ring*/
+ mxc_fec_bd_t *rx_cur; /*the next recveive buffer description*/
+ mxc_fec_bd_t *tx_bd; /*the transmit buffer description rign*/
+ mxc_fec_bd_t *tx_cur; /*the next transmit buffer description*/
+ cyg_bool (*provide_esa)(unsigned char *);
} mxc_fec_priv_t;
#define MXC_FEC_PRIVATE(x) ((mxc_fec_priv_t *)(x)->driver_private)
#define FEC_STATUS_100M 0x10000000
/*The defines about PHY */
+#ifndef FEC_PHY_ADDR
#define PHY_PORT_ADDR 0x01
+#else
+#define PHY_PORT_ADDR FEC_PHY_ADDR
+#endif
#define PHY_CTRL_REG 0x00
#define PHY_CTRL_RESET 0x8000
#define PHY_CTRL_AUTO_NEG 0x1000
#define PHY_CTRL_FULL_DPLX 0x0100
-#define PHY_STATUS_REG 0x01
+#define PHY_STATUS_REG 0x01
#define PHY_STATUS_LINK_ST 0x0004
#define PHY_IDENTIFY_1 0x02
#define PHY_DIAG_RATE 0x0400
#define PHY_MODE_REG 0x15
-#define PHY_LED_SEL 0x200
+#define PHY_LED_SEL 0x200
+
+#define PHY_AUTO_NEG_REG 0x5
+#define PHY_AUTO_10BASET 0x20
+#define PHY_AUTO_10BASET_DPLX 0x40
+#define PHY_AUTO_100BASET 0x80
+#define PHY_AUTO_100BASET_DPLX 0x100
+
+#define PHY_AUTO_NEG_EXP_REG 0x6
+#define PHY_AUTO_NEG_NEW_PAGE 0x2
+#define PHY_AUTO_NEG_CAP 0x1
+#define PHY_INT_SRC_REG 29
+#define PHY_INT_AUTO_NEG 0x40
#define FEC_COMMON_TICK 2
#define FEC_COMMON_TIMEOUT (1000*1000)
#define FEC_MII_TICK 2
//
// dev/if_fec.c
//
-// Device driver for FEC
+// Device driver for FEC
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
//#####DESCRIPTIONBEGIN####
//
// Author(s): Fred Fan
-// Contributors:
+// Contributors:
// Date: 2006-08-23
-// Purpose:
+// Purpose:
// Description: Driver for FEC ethernet controller
//
-// Note:
+// Note:
//
//####DESCRIPTIONEND####
//
#include <cyg/io/eth_phy.h>
#endif
+static bool mxc_fec_init(struct cyg_netdevtab_entry *tab);
#include <cyg/io/fec.h>
#define __WANT_DEVS
#ifndef CYGPKG_DEVS_ETH_PHY
/*!
- * Global variable which contains the name of FEC driver and device.
+ * Global variable which contains the name of FEC driver and device.
*/
static char mxc_fec_name[] = "mxc_fec";
/*!
* Global variable which defines the private structure of FEC device.
*/
-static mxc_fec_priv_t mxc_fec_private ;
+static mxc_fec_priv_t mxc_fec_private;
#endif
/*!
- *Global variable which defines the buffer descriptions for receiving frame
+ * Global variable which defines the buffer descriptors for receive frames
* comment:: it must aligned by 128-bits.
*/
-static mxc_fec_bd_t mxc_fec_rx_bd[FEC_BD_RX_NUM] __attribute__ ( ( aligned(32) ) ) ;
+static mxc_fec_bd_t mxc_fec_rx_bd[FEC_BD_RX_NUM] __attribute__ ((aligned(32)));
/*!
- *Global variable which defines the buffer descriptions for receiving frame
+ * Global variable which defines the buffer descriptors for transmit frames
* comment:: it must aligned by 128-bits.
*/
-static mxc_fec_bd_t mxc_fec_tx_bd[FEC_BD_TX_NUM] __attribute__ ( ( aligned(32) ) ) ;
+static mxc_fec_bd_t mxc_fec_tx_bd[FEC_BD_TX_NUM] __attribute__ ((aligned(32)));
/*!
- * Global variable which contains the frame buffers ,
+ * Global variable which contains the frame buffers
*/
-static unsigned char mxc_fec_rx_buf[FEC_BD_RX_NUM][2048] __attribute__ ( ( aligned(32) ) ) ;
+static unsigned char mxc_fec_rx_buf[FEC_BD_RX_NUM][2048] __attribute__ ((aligned(32)));
/*!
- * Global variable which contains the frame buffers ,
+ * Global variable which contains the frame buffers
*/
-static unsigned char mxc_fec_tx_buf[FEC_BD_TX_NUM][2048] __attribute__ ( ( aligned(32) ) ) ;
+static unsigned char mxc_fec_tx_buf[FEC_BD_TX_NUM][2048] __attribute__ ((aligned(32)));
+#if 0
+static void dump_packet (unsigned char *pkt, size_t len)
+{
+ int i;
+
+ diag_printf("Packet dump: %u byte", len);
+ for (i = 0; i < len; i++) {
+ if (i % 16 == 0) {
+ diag_printf("\n%04x:", i);
+ } else {
+ if (i % 4 == 0) {
+ diag_printf(" ");
+ }
+ if (i % 8 == 0) {
+ diag_printf(" ");
+ }
+ }
+ diag_printf(" %02x", pkt[i]);
+ }
+ if (i % 16)
+ diag_printf("\n");
+}
+#endif
+
+#define mxc_fec_reg_read(hw_reg,reg) _mxc_fec_reg_read(&(hw_reg)->reg, #reg)
+static inline unsigned long _mxc_fec_reg_read(volatile unsigned long *addr,
+ const char *reg)
+{
+ unsigned long val = readl(addr);
+
+ if (net_debug) diag_printf("Read %08lx from FEC reg %s[%p]\n",
+ val, reg, addr);
+ return val;
+}
+
+#define mxc_fec_reg_write(hw_reg,reg,val) _mxc_fec_reg_write(&(hw_reg)->reg, val, #reg)
+static inline void _mxc_fec_reg_write(volatile unsigned long *addr,
+ unsigned long val, const char *reg)
+{
+ if (net_debug) diag_printf("Writing %08lx to FEC reg %s[%p]\n",
+ val, reg, addr);
+ writel(val, addr);
+}
+
+#define mxc_fec_reg_read16(hw_reg,reg) _mxc_fec_reg_read16(&(hw_reg)->reg, #reg)
+static inline unsigned short _mxc_fec_reg_read16(volatile unsigned short *addr,
+ const char *reg)
+{
+ unsigned short val = readw(addr);
+
+ if (net_debug) diag_printf("Read %04x from FEC reg %s[%p]\n",
+ val, reg, addr);
+ return val;
+}
+
+#define mxc_fec_reg_write16(hw_reg,reg,val) _mxc_fec_reg_write16(&(hw_reg)->reg, val, #reg)
+static inline void _mxc_fec_reg_write16(volatile unsigned short *addr,
+ unsigned short val, const char *reg)
+{
+ if (net_debug) diag_printf("Writing %04x to FEC reg %s[%p]\n",
+ val, reg, addr);
+ writew(val, addr);
+}
/*!
- * This function get the value of PHY registers by MII interface
+ * This function gets the value of PHY registers via MII interface
*/
static int
mxc_fec_mii_read(volatile mxc_fec_reg_t *hw_reg, unsigned char phy_addr, unsigned char reg_addr,
- unsigned short int *value)
+ unsigned short int *value)
{
unsigned long waiting = FEC_MII_TIMEOUT;
-
+
if (net_debug) diag_printf("%s: Trying to read phy[%02x] reg %04x\n",
__FUNCTION__, phy_addr, reg_addr);
- if (hw_reg->eir & FEC_EVENT_MII) {
+ if (mxc_fec_reg_read(hw_reg, eir) & FEC_EVENT_MII) {
if (net_debug) diag_printf("%s: Clearing EIR_EVENT_MII\n", __FUNCTION__);
- hw_reg->eir = FEC_EVENT_MII ;
+ mxc_fec_reg_write(hw_reg, eir, FEC_EVENT_MII);
}
- if (net_debug) diag_printf("%s: EIR=%08lx\n", __FUNCTION__, hw_reg->eir);
- hw_reg->mmfr = FEC_MII_READ(phy_addr, reg_addr);/*Write CMD*/
+ if (net_debug) diag_printf("%s: EIR=%08lx\n", __FUNCTION__, mxc_fec_reg_read(hw_reg, eir));
+ mxc_fec_reg_write(hw_reg, mmfr, FEC_MII_READ(phy_addr, reg_addr));/* Write CMD */
while (1) {
- if (hw_reg->eir & FEC_EVENT_MII) {
+ if (mxc_fec_reg_read(hw_reg, eir) & FEC_EVENT_MII) {
if (net_debug) diag_printf("%s: Got EIR_EVENT_MII: EIR=%08lx\n",
- __FUNCTION__, hw_reg->eir);
- hw_reg->eir = FEC_EVENT_MII ;
+ __FUNCTION__, mxc_fec_reg_read(hw_reg, eir));
+ mxc_fec_reg_write(hw_reg, eir, FEC_EVENT_MII);
break;
}
if (--waiting == 0) {
diag_printf("%s: Read from PHY at addr %d reg 0x%02x timed out: EIR=%08lx\n",
- __FUNCTION__, phy_addr, reg_addr, hw_reg->eir);
+ __FUNCTION__, phy_addr, reg_addr,
+ mxc_fec_reg_read(hw_reg, eir));
return -1;
}
- hal_delay_us(FEC_MII_TICK);
+ hal_delay_us(FEC_MII_TICK);
}
- *value = FEC_MII_GET_DATA(hw_reg->mmfr);
+ *value = FEC_MII_GET_DATA(mxc_fec_reg_read(hw_reg, mmfr));
if (net_debug) diag_printf("%s: Read %04x from phy[%02x] reg %04x\n", __FUNCTION__,
*value, phy_addr, reg_addr);
return 0;
/*!
* This function set the value of PHY registers by MII interface
*/
-static int
-mxc_fec_mii_write(volatile mxc_fec_reg_t * hw_reg, unsigned char phy_addr, unsigned char reg_addr,
+static int
+mxc_fec_mii_write(volatile mxc_fec_reg_t *hw_reg, unsigned char phy_addr, unsigned char reg_addr,
unsigned short int value)
{
unsigned long waiting = FEC_MII_TIMEOUT;
-
+
if (net_debug) diag_printf("%s: Trying to write %04x to phy[%02x] reg %04x\n", __FUNCTION__,
value, phy_addr, reg_addr);
- if(hw_reg->eir & FEC_EVENT_MII ) {
+ if (mxc_fec_reg_read(hw_reg, eir) & FEC_EVENT_MII) {
if (net_debug) diag_printf("%s: Clearing EIR_EVENT_MII\n", __FUNCTION__);
- hw_reg->eir = FEC_EVENT_MII;
+ mxc_fec_reg_write(hw_reg, eir, FEC_EVENT_MII);
}
- if (net_debug) diag_printf("%s: EIR=%08lx\n", __FUNCTION__, hw_reg->eir);
- hw_reg->mmfr = FEC_MII_WRITE(phy_addr, reg_addr, value);/*Write CMD*/
+ if (net_debug) diag_printf("%s: EIR=%08lx\n", __FUNCTION__, mxc_fec_reg_read(hw_reg, eir));
+ mxc_fec_reg_write(hw_reg, mmfr, FEC_MII_WRITE(phy_addr, reg_addr, value));/* Write CMD */
if (net_debug) diag_printf("%s: Wrote cmd %08x to MMFR\n", __FUNCTION__,
FEC_MII_WRITE(phy_addr, reg_addr, value));
while (1) {
- if (hw_reg->eir & FEC_EVENT_MII) {
+ if (mxc_fec_reg_read(hw_reg, eir) & FEC_EVENT_MII) {
if (net_debug) diag_printf("%s: Got EIR_EVENT_MII: EIR=%08lx\n",
- __FUNCTION__, hw_reg->eir);
- hw_reg->eir = FEC_EVENT_MII ;
+ __FUNCTION__, mxc_fec_reg_read(hw_reg, eir));
+ mxc_fec_reg_write(hw_reg, eir, FEC_EVENT_MII);
break;
}
if (--waiting == 0) {
diag_printf("%s: Write to PHY at addr %d reg 0x%02x timed out: EIR=%08lx\n",
- __FUNCTION__, phy_addr, reg_addr, hw_reg->eir);
+ __FUNCTION__, phy_addr, reg_addr,
+ mxc_fec_reg_read(hw_reg, eir));
return -1;
}
hal_delay_us(FEC_MII_TICK);
}
static void
-mxc_fec_set_mac_address(volatile mxc_fec_reg_t *dev, unsigned char *enaddr)
+mxc_fec_set_mac_address(volatile mxc_fec_reg_t *hw_reg, unsigned char *enaddr)
{
unsigned long value;
-
+
value = enaddr[0];
value = (value << 8) + enaddr[1];
value = (value << 8) + enaddr[2];
value = (value << 8) + enaddr[3];
- dev->palr = value;
-
+ mxc_fec_reg_write(hw_reg, palr, value);
+
value = enaddr[4];
value = (value << 8) + enaddr[5];
- dev->paur = (value << 16);
+ mxc_fec_reg_write(hw_reg, paur, value << 16);
}
/*!
- * This function set the value of PHY registers by MII interface
+ * This function enables the FEC for reception of packets
*/
-static void
+static void
mxc_fec_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags)
{
- mxc_fec_priv_t *priv = sc?sc->driver_private:NULL;
- volatile mxc_fec_reg_t *chip = priv?priv->hw_reg:NULL;
+ mxc_fec_priv_t *priv = sc ? sc->driver_private : NULL;
+ volatile mxc_fec_reg_t *hw_reg = priv ? priv->hw_reg : NULL;
- if (!(priv && chip) || enaddr == NULL ) {
- diag_printf("BUG[start]: MAC address or some fields in driver is NULL\n");
+ if (!(priv && hw_reg)) {
+ diag_printf("BUG[start]: FEC driver not initialized\n");
+ return;
+ }
+ if (enaddr == NULL) {
+ diag_printf("BUG[start]: no MAC address supplied\n");
return;
}
- mxc_fec_set_mac_address(chip, enaddr);
+ mxc_fec_set_mac_address(hw_reg, enaddr);
priv->tx_busy = 0;
- chip->ecr |= FEC_ETHER_EN;
- chip->rdar |= FEC_RX_TX_ACTIVE;
+ mxc_fec_reg_write(hw_reg, rdar, mxc_fec_reg_read(hw_reg, rdar) | FEC_RX_TX_ACTIVE);
+ mxc_fec_reg_write(hw_reg, ecr, mxc_fec_reg_read(hw_reg, ecr) | FEC_ETHER_EN);
+#ifdef CYGPKG_HAL_ARM_MX25
+ /*
+ * setup the MII gasket for RMII mode
+ */
+
+ /* disable the gasket */
+ mxc_fec_reg_write16(hw_reg, miigsk_enr, 0);
+
+ /* wait for the gasket to be disabled */
+ while (mxc_fec_reg_read16(hw_reg, miigsk_enr) & MIIGSK_ENR_READY)
+ hal_delay_us(FEC_COMMON_TICK);
+
+ /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
+ mxc_fec_reg_write16(hw_reg, miigsk_cfgr, MIIGSK_CFGR_IF_MODE_RMII);
+
+ /* re-enable the gasket */
+ mxc_fec_reg_write16(hw_reg, miigsk_enr, MIIGSK_ENR_EN);
+
+ /* wait until MII gasket is ready */
+ int max_loops = 10;
+ while ((mxc_fec_reg_read16(hw_reg, miigsk_enr) & MIIGSK_ENR_READY) == 0) {
+ if (--max_loops <= 0) {
+ diag_printf("WAIT for MII Gasket ready timed out\n");
+ break;
+ }
+ }
+#endif
}
/*!
* This function pauses the FEC controller.
*/
-static void
+static void
mxc_fec_stop(struct eth_drv_sc *sc)
{
- mxc_fec_priv_t *priv = sc?sc->driver_private:NULL;
- volatile mxc_fec_reg_t *chip = priv?priv->hw_reg:NULL;
- if (!(priv && chip)) {
- diag_printf("BUG[stop]: some fields in driver is NULL\n");
+ mxc_fec_priv_t *priv = sc ? sc->driver_private : NULL;
+ volatile mxc_fec_reg_t *hw_reg = priv ? priv->hw_reg : NULL;
+
+ if (!(priv && hw_reg)) {
+ diag_printf("BUG[stop]: FEC driver not initialized\n");
return;
}
- chip->ecr &= ~FEC_ETHER_EN;
+ mxc_fec_reg_write(hw_reg, ecr, mxc_fec_reg_read(hw_reg, ecr) & ~FEC_ETHER_EN);
}
-static int
+static int
mxc_fec_control(struct eth_drv_sc *sc, unsigned long key, void *data, int data_length)
{
/*TODO:: Add support */
/*!
* This function checks the status of FEC control.
*/
-static int
+static int
mxc_fec_can_send(struct eth_drv_sc *sc)
{
- mxc_fec_priv_t *priv = sc?sc->driver_private:NULL;
- volatile mxc_fec_reg_t *hw_reg = priv?priv->hw_reg:NULL;
+ mxc_fec_priv_t *priv = sc ? sc->driver_private : NULL;
+ volatile mxc_fec_reg_t *hw_reg = priv ? priv->hw_reg : NULL;
if (!(priv && hw_reg)) {
- diag_printf("BUG[can_send]:the private pointer and register pointer in MXC_FEC is NULL\n");
+ diag_printf("BUG[can_send]: FEC driver not initialized\n");
return 0;
}
if (priv->tx_busy) {
- diag_printf("WARNING[can_send]: MXC_FEC is busy for transmittinig\n");
+ diag_printf("WARNING[can_send]: MXC_FEC is busy for transmission\n");
return 0;
}
- if (!(hw_reg->ecr & FEC_ETHER_EN)) {
+ if (!(mxc_fec_reg_read(hw_reg, ecr) & FEC_ETHER_EN)) {
diag_printf("WARNING[can_send]: MXC_FEC is not enabled\n");
return 0;
}
- if (hw_reg->tcr & FEC_TCR_RFC_PAUSE) {
+ if (mxc_fec_reg_read(hw_reg, tcr) & FEC_TCR_RFC_PAUSE) {
diag_printf("WARNING[can_send]: MXC_FEC is paused\n");
return 0;
}
/*!
* This function transmits a frame.
*/
-static void
+static void
mxc_fec_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len, int total,
- unsigned long key)
+ unsigned long key)
{
- mxc_fec_priv_t *dev = sc?sc->driver_private:NULL;
- volatile mxc_fec_reg_t *hw_reg = dev?dev->hw_reg:NULL;
+ mxc_fec_priv_t *dev = sc ? sc->driver_private : NULL;
+ volatile mxc_fec_reg_t *hw_reg = dev ? dev->hw_reg : NULL;
mxc_fec_bd_t *p;
int i, off;
- if ( dev == NULL || hw_reg == NULL) {
- diag_printf("BUG[TX]: some fields in driver are NULL\n");
+ if (dev == NULL || hw_reg == NULL) {
+ diag_printf("BUG[TX]: FEC driver not initialized\n");
return;
}
- if ( total > (FEC_FRAME_LEN-4)) total = FEC_FRAME_LEN-4;
- if ( sg_list == NULL || total <= 14 ) {
- if(sc->funs->eth_drv && sc->funs->eth_drv->tx_done) {
+ if (total > (FEC_FRAME_LEN - 4)) total = FEC_FRAME_LEN - 4;
+ if (sg_list == NULL || total <= 14) {
+ if (sc->funs->eth_drv && sc->funs->eth_drv->tx_done) {
sc->funs->eth_drv->tx_done(sc, key, -1);
}
return;
- }
+ }
- for(i=0, off=0, p = dev->tx_cur; i<sg_len; i++) {
+ for (i = 0, off = 0, p = dev->tx_cur; i < sg_len; i++) {
unsigned long vaddr;
- if(p->status & BD_TX_ST_RDY) {
- diag_printf("BUG[TX]:MXC_FEC's status=%x\n", p->status);
+
+ if (p->status & BD_TX_ST_RDY) {
+ diag_printf("BUG[TX]: trying to resend already finished buffer\n");
break;
}
if (sg_list[i].buf == 0) {
memcpy((void *)vaddr, (void *)sg_list[i].buf, sg_list[i].len);
off += sg_list[i].len;
}
- if ( off < 14 ) {
- diag_printf("WARNING[TX]: data len is %d\n", off);
+ if (off < 14) {
+ diag_printf("WARNING[TX]: packet size %d too small\n", off);
return;
}
- p->length = off;
- p->status &= ~(BD_TX_ST_LAST|BD_TX_ST_RDY|BD_TX_ST_TC|BD_TX_ST_ABC);
- p->status |= BD_TX_ST_LAST| BD_TX_ST_RDY | BD_TX_ST_TC;
- if(p->status & BD_TX_ST_WRAP ) {
+ p->length = off;
+ //p->status &= ~(BD_TX_ST_LAST | BD_TX_ST_RDY | BD_TX_ST_TC | BD_TX_ST_ABC);
+ p->status &= ~BD_TX_ST_ABC;
+ p->status |= BD_TX_ST_LAST | BD_TX_ST_RDY | BD_TX_ST_TC;
+ if (p->status & BD_TX_ST_WRAP) {
p = dev->tx_bd;
- } else p++;
+ } else {
+ p++;
+ }
dev->tx_cur = p;
dev->tx_busy = 1;
dev->tx_key = key;
- hw_reg->tdar = FEC_RX_TX_ACTIVE;
+ mxc_fec_reg_write(hw_reg, tdar, FEC_RX_TX_ACTIVE);
}
/*!
* This function receives ready Frame in DB.
*/
-static void
+static void
mxc_fec_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len)
{
- mxc_fec_priv_t * priv = sc?sc->driver_private:NULL;
- mxc_fec_bd_t * p;
+ mxc_fec_priv_t *priv = sc ? sc->driver_private : NULL;
+ mxc_fec_bd_t *p;
unsigned long vaddr;
- if(sg_list == NULL || priv == NULL || sg_len <= 0) {
- diag_printf("BUG[RX]: driver's private field or argument of this calling is NULL \n");
+
+ if (sg_list == NULL || priv == NULL || sg_len <= 0) {
+ diag_printf("BUG[RX]: FEC driver not initialized\n");
return;
}
-
- /*TODO: I think if buf pointer is NULL, this function
+
+ /*TODO: I think if buf pointer is NULL, this function
* should not be called
*/
- if(sg_list->buf == 0) {
+ if (sg_list->buf == 0) {
diag_printf("WARING[RX]: the sg_list is empty\n");
return;
}
p = priv->rx_cur;
-
- if(p->status & BD_RX_ST_EMPTY) {
- diag_printf("BUG[RX]: status =%x\n", p->status);
+
+ if (p->status & BD_RX_ST_EMPTY) {
+ diag_printf("BUG[RX]: empty buffer received; status=%04x\n", p->status);
return;
}
- if(!(p->status & BD_RX_ST_LAST)) {
- diag_printf("BUG[RX]: status =%x\n", p->status);
+ if (!(p->status & BD_RX_ST_LAST)) {
+ diag_printf("BUG[RX]: status=%0xx\n", p->status);
return;
}
vaddr = hal_ioremap_nocache((unsigned long)p->data);
/*TODO::D_CACHE invalid this data buffer*/
- memcpy((void *)sg_list->buf, (void *)vaddr, p->length -4);
+ memcpy((void *)sg_list->buf, (void *)vaddr, p->length - 4);
}
-static void
+static void
mxc_fec_deliver(struct eth_drv_sc *sc)
{
- /*TODO::When redboot support thread ,
+ /*TODO::When redboot support thread ,
* the polling function will be called at here
*/
return;
}
-static void
-mxc_fec_check_rx_bd(struct eth_drv_sc * sc)
+/* This funtion just called by polling funtion */
+static void
+mxc_fec_check_rx_bd(struct eth_drv_sc *sc)
{
- /* This funtion just called by polling funtion*/
- mxc_fec_priv_t * priv = sc->driver_private;
- mxc_fec_bd_t * p;
- volatile mxc_fec_reg_t * hw_reg = priv->hw_reg;
+ mxc_fec_priv_t *priv = sc->driver_private;
+ mxc_fec_bd_t *p;
+ volatile mxc_fec_reg_t *hw_reg = priv->hw_reg;
int i;
-
- for(i = 0, p = priv->rx_cur; i< FEC_RX_FRAMES; i++){
- /*TODO::D-CACHE invalid this BD.
- *In WRITE_BACK mode: this maybe destroy the next BD
- * when the CACHE_LINE write back.
- */
- if(p->status & BD_RX_ST_EMPTY) {
+
+ for (i = 0, p = priv->rx_cur; i < FEC_RX_FRAMES; i++) {
+ /*
+ * TODO::D-CACHE invalidate this BD.
+ * In WRITE_BACK mode: this may destroy the next BD
+ * when the CACHE_LINE is written back.
+ */
+ if (p->status & BD_RX_ST_EMPTY) {
break;
}
- if(!(p->status & BD_RX_ST_LAST)) {
- diag_printf("BUG[RX]: status=%x, length=%x\n", p->status, p->length);
+ if (!(p->status & BD_RX_ST_LAST)) {
+ diag_printf("BUG[RX]: status=%04x, length=%x\n", p->status, p->length);
goto skip_next;
}
-
- if((p->status & BD_RX_ST_ERRS)|| (p->length > FEC_FRAME_LEN)) {
- diag_printf("BUG[RX]: status=%x, length=%x\n", p->status, p->length);
+
+ if (p->status & BD_RX_ST_ERRS) {
+ diag_printf("RX error: status=%08x errors=%08x\n", p->status,
+ p->status & BD_RX_ST_ERRS);
+ } else if (p->length > FEC_FRAME_LEN) {
+ diag_printf("RX error: packet size 0x%08x larger than max frame length: 0x%08x\n",
+ p->length, FEC_FRAME_LEN);
} else {
- sc->funs->eth_drv->recv(sc, p->length -4);
+ sc->funs->eth_drv->recv(sc, p->length - 4);
}
skip_next:
p->status = (p->status & BD_RX_ST_WRAP) | BD_RX_ST_EMPTY;
-
- if ( p->status & BD_RX_ST_WRAP) {
+
+ if (p->status & BD_RX_ST_WRAP) {
p = priv->rx_bd;
} else {
p++;
- }
- priv->rx_cur = p;
- hw_reg->ecr |= FEC_ETHER_EN;
- hw_reg->rdar |= FEC_RX_TX_ACTIVE;
+ }
+ priv->rx_cur = p;
+ mxc_fec_reg_write(hw_reg, rdar, mxc_fec_reg_read(hw_reg, rdar) | FEC_RX_TX_ACTIVE);
}
}
/*!
* This function checks the event of FEC controller
*/
-static void
-mxc_fec_poll(struct eth_drv_sc * sc)
+static void
+mxc_fec_poll(struct eth_drv_sc *sc)
{
- mxc_fec_priv_t * priv = sc?sc->driver_private:NULL;
- volatile mxc_fec_reg_t * hw_reg = priv?priv->hw_reg:NULL;
- unsigned long value;
+ mxc_fec_priv_t *priv = sc ? sc->driver_private : NULL;
+ volatile mxc_fec_reg_t *hw_reg = priv ? priv->hw_reg : NULL;
+ unsigned long value;
+ int dbg = net_debug;
- if ( priv == NULL || hw_reg == NULL) {
- diag_printf("BUG[POLL]: some fields in driver are NULL\n");
+ if (priv == NULL || hw_reg == NULL) {
+ diag_printf("BUG[POLL]: FEC driver not initialized\n");
return;
}
- value = hw_reg->eir;
- hw_reg->eir = value & (~FEC_EVENT_MII);
-
- if(value&FEC_EVENT_TX_ERR) {
- diag_printf("WARNING[POLL]: There are errors(%lu) for transmit\n",
- value&FEC_EVENT_TX_ERR);
+#if 1
+ net_debug = 0;
+#endif
+ value = mxc_fec_reg_read(hw_reg, eir);
+ mxc_fec_reg_write(hw_reg, eir, value & ~FEC_EVENT_MII);
+#if 1
+ net_debug = dbg;
+#endif
+ if (value & FEC_EVENT_TX_ERR) {
+ diag_printf("WARNING[POLL]: Transmit error\n");
sc->funs->eth_drv->tx_done(sc, priv->tx_key, -1);
priv->tx_busy = 0;
} else {
- if(value&FEC_EVENT_TX) {
- sc->funs->eth_drv->tx_done(sc, priv->tx_key, 0);
+ if (value & FEC_EVENT_TX) {
+ sc->funs->eth_drv->tx_done(sc, priv->tx_key, 0);
priv->tx_busy = 0;
}
}
-
- if(value&FEC_EVENT_RX) {
+
+ if (value & FEC_EVENT_RX) {
mxc_fec_check_rx_bd(sc);
}
- if(value & FEC_EVENT_HBERR) {
+ if (value & FEC_EVENT_HBERR) {
diag_printf("WARNGING[POLL]: Hearbeat error!\n");
}
- if(value & FEC_EVENT_EBERR) {
+ if (value & FEC_EVENT_EBERR) {
diag_printf("WARNING[POLL]: Ethernet Bus Error!\n");
}
}
-
static int
mxc_fec_int_vector(struct eth_drv_sc *sc)
{
/*TODO::
- * get FEC interrupt number
+ * get FEC interrupt number
*/
return -1;
}
* The function initializes the description buffer for receiving or transmitting
*/
static void
-mxc_fec_bd_init(mxc_fec_priv_t * dev)
+mxc_fec_bd_init(mxc_fec_priv_t *dev)
{
int i;
- mxc_fec_bd_t * p;
+ mxc_fec_bd_t *p;
p = dev->rx_bd = (void *)hal_ioremap_nocache(hal_virt_to_phy((unsigned long)mxc_fec_rx_bd));
- for(i=0; i<FEC_BD_RX_NUM; i++, p++){
+ for (i = 0; i < FEC_BD_RX_NUM; i++, p++) {
p->status = BD_RX_ST_EMPTY;
p->length = 0;
p->data = (void *)hal_virt_to_phy((unsigned long)mxc_fec_rx_buf[i]);
}
- dev->rx_bd[i-1].status |= BD_RX_ST_WRAP;
+ dev->rx_bd[i - 1].status |= BD_RX_ST_WRAP;
dev->rx_cur = dev->rx_bd;
- p = dev->tx_bd = (void *)hal_ioremap_nocache(hal_virt_to_phy((unsigned long)mxc_fec_tx_bd));
- for(i=0; i<FEC_BD_TX_NUM; i++, p++){
- p->status = 0;
- p->length = 0;
- p->data = (void *)hal_virt_to_phy((unsigned long)mxc_fec_tx_buf[i]);
- }
+ p = dev->tx_bd = (void *)hal_ioremap_nocache(hal_virt_to_phy((unsigned long)mxc_fec_tx_bd));
+ for (i = 0; i < FEC_BD_TX_NUM; i++, p++) {
+ p->status = 0;
+ p->length = 0;
+ p->data = (void *)hal_virt_to_phy((unsigned long)mxc_fec_tx_buf[i]);
+ }
- dev->tx_bd[i-1].status |= BD_TX_ST_WRAP;
+ dev->tx_bd[i - 1].status |= BD_TX_ST_WRAP;
dev->tx_cur = dev->tx_bd;
-
+
/*TODO:: add the sync function for items*/
}
/*!
- *This function initializes FEC controller.
+ *This function initializes FEC controller.
*/
-static void
-mxc_fec_chip_init(mxc_fec_priv_t * dev)
+static void
+mxc_fec_chip_init(mxc_fec_priv_t *dev)
{
- volatile mxc_fec_reg_t * chip = dev->hw_reg;
+ volatile mxc_fec_reg_t *hw_reg = dev->hw_reg;
unsigned long ipg_clk;
- chip->ecr = FEC_RESET;
- while(chip->ecr & FEC_RESET) {
+ mxc_fec_reg_write(hw_reg, ecr, mxc_fec_reg_read(hw_reg, ecr) | FEC_RESET);
+ while (mxc_fec_reg_read(hw_reg, ecr) & FEC_RESET) {
hal_delay_us(FEC_COMMON_TICK);
}
- chip->eimr = 0x00000000;
- chip->eir = 0xFFFFFFFF;
-
- chip->rcr = (chip->rcr&~(0x0000003F))|FEC_RCR_FCE|FEC_RCR_MII_MODE;
- chip->tcr |= FEC_TCR_FDEN;
- chip->mibc |= FEC_MIB_DISABLE;
-
- chip->iaur = 0;
- chip->ialr = 0;
- chip->gaur = 0;
- chip->galr = 0;
+ mxc_fec_reg_write(hw_reg, eimr, 0);
+ mxc_fec_reg_write(hw_reg, eir, ~0);
+
+ mxc_fec_reg_write(hw_reg, rcr,
+ (mxc_fec_reg_read(hw_reg, rcr) & ~0x3F) |
+ FEC_RCR_FCE | FEC_RCR_MII_MODE);
+
+ mxc_fec_reg_write(hw_reg, tcr, mxc_fec_reg_read(hw_reg, tcr) | FEC_TCR_FDEN);
+ mxc_fec_reg_write(hw_reg, mibc, mxc_fec_reg_read(hw_reg, mibc) | FEC_MIB_DISABLE);
+
+ mxc_fec_reg_write(hw_reg, iaur, 0);
+ mxc_fec_reg_write(hw_reg, ialr, 0);
+ mxc_fec_reg_write(hw_reg, gaur, 0);
+ mxc_fec_reg_write(hw_reg, galr, 0);
- /*TODO:: Use MII_SPEED(IPG_CLK) to get the value*/
ipg_clk = get_main_clock(IPG_CLK);
-
- chip->mscr = (chip->mscr & 0x7e) | (((ipg_clk + 499999) / 2500000 / 2) << 1);
- if (net_debug) diag_printf("mscr set to %08lx for ipg_clk %ld\n", chip->mscr,
- ipg_clk);
- /*Enable ETHER_EN*/
- chip->emrbr = 2048-16;
- chip->erdsr = hal_virt_to_phy((unsigned long)dev->rx_bd);
- chip->etdsr = hal_virt_to_phy((unsigned long)dev->tx_bd);
+
+ mxc_fec_reg_write(hw_reg, mscr,
+ (mxc_fec_reg_read(hw_reg, mscr) & ~0x7e) |
+ (((ipg_clk + 499999) / 2500000 / 2) << 1));
+ if (net_debug) diag_printf("mscr set to %08lx for ipg_clk %ld\n",
+ mxc_fec_reg_read(hw_reg, mscr), ipg_clk);
+
+ mxc_fec_reg_write(hw_reg, emrbr, 2048 - 16);
+ mxc_fec_reg_write(hw_reg, erdsr, hal_virt_to_phy((unsigned long)dev->rx_bd));
+ mxc_fec_reg_write(hw_reg, etdsr, hal_virt_to_phy((unsigned long)dev->tx_bd));
+
+ /* must be done before enabling the MII gasket
+ * (otherwise MIIGSK_ENR_READY will never assert)
+ */
+ mxc_fec_reg_write(hw_reg, ecr, mxc_fec_reg_read(hw_reg, ecr) | FEC_ETHER_EN);
}
static void mxc_fec_phy_status(mxc_fec_priv_t *dev, unsigned short value, bool show)
return;
}
if (dev->status & FEC_STATUS_LINK_ON) {
- diag_printf("FEC: [ %s ] [ %s ]:\n",
+ diag_printf("FEC: [ %s ] [ %s ]:\n",
(dev->status & FEC_STATUS_FULL_DPLX) ? "FULL_DUPLEX" : "HALF_DUPLEX",
(dev->status & FEC_STATUS_100M) ? "100 Mbps" : "10 Mbps");
} else {
#ifndef CYGPKG_DEVS_ETH_PHY
/*!
- * This function initialize PHY
+ * This function initializes the PHY
*/
static bool
mxc_fec_phy_init(mxc_fec_priv_t *dev)
{
+#if 1
unsigned short value = 0;
- unsigned long timeout=FEC_COMMON_TIMEOUT;
+ unsigned long timeout = FEC_COMMON_TIMEOUT;
+
/*Reset PHY*/
mxc_fec_mii_write(dev->hw_reg, dev->phy_addr, PHY_CTRL_REG, PHY_CTRL_RESET);
while (timeout--) {
return false;
}
- if(!(value & PHY_CTRL_RESET)) {
+ if (!(value & PHY_CTRL_RESET)) {
if (net_debug) diag_printf("%s: FEC reset completed\n", __FUNCTION__);
break;
}
id = (value & PHY_ID1_MASK) << PHY_ID1_SHIFT;
mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_IDENTIFY_2, &value);
id |= (value & PHY_ID2_MASK) << PHY_ID2_SHIFT;
- if( id == 0 || id == 0xffffffff) {
+ if (id == 0 || id == 0xffffffff) {
diag_printf("FEC could not identify PHY: ID=%08lx\n", id);
return false;
}
hal_delay_us(FEC_MII_TICK);
}
mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_MODE_REG, &value);
- value &= ~(PHY_LED_SEL);
+ value &= ~PHY_LED_SEL;
mxc_fec_mii_write(dev->hw_reg, dev->phy_addr, PHY_MODE_REG, value);
+#else
+ unsigned long value = 0;
+ unsigned long id = 0, timeout = 50;
+
+ mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_IDENTIFY_1, &value);
+ id = (value & PHY_ID1_MASK) << PHY_ID1_SHIFT;
+ mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_IDENTIFY_2, &value);
+ id |= (value & PHY_ID2_MASK) << PHY_ID2_SHIFT;
+
+ switch (id) {
+ case 0x00540088:
+ break;
+ case 0x00007C0C:
+ break;
+ default:
+ diag_printf("[Warning] FEC not connect right PHY: ID=%lx\n", id);
+ }
+
+ mxc_fec_mii_write(dev->hw_reg, dev->phy_addr, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG|PHY_CTRL_FULL_DPLX);
+
+#ifdef CYGPKG_HAL_ARM_MX27ADS
+ mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_MODE_REG, &value);
+ value &= ~PHY_LED_SEL;
+ mxc_fec_mii_write(dev->hw_reg, dev->phy_addr, PHY_MODE_REG, value);
+#endif
+
+#if defined(CYGPKG_HAL_ARM_MX51) || defined (CYGPKG_HAL_ARM_MX25_3STACK) || defined (CYGPKG_HAL_ARM_MX35_3STACK) || defined (CYGPKG_HAL_ARM_MX27_3STACK)
+ mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_AUTO_NEG_EXP_REG, &value);
+ /* Wait for packet to arrive */
+ while (((value & PHY_AUTO_NEG_NEW_PAGE) == 0) && (timeout != 0)) {
+ hal_delay_us(100);
+ mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_AUTO_NEG_EXP_REG, &value);
+ timeout--;
+ }
+ /* Check if link is capable of auto-negotiation */
+ if ((value & PHY_AUTO_NEG_CAP) == 1) {
+ mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_INT_SRC_REG, &value);
+ timeout = 50;
+ /* Wait for auto-negotiation to complete */
+ while (((value & PHY_INT_AUTO_NEG) == 0) && (timeout != 0)) {
+ hal_delay_us(100);
+ mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_INT_SRC_REG, &value);
+ timeout--;
+ }
+ }
+#endif
+ mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_STATUS_REG, &value);
+ if (value & PHY_STATUS_LINK_ST) {
+ dev->status |= FEC_STATUS_LINK_ON;
+ } else {
+ dev->status &= ~FEC_STATUS_LINK_ON;
+ }
+
+#ifdef CYGPKG_HAL_ARM_MX27ADS
+ mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_DIAG_REG, &value);
+ if (value & PHY_DIAG_DPLX) {
+ dev->status |= FEC_STATUS_FULL_DPLX;
+ } else {
+ dev->status &= ~FEC_STATUS_FULL_DPLX;
+ }
+ if (value & PHY_DIAG_DPLX) {
+ dev->status |= FEC_STATUS_100M;
+ } else {
+ dev->status &= ~FEC_STATUS_100M;
+ }
+#endif
+
+#if defined(CYGPKG_HAL_ARM_MX51) || defined (CYGPKG_HAL_ARM_MX25_3STACK) || defined (CYGPKG_HAL_ARM_MX35_3STACK)
+ mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_AUTO_NEG_REG, &value);
+ if (value & PHY_AUTO_10BASET) {
+ dev->status &= ~FEC_STATUS_100M;
+ if (value & PHY_AUTO_10BASET_DPLX) {
+ dev->status |= FEC_STATUS_FULL_DPLX;
+ } else {
+ dev->status &= ~FEC_STATUS_FULL_DPLX;
+ }
+ }
+ if (value & PHY_AUTO_100BASET) {
+ dev->status |= FEC_STATUS_100M;
+ if (value & PHY_AUTO_100BASET_DPLX) {
+ dev->status |= FEC_STATUS_FULL_DPLX;
+ } else {
+ dev->status &= ~FEC_STATUS_FULL_DPLX;
+ }
+ }
+#endif
+ diag_printf("FEC: [ %s ] [ %s ] [ %s ]:\n",
+ (dev->status&FEC_STATUS_FULL_DPLX)?"FULL_DUPLEX":"HALF_DUPLEX",
+ (dev->status&FEC_STATUS_LINK_ON)?"connected":"disconnected",
+ (dev->status&FEC_STATUS_100M)?"100M bps":"10M bps");
+#endif
return true;
}
}
if (id == 0) {
/* Disable MII */
- fep->hw_reg->mscr = 0;
+ fep->mxc_fec_reg_write(hw_reg, mscr, 0);
ret = -1;
}
unsigned long timeout=FEC_COMMON_TIMEOUT;
mxc_fec_priv_t *dev = &mxc_fec_private;
- /*Reset PHY*/
+ /* Reset PHY */
if (net_debug) diag_printf("%s\n", __FUNCTION__);
_eth_phy_write(dev->phy, PHY_CTRL_REG, dev->phy->phy_addr, PHY_CTRL_RESET);
return;
}
- if(!(value & PHY_CTRL_RESET)) {
+ if (!(value & PHY_CTRL_RESET)) {
if (net_debug) diag_printf("%s: FEC reset completed\n", __FUNCTION__);
break;
}
mxc_fec_mii_write(mxc_fec_private.hw_reg, unit, reg, data);
}
-/*! This function initializes the FEC driver.
+/*! This function initializes the FEC driver.
* It is called by net_init in net module of RedBoot during RedBoot init
*/
-static bool
+static bool
mxc_fec_init(struct cyg_netdevtab_entry *tab)
{
- struct eth_drv_sc * sc = tab ? tab->device_instance : NULL;
- mxc_fec_priv_t * private;
- char eth_add_local[6] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+ struct eth_drv_sc *sc = tab ? tab->device_instance : NULL;
+ mxc_fec_priv_t *private;
+ unsigned char eth_add_local[ETHER_ADDR_LEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+ int ok = 0;
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
cyg_bool set_esa;
- int ok;
-
- /* Get MAC address */
- ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
- "fec_esa", &set_esa, CONFIG_BOOL);
- if (ok && set_esa) {
- CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
- "fec_esa_data", eth_add_local, CONFIG_ESA);
- }
#endif
+
if (net_debug) diag_printf("%s:\n", __FUNCTION__);
- if (sc == NULL){
+ if (sc == NULL) {
diag_printf("%s: no driver attached\n", __FUNCTION__);
return false;
- }
-
+ }
+
private = MXC_FEC_PRIVATE(sc);
if (private == NULL) {
- private = MXC_FEC_PRIVATE(sc) = &mxc_fec_private;
+ private = &mxc_fec_private;
+ }
+ if (private->provide_esa) {
+ ok = private->provide_esa(eth_add_local);
+ }
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+ if (!ok) {
+ /* Get MAC address from fconfig */
+ ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+ "fec_esa", &set_esa, CONFIG_BOOL);
+ if (ok && set_esa) {
+ CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+ "fec_esa_data", eth_add_local, CONFIG_ESA);
+ }
+ }
+#endif
+ if (!ok) {
+ diag_printf("No ESA provided via fuses or RedBoot config\n");
+ return false;
}
private->hw_reg = (void *)SOC_FEC_BASE;
}
private->phy_addr = ok;
mxc_fec_phy_init(private);
-#endif
- /*TODO:: initialize System Resource : irq, timer */
+#endif
+ /* TODO:: initialize System Resource : irq, timer */
sc->funs->eth_drv->init(sc, eth_add_local);
mxc_fec_phy_status(private, _eth_phy_state(private->phy), true);
-
- return true;
+
+ return true;
}
#ifndef CYGPKG_DEVS_ETH_PHY
/*!
- * Global variable which defines the FEC driver,
+ * Global variable which defines the FEC driver,
*/
ETH_DRV_SC(mxc_fec_sc,
- &mxc_fec_private, // Driver specific data
+ &mxc_fec_private, // Driver specific data
mxc_fec_name,
mxc_fec_start,
mxc_fec_stop,
mxc_fec_name,
mxc_fec_init,
&mxc_fec_sc);
-#endif
+
+#endif // CYGPKG_DEVS_ETH_PHY
+2007-06-12 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/if_i82559.c (eth_dsr): Fixed the previous change which broken
+ linkage under some conditions.
+
+2006-11-23 David Fernandez <dfernandez@cct.co.uk>
+
+ * src/if_i82559.c Modifications to remove compile warnings.
+
2005-01-22 Andrew Lunn <andrew.lunn@ascom.ch>
* src/if_i82559.c Added string.h to remove compiler warnings.
CYGACC_CALL_IF_SET_CONSOLE_COMM(_cur_console); \
} /* END BLOCK */
-void CheckRxRing(struct i82559* p_i82559, char * func, int line);
+void CheckRxRing(struct i82559* p_i82559, const char * func, int line);
// ------------------------------------------------------------------------
// Check on the environment.
static void i82559_reset(struct i82559* p_i82559);
static void i82559_restart(struct i82559 *p_i82559);
-static int eth_set_mac_address(struct i82559* p_i82559, char *addr, int eeprom );
+static int eth_set_mac_address(struct i82559* p_i82559, cyg_uint8 *addr, int eeprom );
static void InitRxRing(struct i82559* p_i82559);
static void ResetRxRing(struct i82559* p_i82559);
static void InitTxRing(struct i82559* p_i82559);
static void ResetTxRing(struct i82559* p_i82559);
+#if defined(CYGHWR_DEVS_ETH_INTEL_I82559_MISSED_INTERRUPT) || \
+ defined(CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT) || \
+ !defined(CYGPKG_IO_ETH_DRIVERS_STAND_ALONE)
static void
eth_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data);
+#endif
static cyg_uint32
eth_isr(cyg_vector_t vector, cyg_addrword_t data);
}
static int
-read_eeprom_esa(struct i82559 *p_i82559, char *addr)
+read_eeprom_esa(struct i82559 *p_i82559, cyg_uint8 *addr)
{
int addr_length, i, count;
cyg_uint16 checksum;
//
// ------------------------------------------------------------------------
void
-CheckRxRing(struct i82559* p_i82559, char * func, int line)
+CheckRxRing(struct i82559* p_i82559, const char * func, int line)
{
RFD *p_rfd;
int i;
// ------------------------------------------------------------------------
+#if defined(CYGHWR_DEVS_ETH_INTEL_I82559_MISSED_INTERRUPT) || \
+ defined(CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT) || \
+ !defined(CYGPKG_IO_ETH_DRIVERS_STAND_ALONE)
static void
eth_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
# endif
#endif
}
+#endif
// ------------------------------------------------------------------------
// Deliver routine:
// non0 = It failed.
// ------------------------------------------------------------------------
static int
-eth_set_mac_address(struct i82559* p_i82559, char *addr, int eeprom)
+eth_set_mac_address(struct i82559* p_i82559, cyg_uint8 *addr, int eeprom)
{
cyg_uint32 ioaddr;
cyg_uint16 status;
* src/if_dp83816.c: Enable start/stop functions (device was always
enabled once configured before)
+2004-05-14 Nick Garnett <nickg@ecoscentric.com>
+
+ * src/if_dp83816.c (dp83816_init): Make ESA diag_printf()
+ controlled by DEBUG flag.
+ (dp83816_init):
+ (dp83816_poll): Fixed interrupt enable, masking and acknowledges
+ so that the driver correctly handles Ctrl-C interrupts in RedBoot.
+
+2004-05-13 Nick Garnett <nickg@ecoscentric.com>
+
+ * src/if_dp83816.c (dp83816_poll): Removed test for locked up
+ transmit engine. This test triggers in otherwise normal situations
+ and the warm reset messes things up a lot in both the driver and
+ network stack.
+ (dp83816_recv): Avoid memcpy() when passed a NULL buffer, this can
+ happen when the stack runs out of MBUFs.
+
2003-10-14 Gary Thomas <gary@mlbassoc.com>
* src/if_dp83816.c (dp83816_poll): Try to better detect condition
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2004 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2003 Gary Thomas
+// Copyright (C) 2004 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// 2 for added data IO output: get_reg, put_reg
// 4 for packet allocation/free output
// 8 for only startup status, so we can tell we're installed OK
-#define DEBUG 0x0
-
+#define DEBUG 0
+__externC int norecurse;
#if DEBUG & 1
-#define DEBUG_FUNCTION() do { diag_printf("%s\n", __FUNCTION__); } while (0)
+#define DEBUG_FUNCTION() do { if (!norecurse) { norecurse=1; diag_printf("%s\n", __FUNCTION__); norecurse=0;}} while (0)
#define DEBUG_LINE() do { diag_printf("%d\n", __LINE__); } while (0)
#else
#define DEBUG_FUNCTION() do {} while(0)
// ------------------------------------------------------------------------
// Buffer descriptors
typedef struct dp83816_bd {
- struct dp83816_bd *next; // Next descriptor
- unsigned long stat; // Buffer status & flags
- unsigned char *buf; // Buffer memory
- unsigned long key; // Internal use only
+ volatile struct dp83816_bd *next; // Next descriptor
+ volatile unsigned long stat; // Buffer status & flags
+ volatile unsigned char *buf; // Buffer memory
+ volatile unsigned long key; // Internal use only
} dp83816_bd_t;
// ------------------------------------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2003, 2004 Gary Thomas
+// Copyright (C) 2004 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
#include <cyg/hal/hal_if.h>
#include <cyg/io/eth/eth_drv.h>
#include <cyg/io/eth/netdev.h>
+#include <string.h> // memcpy
#include "dp83816.h"
#include CYGDAT_DEVS_ETH_NS_DP83816_INL
+#if DEBUG & 1
+int norecurse;
+#endif
+
#ifdef CYGHWR_NS_DP83816_USE_EEPROM
static cyg_uint16 dp83816_eeprom_read(struct dp83816_priv_data *dp, int location);
#endif
diag_printf("DP83816 - reset timed out! - stat: %x\n", stat);
return false;
}
+
// Rx ring
bdp = dp->rxnext = CYGARC_UNCACHED_ADDRESS(dp->rxd);
bp = dp->rxbuf;
bdp--; bdp->next = (dp83816_bd_t *)CYG_CPU_TO_LE32(CYGARC_PHYSICAL_ADDRESS(dp->txd));
DP_OUT(dp->base, DP_TXCFG, _TXCFG_ATP |
_TXCFG_MXDMA_128 |
+ /* _TXCFG_CSI | */
((256/32)<<_TXCFG_FLTH_SHIFT) |
((512/32)<<_TXCFG_DRTH_SHIFT));
DP_OUT(dp->base, DP_TXDP, CYGARC_PHYSICAL_ADDRESS(dp->txd));
struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
dp83816_priv_data_t *dp = (dp83816_priv_data_t *)sc->driver_private;
cyg_uint8 *base;
- bool esa_ok;
+ bool esa_ok = false;
unsigned char enaddr[6];
DEBUG_FUNCTION();
base = dp->base;
if (!base) return false; // No device found
+#ifdef CYGPKG_REDBOOT
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+ esa_ok = flash_get_config(dp->esa_key, enaddr, CONFIG_ESA);
+#endif
+#elif defined (CONFIG_ESA)
+ esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+ dp->esa_key, enaddr, CONFIG_ESA);
+#endif
// Get physical device address
-#ifdef CYGHWR_NS_DP83816_USE_EEPROM
+ // There are two different implementations due to parallel implementations.
+ // Both are included for backward compatibility, but
+ // the CYGHWR_DEVS_ETH_NS_DP83816_USE_EEPROM_ESA implementation is
+ // preferred simply because it is smaller.
+#if defined(CYGHWR_DEVS_ETH_NS_DP83816_USE_EEPROM_ESA)
+ if (!esa_ok)
+ {
+ // Read the ESA from the PMATCH receive filter register, which
+ // will have been initialised from the EEPROM.
+ cyg_uint32 rfcrdat;
+ cyg_ucount8 i;
+ for (i = 0; i < 6; i+=2) {
+ DP_OUT(dp->base, DP_RFCR, i);
+ DP_IN(dp->base, DP_RFDR, rfcrdat );
+ enaddr[i] = rfcrdat & 0xff;
+ enaddr[i+1] = (rfcrdat>>8) & 0xff;
+ }
+ esa_ok = true;
+ }
+#elif defined(CYGHWR_NS_DP83816_USE_EEPROM)
+ // This define (CYGHWR_NS_DP83816_USE_EEPROM) is deprecated.
{
cyg_uint16 t;
esa_ok = true;
}
-#else
-#ifdef CYGPKG_REDBOOT
-#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
- esa_ok = flash_get_config(dp->esa_key, enaddr, CONFIG_ESA);
-#else
- esa_ok = false;
-#endif
-#else
- esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
- dp->esa_key, enaddr, CONFIG_ESA);
-#endif
#endif
if (esa_ok) {
memcpy(dp->enaddr, enaddr, sizeof(enaddr));
diag_printf("DP83816 - Warning! ESA unknown\n");
}
+ // DEBUG_FUNCTION();
+
if (!dp83816_reset(dp)) return false;
+#if DEBUG & 8
+ diag_printf("DP83816 - ESA: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ dp->enaddr[0], dp->enaddr[1], dp->enaddr[2],
+ dp->enaddr[3], dp->enaddr[4], dp->enaddr[5] );
+#endif
+
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
cyg_drv_interrupt_create(
dp->interrupt,
cyg_drv_interrupt_attach(dp->interrupt_handle);
cyg_drv_interrupt_unmask(dp->interrupt);
+#elif defined(CYGPKG_REDBOOT)
+ cyg_drv_interrupt_unmask(dp->interrupt);
#endif
// Initialize upper level driver
struct dp83816_priv_data *dp = (struct dp83816_priv_data *)sc->driver_private;
int i, len;
unsigned char *data;
- dp83816_bd_t *bdp = dp->txfill;
+ dp83816_bd_t *bdp;
+#if 0
+ cyg_uint32 ints;
+ cyg_drv_dsr_lock();
+ HAL_DISABLE_INTERRUPTS(ints);
+#endif
+
+ bdp= dp->txfill;
DEBUG_FUNCTION();
len = total_len;
if (len < IEEE_8023_MIN_FRAME) len = IEEE_8023_MIN_FRAME;
data = (unsigned char *)CYGARC_VIRTUAL_ADDRESS(CYG_LE32_TO_CPU((unsigned long)bdp->buf));
+#if DEBUG & 1
+ if (!norecurse) {
+ norecurse=1;
+ diag_printf("send sg_len==%d, txbusy=%d, len=%d, total_len=%d\n", sg_len, dp->txbusy, len, total_len);
+ norecurse = 0;
+ }
+#endif
for (i = 0; i < sg_len; i++) {
memcpy(data, (unsigned char *)sg_list[i].buf, sg_list[i].len);
data += sg_list[i].len;
dp->txfill = bdp;
// Kick the device, in case it went idle
DP_OUT(dp->base, DP_CR, _CR_TXE);
+#if 0
+ cyg_drv_dsr_unlock();
+ HAL_RESTORE_INTERRUPTS(ints);
+#endif
}
static void
data = (unsigned char *)CYGARC_VIRTUAL_ADDRESS(CYG_LE32_TO_CPU((unsigned long)bdp->buf));
for (i = 0; i < sg_len; i++) {
- memcpy((void *)sg_list[i].buf, data, sg_list[i].len);
+ if( sg_list[i].buf )
+ memcpy((void *)sg_list[i].buf, data, sg_list[i].len);
data += sg_list[i].len;
}
}
dp83816_bd_t *bdp;
int i;
+ DEBUG_FUNCTION();
// Free up any active Tx buffers
bdp = CYGARC_UNCACHED_ADDRESS(dp->txd);
for (i = 0; i < dp->txnum; i++, bdp++) {
struct dp83816_priv_data *dp = (struct dp83816_priv_data *)sc->driver_private;
unsigned long stat, cr_stat;
+#if defined(CYGPKG_REDBOOT)
+ cyg_drv_interrupt_acknowledge(dp->interrupt);
+#endif
+
DP_IN(dp->base, DP_ISR, stat);
do {
if ((stat & (_ISR_TXDESC|_ISR_TXOK)) != 0) {
}
DP_IN(dp->base, DP_CR, cr_stat);
if ((stat & (_ISR_HIBERR|_ISR_TXURN|_ISR_RXORN)) != 0) {
-#if 0
+#if DEBUG & 2
diag_printf("DP83816 - major error: %x, cmd_stat: %x\n", stat, cr_stat);
#endif
// Try to reset the device
dp83816_warm_reset(sc);
}
- if (((cr_stat & _CR_RXE) == 0) ||
- ((dp->txbusy > 1) && ((cr_stat & _CR_TXE) == 0))) {
#if 0
+ if (((cr_stat & _CR_RXE) == 0) ||
+ ((dp->txbusy > 1) && ((cr_stat & _CR_TXE) == 0)))
+ {
+#if DEBUG & 2
// What happened?
- diag_printf("DP83816 went to lunch? - stat: %x/%x, txbusy: %x\n", cr_stat, stat, dp->txbusy);
+ diag_printf("DP83816 went to lunch? - stat: %x/%x, txbusy: %x, bdstat: %x\n", cr_stat, stat, dp->txbusy, dp->txint->stat);
#endif
// Try to reset the device
dp83816_warm_reset(sc);
}
+#endif
DP_IN(dp->base, DP_ISR, stat);
} while (stat != 0);
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+2007-04-06 Uwe Kindler <uwe_kindler@web.de>
+
+ * cdl/phy_eth_drivers.cdl:
+ * src/KS8721.c: Add support for Micrel KS8721 PHY
+
+2007-01-17 John Eigelaar <jeigelaar@mweb.co.za>
+
+ * cdl/phy_eth_drivers.cdl:
+ * src/DM9161A.c: Add support for Davicom 9161A.
+
+2006-04-07 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * doc/eth_phy.sgml: Fixed a few typos
+
+2006-03-30 Jay Foster <jay@systech.com>
+ * include/eth_phy.h: Add default mode value for _eth_phy_cfg().
+ * cdl/phy_eth_drivers.cdl: Add support for ICS189x.
+ * include/eth_phy_dev.h:
+ * src/AM79C874.c:
+ * src/DP83847.c:
+ * src/INLXT972.c: Make debug output CDL configurable.
+ * src/eth_phy.c: Fix bug in _eth_phy_init() that prevented using
+ a PHY MII address other than 0.
+ * src/ics189x.c: New
+
2005-08-25 Markus Schade <marks@peppercon.de>
* src/INLXT972.c:
compile eth_phy.c
+ cdl_option CYGDBG_DEVS_ETH_PHY {
+ display "Enable driver debugging"
+ flavor bool
+ default_value 0
+ description "Enables the diagnostic debug messages on the
+ console device."
+ }
+
cdl_option CYGINT_DEVS_ETH_PHY_AUTO_NEGOTIATION_TIME {
display "Time period (seconds) to wait for auto-negotiation"
flavor data
Include support for Intel LXT972xxx PHY"
}
+ cdl_option CYGHWR_DEVS_ETH_PHY_ICS1890 {
+ display "ICS 1890"
+ flavor bool
+ default_value 0
+ compile -library=libextras.a ics189x.c
+ description "
+ Include support for ICS 1890 PHY"
+ }
+
+ cdl_option CYGHWR_DEVS_ETH_PHY_ICS1892 {
+ display "ICS 1892"
+ flavor bool
+ default_value 0
+ compile -library=libextras.a ics189x.c
+ description "
+ Include support for ICS 1892 PHY"
+ }
+
+ cdl_option CYGHWR_DEVS_ETH_PHY_ICS1893 {
+ display "ICS 1893"
+ flavor bool
+ default_value 0
+ compile -library=libextras.a ics189x.c
+ description "
+ Include support for ICS 1893 and 1893AF PHY"
+ }
+
+ cdl_option CYGHWR_DEVS_ETH_PHY_DM9161A {
+ display "Davicom DM9161A"
+ flavor bool
+ default_value 0
+ compile -library=libextras.a DM9161A.c
+ description "
+ Include support for the Davicom DM9161A PHY"
+ }
+
+ cdl_option CYGHWR_DEVS_ETH_PHY_KS8721 {
+ display "Micrel KS8721"
+ flavor bool
+ default_value 0
+ compile -library=libextras.a KS8721.c
+ description "
+ Include support for the Micrel KS8721 PHY"
+ }
+
cdl_option CYGHWR_DEVS_ETH_PHY_LAN8700 {
display "SMSC LAN8700"
flavor bool
description "
Include support for SMSC LAN8700 NetPHY"
}
-
}
<para>
Modern ethernet subsystems are often separated into two pieces, the
media access controller (sometimes known as a MAC) and the physical
-device or line interface (often refered to as a PHY). In this case,
+device or line interface (often referred to as a PHY). In this case,
the MAC handles generating and parsing physical frames and the PHY
handles how this data is actually moved to/from the wire. The MAC
and PHY communicate via a special protocol, known as MII. This MII
of such transmission criteria as line speed, duplex mode, etc.
</para>
<para>
-In most cases, etnernet drivers only need to bother with the PHY during
+In most cases, ethernet drivers only need to bother with the PHY during
system initialization. Since the details of the PHY are separate from
the MAC, there are different drivers for each. The drivers for the PHY
are described by a set of exported functions which are commonly used by
-by the MAC. The primary use of these functions currently is to initialize
+the MAC. The primary use of these functions currently is to initialize
the PHY and determine the status of the line connection.
</para>
<para>
};
</programlisting>
-The <varname>dev</varname> element points to the PHY speficic support
+The <varname>dev</varname> element points to the PHY specific support
functions.
Currently, the only function which must be defined is <function>stat()</function>.
</para>
function may be called by a driver to cause the PHY device to
be reset to a known state.
Not all drivers will require this and this function may not even
-be possible, so it's use and behaviour is somewhat target specific.
+be possible, so it's use and behavior is somewhat target specific.
</para>
<para>
Currently, the only function required of device specific drivers is
This routine should query appropriate registers in the PHY and return
a status bitmap indicating the state of the physical connection.
In the case where the PHY can auto-negotiate a line speed and condition,
-this information may be useful to the MAC to indicate what spped it should
+this information may be useful to the MAC to indicate what speed it should
provide data, etc.
The status bitmask contains these bits:
<programlisting>
externC void _eth_phy_reset(eth_phy_access_t *f);
externC int _eth_phy_state(eth_phy_access_t *f);
externC int _eth_phy_cfg(eth_phy_access_t *f, int mode);
+#define ETH_PHY_MODE_DEFAULT 0
+
// Internal routines
externC void _eth_phy_write(eth_phy_access_t *f, int reg, int unit, unsigned short data);
externC bool _eth_phy_read(eth_phy_access_t *f, int reg, int unit, unsigned short *val);
//
//==========================================================================
+#ifdef CYGDBG_DEVS_ETH_PHY
+#include <cyg/infra/diag.h>
+#define eth_phy_printf(args...) diag_printf(args)
+#else
+#define eth_phy_printf(args...) /* NOOP */
+#endif
+
// Transceiver mode
#define PHY_BMCR 0x00 // Register number
#define PHY_BMCR_RESET 0x8000
#define PHY_ID1 0x02 // Chip ID register (high 16 bits)
#define PHY_ID2 0x03 // Chip ID register (low 16 bits)
+#define PHY_AN_ADV 0x04 // Auto negotiation advertisement register
+#define PHY_AN_ADV_10HDX 0x0020
+#define PHY_AN_ADV_10FDX 0x0040
+#define PHY_AN_ADV_100HDX 0x0080
+#define PHY_AN_ADV_100FDX 0x0100
+#define PHY_AN_ADV_100_T4 0x0200
+
+#define PHY_AN_PAR 0x05 // Auto negotiation link partner ability
+#define PHY_AN_PAR_10HDX 0x0020
+#define PHY_AN_PAR_10FDX 0x0040
+#define PHY_AN_PAR_100HDX 0x0080
+#define PHY_AN_PAR_100FDX 0x0100
+#define PHY_AN_PAR_100_T4 0x0200
+
struct _eth_phy_dev_entry {
char *name;
unsigned long id;
#include <pkgconf/devs_eth_phy.h>
#include <cyg/infra/cyg_type.h>
-#include <cyg/infra/diag.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/drv_api.h>
// Read negotiated state
if (_eth_phy_read(f, 0x1, f->phy_addr, &phy_state)) {
if ((phy_state & 0x20) == 0) {
- diag_printf("... waiting for auto-negotiation");
+ eth_phy_printf("... waiting for auto-negotiation");
for (tries = 0; tries < CYGINT_DEVS_ETH_PHY_AUTO_NEGOTIATION_TIME; tries++) {
if (_eth_phy_read(f, 0x1, f->phy_addr, &phy_state)) {
if ((phy_state & 0x20) != 0) {
}
}
CYGACC_CALL_IF_DELAY_US(1000000); // 1 second
- diag_printf(".");
+ eth_phy_printf(".");
}
- diag_printf("\n");
+ eth_phy_printf("\n");
}
if ((phy_state & 0x20) != 0) {
*state = 0;
#include <pkgconf/devs_eth_phy.h>
#include <cyg/infra/cyg_type.h>
-#include <cyg/infra/diag.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/drv_api.h>
// Read negotiated state
if (_eth_phy_read(f, 0x10, f->phy_addr, &phy_state)) {
if ((phy_state & 0x10) == 0) {
- diag_printf("... waiting for auto-negotiation");
+ eth_phy_printf("... waiting for auto-negotiation");
for (tries = 0; tries < CYGINT_DEVS_ETH_PHY_AUTO_NEGOTIATION_TIME; tries++) {
if (_eth_phy_read(f, 0x10, f->phy_addr, &phy_state)) {
if ((phy_state & 0x10) != 0) {
}
}
CYGACC_CALL_IF_DELAY_US(1000000); // 1 second
- diag_printf(".");
+ eth_phy_printf(".");
}
- diag_printf("\n");
+ eth_phy_printf("\n");
}
if ((phy_state & 0x10) != 0) {
*state = 0;
#include <pkgconf/devs_eth_phy.h>
#include <cyg/infra/cyg_type.h>
-#include <cyg/infra/diag.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/drv_api.h>
// Read negotiated state
if (_eth_phy_read(f, PHY_BMSR, f->phy_addr, &phy_state)) {
if ((phy_state & PHY_BMSR_AUTO_NEG) == 0) {
- diag_printf("... waiting for auto-negotiation");
+ eth_phy_printf("... waiting for auto-negotiation");
for (tries = 0; tries < CYGINT_DEVS_ETH_PHY_AUTO_NEGOTIATION_TIME; tries++) {
if (_eth_phy_read(f, PHY_BMSR, f->phy_addr, &phy_state)) {
if ((phy_state & PHY_BMSR_AUTO_NEG) != 0) {
}
}
CYGACC_CALL_IF_DELAY_US(1000000); // 1 second
- diag_printf(".");
+ eth_phy_printf(".");
}
- diag_printf("\n");
+ eth_phy_printf("\n");
}
if ((phy_state & PHY_BMSR_AUTO_NEG) != 0) {
*state = 0;
//==========================================================================
#include <pkgconf/system.h>
+#include <pkgconf/io_eth_drivers.h>
+#include <pkgconf/devs_eth_phy.h>
#include <cyg/infra/cyg_type.h>
-#include <cyg/infra/diag.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/drv_api.h>
{
cyg_uint32 retval;
int i, off;
- bool is_read = ((cmd & MII_Cmd) == MII_Read);
+ bool is_read = (cmd & MII_Cmd) == MII_Read;
// Set both bits as output
- (f->ops.bit_level_ops.set_dir)(1);
+ f->ops.bit_level_ops.set_dir(1);
// Preamble
for (i = 0; i < 32; i++) {
- (f->ops.bit_level_ops.set_clock)(0);
- (f->ops.bit_level_ops.set_data)(1);
+ f->ops.bit_level_ops.set_clock(0);
+ f->ops.bit_level_ops.set_data(1);
CYGACC_CALL_IF_DELAY_US(1);
- (f->ops.bit_level_ops.set_clock)(1);
+ f->ops.bit_level_ops.set_clock(1);
CYGACC_CALL_IF_DELAY_US(1);
}
// Command/data
for (i = 0, off = 31; i < (is_read ? 14 : 32); i++, --off) {
- (f->ops.bit_level_ops.set_clock)(0);
- (f->ops.bit_level_ops.set_data)((cmd >> off) & 0x00000001);
+ f->ops.bit_level_ops.set_clock(0);
+ f->ops.bit_level_ops.set_data((cmd >> off) & 0x00000001);
CYGACC_CALL_IF_DELAY_US(1);
- (f->ops.bit_level_ops.set_clock)(1);
+ f->ops.bit_level_ops.set_clock(1);
CYGACC_CALL_IF_DELAY_US(1);
}
if (is_read) {
retval >>= 16;
- (f->ops.bit_level_ops.set_clock)(0);
- (f->ops.bit_level_ops.set_dir)(0);
+ f->ops.bit_level_ops.set_clock(0);
+ f->ops.bit_level_ops.set_dir(0);
CYGACC_CALL_IF_DELAY_US(1);
- (f->ops.bit_level_ops.set_clock)(1);
+ f->ops.bit_level_ops.set_clock(1);
CYGACC_CALL_IF_DELAY_US(1);
- (f->ops.bit_level_ops.set_clock)(0);
+ f->ops.bit_level_ops.set_clock(0);
CYGACC_CALL_IF_DELAY_US(1);
for (i = 0, off = 15; i < 16; i++, off--) {
- (f->ops.bit_level_ops.set_clock)(1);
+ f->ops.bit_level_ops.set_clock(1);
retval <<= 1;
- retval |= (f->ops.bit_level_ops.get_data)();
+ retval |= f->ops.bit_level_ops.get_data();
CYGACC_CALL_IF_DELAY_US(1);
- (f->ops.bit_level_ops.set_clock)(0);
+ f->ops.bit_level_ops.set_clock(0);
CYGACC_CALL_IF_DELAY_US(1);
}
}
// Set both bits as output
- (f->ops.bit_level_ops.set_dir)(1);
+ f->ops.bit_level_ops.set_dir(1);
// Postamble
for (i = 0; i < 32; i++) {
- (f->ops.bit_level_ops.set_clock)(0);
- (f->ops.bit_level_ops.set_data)(1);
+ f->ops.bit_level_ops.set_clock(0);
+ f->ops.bit_level_ops.set_data(1);
CYGACC_CALL_IF_DELAY_US(1);
- (f->ops.bit_level_ops.set_clock)(1);
+ f->ops.bit_level_ops.set_clock(1);
CYGACC_CALL_IF_DELAY_US(1);
}
{
int addr;
unsigned short state;
- unsigned long id;
+ unsigned long id = 0;
struct _eth_phy_dev_entry *dev;
if (f->init_done) return true;
- (f->init)();
+ f->init();
// Scan to determine PHY address
f->init_done = true;
for (addr = 0; addr < 0x20; addr++) {
if (_eth_phy_read(f, PHY_ID1, addr, &state)) {
- if (state == 0xffff || state == 0x0000) {
- continue;
- }
- id = state << 16;
+ id = state << 16;
if (_eth_phy_read(f, PHY_ID2, addr, &state)) {
id |= state;
f->phy_addr = addr;
for (dev = __ETH_PHY_TAB__; dev != &__ETH_PHY_TAB_END__; dev++) {
if (dev->id == id) {
- diag_printf("PHY: %s\n", dev->name);
+ eth_phy_printf("PHY: %s\n", dev->name);
f->dev = dev;
return true;
}
}
- diag_printf("Unsupported PHY device - id: %08lx\n", id);
- //break; // Can't handle this PHY, but look for others!
}
}
}
+ if (addr >= 0x20) {
+ // Can't handle this PHY
+ eth_phy_printf("Unsupported PHY device - id: %lx\n", id);
+ }
f->init_done = false;
return false;
}
_eth_phy_reset(eth_phy_access_t *f)
{
if (!f->init_done) {
- diag_printf("PHY reset without init on PHY: %p\n", f);
+ eth_phy_printf("PHY reset without init on PHY: %p\n", f);
return;
}
- (f->init)();
+ f->init();
}
externC void
_eth_phy_write(eth_phy_access_t *f, int reg, int addr, unsigned short data)
{
if (!f->init_done) {
- diag_printf("PHY write without init on PHY: %p\n", f);
+ eth_phy_printf("PHY write without init on PHY: %p\n", f);
return;
}
if (f->ops_type == PHY_BIT_LEVEL_ACCESS_TYPE) {
phy_cmd(f, MII_Start | MII_Write | MII_Phy(addr) | MII_Reg(reg) | MII_TA | data);
} else {
- (f->ops.reg_level_ops.put_reg)(reg, addr, data);
+ f->ops.reg_level_ops.put_reg(reg, addr, data);
}
}
cyg_uint32 ret;
if (!f->init_done) {
- diag_printf("PHY read without init on PHY: %p\n", f);
+ eth_phy_printf("PHY read without init on PHY: %p\n", f);
return false;
}
if (f->ops_type == PHY_BIT_LEVEL_ACCESS_TYPE) {
*val = ret;
return true;
} else {
- return (f->ops.reg_level_ops.get_reg)(reg, addr, val);
+ return f->ops.reg_level_ops.get_reg(reg, addr, val);
}
}
int i;
if (!f->init_done) {
- diag_printf("PHY config without init on PHY: %p\n", f);
+ eth_phy_printf("PHY config without init on PHY: %p\n", f);
return 0;
}
_eth_phy_write(f, PHY_BMCR, f->phy_addr, PHY_BMCR_RESET);
for (i = 0; i < 5*100; i++) {
phy_ok = _eth_phy_read(f, PHY_BMCR, f->phy_addr, &phy_state);
- diag_printf("PHY: %04x\n", phy_state);
+ eth_phy_printf("PHY: %x\n", phy_state);
if (phy_ok && !(phy_state & PHY_BMCR_RESET)) break;
CYGACC_CALL_IF_DELAY_US(10000); // 10ms
}
if (!phy_ok || (phy_state & PHY_BMCR_RESET)) {
- diag_printf("PPC405: Can't get PHY unit to soft reset: %04x\n", phy_state);
+ eth_phy_printf("PPC405: Can't get PHY unit to soft reset: %x\n", phy_state);
return 0;
}
}
}
if (phy_timeout <= 0) {
- diag_printf("** PPC405 Warning: PHY LINK UP failed: %04x\n", phy_state);
+ eth_phy_printf("** PPC405 Warning: PHY LINK UP failed: %04x\n", phy_state);
return 0;
}
int state = 0;
if (!f->init_done) {
- diag_printf("PHY state without init on PHY: %p\n", f);
+ eth_phy_printf("PHY state without init on PHY: %p\n", f);
return 0;
}
- if ((f->dev->stat)(f, &state)) {
+ if (f->dev->stat(f, &state)) {
return state;
} else {
return 0;
* GNUWIN32 compiled with GCC
*
* $Log$
- * Revision 1.1 2008-11-03 11:35:23 lothar
- * Initial revision
+ * Revision 1.1.9.1 2009-06-15 13:39:30 lothar
+ * unified MX27, MX25, MX37 trees
*
* Revision 1.1.1.2 2002/03/14 17:54:24 pfine
* Fixed CR/LF Problem
+2007-05-30 Hajime Ishitani <pigmon@mail.snd.co.jp>
+
+ * src/if_8139.c:
+ * cdl/rltk_8139_eth_drivers.cdl
+ add write in MAC address at EEPROM by SIOCSIFHWADDR.
+
+2006-12-17 Hajime Ishitani <pigmon@mail.snd.co.jp>
+
+ * src/if_8139.c:
+ added 0x10ec/0x8129 for RTL8139C(L) of a known device.
+
+2006-11-13 Hajime Ishitani <pigmon@mail.snd.co.jp>
+
+ * src/if_8139.c: Enabled "PUN/LinkChg" interrupt.
+
+2005-12-02 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/if_8139.c (rltk8139_deliver): Fix the compiler warnings by
+ adding some casts.
+
+2005-11-25 Hajime Ishitani <pigmon@mail.snd.co.jp>
+
+ * src/if_8139.h:
+ * src/if_8139.c: Added a priority level field
+
2005-03-03 Bob Koninckx <bob.koninckx@fmtc.be>
* src/if_8139.c: fixed bug that prevented rltk8139_find to find
# }
# }
-# cdl_component CYGPKG_DEVS_ETH_RLTK_8139_WRITE_EEPROM {
-# display "SIOCSIFHWADDR records MAC address in EEPROM"
-# default_value 0
-# description "
-# The ioctl() socket call with operand SIOCSIFHWADDR sets the
-# interface hardware address - the MAC address or ethernet
-# address. This option causes the new MAC address to be written
-# into the EEPROM associated with the interface, so that the new
-# MAC address is permanently recorded. Doing this should be a
-# carefully chosen decision, hence this option."
-# }
+ cdl_component CYGPKG_DEVS_ETH_RLTK_8139_WRITE_EEPROM {
+ display "SIOCSIFHWADDR records MAC address in EEPROM"
+ default_value 0
+ description "
+ The ioctl() socket call with operand SIOCSIFHWADDR sets the
+ interface hardware address - the MAC address or ethernet
+ address. This option causes the new MAC address to be written
+ into the EEPROM associated with the interface, so that the new
+ MAC address is permanently recorded. Doing this should be a
+ carefully chosen decision, hence this option."
+ }
cdl_option CYGNUM_DEVS_ETH_RLTK_8139_RX_BUF_LEN_IDX {
display "Size of the receive ring"
#include "if_8139.h"
/* Which interrupts we will handle */
-#define RLTK8139_IRQ (IR_SERR|IR_FOVW|IR_RXOVW|IR_TER|IR_TOK|IR_RER|IR_ROK)
+#define RLTK8139_IRQ (IR_SERR|IR_FOVW|IR_RXOVW|IR_TER|IR_TOK|IR_RER|IR_ROK|IR_FUN)
/* Allow platform-specific configuration of the driver */
#ifndef CYGDAT_DEVS_ETH_RLTK_8139_INL
static void rltk8139_poll(struct eth_drv_sc *sc);
static int rltk8139_int_vector(struct eth_drv_sc *sc);
+#ifdef CYGPKG_DEVS_ETH_RLTK_8139_WRITE_EEPROM
+static cyg_uint16 rltk8139_eeprom_read( char *cpErAddr, cyg_uint8 Cmd, cyg_uint8 RomAdr );
+static void rltk8139_eeprom_write( char *cpErAddr, cyg_uint8 Cmd, cyg_uint8 RomAdr, cyg_uint16 SrcData );
+#endif
+
#ifdef DEBUG_RLTK8139_DRIVER
void rltk8139_print_state(struct eth_drv_sc *sc);
#endif
+#ifdef CYGPKG_DEVS_ETH_RLTK_8139_WRITE_EEPROM
+#define EEPROM_CMD_READ 0x06 // eeprom read command
+#define EEPROM_CMD_WRITE 0x05 // eeprom write command
+#define EEPROM_PG_ON 0x80
+#define EEPROM_PG_EECS 0x08
+#define EEPROM_PG_EESK 0x04
+#define EEPROM_PG_EEDI 0x02
+#define EEPROM_PG_EEDO 0x01
+#define EEPROM_WR_BUSY_RETRIES 100 // ready wait re-try count
+
+#define EEPROM_MASK(_param0_,_param1_) ((_param0_ & _param1_) ? EEPROM_PG_EEDI : 0 )
+
+
+#define EEPROM_WR_DATA(_addr_,_txdata_) HAL_WRITE_UINT8(_addr_,_txdata_);
+
+#define EEPROM_WR_DATAPULSE(_addr_,_txdata_) HAL_WRITE_UINT8(_addr_,_txdata_); \
+ cyg_thread_delay(0); \
+ HAL_WRITE_UINT8(_addr_,_txdata_ | EEPROM_PG_EESK);
+
+#define EEPROM_RD_DATA(_addr_,_txdata_,_rxdata_) { \
+ cyg_uint16 read_data; \
+ HAL_WRITE_UINT8(_addr_,_txdata_); \
+ cyg_thread_delay(1); \
+ HAL_READ_UINT8(_addr_, read_data); \
+ _rxdata_ <<= 1; \
+ _rxdata_ |= ((read_data & EEPROM_PG_EEDO) ? 0x0001 : 0x0000 ); \
+ HAL_WRITE_UINT8(_addr_,_txdata_ | EEPROM_PG_EESK); }
+#endif
+
/*
* Define inline functions to access the card. This will also handle
* endianess issues in one place. This code was lifted from the eCos
* Table of all known PCI device/vendor ID combinations for the RealTek 8139.
* Add them as you get to know them.
*/
-#define CYGNUM_DEVS_ETH_RLTK_8139_KNOWN_ALIASES 2
+#define CYGNUM_DEVS_ETH_RLTK_8139_KNOWN_ALIASES 3
static pci_identifier_t
known_8139_aliases[CYGNUM_DEVS_ETH_RLTK_8139_KNOWN_ALIASES] = {
- { 0x10ec, 0x8139, NULL }, /* This is the offical RealTek vendor/device code */
- { 0x11db, 0x1234, NULL} /* SEGA DreamCast BroadBandAdapter */
+ { 0x10ec, 0x8139, NULL }, /* This is the official RealTek vendor/device code of 8139D(L) */
+ { 0x11db, 0x1234, NULL}, /* SEGA DreamCast BroadBandAdapter */
+ { 0x10ec, 0x8129, NULL } /* This is the official RealTek vendor/device code of 8139C(L) */
};
* Note that we use the generic eth_drv_dsr routine instead of
* our own.
*/
- cyg_drv_interrupt_create(rltk8139_info->vector, 0,
+ cyg_drv_interrupt_create(rltk8139_info->vector,
+ rltk8139_info->isr_priority,
(CYG_ADDRWORD)sc,
rltk8139_isr,
eth_drv_dsr,
int i;
Rltk8139_t *rltk8139_info;
+#ifdef CYGPKG_DEVS_ETH_RLTK_8139_WRITE_EEPROM
+ cyg_uint16 WrData, RdData;
+ cyg_uint8 *pSrcData;
+ int iRetry;
+#endif
#ifdef DEBUG_RLTK8139_DRIVER
diag_printf("rltk8139_control(%08x, %lx)\n", sc, key);
rltk8139_info->mac[i] = *(((cyg_uint8 *)data) + i);
OUTB(rltk8139_info->mac[i], rltk8139_info->base_address + IDR0 + i);
}
+
+#ifdef CYGPKG_DEVS_ETH_RLTK_8139_WRITE_EEPROM
+ pSrcData = (cyg_uint8 *)data;
+ for(i = 0; i < 3; i++){
+ WrData = ((cyg_uint16)(*pSrcData++)) & 0xff;
+ WrData |= ((cyg_uint16)(*pSrcData++)) << 8;
+ for( iRetry = 0; iRetry < 3; iRetry++){
+ rltk8139_eeprom_write(
+ (char *)(rltk8139_info->base_address + CR9346),
+ EEPROM_CMD_WRITE, i + 7, WrData);
+ RdData = rltk8139_eeprom_read(
+ (char *)(rltk8139_info->base_address + CR9346),
+ EEPROM_CMD_READ, i + 7);
+ if( RdData == WrData ){
+ break;
+ }
+ }
+ }
+#endif
+
return 0;
#endif
* this happens so seldomly that it's simply not worth the extra
* runtime check.
*/
- tx_buffer = CYGARC_UNCACHED_ADDRESS(rltk8139_info->tx_buffer
- + TX_BUF_SIZE * desc);
+ tx_buffer = (cyg_uint8 *)CYGARC_UNCACHED_ADDRESS(rltk8139_info->tx_buffer
+ + TX_BUF_SIZE * desc);
rltk8139_info->tx_desc_key[desc] = key;
/*
* doesn't have to redetermine this information. Then, inform
* the generic ethernet driver about the packet.
*/
- rltk8139_info->rx_current = CYGARC_UNCACHED_ADDRESS(rltk8139_info->rx_ring + rx_pos + 4);
+ rltk8139_info->rx_current =
+ (cyg_uint8 *)CYGARC_UNCACHED_ADDRESS(rltk8139_info->rx_ring +
+ rx_pos + 4);
rltk8139_info->rx_size = length;
/* Tell eCos about the packet */
return;
}
+ if (status & IR_FUN) {
+ /*
+ * Packet underrun or link change interrupt.
+ * A cable was packet underrun or re-connected ?
+ */
+#ifdef DEBUG_RLTK8139_DRIVER
+ diag_printf("rltk8139_deliver(%s): packet underrun or link change\n",
+ sc->dev_name);
+#endif
+ }
+
#ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
/* Finally, reenable interrupts */
#ifdef CYGPKG_DEVS_ETH_RLTK_8139_MASK_INTERRUPTS_IN_8139
}
}
#endif
+
+
+#ifdef CYGPKG_DEVS_ETH_RLTK_8139_WRITE_EEPROM
+/*
+ * Read mac_address from EEPROM.
+ */
+static cyg_uint16
+rltk8139_eeprom_read( char *rtl_addr, cyg_uint8 eeprom_cmd, cyg_uint8 eeprom_addr )
+{
+cyg_uint8 read_data; // read from eeprom bit data
+cyg_uint8 org_param; // original register parameter
+cyg_uint8 mask_bit8; // mask bit
+int icount; // for loop counter
+
+ // get old parameter
+ HAL_READ_UINT8( rtl_addr, org_param );
+
+ // ready
+ EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON );
+
+ // set command
+ mask_bit8 = 0x04;
+ for(icount = 0; icount < 3; icount++){
+ EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_MASK( mask_bit8, eeprom_cmd ));
+ mask_bit8 >>= 1;
+ }
+
+ // set address
+ mask_bit8 = 0x20;
+ for(icount = 0; icount < 6; icount++){
+ EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_MASK( mask_bit8, eeprom_addr ));
+ mask_bit8 >>= 1;
+ }
+
+ // read data
+ read_data = 0;
+ for(icount = 0; icount < 16; icount++){
+ EEPROM_RD_DATA( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS, read_data );
+ }
+
+ // close
+ EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
+ EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON );
+
+ // put old parameter
+ HAL_WRITE_UINT8(rtl_addr, org_param);
+
+ return(read_data);
+}
+
+
+/*
+ * Write in mac_address at EEPROM.
+ */
+static void
+rltk8139_eeprom_write( char *rtl_addr, cyg_uint8 eeprom_cmd, cyg_uint8 eeprom_addr, cyg_uint16 src_data )
+{
+cyg_uint8 read_data; // read from eeprom bit data
+cyg_uint8 org_param; // original register parameter
+cyg_uint8 mask_bit8; // mask bit
+cyg_uint16 mask_bit16; // mask bit for write data
+int icount; // for loop counter
+
+ // get old parameter
+ HAL_READ_UINT8( rtl_addr, org_param );
+
+ // ready
+ EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON );
+ EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EESK );
+ EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON );
+
+ // set EWEN (eeprom write enable)
+ EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_PG_EEDI );
+ EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
+ EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
+ EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_PG_EEDI );
+ EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_PG_EEDI );
+ EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
+ EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
+ EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
+ EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
+ EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON );
+
+ // set command
+ mask_bit8 = 0x04;
+ for(icount = 0; icount < 3; icount++){
+ EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_MASK( mask_bit8, eeprom_cmd ));
+ mask_bit8 >>= 1;
+ }
+
+ // set address
+ mask_bit8 = 0x20;
+ for(icount = 0; icount < 6; icount++){
+ EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_MASK( mask_bit8, eeprom_addr ));
+ mask_bit8 >>= 1;
+ }
+
+ // set data
+ mask_bit16 = 0x8000;
+ for(icount = 0; icount < 16; icount++){
+ EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_MASK( mask_bit16, src_data ));
+ mask_bit16 >>= 1;
+ }
+
+ // close
+ EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON );
+ EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EESK );
+ EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON );
+
+ // write ready check
+ EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
+
+ // wait busy disable
+ icount = 0;
+ while( 1 ){
+ cyg_thread_delay( 1 );
+ HAL_WRITE_UINT8( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_PG_EESK );
+ HAL_WRITE_UINT8( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
+ HAL_READ_UINT8( rtl_addr, read_data );
+ if(( read_data & EEPROM_PG_EEDO ) != 0 ){
+ break;
+ }
+ if( icount++ >= EEPROM_WR_BUSY_RETRIES ){
+ diag_printf("EEPROM write wait error adr=0x%02x data=0x%04x\n", eeprom_addr, src_data );
+ break;
+ }
+ }
+ HAL_WRITE_UINT8( rtl_addr, EEPROM_PG_ON );
+
+ // put old parameter
+ HAL_WRITE_UINT8( rtl_addr, org_param );
+}
+
+#endif
cyg_vector_t vector;
cyg_handle_t interrupt_handle;
cyg_interrupt interrupt;
+
+ /* device ISR priority */
+ cyg_priority_t isr_priority;
+
} Rltk8139_t;
+2005-12-02 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * cdl/sh_dreamcast_rltk8139_eth_drivers.cdl: Add compiler
+ flags "-D_KERNEL -D__ECOS" so the code compiles.
+
2004-04-21 Yoshinori Sato <ysato@users.sourceforge.jp>
* src/if_dreamcast.c
RealTek 8139 ethernet port 0."
}
}
+ cdl_component CYGPKG_DEVS_ETH_SH_DREAMCAST_RLTK8139_OPTIONS {
+ display "RealTek 8139 ethernet driver build options"
+ flavor none
+ no_define
+
+ cdl_option CYGPKG_DEVS_ETH_SH_DREAMCAST_RLTK8139_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "-D_KERNEL -D__ECOS" }
+ description "
+ This option modifies the set of compiler flags for
+ building the RealTek 8139 ethernet driver package. These
+ flags are used in addition to the set of global flags."
+ }
+ }
}
# EOF sh_dreamcast_rltk8139_eth_drivers.cdl
* src/if_lan91cxx.c: Reset the physical layer before configuring
it, otherwise it might not work.
+2005-01-24 Nick Garnett <nickg@ecoscentric.com>
+
+ * src/if_lan91cxx.c (lan91cxx_send): Rewrote parts of transmit
+ machinery to deal with odd sized message buffers. The TCP/IP stack
+ generates these in rare circumstances.
+
+2005-01-21 Nick Garnett <nickg@ecoscentric.com>
+
+ * src/smsc_lan91cxx.h:
+ * src/if_lan91cxx.c:
+ Rewrote parts of receive machinery to properly deal with 32 bit
+ wide access to the device. The original code didn't quite work.
+ Switched all calls the HAL_DELAY_US() to CYGACC_CALL_IF_DELAY_US().
+ Various small changes to debugging code.
+
+2004-12-01 Nick Garnett <nickg@ecoscentric.com>
+
+ * src/if_lan91cxx.c (lan91cxx_start): Added option to force speed
+ negotiation to 10MHz. Some embedded boards cannot handle 100MHz.
+ Generally added some small improvements to debugging messages.
+
2004-05-22 Andrew Dyer <adyer@righthandtech.com>
* src/if_lan91cxx.c: Fail initialization if no device found.
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2005 eCosCentric Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
configured in PCMCIA mode."
}
- cdl_option CYGSEM_DEVS_ETH_SMSC_LAN91CXX_USE_32BIT {
- display "use 32 bit data access"
- default_value 0
- description "
- The device driver uses 32 bit data access if
- this option is enabled, otherwise 16 bit data access is
- used."
- }
-
cdl_component CYGPKG_DEVS_ETH_SMSC_LAN91CXX_OPTIONS {
display "LAN91CXX ethernet driver build options"
flavor none
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2003 Nick Garnett
// Copyright (C) 2004 Andrew Lunn
+// Copyright (C) 2004 eCosCentric Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//####BSDCOPYRIGHTBEGIN####
va_end( a );
}
#else
+#if 0
+static void db_printf( char *fmt, ... )
+{
+ va_list a;
+ int old_console = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ va_start( a, fmt );
+ CYGACC_CALL_IF_SET_CONSOLE_COMM( 0 );
+ diag_vprintf( fmt, a );
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(old_console);
+ va_end( a );
+}
+#else
#define db_printf diag_printf
#endif
+#endif
+#else
+#if 0
+static void db_printf( char *fmt, ... )
+{
+ va_list a;
+ int old_console = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ va_start( a, fmt );
+ CYGACC_CALL_IF_SET_CONSOLE_COMM( 0 );
+ diag_vprintf( fmt, a );
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(old_console);
+ va_end( a );
+}
#else
#define db_printf( fmt, ... )
#endif
+#endif
#if DEBUG & 1
struct lan91cxx_priv_data *cpd =
(struct lan91cxx_priv_data *)sc->driver_private;
- DEBUG_FUNCTION();
+// DEBUG_FUNCTION();
INCR_STAT( interrupts );
struct lan91cxx_priv_data *cpd =
(struct lan91cxx_priv_data *)sc->driver_private;
- DEBUG_FUNCTION();
+// DEBUG_FUNCTION();
// Service the interrupt:
lan91cxx_poll(sc);
ecor |= LAN91CXX_ECOR_RESET;
put_att(sc, LAN91CXX_ECOR, ecor);
- HAL_DELAY_US(1);
+ CYGACC_CALL_IF_DELAY_US(1);
ecor &= ~LAN91CXX_ECOR_RESET;
put_att(sc, LAN91CXX_ECOR, ecor);
cyg_drv_interrupt_attach(lan91cxx_interrupt_handle);
#endif // !CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
cyg_drv_interrupt_acknowledge(cpd->interrupt);
-#ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
cyg_drv_interrupt_unmask(cpd->interrupt);
-#endif // !CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
// probe chip by reading the signature in BS register
val = get_banksel(sc);
// LINK_OK on 91C111 is just a general purpose input and may not
// have anything to do with the link.
if (!(val & LAN91CXX_STATUS_LINK_OK)) {
- db_printf("no link\n");
+ db_printf("no link\n");
return false; // Link not connected
}
#endif
#ifdef LAN91CXX_IS_LAN91C111
// 91C111 Errata. Internal PHY comes up disabled. Must enable here.
lan91cxx_write_phy(sc, 0, LAN91CXX_PHY_CTRL, LAN91CXX_PHY_CTRL_RST);
- HAL_DELAY_US(500000);
+ CYGACC_CALL_IF_DELAY_US(500000);
lan91cxx_write_phy(sc, 0, LAN91CXX_PHY_CTRL, LAN91CXX_PHY_CTRL_ANEG_EN |
LAN91CXX_PHY_CTRL_SPEED);
+#ifdef LAN91CXX_FORCE_10MHZ
+ lan91cxx_write_phy( sc, 0, LAN91CXX_PHY_AUTO_AD, 0x0061);
+#endif
+
// Start auto-negotiation
put_reg(sc, LAN91CXX_RPCR,
LAN91CXX_RPCR_LEDA_RX | LAN91CXX_RPCR_LEDB_LINK | LAN91CXX_RPCR_ANEG);
while (!(lan91cxx_read_phy(sc, 0, LAN91CXX_PHY_STAT) & 0x20)) {
if (--delay <= 0)
break;
- HAL_DELAY_US(100000);
+ CYGACC_CALL_IF_DELAY_US(100000);
}
#if DEBUG & 1
if (delay <= 0)
(struct lan91cxx_priv_data *)sc->driver_private;
int tcr;
- DEBUG_FUNCTION();
+// DEBUG_FUNCTION();
#ifndef LAN91CXX_IS_LAN91C111
// LINK_OK on 91C111 is just a general purpose input and may not
(struct lan91cxx_priv_data *)sc->driver_private;
int i, len, plen, tcr;
- unsigned short *sdata = NULL;
+ cyg_uint8 *sdata;
+ cyg_uint16 data = 0;
+ int dpos = 0;
unsigned short ints, control;
cyg_uint16 packet, status;
INCR_STAT( tx_count );
+#if DEBUG & 1
+ ints = get_reg(sc, LAN91CXX_INTERRUPT);
+ db_printf("%s:START: ints: %04x\n", __FUNCTION__, ints);
+#endif
+
// Worry about the TX engine stopping.
tcr = get_reg(sc, LAN91CXX_TCR);
if ( 0 == (LAN91CXX_TCR_TXENA & tcr) ) {
// packet length (includes status, byte-count and control shorts)
put_data(sc, CYG_CPU_TO_LE16(0x7FE & (plen + 6)) ); // Always even, always < 15xx(dec)
- // Put data into buffer
for (i = 0; i < sg_len; i++) {
- sdata = (unsigned short *)sg_list[i].buf;
+ sdata = (cyg_uint8 *)sg_list[i].buf;
len = sg_list[i].len;
-
- CYG_ASSERT(0 == (len & 1) || (i == (sg_len-1)), "odd length");
- CYG_ASSERT( sdata, "No sg data pointer here" );
- while(len >= sizeof(*sdata)) {
- put_data(sc, *sdata++);
- len -= sizeof(*sdata);
+ while( len > 0 )
+ {
+ data |= *sdata<<((dpos&1)*8);
+ dpos++, len--, sdata++;
+ if( (dpos & 1) == 0 )
+ {
+ put_data(sc, CYG_CPU_TO_LE16(data));
+ data = 0;
+ }
}
}
- CYG_ASSERT( sdata, "No sg data pointer outside" );
// Lay down the control short unconditionally at the end.
// (or it might use random memory contents)
control = 0;
- if ( 1 & plen ) {
+ if( 1 & plen ) {
// Need to set ODD flag and insert the data
- unsigned char onebyte = *(unsigned char*)sdata;
- control = onebyte;
+ control = data;
control |= LAN91CXX_CONTROLBYTE_ODD;
}
control |= LAN91CXX_CONTROLBYTE_CRC; // Just in case...
put_data(sc, CYG_CPU_TO_LE16(control));
-
+
// Enqueue the packet
put_reg(sc, LAN91CXX_MMU_COMMAND, LAN91CXX_MMU_enq_packet);
tcr = get_reg(sc, LAN91CXX_TCR);
if ( 0 == (LAN91CXX_TCR_TXENA & tcr) ) {
#if DEBUG & 1
- db_printf("%s: ENGINE RESTART: tcr 0x%04x ints %04x\n", __FUNCTION__, tcr, ints);
+ db_printf("%s: ENGINE RESTART: tcr 0x%04x eph 0x%04x ints 0x%04x\n", __FUNCTION__, tcr, get_reg(sc, LAN91CXX_EPH_STATUS), ints);
#endif
tcr |= LAN91CXX_TCR_TXENA;
put_reg(sc, LAN91CXX_TCR, tcr);
}
}
+void get_data_init(struct eth_drv_sc *sc)
+{
+ struct lan91cxx_priv_data *cpd =
+ (struct lan91cxx_priv_data *)sc->driver_private;
+
+ cpd->data_buf = 0xa5a5a5a5;
+ cpd->data_pos = sizeof(rxd_t);
+}
+
+cyg_uint8 get_data_byte(struct eth_drv_sc *sc)
+{
+ cyg_uint8 c;
+ struct lan91cxx_priv_data *cpd =
+ (struct lan91cxx_priv_data *)sc->driver_private;
+
+ if( cpd->data_pos == sizeof(rxd_t) )
+ {
+ cpd->data_buf = get_data(sc);
+ cpd->data_pos = 0;
+ }
+
+ c = (cpd->data_buf>>(cpd->data_pos*8))&0xFF;
+ cpd->data_pos++;
+
+ return c;
+
+}
+
+cyg_uint16 get_data_short(struct eth_drv_sc *sc)
+{
+ cyg_uint16 val;
+
+ val = get_data_byte(sc);
+ val |= get_data_byte(sc)<<8;
+
+ return CYG_LE16_TO_CPU(val);
+}
//
// This function is called when a packet has been received. Its job is
struct lan91cxx_priv_data *cpd =
(struct lan91cxx_priv_data *)sc->driver_private;
unsigned short stat, len;
-#ifdef CYGSEM_DEVS_ETH_SMSC_LAN91CXX_USE_32BIT
- cyg_uint32 val;
-#endif
DEBUG_FUNCTION();
// Read status and (word) length
put_reg(sc, LAN91CXX_POINTER, (LAN91CXX_POINTER_RCV | LAN91CXX_POINTER_READ |
LAN91CXX_POINTER_AUTO_INCR | 0x0000));
-#ifdef CYGSEM_DEVS_ETH_SMSC_LAN91CXX_USE_32BIT
- val = get_data(sc);
- val = CYG_LE32_TO_CPU(val);
- stat = val & 0xffff;
- len = ((val >> 16) & 0xffff) - 6; // minus header/footer words
-#else
- stat = get_data(sc);
- stat = CYG_LE16_TO_CPU(stat);
- len = get_data(sc);
- len = CYG_LE16_TO_CPU(len) - 6; // minus header/footer words
-#endif
+ get_data_init(sc);
+
+ stat = get_data_short(sc);
+ len = get_data_short(sc);
+ len = len - 6; // minus header/footer words
#ifdef KEEP_STATISTICS
if ( stat & LAN91CXX_RX_STATUS_ALIGNERR ) INCR_STAT( rx_align_errors );
// Not OK for one reason or another...
#if DEBUG & 1
db_printf("RxEvent - bad rx: stat: 0x%04x, len: 0x%04x\n", stat, len);
+ db_printf("PHY %2d: %04x\n",0,lan91cxx_read_phy( sc, 0, 0));
+ db_printf("PHY %2d: %04x\n",1,lan91cxx_read_phy( sc, 0, 1));
+ db_printf("PHY %2d: %04x\n",2,lan91cxx_read_phy( sc, 0, 2));
+ db_printf("PHY %2d: %04x\n",3,lan91cxx_read_phy( sc, 0, 3));
+ db_printf("PHY %2d: %04x\n",4,lan91cxx_read_phy( sc, 0, 4));
+ db_printf("PHY %2d: %04x\n",5,lan91cxx_read_phy( sc, 0, 5));
+ db_printf("PHY %2d: %04x\n",16,lan91cxx_read_phy( sc, 0, 16));
+ db_printf("PHY %2d: %04x\n",17,lan91cxx_read_phy( sc, 0, 17));
+ db_printf("PHY %2d: %04x\n",18,lan91cxx_read_phy( sc, 0, 18));
+ db_printf("PHY %2d: %04x\n",19,lan91cxx_read_phy( sc, 0, 19));
+ db_printf("PHY %2d: %04x\n",20,lan91cxx_read_phy( sc, 0, 20));
#endif
// Free packet
put_reg(sc, LAN91CXX_MMU_COMMAND, LAN91CXX_MMU_remrel_rx_frame);
}
+
//
// This function is called as a result of the "eth_drv_recv()" call above.
// Its job is to actually fetch data for a packet from the hardware once
#endif
int i;
short mlen=0, plen;
- cyg_uint16 *data=NULL;
- unsigned char *cp, cval, odd_even = 0;
-#ifdef CYGSEM_DEVS_ETH_SMSC_LAN91CXX_USE_32BIT
- cyg_uint32 val;
-#else
- cyg_uint16 val;
-#endif
+ cyg_uint8 *data=NULL;
+ short val;
+ unsigned char *cp, cval;
DEBUG_FUNCTION();
put_reg(sc, LAN91CXX_POINTER, (LAN91CXX_POINTER_RCV | LAN91CXX_POINTER_READ |
LAN91CXX_POINTER_AUTO_INCR));
- val = get_data(sc);
-
- // packet length (minus header/footer)
-#ifdef CYGSEM_DEVS_ETH_SMSC_LAN91CXX_USE_32BIT
- val = CYG_LE32_TO_CPU(val);
- plen = (val >> 16) - 6;
-#else
- val = CYG_LE16_TO_CPU(val);
- plen = get_data(sc);
- plen = CYG_LE16_TO_CPU(plen) - 6;
-#endif
-
- if( LAN91CXX_RX_STATUS_IS_ODD(cpd,val) )
- plen++;
+ get_data_init(sc);
+
+ val = get_data_short(sc);
+ plen = get_data_short(sc);
+ plen = plen - 6;
for (i = 0; i < sg_len; i++) {
- data = (cyg_uint16 *)sg_list[i].buf;
+ int clen;
+ data = (cyg_uint8 *)sg_list[i].buf;
mlen = sg_list[i].len;
- CYG_ASSERT(0 == (mlen & (sizeof(*data) - 1)) || (i == (sg_len-1)), "odd length");
+ clen = mlen;
+ if( clen > plen )
+ clen = plen;
#if DEBUG & 1
- db_printf("%s : mlen 0x%04x, plen 0x%04x\n", __FUNCTION__, mlen, plen);
+ db_printf("%s : mlen 0x%04x plen 0x%04x clen 0x%04x\n", __FUNCTION__, mlen, plen, clen);
#endif
+ mlen -= clen;
+ plen -= clen;
+
if (data) {
- while (mlen >= sizeof(*data)) {
-#ifdef CYGSEM_DEVS_ETH_SMSC_LAN91CXX_USE_32BIT
- if (!(odd_even)) { // because of the 32bit to 16bit conversion, read only every 2nd word
-#endif
- val = get_data(sc);
-#ifdef CYGSEM_DEVS_ETH_SMSC_LAN91CXX_USE_32BIT
- odd_even = 1;
- }
- else {
- val >>= 16;
- odd_even = 0;
- }
-#endif
- *data++ = val;
- mlen -= sizeof(*data);
- plen -= sizeof(*data);
+ while( clen > 0 ) {
+ *data++ = get_data_byte(sc);
+ clen--;
}
}
else { // must actively discard ie. read it from the chip anyway.
- while (mlen >= sizeof(*data)) {
-#ifdef CYGSEM_DEVS_ETH_SMSC_LAN91CXX_USE_32BIT
- if (!(odd_even)) {
-#endif
- val = get_data(sc);
-#ifdef CYGSEM_DEVS_ETH_SMSC_LAN91CXX_USE_32BIT
- odd_even = 1;
- }
- else {
- val >>= 16;
- odd_even = 0;
- }
+#if DEBUG & 1
+ db_printf("lan91cxx_recv: No data!!!!!\n");
#endif
- mlen -= sizeof(*data);
- plen -= sizeof(*data);
+ while( clen > 0 ) {
+ (void)get_data_byte(sc);
+ clen--;
}
}
- }
- if (!(odd_even)) { // read the control word only if we not already have it because of a 32bit access
- val = get_data(sc); // Read control word (and potential data) unconditionally
-#ifdef CYGSEM_DEVS_ETH_SMSC_LAN91CXX_USE_32BIT
- val = CYG_LE32_TO_CPU(val);
- if (plen & 2) {
- if (data)
- *(cyg_uint16 *)data = val & 0xffff;
- cp = (unsigned char *)data + 2;
- val >>= 16;
- mlen -= 2;
- }
-#else
- val = CYG_LE16_TO_CPU(val);
+#if DEBUG & 1
+ diag_dump_buf( sg_list[i].buf, sg_list[i].len > 64 ? 64 : sg_list[i].len );
#endif
}
- cp = (unsigned char *)data;
+ val = get_data_short(sc); // Read control word (and potential data) unconditionally
+
+ cp = (unsigned char *)data;
CYG_ASSERT(val & LAN91CXX_CONTROLBYTE_RX,
"Controlbyte is not for Rx");
put_reg(sc, LAN91CXX_MMU_COMMAND, LAN91CXX_MMU_remrel_rx_frame);
}
+
static void
lan91cxx_poll(struct eth_drv_sc *sc)
{
// Get the (unmasked) requests
event = get_reg(sc, LAN91CXX_INTERRUPT);
event = event & (event >> 8) & 0xff;
+
if (0 == event)
break;
#if 0
if (event & LAN91CXX_INTERRUPT_ERCV_INT) {
// Early receive interrupt
+ db_printf("Early receive interrupt\n");
}
else if (event & LAN91CXX_INTERRUPT_EPH_INT) {
// ethernet protocol handler failures
+ db_printf("Ethernet protocol handler failures\n");
}
else if (event & LAN91CXX_INTERRUPT_RX_OVRN_INT) {
// receive overrun
+ db_printf("Receive overrun\n");
}
else if (event & LAN91CXX_INTERRUPT_ALLOC_INT) {
// allocation interrupt
+ db_printf("Allocation interrupt\n");
}
else
#endif
for (i = 0; i < sizeof(bits); ++i) {
// Clock Low - output data
put_reg(sc, LAN91CXX_MGMT, mii_reg | bits[i]);
- HAL_DELAY_US(50);
+ CYGACC_CALL_IF_DELAY_US(50);
// Clock Hi - input data
put_reg(sc, LAN91CXX_MGMT, mii_reg | bits[i] | LAN91CXX_MGMT_MCLK);
- HAL_DELAY_US(50);
+ CYGACC_CALL_IF_DELAY_US(50);
bits[i] |= get_reg(sc, LAN91CXX_MGMT) & LAN91CXX_MGMT_MDI;
}
// Return to idle state
put_reg(sc, LAN91CXX_MGMT, mii_reg);
- HAL_DELAY_US(50);
+ CYGACC_CALL_IF_DELAY_US(50);
// Recover input data
for (value = 0, i = 0; i < 16; ++i) {
for (i = 0; i < sizeof(bits); ++i) {
// Clock Low - output data
put_reg(sc, LAN91CXX_MGMT, mii_reg | bits[i]);
- HAL_DELAY_US(50);
+ CYGACC_CALL_IF_DELAY_US(50);
// Clock Hi - input data
put_reg(sc, LAN91CXX_MGMT, mii_reg | bits[i] | LAN91CXX_MGMT_MCLK);
- HAL_DELAY_US(50);
+ CYGACC_CALL_IF_DELAY_US(50);
// bits[i] |= get_reg(sc, LAN91CXX_MGMT) & LAN91CXX_MGMT_MDI;
}
// Return to idle state
put_reg(sc, LAN91CXX_MGMT, mii_reg);
- HAL_DELAY_US(50);
+ CYGACC_CALL_IF_DELAY_US(50);
}
#endif // LAN91CXX_IS_LAN91C111
unsigned char enaddr[6]; // Controller ESA
// Function to configure the ESA - may fetch ESA from EPROM or
// RedBoot config option. Use of the 'config_enaddr()' function
- // is depreciated in favor of the 'provide_esa()' function and
+ // is deprecated in favor of the 'provide_esa()' function and
// 'hardwired_esa' boolean
void (*config_enaddr)(struct lan91cxx_priv_data* cpd);
// New function to fetch the ESA from flash via RedBoot
int within_send;
int addrsh; // Address bits to shift
int c111_reva; // true if this is a revA LAN91C111
+ cyg_uint32 data_buf;
+ int data_pos;
#ifdef KEEP_STATISTICS
struct smsc_lan91cxx_stats stats;
#endif
#include CYGDAT_DEVS_ETH_SMSC_LAN91CXX_INL
-#ifdef CYGSEM_DEVS_ETH_SMSC_LAN91CXX_USE_32BIT
+#ifdef LAN91CXX_32BIT_RX
typedef cyg_uint32 rxd_t;
#else
typedef cyg_uint16 rxd_t;
struct lan91cxx_priv_data *cpd =
(struct lan91cxx_priv_data *)sc->driver_private;
-#ifdef CYGSEM_DEVS_ETH_SMSC_LAN91CXX_USE_32BIT
+#ifdef LAN91CXX_32BIT_RX
HAL_READ_UINT32(cpd->base+((LAN91CXX_DATA_HIGH & 0x7) << cpd->addrsh), val);
#else
HAL_READ_UINT16(cpd->base+((LAN91CXX_DATA & 0x7) << cpd->addrsh), val);
+2006-11-28 Oyvind Harboe <oyvind.harboe@zylin.com>
+
+ * Fixed boot sectors for ST M29W320D
+
+2006-08-29 Yoshinori Sato <ysato@users.sourceforge.jp>
+
+ * include/flash_am29xxxxx_parts.inl [CYGHWR_DEVS_FLASH_AMD_S29GL128M]:
+ * cdl/flash_amd_am29xxxxx.cdl: Add AMD/SPANSION S29GL128M part
+
+2005-08-11 Oyvind Harboe <oyvind.harboe@zylin.com>
+
+ * include/flash_am29xxxxx_parts.inl [CYGHWR_DEVS_FLASH_ST_M29W320D]:
+ * cdl/flash_amd_am29xxxxx.cdl: Add ST M29W320D part.
+
+2006-04-03 Lars Povlsen <lpovlsen@vitesse.com>
+
+ * include/flash_am29xxxxx_parts.inl [CYGHWR_DEVS_FLASH_AMD_MX29LV128]:
+ * cdl/flash_amd_am29xxxxx.cdl: Add MXIC MX29LV128 part.
+
+ * include/flash_am29xxxxx.inl: (find_sector) Fixed dealing with
+ bootblocks. Was returning device block size even for boot blocks.
+
+2006-02-15 Stephane Deltour <stephane.deltour@barco.com>
+
+ * include/flash_am29xxxxx_parts.inl [CYGHWR_DEVS_FLASH_AMD_S29GL128N]:
+ * cdl/flash_amd_am29xxxxx.cdl: Add AMD/SPANSION S29GL128N part.
+
+ * include/flash_am29xxxxx_parts.inl [CYGHWR_DEVS_FLASH_AMD_S29GL256N]:
+ * cdl/flash_amd_am29xxxxx.cdl: Add AMD/SPANSION S29GL256N part.
+
+ * include/flash_am29xxxxx_parts.inl [CYGHWR_DEVS_FLASH_AMD_S29GL512N]:
+ * cdl/flash_amd_am29xxxxx.cdl: Add AMD/SPANSION S29GL512N part.
+
+2005-09-08 Peter Korsgaard <jacmet@sunsite.dk>
+
+ * include/flash_am29xxxxx.inl (flash_program_buf): Handle writes
+ with length not a multiple of flash word size.
+
2005-04-17 David Vrabel <dvrabel@arcom.com>
* include/flash_am29xxxxx_parts.inl [CYGHWR_DEVS_FLASH_AMD_AM29F002T]:
part in the family."
}
+ cdl_option CYGHWR_DEVS_FLASH_AMD_MX29LV128 {
+ display "MXIC MX29LV128 flash memory support"
+ default_value 0
+ implements CYGINT_DEVS_FLASH_AMD_VARIANTS
+ description "
+ When this option is enabled, the AMD flash driver will be
+ able to recognize and handle the MX29LV128
+ part in the family."
+ }
+
cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV160 {
display "AMD AM29LV160 flash memory support"
default_value 0
part in the family."
}
+ cdl_option CYGHWR_DEVS_FLASH_ST_M29W320D {
+ display "ST M29W320D flash memory support"
+ default_value 0
+ implements CYGINT_DEVS_FLASH_AMD_VARIANTS
+ description "
+ When this option is enabled, the AMD flash driver will be
+ able to recognize and handle the ST M29W320D
+ part in the family."
+ }
+
cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV200 {
display "AMD AM29LV200 flash memory support"
default_value 0
part in the family."
}
+ cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL128N {
+ display "AMD/SPANSION S29GL128N flash memory support"
+ default_value 0
+ implements CYGINT_DEVS_FLASH_AMD_VARIANTS
+ description "
+ When this option is enabled, the AMD/SPANSION flash driver will be
+ able to recognize and handle the S29GL128N
+ part in the family."
+ }
+
+ cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL256N {
+ display "AMD/SPANSION S29GL256N flash memory support"
+ default_value 0
+ implements CYGINT_DEVS_FLASH_AMD_VARIANTS
+ description "
+ When this option is enabled, the AMD/SPANSION flash driver will be
+ able to recognize and handle the S29GL256N
+ part in the family."
+ }
+
+ cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL512N {
+ display "AMD/SPANSION S29GL512N flash memory support"
+ default_value 0
+ implements CYGINT_DEVS_FLASH_AMD_VARIANTS
+ description "
+ When this option is enabled, the AMD/SPANSION flash driver will be
+ able to recognize and handle the S29GL512N
+ part in the family."
+ }
+
cdl_option CYGHWR_DEVS_FLASH_AMD_S29PL032J {
display "Spansion S29PL032J flash memory support"
default_value 0
part in the family."
}
+ cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL128M {
+ display "AMD/SPANSION S29GL128M flash memory support"
+ default_value 0
+ implements CYGINT_DEVS_FLASH_AMD_VARIANTS
+ description "
+ When this option is enabled, the AMD/SPANSION flash driver will be
+ able to recognize and handle the S29GL128M
+ part in the family."
+ }
+
cdl_option CYGHWR_DEVS_FLASH_AMD_S29PL127J {
display "Spansion S29PL127J flash memory support"
default_value 0
part in the family."
}
-}
+}
\ No newline at end of file
#define _16AS8 CYGNUM_FLASH_16AS8
#endif
-#if (_16AS8 == 0)
+
+# if (_16AS8 == 0)||CYGHWR_DEVS_FLASH_ST_M29W320D
# define FLASH_Setup_Addr1 (0x555)
# define FLASH_Setup_Addr2 (0x2AA)
# define FLASH_VendorID_Addr (0)
# define FLASH_DeviceID_Addr3 (0x1e)
# define FLASH_WP_Addr (4)
#endif
+
#define FLASH_Setup_Code1 FLASHWORD( 0xAA )
#define FLASH_Setup_Code2 FLASHWORD( 0x55 )
#define FLASH_Setup_Erase FLASHWORD( 0x80 )
const CYG_ADDRWORD mask =
flash_dev_info->bufsiz * sizeof (flash_data_t) - 1;
unsigned long rem_sect_size;
+ int remain;
// check the address is suitably aligned
if ((unsigned long)addr & (CYGNUM_FLASH_INTERLEAVE * CYGNUM_FLASH_WIDTH / 8 - 1))
f_s1 = FLASH_P2V(BANK + FLASH_Setup_Addr1);
f_s2 = FLASH_P2V(BANK + FLASH_Setup_Addr2);
rem_sect_size = 0;
+ remain = len % sizeof (flash_data_t);
len /= sizeof (flash_data_t);
while (len > 0) {
len -= nwords;
}
+ // Program remaining bytes if len not a multiple of flash word size
+ if ((FLASH_ERR_OK == res) && remain)
+ {
+ // construct final word to be programmed with 0xff in the
+ // remaining bytes
+ flash_data_t final = (flash_data_t)-1;
+ unsigned char *src = (unsigned char *) data_ptr;
+ unsigned char *dst = (unsigned char *) &final;
+
+ while (remain--)
+ *dst++ = *src++;
+
+ addr_v = FLASH_P2V(addr_p);
+
+ // Program data [byte] - 4 step sequence
+ *f_s1 = FLASH_Setup_Code1;
+ *f_s2 = FLASH_Setup_Code2;
+ *f_s1 = FLASH_Program;
+ *addr_v = final;
+
+ timeout = CYGNUM_FLASH_TIMEOUT_PROGRAM;
+ while (true) {
+ flash_data_t state = *addr_v;
+ if (final == state) {
+ break;
+ }
+
+ // Can't check for FLASH_Err since it'll fail in parallel
+ // configurations.
+
+ if (--timeout == 0) {
+ res = FLASH_ERR_DRV_TIMEOUT;
+ break;
+ }
+ }
+
+ if (FLASH_ERR_OK != res)
+ *FLASH_P2V(ROM) = FLASH_Reset;
+
+ if (*addr_v != final) {
+ // Only update return value if write operation was OK
+ if (FLASH_ERR_OK == res) res = FLASH_ERR_DRV_VERIFY;
+ }
+ }
+
// Ideally, we'd want to return not only the failure code, but also
// the address/device that reported the error.
return res;
if (flash_dev_info->bootblock) {
cyg_uint32 * bootblocks = flash_dev_info->bootblocks;
while (*bootblocks != _LAST_BOOTBLOCK) {
- int ls = flash_dev_info->block_size;
-
- if (*bootblocks++ == (res - base)) {
- while (res + *bootblocks < a) {
+ if (*bootblocks++ == (res - base)) { /* Matching offset marker */
+ while (res + *bootblocks <= a) {
res += *bootblocks++;
}
+ *remain_size = *bootblocks - (a - res);
+ break;
} else {
+ int ls = flash_dev_info->block_size;
// Skip over segment
while ((ls -= *bootblocks++) > 0) ;
}
}
-
- if (*bootblocks != _LAST_BOOTBLOCK)
- *remain_size = *bootblocks - (a - res);
}
return (flash_data_t *) res;
}
-#endif // CYGONCE_DEVS_FLASH_AMD_AM29XXXXX_INL
+#endif // CYGONCE_DEVS_FLASH_AMD_AM29XXXXX_INL
\ No newline at end of file
bufsiz : 16
},
#endif
+#ifdef CYGHWR_DEVS_FLASH_AMD_MX29LV128
+ { // MX29LV128M-T
+ long_device_id: true,
+ device_id : FLASHWORD(0x227e),
+ device_id2 : FLASHWORD(0x2211),
+ device_id3 : FLASHWORD(0x2201),
+ block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE,
+ block_count: 256,
+ device_size: 0x1000000 * CYGNUM_FLASH_INTERLEAVE,
+ base_mask : ~(0x1000000 * CYGNUM_FLASH_INTERLEAVE - 1),
+ bootblock : true,
+ bootblocks : { 0xff0000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ _LAST_BOOTBLOCK
+ },
+ banked : false,
+ bufsiz : 16
+ },
+#endif
#ifdef CYGHWR_DEVS_FLASH_AMD_AM29LV160
{ // MBM29LV160-T | AM29LV160-T
device_id : FLASHWORD(0x22c4),
bufsiz : 1
},
#endif
+#ifdef CYGHWR_DEVS_FLASH_ST_M29W320D
+ { // M29W320DT
+ device_id : FLASHWORD(0x22ca),
+ block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE,
+ block_count: 64,
+ device_size: 0x400000 * CYGNUM_FLASH_INTERLEAVE,
+ base_mask : ~(0x400000 * CYGNUM_FLASH_INTERLEAVE - 1),
+ bootblock : true,
+ bootblocks : { 0x3f0000 * CYGNUM_FLASH_INTERLEAVE, // offset
+ 0x008000 * CYGNUM_FLASH_INTERLEAVE, // size 1
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE, // size 2
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE, // size 3
+ 0x004000 * CYGNUM_FLASH_INTERLEAVE, // size 4
+ _LAST_BOOTBLOCK
+ },
+ banked : false,
+ bufsiz : 1
+ },
+ { // M29W320DB
+ device_id : FLASHWORD(0x22cb),
+ block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE,
+ block_count: 64,
+ device_size: 0x400000 * CYGNUM_FLASH_INTERLEAVE,
+ base_mask : ~(0x400000 * CYGNUM_FLASH_INTERLEAVE - 1),
+ bootblock : true,
+ bootblocks : { 0x000000 * CYGNUM_FLASH_INTERLEAVE, // offset
+ 0x004000 * CYGNUM_FLASH_INTERLEAVE, // size 1
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE, // size 2
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE, // size 3
+ 0x008000 * CYGNUM_FLASH_INTERLEAVE, // size 4
+ _LAST_BOOTBLOCK
+ },
+ banked : false,
+ bufsiz : 1
+ },
+#endif
#ifdef CYGHWR_DEVS_FLASH_AMD_AM29LV320D
{ // AM29LV320DT
device_id : FLASHWORD(0x22F6),
bufsiz : 1
},
#endif
+
+#ifdef CYGHWR_DEVS_FLASH_AMD_S29GL512N
+ { // AMD/SPANSION S29GL512N
+ long_device_id: true,
+ device_id : FLASHWORD(0x227e),
+ device_id2 : FLASHWORD(0x2223),
+ device_id3 : FLASHWORD(0x2201),
+ block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE,
+ block_count: 512,
+ device_size: 0x4000000 * CYGNUM_FLASH_INTERLEAVE,
+ base_mask : ~(0x4000000 * CYGNUM_FLASH_INTERLEAVE - 1),
+ bootblock : false,
+ banked : false,
+ bufsiz : 16
+ },
+#endif
+
+#ifdef CYGHWR_DEVS_FLASH_AMD_S29GL256N
+ { // AMD/SPANSION S29GL256N
+ long_device_id: true,
+ device_id : FLASHWORD(0x227e),
+ device_id2 : FLASHWORD(0x2222),
+ device_id3 : FLASHWORD(0x2201),
+ block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE,
+ block_count: 256,
+ device_size: 0x2000000 * CYGNUM_FLASH_INTERLEAVE,
+ base_mask : ~(0x2000000 * CYGNUM_FLASH_INTERLEAVE - 1),
+ bootblock : false,
+ banked : false,
+ bufsiz : 16
+ },
+#endif
+
+#ifdef CYGHWR_DEVS_FLASH_AMD_S29GL128N
+ { // AMD/SPANSION S29GL128N
+ long_device_id: true,
+ device_id : FLASHWORD(0x227e),
+ device_id2 : FLASHWORD(0x2221),
+ device_id3 : FLASHWORD(0x2201),
+ block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE,
+ block_count: 128,
+ device_size: 0x1000000 * CYGNUM_FLASH_INTERLEAVE,
+ base_mask : ~(0x1000000 * CYGNUM_FLASH_INTERLEAVE - 1),
+ bootblock : false,
+ banked : false,
+ bufsiz : 16
+ },
+#endif
+
#ifdef CYGHWR_DEVS_FLASH_AMD_S29GL064M
{ // AMD/SPANSION S29GL064M
long_device_id: true,
},
#endif
+#ifdef CYGHWR_DEVS_FLASH_AMD_S29GL128M
+ { // AMD/SPANSION S29GL128M
+ long_device_id: true,
+ device_id : FLASHWORD(0x227e),
+ device_id2 : FLASHWORD(0x2212),
+ device_id3 : FLASHWORD(0x2200),
+ block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE,
+ block_count: 256,
+ device_size: 0x1000000 * CYGNUM_FLASH_INTERLEAVE,
+ base_mask : ~(0x1000000 * CYGNUM_FLASH_INTERLEAVE - 1),
+ bootblock : false,
+ banked : false,
+ bufsiz : 16,
+ },
+#endif
+
#endif // 16 bit devices
-#endif // CYGONCE_DEVS_FLASH_AMD_AM29XXXXX_PARTS_INL
+#endif // CYGONCE_DEVS_FLASH_AMD_AM29XXXXX_PARTS_INL
\ No newline at end of file
-2001-07-19 Gary Thomas <gthomas@redhat.com>
+2006-05-23 Andrew Lunn <andrew.lunn@ascom.ch>
- * src/flash_program_buf.c: Fix - needs to have A16 set.
+ * src/at91_flash.c: Support for the AT91SAM7X devices.
- * src/at91_flash.c: Remove debugging code.
+2006-02-19 Oliver Munz <munz@speag.ch>
+
+ * src/at91_flash.c: Optimize the cyg_uint32 page.
+ Make the lock/unlock functions work.
-2001-07-18 Gary Thomas <gthomas@redhat.com>
+2006-02-19 Oliver Munz <munz@speag.ch>
+ Andrew Lunn <andrew.lunn@ascom.ch>
- * src/flash_query.c:
- * src/flash_program_buf.c:
- * src/flash_erase_block.c:
- * src/flash.h:
* src/at91_flash.c:
- * cdl/flash_at91.cdl: New package - AT29LV1024 FLASH for AT91/EB40.
+ * cdl/flash_at91.cdl: .
+ * ChangeLog: Flash driver for the AT91 Embedded Flash controller,
+ e.g. the AT91SAM7S devices.
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2006 eCosCentric Ltd
+// Copyright (C) 2006 Andrew Lunn <andrew.lunn@ascom.ch>
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
#
# flash_at91.cdl
#
-# FLASH memory - Hardware support on Atmel At91/EB40
+# FLASH programming for devices with the Embedded Flash Controller
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2006 eCosCentric LTD
+## Copyright (C) 2006 Andrew Lunn <andrew.lunn@ascom.ch>
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
-##
-## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
-# Author(s): gthomas
+# Author(s): dmoseley
# Original data: gthomas
-# Contributors:
-# Date: 2001-07-17
+# Contributors: Andrew Lunn, Oliver Munz
+# Date: 2000-10-25
#
#####DESCRIPTIONEND####
#
# ====================================================================
cdl_package CYGPKG_DEVS_FLASH_AT91 {
- display "Atmel At91/EB40 FLASH memory support"
+ display "at91 FLASH memory support"
parent CYGPKG_IO_FLASH
active_if CYGPKG_IO_FLASH
- requires CYGPKG_HAL_ARM_AT91
implements CYGHWR_IO_FLASH_DEVICE
- implements CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM
include_dir .
- include_files ; # none _exported_ whatsoever
-
- description "FLASH memory device support for Atmel At91/EB40 boards"
+ description "FLASH memory device support for at91 EFC"
compile at91_flash.c
+
+ cdl_option CYGBLD_DEV_FLASH_AT91_LOCKING {
+ display "Support block locking"
+ default_value 1
+ implements CYGHWR_IO_FLASH_BLOCK_LOCKING
+ description "
+ The driver will implement flash block locking when this
+ option is enabled. Note that the device implements sector
+ locking, not block locking, where sectors are bigger than
+ blocks. So the sector which contains the block will be
+ locked/unlocked
- make -priority 1 {
- flash_erase_block.o: $(REPOSITORY)/$(PACKAGE)/src/flash_erase_block.c
- $(CC) -S $(INCLUDE_PATH) $(CFLAGS) -g0 -mcpu=strongarm -fno-function-sections $(REPOSITORY)/$(PACKAGE)/src/flash_erase_block.c
- echo " .globl flash_erase_block_end" >>flash_erase_block.s
- echo "flash_erase_block_end:" >>flash_erase_block.s
- $(CC) -c -o flash_erase_block.o flash_erase_block.s
- $(AR) rcs $(PREFIX)/lib/libtarget.a flash_erase_block.o
- }
- make -priority 1 {
- flash_program_buf.o: $(REPOSITORY)/$(PACKAGE)/src/flash_program_buf.c
- $(CC) -S $(INCLUDE_PATH) $(CFLAGS) -g0 -mcpu=strongarm -fno-function-sections $(REPOSITORY)/$(PACKAGE)/src/flash_program_buf.c
- echo " .globl flash_program_buf_end" >>flash_program_buf.s
- echo "flash_program_buf_end:" >>flash_program_buf.s
- $(CC) -c -o flash_program_buf.o flash_program_buf.s
- $(AR) rcs $(PREFIX)/lib/libtarget.a flash_program_buf.o
- }
- make -priority 1 {
- flash_query.o: $(REPOSITORY)/$(PACKAGE)/src/flash_query.c
- $(CC) -S $(INCLUDE_PATH) $(CFLAGS) -g0 -mcpu=strongarm -fno-function-sections $(REPOSITORY)/$(PACKAGE)/src/flash_query.c
- echo " .globl flash_query_end" >>flash_query.s
- echo "flash_query_end:" >>flash_query.s
- $(CC) -c -o flash_query.o flash_query.s
- $(AR) rcs $(PREFIX)/lib/libtarget.a flash_query.o
+ WARNING: The errata says that these lock bits only have
+ a life of 100 cycles for the AT91SAM7S devices."
}
}
//
// at91_flash.c
//
-// Flash programming
+// Flash programming for the at91 devices which have the
+// Embedded Flash Controller.
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2006 eCosCentric Ltd
+// Copyright (C) 2006 Andrew Lunn (andrew.lunn@ascom.ch)
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
-// Contributors: gthomas
-// Date: 2001-07-17
+// Contributors: gthomas, dmoseley, Andrew Lunn, Oliver Munz
+// Date: 2000-07-26
// Purpose:
// Description:
//
//==========================================================================
#include <pkgconf/hal.h>
-#include <cyg/hal/hal_arch.h>
-#include <cyg/hal/hal_cache.h>
-#include <cyg/hal/hal_io.h>
+#include <pkgconf/devs_flash_at91.h>
+
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/infra/cyg_ass.h>
#define _FLASH_PRIVATE_
#include <cyg/io/flash.h>
-#include "flash.h"
+#include <string.h>
-#define _si(p) ((p[0]<<8)|p[1])
+#define FLASH_TIMEOUT 100000
-int
-flash_hwr_init(void)
-{
- unsigned short data[4];
- extern char flash_query, flash_query_end;
- typedef int code_fun(unsigned char *);
- code_fun *_flash_query;
- int code_len, stat, num_regions, region_size;
-
- // Copy 'program' code to RAM for execution
- code_len = (unsigned long)&flash_query_end - (unsigned long)&flash_query;
- _flash_query = (code_fun *)flash_info.work_space;
- memcpy(_flash_query, &flash_query, code_len);
- HAL_DCACHE_SYNC(); // Should guarantee this code will run
-
- stat = (*_flash_query)(data);
-#if 0
- (*flash_info.pf)("stat = %x\n", stat);
- dump_buf(data, sizeof(data));
+#ifdef CYGBLD_DEV_FLASH_AT91_LOCKING
+static cyg_uint32 sector_size;
#endif
- if (data[0] != FLASH_Atmel_code) {
- (*flash_info.pf)("Not Atmel = %x\n", data[0]);
- return FLASH_ERR_HWR;
- }
+// Disable the flash controller from erasing the page before
+// programming it
+static void
+flash_erase_before_write_disable (void)
+{
+ cyg_uint32 fmr;
+
+ HAL_READ_UINT32(AT91_MC+AT91_MC_FMR, fmr);
+ fmr = fmr | AT91_MC_FMR_NEBP;
+ HAL_WRITE_UINT32(AT91_MC+AT91_MC_FMR, fmr);
+}
- if (data[1] == (unsigned short)FLASH_ATMEL_29LV1024) {
- num_regions = 256;
- region_size = 0x100;
- } else {
- (*flash_info.pf)("Unknown device type: %x\n", data[1]);
- return FLASH_ERR_HWR;
+// Enable the flash controller to erase the page before programming
+// it
+static void
+flash_erase_before_write_enable (void)
+{
+
+ cyg_uint32 fmr;
+
+ HAL_READ_UINT32(AT91_MC+AT91_MC_FMR, fmr);
+ fmr = fmr & ~((cyg_uint32) AT91_MC_FMR_NEBP);
+ HAL_WRITE_UINT32(AT91_MC+AT91_MC_FMR, fmr);
+}
+
+// Is the flash controller ready to accept the next command?
+static __inline__ cyg_bool
+flash_controller_is_ready(void)
+CYGBLD_ATTRIB_SECTION(".2ram.flash_run_command");
+
+static __inline__ cyg_bool
+flash_controller_is_ready(void)
+{
+ cyg_uint32 fsr;
+
+ HAL_READ_UINT32(AT91_MC+AT91_MC_FSR, fsr);
+ return (fsr & AT91_MC_FSR_FRDY ? true : false);
+}
+
+// Busy loop waiting for the controller to finish the command.
+// Wait a maximum of timeout loops and then return an error.
+static __inline__ int
+flash_wait_for_controller (cyg_uint32 timeout)
+CYGBLD_ATTRIB_SECTION(".2ram.flash_run_command");
+
+static __inline__ int
+flash_wait_for_controller (cyg_uint32 timeout)
+{
+ while (!flash_controller_is_ready()){
+ timeout--;
+ if (!timeout) {
+ return FLASH_ERR_DRV_TIMEOUT;
}
+ }
+ return FLASH_ERR_OK;
+}
+
+// Execute one command on the flash controller. This code should
+// probably not be in flash
+
+static int
+flash_run_command(cyg_uint32 address,
+ cyg_uint32 command,
+ cyg_uint32 timeout)
+CYGBLD_ATTRIB_SECTION(".2ram.flash_run_command");
+
+static int
+flash_run_command(cyg_uint32 address,
+ cyg_uint32 command,
+ cyg_uint32 timeout)
+{
+ cyg_uint32 retcode;
+ cyg_uint32 fsr;
+ cyg_uint32 mask;
+ cyg_uint32 page;
+
+ page = ((cyg_uint32) address - (cyg_uint32) flash_info.start) /
+ flash_info.block_size;
+
+ // Wait for the last command to finish
+ retcode = flash_wait_for_controller(timeout);
+ if (retcode != FLASH_ERR_OK){
+ return retcode;
+ }
+
+ HAL_DISABLE_INTERRUPTS(mask);
+
+ HAL_WRITE_UINT32(AT91_MC+AT91_MC_FCR,
+ command |
+ ((page & AT91_MC_FCR_PAGE_MASK) << AT91_MC_FCR_PAGE_SHIFT) |
+ AT91_MC_FCR_KEY);
+
+ retcode = flash_wait_for_controller(timeout);
+
+ HAL_RESTORE_INTERRUPTS(mask);
+
+ if (retcode != FLASH_ERR_OK){
+ return retcode;
+ }
+
+ // Check for an error
+ HAL_READ_UINT32(AT91_MC+AT91_MC_FSR, fsr);
+
+ if ((fsr & AT91_MC_FSR_LOCKE) == AT91_MC_FSR_LOCKE)
+ return FLASH_ERR_PROTECT;
+ if ((fsr & AT91_MC_FSR_PROGE) == AT91_MC_FSR_PROGE)
+ return FLASH_ERR_PROGRAM;
- // Hard wired for now
- flash_info.block_size = region_size;
- flash_info.blocks = num_regions;
- flash_info.start = (void *)0x01010000;
- flash_info.end = (void *)(0x01010000+(num_regions*region_size));
+ return FLASH_ERR_OK;
+}
+
+// The flash is embedded in the CPU package. So return the chip
+// ID. This allows us to determine if the chip is one we support and
+// the size of the flash
+int flash_query(void *data)
+{
+ cyg_uint32 chipID1r;
+
+ HAL_READ_UINT32(AT91_DBG+AT91_DBG_C1R, chipID1r);
+
+ memcpy(data, &chipID1r, sizeof(chipID1r));
+ return FLASH_ERR_OK;
+}
+
+// Initialize the hardware. Make sure we have a flash device we know
+// how to program and determine its size, the size of the blocks, and
+// the number of blocks. The query function returns the chip ID 1
+// register which tells us about the CPU we are running on, the flash
+// size etc. Use this information to determine we have a valid setup.
+int
+flash_hwr_init(void){
+
+ cyg_uint32 chipID1r;
+ cyg_uint32 flash_mode;
+ cyg_uint8 fmcn;
+ cyg_uint32 lock_bits;
+
+ flash_query (&chipID1r);
+
+ if ((chipID1r & AT91_DBG_C1R_CPU_MASK) != AT91_DBG_C1R_ARM7TDMI)
+ goto out;
+
+ if (((chipID1r & AT91_DBG_C1R_ARCH_MASK) != AT91_DBG_C1R_ARCH_AT91SAM7Sxx) &&
+ ((chipID1r & AT91_DBG_C1R_ARCH_MASK) != AT91_DBG_C1R_ARCH_AT91SAM7Xxx))
+ goto out;
+
+ if ((chipID1r & AT91_DBG_C1R_FLASH_MASK) == AT91_DBG_C1R_FLASH_0K)
+ goto out;
+
+ switch (chipID1r & AT91_DBG_C1R_FLASH_MASK) {
+ case AT91_DBG_C1R_FLASH_32K:
+ flash_info.block_size = 128;
+ flash_info.blocks = 256;
+ lock_bits = 8;
+ break;
+ case AT91_DBG_C1R_FLASH_64K:
+ flash_info.block_size = 128;
+ flash_info.blocks = 512;
+ lock_bits = 16;
+ break;
+ case AT91_DBG_C1R_FLASH_128K:
+ flash_info.block_size = 256;
+ flash_info.blocks = 512;
+ lock_bits = 8;
+ break;
+ case AT91_DBG_C1R_FLASH_256K:
+ flash_info.block_size = 256;
+ flash_info.blocks = 1024;
+ lock_bits = 16;
+ break;
+ default:
+ goto out;
+ }
+ flash_info.buffer_size = 0;
+ flash_info.start = (void *) 0x00100000;
+ flash_info.end = (void *)(((cyg_uint32) flash_info.start) +
+ flash_info.block_size * flash_info.blocks);
+#ifdef CYGBLD_DEV_FLASH_AT91_LOCKING
+ sector_size = flash_info.block_size * flash_info.blocks / lock_bits;
+#endif
+ // Set the FLASH clock to 1.5 microseconds based on the MCLK. This
+ // assumes the CPU is still running from the PLL clock as defined in
+ // the HAL CDL and the HAL startup code.
+ fmcn = CYGNUM_HAL_ARM_AT91_CLOCK_SPEED / 1000000 * 1.5;
+ HAL_READ_UINT32(AT91_MC+AT91_MC_FMR, flash_mode);
+ flash_mode = flash_mode & ~AT91_MC_FMR_FMCN_MASK;
+ flash_mode = flash_mode | (fmcn << AT91_MC_FMR_FMCN_SHIFT);
+ HAL_WRITE_UINT32(AT91_MC+AT91_MC_FMR, flash_mode);
+
+ return FLASH_ERR_OK;
+
+ out:
+ (*flash_info.pf)("Can't identify FLASH, sorry, ChipID1 %x\n",
+ chipID1r );
+ return FLASH_ERR_HWR;
+}
+
+// Erase a block. The flash controller does not have a command to
+// erase a block. So instead we setup the controller to do a program
+// writing all 0xff with an erase operation first.
+int
+flash_erase_block (volatile unsigned long block)
+{
+ cyg_uint32 retcode;
+ cyg_uint32 *buffer;
+ cyg_uint32 *end;
+
+ buffer = (cyg_uint32 *) block;
+ end = (cyg_uint32 *) (block + flash_info.block_size);
+
+ while (buffer < end){
+ *buffer = (cyg_uint32) 0xffffffff;
+ buffer++;
+ }
+
+ flash_erase_before_write_enable();
+ retcode = flash_run_command(block,
+ AT91_MC_FCR_START_PROG,
+ FLASH_TIMEOUT);
+
+ return retcode;
+}
+
+// Write into the flash. The datasheet says that performing 8 or 16bit
+// accesses results in unpredictable corruption. So the current code
+// checks that these conditions are upheld. It would be possible to
+// perform extra reads and masking operation to support writing to
+// none word assigned addresses or not multiple or a word length.
+int
+flash_program_buf (volatile unsigned long addr, unsigned long *data, int len)
+{
+ cyg_uint32 retcode;
+ volatile unsigned long *target;
+
+ CYG_ASSERT(len % 4 == 0, "Only word writes allowed by current code");
+ CYG_ASSERT(addr % 4 == 0, "Address must be word aligned for current code");
+
+ target = (volatile unsigned long *)addr;
+
+ while (len > 0) {
+ *target = *data;
+ data++;
+ target++;
+ len = len - sizeof(unsigned long);
+ }
+
+ flash_erase_before_write_disable();
+ retcode = flash_run_command(addr,
+ AT91_MC_FCR_START_PROG,
+ FLASH_TIMEOUT);
+
+ return retcode;
+}
+
+#ifdef CYGBLD_DEV_FLASH_AT91_LOCKING
+// Unlock a block. This is not strictly possible, we can only lock and
+// unlock sectors. This will unlock the sector which contains the
+// block.
+int
+flash_unlock_block(volatile unsigned long block, int block_size, int blocks)
+{
+ cyg_uint32 sector;
+ cyg_uint32 retcode;
+ cyg_uint32 status;
+
+ sector = (((cyg_uint32) block) - (cyg_uint32) flash_info.start) /
+ sector_size;
+
+ HAL_READ_UINT32(AT91_MC + AT91_MC_FSR, status);
+
+ if (status & (1 << (sector + 16))){
+ retcode = flash_run_command(block,
+ AT91_MC_FCR_UNLOCK,
+ FLASH_TIMEOUT);
+ return retcode;
+ } else {
return FLASH_ERR_OK;
+ }
}
-// Map a hardware status to a package error
+// Lock a block. This is not strictly possible, we can only lock and
+// unlock sectors. This will lock the sector which contains the
+// block.
int
-flash_hwr_map_error(int err)
+flash_lock_block(volatile unsigned long block, int block_size, int blocks)
{
- if (err) {
- (*flash_info.pf)("Err = %x\n", err);
- return FLASH_ERR_PROGRAM;
- } else {
- return FLASH_ERR_OK;
- }
+ cyg_uint32 sector;
+ cyg_uint32 retcode;
+ cyg_uint32 status;
+
+ sector = (((cyg_uint32) block) - (cyg_uint32) flash_info.start) /
+ sector_size;
+
+ HAL_READ_UINT32(AT91_MC + AT91_MC_FSR, status);
+
+ if (!(status & (1 << (sector + 16)))){
+ retcode = flash_run_command(block,
+ AT91_MC_FCR_LOCK,
+ FLASH_TIMEOUT);
+
+ return retcode;
+ } else {
+ return FLASH_ERR_OK;
+ }
+}
+#endif
+
+// Map a hardware status to a package error. NOP since the errors are
+// already mapped.
+int flash_hwr_map_error(int err){
+
+ return err;
}
// See if a range of FLASH addresses overlaps currently running code
-bool
-flash_code_overlaps(void *start, void *end)
-{
+bool flash_code_overlaps(void *start, void *end){
+
extern char _stext[], _etext[];
return ((((unsigned long)&_stext >= (unsigned long)start) &&
include_dir cyg/io
+ cdl_component CYGHWR_DEVS_FLASH_MMC {
+ display "MXC platform MMC card support"
+ default_value 0
+ requires { CYGSEM_IO_FLASH_READ_INDIRECT == 1 }
+ description "
+ When this option is enabled, it indicates MMC card is
+ supported on the MXC platforms"
+ define_proc {
+ puts $::cdl_system_header "#define MXCFLASH_SELECT_MMC"
+ }
+ compile mxc_mmc.c
+
+ cdl_option CYGHWR_DEVS_FLASH_MMC_ESDHC {
+ display "MXC platform MMC card for newer SDHC controllers"
+ active_if { CYGPKG_HAL_ARM_MX37_3STACK || CYGPKG_HAL_ARM_MX35_3STACK || CYGPKG_HAL_ARM_MX25_3STACK || CYGPKG_HAL_ARM_MX51}
+ default_value 1
+ requires { CYGSEM_IO_FLASH_READ_INDIRECT == 1 }
+ compile mxcmci_core.c mxcmci_host.c mxcmci_mmc.c mxcmci_sd.c mxcmci_sd.c
+ }
+
+ cdl_option CYGHWR_DEVS_FLASH_MMC_SD {
+ display "MXC platform MMC card for older MMC/SD controllers"
+ active_if { CYGPKG_HAL_ARM_MX31_3STACK || CYGPKG_HAL_ARM_MX31ADS }
+ default_value 0
+ requires { CYGSEM_IO_FLASH_READ_INDIRECT == 1 }
+ compile card_mx32.c
+ }
+ }
+
cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
display "MXC platform NOR flash memory support"
default_value 0
description "
- When this option is enabled, it indicates NOR flash is
+ When this option is enabled, it indicates NOR flash is
supported on the MXC platforms"
define_proc {
puts $::cdl_system_header "#define MXCFLASH_SELECT_NOR"
default_value 0
requires { CYGSEM_IO_FLASH_READ_INDIRECT == 1 }
description "
- When this option is enabled, it indicates NAND flash is
+ When this option is enabled, it indicates NAND flash is
supported on the MXC platforms"
define_proc {
puts $::cdl_system_header "#define MXCFLASH_SELECT_NAND"
+ puts $::cdl_system_header "#define CYGIMP_FLASH_ENABLE mxc_flash_enable"
+ puts $::cdl_system_header "#define CYGIMP_FLASH_DISABLE mxc_flash_disable"
}
compile mxc_nfc.c
}
+
+ cdl_option CYGHWR_DEVS_FLASH_IMX_SPI_NOR {
+ display "i.MX platform SPI NOR flash memory support"
+ default_value 0
+ requires { CYGHWR_DEVS_FLASH_MXC_NOR == 1 }
+ description "
+ When this option is enabled, it indicates SPI NOR flash is
+ supported on the i.MX platforms"
+ define_proc {
+ puts $::cdl_system_header "#define IMXFLASH_SELECT_SPI_NOR"
+ }
+ compile spi_nor.c
+ }
+
+ cdl_option CYGHWR_DEVS_FLASH_MXC_ATA {
+ display "MXC platform ATA support"
+ default_value 0
+ description "
+ When this option is enabled, it indicates ATA is
+ supported on the MXC platforms"
+ define_proc {
+ puts $::cdl_system_header "#define MXCFLASH_SELECT_ATA"
+ }
+ compile mxc_ata.c
+ }
+
cdl_component CYGPKG_DEVS_FLASH_NAND_BBT_IN_FLASH {
display "Use a flash based Bad Block Table"
flavor none
no_define
+ active_if CYGHWR_DEVS_FLASH_MXC_NAND
cdl_option CYGHWR_DEVS_FLASH_MXC_BBT_IN_FLASH {
- requires { CYGHWR_DEVS_FLASH_MXC_NAND == 1 }
+ default_value 1
description "
When this option is enabled, the driver will search for a flash
based bad block table"
define_proc {
puts $::cdl_system_header "#define MXCFLASH_FLASH_BASED_BBT"
+ puts $::cdl_system_header "#include <pkgconf/devs_flash_onmxc.h>"
}
}
cdl_component CYGHWR_FLASH_NAND_BBT_HEADER {
display "header file defining the NAND BBT descriptor"
flavor booldata
default_value 0
- requires { CYGHWR_DEVS_FLASH_MXC_NAND == 1 }
description "
defines the name of the header file that describes the BBT layout"
+ }
+ cdl_option CYGNUM_FLASH_NAND_BBT_BLOCKS {
+ display "Number of blocks to reserve for BBT"
+ flavor data
+ default_value 4
+ description "
+ Number of blocks to reserve for BBT"
}
}
+
cdl_option CYGHWR_DEVS_FLASH_MXC_MULTI {
display "MXC platform multi flash memory support"
default_value 1
- active_if {CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR}
+ active_if {(CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MXC_NOR) ||
+ (CYGHWR_DEVS_FLASH_MXC_NAND && CYGHWR_DEVS_FLASH_MMC) ||
+ (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)}
description "
- When this option is enabled, it indicates multi flashes are
+ When this option is enabled, it indicates multi flashes are
supported on the MXC platforms (like NAND and NOR)"
define_proc {
puts $::cdl_system_header "#define MXCFLASH_SELECT_MULTI"
When this option is enabled, it indicates 0xFFFF is used for
the NAND reset command instead of 0xFF."
}
-}
\ No newline at end of file
+}
//
//==========================================================================
-#define NFC_DEBUG_MIN 1
-#define NFC_DEBUG_MED 2
-#define NFC_DEBUG_MAX 3
-#define NFC_DEBUG_DEF NFC_DEBUG_MED
+enum {
+ MXC_NFC_V1 = 0x10,
+ MXC_NFC_V1_1 = 0x11,
+ MXC_NFC_V2 = 0x20,
+ MXC_NFC_V3 = 0x30,
+};
+
+enum {
+ NFC_DEBUG_NONE,
+ NFC_DEBUG_MIN,
+ NFC_DEBUG_MED,
+ NFC_DEBUG_MAX,
+};
+#define NFC_DEBUG_DEF NFC_DEBUG_NONE
extern int _mxc_boot;
typedef unsigned short u16;
typedef unsigned int u32;
typedef unsigned char u8;
+typedef unsigned long long u64;
//----------------------------------------------------------------------------
// Common device details.
-#define FLASH_Read_ID (0x90)
+#define FLASH_Read_ID 0x90
#ifdef CYGHWR_DEVS_FLASH_MXC_NAND_RESET_WORKAROUND
-#define FLASH_Reset 0xFFFF
+#define FLASH_Reset 0xFFFF
#else
-#define FLASH_Reset (0xFF)
+#define FLASH_Reset 0xFF
#endif
-#define FLASH_Read_Mode1 (0x00)
-#define FLASH_Read_Mode1_LG (0x30)
-#define FLASH_Read_Mode2 (0x01)
-#define FLASH_Read_Mode3 (0x50)
-#define FLASH_Program (0x10)
-#define FLASH_Send_Data (0x80)
-#define FLASH_Status (0x70)
-#define FLASH_Block_Erase (0x60)
-#define FLASH_Start_Erase (0xD0)
+#define FLASH_Read_Mode1 0x00
+#define FLASH_Read_Mode1_LG 0x30
+#define FLASH_Read_Mode2 0x01
+#define FLASH_Read_Mode3 0x50
+#define FLASH_Program 0x10
+#define FLASH_Send_Data 0x80
+#define FLASH_Status 0x70
+#define FLASH_Block_Erase 0x60
+#define FLASH_Start_Erase 0xD0
enum nfc_page_area {
- NFC_SPARE_ONLY,
- NFC_MAIN_ONLY,
+ NFC_SPARE_ONLY,
+ NFC_MAIN_ONLY,
};
enum {
- MXC_NAND_8_BIT = 8,
- MXC_NAND_16_BIT = 16,
+ MXC_NAND_8_BIT = 8,
+ MXC_NAND_16_BIT = 16,
};
enum {
- NAND_SLC = 0,
- NAND_MLC = 1,
+ NAND_SLC = 0,
+ NAND_MLC = 1,
};
// read column 464-465 byte but only 464 for bad block marker
#define CYGONCE_DEVS_FLASH_MXC_NAND_PARTS_INL
//==========================================================================
//
-// mxc_nfc.h
+// mxc_nfc.h
//
-// Flash programming to support NAND flash on Freescale MXC platforms
+// Flash programming to support NAND flash on Freescale MXC platforms
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
-// Author(s): Kevin Zhang <k.zhang@freescale.com>
+// Author(s): Kevin Zhang <k.zhang@freescale.com>
// Contributors: Kevin Zhang <k.zhang@freescale.com>
-// Date: 2006-01-23
-// Purpose:
-// Description:
-//
+// Date: 2006-01-23
+// Purpose:
+// Description:
+//
//####DESCRIPTIONEND####
//
//==========================================================================
+/*
+ * calculate the index of the factory bad block marker within the NFC buffer
+ * from the page size of the NAND device and the NFC buffer size
+*/
+#define MXC_NAND_BI_OFF(pg_sz, sp_sz) ((pg_sz) / (sp_sz) * 512 + (pg_sz) % (sp_sz))
+
{
- device_id : 0x35ec, // Samsung K9F5608x0C (on EVB SDR memory card)
- device_id2 : 0xFFFF,
- device_id3 : 0xFFFF,
- device_id4 : 0xFFFF,
- page_size : 512,
- spare_size : 16,
- pages_per_block : 32,
- block_size : 0x4000,
- block_count: 2048,
- device_size: 0x2000000,
- base_mask : ~(0x2000000 - 1),
- port_size : MXC_NAND_8_BIT,
- type : NAND_SLC,
+ device_id : 0x35ec, // Samsung K9F5608x0C (on EVB SDR memory card)
+ device_id2 : 0xFFFF,
+ device_id3 : 0xFFFF,
+ device_id4 : 0xFFFF,
+ col_cycle : 1,
+ row_cycle : 2,
+ page_size : 512,
+ spare_size : 16,
+ pages_per_block : 32,
+ block_size : 0x4000,
+ block_count: 2048,
+ device_size: 0x2000000,
+ port_size : MXC_NAND_8_BIT,
+ type : NAND_SLC,
+ options : NAND_BBT_SCAN2NDPAGE,
+ fis_start_addr: 0x80000, // first 0.5MB reserved for Redboot
+ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables
+ // BI is fixed at 5th byte in the spare area. This value is not used
+ bi_off : 0,
vendor_info: "Samsung K9F5608x0C 8-bit 512B page 32MB",
+ max_bad_blk: 20,
+ },
+ {
+ device_id : 0x36ec, // Samsung K9F1208R0B (on MXC91131 EVB mem1)
+ device_id2 : 0xFFFF,
+ device_id3 : 0xFFFF,
+ device_id4 : 0xFFFF,
+ col_cycle : 1,
+ row_cycle : 3,
+ page_size : 512,
+ spare_size : 16,
+ pages_per_block : 32,
+ block_size : 0x4000,
+ block_count: 4096,
+ device_size: 0x4000000,
+ port_size : MXC_NAND_8_BIT,
+ type : NAND_SLC,
+ options : NAND_BBT_SCAN2NDPAGE,
+ fis_start_addr: 0x80000, // first 0.5MB reserved for Redboot
+ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables
+ // BI is fixed at 5th byte in the spare area. This value is not used
+ bi_off : 0,
+ vendor_info: "Samsung K9F1208R0B 8-bit 512B page 64MB",
+ max_bad_blk: 20,
+ },
+ {
+ device_id : 0x76ec, // Samsung K9F1208x0B
+ device_id2 : 0xFFFF,
+ device_id3 : 0xFFFF,
+ device_id4 : 0xFFFF,
+ col_cycle : 1,
+ row_cycle : 3,
+ page_size : 512,
+ spare_size : 16,
+ pages_per_block : 32,
+ block_size : 0x4000,
+ block_count: 4096,
+ device_size: 0x4000000,
+ port_size : MXC_NAND_8_BIT,
+ type : NAND_SLC,
+ options : NAND_BBT_SCAN2NDPAGE,
+ fis_start_addr: 0x80000, // first 0.5MB reserved for Redboot
+ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables
+ // BI is fixed at 5th byte in the spare area. This value is not used
+ bi_off : 0,
+ vendor_info: "Samsung K9F1208x0B 8-bit 512B page 64MB",
+ max_bad_blk: 20,
},
{
- device_id : 0x36ec, // Samsung K9F1208R0B (on MXC91131 EVB mem1)
- device_id2 : 0xFFFF,
- device_id3 : 0xFFFF,
- device_id4 : 0xFFFF,
- page_size : 512,
- spare_size : 16,
- pages_per_block : 32,
- block_size : 0x4000,
- block_count: 4096,
- device_size: 0x4000000,
- base_mask : ~(0x4000000 - 1),
- port_size : MXC_NAND_8_BIT,
- type : NAND_SLC,
- vendor_info: "Samsung K9F1208R0B 8-bit 512B page 128MB",
- },
- {
- device_id : 0x79ec, // Samsung K9K1G08x0B (MX31 ADS 512B page 8 bit)
- device_id2 : 0xFFFF,
- device_id3 : 0xFFFF,
- device_id4 : 0xFFFF,
- page_size : 512,
- spare_size : 16,
- pages_per_block : 32,
- block_size : 0x4000,
- block_count: 4096 * 2,
- device_size: 0x4000000 * 2,
- base_mask : ~(0x4000000 * 2 - 1),
- port_size : MXC_NAND_8_BIT,
- type : NAND_SLC,
+ device_id : 0x79ec, // Samsung K9K1G08x0B (MX31 ADS 512B page 8 bit)
+ device_id2 : 0xFFFF,
+ device_id3 : 0xFFFF,
+ device_id4 : 0xFFFF,
+ col_cycle : 1,
+ row_cycle : 3,
+ page_size : 512,
+ spare_size : 16,
+ pages_per_block : 32,
+ block_size : 0x4000,
+ block_count: 4096 * 2,
+ device_size: 0x4000000 * 2,
+ port_size : MXC_NAND_8_BIT,
+ type : NAND_SLC,
+ options : NAND_BBT_SCAN2NDPAGE,
+ fis_start_addr: 0x80000, // first 0.5MB reserved for Redboot
+ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables
+ // BI is fixed at 5th byte in the spare area. This value is not used
+ bi_off : 0,
vendor_info: "Samsung K9K1G08x0B 8-bit 512B page 128MB",
+ max_bad_blk: 20,
},
{
- device_id : 0xf1ec, // Samsung K9F1G08U0A (MX31 ADS 2KB page 8 bit nand)
- device_id2 : 0xFFFF,
- device_id3 : 0xFFFF,
- device_id4 : 0xFFFF,
- page_size : 512*4,
- spare_size : 16*4,
- pages_per_block : 64,
- block_size : 64*2*1024,
- block_count: 1024,
- device_size: 128*1024*1024, // 128MB device =0x08000000
- port_size : MXC_NAND_8_BIT,
- base_mask : ~(0x08000000 - 1),
- type : NAND_SLC,
+ device_id : 0xf1ec, // Samsung K9F1G08U0A (MX31 ADS 2KB page 8 bit nand)
+ device_id2 : 0xFFFF,
+ device_id3 : 0xFFFF,
+ device_id4 : 0xFFFF,
+ col_cycle : 2,
+ row_cycle : 2,
+ page_size : 512 * 4,
+ spare_size : 16 * 4,
+ pages_per_block : 64,
+ block_size : 64 * 2 * 1024,
+ block_count: 1024,
+ device_size: 128 * 1024 * 1024, // 128MB device =0x08000000
+ port_size : MXC_NAND_8_BIT,
+ type : NAND_SLC,
+ options : NAND_BBT_SCAN2NDPAGE,
+ fis_start_addr: 0x80000, // first 0.5MB reserved for Redboot
+ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables
+ bi_off : MXC_NAND_BI_OFF(2048, 512 + 16),
vendor_info: "Samsung K9F1G08U0A 8-bit 2K page 128MB",
+ max_bad_blk: 20,
},
{
- device_id : 0xa1ec, // Samsung K9F1G08R0A (2KB page 8 bit nand)
- device_id2 : 0xFFFF,
- device_id3 : 0xFFFF,
- device_id4 : 0xFFFF,
- page_size : 512*4,
- spare_size : 16*4,
- pages_per_block : 64,
- block_size : 64*2*1024,
- block_count: 1024,
- device_size: 0x08000000, // 128MB device =0x08000000
- port_size : MXC_NAND_8_BIT,
- base_mask : ~(0x08000000 - 1),
- type : NAND_SLC,
+ device_id : 0xa1ec, // Samsung K9F1G08R0A (2KB page 8 bit nand)
+ device_id2 : 0xFFFF,
+ device_id3 : 0xFFFF,
+ device_id4 : 0xFFFF,
+ col_cycle : 2,
+ row_cycle : 2,
+ page_size : 512 * 4,
+ spare_size : 16 * 4,
+ pages_per_block : 64,
+ block_size : 64 * 2 * 1024,
+ block_count: 1024,
+ device_size: 0x08000000, // 128MB device =0x08000000
+ port_size : MXC_NAND_8_BIT,
+ type : NAND_SLC,
+ options : NAND_BBT_SCAN2NDPAGE,
+ fis_start_addr: 0x80000, // first 0.5MB reserved for Redboot
+ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables
+ // BI is at 2048th byte out of factory (0-indexed)
+ // our NFC read out data like this:
+ // | 528 | 528 | 528 | 528 |
+ // P1 P2 P3 P4
+ // 0-527|528-1055/1056-1583/1584-2111
+ // So the last subpage starts: 1584th byte. 2048th byte is at offset 464.
+ bi_off : MXC_NAND_BI_OFF(2048, 512 + 16),
vendor_info: "Samsung K9F1G08R0A 8-bit 2K page 128MB",
+ max_bad_blk: 20,
},
{
- device_id : 0xd5ec, // Samsung K9LAG08U0M (2KB page 2G x 8 bit MLC nand)
- device_id2 : 0x2555,
- device_id3 : 0xFFFF,
- device_id4 : 0xFFFF,
- page_size : 512*4,
- spare_size : 16*4,
- pages_per_block : 128,
- block_size : 128*2*1024,
- block_count: 8192,
- device_size: 0x80000000, // 2GB device =0x8000,0000
- port_size : MXC_NAND_8_BIT,
- base_mask : ~(0x80000000 - 1),
- type : NAND_MLC,
+ device_id : 0xaaec, // Samsung K9F2G08R0A (2KB page 8 bit nand)
+ device_id2 : 0xFFFF,
+ device_id3 : 0xFFFF,
+ device_id4 : 0xFFFF,
+ col_cycle : 2,
+ row_cycle : 3,
+ page_size : 512 * 4,
+ spare_size : 16 * 4,
+ pages_per_block : 64,
+ block_size : 64 * 2 * 1024,
+ block_count: 2048,
+ device_size: 0x10000000, // 256MB device =0x10000000
+ port_size : MXC_NAND_8_BIT,
+ type : NAND_SLC,
+ options : NAND_BBT_SCAN2NDPAGE,
+ fis_start_addr: 0x80000, // first 0.5MB reserved for Redboot
+ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables
+ // BI is at 2048th byte out of factory (0-indexed)
+ // our NFC read out data like this:
+ // | 528 | 528 | 528 | 528 |
+ // P1 P2 P3 P4
+ // 0-527|528-1055/1056-1583/1584-2111
+ // So the last subpage starts: 1584th byte. 2048th byte is at offset 464.
+ bi_off : MXC_NAND_BI_OFF(2048, 512 + 16),
+ vendor_info: "Samsung K9F2G08R0A 8-bit 2K page 256MB",
+ max_bad_blk: 20,
+ },
+ {
+ device_id : 0xd5ec, // Samsung K9LAG08U0M (2KB page 2G x 8 bit MLC nand)
+ device_id2 : 0x2555, // interleaved NAND used on MX51 TO 1.0
+ device_id3 : 0xFFFF,
+ device_id4 : 0xFFFF,
+ col_cycle : 2,
+ row_cycle : 3,
+ page_size : 512 * 4,
+ spare_size : 16 * 4,
+ pages_per_block : 128,
+ block_size : 128 * 2 * 1024,
+ block_count: 8192,
+ device_size: 0x80000000, // 2GB device =0x8000,0000
+ port_size : MXC_NAND_8_BIT,
+ type : NAND_MLC,
+ options : NAND_BBT_SCANLSTPAGE,
+ fis_start_addr: 0x80000, // first 0.5MB reserved for Redboot
+ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables
+ // BI is at 2048th byte out of factory (0-indexed)
+ // our NFC read out data like this:
+ // | 528 | 528 | 528 | 528 |
+ // P1 P2 P3 P4
+ // 0-527|528-1055/1056-1583/1584-2111
+ // So the last subpage starts: 1584th byte. 2048th byte is at offset 464.
+ bi_off : MXC_NAND_BI_OFF(2048, 512 + 16), // BUF3 offset + 464
vendor_info: "Samsung K9LAG08U0M 8-bit 2K page 2GB MLC",
+ max_bad_blk: 20,
+ },
+ {
+ device_id : 0xd3ec, // Samsung K9G8G08U0M (2KB page 1G x 8 bit MLC nand)
+ device_id2 : 0x2514, // default for MX51
+ device_id3 : 0xFFFF,
+ device_id4 : 0xFFFF,
+ col_cycle : 2,
+ row_cycle : 3,
+ page_size : 512 * 4,
+ spare_size : 16 * 4,
+ pages_per_block : 128,
+ block_size : 128 * 2 * 1024,
+ block_count: 4096,
+ device_size: 0x40000000,
+ port_size : MXC_NAND_8_BIT,
+ type : NAND_MLC,
+ options : NAND_BBT_SCANLSTPAGE,
+ fis_start_addr: 0x80000, // first 0.5MB reserved for Redboot
+ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables
+ // BI is at 2048th byte out of factory (0-indexed)
+ // our NFC read out data like this:
+ // | 528 | 528 | 528 | 528 |
+ // P1 P2 P3 P4
+ // 0-527|528-1055/1056-1583/1584-2111
+ // So the last subpage starts: 1584th byte. 2048th byte is at offset 464.
+ bi_off : MXC_NAND_BI_OFF(2048, 512 + 16), // BUF3 offset + 464
+ vendor_info: "Samsung K9G8G08U0M 8-bit 2K page 1GB MLC",
+ max_bad_blk: 20,
+ },
+ {
+ device_id : 0xd5ec,
+ device_id2 : 0xb614,
+ device_id3 : 0xec74,
+ device_id4 : 0xFFFF,
+ col_cycle : 2,
+ row_cycle : 3,
+ page_size : 512 * 4,
+ spare_size : 16 * 4,
+ pages_per_block : 128,
+ block_size : 128 * 2 * 1024,
+ block_count: 8192,
+ device_size: 0x80000000, // 2GB device =0x8000,0000
+ port_size : MXC_NAND_8_BIT,
+ type : NAND_MLC,
+ vendor_info: "Samsung K9HCG08U5M 8-bit 2K page 8GB Quad MLC",
+ max_bad_blk: 20,
+ },
+ {
+ device_id : 0xd7ec, // Samsung K9LBG08U0M 8-bit 4K page 4GB MLC. - used on MX37
+ device_id2 : 0xb655,
+ device_id3 : 0xec78,
+ device_id4 : 0xFFFF,
+ col_cycle : 2,
+ row_cycle : 3,
+ page_size : 512 * 8,
+ spare_size : 16 * 8,
+ pages_per_block : 128,
+ block_size : 128 * 4 * 1024,
+ block_count: 8192 / 2, // for now
+ device_size: 0x80000000, // only 2GB supported
+ port_size : MXC_NAND_8_BIT,
+ type : NAND_MLC,
+ options : NAND_BBT_SCANLSTPAGE,
+ fis_start_addr: 0x100000, // first 1MB reserved for Redboot
+ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables
+ // BI is at 4096th byte out of factory (0-indexed)
+ // our NFC read out data like this:
+ // | 528 | 528 | 528 | 528 | 528 | 528 | 528 | 528 |
+ // P1 P2 P3 P4 P5 P6 P7 P8
+ // |0-527|528-1055/1056-1583/1584-2111/2112-2639/2640-3167/3168-3695/3696-4223 |
+ // So the last subpage starts: 3696th byte. 4096th byte is at offset 400.
+ bi_off : MXC_NAND_BI_OFF(4096, 512 + 16),
+ vendor_info: "Samsung K9LBG08U0M 8-bit 4K page 4GB MLC. Only 2GB supported.",
+ max_bad_blk: 20,
+ },
+ {
+ device_id : 0xD5AD, // Hynix HY27UV08BG5M 8-bit 2K page ?? GB MLC nand
+ device_id2 : 0xA555,
+ device_id3 : 0xAD68,
+ col_cycle : 2,
+ row_cycle : 3,
+ page_size : 512 * 4,
+ spare_size : 16 * 4,
+ pages_per_block : 128,
+ block_size : 128 * 2 * 1024,
+ block_count: 2 * 2 * 2048,
+ device_size: 0x80000000, // 2GB device
+ port_size : MXC_NAND_8_BIT,
+ type : NAND_MLC,
+ vendor_info: "Hynix HY27UV08BG5M 8-bit 2K page ?? GB MLC nand",
+ max_bad_blk: 20,
+ },
+ {
+ device_id : 0xAD, // Hynix HYD0SQH0MF3(P) 16-bit 2K page 128MB (1Gb) MLC nand
+ device_id2 : 0xB1,
+ device_id3 : 0x80,
+ device_id4 : 0x55,
+ col_cycle : 2,
+ row_cycle : 2,
+ page_size : 512 * 4,
+ spare_size : 16 * 4,
+ pages_per_block : 64,
+ block_size : 64 * 2 * 1024,
+ block_count: 1024,
+ device_size: 0x08000000, // 128MB device =0x0800,0000
+ port_size : MXC_NAND_16_BIT,
+ type : NAND_MLC,
+ vendor_info: "Hynix HYD0SQH0MF3(P) 16-bit 2K page 128MB MLC nand",
+ max_bad_blk: 20,
+ },
+ {
+ // Micron 29F32G08TAA 8-bit 2K page 4GB (32Gb) nand
+ // Even though it is 4GB device, so far we only use 2GB. Will work on it more
+ // once we have the schematic for this MX32 3DS board with Wolfson
+ // Note: this device doesn't work for NAND boot since it requires a
+ // "reset" command issued to the NAND flash which is missing
+ // from our NFC controller on i.MX31/32 and earlier.
+ device_id : 0xD52C,
+ device_id2 : 0xA5D5,
+ device_id3 : 0xFFFF,
+ device_id4 : 0xFFFF,
+ col_cycle : 2,
+ row_cycle : 3,
+ page_size : 512 * 4,
+ spare_size : 16 * 4,
+ pages_per_block : 128,
+ block_size : 128 * 2 * 1024,
+ block_count: 2 * 2 * 2048,
+ device_size: 0x80000000, // 2GB device
+ port_size : MXC_NAND_8_BIT,
+ type : NAND_MLC,
+ vendor_info: "Micron 29F32G08TAA 16-bit 2K page 4GB (32Gb) nand",
+ max_bad_blk: 20,
+ },
+ {
+ // Micron MT29F8G08AAA 8-bit 4K page 1GB (8Gb) nand, 218B spare
+ device_id : 0xD32C,
+ device_id2 : 0x2E90,
+ device_id3 : 0xFFFF,
+ device_id4 : 0xFFFF,
+ col_cycle : 2,
+ row_cycle : 3,
+ page_size : 512 * 8,
+ spare_size : 218,
+ pages_per_block : 64,
+ block_size : 128 * 2 * 1024,
+ block_count: 2 * 2048,
+ device_size: 0x40000000, // 2GB device
+ port_size : MXC_NAND_8_BIT,
+ type : NAND_SLC,
+ options : NAND_BBT_SCANLSTPAGE,
+ fis_start_addr: 0x100000, // first 1MB reserved for Redboot
+ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables
+ // BI is at 4096th byte out of factory (0-indexed)
+ // our NFC read out data like this:
+ // | 538 | 538 | 538 | 538 | 538 | 538 | 538 | 538 |
+ // P1 P2 P3 P4 P5 P6 P7 P8
+ // |0-537|538-1075|1076-1613|1614-2151|2152-2689|2690-3227|3228-3765|3766-4303 |
+ // So the last subpage starts: 3696th byte. 4096th byte is at offset 330.
+ bi_off : MXC_NAND_BI_OFF(4096, 512 + 26),
+ vendor_info: "Micron MT29F8G08AAA 8-bit 4K page 1GB (8Gb) nand, 218B spare",
+ max_bad_blk: 20,
},
{
- device_id : 0xAD, // Hynix HYD0SQH0MF3(P) (2KB page 2G x 16 bit MLC nand)
- device_id2 : 0xB1,
- device_id3 : 0x80,
- device_id4 : 0x55,
- page_size : 512*4,
- spare_size : 16*4,
- pages_per_block : 64,
- block_size : 64*2*1024,
- block_count: 1024,
- device_size: 0x08000000, // 128MB device =0x0800,0000
- port_size : MXC_NAND_16_BIT,
- base_mask : ~(0x08000000 - 1),
- type : NAND_MLC,
- vendor_info: "Hynix HYD0SQH0MF3",
+ // Micron MT29F32G08QAA 8-bit 4K page 4GB (32Gb) nand, 218B spare
+ device_id : 0xD52C,
+ device_id2 : 0x3E94,
+ device_id3 : 0xFF74,
+ device_id4 : 0xFFFF,
+ col_cycle : 2,
+ row_cycle : 3,
+ page_size : 512 * 8,
+ spare_size : 218,
+ pages_per_block : 128,
+ block_size : 128 * 8 * 512,
+ block_count: 4096,
+ device_size: 0x80000000, // 2GB device
+ port_size : MXC_NAND_8_BIT,
+ type : NAND_MLC,
+ options : NAND_BBT_SCANLSTPAGE,
+ fis_start_addr: 0x100000, // first 1MB reserved for Redboot
+ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables
+ // BI is at 4096th byte out of factory (0-indexed)
+ // our NFC read out data like this:
+ // | 538 | 538 | 538 | 538 | 538 | 538 | 538 | 538 |
+ // P1 P2 P3 P4 P5 P6 P7 P8
+ // |0-537|538-1075|1076-1613|1614-2151|2152-2689|2690-3227|3228-3765|3766-4303 |
+ // So the last subpage starts: 3696th byte. 4096th byte is at offset 330.
+ bi_off : MXC_NAND_BI_OFF(4096, 512 + 26),
+ vendor_info: "Micron MT29F32G08QAA 8-bit 4K page 4GB (32Gb) nand, 218B spare",
+ max_bad_blk: 20,
},
#endif // CYGONCE_DEVS_FLASH_MXC_NAND_PARTS_INL
#include <pkgconf/devs_flash_onmxc.h>
#include "mxc_nand_specifics.h"
-#define NFC_DEBUG_NONE 0
-#define NFC_DEBUG_MIN 1
-#define NFC_DEBUG_MED 2
-#define NFC_DEBUG_MAX 3
-#define NFC_DEBUG_DEF NFC_DEBUG_NONE
-#define PG_2K_DATA_OP_MULTI_CYCLES() true
-
-typedef unsigned short u16;
-typedef unsigned int u32;
-typedef unsigned char u8;
+#if defined(NFC_V1_1)
+#define PG_2K_DATA_OP_MULTI_CYCLES() false
+#else
+#define PG_2K_DATA_OP_MULTI_CYCLES() true
+#endif
-#define ADDR_INPUT_SIZE 8
-//----------------------------------------------------------------------------
-// Common device details.
-#define FLASH_Read_ID (0x90)
-#if CYGHWR_DEVS_FLASH_MXC_NAND_RESET_WORKAROUND
-#define FLASH_Reset 0xFFFF
+#define ADDR_INPUT_SIZE 8
+#define NAND_MAIN_BUF0 (NFC_BASE + 0x000)
+#define NAND_MAIN_BUF1 (NFC_BASE + 0x200)
+#define NAND_MAIN_BUF2 (NFC_BASE + 0x400)
+#define NAND_MAIN_BUF3 (NFC_BASE + 0x600)
+#if defined(NFC_V1_1)
+#define NAND_MAIN_BUF4 (NFC_BASE + 0x800)
+#define NAND_MAIN_BUF5 (NFC_BASE + 0xA00)
+#define NAND_MAIN_BUF6 (NFC_BASE + 0xC00)
+#define NAND_MAIN_BUF7 (NFC_BASE + 0xE00)
+#define NAND_SPAR_BUF0 (NFC_BASE + 0x1000)
+#define NAND_SPAR_BUF1 (NFC_BASE + 0x1040)
+#define NAND_SPAR_BUF2 (NFC_BASE + 0x1080)
+#define NAND_SPAR_BUF3 (NFC_BASE + 0x10C0)
+#define NAND_SPAR_BUF4 (NFC_BASE + 0x1100)
+#define NAND_SPAR_BUF5 (NFC_BASE + 0x1140)
+#define NAND_SPAR_BUF6 (NFC_BASE + 0x1180)
+#define NAND_SPAR_BUF7 (NFC_BASE + 0x11C0)
+#define NFC_BUF_COUNT 8
+#define NFC_SPARE_BUF_SZ 64
#else
-#define FLASH_Reset (0xFF)
+#define NAND_SPAR_BUF0 (NFC_BASE + 0x800)
+#define NAND_SPAR_BUF1 (NFC_BASE + 0x810)
+#define NAND_SPAR_BUF2 (NFC_BASE + 0x820)
+#define NAND_SPAR_BUF3 (NFC_BASE + 0x830)
+#define NAND_RESERVED (NFC_BASE + 0x840)
+#define NFC_BUF_COUNT 4
+#define NFC_SPARE_BUF_SZ 16
#endif
-#define FLASH_Read_Mode1 (0x00)
-#define FLASH_Read_Mode1_2K (0x30)
-#define FLASH_Read_Mode2 (0x01)
-#define FLASH_Read_Mode3 (0x50)
-#define FLASH_Program (0x10)
-#define FLASH_Send_Data (0x80)
-#define FLASH_Status (0x70)
-#define FLASH_Block_Erase (0x60)
-#define FLASH_Start_Erase (0xD0)
-#define NAND_MAIN_BUF0 (NFC_BASE + 0x000)
-#define NAND_MAIN_BUF1 (NFC_BASE + 0x200)
-#define NAND_MAIN_BUF2 (NFC_BASE + 0x400)
-#define NAND_MAIN_BUF3 (NFC_BASE + 0x600)
-#define NAND_SPAR_BUF0 (NFC_BASE + 0x800)
-#define NAND_SPAR_BUF1 (NFC_BASE + 0x810)
-#define NAND_SPAR_BUF2 (NFC_BASE + 0x820)
-#define NAND_SPAR_BUF3 (NFC_BASE + 0x830)
-#define NAND_RESERVED (NFC_BASE + 0x840)
+#define NFC_BUFSIZE_REG (NAND_REG_BASE + 0x00)
+#define RAM_BUFFER_ADDRESS_REG (NAND_REG_BASE + 0x04)
+#define NAND_FLASH_ADD_REG (NAND_REG_BASE + 0x06)
+#define NAND_FLASH_CMD_REG (NAND_REG_BASE + 0x08)
+#define NFC_CONFIGURATION_REG (NAND_REG_BASE + 0x0A)
+#define ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x0C)
+#define ECC_RSLT_MAIN_AREA_REG (NAND_REG_BASE + 0x0E)
+#define ECC_RSLT_SPARE_AREA_REG (NAND_REG_BASE + 0x10)
+#define NF_WR_PROT_REG (NAND_REG_BASE + 0x12)
+#define NAND_FLASH_WR_PR_ST_REG (NAND_REG_BASE + 0x18)
+#define NAND_FLASH_CONFIG1_REG (NAND_REG_BASE + 0x1A)
+#define NAND_FLASH_CONFIG2_REG (NAND_REG_BASE + 0x1C)
+#if defined(NFC_V1_1)
+#define UNLOCK_START_BLK_ADD_REG (NAND_REG_BASE + 0x20)
+#define UNLOCK_END_BLK_ADD_REG (NAND_REG_BASE + 0x22)
+#define UNLOCK_START_BLK_ADD1_REG (NAND_REG_BASE + 0x24)
+#define UNLOCK_END_BLK_ADD1_REG (NAND_REG_BASE + 0x26)
+#define UNLOCK_START_BLK_ADD2_REG (NAND_REG_BASE + 0x28)
+#define UNLOCK_END_BLK_ADD2_REG (NAND_REG_BASE + 0x2A)
+#define UNLOCK_START_BLK_ADD3_REG (NAND_REG_BASE + 0x2C)
+#define UNLOCK_END_BLK_ADD3_REG (NAND_REG_BASE + 0x2E)
+#else
+#define UNLOCK_START_BLK_ADD_REG (NAND_REG_BASE + 0x14)
+#define UNLOCK_END_BLK_ADD_REG (NAND_REG_BASE + 0x16)
+#endif
-#define NFC_BUFSIZE_REG (NAND_REG_BASE + 0x00)
-#define RAM_BUFFER_ADDRESS_REG (NAND_REG_BASE + 0x04)
-#define NAND_FLASH_ADD_REG (NAND_REG_BASE + 0x06)
-#define NAND_FLASH_CMD_REG (NAND_REG_BASE + 0x08)
-#define NFC_CONFIGURATION_REG (NAND_REG_BASE + 0x0A)
-#define ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x0C)
-#define ECC_RSLT_MAIN_AREA_REG (NAND_REG_BASE + 0x0E)
-#define ECC_RSLT_SPARE_AREA_REG (NAND_REG_BASE + 0x10)
-#define NF_WR_PROT_REG (NAND_REG_BASE + 0x12)
-#define UNLOCK_START_BLK_ADD_REG (NAND_REG_BASE + 0x14)
-#define UNLOCK_END_BLK_ADD_REG (NAND_REG_BASE + 0x16)
-#define NAND_FLASH_WR_PR_ST_REG (NAND_REG_BASE + 0x18)
-#define NAND_FLASH_CONFIG1_REG (NAND_REG_BASE + 0x1A)
-#define NAND_FLASH_CONFIG2_REG (NAND_REG_BASE + 0x1C)
+#define NUM_OF_CS_LINES 1
+#define NFC_BUFSIZE 0
enum nfc_internal_buf {
RAM_BUF_0,
RAM_BUF_1,
RAM_BUF_2,
RAM_BUF_3,
+ RAM_BUF_4,
+ RAM_BUF_5,
+ RAM_BUF_6,
+ RAM_BUF_7,
};
enum nfc_output_mode {
FDO_FLASH_STATUS = 0x0020,
};
-/*!
- * Defined the "complete" address input operations which may involve
- * more than one cycle of single address input operation.
- */
-enum nfc_addr_ops {
- ADDRESS_INPUT_READ_ID,
- ADDRESS_INPUT_READ_PAGE,
- ADDRESS_INPUT_PROGRAM_PAGE,
- ADDRESS_INPUT_ERASE_BLOCK,
-};
-
-enum nfc_page_area {
- NFC_SPARE_ONLY,
- NFC_MAIN_ONLY,
-};
-
-enum {
- MXC_NAND_8_BIT = 8,
- MXC_NAND_16_BIT = 16,
-};
-
-enum {
- NAND_SLC = 0,
- NAND_MLC = 1,
-};
-
-// read column 464-465 byte but only 464 for bad block marker
-#define BAD_BLK_MARKER_464 (NAND_MAIN_BUF3 + 464)
-// read column 4-5 byte, but only 5 is used for swapped main area data
-#define BAD_BLK_MARKER_SP_5 (NAND_SPAR_BUF3 + 4)
+#define wait_for_auto_prog_done()
// Polls the NANDFC to wait for an operation to complete
-static inline void wait_op_done(void)
-{
- int mxc_nfc_wait_loop;
- while (!(readw(NAND_FLASH_CONFIG2_REG) & NAND_FLASH_CONFIG2_INT_DONE)) {
- for (mxc_nfc_wait_loop = 0; mxc_nfc_wait_loop < 100; mxc_nfc_wait_loop++);
- }
-}
-
-int nfc_read_region(u32 la, u32 maddr, int len);
-int nfc_program_region(u32 la, u32 maddr, int len);
-int nfc_erase_region(u32 la, int len);
-
+#define wait_op_done() CYG_MACRO_START \
+ volatile int mxc_nfc_wait_loop; \
+ while (!(readw(NAND_FLASH_CONFIG2_REG) & NAND_FLASH_CONFIG2_INT_DONE)) { \
+ for (mxc_nfc_wait_loop = 0; mxc_nfc_wait_loop < 100; mxc_nfc_wait_loop++); \
+ } \
+CYG_MACRO_END
/*!
* NAND flash data output operation (reading data from NAND flash)
* @param buf_no internal ram buffer number that will contain data
* to be outputted from the NAND flash after operation done
* @param mode one of the mode defined in enum nfc_output_mode
+ * @param ecc_en 1 - ecc enabled; 0 - ecc disabled
*/
static void NFC_DATA_OUTPUT(enum nfc_internal_buf buf_no, enum nfc_output_mode mode,
int ecc_en)
if (mode == FDO_SPARE_ONLY) {
config1 |= NAND_FLASH_CONFIG1_SP_EN;
-#ifdef CYGPKG_HAL_ARM_MXC91221
- config1 &= ~NAND_FLASH_CONFIG1_ECC_EN;
-#endif
}
writew(config1, NAND_FLASH_CONFIG1_REG);
flash_status = readw(NAND_MAIN_BUF0) & 0x00FF;
// restore
- writew(saved, NAND_MAIN_BUF0);
+ writew(saved, NAND_MAIN_BUF0);
return flash_status;
}
writew(NF_WR_PROT_UNLOCK, NF_WR_PROT_REG);
}
+static void NFC_SET_NFC_ACTIVE_CS(u32 cs_line)
+{
+ // not needed.
+}
+
/*!
* Issue the address input operation
* @param addr the address for the address input operation
wait_op_done();
}
+#if defined(NFC_V1_1)
+#define NFC_ARCH_INIT() CYG_MACRO_START \
+ unsigned int tmp, reg; \
+ tmp = flash_dev_info->page_size / 512; \
+ if (flash_dev_info->spare_size) { \
+ writew((flash_dev_info->spare_size >> 1), \
+ ECC_RSLT_SPARE_AREA_REG); \
+ } \
+ writew(0x2, NFC_CONFIGURATION_REG); \
+ reg = readw(NAND_FLASH_CONFIG1_REG) | 0x800; \
+ if ((flash_dev_info->spare_size / tmp) > 16) \
+ reg &= ~1; \
+ else \
+ reg |= 1; \
+ writew(reg, NAND_FLASH_CONFIG1_REG); \
+CYG_MACRO_END
+#else
+#define NFC_ARCH_INIT()
+#endif /*NFC_V1_1*/
+
+#define NAND_ADD0_REG 0xDEADDAED
+#define NAND_ADD8_REG 0xDEADDAED
+#define NAND_CMD_REG 0xDEADDAED
+#define NAND_LAUNCH_AUTO_PROG 0xDEADDAED
+#define NAND_STATUS_SUM_REG 0xDEADDAED
+#define NAND_LAUNCH_AUTO_READ 0xDEADDAED
+#define NAND_LAUNCH_AUTO_ERASE 0xDEADDAED
+
#endif // _MXC_NFC_H_
#include <pkgconf/devs_flash_onmxc.h>
#include "mxc_nand_specifics.h"
-#define NFC_DEBUG_MIN 1
-#define NFC_DEBUG_MED 2
-#define NFC_DEBUG_MAX 3
-#define NFC_DEBUG_DEF NFC_DEBUG_MED
-
#define PG_2K_DATA_OP_MULTI_CYCLES() false
-typedef unsigned short u16;
-typedef unsigned int u32;
-typedef unsigned char u8;
-
-#define ADDR_INPUT_SIZE 8
//----------------------------------------------------------------------------
// Common device details.
-#define FLASH_Read_ID (0x90)
-#if CYGHWR_DEVS_FLASH_MXC_NAND_RESET_WORKAROUND
-#define FLASH_Reset 0xFFFF
+#define NAND_MAIN_BUF0 (NFC_BASE + 0x000)
+#define NAND_MAIN_BUF1 (NFC_BASE + 0x200)
+#define NAND_MAIN_BUF2 (NFC_BASE + 0x400)
+#define NAND_MAIN_BUF3 (NFC_BASE + 0x600)
+#if defined (NFC_V2_0)
+#define NAND_SPAR_BUF0 (NFC_BASE + 0x800)
+#define NAND_SPAR_BUF1 (NFC_BASE + 0x810)
+#define NAND_SPAR_BUF2 (NFC_BASE + 0x820)
+#define NAND_SPAR_BUF3 (NFC_BASE + 0x830)
+#define NAND_RESERVED (NFC_BASE + 0x840)
+#define NFC_BUF_COUNT 4
+#define NFC_SPARE_BUF_SZ 16
+#elif defined (NFC_V2_1)
+#define NAND_MAIN_BUF4 (NFC_BASE + 0x800)
+#define NAND_MAIN_BUF5 (NFC_BASE + 0xA00)
+#define NAND_MAIN_BUF6 (NFC_BASE + 0xC00)
+#define NAND_MAIN_BUF7 (NFC_BASE + 0xE00)
+#define NAND_SPAR_BUF0 (NFC_BASE + 0x1000)
+#define NAND_SPAR_BUF1 (NFC_BASE + 0x1040)
+#define NAND_SPAR_BUF2 (NFC_BASE + 0x1080)
+#define NAND_SPAR_BUF3 (NFC_BASE + 0x10C0)
+#define NAND_SPAR_BUF4 (NFC_BASE + 0x1100)
+#define NAND_SPAR_BUF5 (NFC_BASE + 0x1140)
+#define NAND_SPAR_BUF6 (NFC_BASE + 0x1180)
+#define NAND_SPAR_BUF7 (NFC_BASE + 0x11C0)
+#define NFC_BUF_COUNT 8
+#define NFC_SPARE_BUF_SZ 64
#else
-#define FLASH_Reset (0xFF)
+#error NOT supported
#endif
-#define FLASH_Read_Mode1 (0x00)
-#define FLASH_Read_Mode1_2K (0x30)
-#define FLASH_Read_Mode2 (0x01)
-#define FLASH_Read_Mode3 (0x50)
-#define FLASH_Program (0x10)
-#define FLASH_Send_Data (0x80)
-#define FLASH_Status (0x70)
-#define FLASH_Block_Erase (0x60)
-#define FLASH_Start_Erase (0xD0)
-
-#define NAND_MAIN_BUF0 (NFC_BASE + 0x000)
-#define NAND_MAIN_BUF1 (NFC_BASE + 0x200)
-#define NAND_MAIN_BUF2 (NFC_BASE + 0x400)
-#define NAND_MAIN_BUF3 (NFC_BASE + 0x600)
-#define NAND_SPAR_BUF0 (NFC_BASE + 0x800)
-#define NAND_SPAR_BUF1 (NFC_BASE + 0x810)
-#define NAND_SPAR_BUF2 (NFC_BASE + 0x820)
-#define NAND_SPAR_BUF3 (NFC_BASE + 0x830)
-#define NAND_RESERVED (NFC_BASE + 0x840)
-
-#define NFC_BUFSIZE_REG (NAND_REG_BASE + 0x00)
-#define RAM_BUFFER_ADDRESS_REG (NAND_REG_BASE + 0x04)
-#define NAND_FLASH_ADD_REG (NAND_REG_BASE + 0x06)
-#define NAND_FLASH_CMD_REG (NAND_REG_BASE + 0x08)
-#define NFC_CONFIGURATION_REG (NAND_REG_BASE + 0x0A)
-#define ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x0C)
-#define ECC_RSLT_MAIN_AREA_REG (NAND_REG_BASE + 0x0E)
-#define ECC_RSLT_SPARE_AREA_REG (NAND_REG_BASE + 0x10)
-#define NF_WR_PROT_REG (NAND_REG_BASE + 0x12)
-#define UNLOCK_START_BLK_ADD_REG (NAND_REG_BASE + 0x14)
-#define UNLOCK_END_BLK_ADD_REG (NAND_REG_BASE + 0x16)
-#define NAND_FLASH_WR_PR_ST_REG (NAND_REG_BASE + 0x18)
-#define NAND_FLASH_CONFIG1_REG (NAND_REG_BASE + 0x1A)
-#define NAND_FLASH_CONFIG2_REG (NAND_REG_BASE + 0x1C)
-enum nfc_internal_buf {
- RAM_BUF_0 = 0x0 << 4,
- RAM_BUF_1 = 0x1 << 4,
- RAM_BUF_2 = 0x2 << 4,
- RAM_BUF_3 = 0x3 << 4,
-};
+#define ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x08)
+#define NUM_OF_CS_LINES 1
+#define NFC_BUFSIZE 0
-enum nfc_output_mode {
- FDO_PAGE_SPARE = 0x0008,
- FDO_SPARE_ONLY = 0x1008, // LSB has to be 0x08
- FDO_FLASH_ID = 0x0010,
- FDO_FLASH_STATUS = 0x0020,
-};
+#define NFC_PPB_REG NAND_CONFIGURATION2_REG
+#define NFC_PPB_SHIFT 7
+#define NFC_PPB_MASK ~(3 << NFC_PPB_SHIFT)
-/*!
- * Defined the "complete" address input operations which may involve
- * more than one cycle of single address input operation.
- */
-enum nfc_addr_ops {
- ADDRESS_INPUT_READ_ID,
- ADDRESS_INPUT_READ_PAGE,
- ADDRESS_INPUT_PROGRAM_PAGE,
- ADDRESS_INPUT_ERASE_BLOCK,
+enum nfc_internal_buf {
+ RAM_BUF_0 = 0x0 << 4,
+ RAM_BUF_1 = 0x1 << 4,
+ RAM_BUF_2 = 0x2 << 4,
+ RAM_BUF_3 = 0x3 << 4,
+ RAM_BUF_4 = 0x4 << 4,
+ RAM_BUF_5 = 0x5 << 4,
+ RAM_BUF_6 = 0x6 << 4,
+ RAM_BUF_7 = 0x7 << 4,
+ RAM_BUF_MASK = ~(0x7 << 4),
};
-enum nfc_page_area {
- NFC_SPARE_ONLY,
- NFC_MAIN_ONLY,
+enum nfc_output_mode {
+ FDO_PAGE_SPARE = 0x0008,
+ FDO_SPARE_ONLY = 0x1008, // LSB has to be 0x08
+ FDO_FLASH_ID = 0x0010,
+ FDO_FLASH_STATUS = 0x0020,
};
-enum {
- MXC_NAND_8_BIT = 8,
- MXC_NAND_16_BIT = 16,
-};
+#define wait_for_auto_prog_done()
-enum {
- NAND_SLC = 0,
- NAND_MLC = 1,
-};
+// Polls the NANDFC to wait for an operation to complete
+#define wait_op_done() CYG_MACRO_START \
+ u32 __nfc_stat = nfc_reg_read(NFC_IPC_REG); \
+ while (!(__nfc_stat & NFC_IPC_INT)) { \
+ __nfc_stat = nfc_reg_read(NFC_IPC_REG); \
+ } \
+ nfc_reg_write(__nfc_stat & ~NFC_IPC_INT, NFC_IPC_REG); \
+CYG_MACRO_END
+
+#if 1
+#define nfc_reg_write(v, r) __nfc_reg_write(v, (void *)(r), #r, __FUNCTION__)
+static inline void __nfc_reg_write(u32 val, void *addr,
+ const char *reg, const char *fn)
+{
+ nfc_printf(NFC_DEBUG_MAX, "%s: Writing %08x to %s[%04lx]\n", fn, val, reg,
+ (unsigned long)addr & 0x3fff);
+ writel(val, addr);
+}
-// read column 464-465 byte but only 464 for bad block marker
-#define BAD_BLK_MARKER_464 (NAND_MAIN_BUF3 + 464)
-// read column 4-5 byte, but only 5 is used for swapped main area data
-#define BAD_BLK_MARKER_SP_5 (NAND_SPAR_BUF3 + 4)
+#define nfc_reg_read(r) __nfc_reg_read((void *)(r), #r, __FUNCTION__)
+static inline u32 __nfc_reg_read(void *addr,
+ const char *reg, const char *fn)
+{
+ u32 val;
+ val = readl(addr);
+ nfc_printf(NFC_DEBUG_MAX, "%s: Read %08x from %s[%04lx]\n", fn, val, reg,
+ (unsigned long)addr & 0x3fff);
+ return val;
+}
-// Polls the NANDFC to wait for an operation to complete
-#define wait_op_done() \
- do { \
- volatile int mxc_nfc_wait_loop; \
- while ((readl(NFC_IPC_REG) & NFC_IPC_INT) == 0) \
- {for (mxc_nfc_wait_loop = 0; mxc_nfc_wait_loop < 100; mxc_nfc_wait_loop++);} \
- write_nfc_ip_reg(0, NFC_IPC_REG); \
- } while (0)
-
-int nfc_read_region(u32 la, u32 maddr, int len);
-int nfc_program_region(u32 la, u32 maddr, int len);
-int nfc_erase_region(u32 la, int len);
+#define write_nfc_ip_reg(v, r) CYG_MACRO_START \
+ nfc_reg_write(NFC_IPC_CREQ, NFC_IPC_REG); \
+ while (!(nfc_reg_read(NFC_IPC_REG) & NFC_IPC_CACK)); \
+ __nfc_reg_write(v, (void *)(r), #r, __FUNCTION__); \
+ nfc_reg_write(0, NFC_IPC_REG); \
+CYG_MACRO_END
+#else
+#define nfc_reg_read(r) readl(r)
+#define nfc_reg_write(v, r) writel(v, r)
static void write_nfc_ip_reg(u32 val, u32 reg)
{
- volatile int mxc_nfc_wait_loop;
-
- writel(NFC_IPC_CREQ, NFC_IPC_REG);
- for (mxc_nfc_wait_loop = 0; mxc_nfc_wait_loop < 100; mxc_nfc_wait_loop++);
-
- writel(val, reg);
- writel(0, NFC_IPC_REG);
+ nfc_reg_write(NFC_IPC_CREQ, NFC_IPC_REG);
+ while (!(nfc_reg_read(NFC_IPC_REG) & NFC_IPC_CACK));
+ nfc_reg_write(val, reg);
+ nfc_reg_write(0, NFC_IPC_REG);
}
+#endif
/*!
* NAND flash data output operation (reading data from NAND flash)
- * @param buf_no internal ram buffer number that will contain data
- * to be outputted from the NAND flash after operation done
- * @param mode one of the mode defined in enum nfc_output_mode
- * @param ecc_en 1 - ecc enabled; 0 - ecc disabled
+ * @param buf_no internal ram buffer number that will contain data
+ * to be outputted from the NAND flash after operation done
+ * @param mode one of the mode defined in enum nfc_output_mode
+ * @param ecc_en 1 - ecc enabled; 0 - ecc disabled
*/
static void NFC_DATA_OUTPUT(enum nfc_internal_buf buf_no, enum nfc_output_mode mode,
- int ecc_en)
+ int ecc_en)
{
- u32 v = readl(NFC_FLASH_CONFIG2_REG);
-
- if ((v & NFC_FLASH_CONFIG2_ECC_EN) != 0 && ecc_en == 0) {
- write_nfc_ip_reg(v & ~NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG);
- }
- if ((v & NFC_FLASH_CONFIG2_ECC_EN) == 0 && ecc_en != 0) {
- write_nfc_ip_reg(v | NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG);
- }
-
- v = readl(NAND_CONFIGURATION1_REG);
-
- if (mode == FDO_SPARE_ONLY) {
- v = (v & ~0x31) | buf_no | NAND_CONFIGURATION1_SP_EN;
- } else {
- v = (v & ~0x31) | buf_no;
- }
-
- writel(v, NAND_CONFIGURATION1_REG);
-
- writel(mode & 0xFF, NAND_LAUNCH_REG);
- wait_op_done();
+ u32 v = nfc_reg_read(NFC_FLASH_CONFIG2_REG);
+
+ if ((v & NFC_FLASH_CONFIG2_ECC_EN) != 0 && ecc_en == 0) {
+ write_nfc_ip_reg(v & ~NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG);
+ }
+ if ((v & NFC_FLASH_CONFIG2_ECC_EN) == 0 && ecc_en != 0) {
+ write_nfc_ip_reg(v | NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG);
+ }
+
+ v = (nfc_reg_read(NAND_CONFIGURATION1_REG) & RAM_BUF_MASK) | buf_no;
+ if (mode == FDO_SPARE_ONLY) {
+ v |= NAND_CONFIGURATION1_SP_EN;
+ } else {
+ v &= ~NAND_CONFIGURATION1_SP_EN;
+ }
+ nfc_reg_write(v, NAND_CONFIGURATION1_REG);
+
+ nfc_reg_write(mode & 0xFF, NAND_LAUNCH_REG);
+ wait_op_done();
}
static void NFC_CMD_INPUT(u32 cmd)
{
- writel(cmd & 0xFFFF, NAND_ADD_CMD_REG);
- writel(NAND_LAUNCH_FCMD, NAND_LAUNCH_REG);
- wait_op_done();
+ nfc_reg_write(cmd & 0xFFFF, NAND_ADD_CMD_REG);
+ nfc_reg_write(NAND_LAUNCH_FCMD, NAND_LAUNCH_REG);
+ wait_op_done();
}
static u16 NFC_STATUS_READ(void)
{
- u16 flash_status;
- u16 saved = readw(NAND_MAIN_BUF0);
+ u16 flash_status;
+ u16 saved = readw(NAND_MAIN_BUF0);
- NFC_CMD_INPUT(FLASH_Status);
- NFC_DATA_OUTPUT(RAM_BUF_0, FDO_FLASH_STATUS, 1);
- flash_status = readw(NAND_MAIN_BUF0) & 0x00FF;
+ NFC_CMD_INPUT(FLASH_Status);
+ NFC_DATA_OUTPUT(RAM_BUF_0, FDO_FLASH_STATUS, 1);
+ flash_status = readw(NAND_MAIN_BUF0) & 0x00FF;
- // restore
- writew(saved, NAND_MAIN_BUF0);
+ // restore
+ writew(saved, NAND_MAIN_BUF0);
- return flash_status;
+ return flash_status;
}
/*!
* NAND flash data input operation (writing data to NAND flash)
- * @param buf_no internal ram buffer number containing data to be
- * written into the NAND flash
- * @param area NFC_SPARE_ONLY or NFC_MAIN_ONLY,
- * @param ecc_en 1 - ecc enabled; 0 - ecc disabled
+ * @param buf_no internal ram buffer number containing data to be
+ * written into the NAND flash
+ * @param area NFC_SPARE_ONLY or NFC_MAIN_ONLY,
+ * @param ecc_en 1 - ecc enabled; 0 - ecc disabled
*/
static void NFC_DATA_INPUT(enum nfc_internal_buf buf_no, enum nfc_page_area area,
- int ecc_en)
+ int ecc_en)
{
- u32 v = readl(NFC_FLASH_CONFIG2_REG);
-
- // setup config2 register for ECC enable or not
- if ((v & NFC_FLASH_CONFIG2_ECC_EN) != 0 && ecc_en == 0) {
- write_nfc_ip_reg(v & ~NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG);
- }
- if ((v & NFC_FLASH_CONFIG2_ECC_EN) == 0 && ecc_en != 0) {
- write_nfc_ip_reg(v | NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG);
- }
-
- // setup config1 register for ram buffer number, spare-only or not
- v = readl(NAND_CONFIGURATION1_REG);
-
- if (area == NFC_SPARE_ONLY) {
- v = (v & ~0x31) | buf_no | NAND_CONFIGURATION1_SP_EN;
- } else {
- v = (v & ~0x31) | buf_no;
- }
-
- writel(v, NAND_CONFIGURATION1_REG);
-
- // start operation
- writel(NAND_LAUNCH_FDI, NAND_LAUNCH_REG);
- wait_op_done();
+ u32 v = nfc_reg_read(NFC_FLASH_CONFIG2_REG);
+
+ // setup config2 register for ECC enable or not
+ if ((v & NFC_FLASH_CONFIG2_ECC_EN) != 0 && ecc_en == 0) {
+ write_nfc_ip_reg(v & ~NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG);
+ }
+ if ((v & NFC_FLASH_CONFIG2_ECC_EN) == 0 && ecc_en != 0) {
+ write_nfc_ip_reg(v | NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG);
+ }
+
+ // setup config1 register for ram buffer number, spare-only or not
+ v = (nfc_reg_read(NAND_CONFIGURATION1_REG) & RAM_BUF_MASK) | buf_no;
+ if (area == NFC_SPARE_ONLY) {
+ v |= NAND_CONFIGURATION1_SP_EN;
+ } else {
+ v &= ~NAND_CONFIGURATION1_SP_EN;
+ }
+ nfc_reg_write(v, NAND_CONFIGURATION1_REG);
+
+ // start operation
+ nfc_reg_write(NAND_LAUNCH_FDI, NAND_LAUNCH_REG);
+ wait_op_done();
}
static void NFC_DATA_INPUT_2k(enum nfc_internal_buf buf_no)
{
- u32 v;
+ u32 v;
- // setup config1 register for ram buffer number, spare-only or not
- v = readl(NAND_CONFIGURATION1_REG);
- v = (v & ~0x30) | buf_no;
- writel(v, NAND_CONFIGURATION1_REG);
+ // setup config1 register for ram buffer number, spare-only or not
+ v = (nfc_reg_read(NAND_CONFIGURATION1_REG) & RAM_BUF_MASK) | buf_no;
+ nfc_reg_write(v, NAND_CONFIGURATION1_REG);
- // start operation
- writel(NAND_LAUNCH_FDI, NAND_LAUNCH_REG);
- wait_op_done();
+ // start operation
+ nfc_reg_write(NAND_LAUNCH_FDI, NAND_LAUNCH_REG);
+ wait_op_done();
}
/*!
*/
static void NFC_PRESET(u32 max_block_count)
{
- // not needed. It is done in plf_hardware_init()
+ // not needed. It is done in plf_hardware_init()
+}
+
+static void NFC_SET_NFC_ACTIVE_CS(u32 cs_line)
+{
+ // not needed.
}
/*!
* Issue the address input operation
- * @param addr the address for the address input operation
+ * @param addr the address for the address input operation
*/
static void NFC_ADDR_INPUT(u32 addr)
{
- writel((addr & ((1 << ADDR_INPUT_SIZE) - 1)) << 16, NAND_ADD_CMD_REG);
- writel(NAND_LAUNCH_FADD, NAND_LAUNCH_REG);
- wait_op_done();
+#if 0
+ if (nfc_debug) {
+ diag_printf("add = 0x%08x, at 0x%08lx\n",
+ (addr & 0xFF) << 16, NAND_ADD_CMD_REG);
+ diag_printf("NAND_LAUNCH_FADD=%08x, NAND_LAUNCH_REG=%08lx\n",
+ NAND_LAUNCH_FADD, NAND_LAUNCH_REG);
+ }
+#endif
+ nfc_reg_write((addr & 0xFF) << 16, NAND_ADD_CMD_REG);
+ nfc_reg_write(NAND_LAUNCH_FADD, NAND_LAUNCH_REG);
+ wait_op_done();
}
+#define NFC_ARCH_INIT()
+#define NAND_ADD0_REG 0xDEADDAED
+#define NAND_ADD8_REG 0xDEADDAED
+#define NAND_CMD_REG 0xDEADDAED
+#define NAND_LAUNCH_AUTO_PROG 0xDEADDAED
+#define NAND_STATUS_SUM_REG 0xDEADDAED
+#define NAND_LAUNCH_AUTO_READ 0xDEADDAED
+#define NAND_LAUNCH_AUTO_ERASE 0xDEADDAED
#endif // _MXC_NFC_V2_H_
FDO_FLASH_STATUS = 0x0020,
};
-#define wait_for_auto_prog_done() \
- do { \
- while ((readl(NFC_IPC_REG) & NFC_IPC_AUTO_DONE) == 0) \
- {} \
- write_nfc_ip_reg((readl(NFC_IPC_REG) & ~NFC_IPC_AUTO_DONE), NFC_IPC_REG); \
- } while (0)
+#define wait_for_auto_prog_done() \
+ do { \
+ while ((nfc_reg_read(NFC_IPC_REG) & NFC_IPC_AUTO_DONE) == 0) { \
+ } \
+ write_nfc_ip_reg((nfc_reg_read(NFC_IPC_REG) & ~NFC_IPC_AUTO_DONE), NFC_IPC_REG); \
+ } while (0)
// Polls the NANDFC to wait for an operation to complete
-#define wait_op_done() \
- do { \
- while ((readl(NFC_IPC_REG) & NFC_IPC_INT) == 0) \
- {} \
- write_nfc_ip_reg(0, NFC_IPC_REG); \
- } while (0)
+#define wait_op_done() \
+ do { \
+ while ((nfc_reg_read(NFC_IPC_REG) & NFC_IPC_INT) == 0) \
+ {} \
+ write_nfc_ip_reg(0, NFC_IPC_REG); \
+ } while (0)
+
+#if 0
+#define nfc_reg_write(v, r) __nfc_reg_write(v, (void *)(r), #r, __FUNCTION__)
+static inline void __nfc_reg_write(u32 val, void *addr,
+ const char *reg, const char *fn)
+{
+ diag_printf1("%s: Writing %08x to %s[%04lx]\n", fn, val, reg,
+ (unsigned long)addr & 0x1fff);
+ writel(val, addr);
+}
+
+#define nfc_reg_read(r) __nfc_reg_read((void *)(r), #r, __FUNCTION__)
+static inline u32 __nfc_reg_read(void *addr,
+ const char *reg, const char *fn)
+{
+ u32 val;
+ val = readl(addr);
+ diag_printf1("%s: Read %08x from %s[%04lx]\n", fn, val, reg,
+ (unsigned long)addr & 0x1fff);
+ return val;
+}
+#else
+#define nfc_reg_read(r) readl(r)
+#define nfc_reg_write(v, r) writel(v, r)
+#endif
static void write_nfc_ip_reg(u32 val, u32 reg)
{
- writel(NFC_IPC_CREQ, NFC_IPC_REG);
- while((readl(NFC_IPC_REG) & NFC_IPC_CACK) == 0);
+ nfc_reg_write(NFC_IPC_CREQ, NFC_IPC_REG);
+ while((nfc_reg_read(NFC_IPC_REG) & NFC_IPC_CACK) == 0);
- writel(val, reg);
- writel((readl(NFC_IPC_REG) & ~NFC_IPC_CREQ), NFC_IPC_REG);
+ nfc_reg_write(val, reg);
+ nfc_reg_write((nfc_reg_read(NFC_IPC_REG) & ~NFC_IPC_CREQ), NFC_IPC_REG);
}
/*!
* @param ecc_en 1 - ecc enabled; 0 - ecc disabled
*/
static void NFC_DATA_OUTPUT(enum nfc_internal_buf buf_no, enum nfc_output_mode mode,
- int ecc_en)
+ int ecc_en)
{
- u32 v = readl(NFC_FLASH_CONFIG2_REG);
+ u32 v = nfc_reg_read(NFC_FLASH_CONFIG2_REG);
if ((v & NFC_FLASH_CONFIG2_ECC_EN) != 0 && ecc_en == 0) {
- write_nfc_ip_reg(v & ~NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG);
+ write_nfc_ip_reg(v & ~NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG);
}
if ((v & NFC_FLASH_CONFIG2_ECC_EN) == 0 && ecc_en != 0) {
- write_nfc_ip_reg(v | NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG);
+ write_nfc_ip_reg(v | NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG);
}
- v = readl(NAND_CONFIGURATION1_REG);
+ v = nfc_reg_read(NAND_CONFIGURATION1_REG);
if (mode == FDO_SPARE_ONLY) {
- v = (v & ~0x71) | buf_no | NAND_CONFIGURATION1_SP_EN;
+ v = (v & ~0x71) | buf_no | NAND_CONFIGURATION1_SP_EN;
} else {
- v = (v & ~0x71) | buf_no;
+ v = (v & ~0x71) | buf_no;
}
- writel(v, NAND_CONFIGURATION1_REG);
+ nfc_reg_write(v, NAND_CONFIGURATION1_REG);
- writel(mode & 0xFF, NAND_LAUNCH_REG);
+ nfc_reg_write(mode & 0xFF, NAND_LAUNCH_REG);
wait_op_done();
}
static void NFC_CMD_INPUT(u32 cmd)
{
- writel(cmd & 0xFFFF, NAND_CMD_REG);
- writel(NAND_LAUNCH_FCMD, NAND_LAUNCH_REG);
+ nfc_reg_write(cmd & 0xFFFF, NAND_CMD_REG);
+ nfc_reg_write(NAND_LAUNCH_FCMD, NAND_LAUNCH_REG);
wait_op_done();
}
{
u32 v;
- v = readl(NAND_CONFIGURATION1_REG) & (~0x7071);
+ v = nfc_reg_read(NAND_CONFIGURATION1_REG) & (~0x7071);
v |= (cs_line << 12);
- writel(v, NAND_CONFIGURATION1_REG);
+ nfc_reg_write(v, NAND_CONFIGURATION1_REG);
}
static u16 NFC_STATUS_READ(void)
int i;
#ifdef IMX51_TO_2
- return readl(NAND_STATUS_SUM_REG);
+ return nfc_reg_read(NAND_STATUS_SUM_REG);
#else
/* Cannot rely on STATUS_SUM register due to errata */
for (i = 0; i < num_of_nand_chips; i++) {
- NFC_SET_NFC_ACTIVE_CS(i);
- do {
- writel(NAND_LAUNCH_AUTO_STAT, NAND_LAUNCH_REG);
- status = (readl(NAND_CONFIGURATION1_REG) & 0x00FF0000) >> 16;
- } while ((status & 0x40) == 0); // make sure I/O 6 == 1
- /* Get Pass/Fail status */
- status = (readl(NAND_CONFIGURATION1_REG) >> 16) & 0x1;
- status_sum |= (status << i);
+ NFC_SET_NFC_ACTIVE_CS(i);
+ do {
+ nfc_reg_write(NAND_LAUNCH_AUTO_STAT, NAND_LAUNCH_REG);
+ status = (nfc_reg_read(NAND_CONFIGURATION1_REG) & 0x00FF0000) >> 16;
+ } while ((status & 0x40) == 0); // make sure I/O 6 == 1
+ /* Get Pass/Fail status */
+ status = (nfc_reg_read(NAND_CONFIGURATION1_REG) >> 16) & 0x1;
+ status_sum |= (status << i);
}
return status_sum;
#endif
int num_of_bits[] = {0, 0, 1, 0, 2, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 4};
if (ops == FLASH_Read_ID) {
- // issue addr cycle
- writel(0x0, NAND_ADD0_REG + (4 * cs_line));
- writel(NAND_LAUNCH_FADD, NAND_LAUNCH_REG);
- wait_op_done();
- return;
+ // issue addr cycle
+ nfc_reg_write(0x0, NAND_ADD0_REG + (4 * cs_line));
+ nfc_reg_write(NAND_LAUNCH_FADD, NAND_LAUNCH_REG);
+ wait_op_done();
+ return;
}
if (num_of_chips > 1) {
- page_number = (pg_no << num_of_bits[num_of_chips]) | (cs_line & (num_of_chips - 1));
+ page_number = (pg_no << num_of_bits[num_of_chips]) | (cs_line & (num_of_chips - 1));
} else {
- page_number = pg_no;
+ page_number = pg_no;
}
if (is_erase) {
- add0 = page_number;
- add8 = 0;
+ add0 = page_number;
+ add8 = 0;
} else {
- // for both read and write
- if (g_is_2k_page || g_is_4k_page) {
- // the first two addr cycles are for column addr. Page number starts
- // from the 3rd addr cycle.
- add0 = pg_off | (page_number << 16);
- add8 = page_number >> 16;
- } else {
- diag_printf("too bad, die\n");
- asm("1: b 1b");
- // For 512B page, the first addr cycle is for column addr. Page number
- // starts from the 2nd addr cycle.
- add0 = (pg_off & 0xFF) | (page_number << 8);
- add8 = page_number >> 24;
- }
+ // for both read and write
+ if (g_is_2k_page || g_is_4k_page) {
+ // the first two addr cycles are for column addr. Page number starts
+ // from the 3rd addr cycle.
+ add0 = pg_off | (page_number << 16);
+ add8 = page_number >> 16;
+ } else {
+ diag_printf("too bad, die\n");
+ asm("1: b 1b");
+ // For 512B page, the first addr cycle is for column addr. Page number
+ // starts from the 2nd addr cycle.
+ add0 = (pg_off & 0xFF) | (page_number << 8);
+ add8 = page_number >> 24;
+ }
}
- writel(add0, NAND_ADD0_REG);
- writel(add8, NAND_ADD8_REG);
+ nfc_reg_write(add0, NAND_ADD0_REG);
+ nfc_reg_write(add8, NAND_ADD8_REG);
}
/*
u32 v, res = 0;
// clear the NAND_STATUS_SUM_REG register
- writel(0, NAND_STATUS_SUM_REG);
+ nfc_reg_write(0, NAND_STATUS_SUM_REG);
// the 2nd condition is to test for unaligned page address -- ecc has to be off.
if (ecc_force == ECC_FORCE_OFF || pg_off != 0 ) {
- ecc = 0;
+ ecc = 0;
}
// Take care of config1 for RBA and SP_EN
- v = readl(NAND_CONFIGURATION1_REG) & (~0x71);
- writel(v, NAND_CONFIGURATION1_REG);
+ v = nfc_reg_read(NAND_CONFIGURATION1_REG) & (~0x71);
+ nfc_reg_write(v, NAND_CONFIGURATION1_REG);
// For ECC
- v = readl(NFC_FLASH_CONFIG2_REG) & (~NFC_FLASH_CONFIG2_ECC_EN);
+ v = nfc_reg_read(NFC_FLASH_CONFIG2_REG) & (~NFC_FLASH_CONFIG2_ECC_EN);
// setup config2 register for ECC enable or not
write_nfc_ip_reg(v | ecc, NFC_FLASH_CONFIG2_REG);
start_nfc_addr_ops(FLASH_Read_Mode1, pg_no, pg_off, 0, cs_line, num_of_chips);
if (g_is_2k_page || g_is_4k_page) {
- // combine the two commands for 2k/4k page read
- writel((FLASH_Read_Mode1_LG << 8) | FLASH_Read_Mode1, NAND_CMD_REG);
+ // combine the two commands for 2k/4k page read
+ nfc_reg_write((FLASH_Read_Mode1_LG << 8) | FLASH_Read_Mode1, NAND_CMD_REG);
} else {
- // just one command is enough for 512 page
- writel(FLASH_Read_Mode1, NAND_CMD_REG);
+ // just one command is enough for 512 page
+ nfc_reg_write(FLASH_Read_Mode1, NAND_CMD_REG);
}
// start auto-read
- writel(NAND_LAUNCH_AUTO_READ, NAND_LAUNCH_REG);
+ nfc_reg_write(NAND_LAUNCH_AUTO_READ, NAND_LAUNCH_REG);
wait_op_done();
- v = readl(NAND_STATUS_SUM_REG);
+ v = nfc_reg_read(NAND_STATUS_SUM_REG);
// test for CS0 ECC error from the STATUS_SUM register
if ((v & (0x0100 << cs_line)) != 0) {
- // clear the status
- writel((0x0100 << cs_line), NAND_STATUS_SUM_REG);
- diag_printf("ECC error from NAND_STATUS_SUM_REG(0x%x) = 0x%x\n",
- NAND_STATUS_SUM_REG, v);
- diag_printf("NAND_ECC_STATUS_RESULT_REG(0x%x) = 0x%x\n", NAND_ECC_STATUS_RESULT_REG,
- readl(NAND_ECC_STATUS_RESULT_REG));
- res = -1;
+ // clear the status
+ nfc_reg_write((0x0100 << cs_line), NAND_STATUS_SUM_REG);
+ diag_printf("ECC error from NAND_STATUS_SUM_REG(0x%x) = 0x%x\n",
+ NAND_STATUS_SUM_REG, v);
+ diag_printf("NAND_ECC_STATUS_RESULT_REG(0x%x) = 0x%x\n", NAND_ECC_STATUS_RESULT_REG,
+ nfc_reg_read(NAND_ECC_STATUS_RESULT_REG));
+ res = -1;
}
return res;
}
#define NAND_BBT_SAVECONTENT 0x00002000
/* Search good / bad pattern on the first and the second page */
#define NAND_BBT_SCAN2NDPAGE 0x00004000
+/* Search good / bad pattern on the last page only */
+#define NAND_BBT_SCANLSTPAGE 0x00008000
/* The maximum number of blocks to scan for a bbt */
#define NAND_BBT_SCAN_MAXBLOCKS 4
--- /dev/null
+static cyg_int8 bbt_pattern[] = {'B', 'b', 't', '0' };
+static cyg_int8 mirror_pattern[] = {'1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr tx25_bbt_main_descr = {
+ .options = (NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+ NAND_BBT_2BIT | NAND_BBT_VERSION),
+ .offs = 0,
+ .len = 4,
+ .veroffs = 4,
+ .maxblocks = 4,
+ .pattern = bbt_pattern,
+};
+
+static struct nand_bbt_descr tx25_bbt_mirror_descr = {
+ .options = (NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+ NAND_BBT_2BIT | NAND_BBT_VERSION),
+ .offs = 0,
+ .len = 4,
+ .veroffs = 4,
+ .maxblocks = 4,
+ .pattern = mirror_pattern,
+};
+
+static struct nand_bbt_descr *g_mxc_nfc_bbt_main_descr = &tx25_bbt_main_descr;
+static struct nand_bbt_descr *g_mxc_nfc_bbt_mirror_descr = &tx25_bbt_mirror_descr;
static cyg_int8 mirror_pattern[] = {'1', 't', 'b', 'B' };
static struct nand_bbt_descr tx27_bbt_main_descr = {
-#if 1
.options = (NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
NAND_BBT_2BIT | NAND_BBT_VERSION),
-#else
- .options = (NAND_BBT_CREATE | NAND_BBT_WRITE |
- NAND_BBT_2BIT | NAND_BBT_VERSION),
-#endif
.offs = 12,
.len = 4,
.veroffs = 11,
.maxblocks = 4,
- .pattern = bbt_pattern
+ .pattern = bbt_pattern,
};
static struct nand_bbt_descr tx27_bbt_mirror_descr = {
.len = 4,
.veroffs = 11,
.maxblocks = 4,
- .pattern = mirror_pattern
+ .pattern = mirror_pattern,
};
static struct nand_bbt_descr *g_mxc_nfc_bbt_main_descr = &tx27_bbt_main_descr;
--- /dev/null
+static cyg_int8 bbt_pattern[] = {'B', 'b', 't', '0' };
+static cyg_int8 mirror_pattern[] = {'1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr tx37_bbt_main_descr = {
+ .options = (NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+ NAND_BBT_2BIT | NAND_BBT_VERSION),
+ .offs = 0,
+ .len = 4,
+ .veroffs = 4,
+ .maxblocks = 4,
+ .pattern = bbt_pattern,
+};
+
+static struct nand_bbt_descr tx37_bbt_mirror_descr = {
+ .options = (NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+ NAND_BBT_2BIT | NAND_BBT_VERSION),
+ .offs = 0,
+ .len = 4,
+ .veroffs = 4,
+ .maxblocks = 4,
+ .pattern = mirror_pattern,
+};
+
+static struct nand_bbt_descr *g_mxc_nfc_bbt_main_descr = &tx37_bbt_main_descr;
+static struct nand_bbt_descr *g_mxc_nfc_bbt_mirror_descr = &tx37_bbt_mirror_descr;
-//==-*- c-basic-offset: 4; tab-width: 4; -*-================================
+//==========================================================================
//
// mxc_nfc.c
//
//
// Author(s): Kevin Zhang <k.zhang@freescale.com>
// Contributors: Kevin Zhang <k.zhang@freescale.com>
-// Date: 2006-01-23
+// Date: 2006-01-23 Initial version
+// Date: 2007-12-20 Update to support 4K page and bbt management.
// Purpose:
// Description:
+// -- Add bad block management according to Linux NAND MTD implementation.
+// Reference linux/drivers/mtd/nand/nand_bbt.c by Thomas Gleixner
+// Summary:
+// 1. Last 4 blocks are reserved for one main BBT and one
+// mirror BBT (2 spare ones just in case a block turns bad.)
+// 2. The main BBT block's spare area starts with "Bbt0" followed
+// by a version number starting from 1.
+// 3. The mirror BBT block's spare area starts with "1tbB" followed
+// by a version number also starting from 1.
+// 4. The actual main area, starting from first page in the BBT block,
+// is used to indicate if a block is bad or not through 2bit/block:
+// * The table uses 2 bits per block
+// * 11b: block is good
+// * 00b: block is factory marked bad
+// * 01b: block is marked bad due to wear
+// * 10b: block is marked reserved (for BBT)
+// Redboot operations: During boot, it searches for the marker for
+// either main BBT or mirror BBT based on the marker:
+// case 1: Neither table is found:
+// Do the bad block scan of the whole flash with ECC off. Use
+// manufactor marked BI field to decide if a block is bad and
+// then build the BBT in RAM. Then write this table to both
+// main BBT block and mirror BBT block.
+// case 2: Only one table is found:
+// Load the BBT from the flash and stored in the RAM.
+// Then build the 2nd BBT in the flash.
+// case 3: If both tables found, load the one with higher version in the
+// RAM and then update the block with older BBT info with the
+// newer one. If same version, just then read out the table in
+// RAM.
//
//####DESCRIPTIONEND####
//
#include <pkgconf/hal.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_cache.h>
+#include <cyg/io/nand_bbt.h>
#include <redboot.h>
#include <stdlib.h>
+#if 0
+static int nfc_debug = 1;
+#endif
#include CYGHWR_MEMORY_LAYOUT_H
+
#include <cyg/hal/hal_io.h>
#define _FLASH_PRIVATE_
#include <cyg/io/flash.h>
-#ifdef CYGPKG_HAL_ARM_MXC30031ADS
-#include <cyg/io/mxc_nfc_v2.h>
-#else
-#include <cyg/io/mxc_nfc.h>
-#endif
-
-#ifdef MXCFLASH_FLASH_BASED_BBT
-#include <cyg/io/nand_bbt.h>
#include CYGHWR_FLASH_NAND_BBT_HEADER
-#endif
-#define MXC_UNLOCK_BLK_END 0xFFFF
+#include <cyg/io/imx_nfc.h>
+
+#define ECC_FORCE_ON 1
+#define ECC_FORCE_OFF 2
+
+typedef u64 flash_addr_t;
+
+enum blk_bad_type
+{
+ BLK_GOOD = 0,
+ BLK_BAD_RUNTIME = 1,
+ BLK_RESERVED = 2,
+ BLK_BAD_FACTORY = 3,
+};
-#define DBG(n, fmt...) nfc_printf((n) + 1, fmt)
+#define diag_printf1(fmt...) CYG_MACRO_START \
+ if (g_nfc_debug_level >= NFC_DEBUG_MIN) diag_printf(fmt); \
+CYG_MACRO_END
+
+#define MXC_UNLOCK_BLK_END 0xFFFF
-static void print_pkt_16(u16* pkt, u32 len);
-static void print_page (u32 addr, bool spare_only);
-static int nfc_read_page(u32 addr);
-static int nfc_read_page_sp(u32 addr);
-static int nfc_program_page(u32 flash_addr, u32 mem_addr, enum nfc_page_area area);
-static void nfc_flash_reset(void);
-static int mxc_nfc_scan(bool verbose);
-static void read_nflash_id(void* id);
+extern unsigned int hal_timer_count(void);
+int nfc_program_region(flash_addr_t addr, u8 *buf, u32 len);
+int nfc_erase_region(flash_addr_t addr, u32 len, bool skip_bad, bool verbose);
+
+static int nfc_write_pg_random(u32 pg_no, u32 pg_off, u8 *buf, u32 ecc_force);
+static int nfc_read_pg_random(u32 pg_no, u32 pg_off, u32 ecc_force, u32 cs_line,
+ u32 num_of_nand_chips);
+static int nfc_erase_blk(u32 ra);
+static void print_page(u32 addr, bool spare_only);
+static int nfc_read_page(u32 cs_line, u32 pg_no, u32 pg_off);
+static int mxc_nfc_scan(bool lowlevel);
+static void read_nflash_id(u32 *id, u32 cs_line);
+static int nfc_program_blk(u32 ra, u8 *buf, u32 len);
+
+static void print_pkt_16(u16 *pkt, u32 len);
+
+// globals
static int nand_flash_index = -1;
static int g_ecc_enable = true;
static int g_spare_only_read_ok = true;
-static int g_nfc_debug_level = NFC_DEBUG_DEF;
+static int g_nfc_debug_level = NFC_DEBUG_NONE;
static bool g_nfc_debug_measure = false;
-static bool g_nfc_scan_done = false;
static bool g_is_2k_page = false;
-static unsigned int g_nfc_version = MXC_NFC_V1;
-static unsigned int is_bad_blk = false;
-
-/*
-//#define NFC_2K_BI_SWAP
- *
- * The i.MX NAND flash controller overlays the 2KiB+64B page FLASH
- * with its internal 512B+16B buffer structure. Thus the indicator bytes
- * for factory bad blocks that are located at column address 2048
- * in the flash end up in the fourth main area buffer at offset 464.
- * This switch enables a routine that swaps the BI byte from the main
- * buffer to the spare buffer so it won't get cleared when the block is
- * programmed.
- * Since the factory bad block indicators are only meaningful for virgin
- * flash chips, the checking for the factory bad block indicators actually
- * needs to be done only once during initial flash programming and bad block
- * table creation.
- * Lateron the factory bad blocks will be mapped out via the bbt.
- *
- * Furthermore, the only thing that the manufacturer guarantees for
- * bad blocks is that the indicator byte in the first or second page
- * of a bad block will contain at least one zero. There is no guarantee
- * that any byte of the bad block will be changeable. Thus, moving the
- * BI to any other byte within the bad block may be impossible.
- *
- * Therefore this switch is NOT defined here!
- */
-
-extern unsigned int hal_timer_count(void);
+static unsigned long g_block_offset;
+static bool g_is_4k_page = false;
+static unsigned int g_nfc_version = MXC_NFC_V1; // default to version 1.0
+static int num_of_nand_chips = 1;
+static int num_of_nand_chips_for_nandsize = 1;
+static int scale_block_cnt = 1;
+
+#define nfc_printf(level, args...) CYG_MACRO_START \
+ if (g_nfc_debug_level >= level) \
+ diag_printf(args); \
+CYG_MACRO_END
+
+#if defined(NFC_V2_0) || defined(NFC_V2_1)
+#include <cyg/io/mxc_nfc_v2.h>
+#elif defined(NFC_V3_0)
+#include <cyg/io/mxc_nfc_v3.h>
+#else
+#include <cyg/io/mxc_nfc.h>
+#endif
-#define nfc_printf(level, args...) \
- do { \
- if (g_nfc_debug_level >= level) \
- diag_printf(args); \
- } while (0)
+#ifndef NAND_LAUNCH_REG
+#define NAND_LAUNCH_REG 0xDEADEEEE
+#define NAND_CONFIGURATION1_REG 0xDEADEEEE
+#define NFC_FLASH_CONFIG2_REG 0xDEADEEEE
+#define NFC_FLASH_CONFIG2_ECC_EN 0xDEADEEEE
+#define write_nfc_ip_reg(a, b)
+#endif
#ifndef MXCFLASH_SELECT_MULTI
void flash_query(void *data)
void nandflash_query(void *data)
#endif
{
- read_nflash_id(data);
- nfc_printf(NFC_DEBUG_MAX, "%s(ID=0x%x: 0x%x, 0x%x, 0x%x)\n",
- __FUNCTION__, *(u8*)(data), *(u8*)((u32)data + 1),
- *(u8*)((u32)data + 2), *(u8*)((u32)data + 3));
+ u32 id[2];
+ read_nflash_id(&id[0], 0);
+ nfc_printf(NFC_DEBUG_MAX, "%s(ID=0x%02x: 0x%02x, 0x%02x, 0x%02x)\n", __FUNCTION__,
+ id[0] & 0xff, (id[0] >> 8) & 0xff, (id[0] >> 16) & 0xff, id[0] >> 24);
+ memcpy(data, id, sizeof(id));
}
#ifndef MXCFLASH_SELECT_MULTI
-int flash_program_buf(void* addr, void* data, int len)
+int flash_program_buf(void *addr, void *data, int len)
#else
-int nandflash_program_buf(void* addr, void* data, int len)
+int nandflash_program_buf(void *addr, void *data, int len)
#endif
{
- nfc_printf(NFC_DEBUG_MAX, "%s(addr=%p, data=%p, len=0x%x)\n",
+ nfc_printf(NFC_DEBUG_MAX, "%s(addr=%p, data=%p, len=0x%08x)\n",
__FUNCTION__, addr, data, len);
- return nfc_program_region((u32)addr, (u32)data, (u32)len);
+ return nfc_program_region((u32)addr, data, len);
}
#ifndef MXCFLASH_SELECT_MULTI
-int flash_erase_block(void* block, unsigned int size)
+int flash_erase_block(void *block, unsigned int size)
#else
-int nandflash_erase_block(void* block, unsigned int size)
+int nandflash_erase_block(void *block, unsigned int size)
#endif
{
- nfc_printf(NFC_DEBUG_MAX, "%s(block=%p, size=0x%x)\n",
+ nfc_printf(NFC_DEBUG_MAX, "%s(block=%p, size=0x%08x)\n",
__FUNCTION__, block, size);
- return nfc_erase_region((u32)block, size);
+ return nfc_erase_region((u32)block, size, 1, 0);
}
#ifndef MXCFLASH_SELECT_MULTI
}
#ifndef MXCFLASH_SELECT_MULTI
-int flash_lock_block(void* block)
+int flash_lock_block(void *block)
#else
-int nandflash_lock_block(void* block)
+int nandflash_lock_block(void *block)
#endif
{
// Not supported yet
}
#ifndef MXCFLASH_SELECT_MULTI
-int flash_unlock_block(void* block, int block_size, int blocks)
+int flash_unlock_block(void *block, int block_size, int blocks)
#else
-int nandflash_unlock_block(void* block, int block_size, int blocks)
+int nandflash_unlock_block(void *block, int block_size, int blocks)
#endif
{
// Not supported yet
cyg_uint16 device_id3;
cyg_uint16 device_id4;
cyg_uint16 page_size;
- cyg_uint32 spare_size;
+ cyg_uint16 spare_size;
cyg_uint32 pages_per_block;
cyg_uint32 block_size;
cyg_int32 block_count;
- cyg_uint32 base_mask;
- cyg_uint32 chipsize;
cyg_uint32 device_size;
cyg_uint32 port_size; // x8 or x16 IO
- cyg_uint32 type; //SLC vs MLC
- const char *vendor_info;
+ cyg_uint32 type; // SLC vs MLC
+ cyg_uint32 options;
+ cyg_uint32 fis_start_addr;
+ cyg_uint32 bi_off;
+ cyg_uint32 bbt_blk_max_nr;
+ cyg_uint8 vendor_info[96];
+ cyg_uint32 col_cycle; // number of column address cycles
+ cyg_uint32 row_cycle; // number of row address cycles
+ cyg_uint32 max_bad_blk;
} flash_dev_info_t;
-static const flash_dev_info_t* flash_dev_info;
+static const flash_dev_info_t *flash_dev_info;
static const flash_dev_info_t supported_devices[] = {
#include <cyg/io/mxc_nand_parts.inl>
};
-#define NUM_DEVICES (sizeof(supported_devices)/sizeof(flash_dev_info_t))
+#define NUM_DEVICES NUM_ELEMS(supported_devices)
-#define NF_PG_SZ flash_dev_info->page_size
+#define COL_CYCLE flash_dev_info->col_cycle
+#define ROW_CYCLE flash_dev_info->row_cycle
+#define NF_PG_SZ ((flash_dev_info->page_size) * num_of_nand_chips)
+#define NF_SPARE_SZ ((flash_dev_info->spare_size) * num_of_nand_chips)
#define NF_PG_PER_BLK flash_dev_info->pages_per_block
-#define NF_DEV_SZ flash_dev_info->device_size
-#define NF_BLK_SZ flash_dev_info->block_size
-#define NF_BLK_CNT flash_dev_info->block_count
-#define NF_SPARE_SZ flash_dev_info->spare_size
-
-#define NAND_PG_SHIFT (g_is_2k_page ? 12 : 9)
-
-// Mask off the higher bits representing linear address of the nand flash
-#define MXC_NAND_LA_MASK (NF_DEV_SZ - 1)
-
-#define NFC_DEVICE_ALIGN(a) ((a) & MXC_NAND_LA_MASK & (~(NF_DEV_SZ - 1)))
-#define NFC_BLOCK_ALIGN(a) ((a) & MXC_NAND_LA_MASK & (~(NF_BLK_SZ - 1)))
-#define NFC_PAGE_ALIGN(a) ((a) & MXC_NAND_LA_MASK & (~(NF_PG_SZ - 1)))
-
-#define BLOCK_TO_OFFSET(blk) (blk * NF_PG_PER_BLK * NF_PG_SZ)
-#define BLOCK_TO_PAGE(blk) (blk * NF_PG_PER_BLK)
-#define BLOCK_PAGE_TO_OFFSET(blk, pge) ((blk * NF_PG_PER_BLK + pge) * NF_PG_SZ)
-#define OFFSET_TO_BLOCK(offset) ((offset / NF_PG_SZ) / NF_PG_PER_BLK)
-#define OFFSET_TO_PAGE(offset) ((offset / NF_PG_SZ) % NF_PG_PER_BLK)
-
-static u8 *bad_block_table;
-static u32 *l_to_p_table;
+#define NF_DEV_SZ ((flash_dev_info->device_size) * num_of_nand_chips_for_nandsize)
+#define NF_BLK_SZ ((flash_dev_info->block_size) * num_of_nand_chips)
+#define NF_BLK_CNT ((flash_dev_info->block_count) / scale_block_cnt)
+#define NF_VEND_INFO flash_dev_info->vendor_info
+#define NF_OPTIONS flash_dev_info->options
+#define NF_BBT_MAX_NR flash_dev_info->bbt_blk_max_nr
+#define NF_OPTIONS flash_dev_info->options
+#define NF_BI_OFF flash_dev_info->bi_off
+
+#define MXC_NAND_ADDR_MASK (NF_DEV_SZ - 1)
+#define BLOCK_TO_OFFSET(blk) ((blk) * NF_PG_PER_BLK * NF_PG_SZ)
+#define BLOCK_TO_PAGE(blk) ((blk) * NF_PG_PER_BLK)
+#define BLOCK_PAGE_TO_OFFSET(blk, pge) (((blk) * NF_PG_PER_BLK + (pge)) * NF_PG_SZ)
+#define OFFSET_TO_BLOCK(offset) (((offset) / NF_PG_SZ) / NF_PG_PER_BLK)
+#define OFFSET_TO_PAGE(offset) (((offset) / NF_PG_SZ) % NF_PG_PER_BLK)
+
+static u8 *g_bbt, *g_page_buf;
+static u32 g_bbt_sz;
static bool mxcnfc_init_ok = false;
+static bool mxc_nfc_scan_done;
-//mxc_nand_fixup_t nand_page_sz_2k_fixup;
-//mxc_nand_fixup_t nand_port_sz_x16_fixup;
-
+// this callback allows the platform specific function to be called right
+// after flash_dev_query()
nfc_setup_func_t *nfc_setup = NULL;
+// this callback allows the platform specific iomux setup
+nfc_iomuxsetup_func_t *nfc_iomux_setup = NULL;
+
int
#ifndef MXCFLASH_SELECT_MULTI
flash_hwr_init(void)
nandflash_hwr_init(void)
#endif
{
- cyg_uint16 id[4];
- int i, bad_block_num;
+ u32 id[2];
+ int i;
+
nfc_printf(NFC_DEBUG_MAX, "%s()\n", __FUNCTION__);
-#ifdef CYGPKG_HAL_ARM_MXC91131
-extern u32 system_rev;
- // take care of the NFC spare-only read bug on MXC91131 TO 2.0
- if (system_rev == CHIP_REV_2_0) {
- g_spare_only_read_ok = false;
- }
-#endif
+
+ if (nfc_iomux_setup)
+ nfc_iomux_setup();
+
+ NFC_SET_NFC_ACTIVE_CS(0);
+ NFC_CMD_INPUT(FLASH_Reset);
// Look through table for device data
+ flash_dev_query(&id[0]);
flash_dev_info = supported_devices;
- flash_dev_query(id);
for (i = 0; i < NUM_DEVICES; i++) {
- if ((flash_dev_info->device_id == id[0]) &&
- (flash_dev_info->device_id2 == 0xFFFF || flash_dev_info->device_id2 == id[1]))
+ if ((flash_dev_info->device_id == (id[0] & 0xffff)) &&
+ (flash_dev_info->device_id2 == 0xFFFF ||
+ flash_dev_info->device_id2 == (id[0] >> 16)))
break;
flash_dev_info++;
}
- nfc_printf(NFC_DEBUG_MED, "%s(): %d out of NUM_DEVICES=%d, id=0x%x\n",
- __FUNCTION__, i, (u32)NUM_DEVICES, flash_dev_info->device_id);
-
// Did we find the device? If not, return error.
if (NUM_DEVICES == i) {
- diag_printf("Unrecognized NAND part: 0x%04x, 0x%04x, 0x%04x, 0x%04x\n",
- id[0], id[1], id[2], id[3]);
+ diag_printf("Unrecognized NAND part: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
+ id[0] & 0xff, (id[0] >> 8) & 0xff, (id[0] >> 16) & 0xff, id[0] >> 24);
return FLASH_ERR_DRV_WRONG_PART;
}
+ nand_flash_index = i;
+ mxcnfc_init_ok = true;
+
if (NF_PG_SZ == 2048) {
g_is_2k_page = true;
g_spare_only_read_ok = false;
}
+ if (NF_PG_SZ == 4096) {
+ g_is_4k_page = true;
+ g_spare_only_read_ok = false;
+ }
+
+ nfc_printf(NFC_DEBUG_MED, "%s(): %d out of NUM_DEVICES=%d, id=0x%02x\n",
+ __FUNCTION__, i, NUM_DEVICES, flash_dev_info->device_id);
+
if (nfc_setup) {
- g_nfc_version = nfc_setup(NF_PG_SZ, flash_dev_info->port_size,
- flash_dev_info->type);
+ g_nfc_version = nfc_setup(NF_PG_SZ / num_of_nand_chips, flash_dev_info->port_size,
+ flash_dev_info->type, num_of_nand_chips);
+ }
+ diag_printf1("NFC version: %02x\n", g_nfc_version);
+ if (g_nfc_version == MXC_NFC_V3) {
+ for (i = 2; i <= NUM_OF_CS_LINES; i++) {
+ u32 id_tmp[2];
+ read_nflash_id(&id_tmp[0], i - 1);
+ if (id[0] != id_tmp[0]) {
+ break;
+ }
+ /* Support interleave with 1, 2, 4, 8 chips */
+ if (i == (num_of_nand_chips * 2)) {
+ num_of_nand_chips = i;
+ }
+ NFC_CMD_INPUT(FLASH_Reset);
+ }
+
+ if (nfc_setup && (num_of_nand_chips > 1)) {
+ nfc_setup(NF_PG_SZ / num_of_nand_chips, flash_dev_info->port_size,
+ flash_dev_info->type, num_of_nand_chips);
+ }
}
- nand_flash_index = i;
- nfc_flash_reset();
- mxcnfc_init_ok = true;
+ NFC_ARCH_INIT();
- bad_block_table = malloc(NF_BLK_CNT / 4);
- if (bad_block_table == NULL) {
- diag_printf("** Error: could not allocate %d byte for bad block table\n",
- NF_BLK_CNT / 4);
+ g_bbt_sz = NF_BLK_CNT / 4;
+ g_bbt = malloc(g_bbt_sz); // two bit for each block
+ if (g_bbt == NULL) {
+ diag_printf("%s(): failed to allocate %d byte for bbt\n", __FUNCTION__, g_bbt_sz);
return FLASH_ERR_PROTOCOL;
}
- l_to_p_table = malloc(NF_BLK_CNT * 4);
- if (l_to_p_table == NULL) {
- diag_printf("** Error: could not allocate %d byte for bad block relocation table\n",
- NF_BLK_CNT * 4);
+
+ g_page_buf = malloc(NF_PG_SZ); // for programming less than one page size buffer
+ if (g_page_buf == NULL) {
+ diag_printf("%s(): failed to allocate %d byte page buffer\n", __FUNCTION__,
+ NF_PG_SZ);
return FLASH_ERR_PROTOCOL;
}
- memset(bad_block_table, 0, NF_BLK_CNT / 4);
- memset(l_to_p_table, 0, NF_BLK_CNT * 4);
+ memset(g_bbt, 0, g_bbt_sz);
- nfc_printf(NFC_DEBUG_MAX, "%s(bad_block_table=%p)\n",
- __FUNCTION__, bad_block_table);
- bad_block_num = mxc_nfc_scan(false);
-
- nfc_printf(NFC_DEBUG_MIN, "\nFound %d bad/reserved blocks\n\n", bad_block_num);
+ /* For now cap off the Device size to 2GB */
+ i = 1;
+ while ((i <= num_of_nand_chips) && ((NF_DEV_SZ * i) < 0x80000000)) {
+ num_of_nand_chips_for_nandsize = i;
+ i *= 2;
+ }
+ scale_block_cnt = num_of_nand_chips / num_of_nand_chips_for_nandsize;
// Hard wired for now
flash_info.block_size = NF_BLK_SZ;
- flash_info.blocks = NF_BLK_CNT - bad_block_num;
+ flash_info.blocks = NF_BLK_CNT - CYGNUM_FLASH_NAND_BBT_BLOCKS;
flash_info.start = (void *)MXC_NAND_BASE_DUMMY;
- flash_info.end = (void *)(MXC_NAND_BASE_DUMMY + (NF_DEV_SZ) -
- (bad_block_num * NF_BLK_SZ));
-
- nfc_printf(NFC_DEBUG_MED, "%s(): block_size=0x%x, blocks=0x%x, start=%p, end=%p\n",
- __FUNCTION__, flash_info.block_size, flash_info.blocks,
- flash_info.start, flash_info.end);
-
- return FLASH_ERR_OK;
-}
+ flash_info.end = (void *)(MXC_NAND_BASE_DUMMY + NF_DEV_SZ -
+ CYGNUM_FLASH_NAND_BBT_BLOCKS * NF_BLK_SZ);
-/*!
- * Starts the address input cycles for different operations as defined in ops.
- *
- * @param ops operations as defined in enum nfc_addr_ops
- * @param addr starting address
- * @param mask mask for the full address range of the nand flash
- * For 64MB flash, the mask should be 0x03FFFFFF (64MB-1)
- */
-static void start_nfc_addr_ops(enum nfc_addr_ops ops, u32 addr, u32 mask)
-{
- u32 m = mask, a = addr;
+ mxc_nfc_scan(false); // look for table
- switch (ops) {
- case ADDRESS_INPUT_READ_ID:
- NFC_ADDR_INPUT(0);
- return;
- case ADDRESS_INPUT_READ_PAGE:
- case ADDRESS_INPUT_PROGRAM_PAGE:
- if (g_is_2k_page) {
- NFC_ADDR_INPUT(a & 0xFF);
- NFC_ADDR_INPUT((a >> 8) & 0xF);
- } else {
- NFC_ADDR_INPUT(a & 0xFF);
- }
- // don't break on purpose
- case ADDRESS_INPUT_ERASE_BLOCK:
- a >>= NAND_PG_SHIFT;
- m >>= NAND_PG_SHIFT;
- break;
- default:
- diag_printf("!!!!!! %s(): wrong ops: %d !!!!!\n", __FUNCTION__, ops);
- return;
- }
+ diag_printf1("%s(): block_size=0x%08x, blocks=0x%08x, start=%p, end=%p\n",
+ __FUNCTION__, flash_info.block_size, flash_info.blocks,
+ flash_info.start, flash_info.end);
- do {
- NFC_ADDR_INPUT(a);
- m >>= ADDR_INPUT_SIZE;
- a >>= ADDR_INPUT_SIZE;
- } while (m != 0);
+ return FLASH_ERR_OK;
}
-// Doesn't seem to need it as when reaching here means past the query
-// function. So reset isn't necessary.
-static void nfc_flash_reset(void)
+// used by redboot/current/src/flash.c
+int mxc_nand_fis_start(void)
{
-#ifdef MXC_NFC_RESET
- nfc_printf(NFC_DEBUG_MAX, "%s()\n", __FUNCTION__);
- NFC_PRESET(MXC_UNLOCK_BLK_END);
- NFC_CMD_INPUT(FLASH_Reset);
-#endif
+ return flash_dev_info->fis_start_addr * num_of_nand_chips;
}
-static u8 get_byte(cyg_uint16 *buf, int offs)
+static inline u8 get_byte(cyg_uint16 *buf, int offs)
{
cyg_uint16 word = buf[offs >> 1];
if (offs & 1) {
return word & 0xff;
}
-static void store_byte(cyg_uint16 *buf, int offs, u8 val)
+static inline void store_byte(cyg_uint16 *buf, int offs, u8 val)
{
cyg_uint16 word = buf[offs >> 1];
buf[offs >> 1] = word;
}
-static void nfc_buf_mem_cpy(void *dst, void *src, u32 len)
+static inline bool nfc_verify_addr(unsigned long dst, unsigned long len)
+{
+ if (dst < NAND_MAIN_BUF0 || dst + len >= NAND_SPAR_BUF3 + NFC_SPARE_BUF_SZ) {
+ diag_printf("%s: Bad NFC Buffer address 0x%08lx\n", __FUNCTION__, dst);
+ return false;
+ }
+ return true;
+}
+
+static void nfc_buf_read(void *dst, unsigned long src, u32 len)
{
- u16 *d = dst, *s = src;
+ u16 *s = (u16 *)(src & ~1);
+ u8 *bp = dst;
- if (((unsigned long)dst & 1) || ((unsigned long)src & 1)) {
- diag_printf("%s: Source (%p) or destination address (%p) not halfword aligned\n",
- __FUNCTION__, src, dst);
+ if (len == 0) {
return;
}
- if (len == 0) {
+ if (src + len < src) {
+ diag_printf("%s: Bad address range 0x%08lx .. 0x%08lx\n", __FUNCTION__,
+ src, src + len);
+ }
+ if ((unsigned long)dst + len < (unsigned long)dst) {
+ diag_printf("%s: Bad address range 0x%08lx .. 0x%08lx\n", __FUNCTION__,
+ (unsigned long)dst, (unsigned long)dst + len);
+ }
+ if (src < NAND_MAIN_BUF0 || src + len >= NAND_SPAR_BUF3 + NF_PG_SZ) {
+ diag_printf("%s: Bad NFC Buffer address 0x%08lx\n", __FUNCTION__, src);
return;
}
- do {
- *d++ = *s++;
- len -= 2;
- } while (len > 1);
+ if ((unsigned long)dst >= NAND_MAIN_BUF0 &&
+ (unsigned long)dst < NAND_SPAR_BUF3 + NF_PG_SZ) {
+ diag_printf("%s: Bad memory address 0x%08lx\n", __FUNCTION__,
+ (unsigned long)dst);
+ return;
+ }
+ if (src & 1) {
+ *bp++ = get_byte(s, 1);
+ s++;
+ len--;
+ }
+ if ((unsigned long)bp & 1) {
+ while (len > 1) {
+ u16 word = *s++;
+ *bp++ = word & 0xff;
+ *bp++ = word >> 8;
+ len -= 2;
+ }
+ } else {
+ u16 *wp = (u16 *)bp;
+ while (len > 1) {
+ *wp++ = *s++;
+ len -= 2;
+ }
+ bp = (u8*)wp;
+ }
if (len != 0) {
- u16 tmp = *d;
- tmp = (tmp & ~0xff) | (*s & 0xff);
+ u16 word = *s;
+ *bp = word & 0xff;
}
}
-static void read_nflash_id(void *id)
-{
- volatile u32 *ptr = (u32*)NAND_MAIN_BUF0;
- volatile u32 *id_32 = (u32*)id;
-
- nfc_printf(NFC_DEBUG_MAX, "%s()\n", __FUNCTION__);
-// NFC_PRESET(NF_BLK_CNT -1); -- doesn't work for 2k flash, why?
- NFC_PRESET(MXC_UNLOCK_BLK_END);
- NFC_CMD_INPUT(FLASH_Read_ID);
- start_nfc_addr_ops(ADDRESS_INPUT_READ_ID, 0, 0);
- NFC_DATA_OUTPUT(RAM_BUF_0, FDO_FLASH_ID, g_ecc_enable);
-
- *id_32++ = *ptr++;
- *id_32++ = *ptr++;
-}
-
-static u8 bad_block_code(int block)
+static void nfc_buf_write(unsigned long dst, void *src, u32 len)
{
- int offs = block >> 2;
- int shift = (block & 0x03) << 1;
- u8 code = (bad_block_table[offs] >> shift) & 0x03;
+ u8 *bp = src;
+ u16 *d = (u16 *)(dst & ~1);
- if (code != 0) {
- DBG(0, "Block %d is marked %s (%02x) in mem bbt @ %04x\n", block,
- (code != 2) ? "bad" : "reserved", code, offs);
+ if (len == 0) {
+ return;
+ }
+ if (!nfc_verify_addr(dst, len)) {
+ return;
+ }
+ if (dst & 1) {
+ store_byte(d, 1, *bp);
+ d++;
+ bp++;
+ len--;
+ }
+ if ((unsigned long)bp & 1) {
+ while (len > 1) {
+ u16 word;
+ word = *bp++;
+ word |= (u16)(*bp++) << 8;
+ *d++ = word;
+ len -= 2;
+ }
+ } else {
+ u16 *wp = (u16 *)bp;
+ while (len > 1) {
+ *d++ = *wp++;
+ len -= 2;
+ }
+ bp = (u8 *)wp;
+ }
+ if (len != 0) {
+ store_byte(d, 1, *bp);
}
- return code;
}
+#ifndef NFC_V3_0
/*!
- * Checks to see if a block is bad by looking at the 6th byte of the spare area
- * inside a page.
- * @param ra starting address in the raw address space (offset)
- * (No error checking). It doesn't have to be block-aligned.
- * @return true if bad block; false otherwise
+ * Starts the address input cycles for different operations as defined in ops.
+ *
+ * @param ops operations as defined in enum nfc_addr_ops
+ * @param pg_no page number offset from 0
+ * @param pg_off byte offset within the page
+ * @param is_erase don't care for earlier NFC
+ * @param cs_line don't care for earlier NFC
*/
-static u8 nfc_is_badblock(u32 ra)
+static void start_nfc_addr_ops(u32 ops, u32 pg_no, u32 pg_off, u32 is_erase,
+ u32 cs_line, u32 num_of_chips)
{
- u32 block = OFFSET_TO_BLOCK(ra), ecc_val = g_ecc_enable;
- bool res = false;
- u16 temp, i;
-
- if (g_nfc_scan_done) {
- if (block >= NF_BLK_CNT) {
- diag_printf("Error %d: Block count out of range: %d\n", __LINE__, block);
- return true;
- }
- return bad_block_code(block);
- }
+ int i;
- // turn off ecc when scanning for bad blocks
-// g_ecc_enable = false; // TODO: we should turn OFF ecc
- g_ecc_enable = true;
- // check for the 1st and 2nd pages
- for (i = 0, ra = NFC_BLOCK_ALIGN(ra); i < 2; i++, ra += NF_PG_SZ) {
- if (nfc_read_page(ra) != 0) {
- diag_printf("Warning: uncorrectable ECC at addr 0x%08x\n", ra);
+ switch (ops) {
+ case FLASH_Read_ID:
+ /* Only supports one NAND chip (CS0) */
+ if (cs_line != 0)
+ return;
+ NFC_ADDR_INPUT(0);
+ return;
+ case FLASH_Read_Mode1:
+ case FLASH_Program:
+ for (i = 0; i < COL_CYCLE; i++, pg_off >>= 8) {
+ NFC_ADDR_INPUT(pg_off & 0xFF);
}
- if (g_is_2k_page && is_bad_blk) {
- DBG(3, "Bad block %d\n", block);
- res = true;
- break;
- } else {
- temp = readw(NAND_SPAR_BUF0 + 4);
- if ((temp >> 8) != 0xFF) {
- res = true;
- DBG(2, "Block %d is marked bad in OOB area\n", block);
- print_pkt_16((u16*)(NAND_SPAR_BUF0), g_is_2k_page ? 64 : 16);
- break;
- }
+ // don't break on purpose
+ case FLASH_Block_Erase:
+ for (i = 0; i < ROW_CYCLE; i++, pg_no >>= 8) {
+ NFC_ADDR_INPUT(pg_no & 0xFF);
}
+ break;
+ default:
+ diag_printf("!!!!!! %s(): wrong ops: %d !!!!!\n", __FUNCTION__, ops);
+ return;
}
- g_ecc_enable = ecc_val;
- return res;
+}
+#endif // #ifndef NFC_V3_0
+
+static void read_nflash_id(u32 *id, u32 cs_line)
+{
+ volatile u32 *ptr = (volatile u32*)NAND_MAIN_BUF0;
+
+ nfc_printf(NFC_DEBUG_MIN, "%s: read flash id from chip %d @ %p\n",
+ __FUNCTION__, cs_line, ptr);
+
+ NFC_PRESET(MXC_UNLOCK_BLK_END);
+ NFC_SET_NFC_ACTIVE_CS(cs_line);
+ NFC_CMD_INPUT(FLASH_Read_ID);
+
+ start_nfc_addr_ops(FLASH_Read_ID, 0, 0, 0, cs_line, num_of_nand_chips);
+ NFC_DATA_OUTPUT(RAM_BUF_0, FDO_FLASH_ID, g_ecc_enable);
+
+ *id++ = *ptr++;
+ *id++ = *ptr++;
}
-static void nfc_update_blk_table(u32 faddr, u8 is_bad)
+static void mark_blk_bad(unsigned int block, unsigned char *buf,
+ enum blk_bad_type bad_type)
{
- u32 block = OFFSET_TO_BLOCK(faddr);
- int offs = block >> 2;
- int shift = (block & 0x03) << 1;
- u8 mask = 0x03 << shift;
+ unsigned int off = block >> 2; // byte offset - each byte can hold status for 4 blocks
+ unsigned int sft = (block & 3) << 1; // bit shift 0, 2, 4, 6
+ unsigned char val = buf[off];
- if (block >= NF_BLK_CNT) {
- diag_printf("Block count out of range: %d\n", block);
+ if (block > NF_BLK_CNT) {
+ diag_printf("%s: Block number %u out of range: 0..%u\n", __FUNCTION__,
+ block, NF_BLK_CNT - 1);
return;
}
- if (is_bad) {
- nfc_printf(NFC_DEBUG_MED, "marking block %d %s\n", block,
- is_bad == 2 ? "reserved" : "bad");
- bad_block_table[offs] = (bad_block_table[offs] & ~mask) | (is_bad << shift);
- } else {
- nfc_printf(NFC_DEBUG_MAX, "Block %d is good\n", block);
- bad_block_table[offs] &= ~mask;
- }
+ val = (val & ~(3 << sft)) | (bad_type << sft);
+ buf[off] = val;
}
/*!
- * Erase a block without checking the BI field. If the block is bad, mark it
- * in the global table. Note that there is NO error checking for passed-in ra.
- * @param ra starting address in the raw address space (offset)
- * Must be block-aligned
- * @return 0 if successful; -1 otherwise
+ * Checks to see if a block is bad. If buf is not NULL, it indicates a valid
+ * BBT in the RAM. In this case, it assumes to have 2-bit to represent each
+ * block for good or bad
+ * * 11b: block is good
+ * * 00b: block is factory marked bad
+ * * 01b: block is marked bad due to wear
+ * * 10b: block is marked reserved (for BBT)
+ * If buf is NULL, then it indicates a low level scan based on the certain
+ * offset value in certain pages and certain offset to be non-0xFF. In this
+ * case, the HW ECC will be turned off.
+ *
+ * @param block 0-based block number
+ * @param buf BBT buffer. Could be NULL (see above explanation)
+ *
+ * @return 1 if bad block; 0 otherwise
*/
-static int nfc_erase_blk(u32 ra)
+static int nfc_is_badblock(u32 block, u8 *buf)
{
- u16 flash_status;
- u32 flash_addr;
-
- if (ra % NF_BLK_SZ) {
- diag_printf("** Error: block erase address must be block aligned: 0x%08x\n", ra);
- return -1;
+ u32 off; // byte offset
+ u32 sft; // bit shift 0, 2, 4, 6
+ flash_addr_t addr;
+ u16 temp, i;
+ int res;
+ u32 pg_no;
+
+ if (buf) {
+ // use BBT
+ off = block >> 2; // byte offset
+ sft = (block & 3) << 1; // bit shift 0, 2, 4, 6
+ res = (buf[off] >> sft) & 0x3;
+ if (res) {
+ addr = BLOCK_TO_OFFSET(block);
+ diag_printf1("Block %u at %08llx is marked %s (%d) in BBT@%p[%02x] mask %02x\n",
+ block, (u64)addr, res == BLK_RESERVED ? "reserved" :
+ res == BLK_BAD_FACTORY ? "factory bad" : "runtime bad",
+ res, buf, off, 3 << sft);
+ }
+ return res;
+ }
+
+ // need to do low level scan with ECC off
+ if (NF_OPTIONS & NAND_BBT_SCANLSTPAGE) {
+ if (g_is_4k_page || g_is_2k_page) {
+ addr = (block + 1) * NF_BLK_SZ - NF_PG_SZ;
+ pg_no = addr / NF_PG_SZ;
+ for (i = 0; i < num_of_nand_chips; i++) {
+ // we don't do partial page read here. No ecc either
+ nfc_read_pg_random(pg_no, 0, ECC_FORCE_OFF, i, num_of_nand_chips);
+ temp = readw((u32)NAND_MAIN_BUF0 + NF_BI_OFF);
+ if ((temp & 0xFF) != 0xFF) {
+ return BLK_BAD_FACTORY;
+ }
+ }
+ } else {
+ diag_printf("only 2K/4K page is supported\n");
+ // die here -- need to fix the SW
+ while (1);
+ }
+ return 0;
}
- flash_addr = (ra / NF_PG_SZ) << NAND_PG_SHIFT;
- nfc_printf(NFC_DEBUG_MED, "%s: Erasing block %d @ %08x\n", __FUNCTION__, ra / NF_BLK_SZ, ra);
-
- NFC_CMD_INPUT(FLASH_Block_Erase);
-
- start_nfc_addr_ops(ADDRESS_INPUT_ERASE_BLOCK, flash_addr, MXC_NAND_LA_MASK);
- NFC_CMD_INPUT(FLASH_Start_Erase);
-
- flash_status = NFC_STATUS_READ();
-
- // check I/O bit 0 to see if it is 0 for success
- if ((flash_status & 0x1) != 0) {
- diag_printf("** Error: failed to erase block %d at %08x; status=0x%x\n",
- OFFSET_TO_BLOCK(ra), ra, flash_status);
- nfc_update_blk_table(ra, true);
- return -1;
+ addr = block * NF_BLK_SZ;
+ pg_no = addr / NF_PG_SZ;
+ for (i = 0; i < num_of_nand_chips; i++) {
+ nfc_read_pg_random(pg_no, 0, ECC_FORCE_OFF, i, num_of_nand_chips); // no ecc
+ if (g_is_2k_page || g_is_4k_page) {
+ temp = readw(NAND_MAIN_BUF0 + NF_BI_OFF);
+ } else {
+ temp = readw(NAND_SPAR_BUF0 + 4) >> 8; // BI is at 5th byte in spare area
+ }
+ if ((temp & 0xFF) != 0xFF) {
+ return BLK_BAD_FACTORY;
+ }
+ }
+ if (NF_OPTIONS & NAND_BBT_SCAN2NDPAGE) {
+ addr += NF_PG_SZ;
+ pg_no++;
+ for (i = 0; i < num_of_nand_chips; i++) {
+ nfc_read_pg_random(pg_no, 0, ECC_FORCE_OFF, i, num_of_nand_chips); // no ecc
+ if (g_is_2k_page || g_is_4k_page) {
+ temp = readw(NAND_MAIN_BUF0 + NF_BI_OFF);
+ } else {
+ temp = readw(NAND_SPAR_BUF0 + 4) >> 8; // BI is at 5th byte in spare area
+ }
+ if ((temp & 0xFF) != 0xFF) {
+ return BLK_BAD_FACTORY;
+ }
+ }
}
return 0;
}
-/*!
- * Program a block of data in the flash. This function doesn't do
- * bad block checking. But if program fails, it returns an error code.
- * @param ra destination raw flash address
- * @param maddr source address in the RAM
- @ @return 0 if successful; -1 otherwise
- */
-static int nfc_program_blk(u32 ra, u32 maddr)
+/*
+ * check_short_pattern - [GENERIC] check if a pattern is in the buffer
+ * @buf: the buffer to search
+ * @td: search pattern descriptor
+ *
+ * Check for a pattern at the given place. Used to search bad block
+ * tables and good / bad block identifiers.
+*/
+static int check_short_pattern(void *buf, struct nand_bbt_descr *td)
{
- u32 i;
+ int i;
- for (i = 0; i < NF_PG_PER_BLK; i++) {
- if (nfc_program_page(ra, maddr, NFC_MAIN_ONLY) != 0) {
- nfc_update_blk_table(ra, true);
+ for (i = 0; i < td->len; i++) {
+ if (get_byte(buf, td->offs + i) != td->pattern[i]) {
return -1;
}
- ra += NF_PG_SZ;
- maddr += NF_PG_SZ;
}
return 0;
}
+static int nfc_write_page(u32 pg_no, u32 pg_off, u32 ecc_force);
/*
- * Convert a linear address to raw address. No address checking in this function.
- * @param la linear address used by the upper flash driver
- * @return raw address for NAND flash
+ * Program g_bbt into the NAND block with offset at g_main_bbt_addr.
+ * This assumes that the g_bbt has been built already.
+ *
+ * If g_main_bbt_addr is 0, search for a free block from the bottom 4 blocks (but make
+ * sure not re-using the mirror block). If g_mirror_bbt_page is 0, do the same thing.
+ * Otherwise, just use g_main_bbt_addr, g_mirror_bbt_page numbers to prgram the
+ * g_bbt into those two blocks.
+ * todo: need to do the version to see which one is newer.
+ *
+ * @return 0 if successful; -1 otherwise.
*/
-static u32 nfc_l_to_p(u32 la)
+static int mxc_nfc_write_bbt_page(struct nand_bbt_descr *td)
{
- u32 block, offset, ra;
+ int ret;
+ u32 block = td->pages / NF_PG_PER_BLK;
+ flash_addr_t addr = td->pages * NF_PG_SZ;
- block = la / NF_BLK_SZ;
- offset = la % NF_BLK_SZ;
- ra = (l_to_p_table[block] * NF_BLK_SZ) + offset;
+ ret = nfc_erase_blk(addr);
+ if (ret != 0) {
+ diag_printf("Failed to erase bbt block %u\n", block);
+ return ret;
+ }
+ ret = nfc_write_page(td->pages, 0, 0);
+ if (ret != 0) {
+ diag_printf("Failed to write bbt block %u\n", block);
+ return ret;
+ }
+ mark_blk_bad(block, g_bbt, BLK_RESERVED);
+ return 0;
+}
- nfc_printf(NFC_DEBUG_MAX, "\n%s(): l_to_p_table[0x%08x]=0x%08x, offset=0x%08x\n",
- __FUNCTION__, block, l_to_p_table[block], offset);
- nfc_printf(NFC_DEBUG_MAX, "%s(la=0x%08x, ra=0x%08x)\n",
- __FUNCTION__, la, ra);
- return ra;
+static inline void mxc_nfc_buf_clear(unsigned long buf, u8 pattern, int size)
+{
+ int i;
+ u16 *p = (u16 *)buf;
+ u16 fill = pattern;
+ fill = (fill << 8) | pattern;
+ for (i = 0; i < size >> 1; i++) {
+ p[i] = fill;
+ }
}
-/*!
- * Erase a range of NAND flash
- * @param la linear NAND flash address. it has to be block size aligned
- * @param len number of bytes
- * @return FLASH_ERR_OK (0) if successful; non-zero otherwise
- */
-int nfc_erase_region(u32 la, int len)
+
+static int mxc_nfc_write_bbt(struct nand_bbt_descr *td, struct nand_bbt_descr *md)
{
- u32 ra;
+ int ret = -1;
+ int block;
+ int pg_offs = 0;
+ int page = 0;
+ u16 *buf = (u16 *)NAND_MAIN_BUF0;
- nfc_printf(NFC_DEBUG_MED, "%s(la=0x%08x, len=0x%08x)\n", __FUNCTION__, la, len);
+ for (block = NF_BLK_CNT - 1; block >= NF_BLK_CNT - td->maxblocks - 1; block--) {
+ int pg = block * NF_PG_PER_BLK;
- la &= MXC_NAND_LA_MASK;
- if ((la % NF_BLK_SZ) != 0) {
- diag_printf("** Error: address %08x not aligned to block boundary\n", la);
- return FLASH_ERR_INVALID;
+ if ((nfc_is_badblock(block, g_bbt) & 1) == 0) {
+ if (md != NULL && md->pages == pg) {
+ continue;
+ }
+ td->pages = pg;
+ break;
+ }
}
- if (len <= 0 || la + len >= NF_DEV_SZ) {
- diag_printf("** Error: invalid length %d\n", len);
- return FLASH_ERR_INVALID;
+ if (td->pages < 0) {
+ return -1;
}
+ mxc_nfc_buf_clear(NAND_SPAR_BUF0, 0xff, NF_SPARE_SZ);
+ mxc_nfc_buf_clear(NAND_MAIN_BUF0, 0xff, NF_PG_SZ);
+ diag_printf1("%s: Updating bbt %c%c%c%c version %d\n", __FUNCTION__,
+ td->pattern[0], td->pattern[1], td->pattern[2], td->pattern[3], td->version);
+ nfc_buf_write(NAND_SPAR_BUF0 + td->offs, td->pattern, td->len);
+ store_byte((u16 *)NAND_SPAR_BUF0, td->veroffs, td->version);
- // now la has to be block aligned
- do {
- ra = nfc_l_to_p(la);
- la += NF_BLK_SZ;
+ for (block = 0, pg_offs = 0; block < NF_BLK_CNT; pg_offs++) {
+ u16 tmp = 0xffff;
+ int i;
- if (ra > (NF_DEV_SZ - NF_BLK_SZ)) {
- diag_printf("** Error: la=0x%08x (ra=0x%08x) is out of valid range\n", la, ra);
- return FLASH_ERR_ERASE;
+ if (pg_offs << 1 >= NF_PG_SZ) {
+ ret = mxc_nfc_write_bbt_page(td);
+ if (ret != 0) {
+ return ret;
+ }
+ page++;
+ mxc_nfc_buf_clear(NAND_SPAR_BUF0, 0xff, NF_SPARE_SZ);
+ mxc_nfc_buf_clear(NAND_MAIN_BUF0, 0xff, NF_PG_SZ);
+ pg_offs = 0;
}
- if (nfc_is_badblock(ra)) {
- diag_printf("** Error: bad block: %d at address %08x\n",
- OFFSET_TO_BLOCK(ra), ra);
- return FLASH_ERR_ERASE;
- } else {
- if (nfc_erase_blk(ra) == 0) {
- // erase ok
- len -= NF_BLK_SZ;
+ for (i = 0; i < 16 && block < NF_BLK_CNT; i += 2, block++) {
+ u8 code = nfc_is_badblock(block, g_bbt);
+ if ((code & 1) != 0) {
+ tmp &= ~(code << i);
+ diag_printf1("%s: bad block %u pattern[%p] 0x%04x mask 0x%04x\n", __FUNCTION__,
+ block, &buf[pg_offs], tmp, 0x03 << i);
+ }
+ }
+ buf[pg_offs] = tmp;
+ }
+ if (pg_offs > 0) {
+ diag_printf1("%s: Writing final bbt block %d page %d\n", __FUNCTION__,
+ td->pages / NF_PG_PER_BLK, page);
+ ret = mxc_nfc_write_bbt_page(td);
+ }
+ return ret;
+}
+
+static int mxc_nfc_update_bbt(struct nand_bbt_descr *td, struct nand_bbt_descr *md)
+{
+ int ret;
+
+ if (td == NULL) {
+ return -1;
+ }
+ if (td->pages < 0 && (md == NULL || md->pages == -1)) {
+ td->version = 1;
+ } else {
+ if (md != NULL && md->pages >= 0) {
+ if (md->version >= td->version) {
+ td->version = ++md->version;
} else {
- return FLASH_ERR_ERASE;
+ md->version = ++td->version;
}
+ } else {
+ td->version++;
}
- } while (len > 0);
+ }
+ ret = mxc_nfc_write_bbt(td, md);
+ if (ret) {
+ diag_printf("** Error: Failed to update main BBT\n");
+ }
+ if (md) {
+ ret = mxc_nfc_write_bbt(md, td);
+ if (ret) {
+ diag_printf("** Error: Failed to update mirror BBT\n");
+ }
+ }
+ return ret;
+}
- return FLASH_ERR_OK;
+static int program_bbt_to_flash(void)
+{
+ return mxc_nfc_update_bbt(g_mxc_nfc_bbt_main_descr, g_mxc_nfc_bbt_mirror_descr);
}
/*!
- * Program data from memory to flash
- * @param la linear NAND flash address. it has to be block size aligned
- * @param maddr memory buf address where data will be copied from
- * @param len number of bytes
- * @return FLASH_ERR_OK (0) if successful; non-zero otherwise
+ * Unconditionally erase a block without checking the BI field.
+ * Note that there is NO error checking for passed-in ra.
+ *
+ * @param ra starting address in the raw address space (offset)
+ * Must be block-aligned
+ * @return 0 if successful; -1 otherwise
*/
-int nfc_program_region(u32 la, u32 maddr, int len)
+static int nfc_erase_blk(u32 ra)
{
- u32 ra;
-
- nfc_printf(NFC_DEBUG_MED, "%s(la=0x%08x, maddr=0x%08x, len=0x%x)\n",
- __FUNCTION__, la, maddr, len);
+ u16 flash_status, i;
+ u32 pg_no, pg_off;
+
+ if (g_nfc_version == MXC_NFC_V3) {
+ // combine the two commands for erase
+ writel((FLASH_Start_Erase << 8) | FLASH_Block_Erase, NAND_CMD_REG);
+ pg_no = ra / NF_PG_SZ;
+ pg_off = ra % NF_PG_SZ;
+ for (i = 0; i < num_of_nand_chips; i++) {
+ start_nfc_addr_ops(FLASH_Block_Erase, pg_no, pg_off, 1, i, num_of_nand_chips);
+ // start auto-erase
+ writel(NAND_LAUNCH_AUTO_ERASE, NAND_LAUNCH_REG);
+ wait_op_done();
+ pg_off = 0;
+ }
+ flash_status = NFC_STATUS_READ();
+ // check I/O bit 0 to see if it is 0 for success
+ if ((flash_status & ((0x1 << num_of_nand_chips) - 1)) != 0) {
+ return -1;
+ }
+ } else {
+ NFC_CMD_INPUT(FLASH_Block_Erase);
+ start_nfc_addr_ops(FLASH_Block_Erase, ra / NF_PG_SZ, ra % NF_PG_SZ,
+ 1, 0, num_of_nand_chips);
+ NFC_CMD_INPUT(FLASH_Start_Erase);
- la &= MXC_NAND_LA_MASK;
+ flash_status = NFC_STATUS_READ();
- if ((la % NF_BLK_SZ) != 0 || len <= 0) {
- diag_printf("%s(): invalid or not block aligned\n", __FUNCTION__);
- diag_printf("la=0x%08x, len=%d\n", la, len);
- return FLASH_ERR_INVALID;
+ // check I/O bit 0 to see if it is 0 for success
+ if ((flash_status & 0x1) != 0) {
+ return -1;
+ }
}
+ return 0;
+}
- do {
- ra = nfc_l_to_p(la);
- la += NF_BLK_SZ;
+/*!
+ * Program a block of data in the flash. This function doesn't do
+ * bad block checking. But if program fails, it return error.
+ * Note: If "len" is less than a block it will program up to a page's
+ * boundary. If not within a page boundary, then it fills the
+ * rest of the page with 0xFF.
+ *
+ * @param ra destination raw flash address
+ * @param buf source address in the RAM
+ * @param len len to be programmed
+ *
+ * @return 0 if successful; -1 otherwise
+ */
+static int nfc_program_blk(u32 ra, u8 *buf, u32 len)
+{
+ u32 temp = num_of_nand_chips;
- if (ra > (NF_DEV_SZ - NF_BLK_SZ)) {
- diag_printf("%s()1: la=0x%08x (ra=0x%08x) is out of valid range\n",
- __FUNCTION__, la, ra);
- return FLASH_ERR_PROGRAM;
- }
+ /* Needed when romupdate is called */
+ if (ra == 0)
+ num_of_nand_chips = 1;
- if (nfc_is_badblock(ra)) {
- diag_printf("\n%s(ra=0x%08x): bad block: %d\n",
- __FUNCTION__, ra, OFFSET_TO_BLOCK(ra));
- return FLASH_ERR_PROGRAM;
- } else {
- if (nfc_program_blk(ra, maddr) == 0) {
- len -= NF_BLK_SZ;
- maddr += NF_BLK_SZ;
- } else {
- diag_printf("\n%s2(ra=0x%08x): bad block: %d\n",
- __FUNCTION__, ra, OFFSET_TO_BLOCK(ra));
- return FLASH_ERR_PROGRAM;
- }
+ for (; len >= NF_PG_SZ; len -= NF_PG_SZ) {
+ if (nfc_write_pg_random(ra / NF_PG_SZ, ra % NF_PG_SZ, buf, 0) != 0) {
+ return -1;
}
- } while (len > 0);
-
- return FLASH_ERR_OK;
+ ra += NF_PG_SZ;
+ buf += NF_PG_SZ;
+ }
+ if (len != 0) {
+ memset(g_page_buf + len, 0xFF, NF_PG_SZ - len);
+ memcpy(g_page_buf, buf, len);
+ if (nfc_write_pg_random(ra / NF_PG_SZ, ra % NF_PG_SZ, g_page_buf, 0) != 0) {
+ num_of_nand_chips = temp;
+ return -1;
+ }
+ }
+ num_of_nand_chips = temp;
+ return 0;
}
/*!
- * Read data from linear NAND flash address to memory. The MSB of the passed-
- * in flash address will be masked off inside the function.
- *
- * @param la linear NAND flash address. it has to be page aligned
- * @param mem_addr memory buf address where data will be copied to
+ * Erase a range of NAND flash good blocks only.
+ * It skips bad blocks and update the BBT once it sees new bad block due to erase.
+ * @param addr raw NAND flash address. it has to be block size aligned
* @param len number of bytes
+ * @param skip_bad if 1, don't erase bad block; otherwise, always erase
+ * @param verbose use true to print more messages
+ *
* @return FLASH_ERR_OK (0) if successful; non-zero otherwise
*/
-int nfc_read_region(u32 la, u32 mem_addr, int len)
+int nfc_erase_region(flash_addr_t addr, u32 len, bool skip_bad, bool verbose)
{
- u32 ra;
- u32 dst = mem_addr;
-
- // make sure 32-bit aligned
- len = (len + 3) & (~0x3);
-
- nfc_printf(NFC_DEBUG_MED, "\n%s(la=0x%08x, mem_addr=0x%08x, len=0x%x)\n",
- __FUNCTION__, la, mem_addr, len);
+ u32 sz, blk, update = 0, skip = 0, j = 0;
- if (la < (u32)(flash_info.start) || (la + len) > (u32)(flash_info.end)) {
- diag_printf("\n%s(): Error: invalid address=0x%08x, len=%d\n",
- __FUNCTION__, la, len);
- return FLASH_ERR_INVALID;
- }
- la &= MXC_NAND_LA_MASK;
+ nfc_printf(NFC_DEBUG_MED, "%s: addr=0x%08llx len=0x%08x\n",
+ __FUNCTION__, (u64)addr, len);
- if (len <= 0) {
- diag_printf("** Error: invalid length %d\n", len);
+ if ((addr % NF_BLK_SZ) != 0) {
+ diag_printf("Error: flash address 0x%08llx not block aligned\n", addr);
return FLASH_ERR_INVALID;
}
- if ((la % NF_PG_SZ) != 0) {
- diag_printf("** Error: flash address 0x%08x not page aligned\n", la);
+ if ((len % NF_BLK_SZ) != 0 || len == 0) {
+ diag_printf("Error: invalid length %u (must be > 0 and block aligned)\n", len);
return FLASH_ERR_INVALID;
}
-
- do {
- ra = nfc_l_to_p(la);
- la += NF_PG_SZ;
-
- if (nfc_is_badblock(ra)) {
- diag_printf("\n%s(1): ra=0x%08x bad block: %d\n",
- __FUNCTION__, ra, OFFSET_TO_BLOCK(ra));
- return FLASH_ERR_INVALID;
- } else {
- int i;
- if (nfc_read_page(ra) != 0) {
- return FLASH_ERR_INVALID;
+ addr &= MXC_NAND_ADDR_MASK;
+ // now addr has to be block aligned
+ for (sz = 0; sz < len; addr += NF_BLK_SZ, j++, sz += NF_BLK_SZ) {
+ blk = OFFSET_TO_BLOCK(addr);
+ if (skip_bad && nfc_is_badblock(blk, g_bbt)) {
+ if (skip++ >= flash_dev_info->max_bad_blk) {
+ diag_printf("\nToo many bad blocks encountered\n");
+ return FLASH_ERR_PROTOCOL;
}
- i = (len < NF_PG_SZ) ? len: NF_PG_SZ;
-// diag_printf("\nlen=%d, i=%d\n", len, i);
- // now do the copying
- nfc_buf_mem_cpy((void*)dst, (void*)(NAND_MAIN_BUF0), i);
- len -= i;
- dst += i;
+ diag_printf("\nSkipping bad block %u at addr 0x%08llx\n",
+ blk, (u64)addr);
+ continue;
}
- } while (len > 0);
-
- return FLASH_ERR_OK;
-}
-
-#ifdef NFC_2K_BI_SWAP
-static void mxc_swap_2k_BI_main_sp(int check_bad_blk)
-{
- u16 tmp1, tmp2, new_tmp1;
- tmp1 = readw(BAD_BLK_MARKER_464);
- tmp2 = readw(BAD_BLK_MARKER_SP_5);
-
- new_tmp1 = (tmp1 & 0xFF00) | (tmp2 >> 8);
- tmp2 = (tmp1 << 8) | (tmp2 & 0xFF);
- writew(new_tmp1, BAD_BLK_MARKER_464);
- writew(tmp2, BAD_BLK_MARKER_SP_5);
- if (check_bad_blk) {
- is_bad_blk = 0;
- if ((tmp1 & 0xFF) != 0xFF) {
- is_bad_blk = 1;
+ if (nfc_erase_blk(addr) != 0) {
+ diag_printf("\nError: Failed to erase block %u at addr 0x%08llx\n",
+ blk, (u64)addr);
+ mark_blk_bad(blk, g_bbt, BLK_BAD_RUNTIME);
+ // we don't need to update the table immediately here since even
+ // with power loss now, we should see the same erase error again.
+ update++;
+ continue;
+ }
+ if (verbose) {
+ if ((j % 0x20) == 0)
+ diag_printf("\n%s 0x%08llx: ", skip_bad ? "Erase" : "FORCE erase", (u64)addr);
+ diag_printf(".");
+ }
+ }
+ if (update) {
+ if (program_bbt_to_flash() != 0) {
+ diag_printf("\nError: Failed to update bad block table\n");
+ return -1;
}
+ diag_printf("\nnew bad blocks=%d\n", update);
}
+ return FLASH_ERR_OK;
}
-#endif
-static int nfc_program_page_raw(u32 block, u32 page)
+/*!
+ * Program a range of NAND flash in blocks only.
+ * It skips bad blocks and update the BBT once it sees new bad block due to program.
+ * @param addr raw NAND flash address. it has to be block size aligned
+ * @param len number of bytes
+ * @return FLASH_ERR_OK (0) if successful; non-zero otherwise
+ */
+int nfc_program_region(flash_addr_t addr, u8 *buf, u32 len)
{
- u16 flash_status;
- u32 flash_addr = (block * NF_PG_PER_BLK + page) << NAND_PG_SHIFT;
+ u32 sz, blk, update = 0, skip = 0, partial_block_size;
- diag_printf("%s: addr=%08x block=%6d page=%6d\n", __FUNCTION__,
- flash_addr, block, page);
-#if 0
-return 0;
-#endif
- NFC_CMD_INPUT(FLASH_Send_Data);
- start_nfc_addr_ops(ADDRESS_INPUT_PROGRAM_PAGE, flash_addr,
- MXC_NAND_LA_MASK);
+ diag_printf1("%s: addr=0x%08llx, len=0x%08x\n", __FUNCTION__, (u64)addr, len);
- NFC_DATA_INPUT(RAM_BUF_0, NFC_MAIN_ONLY, g_ecc_enable);
- if (g_is_2k_page && PG_2K_DATA_OP_MULTI_CYCLES()) {
- NFC_DATA_INPUT_2k(RAM_BUF_1);
- NFC_DATA_INPUT_2k(RAM_BUF_2);
- NFC_DATA_INPUT_2k(RAM_BUF_3);
+ if ((addr % (NF_PG_SZ / num_of_nand_chips)) != 0) {
+ diag_printf("Error: flash address 0x%08llx not page aligned\n", (u64)addr);
+ return FLASH_ERR_INVALID;
}
- NFC_CMD_INPUT(FLASH_Program);
-
- flash_status = NFC_STATUS_READ();
- // check I/O bit 0 to see if it is 0 for success
- if ((flash_status & 0x1) != 0) {
- diag_printf("** Error: failed to program page %d at 0x%08x status=0x%x\n",
- flash_addr >> NAND_PG_SHIFT, (block * NF_PG_PER_BLK + page) * NF_PG_SZ,
- flash_status);
- return -1;
+ if (len == 0) {
+ diag_printf("Error: invalid length\n");
+ return FLASH_ERR_INVALID;
}
- return 0;
-}
+ partial_block_size = addr % NF_BLK_SZ;
-static int nfc_write_pg_random(u32 flash_addr, u32 mem_addr,
- enum nfc_page_area area, int swap)
-{
- u16 flash_status, i;
-
- nfc_printf(NFC_DEBUG_MAX, "%s: addr=%08x block=%6d page=%6d, col=%4d\n", __FUNCTION__,
- flash_addr, (flash_addr >> NAND_PG_SHIFT) / NF_PG_PER_BLK,
- flash_addr >> NAND_PG_SHIFT, flash_addr % NF_PG_SZ);
- switch (area) {
- case NFC_MAIN_ONLY:
- // Read back the spare area first
- for (i = 0; i < 16; i++) {
- // Make all spare area as 0xFF
- writel(0xFFFFFFFF, NAND_SPAR_BUF0 + i * 4);
- }
-
- nfc_buf_mem_cpy((void *)NAND_MAIN_BUF0, (void *)mem_addr, 512);
- if (g_is_2k_page) {
- nfc_buf_mem_cpy((void *)NAND_MAIN_BUF1, (void *)(mem_addr + 512),
- 512 * 3);
-#ifdef MXC_NAND_BOOT_LOAD_AT_0x400
- // To replace the data at offset 0x400 with the address of the NFC base
- // This is needed for certain platforms
- if ((flash_addr <= 0x400) && ((flash_addr + NF_PG_SZ - 1) > 0x400)) {
-// diag_printf("\nflash_addr = 0x%08x\n", flash_addr);
- diag_printf("\n[INFO] 2K page: copy data at 0x400 to spare area and set it to 0x%08x\n", NFC_BASE);
- writel(readl(NFC_BASE + 0x400), NAND_SPAR_BUF2);
- writel(NFC_BASE, NFC_BASE + 0x400);
- }
-#endif
-#ifdef NFC_2K_BI_SWAP
- if (swap)
- mxc_swap_2k_BI_main_sp(0);
-#endif
- } else {
-#ifdef MXC_NAND_BOOT_LOAD_AT_0x400
- // To replace the data at offset 0x400 with the address of the NFC base
- // This is needed for certain platforms
- if ((flash_addr <= 0x400) && ((flash_addr + NF_PG_SZ - 1) > 0x400)) {
- diag_printf("\nflash_addr = 0x%08x\n", flash_addr);
- diag_printf("\n[INFO] 512 page: copy data at 0x400 to spare area and set it to 0x%08x\n", NFC_BASE);
- writel(readl(NFC_BASE), NAND_SPAR_BUF0);
- writel(NFC_BASE, NFC_BASE);
+ addr &= MXC_NAND_ADDR_MASK;
+ // now addr has to be block aligned
+ while (1) {
+ blk = OFFSET_TO_BLOCK(addr);
+ if (nfc_is_badblock(blk, g_bbt)) {
+ if (skip++ >= flash_dev_info->max_bad_blk) {
+ diag_printf("\nToo many bad blocks encountered\n");
+ return FLASH_ERR_PROTOCOL;
}
-#endif
+ diag_printf("\nSkipping bad block %u at addr 0x%08llx\n", blk, addr);
+ goto incr_address;
}
- break;
- case NFC_SPARE_ONLY:
- // This is used ONLY for testing when manually create "bad" blocks
- nfc_buf_mem_cpy((void *)(NAND_SPAR_BUF0), (void *)mem_addr, 16);
- if (!g_is_2k_page) {
- NFC_CMD_INPUT(FLASH_Read_Mode3);
+
+ sz = (len >= partial_block_size) ? partial_block_size : len;
+
+ if (nfc_program_blk(addr, buf, sz) != 0) {
+ update++;
+ diag_printf("\nError: Failed to program flash block %u at addr 0x%08llx\n",
+ blk, (u64)addr);
+ mark_blk_bad(blk, g_bbt, BLK_BAD_RUNTIME);
+ if (skip + update > flash_dev_info->max_bad_blk) {
+ diag_printf("\nToo many bad blocks encountered\n");
+ return FLASH_ERR_PROTOCOL;
+ }
+ // we don't need to update the table immediately here since even
+ // with power loss now, we should see the same program error again.
+ goto incr_address;
}
- break;
- default:
- diag_printf("NOT supported yet!\n");
- return -1;
- }
+ diag_printf(".");
- NFC_CMD_INPUT(FLASH_Send_Data);
- start_nfc_addr_ops(ADDRESS_INPUT_PROGRAM_PAGE, flash_addr,
- MXC_NAND_LA_MASK);
+ len -= sz;
+ buf += sz;
+ if (len == 0)
+ break;
- NFC_DATA_INPUT(RAM_BUF_0, area, g_ecc_enable);
- if (g_is_2k_page && PG_2K_DATA_OP_MULTI_CYCLES()) {
- NFC_DATA_INPUT_2k(RAM_BUF_1);
- NFC_DATA_INPUT_2k(RAM_BUF_2);
- NFC_DATA_INPUT_2k(RAM_BUF_3);
+incr_address:
+ addr += partial_block_size;
+ partial_block_size = NF_BLK_SZ;
}
- NFC_CMD_INPUT(FLASH_Program);
-
- flash_status = NFC_STATUS_READ();
- // check I/O bit 0 to see if it is 0 for success
- if ((flash_status & 0x1) != 0) {
- diag_printf("Error: failed to write page %d col=%d (address 0x%08x) status=0x%x\n",
- flash_addr >> NAND_PG_SHIFT, flash_addr % NF_PG_SZ,
- (flash_addr >> NAND_PG_SHIFT) * NF_PG_SZ + (flash_addr % NF_PG_SZ),
- flash_status);
- return -1;
+ if (update) {
+ if (program_bbt_to_flash() != 0) {
+ diag_printf("\nError: Failed to update bad block table\n");
+ return -1;
+ }
+ diag_printf("\nnew bad blocks: %d\n", update);
}
+ if (skip)
+ diag_printf("\nbad blocks skipped: %d\n", skip);
- return 0;
+ return FLASH_ERR_OK;
}
/*!
- * This function programs a page's main, spare, or both. For main area program,
- * It copies out the spare area of that page first and then write it along
- * with the main area back to the NAND flash (FIXME: can't just program main alone?
- * For spare area program, it will scratch out the main area data (FIXME).
+ * Read data from raw NAND flash address to memory. The MSB of the passed-
+ * in flash address will be masked off inside the function.
+ * It skips bad blocks and read good blocks of data for "len" bytes.
*
- * @param ra starting address to be programmed inside the NAND flash.
- * Must be page-aligned
- * @param mem_addr source address in the RAM.
- * For main area: mem_addr -> starting of data for main area
- * For spare area: mem_addr -> starting of data for spare area
- * For both area: mem_addr -> starting of data for main area along with spare area
- * @return 0 if no error or 1-bit error; -1 otherwise
+ * @param addr NAND flash address. it has to be page aligned
+ * @param buf memory buf where data will be copied to
+ * @param len number of bytes
+ * @return FLASH_ERR_OK (0) if successful; non-zero otherwise
*/
-// FIXME: Add programming of the spare area only
-static int nfc_program_page(u32 ra, u32 mem_addr, enum nfc_page_area area)
+int nfc_read_region(flash_addr_t addr, u8 *buf, u32 len)
{
- u32 flash_addr;
+ u32 blk, bad = 0, start_point = 0, pg_no;
+ unsigned long offset = addr % NF_PG_SZ;
-// diag_printf("%s(0x%08x, 0x%08x, %d\n", __FUNCTION__, ra, mem_addr, area);
+ diag_printf1("%s: addr=0x%08llx, buf=0x%p, len=0x%08x\n",
+ __FUNCTION__, addr, buf, len);
- if (ra % NF_PG_SZ) {
- diag_printf("** Error: Non page-aligned write not supported: 0x%08x\n", ra);
- return -1;
+ if (addr < (u32)flash_info.start || (addr + len) > (u32)flash_info.end || len == 0) {
+ diag_printf("Error: flash address 0x%08llx..0x%08llx outside valid range %p..%p\n",
+ (u64)addr, (u64)addr + len - 1, flash_info.start, flash_info.end);
+ return FLASH_ERR_INVALID;
}
- flash_addr = (ra / NF_PG_SZ) << NAND_PG_SHIFT;
- return nfc_write_pg_random(flash_addr, mem_addr, area, 1);
-}
+ addr = (addr & MXC_NAND_ADDR_MASK) - offset;
+ blk = OFFSET_TO_BLOCK(addr);
+ while (len > 0) {
+ int i;
-/*!
- * Low level spare-only read. Only applies to 512 byte page NAND.
- *
- * @param addr starting address to be read from the NAND flash
- * @param buf one of the internal buffers
- * @return 0 if no error or 1-bit error; -1 otherwise
- */
-static int nfc_sp_only_read_ll(u32 addr, enum nfc_internal_buf buf)
-{
- volatile u16 temp;
+ if ((addr % NF_BLK_SZ) == 0) {
+ // only need to test block aligned page address
+ blk = OFFSET_TO_BLOCK(addr);
+ if (nfc_is_badblock(blk, g_bbt)) {
+ if (bad++ >= flash_dev_info->max_bad_blk) {
+ diag_printf("\nToo many bad blocks encountered\n");
+ return FLASH_ERR_PROTOCOL;
+ }
+ diag_printf("\nSkipping bad block %u at addr 0x%08llx\n", blk, (u64)addr);
+ addr += NF_BLK_SZ;
+ continue;
+ }
+ }
- NFC_CMD_INPUT(FLASH_Read_Mode3);
- start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, MXC_NAND_LA_MASK);
- NFC_DATA_OUTPUT(buf, FDO_SPARE_ONLY, g_ecc_enable);
- temp = readw(ECC_STATUS_RESULT_REG);
- NFC_CMD_INPUT(FLASH_Read_Mode1);
+ pg_no = addr / NF_PG_SZ;
+ if ((addr % NF_PG_SZ) != 0) {
+ /* Find which interleaved NAND device */
+ start_point = (addr - (pg_no * NF_PG_SZ)) / (NF_PG_SZ / num_of_nand_chips);
+ } else {
+ start_point = 0;
+ }
+ for (i = start_point; i < num_of_nand_chips; i++) {
+ int chunk_size = len > NF_PG_SZ / num_of_nand_chips ?
+ NF_PG_SZ / num_of_nand_chips : len;
- if (g_ecc_enable) {
- if ((temp & 0x2) != 0x0) {
- nfc_printf(NFC_DEBUG_MED, "\nError %d: %s(addr=0x%08x): ECC status result reg=0x%x\n",
- __LINE__, __FUNCTION__, addr, temp);
- return -1;
+ if (nfc_read_page(i, pg_no, 0) != 0) {
+ diag_printf("\nError: Failed to read flash block %u at addr 0x%08llx\n",
+ blk, (u64)addr);
+ return FLASH_ERR_INVALID;
+ }
+ // now do the copying
+ nfc_buf_read(buf, NAND_MAIN_BUF0, chunk_size);
+
+ buf += chunk_size;
+ len -= chunk_size;
+ addr += NF_PG_SZ / num_of_nand_chips - offset;
+ offset = 0;
}
}
- return 0;
+ return FLASH_ERR_OK;
}
-/*!
- * Read spare area from NAND flash to the 1st internal RAM buffer.
- * Not supported for 2kB page NAND.
- *
- * @param addr starting address to be read from the NAND flash
+/*
+ * Support only either program for main area only. Or spare-area only for 512B.
+ * If one wants to write to the spare-area, then before calling this function,
+ * the spare area NFC RAM buffer has to be setup already. This function doesn't touch
+ * the spare area NFC RAM buffer.
*
- * @return 0 if no error or 1-bit error; -1 otherwise
+ * @param pg_no page number offset from 0
+ * @param pg_off byte offset within the page
+ * @param buf data buffer in the RAM to be written to NAND flash
+ * @param ecc_force can force ecc to be off. Otherwise, by default it is on
+ * unless the page offset is non-zero
+ *
+ * @return 0 if successful; non-zero otherwise
*/
-static int nfc_read_page_sp(u32 addr)
+// SP-only opearation is not supported anymore !!!
+static int nfc_write_pg_random(u32 pg_no, u32 pg_off, u8 *buf, u32 ecc_force)
{
- if (g_spare_only_read_ok) {
- if (g_is_2k_page) {
- diag_printf("** Error: spare-only read for 2k page is not supported\n");
+ u16 flash_status;
+ u32 ecc = NFC_FLASH_CONFIG2_ECC_EN, v, i;
+ u32 write_count = NF_PG_SZ, start_point = 0, rba, rba_count = 0;
+
+ // the 2nd condition is to test for unaligned page address -- ecc has to be off.
+ if (ecc_force == ECC_FORCE_OFF || pg_off != 0) {
+ ecc = 0;
+ }
+
+ diag_printf1("%s(0x%x, 0x%x, %d)\n", __FUNCTION__, pg_no, pg_off, ecc_force);
+
+ switch (g_nfc_version & 0xf0) {
+ case MXC_NFC_V3:
+ /* Check if Page size is greater than NFC buffer */
+ do {
+ if (write_count <= NFC_BUFSIZE) {
+ // No need to worry about the spare area
+ nfc_buf_write(NAND_MAIN_BUF0, buf, write_count);
+ write_count = 0;
+ } else {
+ // No need to worry about the spare area
+ nfc_buf_write(NAND_MAIN_BUF0, buf, NFC_BUFSIZE);
+ write_count -= NFC_BUFSIZE;
+ buf += NFC_BUFSIZE;
+ }
+ // combine the two commands for program
+ writel((FLASH_Program << 8) | FLASH_Send_Data, NAND_CMD_REG);
+
+ for (i = start_point; i < num_of_nand_chips; i++) {
+ rba = rba_count * ((NF_PG_SZ / num_of_nand_chips) / 512);
+ /* Completely wrote out the NFC buffer, break and copy more to the NFC buffer */
+ if (rba > 7) {
+ rba_count = 0;
+ break;
+ }
+
+ // For ECC
+ v = readl(NFC_FLASH_CONFIG2_REG) & ~NFC_FLASH_CONFIG2_ECC_EN;
+ // setup config2 register for ECC enable or not
+ write_nfc_ip_reg(v | ecc, NFC_FLASH_CONFIG2_REG);
+
+ start_nfc_addr_ops(FLASH_Program, pg_no, pg_off, 0, i, num_of_nand_chips);
+
+ // start auto-program
+ writel(NAND_LAUNCH_AUTO_PROG, NAND_LAUNCH_REG);
+ if (i < (num_of_nand_chips - i))
+ wait_for_auto_prog_done();
+ else
+ wait_op_done();
+ pg_off = 0;
+ rba_count++;
+ }
+ start_point = i;
+ } while (write_count > 0);
+ flash_status = NFC_STATUS_READ();
+ // check I/O bit 0 to see if it is 0 for success
+ if ((flash_status & ((0x1 << num_of_nand_chips) - 1)) != 0) {
+ return -1;
+ }
+ break;
+ default:
+ if (g_nfc_version != MXC_NFC_V1) {
+ int i;
+
+ for (i = 1; i < NFC_SPARE_BUF_SZ / 16; i++) {
+ memcpy((void *)(NAND_SPAR_BUF0 + i * NFC_SPARE_BUF_SZ),
+ (void *)(NAND_SPAR_BUF0 + i * 16), 16);
+ }
+ }
+ nfc_buf_write(NAND_MAIN_BUF0, buf, NF_PG_SZ);
+#ifdef BARKER_CODE_SWAP_LOC
+ // To replace the data at offset MXC_NAND_BOOT_LOAD_BARKER with
+ // the address of the NFC base. This is needed for certain platforms.
+ if (pg_no == 0) {
+ diag_printf("\n[INFO]: copy data at 0x%x to spare area and set it to 0x%x\n",
+ BARKER_CODE_SWAP_LOC, BARKER_CODE_VAL);
+ writel(readl(NFC_BASE + BARKER_CODE_SWAP_LOC), NAND_SPAR_BUF0);
+ // todo: set BARKER_CODE_VAL and BARKER_CODE_SWAP_LOC for skye, etc.
+ writel(BARKER_CODE_VAL, NFC_BASE + BARKER_CODE_SWAP_LOC);
+ }
+#endif
+ NFC_CMD_INPUT(FLASH_Send_Data);
+ start_nfc_addr_ops(FLASH_Program, pg_no, pg_off, 0, 0, num_of_nand_chips);
+
+ NFC_DATA_INPUT(RAM_BUF_0, NFC_MAIN_ONLY, ecc);
+ if (g_is_4k_page && PG_2K_DATA_OP_MULTI_CYCLES()) {
+ diag_printf("4K page with multi cycle write is not supported\n");
+ return -1;
+ }
+ if (g_is_2k_page && PG_2K_DATA_OP_MULTI_CYCLES()) {
+ NFC_DATA_INPUT_2k(RAM_BUF_1);
+ NFC_DATA_INPUT_2k(RAM_BUF_2);
+ NFC_DATA_INPUT_2k(RAM_BUF_3);
+ }
+ NFC_CMD_INPUT(FLASH_Program);
+
+ flash_status = NFC_STATUS_READ();
+ // check I/O bit 0 to see if it is 0 for success
+ if ((flash_status & 0x1) != 0) {
+ diag_printf("** Error: failed to program page %u at 0x%08x status=0x%02x\n",
+ pg_no, pg_no * NF_PG_SZ + pg_off, flash_status);
return -1;
}
- return nfc_sp_only_read_ll(addr, RAM_BUF_0);
}
- return -1;
+ return 0;
}
-static int nfc_read_pg_random(u32 flash_addr, int swap)
+#ifndef NFC_V3_0
+// for version V1 and V2 of NFC
+static int nfc_read_pg_random(u32 pg_no, u32 pg_off, u32 ecc_force, u32 cs_line,
+ u32 num_of_nand_chips)
{
- volatile u16 t1, t2 = 0, t3 = 0, t4 = 0;
+ u32 t1, ecc = 1;
+ u8 t2 = 0, t3 = 0, t4 = 0, t5 = 0, t6 = 0, t7 = 0, t8 = 0;
int res = 0;
-
-#if 0 //TODO: kevin revisit
- if (!g_is_2k_page && (t1 = (flash_addr & ((1 << (1 + NAND_PG_SHIFT)) - 1))) >= 512) {
- NFC_CMD_INPUT(FLASH_Read_Mode3);
- flash_addr -= 512;
- diag_printf("kevin: 0x%08x\n", flash_addr);
- } else {
- NFC_CMD_INPUT(FLASH_Read_Mode1);
- }
-#endif
- nfc_printf(NFC_DEBUG_MAX, "%s: addr=%08x block=%6d page=%6d, col=%4d\n", __FUNCTION__,
- flash_addr, (flash_addr >> NAND_PG_SHIFT) / NF_PG_PER_BLK,
- flash_addr >> NAND_PG_SHIFT, flash_addr % NF_PG_SZ);
+
+ if (ecc_force == ECC_FORCE_OFF || pg_off != 0 )
+ ecc = 0;
NFC_CMD_INPUT(FLASH_Read_Mode1);
+ start_nfc_addr_ops(FLASH_Read_Mode1, pg_no, pg_off, 0, 0, num_of_nand_chips);
- start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, flash_addr, MXC_NAND_LA_MASK);
- if (g_is_2k_page) {
- NFC_CMD_INPUT(FLASH_Read_Mode1_2K);
+ if (g_is_2k_page || g_is_4k_page) {
+ NFC_CMD_INPUT(FLASH_Read_Mode1_LG);
}
-
- if (g_nfc_version == MXC_NFC_V1) {
- NFC_DATA_OUTPUT(RAM_BUF_0, FDO_PAGE_SPARE, g_ecc_enable);
- t1 = readw(ECC_STATUS_RESULT_REG);
- if (g_is_2k_page) {
- NFC_DATA_OUTPUT(RAM_BUF_1, FDO_PAGE_SPARE, g_ecc_enable);
+ NFC_DATA_OUTPUT(RAM_BUF_0, FDO_PAGE_SPARE, ecc);
+ switch (g_nfc_version & 0xf0) {
+ case MXC_NFC_V1:
+ t1 = readw(ECC_STATUS_RESULT_REG);
+ if (g_is_2k_page && PG_2K_DATA_OP_MULTI_CYCLES()) {
+ NFC_DATA_OUTPUT(RAM_BUF_1, FDO_PAGE_SPARE, ecc);
t2 = readw(ECC_STATUS_RESULT_REG);
- NFC_DATA_OUTPUT(RAM_BUF_2, FDO_PAGE_SPARE, g_ecc_enable);
+ NFC_DATA_OUTPUT(RAM_BUF_2, FDO_PAGE_SPARE, ecc);
t3 = readw(ECC_STATUS_RESULT_REG);
- NFC_DATA_OUTPUT(RAM_BUF_3, FDO_PAGE_SPARE, g_ecc_enable);
+ NFC_DATA_OUTPUT(RAM_BUF_3, FDO_PAGE_SPARE, ecc);
t4 = readw(ECC_STATUS_RESULT_REG);
}
-
- if (g_ecc_enable && ((t1 & 0xA) != 0x0 || (t2 & 0xA) != 0x0 || (t3 & 0xA) != 0x0
- || (t4 & 0xA) != 0x0)) {
- diag_printf("** Error: uncorrectable ECC error in flash at addr 0x%08x page %d, col %d: ECC status=0x%x:0x%x:0x%x:0x%x\n",
- (flash_addr >> NAND_PG_SHIFT) * NF_PG_SZ + (flash_addr % NF_PG_SZ),
- flash_addr >> NAND_PG_SHIFT,
- flash_addr % NF_PG_SZ, t1, t2, t3, t4);
+
+ if (ecc && ((t1 & 0xA) != 0x0 || (t2 & 0xA) != 0x0 ||
+ (t3 & 0xA) != 0x0 || (t4 & 0xA) != 0x0)) {
+ diag_printf("\n** Error: %s(page=%d, col=%d): ECC status=0x%x:0x%x:0x%x:0x%x\n",
+ __FUNCTION__, pg_no, pg_off, t1, t2, t3, t4);
res = -1;
goto out;
}
- } else if (g_nfc_version == MXC_NFC_V2) {
- NFC_DATA_OUTPUT(RAM_BUF_0, FDO_PAGE_SPARE, g_ecc_enable);
- if (g_is_2k_page) {
- if (PG_2K_DATA_OP_MULTI_CYCLES()) {
- NFC_DATA_OUTPUT(RAM_BUF_1, FDO_PAGE_SPARE, g_ecc_enable);
- NFC_DATA_OUTPUT(RAM_BUF_2, FDO_PAGE_SPARE, g_ecc_enable);
- NFC_DATA_OUTPUT(RAM_BUF_3, FDO_PAGE_SPARE, g_ecc_enable);
- }
- // To replace the data at offset 0x400 with the address of the NFC base
- // This is needed for certain platforms
- if ((flash_addr <= 0x400) && ((flash_addr + NF_PG_SZ - 1) > 0x400)) {
-// diag_printf("\nRead: flash_addr = 0x%08x\n", flash_addr);
- diag_printf("\n[INFO] 2K page: copy back data from spare to 0x400\n");
- writel(readl(NAND_SPAR_BUF2), NFC_BASE + 0x400);
- }
- } else {
- // To replace the data at offset 0x400 with the address of the NFC base
- // This is needed for certain platforms
- if ((flash_addr <= 0x400) && ((flash_addr + NF_PG_SZ - 1) > 0x400)) {
- diag_printf("\nflash_addr = 0x%08x\n", flash_addr);
- diag_printf("\n[INFO] 512 page: copy back data from spare to 0x400\n");
- writel(readl(NAND_SPAR_BUF0), NFC_BASE);
- }
+ break;
+ case MXC_NFC_V2:
+ if (g_is_2k_page && PG_2K_DATA_OP_MULTI_CYCLES()) {
+ NFC_DATA_OUTPUT(RAM_BUF_1, FDO_PAGE_SPARE, ecc);
+ NFC_DATA_OUTPUT(RAM_BUF_2, FDO_PAGE_SPARE, ecc);
+ NFC_DATA_OUTPUT(RAM_BUF_3, FDO_PAGE_SPARE, ecc);
}
- if (g_ecc_enable) {
- t1 = readw(ECC_STATUS_RESULT_REG);
- if (!g_is_2k_page) {
- if ((t1 & 0xF) > 4) {
- diag_printf("** Error: uncorrectable ECC error at address 0x%08x page %d, col %d ECC status=0x%x\n",
- (flash_addr >> NAND_PG_SHIFT) * NF_PG_SZ + (flash_addr % NF_PG_SZ),
- flash_addr >> NAND_PG_SHIFT,
- flash_addr % NF_PG_SZ, t1 & 0xF);
- res = -1;
- goto out;
- }
- } else {
+ if (ecc) {
+ t1 = readl(ECC_STATUS_RESULT_REG);
+ if (g_is_2k_page || g_is_4k_page) {
t2 = (t1 >> 4) & 0xF;
t3 = (t1 >> 8) & 0xF;
t4 = (t1 >> 12) & 0xF;
- if (t2 > 4 || t3 > 4 || t4 > 4) {
- diag_printf("** Error: uncorrectable ECC error at address 0x%08x page %d, col=%d ECC status=0x%x:0x%x:0x%x\n",
- (flash_addr >> NAND_PG_SHIFT) * NF_PG_SZ + (flash_addr % NF_PG_SZ),
- flash_addr >> NAND_PG_SHIFT,
- flash_addr % NF_PG_SZ, t2, t3, t4);
- res = -1;
- goto out;
+ if (g_is_4k_page) {
+ t5 = (t1 >> 16) & 0xF;
+ t6 = (t1 >> 20) & 0xF;
+ t7 = (t1 >> 24) & 0xF;
+ t8 = (t1 >> 28) & 0xF;
}
}
+ if ((t1 = (t1 & 0xF)) > 4 || t2 > 4 || t3 > 4 || t4 > 4 ||
+ t5 > 4 || t6 > 4 || t7 > 4 || t8 > 4) {
+ diag_printf("\n** Error: ECC error reading block %u page %u\n",
+ pg_no / NF_PG_PER_BLK, pg_no % NF_PG_PER_BLK);
+ diag_printf(" ECC status=%x:%x:%x:%x:%x:%x:%x:%x\n",
+ t1, t2, t3, t4, t5, t6, t7, t8);
+ res = -1;
+ goto out;
+ }
}
+ break;
+ default:
+ diag_printf("Unknown NFC version: %d\n", g_nfc_version);
+ return -1;
}
-out:
- if (g_is_2k_page) {
-#ifdef NFC_2K_BI_SWAP
- if (swap)
- mxc_swap_2k_BI_main_sp(1);
-#endif
+ if (g_nfc_version != MXC_NFC_V1) {
+ int i;
+
+ for (i = 1; i < NFC_SPARE_BUF_SZ / 16; i++) {
+ memcpy((void *)(NAND_SPAR_BUF0 + i * 16),
+ (void *)(NAND_SPAR_BUF0 + i * NFC_SPARE_BUF_SZ), 16);
+ }
+ }
+#ifdef BARKER_CODE_SWAP_LOC
+ // To replace the data at offset BARKER_CODE_SWAP_LOC with the address of the NFC base
+ // This is needed for certain platforms
+ if (pg_no == 0) {
+ diag_printf("\n[INFO]: copy back data from spare to 0x%x\n", BARKER_CODE_SWAP_LOC);
+ writel(readl(NAND_SPAR_BUF0), NFC_BASE + BARKER_CODE_SWAP_LOC);
}
+#endif
+
+out:
return res;
}
+#endif // ifndef NFC_V3_0
/*!
* Read a page's both main and spare area from NAND flash to the internal RAM buffer.
* It always reads data to the internal buffer 0.
*
- * @param ra starting address to be read from the NAND flash; must be page-aligned
+ * @param cs_line which NAND device is used
+ * @param pg_no page number of the device
+ * @param pg_off offset within a page
*
* @return 0 if no error or 1-bit error; -1 otherwise
*/
-static int nfc_read_page(u32 ra)
+static int nfc_read_page(u32 cs_line, u32 pg_no, u32 pg_off)
{
- u32 flash_addr;
-
- if (ra % NF_PG_SZ) {
- diag_printf("Non page-aligned read not supported here: 0x%08x\n", ra);
- return -1;
- }
-
- flash_addr = (ra / NF_PG_SZ) << NAND_PG_SHIFT;
-
- return nfc_read_pg_random(flash_addr, 1);
+ return nfc_read_pg_random(pg_no, pg_off, ECC_FORCE_ON, cs_line, num_of_nand_chips);
}
-// Read data into buffer
-int flash_read_buf(void* addr, void* data, int len)
+static int nfc_write_page(u32 pg_no, u32 pg_off, u32 ecc_force)
{
- if (IS_BOOTING_FROM_NOR() || IS_FIS_FROM_NOR()) {
- memcpy(data, addr, len);
- return 0;
- } else {
- return nfc_read_region((u32)addr, (u32)data, len);
+ u16 flash_status;
+ u32 ecc = NFC_FLASH_CONFIG2_ECC_EN;
+
+ diag_printf1("Writing page %u addr 0x%08llx\n",
+ pg_no, (u64)pg_no * NF_PG_SZ + pg_off);
+ if (ecc_force == ECC_FORCE_OFF || pg_off != 0) {
+ ecc = 0;
}
-}
-void mxc_nfc_print_info(void)
-{
- diag_printf("[0x%08x bytes]: %d blocks of %d pages of %d bytes each.\n",
- NF_DEV_SZ, NF_BLK_CNT,
- NF_PG_PER_BLK, NF_PG_SZ);
-}
+ if (g_nfc_version == MXC_NFC_V3) {
+ int i;
+ u32 v;
+ u32 start_point = 0, rba, rba_count = 0;
-#ifdef MXCFLASH_FLASH_BASED_BBT
-/*
- * The NFC buffers cannot be accessed in byte mode.
- * This routine extracts one byte at a given location in the NFC buffer.
- */
+ // combine the two commands for program
+ writel((FLASH_Program << 8) | FLASH_Send_Data, NAND_CMD_REG);
-/**
- * check_short_pattern - [GENERIC] check if a pattern is in the buffer
- * @buf: the buffer to search
- * @td: search pattern descriptor
- *
- * Check for a pattern at the given place. Used to search bad block
- * tables and good / bad block identifiers.
- *
-*/
-static int check_short_pattern(void *buf, struct nand_bbt_descr *td)
-{
- int i;
+ for (i = start_point; i < num_of_nand_chips; i++) {
+ rba = rba_count * ((NF_PG_SZ / num_of_nand_chips) / 512);
+ /* Completely wrote out the NFC buffer, break and copy more to the NFC buffer */
+ if (rba > 7) {
+ rba_count = 0;
+ break;
+ }
- for (i = 0; i < td->len; i++) {
- if (get_byte(buf, td->offs + i) != td->pattern[i]) {
- return -1;
+ // For ECC
+ v = readl(NFC_FLASH_CONFIG2_REG) & ~NFC_FLASH_CONFIG2_ECC_EN;
+ // setup config2 register for ECC enable or not
+ write_nfc_ip_reg(v | ecc, NFC_FLASH_CONFIG2_REG);
+
+ start_nfc_addr_ops(FLASH_Program, pg_no, pg_off, 0, i, num_of_nand_chips);
+
+ // start auto-program
+ writel(NAND_LAUNCH_AUTO_PROG, NAND_LAUNCH_REG);
+ if (i < (num_of_nand_chips - i))
+ wait_for_auto_prog_done();
+ else
+ wait_op_done();
+ pg_off = 0;
+ rba_count++;
}
- }
- return 0;
-}
-
-/**
- * search_bbt - [GENERIC] scan the device for a specific bad block table
- * @mtd: MTD device structure
- * @buf: temporary buffer
- * @td: descriptor for the bad block table
- *
- * Read the bad block table by searching for a given ident pattern.
- * Search is preformed either from the beginning up or from the end of
- * the device downwards. The search starts always at the start of a
- * block.
- * If the option NAND_BBT_PERCHIP is given, each chip is searched
- * for a bbt, which contains the bad block information of this chip.
- * This is necessary to provide support for certain DOC devices.
- *
- * The bbt ident pattern resides in the oob area of the first page
- * in a block.
- */
-static int search_bbt(struct nand_bbt_descr *td)
-{
- int bits, startblock, block, dir;
- int bbtblocks;
- void *oob = (void *)NAND_SPAR_BUF0;
-
- /* Search direction top -> down ? */
- if (td->options & NAND_BBT_LASTBLOCK) {
- startblock = (NF_DEV_SZ / NF_BLK_SZ) - 1;
- dir = -1;
+ start_point = i;
+ flash_status = NFC_STATUS_READ();
} else {
- startblock = 0;
- dir = 1;
- }
-
- bbtblocks = NF_DEV_SZ / NF_BLK_SZ;
+ if (g_nfc_version != MXC_NFC_V1) {
+ int i;
- /* Number of bits for each erase block in the bbt */
- bits = td->options & NAND_BBT_NRBITS_MSK;
+ for (i = NFC_SPARE_BUF_SZ / 16 - 1; i >= 0; i--) {
+ memcpy((void *)(NAND_SPAR_BUF0 + i * NFC_SPARE_BUF_SZ),
+ (void *)(NAND_SPAR_BUF0 + i * 16), 16);
+ }
+ }
+ NFC_CMD_INPUT(FLASH_Send_Data);
+ start_nfc_addr_ops(FLASH_Program, pg_no, pg_off, 0, 0, num_of_nand_chips);
- /* Reset version information */
- td->version = 0;
- td->pages = -1;
- /* Scan the maximum number of blocks */
- for (block = 0; block < td->maxblocks; block++) {
- int actblock = startblock + dir * block;
- int ret;
-
- nfc_printf(NFC_DEBUG_MAX, "%s: Reading block %d (page %d) addr %08x\n", __FUNCTION__,
- actblock, actblock * NF_PG_PER_BLK, actblock * NF_BLK_SZ);
-
- ret = nfc_read_page(actblock * NF_BLK_SZ);
- if (ret != 0) {
- nfc_printf(NFC_DEBUG_MED, "Failed to read bbt page %d\n",
- actblock * NF_PG_PER_BLK);
- continue;
+ NFC_DATA_INPUT(RAM_BUF_0, NFC_MAIN_ONLY, ecc);
+ if (g_is_4k_page && PG_2K_DATA_OP_MULTI_CYCLES()) {
+ diag_printf("4K page with multi cycle write is not supported\n");
+ return -1;
}
- if (check_short_pattern(oob, td) == 0) {
- nfc_printf(NFC_DEBUG_MED, "Found bbt pattern in block %d\n", actblock);
- td->pages = actblock * NF_PG_PER_BLK;
- if (td->options & NAND_BBT_VERSION) {
- td->version = get_byte(oob, td->veroffs);
- }
- break;
+ if (g_is_2k_page && PG_2K_DATA_OP_MULTI_CYCLES()) {
+ NFC_DATA_INPUT_2k(RAM_BUF_1);
+ NFC_DATA_INPUT_2k(RAM_BUF_2);
+ NFC_DATA_INPUT_2k(RAM_BUF_3);
}
- nfc_printf(NFC_DEBUG_MED, "No bbt pattern in block %d\n", actblock);
- }
- startblock += flash_dev_info->chipsize / NF_BLK_SZ;
+ NFC_CMD_INPUT(FLASH_Program);
- /* Check, if we found a bbt */
- if (td->pages == -1) {
- nfc_printf(NFC_DEBUG_MED, "Bad block table not found\n");
+ flash_status = NFC_STATUS_READ();
+ }
+ if ((flash_status & 0x1) != 0) {
+ diag_printf("** Error: failed to program page %u at addr 0x%08llx\n",
+ pg_no, (u64)pg_no * NF_PG_SZ + pg_off);
return -1;
- } else {
- nfc_printf(NFC_DEBUG_MED, "Bad block table found at page %d, version 0x%02X\n",
- td->pages, td->version);
}
return 0;
}
-/**
- * nand_isbad_bbt - [NAND Interface] Check if a block is bad
- * @mtd: MTD device structure
- * @offs: offset in the device
- * @allowbbt: allow access to bad block table region
- *
-*/
-int nand_isbad_bbt(u16 *bbt, int block, int allowbbt)
-{
- cyg_uint8 res;
-
- block <<= 1;
- res = (get_byte(bbt, block >> 3) >> (block & 0x06)) & 0x03;
-
- switch (res ^ 0x03) {
- case 0x00:
- return 0;
- case 0x01:
- return 1;
- case 0x02:
- return allowbbt ? 0 : 1;
- }
- return 1;
-}
-
-static int mxc_nfc_find_bbt(struct nand_bbt_descr *td, struct nand_bbt_descr *md)
+// Read data into buffer
+#ifndef MXCFLASH_SELECT_MULTI
+int flash_read_buf(void *addr, void *data, int len)
+#else
+int nandflash_read_buf(void *addr, void *data, int len)
+#endif
{
- int ret;
- int bad = 0;
- int block;
- int good;
- struct nand_bbt_descr *bd = NULL;
-
- search_bbt(td);
- bad += td->pages >= 0; /* account for reserved bbt block */
- if (md != NULL) {
- search_bbt(md);
- bad += md->pages >= 0;
- }
- if (td->pages < 0 && (md != NULL && md->pages < 0)) {
- diag_printf("No FLASH based bad block table found\n");
- return -1;
- }
- if (md == NULL || md->version <= td->version) {
- ret = nfc_read_page(td->pages * NF_PG_SZ);
- if (ret == 0) {
- bd = td;
- nfc_printf(NFC_DEBUG_MIN, "Using normal bbt at page %d\n", bd->pages);
- }
- }
- if (bd == NULL && md != NULL) {
- ret = nfc_read_page(md->pages * NF_PG_SZ);
- if (ret == 0) {
- bd = md;
- nfc_printf(NFC_DEBUG_MIN, "Using mirror bbt at page %d\n", bd->pages);
- }
- }
- if (bd == NULL) {
- ret = nfc_read_page(td->pages * NF_PG_SZ);
- if (ret == 0) {
- bd = td;
- nfc_printf(NFC_DEBUG_MIN, "Using normal bbt at page %d\n", bd->pages);
- nfc_update_blk_table(td->pages * NF_PG_SZ, 2);
- bad++;
- } else {
- diag_printf("** Error: Failed to read bbt from flash\n");
- return -1;
- }
- }
- for (block = 0, good = 0; block < NF_BLK_CNT; block++) {
- if (nand_isbad_bbt((u16 *)NAND_MAIN_BUF0, block, true)) {
- nfc_update_blk_table(block * NF_BLK_SZ, true);
- nfc_printf(NFC_DEBUG_MIN, "Block %d is marked bad in flash bbt\n", block);
- bad++;
- } else {
- l_to_p_table[good] = block;
- good++;
- }
- }
- g_nfc_scan_done = true;
- nfc_printf(NFC_DEBUG_MIN, "%s: Found %d bad/reserved blocks\n", __FUNCTION__, bad);
- return bad;
+ flash_addr_t flash_addr = (unsigned long)addr;
+ return nfc_read_region(flash_addr, data, len);
}
-static inline void mxc_nfc_buf_clear(unsigned long buf, u8 pattern, int size)
+void mxc_nfc_print_info(void)
{
- int i;
- u16 *p = (u16 *)buf;
- u16 fill = pattern;
-
- fill = (fill << 8) | pattern;
- for (i = 0; i < size >> 1; i++) {
- p[i] = fill;
- }
+ diag_printf("[0x%08x bytes]: %u blocks of %u pages of %u bytes each.\n",
+ NF_DEV_SZ, NF_BLK_CNT,
+ NF_PG_PER_BLK, NF_PG_SZ);
}
-static int mxc_nfc_write_bbt(int block, int page)
+static inline void mxc_clr_block_offset(void *start, void *end)
{
- int ret;
-
- DBG(1, "%s: Writing bbt block %d page %d\n", __FUNCTION__,
- block, page);
- ret = nfc_program_page_raw(block, page);
- if (ret != 0) {
- DBG(0, "%s: Failed to write bbt block %d page %d\n", __FUNCTION__, block, page);
- return ret;
- }
- nfc_update_blk_table(block * NF_BLK_SZ, 2);
- return 0;
+ nfc_printf(NFC_DEBUG_MIN, "Clearing block offset %lu for %p..%p\n",
+ g_block_offset, start, end);
+ g_block_offset = 0;
}
-static int mxc_nfc_create_bbt(struct nand_bbt_descr *td, struct nand_bbt_descr *md)
-{
- int ret = 0;
- int block;
- int pg_offs = 0;
- int page = 0;
- u16 *buf = (u16 *)NAND_MAIN_BUF0;
- u16 *oob = (u16 *)NAND_SPAR_BUF0;
+static void *flash_region_start;
+static void *flash_region_end;
+static int flash_enable;
- if (td->pages >= 0) {
- return 1;
- }
- if (md->pages < 0) {
- td->version = 1;
+void mxc_flash_enable(void *start, void *end)
+{
+ if (flash_enable++ == 0) {
+ flash_region_start = start;
+ flash_region_end = end;
+ mxc_clr_block_offset(start, end);
} else {
- td->version = md->version;
+ if (start < flash_region_start || end > flash_region_end) {
+ diag_printf("** WARNING: Enable %p..%p outside enabled flash region %p..%p\n",
+ start, end, flash_region_start, flash_region_end);
+ }
}
- for (block = NF_BLK_CNT - 1; block >= NF_BLK_CNT - td->maxblocks - 1; block--) {
- int pg = block * NF_PG_PER_BLK;
+}
- if ((bad_block_code(block) & ~2) == 0) {
- if (md != NULL && md->pages == pg) {
- continue;
+void mxc_flash_disable(void *start, void *end)
+{
+ if (flash_enable) {
+ if (--flash_enable == 0) {
+ if (start != flash_region_start || end != flash_region_end) {
+ diag_printf("** Error: Disable %p..%p not equal to enabled flash region %p..%p\n",
+ start, end, flash_region_start, flash_region_end);
}
- td->pages = pg;
- break;
}
+ } else {
+ diag_printf("** Error: unbalanced call to flash_disable()\n");
}
- if (td->pages < 0) {
- return -1;
- }
- mxc_nfc_buf_clear(NAND_SPAR_BUF0, 0xff, NF_SPARE_SZ);
- mxc_nfc_buf_clear(NAND_MAIN_BUF0, 0xff, NF_PG_SZ);
+}
+
+static int mxc_nfc_isbad_bbt(u16 *bbt, int block)
+{
+ cyg_uint8 res;
- DBG(0, "%s: Creating bbt %c%c%c%c version %d\n", __FUNCTION__,
- td->pattern[0], td->pattern[1], td->pattern[2], td->pattern[3], td->version);
- nfc_buf_mem_cpy(oob + (td->offs >> 1), td->pattern, td->len);
- store_byte(oob, td->veroffs, td->version);
+ block <<= 1;
+ res = (get_byte(bbt, block >> 3) >> (block & 0x06)) & 0x03;
+ res ^= 0x03;
+ return res;
+}
- for (block = 0, pg_offs = 0; block < NF_BLK_CNT;) {
- u16 tmp = 0xffff;
- int i;
+static int mxc_nfc_search_bbt(struct nand_bbt_descr *td)
+{
+ int i;
- if (pg_offs << 1 >= NF_PG_SZ) {
- ret = mxc_nfc_write_bbt(td->pages / NF_PG_PER_BLK, page);
- if (ret != 0) {
- return ret;
- }
- page++;
- mxc_nfc_buf_clear(NAND_SPAR_BUF0, 0xff, NF_SPARE_SZ);
- mxc_nfc_buf_clear(NAND_MAIN_BUF0, 0xff, NF_PG_SZ);
- pg_offs = 0;
+ td->pages = -1;
+ for (i = 0; i < NF_BBT_MAX_NR; i++) {
+ u32 blk = NF_BLK_CNT - i - 1;
+ flash_addr_t addr = blk * NF_BLK_SZ;
+
+ if (nfc_read_pg_random(addr / NF_PG_SZ, addr % NF_PG_SZ,
+ ECC_FORCE_ON, 0, num_of_nand_chips) != 0) {
+ diag_printf("Failed to read bbt page %u at 0x%08llx\n",
+ (u32)(addr / NF_PG_SZ), addr);
+ continue;
}
- for (i = 0; i < 16 && block < NF_BLK_CNT; i += 2, block++) {
- u8 code = bad_block_code(block);
- if ((code & ~2) != 0) {
- tmp &= ~(code << i);
- DBG(2, "%s: bad block %d pattern[%p] %04x mask %04x\n", __FUNCTION__,
- block, &buf[pg_offs], tmp, 0x03 << i);
- }
+ if (check_short_pattern((void *)NAND_SPAR_BUF0, td) == 0) {
+ diag_printf1("found BBT at block %u addr %08llx\n", blk, (u64)addr);
+ td->pages = blk * NF_PG_PER_BLK;
+ td->version = get_byte((void *)NAND_SPAR_BUF0, td->veroffs);
+ mark_blk_bad(blk, g_bbt, BLK_RESERVED);
+ diag_printf1("Found version %d BBT at block %d (0x%08llx)\n",
+ td->version, td->pages / NF_PG_PER_BLK,
+ (u64)td->pages * NF_PG_SZ);
+ return 0;
}
- buf[pg_offs] = tmp;
- pg_offs++;
- }
- if (pg_offs > 0) {
- DBG(0, "%s: Writing final bbt block %d page %d\n", __FUNCTION__,
- td->pages / NF_PG_PER_BLK, page);
- ret = mxc_nfc_write_bbt(td->pages / NF_PG_PER_BLK, page);
}
- return ret;
+ return 1;
}
-#endif
-static int mxc_nfc_scan(bool verbose)
+/*
+ * Look for the BBT depending on the passed-in lowlevel value.
+ * @param lowlevel If true, then it does a low level scan based on factory
+ * marked BI(block info) field with ECC off to decide if a
+ * block is bad.
+ * If false, then it checks to see if an existing BBT in the
+ * flash or not. If not, then it returns -1. If yes, it will
+ * prints out the number of bad blocks.
+ *
+ * @return number of bad blocks for the whole nand flash
+ *
+ * Note: For a brand new flash, this function has to be called with
+ * lowlevel=true.
+ *
+ *
+ */
+static int mxc_nfc_scan(bool lowlevel)
{
- int addr, bad = -1;
- int i, j;
- u32 count1 = hal_timer_count(), count2;
+ u32 bad = 0, i;
+ u32 count1 = 0, count2 = 0;
+ u8 *buf = NULL;
+ struct nand_bbt_descr *td = g_mxc_nfc_bbt_main_descr;
+ struct nand_bbt_descr *md = g_mxc_nfc_bbt_mirror_descr;
- g_nfc_scan_done = false;
+ nfc_printf(NFC_DEBUG_MAX, "%s()\n", __FUNCTION__);
+ mxc_nfc_scan_done = 0;
-#ifdef MXCFLASH_FLASH_BASED_BBT
- bad = mxc_nfc_find_bbt(g_mxc_nfc_bbt_main_descr, g_mxc_nfc_bbt_mirror_descr);
-#endif
- if (bad < 0) {
- for (i = 0, j = 0, addr = 0; addr < NF_DEV_SZ; addr += NF_BLK_SZ, i++) {
- if (nfc_is_badblock(addr)) {
+ if (g_nfc_debug_measure) {
+ count1 = hal_timer_count();
+ }
+ // read out the last 4 blocks for marker
+ // need to keep where is the td and md block number
+ if (!lowlevel) {
+ struct nand_bbt_descr *bd;
+
+ diag_printf1("Searching for BBT in the flash ...\n");
+ if (mxc_nfc_search_bbt(td) != 0) {
+ diag_printf("No main BBT found in flash\n");
+ }
+ if (md && mxc_nfc_search_bbt(md) != 0) {
+ diag_printf("No mirror BBT found in flash\n");
+ }
+ if (td->pages == -1 && (!md || md->pages == -1)) {
+ diag_printf("No BBT found. Need to do \"nand scan\" first\n");
+ return -1;
+ }
+ if (td->pages >= 0 && (md == NULL || md->version <= td->version)) {
+ bd = td;
+ nfc_printf(NFC_DEBUG_MIN, "Using normal bbt at page %d\n", bd->pages);
+ } else if (md != NULL && md->pages >= 0) {
+ bd = md;
+ nfc_printf(NFC_DEBUG_MIN, "Using mirror bbt at page %d\n", bd->pages);
+ } else {
+ diag_printf("** Error: Failed to read bbt from flash\n");
+ return -1;
+ }
+ nfc_read_page(0, bd->pages, 0);
+ for (i = 0; i < NF_BLK_CNT; i++) {
+ int res = mxc_nfc_isbad_bbt((u16 *)NAND_MAIN_BUF0, i);
+ if (res) {
+ // construct the bad block table
+ mark_blk_bad(i, g_bbt, res);
bad++;
- nfc_update_blk_table(addr, true);
- if (verbose)
- nfc_printf(NFC_DEBUG_DEF, " block %d at 0x%08x\n",
- OFFSET_TO_BLOCK(addr), addr);
- } else {
- nfc_update_blk_table(addr, false);
- l_to_p_table[j] = i;
- j++;
}
}
- }
-#ifdef MXCFLASH_FLASH_BASED_BBT
- if (mxc_nfc_create_bbt(g_mxc_nfc_bbt_main_descr, g_mxc_nfc_bbt_mirror_descr) == 0) {
- bad++; /* account for reserved block for main bbt */
- }
- if (g_mxc_nfc_bbt_mirror_descr != NULL) {
- if (mxc_nfc_create_bbt(g_mxc_nfc_bbt_mirror_descr, g_mxc_nfc_bbt_main_descr) == 0) {
- bad++; /* account for reserved block for mirror bbt */
+ buf = g_bbt;
+ } else {
+ diag_printf("Doing low level scan to construct BBT\n");
+ for (i = 0; i < NF_BLK_CNT; i++) {
+ int res = nfc_is_badblock(i, buf);
+ if (res) {
+ // construct the bad block table
+ if (!buf)
+ mark_blk_bad(i, g_bbt, res);
+ bad++;
+ }
}
}
-#endif
+ diag_printf1("Total bad blocks: %d\n", bad);
if (g_nfc_debug_measure) {
count2 = hal_timer_count();
- diag_printf("counter1=%d, counter2=%d, diff=%d\n",
- count1, count2, count2 - count1);
- diag_printf("Using [diff * 1000000 / 32768] to get usec\n");
+ diag_printf("counter1=0x%x, counter2=0x%x, diff=0x%x (%u usec)\n",
+ count1, count2, count2 - count1,
+ (count2 - count1) * 1000000 / 32768);
}
- g_nfc_scan_done = true;
+ mxc_nfc_scan_done = 1;
return bad;
}
////////////////////////// "nand" commands support /////////////////////////
// Image management functions
local_cmd_entry("info",
- "Show nand flash info (number of good/bad blocks)",
- "[-f <raw address>] [-l <length>]",
- nand_info,
- NAND_cmds
+ "Show nand flash info (number of good/bad blocks)",
+ "",
+ nand_info,
+ NAND_cmds
);
local_cmd_entry("show",
- "Show a page main/spare areas or spare area only (-s)",
- "-f <raw page address> [-s]",
- nand_show,
- NAND_cmds
+ "Show a page main/spare areas or spare area only (-s)",
+ "-f <raw page address> [-s]",
+ nand_show,
+ NAND_cmds
);
local_cmd_entry("read",
- "Read data from nand flash into RAM",
- "-f <raw address> -b <memory_load_address> -l <image_length> [-c <col_addr>]",
- nand_read,
- NAND_cmds
+ "Read data from nand flash into RAM",
+ "-f <raw addr> -b <mem_load_addr> -l <byte len> [-c <col>]\n"
+ " Note -c is only for 2K-page for value <0, 2048+64-1>",
+ nand_read,
+ NAND_cmds
);
local_cmd_entry("write",
- "Write data from RAM into nand flash",
- "-f <raw address> -b <memory_address> -l <image_length> [-c <col_addr>]",
- nand_write,
- NAND_cmds
+ "Write data from RAM into nand flash",
+ "-f <raw address> -b <memory_address> -l <image_length> [-c <col_addr>]",
+ nand_write,
+ NAND_cmds
);
local_cmd_entry("erase",
- "Erase nand flash contents",
- "-f <raw address> -l <length> [-o] [-z] \n\
- -o: force erase (even for bad blocks) \n\
- -z: mark bad (testing only!)",
- nand_erase,
- NAND_cmds
+ "Erase nand flash contents",
+ "-f <raw address> -l <length> [-o]\n"
+ " -o: force erase (even for bad blocks)",
+ nand_erase,
+ NAND_cmds
);
-#if 0
-local_cmd_entry("format",
- "Check ALL blocks with ECC disabled and Erase the entire NAND flash with ECC ",
- "-f <raw address> -l <length> [-o] [-z] \n\
- -o: force erase (even for bad blocks) \n\
- -z: mark bad (testing only!)",
- nand_format,
- NAND_cmds
+local_cmd_entry("scan",
+ "Scan bad blocks and may also save bad block table into the NAND flash.",
+ "[-o] [-r]\n"
+ "No argument: save existing bad block table (BBT)\n"
+ " -r: re-scan with ECC off and save BBT -- for brand NEW flash\n"
+ " -o: force erase all, reconstruct BBT (no ECC) and save BBT -- for development.",
+ nand_scan,
+ NAND_cmds
);
-#endif
+
local_cmd_entry("debug",
- "Various NAND debug features ",
- "<0> min debug messages <default> \n\
- <1> med debug messages \n\
- <2> max debug messages \n\
- <3> enable(default)/disable h/w ECC for both r/w \n\
- <4> disable(default)/enable spare-only read \n\
- <9> enable/disable measurement \n\
- no parameter - display current debug setup",
- nand_debug_fun,
- NAND_cmds
- );
+ "Various NAND debug features ",
+ "<0> no debug messages <default>\n"
+ " <1> min debug messages\n"
+ " <2> med debug messages\n"
+ " <3> max debug messages\n"
+ " <4> enable(default)/disable h/w ECC for both r/w\n"
+ " <5> disable(default)/enalbe spare-only read\n"
+ " <9> enable/disable measurement\n"
+ " no parameter - display current debug setup",
+ nand_debug_fun,
+ NAND_cmds
+ );
+
+local_cmd_entry("bad",
+ "Mark bad block in BBT",
+ "[-f <raw address>] [-b <block number>] [-c]\n"
+ " -c: clear bad block mark\n"
+ " -f and -b are mutually exclusive",
+ nand_bad,
+ NAND_cmds
+ );
// Define table boundaries
-CYG_HAL_TABLE_BEGIN(__NAND_cmds_TAB__, NAND_cmds);
-CYG_HAL_TABLE_END(__NAND_cmds_TAB_END__, NAND_cmds);
+CYG_HAL_TABLE_BEGIN( __NAND_cmds_TAB__, NAND_cmds);
+CYG_HAL_TABLE_END( __NAND_cmds_TAB_END__, NAND_cmds);
extern struct cmd __NAND_cmds_TAB__[], __NAND_cmds_TAB_END__;
// CLI function
static cmd_fun do_nand_cmds;
RedBoot_nested_cmd("nand",
- "Utility function to NAND flash using raw address",
- "{cmds}",
- do_nand_cmds,
- __NAND_cmds_TAB__, &__NAND_cmds_TAB_END__
- );
+ "Utility function to NAND flash using raw address",
+ "{cmds}",
+ do_nand_cmds,
+ __NAND_cmds_TAB__, &__NAND_cmds_TAB_END__
+ );
static void nand_usage(char *why)
{
struct option_info opts[2];
init_opts(&opts[0], 'f', true, OPTION_ARG_TYPE_NUM,
- (void *)&ra, (bool *)&flash_addr_set, "NAND FLASH memory byte address");
+ &ra, &flash_addr_set, "NAND FLASH memory byte address");
init_opts(&opts[1], 's', false, OPTION_ARG_TYPE_FLG,
- (void *)&spar_only, (bool *)0, "Spare only");
+ &spar_only, NULL, "Spare only");
- if (!scan_opts(argc, argv, 2, opts, 2, 0, 0, "")) {
+ if (!scan_opts(argc, argv, 2, opts, 2, 0, 0, 0)) {
return;
}
if (!flash_addr_set) {
curr_addr = ra;
}
- ra &= MXC_NAND_LA_MASK;
-
if (ra % NF_PG_SZ) {
- diag_printf("** Error: address not page aligned\n");
+ diag_printf("** Error: flash address must be page aligned\n");
return;
}
- if (nfc_is_badblock(NFC_BLOCK_ALIGN(ra))) {
+ ra &= MXC_NAND_ADDR_MASK;
+ if (nfc_is_badblock(OFFSET_TO_BLOCK(ra), g_bbt)) {
diag_printf("This is a bad block\n");
}
static void nand_read(int argc, char *argv[])
{
int len;
- unsigned long mem_addr, ra, col;
+ u32 mem_addr, ra, col, i, pg_no, pg_off;
bool mem_addr_set = false;
bool flash_addr_set = false;
bool length_set = false;
bool col_set = false;
struct option_info opts[4];
int j = 0;
- bool ecc_status = g_ecc_enable;;
+ bool ecc_status = g_ecc_enable;
init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM,
&mem_addr, &mem_addr_set, "memory base address");
&len, &length_set, "image length [in FLASH]");
init_opts(&opts[3], 'c', true, OPTION_ARG_TYPE_NUM,
&col, &col_set, "column addr");
-
+
if (!scan_opts(argc, argv, 2, opts, 4, 0, 0, 0)) {
nand_usage("invalid arguments");
return;
}
+ if (ra % NF_PG_SZ) {
+ diag_printf("** Error: flash address must be page aligned\n");
+ return;
+ }
+
if (!mem_addr_set || !flash_addr_set || !length_set) {
- nand_usage("required parameter missing");
+ nand_usage("** Error: required parameter missing");
return;
}
if ((mem_addr < (CYG_ADDRESS)ram_start) ||
- ((mem_addr + len) >= (CYG_ADDRESS)ram_end)) {
- diag_printf("** WARNING: RAM address: %08lx may be invalid\n", mem_addr);
- diag_printf(" valid range is %p-%p\n", ram_start, ram_end);
+ ((mem_addr+len) >= (CYG_ADDRESS)ram_end)) {
+ diag_printf("** WARNING: RAM address: 0x%08x may be invalid\n", mem_addr);
+ diag_printf(" valid range is 0x%p-0x%p\n", ram_start, ram_end);
}
- // Safety check - make sure the address range is not within the code we're running
- if (flash_code_overlaps((void *)ra, (void *)(ra+len-1))) {
- diag_printf("**Error: Can't program this region - contains code in use!\n");
- return;
- }
-
if (col_set) {
- u32 flash_addr = ((ra / NF_PG_SZ) << NAND_PG_SHIFT) + col;
+ diag_printf("Random read at page %u, column 0x%04x\n",
+ ra / NF_PG_SZ, col);
- diag_printf("Random read at page %ld, column %ld (addr %08x)\n",
- ra / NF_PG_SZ, col, flash_addr);
-
- if (g_is_2k_page) {
+ if (g_is_2k_page || g_is_4k_page) {
g_ecc_enable = false;
}
- nfc_read_pg_random(flash_addr, 0); // don't swap BI for 2k page
- if (g_is_2k_page) {
+ nfc_read_pg_random(ra / NF_PG_SZ, col, ECC_FORCE_OFF, 0, num_of_nand_chips);
+ if (g_is_2k_page || g_is_4k_page) {
g_ecc_enable = ecc_status;
}
-
- nfc_buf_mem_cpy((void *)mem_addr, (void *)NAND_MAIN_BUF0, NF_PG_SZ);
+ nfc_buf_read((void *)mem_addr, NAND_MAIN_BUF0, NF_PG_SZ);
return;
}
-
+
// ensure integer multiple of page size
len = (len + NF_PG_SZ - 1) & ~(NF_PG_SZ - 1);
- ra &= MXC_NAND_LA_MASK;
-
+ ra &= MXC_NAND_ADDR_MASK;
do {
if (OFFSET_TO_BLOCK(ra) > (NF_BLK_CNT - 1)) {
- diag_printf("Out of range: addr=0x%08lx\n", ra);
+ diag_printf("\n** Error: flash address: 0x%08x out of range\n", ra);
return;
}
- if (nfc_read_page(ra) != 0) {
- diag_printf("** Error: uncorrectable ECC at addr 0x%08lx\n", ra);
- diag_printf("should invoke bad block management to replace this block\n");
- diag_printf("and then mark this block \"bad\". But Redboot doesn't do it yet.\n");
- }
- if ((j++ % 0x20) == 0)
- diag_printf("\n%s 0x%08lx: ", __FUNCTION__, ra);
- diag_printf(".");
+ pg_no = ra / NF_PG_SZ;
+ pg_off = ra % NF_PG_SZ;
+ for (i = 0; i < num_of_nand_chips; i++) {
+ if (nfc_read_page(i, pg_no, pg_off) != 0) {
+ diag_printf("\n** Error: uncorrectable ECC at addr 0x%08x\n", ra);
+ diag_printf("use 'nand bad -b %u' to mark this block in BBT\n",
+ pg_no / NF_PG_PER_BLK);
+ }
+ if ((j++ % 0x20) == 0)
+ diag_printf("\n%s 0x%08x: ", __FUNCTION__, ra);
+ diag_printf(".");
- nfc_buf_mem_cpy((void *)mem_addr, (void *)NAND_MAIN_BUF0, NF_PG_SZ);
+ nfc_buf_read((void *)mem_addr, NAND_MAIN_BUF0, NF_PG_SZ / num_of_nand_chips);
- ra += NF_PG_SZ;
- mem_addr += NF_PG_SZ;
- len -= NF_PG_SZ;
+ ra += NF_PG_SZ / num_of_nand_chips;
+ mem_addr += NF_PG_SZ / num_of_nand_chips;
+ len -= NF_PG_SZ / num_of_nand_chips;
+ pg_off = 0;
+ }
} while (len > 0);
diag_printf("\n");
}
static void nand_write(int argc, char *argv[])
{
- int len, j = 0;
- u32 mem_addr, ra, col;
+ int len, len_st, j = 0;
+ u32 mem_addr, mem_addr_st, ra, col;
bool mem_addr_set = false;
bool flash_addr_set = false;
bool length_set = false;
bool col_set = false;
struct option_info opts[4];
- bool ecc_status = g_ecc_enable;;
+ bool ecc_status = g_ecc_enable;
+ int skip = 0;
init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM,
- (void *)&mem_addr, (bool *)&mem_addr_set, "memory base address");
+ &mem_addr, &mem_addr_set, "memory base address");
init_opts(&opts[1], 'f', true, OPTION_ARG_TYPE_NUM,
- (void *)&ra, (bool *)&flash_addr_set, "FLASH memory base address");
+ &ra, &flash_addr_set, "FLASH memory base address");
init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM,
- (void *)&len, (bool *)&length_set, "image length [in FLASH]");
+ &len, &length_set, "image length [in FLASH]");
init_opts(&opts[3], 'c', true, OPTION_ARG_TYPE_NUM,
- (void *)&col, (bool *)&col_set, "column addr");
- if (!scan_opts(argc, argv, 2, opts, 4, 0, 0, 0))
- {
+ &col, &col_set, "column addr");
+ if (!scan_opts(argc, argv, 2, opts, 4, 0, 0, 0)) {
nand_usage("invalid arguments");
return;
}
if ((mem_addr < (CYG_ADDRESS)ram_start) ||
((mem_addr+len) >= (CYG_ADDRESS)ram_end)) {
diag_printf("** WARNING: RAM address: %p may be invalid\n", (void *)mem_addr);
- diag_printf(" valid range is %p-%p\n", (void *)ram_start, (void *)ram_end);
+ diag_printf(" valid range is %p-%p\n", (void *)ram_start, (void *)ram_end);
}
if (col_set) {
- u32 flash_addr = ((ra / NF_PG_SZ) << NAND_PG_SHIFT) + col;
+ diag_printf("Random write at page %u, column %u\n", ra / NF_PG_SZ, col);
- diag_printf("Random write at page %d, column %d (addr %08x)\n",
- ra / NF_PG_SZ, col, flash_addr);
-
- if (g_is_2k_page) {
+ if (g_is_2k_page || g_is_4k_page) {
g_ecc_enable = false;
}
- nfc_write_pg_random(flash_addr, mem_addr, NFC_MAIN_ONLY, 0);
- if (g_is_2k_page) {
+ nfc_write_pg_random(ra / NF_PG_SZ, col, (u8 *)mem_addr, 0);
+ if (g_is_2k_page || g_is_4k_page) {
g_ecc_enable = ecc_status;
}
return;
}
- ra &= MXC_NAND_LA_MASK;
-
- if ((len % NF_PG_SZ) != 0) {
- diag_printf("Not a full page write?\n\n");
+ if ((ra % NF_PG_SZ) != 0) {
+ diag_printf("** Error: flash address must be page aligned\n");
+ return;
}
+ mem_addr_st = mem_addr;
+ len_st = len;
+ ra &= MXC_NAND_ADDR_MASK;
do {
if (OFFSET_TO_BLOCK(ra) > (NF_BLK_CNT - 1)) {
- diag_printf("Out of range: addr=0x%08x\n", ra);
+ diag_printf("Out of range: addr=0x%x\n", ra);
return;
}
- if (nfc_is_badblock(ra)) {
- diag_printf("\nERROR: bad block at raw addr=0x%08x(block=%d)\n",
- ra, OFFSET_TO_BLOCK(ra));
- diag_printf("%s() failed\n", __FUNCTION__);
- return;
+ if (nfc_is_badblock(OFFSET_TO_BLOCK(ra), g_bbt)) {
+ if (skip++ >= flash_dev_info->max_bad_blk) {
+ diag_printf("\nToo many bad blocks encountered\n");
+ return;
+ }
+ diag_printf("\nSkipping bad block %u at addr=0x%08llx\n",
+ OFFSET_TO_BLOCK(ra), (u64)ra);
+ ra = (OFFSET_TO_BLOCK(ra) + 1) * NF_BLK_SZ;
+ continue;
}
- if (nfc_program_page(ra, mem_addr, NFC_MAIN_ONLY) != 0) {
+ if ((ra % NF_BLK_SZ) == 0) {
+ mem_addr_st = mem_addr;
+ len_st = len;
+ }
+ if (nfc_write_pg_random(ra / NF_PG_SZ, ra % NF_PG_SZ, (u8 *)mem_addr, 0) != 0) {
if (g_nfc_debug_level >= NFC_DEBUG_DEF) {
- diag_printf("Error %d: program error at addr 0x%08x\n", __LINE__, ra);
- diag_printf("should invoke bad block management to replace this block \n");
- diag_printf("and then mark this block \"bad\". But Redboot doesn't do it yet.\n");
+ diag_printf("Warning %d: program error at addr 0x%x\n", __LINE__, ra);
}
- return;
+ mark_blk_bad(OFFSET_TO_BLOCK(ra), g_bbt, BLK_BAD_RUNTIME);
+ ra = (OFFSET_TO_BLOCK(ra) + 1) * NF_BLK_SZ; //make sure block size aligned
+ mem_addr = mem_addr_st; // rewind to blocl boundary
+ len = len_st;
+ continue;
}
if ((j++ % 0x20) == 0)
diag_printf("\nProgramming 0x%08x: ", ra);
diag_printf(".");
-
+
len -= NF_PG_SZ;
ra += NF_PG_SZ;
mem_addr += NF_PG_SZ;
} while (len > 0);
+ if (skip) {
+ diag_printf("\n%s(skip bad blocks=%d\n\n", __FUNCTION__, skip);
+ }
diag_printf("\n");
}
void nand_debug_fun(int argc, char *argv[])
{
int opt;
+ const char *dbg_lvl_str;
if (argc == 3) {
opt = argv[2][0] - '0';
switch (opt) {
case 0:
- g_nfc_debug_level = NFC_DEBUG_MIN;
+ g_nfc_debug_level = NFC_DEBUG_NONE;
break;
case 1:
- g_nfc_debug_level = NFC_DEBUG_MED;
+ g_nfc_debug_level = NFC_DEBUG_MIN;
break;
case 2:
- g_nfc_debug_level = NFC_DEBUG_MAX;
+ g_nfc_debug_level = NFC_DEBUG_MED;
break;
case 3:
- g_ecc_enable = g_ecc_enable? false: true;
+ g_nfc_debug_level = NFC_DEBUG_MAX;
break;
case 4:
+ g_ecc_enable = g_ecc_enable? false: true;
+ break;
+ case 5:
// toggle g_spare_only_read_ok
g_spare_only_read_ok = g_spare_only_read_ok? false: true;
break;
default:
diag_printf("%s(%s) not supported\n", __FUNCTION__, argv[2]);
- break;
-
}
}
- diag_printf("Current debug options are: \n");
- diag_printf(" h/w ECC: %s\n", g_ecc_enable ? "on":"off");
- diag_printf(" sp-only read: %s\n", g_spare_only_read_ok ? "on":"off");
- diag_printf(" measurement: %s\n", g_nfc_debug_measure ? "on":"off");
- diag_printf(" message level: %s\n", (g_nfc_debug_level == NFC_DEBUG_MIN) ? "min" : \
- ((g_nfc_debug_level == NFC_DEBUG_MED) ? "med" : "max"));
+ switch (g_nfc_debug_level) {
+ case NFC_DEBUG_NONE:
+ dbg_lvl_str = "none";
+ break;
+ case NFC_DEBUG_MIN:
+ dbg_lvl_str = "min";
+ break;
+ case NFC_DEBUG_MED:
+ dbg_lvl_str = "med";
+ break;
+ case NFC_DEBUG_MAX:
+ dbg_lvl_str = "max";
+ break;
+ default:
+ dbg_lvl_str = "invalid";
+ }
+ diag_printf("Current debug options are:\n");
+ diag_printf(" h/w ECC: %s\n", g_ecc_enable ? "on" : "off");
+ diag_printf(" sp-only read: %s\n", g_spare_only_read_ok ? "on" : "off");
+ diag_printf(" measurement: %s\n", g_nfc_debug_measure ? "on" : "off");
+ diag_printf(" message level: %s\n", dbg_lvl_str);
}
static void nand_erase(int argc, char *argv[])
{
- u32 i, j = 0, len, ra;
+ u32 len, ra;
bool faddr_set = false;
bool force_erase_set = false;
- bool force_bad_block_set = false;
bool length_set = false;
struct option_info opts[4];
init_opts(&opts[0], 'f', true, OPTION_ARG_TYPE_NUM,
- &ra, (bool *)&faddr_set, "FLASH memory base address");
+ &ra, &faddr_set, "FLASH memory base address");
init_opts(&opts[1], 'l', true, OPTION_ARG_TYPE_NUM,
- &len, (bool *)&length_set, "length in bytes");
+ &len, &length_set, "length in bytes");
init_opts(&opts[2], 'o', false, OPTION_ARG_TYPE_FLG,
- &force_erase_set, (bool *)&force_erase_set, "force erases block");
- init_opts(&opts[3], 'z', false, OPTION_ARG_TYPE_FLG,
- &force_bad_block_set, (bool *)&force_bad_block_set, "erases blocks and mark bad");
+ &force_erase_set, &force_erase_set, "force erases block");
if (!scan_opts(argc, argv, 2, opts, 4, 0, 0, 0)) {
nand_usage("invalid arguments");
if ((ra % NF_BLK_SZ) != 0 ||
(len % NF_BLK_SZ) != 0 || len == 0) {
diag_printf("Address or length is not block aligned or length is zero!\n");
- diag_printf("Block size is 0x%08x\n", NF_BLK_SZ);
+ diag_printf("Block size is 0x%x\n", NF_BLK_SZ);
return;
}
- if (!verify_action("About to erase 0x%08x bytes from nand offset 0x%08x\n", len, ra)) {
+ if (!verify_action("About to erase 0x%x bytes from nand offset 0x%x\n", len, ra)) {
diag_printf("** Aborted\n");
return;
}
- ra &= MXC_NAND_LA_MASK;
-
// now ra is block aligned
if (force_erase_set == true) {
diag_printf("Force erase ...");
- for (i = ra; i < (ra + len); i += NF_BLK_SZ) {
- if (nfc_erase_blk(i) != 0) { //error
- diag_printf("\n**Error: could not erase block %d at address 0x%08x\n",
- i / NF_BLK_SZ, i);
- goto nand_erase_out; //don't erase bad block
- } else {
- if ((j++ % 0x20) == 0)
- diag_printf("\nErasing 0x%08x: ", i);
- diag_printf(".");
- }
- }
+ nfc_erase_region(ra, len, 0, 1);
diag_printf("\n");
- } else if (force_bad_block_set == true) {
- u16 temp_spare_buf[8] = {0, 0, 0, 0, 0, 0, 0, 0};
-
- for (i = ra; i < (ra + len); i += NF_BLK_SZ) {
- if (i == 0) {
- continue;
- }
- if (nfc_is_badblock(i)) {
- diag_printf("block at 0x%08x is already bad\n", i);
- continue; //don't erase bad block
- }
- diag_printf("Erasing ... \n");
+ } else {
+ nfc_erase_region(ra, len, 1, 1);
+ }
+ diag_printf("\n");
+}
- if (nfc_erase_blk(i) != 0) { //error
- diag_printf("\n**Error: could not erase block %d at address 0x%08x\n",
- i / NF_BLK_SZ, i);
- goto nand_erase_out; //don't erase bad block
- }
+extern void romupdate(int argc, char *argv[]);
+static void nand_scan(int argc, char *argv[])
+{
+ bool force_erase = false;
+ bool force_rescan = false;
+ struct option_info opts[2];
- diag_printf("\nMarking bad block at: 0x%08x\n", i);
+ init_opts(&opts[0], 'o', false, OPTION_ARG_TYPE_FLG,
+ &force_erase, NULL, "force erases block first");
- if (nfc_program_page(i, (u32)temp_spare_buf, NFC_SPARE_ONLY) != 0) {
- diag_printf("**Error: Can't program block %d at address 0x%08x\n",
- i / NF_BLK_SZ, i);
- continue;
- }
- }
- } else {
- for (i = ra; i < (ra + len); i += NF_BLK_SZ) {
- if (nfc_is_badblock(i)) {
- diag_printf("\nWarning: Skipping erase of bad/reserved block %d at address 0x%08x\n",
- i / NF_BLK_SZ, i);
- continue; //don't erase bad block
- }
- if (nfc_erase_blk(i) != 0) { //error
- diag_printf("\n**Error: could not erase block %d at address 0x%08x\n",
- i / NF_BLK_SZ, i);
- continue; //don't erase bad block
- }
- if ((j++ % 0x20) == 0)
- diag_printf("\nErasing 0x%08x: ", i);
- diag_printf(".");
+ init_opts(&opts[1], 'r', false, OPTION_ARG_TYPE_FLG,
+ &force_rescan, NULL, "force low level re-scan");
+
+ if (!scan_opts(argc, argv, 2, opts, 2, 0, 0, 0)) {
+ nand_usage("invalid arguments");
+ return;
+ }
+
+ if (!force_erase && !force_rescan && !mxc_nfc_scan_done) {
+ diag_printf("Need to build BBT first with \"nand scan [-o|-r]\"\n");
+ return;
+ }
+ if (force_erase) {
+ void *bbt = g_bbt;
+
+ diag_printf("Force erase first ...\n");
+ g_bbt = NULL;
+ // do force erase, skipping bad blocks. After this call, g_bbt should be re-built
+ // for the whole NAND flash.
+ if (nfc_erase_region(0, NF_DEV_SZ, true, false) != 0) {
+ g_bbt = bbt;
+ return;
}
+ g_bbt = bbt;
+ mxc_nfc_scan_done = 0;
+ diag_printf("\n");
+ }
+ if (force_rescan) {
+ diag_printf("Force re-scan ...\n");
+ memset(g_bbt, 0, g_bbt_sz);
+ mxc_nfc_scan(true);
+ }
+ // program g_bbt into the flash
+ diag_printf("Writing BBT to flash\n");
+ if (program_bbt_to_flash() != 0) {
+ diag_printf("Error: Failed to write BBT to flash\n");
+ }
+ if (force_erase) {
+ romupdate(0, NULL);
}
-nand_erase_out:
- diag_printf("\n");
- mxc_nfc_scan(false);
}
-static int nfc_dump_bad_blocks(unsigned long ra, u32 len)
+static void nand_info(int argc, char *argv[])
{
- int i, j = 0;
-
- for (i = 0; i < ((len + NF_BLK_SZ - 1) / NF_BLK_SZ); i++) {
- u8 code = nfc_is_badblock(NFC_BLOCK_ALIGN(ra));
- if (code != 0) {
- diag_printf("block %ld at offset 0x%08lx is %s\n",
- OFFSET_TO_BLOCK(ra), ra,
- code == 2 ? "reserved" : "bad");
+ u32 i, j = 0;
+
+ if (nand_flash_index == -1) {
+ diag_printf("Can't find valid NAND flash: %d\n", __LINE__);
+ return;
+ }
+
+ diag_printf("\nType:\t\t %s\n", NF_VEND_INFO);
+ diag_printf("Total size:\t 0x%08x bytes (%d MiB)\n", NF_DEV_SZ, NF_DEV_SZ / SZ_1M);
+ diag_printf("Total blocks:\t 0x%x (%d)\n", NF_BLK_CNT, NF_BLK_CNT);
+ diag_printf("Block size:\t 0x%x (%d)\n", NF_BLK_SZ, NF_BLK_SZ);
+ diag_printf("Page size:\t 0x%x (%d)\n", NF_PG_SZ, NF_PG_SZ);
+ diag_printf("Spare size:\t 0x%x (%d)\n", NF_SPARE_SZ, NF_SPARE_SZ);
+ diag_printf("Pages per block: 0x%x (%d)\n", NF_PG_PER_BLK, NF_PG_PER_BLK);
+
+ if (mxc_nfc_scan(false) == -1) {
+ return;
+ }
+ diag_printf("\n");
+ for (i = 0; i < NF_BLK_CNT; i++) {
+ int res = nfc_is_badblock(i, g_bbt);
+ if (res & ~BLK_RESERVED) {
+ diag_printf("block %d at offset 0x%x is a %s bad block\n",
+ i, i * NF_BLK_SZ, res == BLK_BAD_FACTORY ? "factory" : "runtime");
j++;
}
- ra += NF_BLK_SZ;
}
- return j;
+ diag_printf("==================================\n");
+ diag_printf("Found %d bad block(s) out of %d\n", j, i);
}
-static void nand_info(int argc, char *argv[])
+static void nand_bad(int argc, char *argv[])
{
- u32 i, j = 0, len, ra;
- bool flash_addr_set = false;
- bool flash_len_set = false;
- struct option_info opts[2];
+ u32 ra;
+ u32 block;
+ bool ra_set = false;
+ bool block_set = false;
+ bool clear = false;
+ struct option_info opts[3];
+ int bad;
init_opts(&opts[0], 'f', true, OPTION_ARG_TYPE_NUM,
- &ra, &flash_addr_set, "NAND FLASH memory byte address");
- init_opts(&opts[1], 'l', true, OPTION_ARG_TYPE_NUM,
- &len, &flash_len_set, "length");
+ &ra, &ra_set, "FLASH memory base address");
+ init_opts(&opts[1], 'b', true, OPTION_ARG_TYPE_NUM,
+ &block, &block_set, "block number");
+ init_opts(&opts[2], 'c', false, OPTION_ARG_TYPE_FLG,
+ &clear, NULL, "clear bad block marker");
- if (!scan_opts(argc, argv, 2, opts, 2, 0, 0, 0)) {
+ if (!scan_opts(argc, argv, 2, opts, NUM_ELEMS(opts), NULL, 0, NULL)) {
nand_usage("invalid arguments");
return;
}
- if (nand_flash_index == -1) {
- diag_printf("Can't find valid NAND flash: %d\n", __LINE__);
+ if (!ra_set && !block_set) {
+ nand_usage("missing argument");
return;
}
-
- i = mxc_nfc_scan(true);
- if (!flash_addr_set) {
- diag_printf("\nType: %s\n", flash_dev_info->vendor_info);
- diag_printf("Total size:\t 0x%08x bytes (%d MB)\n", NF_DEV_SZ, NF_DEV_SZ / 0x100000);
- diag_printf("Total blocks:\t 0x%x (%d)\n", NF_BLK_CNT, NF_BLK_CNT);
- diag_printf("Block size:\t 0x%x (%d)\n", NF_BLK_SZ, NF_BLK_SZ);
- diag_printf("Page size:\t 0x%x (%d)\n", NF_PG_SZ, NF_PG_SZ);
- diag_printf("Pages per block: 0x%x (%d)\n", NF_PG_PER_BLK, NF_PG_PER_BLK);
-
- diag_printf("Bad blocks: \n");
-
- if (i == 0) {
- diag_printf(" none\n");
- } else {
- nfc_dump_bad_blocks(0, NF_DEV_SZ);
- diag_printf("\nTotal number of bad/reserved blocks: %d\n", i);
- }
+ if (ra_set && block_set) {
+ nand_usage("options -f and -b are mutually exclusive");
return;
+ } else if (ra_set) {
+ block = OFFSET_TO_BLOCK(ra & MXC_NAND_ADDR_MASK);
+ } else {
+ ra = BLOCK_TO_OFFSET(block) + (unsigned long)flash_info.start;
}
-
- if (!flash_len_set) {
- len = NF_DEV_SZ;
+ if ((ra % NF_BLK_SZ) != 0) {
+ diag_printf("Address is not block aligned!\n");
+ diag_printf("Block size is 0x%08x\n", NF_BLK_SZ);
+ return;
}
- ra &= MXC_NAND_LA_MASK;
-
- if (ra % NF_BLK_SZ) {
- diag_printf("** Error: address 0x%08x not aligned to block boundary\n", ra);
+ bad = nfc_is_badblock(block, g_bbt);
+ if ((bad && !clear) || (!bad && clear)) {
+ diag_printf("block %5u at address 0x%08x is already %s\n",
+ block, ra, bad ? "bad" : "good");
return;
}
- diag_printf("\n");
- j = nfc_dump_bad_blocks(0, NF_DEV_SZ);
- diag_printf("==================================\n");
- diag_printf("Found %d bad block(s) out of %d\n", j, (len + NF_BLK_SZ - 1) / NF_BLK_SZ);
+ if (clear && bad != BLK_BAD_RUNTIME) {
+ diag_printf("Refusing to mark a factory bad block as good!\n");
+ return;
+ }
+ if (!verify_action("Mark block %u at address 0x%08x %s in BBT",
+ block, ra, clear ? "good" : "bad")) {
+ diag_printf("** Aborted\n");
+ return;
+ }
+
+ nfc_printf(NFC_DEBUG_MIN, "Marking block %5u at 0x%08x %s\n",
+ block, ra, clear ? "good" : "bad");
+ mark_blk_bad(block, g_bbt, clear ? 0 : BLK_BAD_RUNTIME);
+ mxc_nfc_update_bbt(g_mxc_nfc_bbt_main_descr,
+ g_mxc_nfc_bbt_mirror_descr);
}
static void do_nand_cmds(int argc, char *argv[])
struct cmd *cmd;
if (!mxcnfc_init_ok) {
- diag_printf("\nWarning:NAND flash hasn't been initialized. Try \"factive nand\" first\n\n");
+#ifdef CYGHWR_DEVS_FLASH_MXC_MULTI
+ diag_printf("Warning: NAND flash hasn't been initialized. Try \"factive nand\" first\n\n");
+#else
+ diag_printf("Error: NAND flash hasn't been initialized\n");
+#endif
return;
}
nand_usage("too few arguments");
return;
}
+
if ((cmd = cmd_search(__NAND_cmds_TAB__, &__NAND_cmds_TAB_END__,
- argv[1])) != (struct cmd *)0) {
- (cmd->fun)(argc, argv);
+ argv[1])) != NULL) {
+ cmd->fun(argc, argv);
return;
}
nand_usage("unrecognized command");
* @param pkt pointer to the starting address of the memory
* @param len byte length of the buffer to be displayed
*/
-static void print_pkt_16(u16* pkt, u32 len)
+static void print_pkt_16(u16 *pkt, u32 len)
{
diag_printf("******************** %d bytes********************\n", len);
u32 i = 0, tempLen = (len + 1) / 2;
- while (tempLen >= 0) {
+ while (tempLen != 0) {
if (tempLen >= 8) {
- diag_printf("[%03x-%03x] ", i*2, ((i*2)+14));
+ diag_printf("[%03x-%03x] ", i * 2, (i * 2) + 14);
diag_printf("%04x %04x %04x %04x %04x %04x %04x %04x\n",
- pkt[i], pkt[i+1], pkt[i+2], pkt[i+3],
- pkt[i+4], pkt[i+5], pkt[i+6], pkt[i+7]);
+ pkt[i], pkt[i + 1], pkt[i + 2], pkt[i + 3],
+ pkt[i + 4], pkt[i + 5], pkt[i + 6], pkt[i + 7]);
+ tempLen -= 8;
+ i += 8;
} else {
- if (tempLen == 0) {
- diag_printf("*************************************************\n");
- return;
- }
- diag_printf("[%03x-%03x] ", i*2, ((i*2)+14));
- switch(tempLen) {
- case 1:
- diag_printf("%04x\n", pkt[i]);
- break;
- case 2:
- diag_printf("%04x %04x\n", pkt[i], pkt[i+1]);
- break;
- case 3:
- diag_printf("%04x %04x %04x\n", pkt[i], pkt[i+1], pkt[i+2]);
- break;
- case 4:
- diag_printf("%04x %04x %04x %04x\n", pkt[i],pkt[i+1], pkt[i+2],pkt[i+3]);
- break;
- case 5:
- diag_printf("%04x %04x %04x %04x %04x\n", pkt[i], pkt[i+1], pkt[i+2], pkt[i+3],pkt[i+4]);
- break;
- case 6:
- diag_printf("%04x %04x %04x %04x %04x %04x\n", pkt[i], pkt[i+1], pkt[i+2], pkt[i+3],pkt[i+4],
- pkt[i+5]);
- break;
- case 7:
- diag_printf("%04x %04x %04x %04x %04x %04x %04x\n", pkt[i], pkt[i+1], pkt[i+2], pkt[i+3],pkt[i+4],
- pkt[i+5], pkt[i+6]);
- break;
+ if (tempLen != 0) {
+ diag_printf("[%03x-%03x]", i * 2, (i + tempLen) * 2);
+ while (tempLen-- != 0) {
+ diag_printf(" %04x", pkt[i++]);
+ }
+ diag_printf("\n");
}
+ diag_printf("*************************************************\n");
+ return;
}
- tempLen -= 8;
- i += 8;
}
}
// addr = starting byte address within NAND flash
static void print_page(u32 addr, bool spare_only)
{
+ u32 i, pg_no, pg_off;
u32 blk_num = OFFSET_TO_BLOCK(addr), pg_num = OFFSET_TO_PAGE(addr);
+ if (addr % NF_PG_SZ) {
+ diag_printf("Non page-aligned read not supported here: 0x%x\n", addr);
+ return;
+ }
if (spare_only) {
- if (nfc_read_page_sp(addr) != 0) {
- diag_printf("Error %d: uncorrectable. But still printing ...\n", __LINE__);
- }
+ diag_printf("Error %d: Not supported\n", __LINE__);
+ return;
} else {
- if (nfc_read_page(addr) != 0) {
- diag_printf("Error %d: uncorrectable. But still printing ...\n", __LINE__);
- }
- }
+ pg_no = addr / NF_PG_SZ;
+ pg_off = addr % NF_PG_SZ;
+ for (i = 0; i < num_of_nand_chips; i++) {
+ if (nfc_read_page(i, pg_no, pg_off) != 0) {
+ diag_printf("Error %d: uncorrectable. But still printing ...\n", __LINE__);
+ }
+ pg_off = 0;
+ diag_printf("\n============ Printing block(%d) page(%d) ==============\n",
+ blk_num, pg_num);
- diag_printf("\n============ Printing block(%d) page(%d) ==============\n",
- blk_num, pg_num);
+ diag_printf("<<<<<<<<< spare area >>>>>>>>>\n");
+ print_pkt_16((u16*)NAND_SPAR_BUF0, NF_SPARE_SZ);
- diag_printf("<<<<<<<<< spare area >>>>>>>>>\n");
- print_pkt_16((u16*)(NAND_SPAR_BUF0), g_is_2k_page ? 64 : 16);
+ if (!spare_only) {
+ diag_printf("<<<<<<<<< main area >>>>>>>>>\n");
+ print_pkt_16((u16*)NAND_MAIN_BUF0, NF_PG_SZ / num_of_nand_chips);
+ }
- if (!spare_only) {
- diag_printf("<<<<<<<<< main area >>>>>>>>>\n");
- print_pkt_16((u16*)(NAND_MAIN_BUF0), NF_PG_SZ);
+ diag_printf("\n");
+ }
}
-
- diag_printf("\n");
}
// Author(s): Kevin Zhang <k.zhang@freescale.com>
// Contributors: Kevin Zhang <k.zhang@freescale.com>
// Date: 2006-01-23
-// Purpose:
-// Description:
-//
+// Purpose:
+// Description:
+//
//####DESCRIPTIONEND####
//
//==========================================================================
extern int nandflash_program_buf(void* addr, void* data, int len);
extern int nandflash_lock_block(void* block);
extern int nandflash_unlock_block(void* block, int block_size, int blocks);
+extern void mxc_nfc_print_info(void);
+extern int nandflash_read_buf(void* addr, void* data, int len);
+
+extern void mmcflash_query(void* data);
+extern int mmcflash_hwr_init(void);
+extern int mmcflash_hwr_map_error(int e);
+extern bool mmcflash_code_overlaps(void *start, void *end);
+extern int mmcflash_erase_block(void* block, unsigned int size);
+extern int mmcflash_program_buf(void* addr, void* data, int len);
+extern int mmcflash_lock_block(void* block);
+extern int mmcflash_unlock_block(void* block, int block_size, int blocks);
+extern void mxc_mmc_print_info(void);
+extern int mmcflash_read_buf(void* addr, void* data, int len);
+
+extern void ata_hwr_init(void);
+
+extern void spi_norflash_query(void* data);
+extern int spi_norflash_hwr_init(void);
+extern int spi_norflash_hwr_map_error(int e);
+extern bool spi_norflash_code_overlaps(void *start, void *end);
+extern int spi_norflash_erase_block(void* block, unsigned int size);
+extern int spi_norflash_program_buf(void* addr, void* data, int len);
+extern int spi_norflash_lock_block(void* block);
+extern int spi_norflash_unlock_block(void* block, int block_size, int blocks);
+extern int spi_norflash_read_buf(void* addr, void* data, int len);
+
+#ifndef IS_BOOTING_FROM_SPI_NOR()
+#define IS_BOOTING_FROM_SPI_NOR() 0
+#endif
+#ifndef IS_FIS_FROM_SPI_NOR()
+#define IS_FIS_FROM_SPI_NOR() 0
+#endif
static int mxc_flash_warning_done = 0;
void flash_query(void* data)
{
if (IS_BOOTING_FROM_NOR() || IS_FIS_FROM_NOR()) {
+#ifdef MXCFLASH_SELECT_NOR
norflash_query(data);
+#endif
+ } else if (IS_BOOTING_FROM_SPI_NOR() || IS_FIS_FROM_SPI_NOR()){
+#ifdef IMXFLASH_SELECT_SPI_NOR
+ spi_norflash_query(data);
+#endif
} else if (IS_BOOTING_FROM_NAND() || IS_FIS_FROM_NAND()) {
nandflash_query(data);
+ } else if (IS_BOOTING_FROM_MMC() || IS_FIS_FROM_MMC()){
+#ifdef MXCFLASH_SELECT_MMC
+ mmcflash_query(data);
+#endif
} else {
if (!mxc_flash_warning_done) {
mxc_flash_warning_done = 1;
- diag_printf("1: Use \"factive [NOR|NAND]\" to select either NOR or NAND flash\n");
+ diag_printf("1: Use \"factive\" to select a boot type such as NAND|NOR|MMC|...\n");
}
}
}
int flash_hwr_init(void)
{
if (IS_BOOTING_FROM_NOR() || IS_FIS_FROM_NOR()) {
+#ifdef MXCFLASH_SELECT_NOR
return norflash_hwr_init();
+#endif
+ } else if (IS_BOOTING_FROM_SPI_NOR() || IS_FIS_FROM_SPI_NOR()){
+#ifdef IMXFLASH_SELECT_SPI_NOR
+#ifdef MXCFLASH_SELECT_ATA
+ /* ATA support is needed only for SPI boot */
+ ata_hwr_init();
+#endif
+ return spi_norflash_hwr_init();
+#endif
} else if (IS_BOOTING_FROM_NAND() || IS_FIS_FROM_NAND()) {
+#ifdef MXCFLASH_SELECT_NAND
return nandflash_hwr_init();
+#endif
+ } else if (IS_BOOTING_FROM_MMC() || IS_FIS_FROM_MMC()){
+#ifdef MXCFLASH_SELECT_MMC
+ return mmcflash_hwr_init();
+#endif
} else {
if (!mxc_flash_warning_done)
mxc_flash_warning_done = 1;
- diag_printf("2: Use \"factive [NOR|NAND]\" to select either NOR or NAND flash\n");
+ diag_printf("2: Use \"factive\" to select a boot type such as NAND|NOR|MMC|...\n");
return -1;
}
+
+ return -1;
}
int flash_hwr_map_error(int e)
{
if (IS_BOOTING_FROM_NOR() || IS_FIS_FROM_NOR()) {
+#ifdef MXCFLASH_SELECT_NOR
return norflash_hwr_map_error(e);
- } else {
+#endif
+ } else if (IS_BOOTING_FROM_NAND() || IS_FIS_FROM_NAND()) {
+#ifdef MXCFLASH_SELECT_NAND
return nandflash_hwr_map_error(e);
+#endif
+ } else if (IS_BOOTING_FROM_SPI_NOR() || IS_FIS_FROM_SPI_NOR()){
+#ifdef IMXFLASH_SELECT_SPI_NOR
+ return spi_norflash_hwr_map_error(e);
+#endif
+ } else if (IS_BOOTING_FROM_MMC() || IS_FIS_FROM_MMC()){
+#ifdef MXCFLASH_SELECT_MMC
+ return mmcflash_hwr_map_error(e);
+#endif
}
+ return e;
}
bool flash_code_overlaps(void *start, void *end)
{
if (IS_BOOTING_FROM_NOR() || IS_FIS_FROM_NOR()) {
+#ifdef MXCFLASH_SELECT_NOR
return norflash_code_overlaps(start, end);
- } else {
+#endif
+ } else if (IS_BOOTING_FROM_SPI_NOR() || IS_FIS_FROM_SPI_NOR()){
+#ifdef IMXFLASH_SELECT_SPI_NOR
+ return spi_norflash_code_overlaps(start, end);
+#endif
+ } else if (IS_BOOTING_FROM_MMC() || IS_FIS_FROM_MMC()){
+#ifdef MXCFLASH_SELECT_MMC
+ return mmcflash_code_overlaps(start, end);
+#endif
+ } else if (IS_BOOTING_FROM_NAND() || IS_FIS_FROM_NAND()){
+#ifdef MXCFLASH_SELECT_NAND
return nandflash_code_overlaps(start, end);
+#endif
+ } else {
+ diag_printf("Error %d: where is fis\n", __LINE__);
+ return true;
}
+ return false;
}
int flash_erase_block(void* block, unsigned int size)
{
if (IS_BOOTING_FROM_NOR() || IS_FIS_FROM_NOR()) {
+#ifdef MXCFLASH_SELECT_NOR
return norflash_erase_block(block, size);
- } else {
+#endif
+ } else if (IS_BOOTING_FROM_SPI_NOR() || IS_FIS_FROM_SPI_NOR()){
+#ifdef IMXFLASH_SELECT_SPI_NOR
+ return spi_norflash_erase_block(block, size);
+#endif
+ } else if (IS_BOOTING_FROM_MMC() || IS_FIS_FROM_MMC()){
+#ifdef MXCFLASH_SELECT_MMC
+ return mmcflash_erase_block(block, size);
+#endif
+ } else if (IS_BOOTING_FROM_NAND() || IS_FIS_FROM_NAND()){
+#ifdef MXCFLASH_SELECT_NAND
return nandflash_erase_block(block, size);
+#endif
+ } else {
+ diag_printf("Error %d: where is fis\n", __LINE__);
+ return -1;
}
+ return 0;
}
int flash_program_buf(void* addr, void* data, int len)
{
if (IS_BOOTING_FROM_NOR() || IS_FIS_FROM_NOR()) {
+#ifdef MXCFLASH_SELECT_NOR
return norflash_program_buf(addr, data, len);
- } else {
+#endif
+ } else if (IS_BOOTING_FROM_SPI_NOR() || IS_FIS_FROM_SPI_NOR()){
+#ifdef IMXFLASH_SELECT_SPI_NOR
+ return spi_norflash_program_buf(addr, data, len);
+#endif
+ } else if (IS_BOOTING_FROM_NAND() || IS_FIS_FROM_NAND()) {
+#ifdef MXCFLASH_SELECT_NAND
return nandflash_program_buf(addr, data, len);
+#endif
+ } else if (IS_BOOTING_FROM_MMC() || IS_FIS_FROM_MMC()){
+#ifdef MXCFLASH_SELECT_MMC
+ return mmcflash_program_buf(addr, data, len);
+#else
+ return 0;
+#endif
+ } else {
+ return -1;
+ }
+}
+
+int flash_read_buf(void* addr, void* data, int len)
+{
+ if (IS_BOOTING_FROM_NAND() || IS_FIS_FROM_NAND()){
+#ifdef MXCFLASH_SELECT_NAND
+ return nandflash_read_buf(addr, data, len);
+#endif
+ } else if (IS_BOOTING_FROM_NOR() || IS_FIS_FROM_NOR()) {
+#ifdef MXCFLASH_SELECT_NOR
+ memcpy(data, addr, len);
+ return 0;
+#endif
+ } else if (IS_BOOTING_FROM_SPI_NOR() || IS_FIS_FROM_SPI_NOR()){
+#ifdef IMXFLASH_SELECT_SPI_NOR
+ return spi_nor_read(addr, data, len);
+#endif
+ } else if (IS_BOOTING_FROM_MMC() || IS_FIS_FROM_MMC()) {
+#ifdef MXCFLASH_SELECT_MMC
+ return mmcflash_read_buf(addr, data, len);
+#endif
+ } else {
+ return -1;
}
+ return 0;
}
int flash_lock_block(void* block)
{
if (IS_BOOTING_FROM_NOR() || IS_FIS_FROM_NOR()) {
+#ifdef MXCFLASH_SELECT_NOR
return norflash_lock_block(block);
- } else {
+#endif
+ } else if (IS_BOOTING_FROM_MMC() || IS_FIS_FROM_MMC()){
+#ifdef MXCFLASH_SELECT_MMC
+ return mmcflash_lock_block(block);
+#endif
+ } else if (IS_BOOTING_FROM_NAND() || IS_FIS_FROM_NAND()) {
+#ifdef MXCFLASH_SELECT_NAND
return nandflash_lock_block(block);
+#endif
}
+ return 0;
}
int flash_unlock_block(void* block, int block_size, int blocks)
{
if (IS_BOOTING_FROM_NOR() || IS_FIS_FROM_NOR()) {
+#ifdef MXCFLASH_SELECT_NOR
return norflash_unlock_block(block, block_size, blocks);
- } else {
+#endif
+ } else if (IS_BOOTING_FROM_MMC() || IS_FIS_FROM_MMC()){
+#ifdef MXCFLASH_SELECT_MMC
+ return mmcflash_unlock_block(block, block_size, blocks);
+#endif
+ } else if (IS_BOOTING_FROM_NAND() || IS_FIS_FROM_NAND()) {
+#ifdef MXCFLASH_SELECT_NAND
return nandflash_unlock_block(block, block_size, blocks);
+#endif
}
+ return 0;
}
-extern void mxc_nfc_print_info(void);
-
static void mxc_flash_print_info(void)
{
if (IS_BOOTING_FROM_NOR()) {
diag_printf("\nBooting from [NOR flash]\n");
- MXC_ASSERT_NOR_BOOT();
} else if (IS_BOOTING_FROM_NAND()) {
+#ifdef MXCFLASH_SELECT_NAND
diag_printf("\nBooting from [NAND flash]\n");
- MXC_ASSERT_NAND_BOOT();
mxc_nfc_print_info();
+#endif
+ } else if (IS_BOOTING_FROM_SPI_NOR()) {
+#ifdef MXCFLASH_SELECT_SPI_NOR
+ diag_printf("\nBooting from [SPI NOR flash]\n");
+ imx_spi_nor_print_info();
+#endif
} else if (IS_BOOTING_FROM_SDRAM()) {
diag_printf("\nBooting from [SDRAM]\n");
- } else {
- diag_printf("\n!!!Warning: Unknown boot source !!!\n");
+ } else if (IS_BOOTING_FROM_MMC() ){
+#ifdef MXCFLASH_SELECT_MMC
+ mxc_mmc_print_info();
+#else
+ return;
+#endif
}
diag_printf("\n");
}
+2006-12-14 Yoshinori Sato <ysato@users.sourceforge.jp>
+
+ * cdl/flash_intel_28fxxx.cdl, include/flash_28fxxx_parts.inl: Add
+ Intel 28F320J3 part.
+
+2006-11-28 Sergei Gavrikov <sg@sgs.gomel.by>
+
+ * cdl/flash_intel_28fxxx.cdl, include/flash_28fxxx_parts.inl:
+ Add Intel 28F160C3-B part.
+
+2006-11-21 Alexander Neundorf <alexander.neundorf@jenoptik.com>
+
+ * cdl/flash_intel_28fxxx.cdl, include/flash_28fxxx_parts.inl:
+ Add Intel 28F128K3, 28F128P30 and 28F128J3 parts.
+
+2006-11-17 Alexander Neundorf <alexander.neundorf@jenoptik.com>
+
+ * cdl/flash_intel_28fxxx.cdl, include/flash_28fxxx.inl:
+ Make the timeout configurable by adding a new CDL-option
+ CYGNUM_DEVS_FLASH_INTEL_28FXXX_TIMEOUT
+
+2006-05-10 Sergei Gavrikov <sg@belvok.com>
+
+ * cdl/flash_intel_28fxxx.cdl, include/flash_28fxxx_parts.inl: Add
+ Intel 28F160B3-T part.
+
2005-04-22 David Vrabel <dvrabel@arcom.com>
* cdl/flash_intel_28fxxx.cdl, include/flash_28fxxx_parts.inl: Add
requires { CYGINT_DEVS_FLASH_INTEL_VARIANTS != 0 }
+ cdl_option CYGNUM_DEVS_FLASH_INTEL_28FXXX_TIMEOUT {
+ display "Timeout for flash operations (simple counter based)"
+ flavor data
+ legal_values 1000000 to 1000000000
+ default_value 50000000
+ description "
+ Timeout for flash operations. This is just a simple
+ counter. It depends on the speed of the flash, the processor, etc.
+ It has to be adjusted for each hardware configuration. "
+ }
+
+
cdl_interface CYGINT_DEVS_FLASH_INTEL_VARIANTS {
display "Number of included variants"
}
part in the family."
}
+ cdl_option CYGHWR_DEVS_FLASH_INTEL_28F160B3T {
+ display "Intel 28F160B3T flash memory support"
+ default_value 0
+ implements CYGHWR_IO_FLASH_BLOCK_LOCKING
+ implements CYGINT_DEVS_FLASH_INTEL_VARIANTS
+ description "
+ When this option is enabled, the Intel flash driver will be
+ able to recognize and handle the 28F160B3T
+ part in the family."
+ }
+
+ cdl_option CYGHWR_DEVS_FLASH_INTEL_28F160C3B {
+ display "Intel 28F160C3B flash memory support"
+ default_value 0
+ implements CYGHWR_IO_FLASH_BLOCK_LOCKING
+ implements CYGINT_DEVS_FLASH_INTEL_VARIANTS
+ description "
+ When this option is enabled, the Intel flash driver will be
+ able to recognize and handle the 28F160C3B
+ part in the family."
+ }
+
cdl_option CYGHWR_DEVS_FLASH_INTEL_28F320B3 {
display "Intel 28F320B3 flash memory support"
default_value 0
part in the family."
}
+ cdl_option CYGHWR_DEVS_FLASH_INTEL_28F128K3 {
+ display "Intel 28F128K3 flash memory support"
+ default_value 0
+ implements CYGHWR_IO_FLASH_BLOCK_LOCKING
+ implements CYGINT_DEVS_FLASH_INTEL_VARIANTS
+ description "
+ When this option is enabled, the Intel flash driver will be
+ able to recognize and handle the 28F128K3
+ part in the family."
+ }
+
+ cdl_option CYGHWR_DEVS_FLASH_INTEL_28F128P30 {
+ display "Intel 28F128P30 flash memory support"
+ default_value 0
+ implements CYGHWR_IO_FLASH_BLOCK_LOCKING
+ implements CYGINT_DEVS_FLASH_INTEL_VARIANTS
+ implements CYGHWR_DEVS_FLASH_INTEL_BUFFERED_WRITES
+ description "
+ When this option is enabled, the Intel flash driver will be
+ able to recognize and handle the 28F128P30
+ part in the family."
+ }
+
+ cdl_option CYGHWR_DEVS_FLASH_INTEL_28F128J3 {
+ display "Intel 28F128J3 flash memory support"
+ default_value 0
+ implements CYGHWR_IO_FLASH_BLOCK_LOCKING
+ implements CYGINT_DEVS_FLASH_INTEL_VARIANTS
+ description "
+ When this option is enabled, the Intel flash driver will be
+ able to recognize and handle the 28F128J3
+ part in the family."
+ }
+
+ cdl_option CYGHWR_DEVS_FLASH_INTEL_28F320J3 {
+ display "Intel 28F320J3 flash memory support"
+ default_value 0
+ implements CYGHWR_IO_FLASH_BLOCK_LOCKING
+ implements CYGINT_DEVS_FLASH_INTEL_VARIANTS
+ description "
+ When this option is enabled, the Intel flash driver will be
+ able to recognize and handle the 28F320J3
+ part in the family."
+ }
+
cdl_option CYGHWR_DEVS_FLASH_INTEL_28F800B5 {
display "Intel 28F800B5 flash memory support"
default_value 0
*b_v = FLASH_Block_Erase;
*b_v = FLASH_Confirm;
- timeout = 50000000;
+ timeout = CYGNUM_DEVS_FLASH_INTEL_28FXXX_TIMEOUT ;
while(((stat = *b_v) & FLASH_Status_Ready) != FLASH_Status_Ready) {
if (--timeout == 0) break;
}
volatile flash_data_t* data_p = (flash_data_t*) data;
int res = FLASH_ERR_OK;
-
+
// Base address of device(s) being programmed.
ROM = FLASH_P2V((unsigned long)addr & flash_dev_info->base_mask);
BA = FLASH_P2V((unsigned long)addr & ~(flash_dev_info->block_size - 1));
wc = (wc + 1) & ~0x1;
- timeout = 50000000;
+ timeout = CYGNUM_DEVS_FLASH_INTEL_28FXXX_TIMEOUT;
do {
*addr_v = FLASH_Write_Buffer_M18;
if (--timeout == 0) {
// confirm
*addr_p = FLASH_Confirm;
- timeout = 50000000;
+ timeout = CYGNUM_DEVS_FLASH_INTEL_28FXXX_TIMEOUT;
while(((stat = *addr_p) & FLASH_Status_Ready) != FLASH_Status_Ready) {
if (--timeout == 0) {
res = FLASH_ERR_DRV_TIMEOUT;
if (wc > len) wc = len;
len -= wc;
wc = wc / ((CYGNUM_FLASH_WIDTH/8)*CYGNUM_FLASH_INTERLEAVE); // Word count
- timeout = 50000000;
+ timeout = CYGNUM_DEVS_FLASH_INTEL_28FXXX_TIMEOUT;
*BA = FLASH_Write_Buffer;
while(((stat = BA[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) {
*BA = FLASH_Confirm;
*BA = FLASH_Read_Status;
- timeout = 50000000;
+ timeout = CYGNUM_DEVS_FLASH_INTEL_28FXXX_TIMEOUT;
while(((stat = BA[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) {
if (--timeout == 0) {
res = FLASH_ERR_DRV_TIMEOUT;
while (len > 0) {
addr_v = FLASH_P2V(addr_p++);
- *addr_v = FLASH_Program;
+ *addr_v = FLASH_Program;
*addr_v = *data_p;
- timeout = 50000000;
+ timeout = CYGNUM_DEVS_FLASH_INTEL_28FXXX_TIMEOUT;
while(((stat = *addr_v) & FLASH_Status_Ready) != FLASH_Status_Ready) {
if (--timeout == 0) {
res = FLASH_ERR_DRV_TIMEOUT;
volatile flash_data_t *ROM;
int res = FLASH_ERR_OK;
flash_data_t state;
- int timeout = 5000000;
+ int timeout = CYGNUM_DEVS_FLASH_INTEL_28FXXX_TIMEOUT;
volatile flash_data_t* b_p = (flash_data_t*) block;
volatile flash_data_t *b_v;
cyg_bool bootblock;
}
CYGHWR_FLASH_WRITE_ENABLE();
-
+
while (len > 0) {
b_v = FLASH_P2V(b_p);
#ifdef CYGPKG_HAL_ARM_MXC30031ADS
volatile flash_data_t *ROM;
int res = FLASH_ERR_OK;
flash_data_t state;
- int timeout = 5000000;
+ int timeout = CYGNUM_DEVS_FLASH_INTEL_28FXXX_TIMEOUT;
volatile flash_data_t* b_p = (flash_data_t*) block;
volatile flash_data_t *b_v;
// Clears all lock bits
ROM[0] = FLASH_Clear_Lock;
ROM[0] = FLASH_Clear_Lock_Confirm; // Confirmation
- timeout = 5000000;
+ timeout = CYGNUM_DEVS_FLASH_INTEL_28FXXX_TIMEOUT;
while(((state = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) {
if (--timeout == 0) break;
}
if (is_locked[i]) {
*b_v = FLASH_Set_Lock;
*b_v = FLASH_Set_Lock_Confirm; // Confirmation
- timeout = 5000000;
+ timeout = CYGNUM_DEVS_FLASH_INTEL_28FXXX_TIMEOUT;
while(((state = ROM[0]) & FLASH_Status_Ready)
!= FLASH_Status_Ready) {
if (--timeout == 0){
// Clears all lock bits
ROM[0] = FLASH_Clear_Locks;
ROM[0] = FLASH_Clear_Locks_Confirm; // Confirmation
- timeout = 5000000;
+ timeout = CYGNUM_DEVS_FLASH_INTEL_28FXXX_TIMEOUT;
while(((stat = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) {
if (--timeout == 0) break;
}
if (is_locked[i]) {
*bpv = FLASH_Set_Lock;
*bpv = FLASH_Set_Lock_Confirm; // Confirmation
- timeout = 5000000;
+ timeout = CYGNUM_DEVS_FLASH_INTEL_28FXXX_TIMEOUT;
while(((stat = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) {
if (--timeout == 0) break;
}
},
#endif
-
#ifdef CYGHWR_DEVS_FLASH_INTEL_28F320S3
{ // 28F320S3
device_id : FLASHWORD(0x00d4),
},
#endif
+#ifdef CYGHWR_DEVS_FLASH_INTEL_28F320J3
+ { // 28F320J3
+ device_id : FLASHWORD(0x0016),
+ block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE,
+ block_count: 32,
+ device_size: 0x400000 * CYGNUM_FLASH_INTERLEAVE,
+ base_mask : ~(0x400000 * CYGNUM_FLASH_INTERLEAVE - 1),
+ locking : false,
+ buffered_w : false,
+ bootblock : false,
+ banked : false
+ },
+#endif
+
+#ifdef CYGHWR_DEVS_FLASH_INTEL_28F128K3
+ {
+ device_id : FLASHWORD(0x8802),
+ block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE,
+ block_count: 128,
+ device_size: 0x1000000 * CYGNUM_FLASH_INTERLEAVE,
+ base_mask : ~(0x1000000 * CYGNUM_FLASH_INTERLEAVE - 1),
+ locking : true,
+ buffered_w : true,
+ bootblock : false,
+ banked : false
+ },
+#endif
+
+#ifdef CYGHWR_DEVS_FLASH_INTEL_28F128P30
+ {
+ device_id : FLASHWORD(0x8818),
+ block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE,
+ block_count: 128,
+ device_size: 0x1000000 * CYGNUM_FLASH_INTERLEAVE,
+ base_mask : ~(0x1000000 * CYGNUM_FLASH_INTERLEAVE - 1),
+ locking : true,
+ buffered_w : true,
+ bootblock : false,
+ banked : false
+ },
+#endif
+
+#ifdef CYGHWR_DEVS_FLASH_INTEL_28F128J3
+ {
+ device_id : FLASHWORD(0x18),
+ block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE,
+ block_count: 128,
+ device_size: 0x1000000 * CYGNUM_FLASH_INTERLEAVE,
+ base_mask : ~(0x1000000 * CYGNUM_FLASH_INTERLEAVE - 1),
+ locking : true,
+ buffered_w : true,
+ bootblock : false,
+ banked : false
+ },
+#endif
+
#ifdef CYGHWR_DEVS_FLASH_INTEL_28F160S5
{ // 28F160S5
device_id : FLASHWORD(0x00d0),
},
#endif
+#ifdef CYGHWR_DEVS_FLASH_INTEL_28F160B3T
+ { // 28F160B3-T
+ device_id : FLASHWORD(0x8890),
+ block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE,
+ block_count: 32,
+ device_size: 0x200000 * CYGNUM_FLASH_INTERLEAVE,
+ base_mask : ~(0x200000 * CYGNUM_FLASH_INTERLEAVE - 1),
+ buffered_w : false,
+ locking : true,
+ bootblock : true,
+ bootblocks : { 0x1f0000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0
+ },
+ banked : false
+ },
+#endif
+
+#ifdef CYGHWR_DEVS_FLASH_INTEL_28F160C3B
+ { // 28F160C3-B
+ device_id : FLASHWORD(0x88C3),
+ block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE,
+ block_count: 32,
+ device_size: 0x200000 * CYGNUM_FLASH_INTERLEAVE,
+ base_mask : ~(0x200000 * CYGNUM_FLASH_INTERLEAVE - 1),
+ buffered_w : false,
+ locking : true,
+ bootblock : true,
+ bootblocks : { 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x002000 * CYGNUM_FLASH_INTERLEAVE,
+ 0x1f0000 * CYGNUM_FLASH_INTERLEAVE,
+ 0
+ },
+ banked : false
+ },
+#endif
+
#ifdef CYGHWR_DEVS_FLASH_INTEL_28F800B5
{ // 28F800B5-T
device_id : FLASHWORD(0x889c),
+2006-12-21 Wang Cui <iucgnaw@msn.com>
+
+ * include/flash_sst_39vfxxx.inl: Add supported devices:
+ SST39VF160, SST39VF1601, SST39VF1602, SST39VF320, SST39VF3201,
+ SST39VF3202, SST39VF6401, SST39VF6402,
+
2003-10-02 Roland Caßebohm <r.cassebohm@visionsystems.de>
* include/flash_sst_39vfxxx.inl:
# define CYGNUM_FLASH_ID_DEVICE FLASHWORD(0x2780)
#endif
+#ifdef CYGPKG_DEVS_FLASH_SST_39VF160
+# define FLASH_BLOCK_SIZE ((4*1024)*CYGNUM_FLASH_INTERLEAVE)
+# define FLASH_NUM_REGIONS ((2*1024*1024)/FLASH_BLOCK_SIZE)
+# define CYGNUM_FLASH_BASE_MASK (0xFFE00000u) // 2048kB devices
+# define CYGNUM_FLASH_WIDTH (16)
+# define CYGNUM_FLASH_BLANK (1)
+# define CYGNUM_FLASH_ID_MANUFACTURER FLASHWORD(0x00BF)
+# define CYGNUM_FLASH_ID_DEVICE FLASHWORD(0x2782)
+#endif
+#ifdef CYGPKG_DEVS_FLASH_SST_39VF1601
+# define FLASH_BLOCK_SIZE ((4*1024)*CYGNUM_FLASH_INTERLEAVE)
+# define FLASH_NUM_REGIONS ((2*1024*1024)/FLASH_BLOCK_SIZE)
+# define CYGNUM_FLASH_BASE_MASK (0xFFE00000u) // 2048kB devices
+# define CYGNUM_FLASH_WIDTH (16)
+# define CYGNUM_FLASH_BLANK (1)
+# define CYGNUM_FLASH_ID_MANUFACTURER FLASHWORD(0x00BF)
+# define CYGNUM_FLASH_ID_DEVICE FLASHWORD(0x234B)
+#endif
+#ifdef CYGPKG_DEVS_FLASH_SST_39VF1602
+# define FLASH_BLOCK_SIZE ((4*1024)*CYGNUM_FLASH_INTERLEAVE)
+# define FLASH_NUM_REGIONS ((2*1024*1024)/FLASH_BLOCK_SIZE)
+# define CYGNUM_FLASH_BASE_MASK (0xFFE00000u) // 2048kB devices
+# define CYGNUM_FLASH_WIDTH (16)
+# define CYGNUM_FLASH_BLANK (1)
+# define CYGNUM_FLASH_ID_MANUFACTURER FLASHWORD(0x00BF)
+# define CYGNUM_FLASH_ID_DEVICE FLASHWORD(0x234A)
+#endif
+
+#ifdef CYGPKG_DEVS_FLASH_SST_39VF320
+# define FLASH_BLOCK_SIZE ((4*1024)*CYGNUM_FLASH_INTERLEAVE)
+# define FLASH_NUM_REGIONS ((4*1024*1024)/FLASH_BLOCK_SIZE)
+# define CYGNUM_FLASH_BASE_MASK (0xFFC00000u) // 4096kB devices
+# define CYGNUM_FLASH_WIDTH (16)
+# define CYGNUM_FLASH_BLANK (1)
+# define CYGNUM_FLASH_ID_MANUFACTURER FLASHWORD(0x00BF)
+# define CYGNUM_FLASH_ID_DEVICE FLASHWORD(0x2784)
+#endif
+#ifdef CYGPKG_DEVS_FLASH_SST_39VF3201
+# define FLASH_BLOCK_SIZE ((4*1024)*CYGNUM_FLASH_INTERLEAVE)
+# define FLASH_NUM_REGIONS ((4*1024*1024)/FLASH_BLOCK_SIZE)
+# define CYGNUM_FLASH_BASE_MASK (0xFFC00000u) // 4096kB devices
+# define CYGNUM_FLASH_WIDTH (16)
+# define CYGNUM_FLASH_BLANK (1)
+# define CYGNUM_FLASH_ID_MANUFACTURER FLASHWORD(0x00BF)
+# define CYGNUM_FLASH_ID_DEVICE FLASHWORD(0x235B)
+#endif
+#ifdef CYGPKG_DEVS_FLASH_SST_39VF3202
+# define FLASH_BLOCK_SIZE ((4*1024)*CYGNUM_FLASH_INTERLEAVE)
+# define FLASH_NUM_REGIONS ((4*1024*1024)/FLASH_BLOCK_SIZE)
+# define CYGNUM_FLASH_BASE_MASK (0xFFC00000u) // 4096kB devices
+# define CYGNUM_FLASH_WIDTH (16)
+# define CYGNUM_FLASH_BLANK (1)
+# define CYGNUM_FLASH_ID_MANUFACTURER FLASHWORD(0x00BF)
+# define CYGNUM_FLASH_ID_DEVICE FLASHWORD(0x235A)
+#endif
+
+#ifdef CYGPKG_DEVS_FLASH_SST_39VF6401
+# define FLASH_BLOCK_SIZE ((4*1024)*CYGNUM_FLASH_INTERLEAVE)
+# define FLASH_NUM_REGIONS ((8*1024*1024)/FLASH_BLOCK_SIZE)
+# define CYGNUM_FLASH_BASE_MASK (0xFF800000u) // 8184kB devices
+# define CYGNUM_FLASH_WIDTH (16)
+# define CYGNUM_FLASH_BLANK (1)
+# define CYGNUM_FLASH_ID_MANUFACTURER FLASHWORD(0x00BF)
+# define CYGNUM_FLASH_ID_DEVICE FLASHWORD(0x236B)
+#endif
+#ifdef CYGPKG_DEVS_FLASH_SST_39VF6402
+# define FLASH_BLOCK_SIZE ((4*1024)*CYGNUM_FLASH_INTERLEAVE)
+# define FLASH_NUM_REGIONS ((8*1024*1024)/FLASH_BLOCK_SIZE)
+# define CYGNUM_FLASH_BASE_MASK (0xFF800000u) // 8184kB devices
+# define CYGNUM_FLASH_WIDTH (16)
+# define CYGNUM_FLASH_BLANK (1)
+# define CYGNUM_FLASH_ID_MANUFACTURER FLASHWORD(0x00BF)
+# define CYGNUM_FLASH_ID_DEVICE FLASHWORD(0x236A)
+#endif
+
#define FLASH_DEVICE_SIZE (FLASH_BLOCK_SIZE*FLASH_NUM_REGIONS)
#define CYGNUM_FLASH_DEVICES (CYGNUM_FLASH_INTERLEAVE*CYGNUM_FLASH_SERIES)
{
int dir = I2C_READ, i;
unsigned long v;
- unsigned int dev_addr, dev_reg;
+ unsigned long dev_addr, dev_reg;
struct mxc_i2c_request rq;
if (g_i2c_nr == -1) {
return;
}
- if (!parse_num(*(&argv[1]), (unsigned long *)&dev_addr, &argv[1], ":")) {
+ if (!parse_num(argv[1], &dev_addr, &argv[1], ":")) {
diag_printf("Error: Invalid parameter %d\n", __LINE__);
return;
}
- if (!parse_num(*(&argv[2]), (unsigned long *)&dev_reg, &argv[2], ":")) {
+ if (!parse_num(argv[2], &dev_reg, &argv[2], ":")) {
diag_printf("Error: Invalid parameter %d\n", __LINE__);
return;
}
if (argc == 4) {
- if (!parse_num(*(&argv[3]), &v, &argv[3], ":")) {
+ if (!parse_num(argv[3], &v, &argv[3], ":")) {
diag_printf("Error: Invalid parameter\n");
return;
}
do_i2c_init
);
-static void do_i2c_init(int argc,char *argv[])
+static void do_i2c_init(int argc, char *argv[])
{
unsigned freq;
return;
}
- if (!parse_num(*(&argv[1]), (unsigned long *)&g_i2c_nr, &argv[1], ":")) {
+ if (!parse_num(argv[1], (unsigned long *)&g_i2c_nr, &argv[1], ":")) {
diag_printf("Error: Invalid parameter\n");
return;
}
}
diag_printf1("i2c max number is: %d\n", i2c_num - 1);
- if (!parse_num(*(&argv[2]), (unsigned long *)&freq, &argv[2], ":")) {
+ if (!parse_num(argv[2], (unsigned long *)&freq, &argv[2], ":")) {
diag_printf("Error: Invalid parameter\n");
return;
}
- if (!parse_num(*(&argv[3]), (unsigned long *)&g_dev_addr_width, &argv[3], ":")) {
+ if (!parse_num(argv[3], (unsigned long *)&g_dev_addr_width, &argv[3], ":")) {
diag_printf("Error: Invalid parameter\n");
return;
}
- if (!parse_num(*(&argv[4]), (unsigned long *)&g_dev_data_width, &argv[4], ":")) {
+ if (!parse_num(argv[4], (unsigned long *)&g_dev_data_width, &argv[4], ":")) {
diag_printf("Error: Invalid parameter\n");
return;
}
+2007-06-01 Jim Seymour <jim@cipher.com>
+
+ * src/at91_serial.c (at91_serial_DSR): Remove CYG_FAIL if receive
+ buffer fills up; eliminate compiler warning when setting "end"
+ pointer.
+
+2006-03-05 Oliver Munz <munz@speag.ch>
+
+ * src/at91_serial.c (at91_serial_ISR): Only call the DSR if there
+ is work to do.
+
+2006-02-28 Andrew Lunn <andrew.lunn@ascom.ch>
+ Oliver Munz <munz@speag.ch>
+
+ * src/at91_serial.c (at91_serial_config_port): Enable the DMA
+ if the control register exists.
+
+2006-02-19 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/at91_serial.c (at91_serial_lookup): Enable the peripheral
+ clock at lookup time to keep the power usage low.
+
2004-11-10 Sebastian Block <sebastianblock@gmx.net>
* src/at91_serial.c: Added third port
AT91_US_CR_RxENAB | AT91_US_CR_TxENAB | AT91_US_CR_RSTATUS | AT91_US_CR_STTTO
);
+ // Enable the DMA is the control register exists
+#ifdef AT91_US_PTCR
+ HAL_WRITE_UINT32(base + AT91_US_PTCR,
+ AT91_US_PTCR_RXTEN |
+ AT91_US_PTCR_TXTEN);
+#endif
+
if (new_config != &chan->config) {
chan->config = *new_config;
}
const char *name)
{
serial_channel * const chan = (serial_channel *) (*tab)->priv;
-
+
+#ifdef AT91_PMC_PCER
+ // Enable the peripheral clock to the device
+ at91_serial_info * const at91_chan = (at91_serial_info *)chan->dev_priv;
+ HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_PCER,
+ (1 << at91_chan->int_num));
+#endif
(chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices
return ENOERR;
}
at91_serial_info * const at91_chan = (at91_serial_info *) chan->dev_priv;
const CYG_ADDRWORD base = at91_chan->base;
CYG_WORD32 stat, mask;
-
+ cyg_uint32 retcode = 0;
+
HAL_READ_UINT32(base + AT91_US_CSR, stat);
HAL_READ_UINT32(base + AT91_US_IMR, mask);
stat &= mask;
(CYG_ADDRESS) at91_chan->rcv_buffer[at91_chan->curbuf]
+ at91_chan->rcv_chunk_size + RCVBUF_EXTRA - x
);
+ retcode = CYG_ISR_CALL_DSR;
}
- if (stat & (AT91_US_IER_TxRDY | AT91_US_IER_ENDTX))
+ if (stat & (AT91_US_IER_TxRDY | AT91_US_IER_ENDTX)) {
HAL_WRITE_UINT32(base + AT91_US_IDR, AT91_US_IER_TxRDY | AT91_US_IER_ENDTX);
-
+ retcode = CYG_ISR_CALL_DSR;
+ }
at91_chan->stat |= stat;
+
cyg_drv_interrupt_acknowledge(vector);
- return CYG_ISR_CALL_DSR;
+ return retcode;
}
// Serial I/O - high level interrupt handler (DSR)
if (stat & (AT91_US_IER_ENDRX | AT91_US_IER_TIMEOUT)) {
const cyg_uint8 cb = at91_chan->curbuf, nb = cb ^ 0x01;
const cyg_uint8 * p = at91_chan->rcv_buffer[cb], * end;
+ cyg_uint32 temp_word;
at91_chan->curbuf = nb;
HAL_WRITE_UINT32(base + AT91_US_RCR, 0);
- HAL_READ_UINT32(base + AT91_US_RPR, (CYG_ADDRESS) end);
+ HAL_READ_UINT32(base + AT91_US_RPR, temp_word);
+ end = (const cyg_uint8 *)temp_word;
HAL_WRITE_UINT32(base + AT91_US_RTO, RCV_TIMEOUT);
HAL_WRITE_UINT32(base + AT91_US_CR, AT91_US_CR_RSTATUS | AT91_US_CR_STTTO);
HAL_WRITE_UINT32(base + AT91_US_RPR, (CYG_ADDRESS) at91_chan->rcv_buffer[nb]);
default:
// Buffer full or unknown error, can't do anything about it
// Discard data
- CYG_FAIL("Serial receiver buffer overflow");
p = end;
break;
}
+2007-06-22 Alexander Aganichev <aaganichev@gmail.com>
+
+ * cdl/ser_arm_lpc2xxx.cdl:
+ Added requirement of
+ CYGPKG_IO_SERIAL_GENERIC_16X5X_XMIT_REQUIRE_PRIME option.
+
2004-11-15 Jani Monoses <jani@iv.ro>
* include/arm_lpc2xxx_ser.inl:
puts $::cdl_header "#define CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP 4"
}
+ requires { CYGPKG_IO_SERIAL_GENERIC_16X5X_XMIT_REQUIRE_PRIME == "1" }
define_proc {
puts $::cdl_system_header "/***** serial driver proc output start *****/"
+2008-07-08 Uwe Kindler <uwe_kindler@web.de>
+
+ * cdl/ser_generic_16x5x.cdl
+ (CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO): New interface
+ for devices that support per channel interrupt priorities.
+
+ * src/ser_16x5x.c Added int_prio to pc_serial_info type.
+ serial_config_port(): uses macro
+ CYG_IO_SERIAL_GENERIC_16X5X_CHAN_BAUD_GENERATOR() to get the baud
+ devisor from platform if device suppports per channel baudrate
+ clocks, pc_serial_init(): Use interrupt priority from int_prio
+ data field if device implements
+ CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO
+
+2007-06-22 Alexander Aganichev <aaganichev@gmail.com>
+
+ * cdl/ser_generic_16x5x.cdl
+ (CYGPKG_IO_SERIAL_GENERIC_16X5X_XMIT_REQUIRE_PRIME): New option.
+
+ * src/ser_16x5x.c (pc_serial_start_xmit): Allow platform to define
+ CYGPKG_IO_SERIAL_GENERIC_16X5X_XMIT_REQUIRE_PRIME if enabling THRE
+ interrupt does not generate interrupt unless bytes are posted to the
+ FIFO.
+
+2006-11-27 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * src/ser_16x5x.c (serial_config_port): Add
+ CYGPRI_IO_SERIAL_GENERIC_16X5X_PLF_INIT_HOOK
+ in case devices need extra initialization.
+
+2006-02-07 Daniel Néri <daniel.neri@sigicom.se>
+
+ * cdl/ser_generic_16x5x.cdl
+ (CYGNUM_IO_SERIAL_GENERIC_16X5X_FIFO_TX_SIZE): New option.
+
+ * src/ser_16x5x.c (serial_config_port, pc_serial_putc,
+ pc_serial_DSR): At TX interrupt, write up to
+ CYGNUM_IO_SERIAL_GENERIC_16X5X_FIFO_TX_SIZE bytes to the transmit
+ FIFO. This makes better use of the FIFO, since the LSR_THE flag
+ resets when the FIFO is non-empty (not when it's full, as this
+ code previously assumed).
+
2003-09-19 Gary Thomas <gary@mlbassoc.com>
* src/ser_16x5x.c (pc_serial_init):
- Allow platform to define CYG_IO_SERIAL_GENERIC_16X5X_BAUD_GENERATOR if the
- baud rate clock (values) cannot be known at compile time. In this case,
- the baud rate generator values are provided by platform specific code,
- computed when the device is first initialized.
+ Allow platform to define CYG_IO_SERIAL_GENERIC_16X5X_BAUD_GENERATOR
+ if the baud rate clock (values) cannot be known at compile time. In
+ this case, the baud rate generator values are provided by platform
+ specific code, computed when the device is first initialized.
2003-07-16 Jonathan Larmour <jifl@eCosCentric.com>
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2006 eCosCentric Limited.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
puts $::cdl_header "#include <pkgconf/system.h>";
puts $::cdl_header "#include CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG";
}
+
+ cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO {
+ display "Per channel interrupt priority support"
+ flavor bool
+ description "
+ A platform should implement this interface if it supports
+ per channel interrupt priorities. If a platform implements
+ this interface it needs to provide an interrupt priority
+ value for each UART channel it supports."
+ }
+
+ cdl_option CYGPKG_IO_SERIAL_GENERIC_16X5X_XMIT_REQUIRE_PRIME {
+ display "Transmission require priming"
+ flavor bool
+ default_value 0
+ description "
+ This option should be switched on when enabling THRE interrupt
+ does not generate interrupt unless bytes are posted to the FIFO."
+ }
cdl_component CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO {
display "16x5x FIFO support"
the RX interrupt occurs when a FIFO is used. (16550 and
above only), this may be after 1, 4, 8 or 14 characters."
}
+
+ cdl_option CYGNUM_IO_SERIAL_GENERIC_16X5X_FIFO_TX_SIZE {
+ display "16x5x TX FIFO size"
+ flavor data
+ default_value 16
+ description "
+ Configures the maximum number of bytes written to the
+ 16x5x UART transmit FIFO when the TX interrupt occurs."
+ }
}
cdl_component CYGPKG_IO_SERIAL_GENERIC_16X5X_OPTIONS {
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2003 Gary Thomas
+// Copyright (C) 2006 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
typedef struct pc_serial_info {
cyg_addrword_t base;
int int_num;
+#ifdef CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO
+ int int_prio;
+#endif // CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO
cyg_interrupt serial_interrupt;
cyg_handle_t serial_interrupt_handle;
#ifdef CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO
s16550,
s16550a
} deviceType;
+ unsigned tx_fifo_size;
+ volatile unsigned tx_fifo_avail;
#endif
} pc_serial_info;
{
pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv;
cyg_addrword_t base = ser_chan->base;
+ //
+ // If the device supports a dynamic per channel baudrate generator
+ // then we call the CYG_IO_SERIAL_GENERIC_16X5X_CHAN_BAUD_GENERATOR()
+ // macro to get the baud divisor. The macro takes the serial channel data
+ // pointer and the baudrate as parameters and returns the baud divisior
+ //
+#ifdef CYG_IO_SERIAL_GENERIC_16X5X_CHAN_BAUD_GENERATOR
+ unsigned short baud_divisor = CYG_IO_SERIAL_GENERIC_16X5X_CHAN_BAUD_GENERATOR(ser_chan, new_config->baud);
+#else
unsigned short baud_divisor = select_baud[new_config->baud];
+#endif
unsigned char _lcr, _ier;
if (baud_divisor == 0) return false; // Invalid configuration
_fcr_thresh=FCR_RT14; break;
}
_fcr_thresh|=FCR_FE|FCR_CRF|FCR_CTF;
- HAL_WRITE_UINT8(base+REG_fcr, _fcr_thresh); // Enable and clear FIFO
+ ser_chan->tx_fifo_size =
+ CYGNUM_IO_SERIAL_GENERIC_16X5X_FIFO_TX_SIZE;
+ // Enable and clear FIFO
+ HAL_WRITE_UINT8(base+REG_fcr, _fcr_thresh);
}
- else
+ else {
+ ser_chan->tx_fifo_size = 1;
HAL_WRITE_UINT8(base+REG_fcr, 0); // make sure it's disabled
+ }
+
+ ser_chan->tx_fifo_avail = ser_chan->tx_fifo_size;
#endif
if (chan->out_cbuf.len != 0) {
_ier = IER_RCV;
#endif
HAL_WRITE_UINT8(base+REG_ier, _ier);
+#ifdef CYGPRI_IO_SERIAL_GENERIC_16X5X_PLF_INIT_HOOK
+ CYGPRI_IO_SERIAL_GENERIC_16X5X_PLF_INIT_HOOK( ser_chan, new_config );
+#endif
+
if (new_config != &chan->config) {
chan->config = *new_config;
}
#endif
// Really only required for interrupt driven devices
(chan->callbacks->serial_init)(chan);
-
+ //
+ // If the device supports per channel interrupt priorities then
+ // we take the priority from the serial channel data. If it does
+ // not support per channel interrupt priority we fall back to
+ // the old method and use CYG_IO_SERIAL_GENERIC_16X5X_INT_PRIORITY
+ // to define the priority
+ //
+#ifdef CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO
+ cyg_priority_t intprio = ser_chan->int_prio;
+#else
+ cyg_priority_t intprio = CYG_IO_SERIAL_GENERIC_16X5X_INT_PRIORITY;
+#endif // CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO
if (chan->out_cbuf.len != 0) {
cyg_drv_interrupt_create(ser_chan->int_num,
- CYG_IO_SERIAL_GENERIC_16X5X_INT_PRIORITY,
+ intprio,
(cyg_addrword_t)chan,
pc_serial_ISR,
pc_serial_DSR,
static bool
pc_serial_putc(serial_channel *chan, unsigned char c)
{
+#ifndef CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO
cyg_uint8 _lsr;
+#endif
pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv;
cyg_addrword_t base = ser_chan->base;
+#ifdef CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO
+ if (ser_chan->tx_fifo_avail > 0) {
+ HAL_WRITE_UINT8(base+REG_thr, c);
+ --ser_chan->tx_fifo_avail;
+ return true;
+ }
+#else
HAL_READ_UINT8(base+REG_lsr, _lsr);
if (_lsr & LSR_THE) {
// Transmit buffer is empty
HAL_WRITE_UINT8(base+REG_thr, c);
return true;
}
+#endif
// No space
return false;
}
HAL_READ_UINT8(base+REG_ier, _ier);
_ier |= IER_XMT; // Enable xmit interrupt
HAL_WRITE_UINT8(base+REG_ier, _ier);
+#ifdef CYGPKG_IO_SERIAL_GENERIC_16X5X_XMIT_REQUIRE_PRIME
+ (chan->callbacks->xmt_char)(chan);
+#endif
}
// Disable the transmitter on the device
break;
}
case ISR_Tx:
+#ifdef CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO
+ ser_chan->tx_fifo_avail = ser_chan->tx_fifo_size;
+#endif
(chan->callbacks->xmt_char)(chan);
break;
+2006-01-27 Will Wagner <willw@carallon.com>
+
+ * src/quicc_smc_serial.h: Removed unused structure
+ * src/quicc_smc_serial.c(quicc_smc_serial_config_port): Corrected CLEN in SMCMR
+ * src/quicc_smc_serial.c(quicc_smc_serial_DSR & quicc_scc_serial_DSR): Better handling of frame and parity errors
+
2004-05-10 Robert Chenault <robertchenault@yahoo.com>
* src/quicc_smc_serial.h: Added two casts of (int) on
ctl->smc_smcmr = QUICC_SMCMR_UART; // Disabled, UART mode
HAL_IO_BARRIER(); // Inforce I/O ordering
// Disable port interrupts while changing hardware
- _lcr = smc_select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] |
+ _lcr = QUICC_SMCMR_CLEN(new_config->word_length + ((new_config->parity == CYGNUM_SERIAL_PARITY_NONE)? 0: 1) + ((new_config->stop == CYGNUM_SERIAL_STOP_2)? 2: 1)) |
smc_select_stop_bits[new_config->stop] |
smc_select_parity[new_config->parity];
// Stop transmitter while changing baud rate
while (ctl->smc_smce & QUICC_SMCE_RX) {
// Receive interrupt
ctl->smc_smce = QUICC_SMCE_RX; // Reset interrupt state;
- rxlast = (struct cp_bufdesc *) (
- (char *)eppc_base() + pram->rbptr );
+ rxlast = (struct cp_bufdesc *) ((char *)eppc_base() + pram->rbptr);
while (rxbd != rxlast) {
if ((rxbd->ctrl & QUICC_BD_CTL_Ready) == 0) {
- for (i = 0; i < rxbd->length; i++) {
- (chan->callbacks->rcv_char)(chan, rxbd->buffer[i]);
+ if((rxbd->ctrl & (QUICC_BD_CTL_Frame | QUICC_BD_CTL_Parity)) == 0) {
+ for (i = 0; i < rxbd->length; i++) {
+ (chan->callbacks->rcv_char)(chan, rxbd->buffer[i]);
+ }
+ } else {
+ // is this necessary?
+ rxbd->ctrl &= QUICC_BD_CTL_MASK;
+ // should we report the error?
}
// Note: the MBX860 does not seem to snoop/invalidate the data cache properly!
HAL_DCACHE_IS_ENABLED(cache_state);
rxlast = (struct cp_bufdesc *) ((char *)eppc_base() + pram->rbptr);
while (rxbd != rxlast) {
if ((rxbd->ctrl & QUICC_BD_CTL_Ready) == 0) {
- for (i = 0; i < rxbd->length; i++) {
- (chan->callbacks->rcv_char)(chan, rxbd->buffer[i]);
+ if((rxbd->ctrl & (QUICC_BD_CTL_Frame | QUICC_BD_CTL_Parity)) == 0) {
+ for (i = 0; i < rxbd->length; i++) {
+ (chan->callbacks->rcv_char)(chan, rxbd->buffer[i]);
+ }
+ } else {
+ // is this necessary?
+ rxbd->ctrl &= QUICC_BD_CTL_MASK;
+ // should we report the error?
}
// Note: the MBX860 does not seem to snoop/invalidate the data cache properly!
HAL_DCACHE_IS_ENABLED(cache_state);
#include <cyg/hal/quicc/ppc8xx.h> // QUICC structure definitions
-static unsigned int smc_select_word_length[] = {
- QUICC_SMCMR_CLEN(5), // 5 bits / word (char)
- QUICC_SMCMR_CLEN(6),
- QUICC_SMCMR_CLEN(7),
- QUICC_SMCMR_CLEN(8)
-};
-
static unsigned int smc_select_stop_bits[] = {
0,
QUICC_SMCMR_SB(1), // 1 stop bit
+2006-09-27 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/spi_at91.c (spi_at91_transaction_begin): Don't use #ifdef
+ inside a macro invocation. The compiler throws a wobbly.
+
+2006-09-07 John Eigelaar <jeigelaar@mweb.co.za>
+
+ * src/spi_at91.c: Fixed the chip select functions.
+ Changed the Mode Register setup as to disable the Mode Failure
+ Detaction for variants that support it. The Mode Failure Detection
+ breaks because NPCS0 is not connected, we are using GPIO, and is
+ thus floating.
+
+2006-06-01 John Eigelaar <jeigelaar@mweb.co.za>
+
+ * src/spi_at91.c:
+ * cdl/spi_at91.cdl:
+ * include/spi_at91.h: Generalize so that multiple SPI
+ busses can be driven.
+
+2006-05-19 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/spi_at91.c: Use the AT91 GPIO/PIO macros to aid
+ portability between different AT91 device.
+
2004-11-11 Sebastian Block <sebastianblock@gmx.net>
* src/spi_at91.c: Fixed negation of the chip select signal when
compile spi_at91.c
compile -library=libextras.a spi_at91_init.cxx
- cdl_option CYGHWR_DEVS_SPI_ARM_AT91_PCSDEC {
- display "Support 4 to 16 decoder of chip select signals."
+
+ cdl_option CYGHWR_DEVS_SPI_ARM_AT91_BUS0 {
+ display "Enable support for SPI bus 0"
+ flavor bool
+ default_value 1
+ description "Enable this option to add support for the first
+ SPI peripheral. The most AT91 devices only have one bus"
+ }
+
+ cdl_interface CYGINT_DEVS_SPI_ARM_AT91_HAS_BUS1 {
+ description "
+ This interface is implemented by HALs for devices which have
+ the second SPI bus controller."
+ }
+
+
+ cdl_option CYGHWR_DEVS_SPI_ARM_AT91_BUS1 {
+ active_if CYGINT_DEVS_SPI_ARM_AT_HAS_BUS1
+ display "Enable support for SPI bus 1"
flavor bool
default_value 0
- description "Enable this option if SPI peripheral chip
- selects are connected through an 4 to 16 decoder."
+ description "Enable this option to add support for the second
+ SPI peripheral. The most AT91 devices only have one bus"
+ }
+
+ cdl_component CYGPKG_DEVS_SPI_ARM_AT91_BUS0_CFG {
+ active_if CYGHWR_DEVS_SPI_ARM_AT91_BUS0
+ display "Configuration options for SPI Bus 0"
+ flavor none
+ description "This is the configuration options for SPI Bus 0"
+
+ cdl_option CYGHWR_DEVS_SPI_ARM_AT91_BUS0_PCSDEC {
+ display "Support 4 to 16 decoder of chip select signals."
+ flavor bool
+ default_value 0
+ description "Enable this option if SPI peripheral chip
+ selects are connected through an 4 to 16 decoder."
+ }
+
+ cdl_option CYGDAT_DEVS_SPI_ARM_AT91_BUS0_NPCS0 {
+ display "PIO-Pin used for NPSC0"
+ flavor data
+ default_value {"AT91_SPI_NPCS0"}
+ description "Any GPIO pin is able to be used as the SPI driver
+ uses GPIO to control the chip selects. Specify the pin
+ as \"AT91_GPIO_PA13\" or \"AT91_GPIO_PB5\" etc. Specify
+ \"NONE\" if this chip select is to be disabled"
+ }
+
+ cdl_option CYGDAT_DEVS_SPI_ARM_AT91_BUS0_NPCS1 {
+ display "PIO-Pin used for NPSC1"
+ flavor data
+ default_value {"AT91_SPI_NPCS1"}
+ description "Any GPIO pin is able to be used as the SPI driver
+ uses GPIO to control the chip selects. Specify the pin
+ as \"AT91_GPIO_PA13\" or \"AT91_GPIO_PB5\" etc. Specify
+ \"NONE\" if this chip select is to be disabled"
+ }
+ cdl_option CYGDAT_DEVS_SPI_ARM_AT91_BUS0_NPCS2 {
+ display "PIO-Pin used for NPSC2"
+ flavor data
+ default_value {"AT91_SPI_NPCS2"}
+ description "Any GPIO pin is able to be used as the SPI driver
+ uses GPIO to control the chip selects. Specify the pin
+ as \"AT91_GPIO_PA13\" or \"AT91_GPIO_PB5\" etc. Specify
+ \"NONE\" if this chip select is to be disabled"
+ }
+ cdl_option CYGDAT_DEVS_SPI_ARM_AT91_BUS0_NPCS3 {
+ display "PIO-Pin used for NPSC3"
+ flavor data
+ default_value {"AT91_SPI_NPCS3"}
+ description "Any GPIO pin is able to be used as the SPI driver
+ uses GPIO to control the chip selects. Specify the pin
+ as \"AT91_GPIO_PA13\" or \"AT91_GPIO_PB5\" etc. Specify
+ \"NONE\" if this chip select is to be disabled"
+ }
+
}
+
+ cdl_component CYGPKG_DEVS_SPI_ARM_AT91_BUS1_CFG {
+ active_if CYGHWR_DEVS_SPI_ARM_AT91_BUS1
+ display "Configuration options for SPI Bus 1"
+ flavor none
+ description "This is the configuration options for SPI Bus 1"
+
+ cdl_option CYGHWR_DEVS_SPI_ARM_AT91_BUS1_PCSDEC {
+ display "Support 4 to 16 decoder of chip select signals."
+ flavor bool
+ default_value 0
+ description "Enable this option if SPI peripheral chip
+ selects are connected through an 4 to 16 decoder."
+ }
+
+ cdl_option CYGDAT_DEVS_SPI_ARM_AT91_BUS1_NPCS0 {
+ display "PIO-Pin used for NPSC0"
+ flavor data
+ default_value {"AT91_SPI1_NPCS0"}
+ description "Any GPIO pin is able to be used as the SPI driver
+ uses GPIO to control the chip selects. Specify the pin
+ as \"AT91_GPIO_PA13\" or \"AT91_GPIO_PB5\" etc. Specify
+ \"NONE\" if this chip select is to be disabled"
+ }
+
+ cdl_option CYGDAT_DEVS_SPI_ARM_AT91_BUS1_NPCS1 {
+ display "PIO-Pin used for NPSC1"
+ flavor data
+ default_value {"AT91_SPI1_NPCS1"}
+ description "Any GPIO pin is able to be used as the SPI driver
+ uses GPIO to control the chip selects. Specify the pin
+ as \"AT91_GPIO_PA13\" or \"AT91_GPIO_PB5\" etc. Specify
+ \"NONE\" if this chip select is to be disabled"
+ }
+ cdl_option CYGDAT_DEVS_SPI_ARM_AT91_BUS1_NPCS2 {
+ display "PIO-Pin used for NPSC2"
+ flavor data
+ default_value {"AT91_SPI1_NPCS2"}
+ description "Any GPIO pin is able to be used as the SPI driver
+ uses GPIO to control the chip selects. Specify the pin
+ as \"AT91_GPIO_PA13\" or \"AT91_GPIO_PB5\" etc. Specify
+ \"NONE\" if this chip select is to be disabled"
+ }
+ cdl_option CYGDAT_DEVS_SPI_ARM_AT91_BUS1_NPCS3 {
+ display "PIO-Pin used for NPSC3"
+ flavor data
+ default_value {"AT91_SPI1_NPCS3"}
+ description "Any GPIO pin is able to be used as the SPI driver
+ uses GPIO to control the chip selects. Specify the pin
+ as \"AT91_GPIO_PA13\" or \"AT91_GPIO_PB5\" etc. Specify
+ \"NONE\" if this chip select is to be disabled"
+ }
+
+ }
+
cdl_component CYGPKG_DEVS_SPI_ARM_AT91_OPTIONS {
display "Atmel AT91 SPI driver build options"
cyg_drv_mutex_t transfer_mx; // Transfer mutex
cyg_drv_cond_t transfer_cond; // Transfer condition
cyg_bool transfer_end; // Transfer end flag
- cyg_bool cs_up; // Chip Select up flag
+ cyg_bool cs_up; // Chip Select up flag
+ cyg_vector_t interrupt_number; // SPI Interrupt Number
+ cyg_addrword_t base; // Base Address of the SPI peripheral
+ cyg_uint8 cs_en[4]; // The Configurations state for the CS
+ cyg_uint32 cs_gpio[4]; // The GPIO Configurations for the CS
} cyg_spi_at91_bus_t;
//-----------------------------------------------------------------------------
} cyg_spi_at91_device_t;
//-----------------------------------------------------------------------------
-// AT91 SPI exported bus
+// AT91 SPI exported busses
-externC cyg_spi_at91_bus_t cyg_spi_at91_bus;
+/* For backwards compatability */
+#define cyg_spi_at91_bus cyg_spi_at91_bus0
+
+externC cyg_spi_at91_bus_t cyg_spi_at91_bus0;
+externC cyg_spi_at91_bus_t cyg_spi_at91_bus1;
//-----------------------------------------------------------------------------
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
#include <cyg/error/codes.h>
// -------------------------------------------------------------------------
+static void spi_at91_init_bus(cyg_spi_at91_bus_t * bus);
static cyg_uint32 spi_at91_ISR(cyg_vector_t vector, cyg_addrword_t data);
// -------------------------------------------------------------------------
// AT91 SPI BUS
-cyg_spi_at91_bus_t cyg_spi_at91_bus = {
+#ifdef CYGHWR_DEVS_SPI_ARM_AT91_BUS0
+cyg_spi_at91_bus_t cyg_spi_at91_bus0 = {
.spi_bus.spi_transaction_begin = spi_at91_transaction_begin,
.spi_bus.spi_transaction_transfer = spi_at91_transaction_transfer,
.spi_bus.spi_transaction_tick = spi_at91_transaction_tick,
.spi_bus.spi_transaction_end = spi_at91_transaction_end,
.spi_bus.spi_get_config = spi_at91_get_config,
- .spi_bus.spi_set_config = spi_at91_set_config
+ .spi_bus.spi_set_config = spi_at91_set_config,
+ .interrupt_number = CYGNUM_HAL_INTERRUPT_SPI,
+ .base = AT91_SPI,
+#ifndef CYGDAT_DEVS_SPI_ARM_AT91_BUS0_NPCS0_NONE
+ .cs_en[0] = true,
+ .cs_gpio[0] = CYGDAT_DEVS_SPI_ARM_AT91_BUS0_NPCS0,
+#else
+ .cs_en[0] = false,
+#endif
+#ifndef CYGDAT_DEVS_SPI_ARM_AT91_BUS0_NPCS1_NONE
+ .cs_en[1] = true,
+ .cs_gpio[1] = CYGDAT_DEVS_SPI_ARM_AT91_BUS0_NPCS1,
+#else
+ .cs_en[1] = false,
+#endif
+#ifndef CYGDAT_DEVS_SPI_ARM_AT91_BUS0_NPCS2_NONE
+ .cs_en[2] = true,
+ .cs_gpio[2] = CYGDAT_DEVS_SPI_ARM_AT91_BUS0_NPCS2,
+#else
+ .cs_en[2] = false,
+#endif
+#ifndef CYGDAT_DEVS_SPI_ARM_AT91_BUS0_NPCS3_NONE
+ .cs_en[3] = true,
+ .cs_gpio[3] = CYGDAT_DEVS_SPI_ARM_AT91_BUS0_NPCS3,
+#else
+ .cs_en[3] = false,
+#endif
};
CYG_SPI_DEFINE_BUS_TABLE(cyg_spi_at91_device_t, 0);
+#endif
+#ifdef CYGHWR_DEVS_SPI_ARM_AT91_BUS1
+cyg_spi_at91_bus_t cyg_spi_at91_bus1 = {
+ .spi_bus.spi_transaction_begin = spi_at91_transaction_begin,
+ .spi_bus.spi_transaction_transfer = spi_at91_transaction_transfer,
+ .spi_bus.spi_transaction_tick = spi_at91_transaction_tick,
+ .spi_bus.spi_transaction_end = spi_at91_transaction_end,
+ .spi_bus.spi_get_config = spi_at91_get_config,
+ .spi_bus.spi_set_config = spi_at91_set_config,
+ .interrupt_number = CYGNUM_HAL_INTERRUPT_SPI1,
+ .base = AT91_SPI1,
+#ifndef CYGDAT_DEVS_SPI_ARM_AT91_BUS1_NPCS0_NONE
+ .cs_en[0] = true,
+ .cs_gpio[0] = CYGDAT_DEVS_SPI_ARM_AT91_BUS1_NPCS0,
+#else
+ .cs_en[0] = false,
+#endif
+#ifndef CYGDAT_DEVS_SPI_ARM_AT91_BUS1_NPCS1_NONE
+ .cs_en[1] = true,
+ .cs_gpio[1] = CYGDAT_DEVS_SPI_ARM_AT91_BUS1_NPCS1,
+#else
+ .cs_en[1] = false,
+#endif
+#ifndef CYGDAT_DEVS_SPI_ARM_AT91_BUS1_NPCS2_NONE
+ .cs_en[2] = true,
+ .cs_gpio[2] = CYGDAT_DEVS_SPI_ARM_AT91_BUS1_NPCS2,
+#else
+ .cs_en[2] = false,
+#endif
+#ifndef CYGDAT_DEVS_SPI_ARM_AT91_BUS1_NPCS3_NONE
+ .cs_en[3] = true,
+ .cs_gpio[3] = CYGDAT_DEVS_SPI_ARM_AT91_BUS1_NPCS3,
+#else
+ .cs_en[3] = false,
+#endif
+};
+CYG_SPI_DEFINE_BUS_TABLE(cyg_spi_at91_device_t, 1);
+#endif
// -------------------------------------------------------------------------
void
cyg_spi_at91_bus_init(void)
{
+
+#ifdef CYGHWR_DEVS_SPI_ARM_AT91_BUS0
+ // NOTE: here we let the SPI controller control
+ // the data in, out and clock signals, but
+ // we need to handle the chip selects manually
+ // in order to achieve better chip select control
+ // in between transactions.
+
+ // Put SPI MISO, MOIS and SPCK pins into peripheral mode
+ HAL_ARM_AT91_PIO_CFG(AT91_SPI_SPCK);
+ HAL_ARM_AT91_PIO_CFG(AT91_SPI_MISO);
+ HAL_ARM_AT91_PIO_CFG(AT91_SPI_MOIS);
+ spi_at91_init_bus(&cyg_spi_at91_bus0);
+#endif
+#ifdef CYGHWR_DEVS_SPI_ARM_AT91_BUS1
+ // NOTE: here we let the SPI controller control
+ // the data in, out and clock signals, but
+ // we need to handle the chip selects manually
+ // in order to achieve better chip select control
+ // in between transactions.
+
+ // Put SPI MISO, MOIS and SPCK pins into peripheral mode
+ HAL_ARM_AT91_PIO_CFG(AT91_SPI1_SPCK);
+ HAL_ARM_AT91_PIO_CFG(AT91_SPI1_MISO);
+ HAL_ARM_AT91_PIO_CFG(AT91_SPI1_MOSI);
+ spi_at91_init_bus(&cyg_spi_at91_bus1);
+#endif
+}
+
+// -------------------------------------------------------------------------
+
+static void spi_at91_init_bus(cyg_spi_at91_bus_t * spi_bus)
+{
+ cyg_uint32 ctr;
// Create and attach SPI interrupt object
- cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_SPI,
+ cyg_drv_interrupt_create(spi_bus->interrupt_number,
4,
- (cyg_addrword_t)&cyg_spi_at91_bus,
+ (cyg_addrword_t)spi_bus,
spi_at91_ISR,
spi_at91_DSR,
- &cyg_spi_at91_bus.spi_interrupt_handle,
- &cyg_spi_at91_bus.spi_interrupt);
+ &spi_bus->spi_interrupt_handle,
+ &spi_bus->spi_interrupt);
- cyg_drv_interrupt_attach(cyg_spi_at91_bus.spi_interrupt_handle);
+ cyg_drv_interrupt_attach(spi_bus->spi_interrupt_handle);
// Init transfer mutex and condition
- cyg_drv_mutex_init(&cyg_spi_at91_bus.transfer_mx);
- cyg_drv_cond_init(&cyg_spi_at91_bus.transfer_cond,
- &cyg_spi_at91_bus.transfer_mx);
+ cyg_drv_mutex_init(&spi_bus->transfer_mx);
+ cyg_drv_cond_init(&spi_bus->transfer_cond,
+ &spi_bus->transfer_mx);
// Init flags
- cyg_spi_at91_bus.transfer_end = true;
- cyg_spi_at91_bus.cs_up = false;
+ spi_bus->transfer_end = true;
+ spi_bus->cs_up = false;
// Soft reset the SPI controller
- HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_CR, AT91_SPI_CR_SWRST);
+ HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_CR, AT91_SPI_CR_SWRST);
// Configure SPI pins
- // NOTE: here we let the SPI controller control
- // the data in, out and clock signals, but
- // we need to handle the chip selects manually
- // in order to achieve better chip select control
- // inbetween transactions.
-
- // Put SPI MISO, MOIS and SPCK pins into peripheral mode
- HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_PDR, AT91_PIO_PSR_SPCK |
- AT91_PIO_PSR_MISO |
- AT91_PIO_PSR_MOIS);
-
- // Put SPI chip select pins in IO output mode
- HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_SODR, AT91_SPI_PIO_NPCS(0x0F));
- HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_PER, AT91_SPI_PIO_NPCS(0x0F));
- HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_OER, AT91_SPI_PIO_NPCS(0x0F));
+ // Put SPI chip select pins in IO output mode
+ for(ctr = 0;ctr<4;ctr++)
+ {
+ if(spi_bus->cs_en[ctr])
+ {
+ HAL_ARM_AT91_GPIO_CFG_DIRECTION(spi_bus->cs_gpio[ctr],AT91_PIN_OUT);
+ }
+ }
// Call upper layer bus init
- CYG_SPI_BUS_COMMON_INIT(&cyg_spi_at91_bus.spi_bus);
+ CYG_SPI_BUS_COMMON_INIT(&spi_bus->spi_bus);
}
-// -------------------------------------------------------------------------
-
static cyg_uint32
spi_at91_ISR(cyg_vector_t vector, cyg_addrword_t data)
{
cyg_uint32 stat;
-
+ cyg_spi_at91_bus_t * spi_bus = (cyg_spi_at91_bus_t *)data;
// Read the status register and disable
// the SPI int events that have occoured
- HAL_READ_UINT32(AT91_SPI+AT91_SPI_SR, stat);
- HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_IDR, stat);
+ HAL_READ_UINT32(spi_bus->base+AT91_SPI_SR, stat);
+ HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_IDR, stat);
cyg_drv_interrupt_mask(vector);
cyg_drv_interrupt_acknowledge(vector);
// Read the status register and
// check for transfer completition
- HAL_READ_UINT32(AT91_SPI+AT91_SPI_SR, stat);
+ HAL_READ_UINT32(spi_bus->base+AT91_SPI_SR, stat);
if((stat & AT91_SPI_SR_ENDRX) && (stat & AT91_SPI_SR_ENDTX))
{
return res;
}
+static void
+spi_at91_set_npcs(cyg_spi_at91_bus_t *spi_bus,int val)
+{
+ cyg_uint32 ctr;
+ for(ctr=0;ctr<4;ctr++)
+ {
+ if(spi_bus->cs_en[ctr])
+ {
+ HAL_ARM_AT91_GPIO_PUT(spi_bus->cs_gpio[ctr], (val & (1<<ctr)));
+ }
+ }
+}
+
static void
spi_at91_start_transfer(cyg_spi_at91_device_t *dev)
{
// Raise CS
#ifdef CYGHWR_DEVS_SPI_ARM_AT91_PCSDEC
- HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_CODR,
- AT91_SPI_PIO_NPCS(~dev->dev_num));
+ spi_at91_set_npcs(spi_bus,~dev->dev_num);
#else
- HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_CODR,
- AT91_SPI_PIO_NPCS(1<<dev->dev_num));
+ spi_at91_set_npcs(spi_bus,~(1<<dev->dev_num));
#endif
CYGACC_CALL_IF_DELAY_US(dev->cs_up_udly);
// Drop CS
CYGACC_CALL_IF_DELAY_US(dev->cs_dw_udly);
- HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_SODR, AT91_SPI_PIO_NPCS(0x0F));
+ spi_at91_set_npcs(spi_bus,0x0F);
spi_bus->cs_up = false;
}
// Set rx buf pointer and counter
if (NULL != rx_data)
{
- HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_RPR, (cyg_uint32)rx_data);
- HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_RCR, (cyg_uint32)tr_count);
+ HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_RPR, (cyg_uint32)rx_data);
+ HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_RCR, (cyg_uint32)tr_count);
}
// Set tx buf pointer and counter
- HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_TPR, (cyg_uint32)tx_data);
- HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_TCR, (cyg_uint32)tr_count);
+ HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_TPR, (cyg_uint32)tx_data);
+ HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_TCR, (cyg_uint32)tr_count);
+#ifdef AT91_SPI_PTCR
+ HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_PTCR,
+ AT91_SPI_PTCR_RXTEN | AT91_SPI_PTCR_TXTEN);
+#endif
// Enable the SPI int events we are interested in
- HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_IER, AT91_SPI_SR_ENDRX |
- AT91_SPI_SR_ENDTX);
+ HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_IER,
+ AT91_SPI_SR_ENDRX | AT91_SPI_SR_ENDTX);
cyg_drv_mutex_lock(&spi_bus->transfer_mx);
{
spi_bus->transfer_end = false;
// Unmask the SPI int
- cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_SPI);
+ cyg_drv_interrupt_unmask(spi_bus->interrupt_number);
// Wait for its completition
cyg_drv_dsr_lock();
CYGACC_CALL_IF_DELAY_US(val > 1 ? val : 1);
// Clear the rx data reg
- HAL_READ_UINT32(AT91_SPI+AT91_SPI_RDR, val);
+ HAL_READ_UINT32(spi_bus->base+AT91_SPI_RDR, val);
}
// Adjust running variables
cyg_uint8 *rx_data)
{
cyg_uint32 val;
+ cyg_spi_at91_bus_t *spi_bus = (cyg_spi_at91_bus_t *)dev->spi_device.spi_bus;
// Transmit and receive byte by byte
while (count-- > 0)
// Wait for transmit data register empty
do
{
- HAL_READ_UINT32(AT91_SPI+AT91_SPI_SR, val);
+ HAL_READ_UINT32(spi_bus->base+AT91_SPI_SR, val);
} while ( !(val & AT91_SPI_SR_TDRE) );
// Send next byte over the wire
val = *tx_data++;
- HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_TDR, val);
+ HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_TDR, val);
// Wait for reveive data register full
do
{
- HAL_READ_UINT32(AT91_SPI+AT91_SPI_SR, val);
+ HAL_READ_UINT32(spi_bus->base+AT91_SPI_SR, val);
} while ( !(val & AT91_SPI_SR_RDRF) );
// Store received byte
- HAL_READ_UINT32(AT91_SPI+AT91_SPI_RDR, val);
+ HAL_READ_UINT32(spi_bus->base+AT91_SPI_RDR, val);
if (NULL != rx_data)
*rx_data++ = val;
}
spi_at91_transaction_begin(cyg_spi_device *dev)
{
cyg_spi_at91_device_t *at91_spi_dev = (cyg_spi_at91_device_t *) dev;
+ cyg_spi_at91_bus_t *spi_bus =
+ (cyg_spi_at91_bus_t *)at91_spi_dev->spi_device.spi_bus;
cyg_uint32 val;
if (!at91_spi_dev->init)
val |= AT91_SPI_CSR_SCBR(at91_spi_dev->cl_scbr);
- HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_CSR0, val);
+ HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_CSR0, val);
// Enable SPI clock
- HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_PCER, AT91_PMC_PCER_SPI);
-
+ HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_PCER, 1<<spi_bus->interrupt_number);
+
// Enable the SPI controller
- HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_CR, AT91_SPI_CR_SPIEN);
+ HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_CR, AT91_SPI_CR_SPIEN);
+ /* As we are using this driver only in master mode with NPCS0
+ configured as GPIO instead of a peripheral pin, it is neccessary
+ for the Mode Failure detection to be switched off as this will
+ cause havoc with the driver */
+
// Put SPI bus into master mode
- if (1 == at91_spi_dev->cl_div32)
- HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_MR, AT91_SPI_MR_MSTR |
- AT91_SPI_MR_DIV32);
- else
- HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_MR, AT91_SPI_MR_MSTR);
+ if (1 == at91_spi_dev->cl_div32) {
+ val = AT91_SPI_MR_MSTR | AT91_SPI_MR_DIV32;
+#ifdef AT91_SPI_MR_MODFDIS
+ val |= AT91_SPI_MR_MODFDIS;
+#endif
+ HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_MR, val);
+ } else {
+ val = AT91_SPI_MR_MSTR;
+#ifdef AT91_SPI_MR_MODFDIS
+ val |= AT91_SPI_MR_MODFDIS;
+#endif
+ HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_MR, val);
+ }
}
static void
static void
spi_at91_transaction_end(cyg_spi_device* dev)
{
- // Disable the SPI controller
- HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_CR, AT91_SPI_CR_SPIDIS);
+ cyg_spi_at91_device_t * at91_spi_dev = (cyg_spi_at91_device_t *)dev;
+ cyg_spi_at91_bus_t *spi_bus =
+ (cyg_spi_at91_bus_t *)at91_spi_dev->spi_device.spi_bus;
+ // Disable the SPI controller
+ HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_CR, AT91_SPI_CR_SPIDIS);
+
// Disable SPI clock
- HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_PCDR, AT91_PMC_PCER_SPI);
-
+ HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_PCDR,1<<spi_bus->interrupt_number);
+
spi_at91_drop_cs((cyg_spi_at91_device_t *) dev);
}
+2006-06-01 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * cdl/spi_eb55.cdl: Updates needed for recent changes to AT91 SPI
+ driver.
+
2004-08-31 Savin Zlobec <savin@elatec.si>
* cdl/spi_eb55.cdl:
active_if CYGPKG_IO_SPI
active_if CYGPKG_DEVS_SPI_ARM_AT91
display "Atmel AT91EB55 SPI devices"
- requires CYGHWR_DEVS_SPI_ARM_AT91_PCSDEC
+ requires CYGHWR_DEVS_SPI_ARM_AT91_BUS0_PCSDEC
hardware
include_dir cyg/io
compile spi_eb55.c
display "SPI driver for FSL MXC-based platforms"
compile -library=libextras.a mxc_spi.c
-
+
include_dir cyg/io
cdl_option CYGHWR_DEVS_FSL_SPI_VER_XX {
}
}
cdl_option CYGHWR_DEVS_FSL_SPI_VER_0_4 {
- display "SPI version 0.4 support for MX31, MXC91231"
+ display "SPI version 0.4 support for MX31"
default_value 0
description "
When this option is enabled, it indicates the SPI version
puts $::cdl_system_header "#define MXC_SPI_VER_0_7"
}
}
+ cdl_option CYGHWR_DEVS_FSL_SPI_VER_2_3 {
+ display "SPI version 2.3 support"
+ default_value 0
+ description "
+ When this option is enabled, it indicates the SPI version
+ is 2.3"
+ define_proc {
+ puts $::cdl_system_header "#define MXC_SPI_VER_2_3"
+ }
+ }
}
#define SPI_RX_REG_OFF 0x0
#define SPI_TX_REG_OFF 0x4
#define SPI_CTRL_REG_OFF 0x8
-#define SPI_INT_CTRL_REG_OFF 0xC
#if defined(MXC_SPI_VER_0_4)
+#define SPI_INT_CTRL_REG_OFF 0xC
#define SPI_DMA_REG_OFF 0x10
#define SPI_INT_STAT_REG_OFF 0x14
#define SPI_PERIOD_REG_OFF 0x18
#define SPI_CTRL_REG_RATE_WD 3 // 3-bit width
#define SPI_CTRL_REG_BIT_COUNT32 (0x1F << 8) // 32-bit xfer
+#define SPI_CTRL_REG_BIT_COUNT23 (0x16 << 8) // 23-bit xfer
#define SPI_CTRL_CS0 (0 << 24)
#define SPI_CTRL_CS1 (1 << 24)
#define SPI_CTRL_CS2 (2 << 24)
#define SPI_CTRL_CS3 (3 << 24)
+#define SPI_CTRL_CS_MASK (3 << 24)
#define SPI_CTRL_SSPOL_HIGH (1 << 7)
#define SPI_CTRL_SSCTL_SET (1 << 6)
#define SPI_CTRL_SCLK_POL_LOW (1 << 4)
#define SPI_CTRL_MODE_MASTER (1 << 1)
#define SPI_CTRL_EN (1 << 0)
+#define SPI_TEST_REG_RXCNT_OFFSET 4
+#define SPI_TEST_REG_RXCNT_MASK (0xF << 4)
#elif defined(MXC_SPI_VER_0_7)
+#define SPI_INT_CTRL_REG_OFF 0xC
#define SPI_DMA_REG_OFF 0x10
#define SPI_INT_STAT_REG_OFF 0x14
#define SPI_PERIOD_REG_OFF 0x18
#define SPI_CTRL_REG_RATE_SH 16 // start from bit 16
#define SPI_CTRL_REG_RATE_WD 3 // 3-bit width
+#define SPI_CTRL_REG_BIT_COUNT46 (0x2D << 20) // 48-bit xfer
#define SPI_CTRL_REG_BIT_COUNT32 (0x1F << 20) // 32-bit xfer
+#define SPI_CTRL_REG_BIT_COUNT23 (0x16 << 20) // 23-bit xfer
#define SPI_CTRL_CS0 (0 << 12)
#define SPI_CTRL_CS1 (1 << 12)
#define SPI_CTRL_CS2 (2 << 12)
#define SPI_CTRL_CS3 (3 << 12)
+#define SPI_CTRL_CS_MASK (3 << 12)
#define SPI_CTRL_SSPOL_HIGH (1 << 7)
#define SPI_CTRL_SSCTL_SET (1 << 6)
#define SPI_CTRL_SCLK_POL_LOW (1 << 4)
#define SPI_CTRL_MODE_MASTER (1 << 1)
#define SPI_CTRL_EN (1 << 0)
+#define SPI_TEST_REG_RXCNT_OFFSET 4
+#define SPI_TEST_REG_RXCNT_MASK (0xF << 4)
+
+
+#elif defined(MXC_SPI_VER_2_3)
+#define SPI_CONFIG_REG_OFF 0xC
+#define SPI_INT_CTRL_REG_OFF 0x10
+#define SPI_DMA_REG_OFF 0x14
+#define SPI_INT_STAT_REG_OFF 0x18
+#define SPI_PERIOD_REG_OFF 0x1C
+#define SPI_TEST_REG_OFF 0x20
+#define SPI_INT_STAT_RR (1 << 3)
+
+#define SPI_CTRL_REG_XCH_BIT (1 << 2)
+#define SPI_CTRL_REG_RATE_SH 12 // start from bit 12
+#define SPI_CTRL_REG_RATE_WD 4 // 3-bit width
+#define SPI_CTRL_REG_BIT_COUNT32 (0x1F << 20) // 32-bit xfer
+#define SPI_CTRL_REG_BIT_COUNT23 (0x16 << 20) // 23-bit xfer
+#define SPI_CTRL_REG_BIT_COUNT46 (0x2D << 20) // 46-bit xfer
+#define SPI_CTRL_CS0 (0 << 18)
+#define SPI_CTRL_CS1 (1 << 18)
+#define SPI_CTRL_CS2 (2 << 18)
+#define SPI_CTRL_CS3 (3 << 18)
+#define SPI_CTRL_CS_MASK (3 << 18)
+#define SPI_CTRL_MODE_MASTER_0 (1 << 4)
+#define SPI_CTRL_MODE_MASTER_1 (1 << 5)
+#define SPI_CTRL_MODE_MASTER_2 (1 << 6)
+#define SPI_CTRL_MODE_MASTER_3 (1 << 7)
+#define SPI_CTRL_EN (1 << 0)
+
+#define SPI_CFG_SS0_POL_HIGH (1 << 12)
+#define SPI_CFG_SS1_POL_HIGH (1 << 13)
+#define SPI_CFG_SS2_POL_HIGH (1 << 14)
+#define SPI_CFG_SS3_POL_HIGH (1 << 15)
+#define SPI_CFG_SS0_POL_LOW (0 << 12)
+#define SPI_CFG_SS1_POL_LOW (0 << 13)
+#define SPI_CFG_SS2_POL_LOW (0 << 14)
+#define SPI_CFG_SS3_POL_LOW (0 << 15)
+
+#define SPI_TEST_REG_RXCNT_OFFSET 8
+#define SPI_TEST_REG_RXCNT_MASK (0x7F << 8)
#else
+// For MX27
+#define SPI_INT_CTRL_REG_OFF 0xC
#define SPI_INT_STAT_REG_OFF 0xC
#define SPI_TEST_REG_OFF 0x10
#define SPI_PERIOD_REG_OFF 0x14
#define SPI_CTRL_CS0 (0 << 19)
#define SPI_CTRL_CS1 (1 << 19)
#define SPI_CTRL_CS2 (2 << 19)
+#define SPI_CTRL_CS_MASK (3 << 19)
#define SPI_CTRL_SSPOL_HIGH (1 << 8)
#define SPI_CTRL_SSCTL_SET (1 << 7)
#define SPI_CTRL_SCLK_POL_LOW (1 << 5)
#define SPI_CTRL_REG_BIT_COUNT32 0x1F // 32-bit xfer
+#define SPI_CTRL_REG_BIT_COUNT23 0x16 // 23-bit xfer
#define SPI_CTRL_MODE_MASTER (1 << 11)
#define SPI_CTRL_EN (1 << 10)
+#define SPI_TEST_REG_RXCNT_OFFSET 4
+#define SPI_TEST_REG_RXCNT_MASK (0xF << 4)
#endif
unsigned int pmic_reg(unsigned int reg, unsigned int val, unsigned int write);
unsigned int spi_xchg_single(unsigned int data, unsigned int base);
+#ifdef CPLD_SPI_BASE
+unsigned int spi_cpld_xchg_single(unsigned int data, unsigned int data1, unsigned int base);
+unsigned int cpld_reg(unsigned int reg, unsigned int val, unsigned int read);
+unsigned int cpld_reg_xfer(unsigned int reg, unsigned int val, unsigned int read);
+#endif /* CPLD_SPI_BASE */
+
#endif /* __MXC_SPI_H__ */
const unsigned int baud_rate_div[] = {
4, 8, 16, 32, 64, 128, 256, 512,
};
-
+static int version = 1;
#elif defined(MXC_SPI_VER_XX)
const unsigned int baud_rate_div[] = {
3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, 256, 384, 512,
};
-
+static int version = 2;
+#elif defined(MXC_SPI_VER_2_3)
+const unsigned int baud_rate_div[] = {
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+};
+static int version = 3;
#else
#error No SPI version defined
#endif
const int BAUD_RATE_DIV_MAX = sizeof(baud_rate_div) / sizeof(unsigned int);
-/*!
- * It is for the master mode operation to exchange a single word with
- * external device.
- *
- * @param data data to be transferred
- * @param base base address of the spi module
- *
- * @return the value received from the Rx register
- */
-unsigned int spi_xchg_single(unsigned int data, unsigned int base)
-{
- volatile unsigned int cfg_reg = readl(base + SPI_CTRL_REG_OFF);
-
- hal_delay_us(100);
-
- writel(data, base + SPI_TX_REG_OFF);
-
- cfg_reg |= SPI_CTRL_REG_XCH_BIT;
-
- writel(cfg_reg, base + SPI_CTRL_REG_OFF);
-
- while ((readl(base + SPI_INT_STAT_REG_OFF) & SPI_INT_STAT_RR) == 0) {
- }
-
- return readl(base + SPI_RX_REG_OFF);
-}
-
/*!
* Initialize and enable a spi module
*
}
// to adjust for differen spi versions
- if (BAUD_RATE_DIV_MAX > 8) {
+ if (version == 2) {
ctrl_val |= ((i + 1) << SPI_CTRL_REG_RATE_SH);
} else
ctrl_val |= (i << SPI_CTRL_REG_RATE_SH);
diag_printf1("ctrl_val=0x%x, i=%d, SPI_CTRL_REG_RATE_SH=%d\n",
ctrl_val, i, SPI_CTRL_REG_RATE_SH);
+ /* Reinitialize the control register */
+ writel(0, base + SPI_CTRL_REG_OFF);
writel(SPI_CTRL_EN, base + SPI_CTRL_REG_OFF);
writel(ctrl_val, base + SPI_CTRL_REG_OFF);
}
#ifdef PMIC_SPI_BASE
+/*!
+ * It is for the master mode operation to exchange a single word with
+ * external device.
+ *
+ * @param data data to be transferred
+ * @param base base address of the spi module
+ *
+ * @return the value received from the Rx register
+ */
+unsigned int spi_xchg_single(unsigned int data, unsigned int base)
+{
+ volatile unsigned int cfg_reg = readl(base + SPI_CTRL_REG_OFF);
+
+#if defined(MXC_SPI_VER_2_3)
+ int ss_num = (PMIC_SPI_CHIP_SELECT_NO >> 18) & 0x3;
+ volatile unsigned int pol_reg = readl(base + SPI_CONFIG_REG_OFF);
+ pol_reg &= ~(1 << (12 + ss_num));
+ /* Activate the SS signal */
+ pol_reg |= PMIC_SPI_SS_POL;
+ writel(pol_reg, base + SPI_CONFIG_REG_OFF);
+#endif
+
+ hal_delay_us(100);
+
+ writel(data, base + SPI_TX_REG_OFF);
+
+ cfg_reg |= SPI_CTRL_REG_XCH_BIT;
+
+ writel(cfg_reg, base + SPI_CTRL_REG_OFF);
+
+ while ((readl(base + SPI_INT_STAT_REG_OFF) & SPI_INT_STAT_RR) == 0) {
+ }
+
+#if defined(MXC_SPI_VER_2_3)
+ pol_reg &= ~(1 << (12 + ss_num));
+ pol_reg |= (~PMIC_SPI_SS_POL) & (1 << (12 + ss_num));
+ /* Deactivate the SS signal */
+ writel(PMIC_SPI_SS_POL, base + SPI_CONFIG_REG_OFF);
+#endif
+
+ return readl(base + SPI_RX_REG_OFF);
+}
+
static void mxc_pmic_init(void)
{
- volatile unsigned int rev_id;
+ volatile unsigned int rev_id;
+ unsigned int ctrl;
- spi_init(PMIC_SPI_BASE, 4000000, // 4MHz data rate
- SPI_CTRL_REG_BIT_COUNT32 |
- SPI_CTRL_CS0 |
- SPI_CTRL_SSPOL_HIGH |
- SPI_CTRL_MODE_MASTER |
- SPI_CTRL_EN
- );
+#if defined(MXC_SPI_VER_2_3)
+ ctrl = SPI_CTRL_REG_BIT_COUNT32 | SPI_CTRL_MODE_MASTER_0 | SPI_CTRL_EN;
+#else
+ ctrl = SPI_CTRL_REG_BIT_COUNT32 | SPI_CTRL_SSPOL_HIGH |
+ SPI_CTRL_MODE_MASTER | SPI_CTRL_EN;
+#endif
+ /* Activate the SS signal */
+ ctrl |= PMIC_SPI_CHIP_SELECT_NO;
+ spi_init(PMIC_SPI_BASE, 6000000, // 4MHz data rate
+ ctrl);
rev_id = pmic_reg(7, 0, 0);
- diag_printf("PMIC ID: 0x%08x [Rev: ", rev_id);
+ diag_printf("PMIC ID: 0x%08x [Rev: ", rev_id);
switch (rev_id & 0x1F) {
case 0x1:
diag_printf("1.0");
return temp;
}
#endif // PMIC_SPI_BASE
+
+#ifdef CPLD_SPI_BASE
+
+unsigned int spi_cpld_xchg_single(unsigned int data, unsigned int data1, unsigned int base)
+{
+ volatile unsigned int cfg_reg = readl(base + SPI_CTRL_REG_OFF);
+ unsigned int temp;
+
+ /* Activate the SS signal */
+ cfg_reg |= CPLD_SPI_CHIP_SELECT_NO;
+ writel(cfg_reg, CPLD_SPI_BASE + SPI_CTRL_REG_OFF);
+
+ /* Write the data */
+ writel(data, base + SPI_TX_REG_OFF);
+ writel(data1, base + SPI_TX_REG_OFF);
+
+ cfg_reg |= SPI_CTRL_REG_XCH_BIT;
+ writel(cfg_reg, base + SPI_CTRL_REG_OFF);
+
+ while ((((cfg_reg = readl(base + SPI_TEST_REG_OFF)) &
+ SPI_TEST_REG_RXCNT_MASK) >> SPI_TEST_REG_RXCNT_OFFSET) != 2) {
+ }
+
+ /* Deactivate the SS signal */
+ cfg_reg = readl(base + SPI_CTRL_REG_OFF);
+ cfg_reg &= ~SPI_CTRL_CS_MASK;
+ writel(cfg_reg, base + SPI_CTRL_REG_OFF);
+
+ /* Read from RX FIFO, second entry contains the data */
+ temp = readl(base + SPI_RX_REG_OFF);
+ temp = readl(base + SPI_RX_REG_OFF);
+ return ((temp >> 6) & 0xffff);
+}
+
+static void mxc_cpld_spi_init(void)
+{
+ unsigned int ctrl;
+
+ ctrl = SPI_CTRL_REG_BIT_COUNT46 | CPLD_SPI_CTRL_MODE_MASTER | SPI_CTRL_EN;
+
+ spi_init(CPLD_SPI_BASE, 18000000, // 54MHz data rate
+ ctrl);
+}
+
+RedBoot_init(mxc_cpld_spi_init, RedBoot_INIT_PRIO(102));
+
+static void do_cpld(int argc, char *argv[]);
+
+RedBoot_cmd("spi_cpld",
+ "Read/Write 16-bit internal CPLD register over CSPI",
+ "<reg num> [16-bit value to be written]",
+ do_cpld
+ );
+
+static void do_cpld(int argc,char *argv[])
+{
+ unsigned int reg, temp, val = 0, read = 1;
+
+ if (argc == 1) {
+ diag_printf("\tRead: spi_cpld <reg num>\n");
+ diag_printf("\tWrite: spi_cpld <reg num> <value to be written>\n");
+ return;
+ }
+
+ if (!parse_num(*(&argv[1]), (unsigned long *)®, &argv[1], ":")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+
+ if (argc == 3) {
+ if (!parse_num(*(&argv[2]), (unsigned long *)&val, &argv[2], ":")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ read = 0;
+ }
+
+ temp = cpld_reg(reg, val, read);
+
+ diag_printf("\tval: 0x%04x\n\n", temp);
+}
+
+/*!
+ * To read/write to a CPLD register.
+ *
+ * @param reg register number inside the CPLD
+ * @param val data to be written to the register; don't care for read
+ * @param read 0 for write; 1 for read
+ *
+ * @return the actual data in the CPLD register
+ */
+unsigned int cpld_reg_xfer(unsigned int reg, unsigned int val, unsigned int read)
+{
+ unsigned int local_val1, local_val2;
+
+ reg >>= 1;
+
+ local_val1 = (read << 13) | ((reg & 0x0001FFFF) >> 5) | 0x00001000;
+ if (read) {
+ //local_val1 = (read << 22) | (reg << 4) | 0x00200004;
+ //local_val2 = 0x1F;
+ local_val2 = ( ((reg & 0x0000001F) << 27) | 0x0200001f);
+
+ } else {
+ //local_val1 = (read << 22) | (reg << 4) | 0x00200007;
+ //local_val2 = ((val & 0xFFFF) << 6) | 0x00400027;
+ local_val2 = ( ((reg & 0x0000001F) << 27) | ((val & 0x0000FFFF) << 6) | 0x03C00027);
+
+ }
+
+ diag_printf1("reg=0x%x, val=0x%08x\n", reg, val);
+ return spi_cpld_xchg_single(local_val1, local_val2, CPLD_SPI_BASE);
+}
+
+/*!
+ * To read/write to a CPLD register. For write, it does another read for the
+ * actual register value.
+ *
+ * @param reg register number inside the CPLD
+ * @param val data to be written to the register; don't care for read
+ * @param read 0 for write; 1 for read
+ *
+ * @return the actual data in the CPLD register
+ */
+unsigned int cpld_reg(unsigned int reg, unsigned int val, unsigned int read)
+{
+ unsigned int temp;
+
+ if (reg > 0x20068 || read > 1 ) {
+ diag_printf("<reg num> = %x is invalid. Should be less then 0x20068\n", reg);
+ return 0;
+ }
+
+ temp = cpld_reg_xfer(reg, val, read);
+ diag_printf1("reg=0x%x, val=0x%08x\n", reg, val);
+
+ if (read == 0) {
+ temp = cpld_reg_xfer(reg, val, 1);
+ }
+
+ return temp;
+}
+
+#endif // CPLD_SPI_BASE
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
-// This file is a part of Diagnosis Package based on eCos for Freescale i.MX
+// This file is a part of Diagnosis Package based on eCos for Freescale i.MX
// Family microprocessor.
// Copyright (C) 2008 Freescale Semiconductor, Inc.
//
//this error code is defined in error/include/codes.h
//but when the usb driver is used in redboot, the codes.h won't
//be included, so that this definition will solve the problem
-#define EPIPE 304
+#define EPIPE 304
/* Constants */
#define SDP_CMD_MAX_LEN 0x10 /* 16 bytes */
/* Bit3 - Mass Storage Information
Bit2 - Enumeration Information
Bit1 - Transaction Information
- Bit0 - Basic Information
+ Bit0 - Basic Information
*/
//#define DEBUG_TRANS 0x8 //also defined in usbs_msc.c
#define DEBUG_ENUM 0x4
//This variable is used to workaround the 31-byte packet issue in i.MX37
//It is initialized as "0x1",
//When data read/write, it must initialize as '0x0'
-cyg_uint32 g_td_buffer_offset = 0;
+cyg_uint32 g_td_buffer_offset = 0;
//The below two flags is used to distinguish the received data is data or command
cyg_uint32 g_received_data_type;
//2k aligned, this buffer must be uncacheable and unbufferable.
#if defined(CYGHWR_IMX_USB_BUFFER_USE_IRAM)
-static volatile cyg_uint8 usb_buffer[BUFFER_SIZE] __attribute__((aligned(0x800)));
+static volatile cyg_uint8 usb_buffer[BUFFER_SIZE] __attribute__((aligned(0x800)));
static volatile cyg_uint8 bulk_buffer[BULK_TD_BUFFER_TOTAL_SIZE*NUM_OF_BULK_BUFFER] __attribute__((aligned(0x1000)));
//#pragma arm section
#else
Reserve 0x800 bytes as USB buffer
Don't use 0x10001000~0x10001800 for other program. */
#if defined(CYGHWR_USB_DEVS_MX37_OTG)
-static volatile cyg_uint8 * usb_buffer=(cyg_uint8 *)(0x10001000);
+static volatile cyg_uint8 * usb_buffer=(cyg_uint8 *)(0x10001000);
static volatile cyg_uint8 * bulk_buffer = (cyg_uint8 *)(0x10002000);
#endif
#if defined(CYGHWR_USB_DEVS_MX51_OTG)
-static volatile cyg_uint8 * usb_buffer=(cyg_uint8 *)(0x1FFE9000);
+static volatile cyg_uint8 * usb_buffer=(cyg_uint8 *)(0x1FFE9000);
static volatile cyg_uint8 * bulk_buffer = (cyg_uint8 *)(0x1FFEA000);
#endif
-//
+//
#endif //defined(CYGHWR_IMX_USB_BUFFER_USE_IRAM)
VOLATILE usbs_imx_otg_hardware* usbs_imx_otg_base = (VOLATILE usbs_imx_otg_hardware* const) USB_BASE_ADDRESS;
/* Base address of the buffer allocated to IP Layer */
static VOLATILE cyg_uint32 g_bulkbuffer_address_base;
/* length of the buffer */
-static VOLATILE cyg_uint32 g_bulkbuffer_length;
+static VOLATILE cyg_uint32 g_bulkbuffer_length;
/* Buffer information used for data transfer */
-static VOLATILE buffer_map_t g_bulkbuffer_map;
+static VOLATILE buffer_map_t g_bulkbuffer_map;
/* Number of Endpoints configured in system */
-static VOLATILE cyg_uint8 g_max_ep_supported;
+static VOLATILE cyg_uint8 g_max_ep_supported;
/* State os USB Device */
-static VOLATILE usb_state_t g_usb_dev_state = USB_DEV_DUMMY_STATE;
+static VOLATILE usb_state_t g_usb_dev_state = USB_DEV_DUMMY_STATE;
/* Length of setup data received */
static VOLATILE cyg_uint8 * g_usb_setup_data;
/* Array to keep information about the endpoints used */
-static VOLATILE usb_end_pt_info_t g_end_pt_info[USB_DEV_INF_DESC_NUM_OF_EP];
+static VOLATILE usb_end_pt_info_t g_end_pt_info[USB_DEV_INF_DESC_NUM_OF_EP];
/* Number of endpoints */
-static VOLATILE cyg_uint8 g_number_of_endpoints;
+static VOLATILE cyg_uint8 g_number_of_endpoints;
/* USB Descriptors */
-static VOLATILE usb_descriptor g_usb_desc;
+static VOLATILE usb_descriptor g_usb_desc;
/* Number of Endpoint configured as IN */
-static VOLATILE cyg_uint8 g_in_endpoint;
+static VOLATILE cyg_uint8 g_in_endpoint;
/* Number of Endpoint configured as OUT*/
-static VOLATILE cyg_uint8 g_out_endpoint;
+static VOLATILE cyg_uint8 g_out_endpoint;
/* Support for the interrupt handling code.*/
static cyg_interrupt g_usbs_dev_intr_data;
// ----------------------------------------------------------------------------
// Set USB device address
#define USBS_DEVICE_SET_ADDRESS(addr) (usbs_imx_otg_base->devaddr = ((cyg_uint32)addr & 0x7F) << 25)
-/*
-#*************
-# OTG
-#*************
+/*
+#*************
+# OTG
+#*************
*/
#define USB_OTG_ID (&(usbs_imx_otg_base->id)) /* Identification Register */
#define USB_OTG_HWGENERAL (&(usbs_imx_otg_base->hwgeneral)) /* General Hardware Parameters */
#define USB_OTG_ENDPTNAKEN (&(usbs_imx_otg_base->endptnaken)) /*Endpoint NAK Enable */
#define USB_OTG_CONFIGFLAG (&(usbs_imx_otg_base->configflg)) /* Configured Flag Register */
#define USB_OTG_PORTSC1 (&(usbs_imx_otg_base->portsc1)) /* Port 0 Status/Control */
-#define USB_OTG_OTGSC (&(usbs_imx_otg_base->otgsc)) /* OTG Status and Control */
+#define USB_OTG_OTGSC (&(usbs_imx_otg_base->otgsc)) /* OTG Status and Control */
#define USB_OTG_USBMODE (&(usbs_imx_otg_base->usbmode)) /* USB Device Mode */
#define USB_OTG_ENDPTSETUPSTAT (&(usbs_imx_otg_base->endptsetupstat)) /* Endpoint Setup Status */
#define USB_OTG_ENDPTPRIME (&(usbs_imx_otg_base->endptprime)) /* Endpoint Initialization */
/* USB Device Descriptor according to USB2.0 Specification */
static VOLATILE usb_device_descriptor g_usb_device_desc ={
USB_DEV_DESC_LEN,
- USB_DEV_DESC_TYPE,
- USB_DEV_DESC_SPEC_LB,
- USB_DEV_DESC_SPEC_HB,
- USB_DEV_DESC_DEV_CLASS,
- USB_DEV_DESC_DEV_SUBCLASS,
- USB_DEV_DESC_DEV_PROTOCOL,
- USB_DEV_DESC_EP0_MAXPACKETSIZE,
- USB_DEV_DESC_VENDORID_LB,
- USB_DEV_DESC_VENDORID_HB,
- USB_DEV_DESC_PRODUCTID_LB,
- USB_DEV_DESC_PRODUCTID_HB,
- USB_DEV_DESC_DEV_RELEASE_NUM_LB,
- USB_DEV_DESC_DEV_RELEASE_NUM_HB,
+ USB_DEV_DESC_TYPE,
+ USB_DEV_DESC_SPEC_LB,
+ USB_DEV_DESC_SPEC_HB,
+ USB_DEV_DESC_DEV_CLASS,
+ USB_DEV_DESC_DEV_SUBCLASS,
+ USB_DEV_DESC_DEV_PROTOCOL,
+ USB_DEV_DESC_EP0_MAXPACKETSIZE,
+ USB_DEV_DESC_VENDORID_LB,
+ USB_DEV_DESC_VENDORID_HB,
+ USB_DEV_DESC_PRODUCTID_LB,
+ USB_DEV_DESC_PRODUCTID_HB,
+ USB_DEV_DESC_DEV_RELEASE_NUM_LB,
+ USB_DEV_DESC_DEV_RELEASE_NUM_HB,
USB_DEV_DESC_DEV_STRING_IND_MANUFACTURE,
- USB_DEV_DESC_DEV_STRING_IND_PRODUCT,
+ USB_DEV_DESC_DEV_STRING_IND_PRODUCT,
USB_DEV_DESC_DEV_STRING_IND_SERIAL_NUM,
USB_DEV_DESC_DEV_NUM_CONFIGURATIONS
};
/* USB Config Descriptor according to USB2.0 Specification */
static VOLATILE usb_conf_desc g_usb_config_desc = {
- {
- USB_DEV_CONFIG_DESC_LEN,
- USB_DEV_CONFIG_DESC_TYPE,
- USB_DEV_CONFIG_DESC_TTL_LEN_LB ,
- USB_DEV_CONFIG_DESC_TTL_LEN_HB ,
- USB_DEV_CONFIG_DESC_NUM_0F_INF,
- USB_DEV_CONFIG_DESC_CONFIG_VALUE ,
- USB_DEV_CONFIG_DESC_STRING_INDEX,
- USB_DEV_CONFIG_DESC_ATTRIBUTES,
+ {
+ USB_DEV_CONFIG_DESC_LEN,
+ USB_DEV_CONFIG_DESC_TYPE,
+ USB_DEV_CONFIG_DESC_TTL_LEN_LB ,
+ USB_DEV_CONFIG_DESC_TTL_LEN_HB ,
+ USB_DEV_CONFIG_DESC_NUM_0F_INF,
+ USB_DEV_CONFIG_DESC_CONFIG_VALUE ,
+ USB_DEV_CONFIG_DESC_STRING_INDEX,
+ USB_DEV_CONFIG_DESC_ATTRIBUTES,
USB_DEV_CONFIG_DESC_MAX_POWER
},
/* USB Interface Descriptor according to USB2.0 Specification */
{//09
- USB_DEV_INF_DESC_LEN,
- USB_DEV_INF_DESC_TYPE,
- USB_DEV_INF_DESC_INF_INDEX,
+ USB_DEV_INF_DESC_LEN,
+ USB_DEV_INF_DESC_TYPE,
+ USB_DEV_INF_DESC_INF_INDEX,
USB_DEV_INF_DESC_ALT_SETTING,
USB_DEV_INF_DESC_NUM_OF_EP, /* NOTE : This should not be more than 2 */
#if defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT)
USB_DEV_INF_DESC_INF_SUBCLASS_NS_BLANK,
USB_DEV_INF_DESC_INF_PROTOCOL,
#else
- USB_DEV_INF_DESC_INF_CLASS_MSC,
- USB_DEV_INF_DESC_INF_SUBCLASS_MSC_SCSI,
- USB_DEV_INF_DESC_INF_PROTOCOL_MSC_BOT,
+ USB_DEV_INF_DESC_INF_CLASS_MSC,
+ USB_DEV_INF_DESC_INF_SUBCLASS_MSC_SCSI,
+ USB_DEV_INF_DESC_INF_PROTOCOL_MSC_BOT,
#endif
USB_DEV_INF_DESC_STRING_INDEX
},
USB_EP1_DESC_SIZE,
USB_EP1_DESC_TYPE,
USB_EP1_DESC_EP_ADDR,
- USB_EP1_DESC_ATTRIBUTES,
- USB_EP1_DESC_MAX_PACKET_SIZE_HS_LB,
- USB_EP1_DESC_MAX_PACKET_SIZE_HS_HB,
+ USB_EP1_DESC_ATTRIBUTES,
+ USB_EP1_DESC_MAX_PACKET_SIZE_HS_LB,
+ USB_EP1_DESC_MAX_PACKET_SIZE_HS_HB,
USB_EP1_DESC_INTERVAL
},
/* USB Endpoint 2 Descriptors according to USB2.0 Specification, IN */
{//25
- USB_EP2_DESC_SIZE,
+ USB_EP2_DESC_SIZE,
USB_EP2_DESC_TYPE,
- USB_EP2_DESC_EP_ADDR,
- USB_EP2_DESC_ATTRIBUTES,
- USB_EP2_DESC_MAX_PACKET_SIZE_HS_LB,
- USB_EP2_DESC_MAX_PACKET_SIZE_HS_HB,
+ USB_EP2_DESC_EP_ADDR,
+ USB_EP2_DESC_ATTRIBUTES,
+ USB_EP2_DESC_MAX_PACKET_SIZE_HS_LB,
+ USB_EP2_DESC_MAX_PACKET_SIZE_HS_HB,
USB_EP2_DESC_INTERVAL
}
}
USB_LANGUAGE_ID_HB
};
-/*
+/*
STRING DESCRIPTOR
See table 9-15 in USB2.0 spec (www.usb.org)
iManufacturer
}
};
#if defined(CYGHWR_USB_DEVS_MX37_OTG)
-/*iProduct*/
+/*iProduct*/
static VOLATILE usb_str2_desc g_usb_otg_string_desc2 = {
USB_STR2_DESC_SIZE_NS, /* bLength */
USB_STR2_DESC_TYPE, /* bDescriptorType */
{
'M', 0x00, /* bString */
- 'A', 0x00,
- 'R', 0x00,
+ 'A', 0x00,
+ 'R', 0x00,
'L', 0x00,
- 'E', 0x00,
- 'Y', 0x00,
- ' ', 0x00,
- 'U', 0x00,
- 'S', 0x00,
+ 'E', 0x00,
+ 'Y', 0x00,
+ ' ', 0x00,
+ 'U', 0x00,
+ 'S', 0x00,
'B', 0x00,
' ', 0x00,
'O', 0x00,
USB_STR2_DESC_TYPE, /* bDescriptorType */
{
'E', 0x00, /* bString */
- 'l', 0x00,
- 'v', 0x00,
+ 'l', 0x00,
+ 'v', 0x00,
'i', 0x00,
- 's', 0x00,
- ' ', 0x00,
- 'U', 0x00,
- 'S', 0x00,
- 'B', 0x00,
+ 's', 0x00,
+ ' ', 0x00,
+ 'U', 0x00,
+ 'S', 0x00,
+ 'B', 0x00,
' ', 0x00,
'O', 0x00,
'T', 0x00,
's', 0x00,
'h', 0x00
}
-};
+};
// ****************************************************************************
buffer: (const unsigned char*) 0,
buffer_size: 0,
halted: 0,
- },
+ },
transmitted: 0,
pkt_size: 0
};
cyg_uint8 zlt - zero lengh packet termination (enable - ZLT_ENABLE; disable - ZLT_DISABLE)
cyg_uint16 mps - Max packet length
cyg_uint8 ios - interrupt on Setup
- cyg_uint32 next_link_ptr - Next Link Pointer,
+ cyg_uint32 next_link_ptr - Next Link Pointer,
cyg_uint8 terminate - terminate - TERMINATE; not terminate - NOT_TERMINATE
cyg_uint16 total_bytes - Total Bytes to be transfered in this dQH
cyg_uint8 ioc - interrupt on complete, set - IOC_SET, not set - IOC_NOTSET
- cyg_uint8 status - status
+ cyg_uint8 status - status
cyg_uint32 buffer_ptr0 - Buffer Pointer page 0
cyg_uint16 current_offset - current offset
cyg_uint32 buffer_ptr1 - Buffer Pointer page 1
cyg_uint32 buffer_ptr2 - Buffer Pointer page 1
cyg_uint32 buffer_ptr3 - Buffer Pointer page 1
cyg_uint32 buffer_ptr4 - Buffer Pointer page 1
-
-RETURN VALUE: None
-IMPORTANT NOTES:None
+
+RETURN VALUE: None
+IMPORTANT NOTES:None
=============================================================================*/
-static void
+static void
usbs_setup_queuehead(struct dqh_t* qhead)
{
volatile struct dqh_setup_t* dqh_word = (volatile struct dqh_setup_t*) qhead->dqh_base;
/*Current dTD Pointer => for hw use, not modified by DCD software */
dqh_word->dqh_word1 = 0x0;
-
+
/*Next dTD Pointer */
dqh_word->dqh_word2 = (((qhead->next_link_ptr) & 0xFFFFFFE0) | qhead->terminate);
-
- /*Bit30:16 total_bytes; Bit15 ioc; Bit11:10 MultO; Bit7:0 status */
+
+ /*Bit30:16 total_bytes; Bit15 ioc; Bit11:10 MultO; Bit7:0 status */
dqh_word->dqh_word3 = ((((cyg_uint32)(qhead->total_bytes) & 0x7FFF) << 16) | ((cyg_uint32)(qhead->ioc) <<15) | (qhead->status));
/*Bit31:12 Buffer Pointer (Page 0) */
/*Bit31:12 Buffer Pointer (Page 1) */
dqh_word->dqh_word5 = (qhead->buffer_ptr1 & 0xFFFFF000);
-
+
/*Bit31:12 Buffer Pointer (Page 2) */
dqh_word->dqh_word6 = (qhead->buffer_ptr2 & 0xFFFFF000);
/*Bit31:12 Buffer Pointer (Page 3) */
dqh_word->dqh_word7 = (qhead->buffer_ptr3 & 0xFFFFF000);
-
+
/*Bit31:12 Buffer Pointer (Page 4) */
dqh_word->dqh_word8 = (qhead->buffer_ptr4 & 0xFFFFF000);
DESCRIPTION: This function is used to setup the dTD
ARGUMENTS PASSED:
cyg_uint32 dtd_base - Base Address of the dTD
- cyg_uint32 next_link_ptr - Next Link Pointer,
+ cyg_uint32 next_link_ptr - Next Link Pointer,
cyg_uint8 terminate - terminate - TERMINATE; not terminate - NOT_TERMINATE
cyg_uint16 total_bytes - Total Bytes to be transfered in this dQH
cyg_uint8 ioc - interrupt on complete, set - IOC_SET, not set - IOC_NOTSET
- cyg_uint8 Status - Status
+ cyg_uint8 Status - Status
cyg_uint32 buffer_ptr0 - Buffer Pointer page 0
cyg_uint16 current_offset - current offset
cyg_uint32 buffer_ptr1 - Buffer Pointer page 1
cyg_uint32 buffer_ptr2 - Buffer Pointer page 1
cyg_uint32 buffer_ptr3 - Buffer Pointer page 1
- cyg_uint32 buffer_ptr4 - Buffer Pointer page 1
-RETURN VALUE: None
-IMPORTANT NOTES:None
+ cyg_uint32 buffer_ptr4 - Buffer Pointer page 1
+RETURN VALUE: None
+IMPORTANT NOTES:None
==============================================================================*/
-static void
+static void
usbs_setup_transdesc(struct dtd_t* td)
{
volatile struct dtd_setup_t* dtd_word = (volatile struct dtd_setup_t *) td->dtd_base;
/* Bit30:16 total_bytes, Bit15 ioc, Bit7:0 status */
dtd_word->dtd_word1 = ((((cyg_uint32)td->total_bytes & 0x7FFF) << 16)| ((cyg_uint32)td->ioc <<15) | (td->status));
-
+
/* Bit31:12 Buffer Pointer Page 0 ; Bit11:0 Current Offset */
dtd_word->dtd_word2 = ((td->buffer_ptr0 & 0xFFFFF000) | (td->current_offset & 0xFFF));
-
+
/* Bit31:12 Buffer Pointer Page 1 ; Bit10:0 Frame Number */
dtd_word->dtd_word3 = (td->buffer_ptr1 & 0xFFFFF000);
FUNCTION: util_alloc_buffer
DESCRIPTION: This utility function allocate the free buffer available
ARGUMENTS PASSED: None
-RETURN VALUE: cyg_uint32 address : address of the allocated buffer
-IMPORTANT NOTES: If Buffer1 is FREE then return Buffer1 and mark this as Busy else check for buffer2 . If
+RETURN VALUE: cyg_uint32 address : address of the allocated buffer
+IMPORTANT NOTES: If Buffer1 is FREE then return Buffer1 and mark this as Busy else check for buffer2 . If
none of the buffer is free then return NULL.
==================================================================================================*/
cyg_uint32 util_alloc_buffer(void)
{
cyg_uint32 buffer_addr = (cyg_uint32)NULL; //force type conversion for multiple NULL definitions
-
- /* Check if buffer1 is free then mark it busy and return address */
+
+ /* Check if buffer1 is free then mark it busy and return address */
if (g_bulkbuffer_map.buffer1_status == BUFFER_FREE )
{
buffer_addr = g_bulkbuffer_map.buffer1_address;
g_bulkbuffer_map.buffer1_status = BUFFER_IN_USE;
}
- /* Check if buffer2 is free then mark it busy and return address */
+ /* Check if buffer2 is free then mark it busy and return address */
else if(g_bulkbuffer_map.buffer2_status == BUFFER_FREE)
{
buffer_addr = g_bulkbuffer_map.buffer2_address;
g_bulkbuffer_map.buffer2_status = BUFFER_IN_USE;
}
-
+
return buffer_addr ;
}
/*==================================================================================================
FUNCTION: util_free_buffer
DESCRIPTION: This function put the buffer in free state.
-ARGUMENTS PASSED: cyg_uint32 address : address of the buffer .
+ARGUMENTS PASSED: cyg_uint32 address : address of the buffer .
RETURN VALUE: None
IMPORTANT NOTES: None
-
+
==================================================================================================*/
void util_free_buffer(cyg_uint32 address)
{
};
RETURN VALUE: None
IMPORTANT NOTES: None
-
+
==================================================================================================*/
void util_set_status_bulk_buffer(cyg_uint32 buffer_addr,int buffer_status)
{
FUNCTION: usbs_endpoint_stall
DESCRIPTION: This function Send/Receive the STALL HANDSHAKE to USB Host
ARGUMENTS PASSED:
- cyg_uint8 endpoint - Endpoint Number .
+ cyg_uint8 endpoint - Endpoint Number .
cyg_uint8 direction - IN/OUT : direction of EndPoint.
RETURN VALUE: None
-IMPORTANT NOTES:None
+IMPORTANT NOTES:None
==============================================================================*/
static void
usbs_endpoint_stall(cyg_uint8 endpoint , cyg_uint8 direction)
{
if( direction == OUT )
- {
+ {
usbs_imx_otg_base->endptctrl[endpoint]|= STALL_RX;
- }
- else
+ }
+ else
{
usbs_imx_otg_base->endptctrl[endpoint] |= STALL_TX;
}
usbs_endpoint_unstall(cyg_uint8 endpoint , cyg_uint8 direction)
{
if( direction == OUT )
- {
+ {
usbs_imx_otg_base->endptctrl[endpoint]&= ~STALL_RX;
- }
- else
+ }
+ else
{
usbs_imx_otg_base->endptctrl[endpoint]&= ~STALL_TX;
}
ARGUMENTS PASSED: cyg_uint8 direction OUT Receive Status Command From Host
IN Send Status Command to Host
RETURN VALUE: None
-IMPORTANT NOTES:
+IMPORTANT NOTES:
===============================================================================*/
-static void
+static void
usbs_status_phase(cyg_uint8 trans_type, cyg_uint8 direction)
{
usb_buffer_descriptor_t bd ;
-
+
/* Buffer pointer is not used for EP0 */
bd.buffer = (cyg_uint32 *) 0xFFFFFFFF;
bd.size = 0x0;
-
+
if(trans_type==CONTROL)
{
switch ( direction )
{
switch ( direction )
{
- case OUT :
+ case OUT :
/* Send ZERO length Length Data */
//usbs_ep2_send_data(EP2,&bd,FALSE);
break;
//usbs_ep1_receive_data(EP1,&bd);
break;
}
- }
-
+ }
+
}
// ---------------------------------------------------------------------------
// The following static functions are for USB device enumeration processing
/*============================================================================
FUNCTION: usbs_handle_get_descriptor
DESCRIPTION: This function Handle the GET DESCRIPTOR request
-ARGUMENTS PASSED: None
+ARGUMENTS PASSED: None
RETURN VALUE: None
-IMPORTANT NOTES: None
+IMPORTANT NOTES: None
============================================================================*/
static void
usbs_handle_get_descriptor()
break;
}
-
+
}
/*=============================================================================
FUNCTION: usbs_handle_get_device_desc
DESCRIPTION: This function Handle the GET DEVICE DESCRIPTOR request
ARGUMENTS PASSED: None
RETURN VALUE: None
-IMPORTANT NOTES: None
+IMPORTANT NOTES: None
==============================================================================*/
-static void
+static void
usbs_handle_get_device_desc(void)
{
usb_buffer_descriptor_t bd ;
cyg_uint8 zlt = 0;//0 means false
USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - get device descriptor\n");
-
+
/* get the buffer address for data transfer over EP0 */
buffer_addrs = g_bulkbuffer_map.ep0_buffer_addrs; //256bytes before the two Bulk buffers
-
+
/* Fill the buffer with the descriptor data */
usbs_ep0in_fill_buffer(FILL_DEVICE_DESC,buffer_addrs);
desc_length = g_usb_setup_data[WLENGTH_LOWBYTE];
desc_length |= ( g_usb_setup_data[WLENGTH_HIGHBYTE] <<0x8);
- /* If requested length of descriptor is lesser than actual length of descriptor then send
+ /* If requested length of descriptor is lesser than actual length of descriptor then send
* requested length of descroptor only else send the actual length of descriptor*/
if( g_usb_dev_state == USB_DEV_DEFAULT_STATE )
{
bd.size = MPS_8;
}
- else
+ else
{
bd.size = USB_DEV_DESC_LEN;
}
/* Send descriptor - Data Phase*/
usbs_ep0_send_data(&bd,zlt); //zlt is false=>not zero length packet
//send dev descriptor to host.
-
+
/* Status Phase -- OUT */
usbs_status_phase(CONTROL,OUT); //Get Zero-length data packet from Host, Device sends status: ACK(success), NAK(busy), or STALL(failed)
-
+
}
/*=============================================================================
FUNCTION: usbs_handle_get_config_desc
DESCRIPTION: This function Handle the GET CONFIGURATION DESCRIPTOR request
ARGUMENTS PASSED:
RETURN VALUE: None
-IMPORTANT NOTES:None
+IMPORTANT NOTES:None
=============================================================================*/
-static void
+static void
usbs_handle_get_config_desc(void)
{
usb_buffer_descriptor_t bd;
/* Fill the buffer with the descriptor data */
usbs_ep0in_fill_buffer(FILL_CONF_DESC, buffer_addrs);
-
+
/* total length of descriptor */
desc_length = ((g_usb_desc.config_desc->usb_config_desc.total_length_lo) \
| ( g_usb_desc.config_desc->usb_config_desc.total_length_hi << 0x8 ));
desc_length_req |= ( g_usb_setup_data[WLENGTH_HIGHBYTE] <<0x8);
- /* If requested length of descriptor is lesser than actual length of descriotor then send
+ /* If requested length of descriptor is lesser than actual length of descriotor then send
* requested length of descroptor only else send the actual length of descriptor*/
if(desc_length_req <= desc_length)
{
zlt = 1;
}
}
- usbs_ep0_send_data(&bd,zlt);
-
+ usbs_ep0_send_data(&bd,zlt);
+
/* Status Phase -- OUT */
- usbs_status_phase(CONTROL,OUT);
-
+ usbs_status_phase(CONTROL,OUT);
+
}
/*=============================================================================
FUNCTION: usbs_handle_get_string_desc
DESCRIPTION: This function Handle the GET STRING DESCRIPTOR request
ARGUMENTS PASSED: None
-RETURN VALUE: None
-IMPORTANT NOTES: None
+RETURN VALUE: None
+IMPORTANT NOTES: None
==============================================================================*/
-static void
+static void
usbs_handle_get_string_desc(void)
{
usb_buffer_descriptor_t bd;
cyg_uint16 length_of_desc = 0x0;
int zlt = 0;
-
- /* Get Buufer to fill the data to be received/transmitted. */
+
+ /* Get Buufer to fill the data to be received/transmitted. */
buffer_addrs = g_bulkbuffer_map.ep0_buffer_addrs;
-
+
/* Get the length of descriptor requested */
desc_length_req = g_usb_setup_data[WLENGTH_LOWBYTE];
desc_length_req |= ( g_usb_setup_data[WLENGTH_HIGHBYTE] <<0x8);
{
case STR_DES0:
usbs_ep0in_fill_buffer(FILL_STR_DES0,buffer_addrs);
- /* If requested length of descriptor is lesser than actual length of descriotor then send
+ /* If requested length of descriptor is lesser than actual length of descriotor then send
* requested length of descroptor only else send the actual length of descriptor*/
if(desc_length_req <= g_usb_desc.str_desc0->length )
{
}
}
/* Data Phase -- IN */
- usbs_ep0_send_data(&bd,zlt);
+ usbs_ep0_send_data(&bd,zlt);
/* Status Phase -- OUT */
- usbs_status_phase(CONTROL,OUT);
+ usbs_status_phase(CONTROL,OUT);
USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - get string descriptor 0\n");
break;
-
+
case STR_DES1: /*iManufacturer */
usbs_ep0in_fill_buffer(FILL_STR_DES1,buffer_addrs);
- /* If requested length of descriptor is lesser than actual length of descriotor then send
+ /* If requested length of descriptor is lesser than actual length of descriotor then send
* requested length of descroptor only else send the actual length of descriptor*/
if(desc_length_req <= g_usb_desc.str_desc1->length )
{
else
{
bd.size = g_usb_desc.str_desc1->length;
- if ( bd.size > MPS_64)
+ if ( bd.size > MPS_64)
{
zlt = 1;
}
}
/* Data Phase -- IN */
- usbs_ep0_send_data(&bd,zlt);
+ usbs_ep0_send_data(&bd,zlt);
/* Status Phase -- OUT */
- usbs_status_phase(CONTROL,OUT);
+ usbs_status_phase(CONTROL,OUT);
USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - get string descriptor 1\n");
break;
-
+
case STR_DES2: /*iProduct */
usbs_ep0in_fill_buffer(FILL_STR_DES2,buffer_addrs );
- length_of_desc = g_usb_desc.str_desc2->length;
- /* If requested length of descriptor is lesser than actual length of descriotor then send
+ length_of_desc = g_usb_desc.str_desc2->length;
+ /* If requested length of descriptor is lesser than actual length of descriotor then send
* requested length of descroptor only else send the actual length of descriptor*/
if(desc_length_req <= length_of_desc )
{
}
}
/* Data Phase -- IN */
- usbs_ep0_send_data(&bd,zlt);
+ usbs_ep0_send_data(&bd,zlt);
/* Status Phase -- OUT */
- usbs_status_phase(CONTROL,OUT);
+ usbs_status_phase(CONTROL,OUT);
USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - get string descriptor 2\n");
break;
-
- case STR_DES3:
+
+ case STR_DES3:
/* send zero length data */
usbs_status_phase(CONTROL,IN);
/* Status Phase -- OUT */
usbs_status_phase(CONTROL,OUT);
break;
-
+
case STR_DES5: /*iSerialNumber */
#if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT)
usbs_ep0in_fill_buffer(FILL_SN_DESC,buffer_addrs );
- /* If requested length of descriptor is lesser than actual length of descriotor then send
+ /* If requested length of descriptor is lesser than actual length of descriotor then send
* requested length of descroptor only else send the actual length of descriptor*/
if(desc_length_req <= g_usb_desc.sn_desc->length )
{
}
}
/* Data Phase -- IN */
- usbs_ep0_send_data(&bd,zlt);
+ usbs_ep0_send_data(&bd,zlt);
/* Status Phase -- OUT */
- usbs_status_phase(CONTROL,OUT);
+ usbs_status_phase(CONTROL,OUT);
USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - get string descriptor - SN\n");
break;
#endif
case STR_DES4: /*iSerialNumber */
usbs_ep0in_fill_buffer(FILL_STR_DES3,buffer_addrs );
- /* If requested length of descriptor is lesser than actual length of descriotor then send
+ /* If requested length of descriptor is lesser than actual length of descriotor then send
* requested length of descroptor only else send the actual length of descriptor*/
if(desc_length_req <= g_usb_desc.str_desc3->length )
{
}
}
/* Data Phase -- IN */
- usbs_ep0_send_data(&bd,zlt);
+ usbs_ep0_send_data(&bd,zlt);
/* Status Phase -- OUT */
- usbs_status_phase(CONTROL,OUT);
+ usbs_status_phase(CONTROL,OUT);
USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - get string descriptor 3\n");
break;
default:
break;
}
-
+
}
/*=============================================================================
DESCRIPTION: This function Handle the SET ADDRESS Request from USB Host
ARGUMENTS PASSED: None
RETURN VALUE: None
-IMPORTANT NOTES:
+IMPORTANT NOTES:
==============================================================================*/
-static void
+static void
usbs_handle_set_address(void)
{
cyg_uint16 device_addrs;
- USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - set address handler\n");
+ USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - set address handler\n");
/* Get the Device Address to be SET from the Setup Data */
device_addrs = g_usb_setup_data[WVALUE_LOWBYTE] + (g_usb_setup_data[WVALUE_HIGHBYTE]<<8);
-
+
if ((g_usb_setup_data[WINDEX_LOWBYTE] == 0) &&
(g_usb_setup_data[WINDEX_HIGHBYTE] == 0) &&
(g_usb_setup_data[WLENGTH_LOWBYTE] == 0) &&
(g_usb_setup_data[WLENGTH_HIGHBYTE] == 0) &&
(device_addrs <= USB_MAX_DEVICE_ADDR))
- {
+ {
switch(g_usb_dev_state)
{
case USB_DEV_DEFAULT_STATE :
g_usb_dev_state = USB_DEV_ADDRESSED_STATE;
}
break;
-
+
case USB_DEV_ADDRESSED_STATE :
/* Send Ack to Host */
usbs_status_phase(CONTROL,IN);
/* Set the Device Address */
USBS_DEVICE_SET_ADDRESS(USB_DEFAULT_ADDR);
/* Change state to ADDRESSED STATE */
- g_usb_dev_state = USB_DEV_DEFAULT_STATE;
+ g_usb_dev_state = USB_DEV_DEFAULT_STATE;
}
else
{
USBS_DEVICE_SET_ADDRESS(device_addrs);
}
break;
-
+
case USB_DEV_CONFIGURED_STATE :
if ( device_addrs == USB_DEFAULT_ADDR)
{
/* Set the Device Address */
USBS_DEVICE_SET_ADDRESS(device_addrs);
/* Change state to ADDRESSED STATE */
- g_usb_dev_state = USB_DEV_DEFAULT_STATE;
+ g_usb_dev_state = USB_DEV_DEFAULT_STATE;
}
else
{
- /* Send STALL Handshake */
+ /* Send STALL Handshake */
usbs_endpoint_stall(EP0,IN);
}
default :
usbs_endpoint_stall(EP0,IN);
}
-
+
}
/*=============================================================================
FUNCTION: usbs_handle_get_configuration
DESCRIPTION: This function Handle the GET CONFIGURATION request
-ARGUMENTS PASSED: None
-RETURN VALUE: None
-IMPORTANT NOTES: None
+ARGUMENTS PASSED: None
+RETURN VALUE: None
+IMPORTANT NOTES: None
=============================================================================*/
-static void
+static void
usbs_handle_get_configuration(void)
{
usb_buffer_descriptor_t bd;
cyg_uint32 buffer_addrs;
cyg_uint32* buffer_ptr;
-
+
if((g_usb_setup_data[WINDEX_LOWBYTE] == 0) &&
(g_usb_setup_data[WINDEX_HIGHBYTE] == 0) &&
(g_usb_setup_data[WVALUE_LOWBYTE] == 0) &&
(g_usb_setup_data[WVALUE_HIGHBYTE] == 0) &&
(g_usb_setup_data[WLENGTH_LOWBYTE] == LEN_OF_CONFIG_VALUE) &&
- (g_usb_setup_data[WLENGTH_HIGHBYTE] == 0))
+ (g_usb_setup_data[WLENGTH_HIGHBYTE] == 0))
{
switch(g_usb_dev_state)
{
bd.size=LEN_OF_CONFIG_VALUE;
usbs_ep0_send_data(&bd,0);
-
+
/* Receive Ack from Host*/
usbs_status_phase(CONTROL,OUT);
break;
usbs_endpoint_stall(EP0,IN);
}
- }
+ }
USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - get config handler\n");
}
/*=============================================================================
FUNCTION: usbs_handle_set_configuration
DESCRIPTION: This function Handle the SET CONFIGURATION request
-ARGUMENTS PASSED: None
-RETURN VALUE: None
-IMPORTANT NOTES: None
+ARGUMENTS PASSED: None
+RETURN VALUE: None
+IMPORTANT NOTES: None
=============================================================================*/
-static void
+static void
usbs_handle_set_configuration(void)
{
- usb_end_pt_info_t config_data ;
+ usb_end_pt_info_t config_data ;
cyg_uint8 i;
switch (g_usb_dev_state)
{
case USB_DEV_ADDRESSED_STATE :
if (g_usb_setup_data[WVALUE_LOWBYTE] == USB_DEV_VALUE_OF_UNCONFIG)
- {
+ {
/* Send Ack to Host*/
usbs_status_phase(CONTROL,IN);
}
/* Configure endpoints */
for ( i = 0 ; i< g_number_of_endpoints ; i++)
{
- config_data.end_pt_no = g_end_pt_info[i].end_pt_no;
+ config_data.end_pt_no = g_end_pt_info[i].end_pt_no;
config_data.direction = g_end_pt_info[i].direction;
config_data.transfer_type = g_end_pt_info[i].transfer_type;
config_data.max_pkt_size = g_end_pt_info[i].max_pkt_size;
-
+
usbs_imx_otg_dev_set_configuration(&config_data);
}
//USBDBGMSG("+USBDBGMSG:EP0 IN stalled at set conf in addr state\n");
}
USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - set conf@ADDRESSED_STATE\n");
- break;
+ break;
case USB_DEV_CONFIGURED_STATE :
if(g_usb_setup_data[WVALUE_LOWBYTE] == USB_DEV_CONFIG_DESC_CONFIG_VALUE)
{
usbs_status_phase(CONTROL,IN);
}
else if (g_usb_setup_data[WVALUE_LOWBYTE] == USB_DEV_VALUE_OF_UNCONFIG)
- {
+ {
/* Send Ack to Host*/
usbs_status_phase(CONTROL,IN);
/* Send STALL Handshake */
usbs_endpoint_stall(EP0,IN);
USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - set conf@incorrect state\n");
- break;
+ break;
}
USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - set config handler\n");
FUNCTION: usbs_handle_msc_get_maxlun
DESCRIPTION: This function Handle the GET MAX LUN Mass Storage class
specific request
-ARGUMENTS PASSED: None
-RETURN VALUE: None
-IMPORTANT NOTES: None
+ARGUMENTS PASSED: None
+RETURN VALUE: None
+IMPORTANT NOTES: None
=============================================================================*/
-static void
+static void
usbs_handle_msc_get_maxlun(void)
{
usb_buffer_descriptor_t bd ;
cyg_uint8 zlt = 0;//0 means false
cyg_uint8 Max_Lun=0;
USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: MASS - Get MAX LUN\n");
-
+
/* get the buffer address for data transfer over EP0 */
buffer_addrs = g_bulkbuffer_map.ep0_buffer_addrs; //256bytes before the two Bulk buffers
{
/* Fill the buffer with the descriptor data */
*(cyg_uint8 *)buffer_addrs = 0;//Max_Lun;
- bd.size = 0;
+ bd.size = 0;
}
else
{
*(cyg_uint8 *)buffer_addrs = Max_Lun;
bd.size = desc_length;
}
-
+
/* Send descriptor - Data Phase*/
usbs_ep0_send_data(&bd,zlt); //zlt is false=>not zero length packet
//send dev descriptor to host.
-
+
/* Status Phase -- OUT */
usbs_status_phase(CONTROL,OUT); //Get Zero-length data packet from Host, Device sends status: ACK(success), NAK(busy), or STALL(failed)
-
+
}
/*=============================================================================
FUNCTION: usbs_ep0in_fill_buffer
-DESCRIPTION: This function is used to fill the corresponding
+DESCRIPTION: This function is used to fill the corresponding
response for the data phase of SETUP Transfer
ARGUMENTS PASSED:
cyg_uint8 type: type of descriptor
- cyg_uint32 buffer_addrs - buffer pointer to be filled
+ cyg_uint32 buffer_addrs - buffer pointer to be filled
RETURN VALUE: None
IMPORTANT NOTES:None
=============================================================================*/
-static void
+static void
usbs_ep0in_fill_buffer(cyg_uint8 type, cyg_uint32 buffer_addrs)
{
const cyg_uint8 *data=0;
- cyg_uint32 *buffer_page = (cyg_uint32*)buffer_addrs;
+ cyg_uint32 *buffer_page = (cyg_uint32*)buffer_addrs;
int k = 0;
//USBDBGMSG("+USBDBGMSG: enum - copy descriptor to buffer\n");
switch (type)
break;
case FILL_CONF_DESC: /*8*32 bit */
data = (cyg_uint8 *)g_usb_desc.config_desc;
- break;
+ break;
case FILL_STR_DES0: /*1*32 bit */
data = (cyg_uint8 *)g_usb_desc.str_desc0;
- break;
+ break;
case FILL_STR_DES1: /*7*32 bit */
- data =(cyg_uint8 *)g_usb_desc.str_desc1;
- break;
+ data =(cyg_uint8 *)g_usb_desc.str_desc1;
+ break;
case FILL_STR_DES2: /*7*32 bit */
data = (cyg_uint8 *)g_usb_desc.str_desc2;
- break;
+ break;
case FILL_STR_DES3: /*6*32 bit */
data = (cyg_uint8 *)g_usb_desc.str_desc3;
break;
break;
#endif
}
-
+
for (k=0; k<(MPS_64/sizeof(cyg_uint32)); k++)
{
- *buffer_page = data[0] + (data[1] << 8) + (data[2] << 16) + (data[3] << 24);
+ *buffer_page = data[0] + (data[1] << 8) + (data[2] << 16) + (data[3] << 24);
//USBDBGMSG("+USBDBGMSG: desc[k] = 0x%x\n",(*buffer_page));
buffer_page++;
data += 4;
-
+
}
-
+
}
/*=============================================================================
FUNCTION: usbs_ep0_init_dqh
DESCRIPTION: This function is used to initialize the queue header of EP0
-ARGUMENTS PASSED: NONE
+ARGUMENTS PASSED: NONE
RETURN VALUE: NONE
IMPORTANT NOTES: called by usbs_imx_otg_dev_ep0_init(),usbs_imx_otg_dev_handle_bus_reset()
=============================================================================*/
cyg_uint32 total_bytes;
volatile cyg_uint32 * ep_q_hdr_base;
cyg_int8 i;
-
+
//clear queue header
ep_q_hdr_base = ((volatile cyg_uint32 *)g_bulkbuffer_map.ep_dqh_base_addrs);
/* Clear the dQH Memory */
{
*ep_q_hdr_base++ = 0;
}
-
+
/******************************************************************************
/ =================
/ dQH0 for EP0OUT
/ =================
/ Initialize device queue heads in system memory
/ 8 bytes for the 1st setup packet */
-
+
total_bytes = 0x8;
qhead.dqh_base = USBS_EP_GET_dQH(EP0,OUT);
qhead.zlt = ZLT_DISABLE;
/ ================*/
}
/*=============================================================================
-FUNCTION: usbs_ep0_send_data
+FUNCTION: usbs_ep0_send_data
DESCRIPTION: This function Send Data to host through EP0-IN Pipe.
ARGUMENTS PASSED:
- usb_buffer_descriptor_t *bd : This is the pointer to the buffer descriptor.
+ usb_buffer_descriptor_t *bd : This is the pointer to the buffer descriptor.
cyg_uint8 zlt : Flag to decide if Zero Length Packet to be sent
RETURN VALUE:
- USB_SUCCESS - The buffer was successfully processed by the USB device and
+ USB_SUCCESS - The buffer was successfully processed by the USB device and
data sent to the Host.
USB_FAILURE - Some failure occurred in transmitting the data.
-IMPORTANT NOTES: None
+IMPORTANT NOTES: None
=============================================================================*/
-static usb_status_t
+static usb_status_t
usbs_ep0_send_data(usb_buffer_descriptor_t* bd,cyg_uint8 zlt)
{
struct dtd_t td;
cyg_uint32 total_bytes ;
cyg_uint32 dtd_address,dqh_address;
-
+
usb_status_t status = USB_FAILURE;
/* Get Device Transfer Descriptor of the requested endpoint */
dtd_address = USBS_EP_GET_dTD(EP0,IN);
-
+
/* Get Device Queue head of the requested endpoint */
dqh_address = USBS_EP_GET_dQH(EP0,IN);
total_bytes = bd->size;
/* Setup Transfer Descriptor for EP0 IN*/
- td.dtd_base = dtd_address;
+ td.dtd_base = dtd_address;
td.next_link_ptr = 0;
td.terminate = TERMINATE;
td.total_bytes = total_bytes;
td.buffer_ptr2 = 0;
td.buffer_ptr3 = 0;
td.buffer_ptr4 = 0;
-
- /* Set the transfer descriptor */
+
+ /* Set the transfer descriptor */
usbs_setup_transdesc(&td);
-
+
/* Enable ZLT when data size is in multiple of Maximum Packet Size */
if(zlt)
{
/* set ZLT enable */
(*(volatile cyg_uint32*)(dqh_address)) &= ~0x20000000;
}
-
+
/* 1. write dQH next ptr and dQH terminate bit to 0 */
- *(volatile cyg_uint32*)(dqh_address+0x8)= (dtd_address);
-
+ *(volatile cyg_uint32*)(dqh_address+0x8)= (dtd_address);
+
/* 2. clear active & halt bit in dQH */
*(volatile cyg_uint32*)(dqh_address+0xC) &= ~0xFF;
-
+
/* 3. prime endpoint by writing '1' in ENDPTPRIME */
usbs_imx_otg_base->endptprime |= BIT16;
-
+
/* wait for complete set and clear */
while (!(usbs_imx_otg_base->endptcomplete & EPIN_COMPLETE));
-
+
usbs_imx_otg_base->endptcomplete = EPIN_COMPLETE;
-
+
status = USB_SUCCESS;
return status;
FUNCTION: usbs_ep0_recevie_data
DESCRIPTION: This function Handle the Status Token (IN/OUT) from USB Host
ARGUMENTS PASSED:
- usb_buffer_descriptor_t *bd : This is the pointer to the buffer descriptor.
+ usb_buffer_descriptor_t *bd : This is the pointer to the buffer descriptor.
RETURN VALUE:
- USB_SUCCESS - : The buffer was successfully processed by the USB device and
+ USB_SUCCESS - : The buffer was successfully processed by the USB device and
data is received from the host.
USB_FAILURE - : Some failure occurred in receiving the data.
USB_INVALID - : If the endpoint is invalid.
-IMPORTANT NOTES:None
+IMPORTANT NOTES:None
=============================================================================*/
static usb_status_t usbs_ep0_receive_data(usb_buffer_descriptor_t* bd)
{
/* Get Device Device Queue Head of the requested endpoint */
dqh_address = USBS_EP_GET_dQH(EP0, OUT);
-
+
/* Get Device Transfer Descriptor of the requested endpoint */
dtd_address = USBS_EP_GET_dTD(EP0, OUT);
/* Get the total bytes to be received */
- total_bytes = bd->size;
-
+ total_bytes = bd->size;
+
td.dtd_base = dtd_address;
td.next_link_ptr = dtd_address + 0x20;
td.terminate = TERMINATE;
td.buffer_ptr2 = 0;
td.buffer_ptr3 = 0;
td.buffer_ptr4 = 0;
-
+
/* Set the Transfer Descriptor */
usbs_setup_transdesc(&td);
/* 1. write dQH next ptr and dQH terminate bit to 0 */
*(volatile cyg_uint32*)(dqh_address+0x8)= dtd_address;
-
+
/* 2. clear active & halt bit in dQH */
*(volatile cyg_uint32*)(dqh_address+0xC) &= ~0xFF;
-
+
/* 3. prime endpoint by writing '1' in ENDPTPRIME */
usbs_imx_otg_base->endptprime |= ( EPOUT_PRIME << EP0 );
/* 4. Wait for the Complete Status */
while (!((usbs_imx_otg_base->endptprime) & ( EPOUT_COMPLETE << EP0)));
-
+
/*clear the complete status */
usbs_imx_otg_base->endptprime = (EPOUT_COMPLETE << EP0);
-
+
status = USB_SUCCESS;
return status;
volatile struct dqh_setup_t * dqh_word ;
cyg_uint32 dqh_address;
cyg_uint32 temp;
-
+
//USBDBGMSG("+USBDBGMSG: enter ep0 dsr.\n");
/* 1. Receive Setup Data*/
bd.buffer = (cyg_uint32 *)g_usb_setup_data;
bd.size = 0;
-
- /* Get the Device Queue Head Address for EP0 OUT */
+
+ /* Get the Device Queue Head Address for EP0 OUT */
dqh_address = USBS_EP_GET_dQH(EP0,OUT);
dqh_word = (volatile struct dqh_setup_t*)dqh_address;
-
+
/* write '1' to clear corresponding bit in ENDPTSETUPSTAT */
temp = usbs_imx_otg_base->endptsetupstat;
- usbs_imx_otg_base->endptsetupstat = temp;
+ usbs_imx_otg_base->endptsetupstat = temp;
// if(usbs_imx_otg_base->endptsetupstat & BIT0)
-// usbs_imx_otg_base->endptsetupstat = BIT0;
-
+// usbs_imx_otg_base->endptsetupstat = BIT0;
+
do{
/* write '1' to Setup Tripwire (SUTW) in USBCMD register */
usbs_imx_otg_base->usbcmd |= BIT13;
-
+
/* Copy the SetupBuffer into local software byte array */
temp = (dqh_word->dqh_word10);
(bd.buffer) =(cyg_uint8 *)(bd.buffer) + 1;
*((cyg_uint8 *)(bd.buffer)) = (cyg_uint8 )((temp & 0xFF000000)>>24);
(bd.buffer) =(cyg_uint8 *)(bd.buffer) + 1;
-
+
temp = (dqh_word->dqh_word11);
*((cyg_uint8 *)(bd.buffer)) = (cyg_uint8 )(temp & 0x000000FF);
(bd.buffer) =(cyg_uint8 *)(bd.buffer) + 1;
(bd.buffer) =(cyg_uint8 *)(bd.buffer) + 1;
*((cyg_uint8 *)(bd.buffer)) = (cyg_uint8 )((temp & 0xFF000000)>>24);
(bd.buffer) =(cyg_uint8 *)(bd.buffer) + 1;
- }while (!(usbs_imx_otg_base->usbcmd & BIT13));
-
+ }while (!(usbs_imx_otg_base->usbcmd & BIT13));
+
/* Write '0' to clear SUTW in USBCMD register */
usbs_imx_otg_base->usbcmd &= ~BIT13;
status = USB_SUCCESS;
}
USBDBGMSG("(MSB)\n");
#endif
-
+
/* 2. Process Setup Data*/
/* switch construct to handle different request*/
/* Parser the Setup Request Type */
- switch (g_usb_setup_data[BREQUEST])
- {
+ switch (g_usb_setup_data[BREQUEST])
+ {
case USB_GET_DESCRIPTOR:
/* Handle the GET DESCRIPTOR Request */
usbs_handle_get_descriptor();
break;
-
+
case USB_SET_ADDRESS:
/* Handle the SET ADDRESS Request */
usbs_handle_set_address();
break;
-
+
case USB_SET_CONFIGURATION:
/* Handle the SET CONFIGURATION Request */
if ((g_usb_setup_data[WINDEX_LOWBYTE] == 0) &&
(g_usb_setup_data[WINDEX_HIGHBYTE] == 0)&&
(g_usb_setup_data[WLENGTH_LOWBYTE] == 0)&&
(g_usb_setup_data[WLENGTH_HIGHBYTE] == 0)&&
- (g_usb_setup_data[WVALUE_HIGHBYTE] == 0))
+ (g_usb_setup_data[WVALUE_HIGHBYTE] == 0))
{
usbs_handle_set_configuration();
}
//USBDBGMSG("+USBDBGMSG:EP0 IN stalled at set conf in ep0 dsr\n");
}
break;
-
+
case USB_GET_CONFIGURATION:
/* GET CONFIGURATION request handler */
usbs_handle_get_configuration();
usbs_handle_msc_get_maxlun();
break;
case USB_MSC_BOT_RESET:
-
+
default:
/* Send STALL Handshake */
- usbs_endpoint_stall(EP0,IN);
+ usbs_endpoint_stall(EP0,IN);
USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG:EP0 IN stalled in ep0 dsr\n");
USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG:Setup Request Type 0x%02x,0x%02X\n",g_usb_setup_data[BMREQUESTTYPE],g_usb_setup_data[BREQUEST]);
break;
}
-
+
USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: ep0 dsr\n");
}
/*=============================================================================
{
/*fill the structure for ep0*/
if ((EP0_STATE_IDLE != ep0.ep_state) &&
- ((usbs_control_return (*)(usbs_control_endpoint*, int)) 0 != ep0.common.complete_fn))
+ ((usbs_control_return (*)(usbs_control_endpoint*, int)) 0 != ep0.common.complete_fn))
{
#if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT)
(*ep0.common.complete_fn)(&ep0.common, -EPIPE);
usbs_imx_otg_dev_ep0_start(usbs_control_endpoint* endpoint)
{
cyg_uint32 temp;
-
+
CYG_ASSERT( endpoint == &ep0.common, "USB startup involves the wrong endpoint");
-
+
/*clear all interrupt status bits*/
temp = usbs_imx_otg_base->usbsts;
usbs_imx_otg_base->usbsts = temp; //clear all the previous interrupts
-
+
/*enable all the sub-interrupt sources for USB device*/
USBS_IMX_OTG_INTR_UNMASK(IMX_USB_INTR_DEV_PCE|IMX_USB_INTR_DEV_RESET|IMX_USB_INTR_DEV_USBINT);
-
+
/*set Run/Stop bit to Run Mode*/
- usbs_imx_otg_base->usbcmd |= BIT0;
+ usbs_imx_otg_base->usbcmd |= BIT0;
USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: mx37 ep0 start.\n");
}
cyg_uint32 dqh_address;
cyg_uint32 received_buffer_addrs = 0x0;
cyg_uint32 received_data_length = 0x0;
- cyg_uint32* temp = 0x0;
+ cyg_uint32* temp = 0x0;
- int i;
-
- if(g_usb_dev_state != USB_DEV_CONFIGURED_STATE)
+ if (g_usb_dev_state != USB_DEV_CONFIGURED_STATE)
return; //EP1 only receives data when the USB device has been configured
-
- if(ep1.common.buffer == NULL)
- {
+
+ if (ep1.common.buffer == NULL) {
USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep1_rx_complete: NULL buffer \n");
return; //there is not a buffer used to store the data from host
- }
-
+ }
+
/* Get Device Device Queue Head of the out endpoint */
dqh_address = USBS_EP_GET_dQH(EP1,OUT);
-
+
/* Get Device Transfer Descriptor of the out endpoint */
dtd_address = USBS_EP_GET_dTD(EP1,OUT);
-
+
/*clear the complete status */
usbs_imx_otg_base->endptcomplete |= (EPOUT_COMPLETE << EP1);
//received_buffer_addrs = (*((unsigned int *)dtd_address + 2)) & 0xFFFFF000;
received_buffer_addrs = (cyg_uint32)ep1.common.buffer;
USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep1_rx_complete: received_buffer_addrs 0x%08X \n",received_buffer_addrs);
- if( received_buffer_addrs == 0)
- {
+ if ( received_buffer_addrs == 0) {
USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep1_rx_complete: NULL rx buffer \n");
return;
}
-
+
/* calculate the received data length using number of bytes left in TD */
temp = (cyg_uint32 *)dtd_address;
temp++; //pointer to total bytes in dtd, second work in dTD
else if((g_bulk_out_sector_number_is_one == 1)&&(received_data_length!=31)) //last bulk out data sector
g_bulk_out_transdesc_buffer_offset = 1;
#endif
-
+
/* tell ep1 how many bytes data is received*/
- ep1.fetched = received_data_length;
-
- if(ep1.fetched)
+ ep1.fetched = received_data_length;
+
+ if(ep1.fetched)
{
if(ep1.fetched == 31)
g_received_data_type = MASS_STORAGE_CBW_TYPE;
- else
+ else
g_received_data_type = MASS_STORAGE_DATA_TYPE;
ep1.common.complete_data = (void*)(ep1.common.buffer);
ep1.common.buffer_size = 0;
ep1_start_rx((usbs_rx_endpoint *)(&(ep1.common))); //prevent to receive more CBW before processing done
}
-
+
#if 0
if(ep1.fetched == 31)
{
USBDBGMSG(DEBUG_TRANS,"\n");
}
#endif
-
-
+
+
}
/*=============================================================================
// Start to receive data from host. This functionality is overloaded to cope with
// waiting for stalls to complete.
-// The transfer descriptor is prepared
+// The transfer descriptor is prepared
=============================================================================*/
static void
ep1_start_rx(usbs_rx_endpoint* endpoint)
cyg_uint32 dqh_address;
cyg_uint32 buffer_addrs_page0;
- if(g_usb_dev_state != USB_DEV_CONFIGURED_STATE)
+ if(g_usb_dev_state != USB_DEV_CONFIGURED_STATE)
return; //EP1 only receives data when the USB device has been configured
#if 0 //don't check to prevent EP1 from receiving data before processing the previous.
if(endpoint->buffer == NULL)
#endif
/* Get Device Device Queue Head of the out endpoint */
dqh_address = USBS_EP_GET_dQH(EP1,OUT);
-
+
/* Get Device Transfer Descriptor of the out endpoint */
dtd_address = USBS_EP_GET_dTD(EP1,OUT);
/* ==Prepare TD for next bulk out transfer== */
/* get the dTD buffer pointer */
buffer_addrs_page0 = (cyg_uint32)(endpoint->buffer);
-
+
/* Get the total bytes to be received */
total_bytes = endpoint->buffer_size;
-
+
/* OUT setup dTD */
- td.dtd_base = dtd_address;
+ td.dtd_base = dtd_address;
td.next_link_ptr = dtd_address + 0x20;
td.terminate = TERMINATE;
td.total_bytes = total_bytes;
td.ioc = IOC_SET;
td.status = ACTIVE;
- td.buffer_ptr0 = buffer_addrs_page0 ;
- td.current_offset = ( buffer_addrs_page0 & 0xFFF ) + g_td_buffer_offset;
+ td.buffer_ptr0 = buffer_addrs_page0 ;
+ td.current_offset = ( buffer_addrs_page0 & 0xFFF ) + g_td_buffer_offset;
td.buffer_ptr1 = 0;
td.buffer_ptr2 = 0;
td.buffer_ptr3 = 0;
td.buffer_ptr2 = (td.buffer_ptr1 + BULK_TD_BUFFER_PAGE_SIZE);
if(total_bytes > BULK_TD_BUFFER_PAGE_SIZE*3)
td.buffer_ptr3 = (td.buffer_ptr2 + BULK_TD_BUFFER_PAGE_SIZE);
-
+
/* Set the Transfer Descriptor */
usbs_setup_transdesc(&td);
/* 1. write dQH next ptr and dQH terminate bit to 0 */
*(volatile cyg_uint32 *)(dqh_address+0x8)= dtd_address;
-
+
/* 2. clear active & halt bit in dQH */
*(volatile cyg_uint32 *)(dqh_address+0xC) &= ~0xFF;
- /* 3. prime endpoint by writing '1' in ENDPTPRIME
+ /* 3. prime endpoint by writing '1' in ENDPTPRIME
prime bulk out endpoint after sending the CSW of last command
*/
//usbs_imx_otg_base->endptprime |= ( EPOUT_PRIME << EP1 );
// Updating the stalled flag means that the DSR will do nothing.
usbs_endpoint_stall(EP1,OUT);
ep1.common.halted = 1;
- }
+ }
else {
- // Take care of the hardware so that a new transfer is allowed.
+ // Take care of the hardware so that a new transfer is allowed.
usbs_endpoint_unstall(EP1,OUT);
ep1.common.halted = 0;
}
{
int result = 0; //contains the actual recevied data length from bulk-out endpoint
g_received_data_type = 0;//MASS_STORAGE_CBW_TYPE
-
+
if(ep1.common.buffer)//buffer of TD is not null, then receive
{
ep1_rx_complete(result);
}
//USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep1 dsr - result = %d\n",result);
//recevie mass storage device CBW
-
+
if((ep1.fetched == 31)&&(g_received_data_type == MASS_STORAGE_CBW_TYPE))
{
USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep1 dsr - CBW received\n");
}
else
USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep1 dsr - received %d byte\n",ep1.fetched);
-
+
}
/*=============================================================================
static void
usbs_imx_otg_dev_ep1_init(void)
{
- //at present, ep1.common.buffer is NULL. The buffer should be initialized
+ //at present, ep1.common.buffer is NULL. The buffer should be initialized
//by upper layer caller.
/*buffer is assigned in MSC initialization*/
-
+
// Endpoints should never be halted during a start-up.
ep1.common.halted = 0; //false =0, true =1
ep1.common.complete_fn = ep1_rx_complete;
{
void (*complete_fn)(void*, int) = ep2.common.complete_fn;
void* complete_data = ep2.common.complete_data;
-
+
ep2.common.buffer = (unsigned char*) 0;
ep2.common.buffer_size = 0;
ep2.common.complete_fn = (void (*)(void*, int)) 0;
ep2.common.complete_data = (void*) 0;
- if ((void (*)(void*, int))0 != complete_fn) {
- (*complete_fn)(complete_data, result);
+ if (NULL != complete_fn) {
+ complete_fn(complete_data, result);
}
}
/* Get Device Transfer Descriptor of the requested endpoint */
dtd_address = USBS_EP_GET_dTD(EP2,IN);
-
+
/* Get Device Queue head of the requested endpoint */
- dqh_address = USBS_EP_GET_dQH(EP2,IN);
-
+ dqh_address = USBS_EP_GET_dQH(EP2,IN);
+
/* allocate memory for data transfer */
buffer_addrs_page0 = endpoint->buffer;
total_bytes = (cyg_uint32)(endpoint->buffer_size);
size = (total_bytes < BULK_TD_BUFFER_TOTAL_SIZE )?total_bytes:(BULK_TD_BUFFER_TOTAL_SIZE);
-
- td.dtd_base = dtd_address;
+
+ td.dtd_base = dtd_address;
td.next_link_ptr = dtd_address + 0x20 ;
td.terminate = TERMINATE;
td.total_bytes = size;
td.ioc = IOC_SET;
td.status = ACTIVE;
td.buffer_ptr0 = buffer_addrs_page0 ;
- td.current_offset = (buffer_addrs_page0 & 0xFFF)+ g_td_buffer_offset;
+ td.current_offset = (buffer_addrs_page0 & 0xFFF)+ g_td_buffer_offset;
td.buffer_ptr1 = 0;
td.buffer_ptr2 = 0;
td.buffer_ptr3 = 0;
if(size > BULK_TD_BUFFER_PAGE_SIZE*3)
td.buffer_ptr3 = (td.buffer_ptr2 + BULK_TD_BUFFER_PAGE_SIZE);
- /* Set the Transfer Descriptor */
+ /* Set the Transfer Descriptor */
usbs_setup_transdesc(&td);
/* 1. write dQH next ptr and dQH terminate bit to 0 */
- *(volatile cyg_uint32 *)(dqh_address+0x8)= (dtd_address);
-
+ *(volatile cyg_uint32 *)(dqh_address+0x8)= (dtd_address);
+
/* 2. clear active & halt bit in dQH */
*(volatile cyg_uint32 *)(dqh_address+0xC) &= ~0xFF;
/* 3. prime endpoint by writing '1' in ENDPTPRIME */
usbs_imx_otg_base->endptprime = ( EPIN_PRIME << EP2 );
-
+
/* wait for complete set and clear */
while (!((usbs_imx_otg_base->endptcomplete) & (EPIN_COMPLETE<<EP2)));
-
+
usbs_imx_otg_base->endptcomplete |= (EPIN_COMPLETE << EP2);
ep2.transmitted = size;
ep2_tx_complete(-EPIPE);
-
+
USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep2 tx done\n");// ep2.transmitted);
-
+
}
/*=============================================================================
// The exported interface to halt the EP2
// Updating the stalled flag means that the DSR will do nothing.
usbs_endpoint_stall(EP2,IN);
ep2.common.halted = 1;
- }
+ }
else {
- // Take care of the hardware so that a new transfer is allowed.
+ // Take care of the hardware so that a new transfer is allowed.
usbs_endpoint_unstall(EP2,IN);
ep2.common.halted = 0;
}
/* EP2 DSR will be called as soon as a transfer complete to clear status*/
usbs_imx_otg_base->endptcomplete |= (EPIN_COMPLETE << EP2);
-
+
if(ep2.common.buffer_size==0)
{
ep2_tx_complete(-EPIPE);
ep2.transmitted = 0; //clear the field to wait for the next transmit
}
-
+
}
/*=============================================================================
static void
usbs_imx_otg_dev_ep2_init(void)
{
- //at initialization, ep2.common.buffer is NULL. The buffer should be initialized
+ //at initialization, ep2.common.buffer is NULL. The buffer should be initialized
//by upper layer caller.
// Endpoints should never be halted after a reset
status = g_isr_status_bits;
g_isr_status_bits = 0;
//cyg_drv_isr_unlock();
-
+
// Reset is special, since it invalidates everything else.
// If the reset is still ongoing then do not attempt any
// further processing, there will just be another interrupt.
// immediately if reset is still asserted, i.e. no threads
// will run, but there is no easy way of triggering action
// at the end of reset.
- if (status & IMX_USB_STS_RESET)
+ if (status & IMX_USB_STS_RESET)
{
- int new_status = usbs_imx_otg_base->usbsts;
- if (0 == (new_status & IMX_USB_STS_RESET))
+ int new_status = usbs_imx_otg_base->usbsts;
+ if (0 == (new_status & IMX_USB_STS_RESET))
{
usbs_imx_otg_dev_handle_bus_reset();
USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: !!USB BUS RESET\n");
- }
-
+ }
+
// This unmask is likely to cause another interrupt immediately
#if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT)
cyg_interrupt_unmask(MX51_IRQ_USB_SERVICE_REQUEST);
#endif
- }
+ }
else if(status & IMX_USB_STS_USBINT)
{
-
+
if(usbs_imx_otg_base->endptsetupstat & BIT0)
- {// if Setup Packet arrived
+ {// if Setup Packet arrived
usbs_imx_otg_dev_ep0_dsr();
}
- else if((usbs_imx_otg_base->endptcomplete) & ( EPIN_COMPLETE << EP2))
+ else if((usbs_imx_otg_base->endptcomplete) & ( EPIN_COMPLETE << EP2))
{// EP2 Queue Header buffer completes sending data
//complete bit is cleared in ep2_start_tx
}
-
-
+
+
else if((usbs_imx_otg_base->endptcomplete) & ( EPOUT_COMPLETE << EP1))
- {// EP1 Queue Header buffer get data
+ {// EP1 Queue Header buffer get data
usbs_imx_otg_dev_ep1_dsr();
-
+
}
else if((usbs_imx_otg_base->endptcomplete) & ( EPOUT_COMPLETE << EP0))
cyg_interrupt_unmask(MX51_IRQ_USB_SERVICE_REQUEST);
#endif
}
- else
+ else
{
#if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT)
// This unmask is likely to cause another interrupt immediately
cyg_interrupt_unmask(MX51_IRQ_USB_SERVICE_REQUEST);
#endif
- }
+ }
+
-
}
/*=============================================================================
// The DSR thread
CYG_ASSERT( 0 != isr_status_bits, "DSR's should only be scheduled when there is work to do");
cyg_semaphore_post(&usbs_imx_otg_dev_sem);
-
+
CYG_UNUSED_PARAM(cyg_vector_t, vector);
CYG_UNUSED_PARAM(cyg_ucount32, count);
CYG_UNUSED_PARAM(cyg_addrword_t, data);
// interrupts in the control register.
status_bits = usbs_imx_otg_base->usbsts;
USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: usb intr 0x%08X\n",status_bits);
- if (status_bits & IMX_USB_STS_RESET)
+ if (status_bits & IMX_USB_STS_RESET)
{
-
+
g_isr_status_bits |= IMX_USB_STS_RESET;
usbs_imx_otg_base->usbsts |= IMX_USB_STS_RESET;
cyg_interrupt_mask(IMX_IRQ_USB_DEV_SERVICE_REQUEST);
- }
+ }
else if(status_bits & IMX_USB_STS_USBINT)
{
g_isr_status_bits |= IMX_USB_STS_USBINT;
usbs_imx_otg_base->usbsts |= IMX_USB_STS_USBINT;
cyg_interrupt_mask(IMX_IRQ_USB_DEV_SERVICE_REQUEST);
}
- else
+ else
{
usbs_imx_otg_base->usbsts = status_bits; //clear the status bit of USBSTS
g_isr_status_bits &= ~status_bits;
usbs_imx_otg_dev_poll(usbs_control_endpoint* endpoint)
{
CYG_ASSERT( endpoint == &ep0.common, "USB poll involves the wrong endpoint");
-
- if (g_isr_status_bits & IMX_USB_STS_RESET)
+
+ if (g_isr_status_bits & IMX_USB_STS_RESET)
{
// Reset was detected the last time poll() was invoked. If
// reset is still active, do nothing. Once the reset has
// completed things can continue.
- if (0 == (IMX_USB_STS_RESET & usbs_imx_otg_base->usbsts))
+ if (0 == (IMX_USB_STS_RESET & usbs_imx_otg_base->usbsts))
{
g_isr_status_bits = 0;
usbs_imx_otg_dev_handle_bus_reset();
}
- }
- else
+ }
+ else
{
g_isr_status_bits = usbs_imx_otg_base->usbsts;
- if (IMX_USB_STS_PTCHANGE & g_isr_status_bits)
+ if (IMX_USB_STS_PTCHANGE & g_isr_status_bits)
{
//process Port Change Detect
usbs_imx_otg_dev_handle_port_change();
- }
+ }
else if (IMX_USB_STS_USBINT & g_isr_status_bits)
{
usbs_imx_otg_dev_dsr(IMX_IRQ_USB_DEV_SERVICE_REQUEST, 0, (cyg_addrword_t) 0);
usbs_imx_otg_dev_handle_bus_reset(void)
{
cyg_uint32 temp;
-
+
usbs_imx_otg_base->usbcmd &= ~BIT0; //detach device from bus temprorarily
usbs_imx_otg_base->usbsts |= BIT6; //clear reset bit in USBSTS
//temp = usbs_imx_otg_base->usbsts;
//usbs_imx_otg_base->usbsts = temp;
-
+
/*1. Reading and writing back the ENDPTSETUPSTAT register
clears the setup token semaphores */
temp = usbs_imx_otg_base->endptsetupstat;
clears the endpoint complete status bits */
temp = usbs_imx_otg_base->endptcomplete;
usbs_imx_otg_base->endptcomplete = temp;
-
+
/*3. Cancel all primed status by waiting until all bits in ENDPTPRIME are 0
and then write 0xFFFFFFFF to ENDPTFLUSH */
- while(usbs_imx_otg_base->endptprime);
- usbs_imx_otg_base->endptflush = 0xFFFFFFFF;
+ while(usbs_imx_otg_base->endptprime);
+ usbs_imx_otg_base->endptflush = 0xFFFFFFFF;
/*4. Initialize EP0 Queue Head again*/
usbs_ep0_init_dqh();
-
- usbs_imx_otg_base->endptlistaddr = g_bulkbuffer_map.ep_dqh_base_addrs;
-
+
+ usbs_imx_otg_base->endptlistaddr = g_bulkbuffer_map.ep_dqh_base_addrs;
+
usbs_imx_otg_base->usbcmd |= BIT0; //re-attach device to the bus
g_usb_dev_state = USB_DEV_DEFAULT_STATE;
-
+
}
/*=============================================================================
// Perform port change operations on all endpoints that have been
FUNCTION: usbs_imx_otg_dev_set_configuration
DESCRIPTION: This function Handle the SET CONFIGRATION Request.
ARGUMENTS PASSED: usb_end_pt_info_t* config_data;
-RETURN VALUE: None
-IMPORTANT NOTES: None
+RETURN VALUE: None
+IMPORTANT NOTES: None
=============================================================================*/
static void
usbs_imx_otg_dev_set_configuration(usb_end_pt_info_t* config_data)
cyg_uint32 dqh_address = 0;
cyg_uint32 dtd_address = 0;
cyg_uint8 endpt_num,direction;
-
+
struct dqh_t qhead;
-
+
/* get endpoint number to be configured and its direction */
- endpt_num= config_data->end_pt_no;
+ endpt_num= config_data->end_pt_no;
direction= config_data->direction;
USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: set config - ep%d\n",endpt_num);
/* Check if the endpoint number and direction is withing the permitted range or not */
- if (( endpt_num != EP0 ) && (endpt_num <= ( g_max_ep_supported - 1)) &&
+ if (( endpt_num != EP0 ) && (endpt_num <= ( g_max_ep_supported - 1)) &&
( direction == OUT || direction == IN))
{
/* get the device q head and deice TD */
- dqh_address = USBS_EP_GET_dQH(endpt_num,direction);
+ dqh_address = USBS_EP_GET_dQH(endpt_num,direction);
dtd_address = USBS_EP_GET_dTD(endpt_num,direction);
if ( direction == OUT )
{
total_bytes = BULK_BUFFER_SIZE ;
-
+
qhead.dqh_base = dqh_address;
qhead.zlt = ZLT_DISABLE;
qhead.mps = config_data->max_pkt_size;
qhead.buffer_ptr4 = 0;
usbs_setup_queuehead(&qhead);
-
+
/* Endpoint 1 : MPS = 64, OUT (Rx endpoint) */
usbs_imx_otg_base->endptctrl[endpt_num] = 0x00080048;
/* Enable EP1 OUT */
usbs_imx_otg_base->endptctrl[endpt_num] |= EPOUT_ENABLE;
-
+
/* allocate buffer for receiving data */
/* free the usb buffer after re-enumeration*/
//g_bulkbuffer_map.buffer1_status = BUFFER_FREE;
//g_bulkbuffer_map.buffer2_status = BUFFER_FREE;
g_bulkbuffer_a.stat = BUFFER_FREED;
- g_bulkbuffer_b.stat = BUFFER_FREED;
-
+ g_bulkbuffer_b.stat = BUFFER_FREED;
+
//buffer_addrs_page0 = util_alloc_buffer();
ep1.common.buffer = g_bulkbuffer_a.buffer;
ep1.common.buffer_size = total_bytes;
g_bulkbuffer_a.stat = BUFFER_ALLOCATED;
buffer_addrs_page0 = (cyg_uint32)(ep1.common.buffer);
-
-
+
+
USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: set config - ep1 dtd buffer 0x%08X\n",buffer_addrs_page0);
-
+
/* OUT setup dTD */
td.dtd_base = dtd_address;
td.next_link_ptr = dtd_address + 0x20;
td.buffer_ptr2 = 0x0;
td.buffer_ptr3 = 0x0;
td.buffer_ptr4 = 0x0;
-
+
/* Set the Transfer Descriptor */
usbs_setup_transdesc(&td);
/* 1. write dQH next ptr and dQH terminate bit to 0 */
- *(volatile cyg_uint32*)(dqh_address+0x8)= dtd_address;
-
+ *(volatile cyg_uint32*)(dqh_address+0x8)= dtd_address;
+
/* 2. clear active & halt bit in dQH */
*(volatile cyg_uint32*)(dqh_address+0xC) &= ~0xFF;
-
+
/* 3. prime endpoint by writing '1' in ENDPTPRIME */
usbs_imx_otg_base->endptprime |= ( EPOUT_PRIME << endpt_num );
/* Endpoint Configured for output */
g_out_endpoint= endpt_num;
-
+
}
else
{
total_bytes = 0x4 ;
-
+
qhead.dqh_base = USBS_EP_GET_dQH(endpt_num,direction);
qhead.zlt = ZLT_DISABLE;
qhead.mps = config_data->max_pkt_size;
qhead.buffer_ptr4 = 0;
usbs_setup_queuehead(&qhead);
-
+
/* Endpoint Configured for Input */
g_in_endpoint= endpt_num;
-
+
/* Endpoint 2: MPS = 64, IN (Tx endpoint) */
usbs_imx_otg_base->endptctrl[endpt_num] = 0x00480008;
/* Enable EP2 IN */
usbs_imx_otg_base->endptctrl[endpt_num] |= EPIN_ENABLE;
-
+
/* 3. prime endpoint by writing '1' in ENDPTPRIME */
usbs_imx_otg_base->endptprime |= (EPIN_PRIME << g_in_endpoint);
-
+
}
}
- else
+ else
{
/* TODO: error handling TBD */
- }
+ }
}
#if defined(CYGHWR_USB_DEVS_MX51_OTG)
cyg_uint32 temp;
- /*Configure USB_PHYCLOCK_ROOT source as 24MHz OSC*/
+ /*Configure USB_PHYCLOCK_ROOT source as 24MHz OSC*/
CCM_CSCMR1_REGVAL = CCM_CSCMR1_REGVAL & (~CSCMR1_USBOH3_PHY_CLK_SEL_VALUE); //configure USB CRM
- /*Configure plldivvalue of USB_PHY_CTRL_1_REG for 24 Mhz*/
- temp = *(volatile cyg_uint32 *)USB_PHY_CTRL_1_REG;
- temp &= ~USB_PHY_CTRL_PLLDIVVALUE_MASK;
- temp |= USB_PHY_CTRL_PLLDIVVALUE_24_MHZ;
+ /*Configure plldivvalue of USB_PHY_CTRL_1_REG for 24 Mhz*/
+ temp = *(volatile cyg_uint32 *)USB_PHY_CTRL_1_REG;
+ temp &= ~USB_PHY_CTRL_PLLDIVVALUE_MASK;
+ temp |= USB_PHY_CTRL_PLLDIVVALUE_24_MHZ;
*(volatile cyg_uint32 *)USB_PHY_CTRL_1_REG = temp;
#endif
}
{
cyg_uint32 temp;
cyg_uint32 timeout = 0x1D0000;
- usb_plat_config_data_t config_data_ptr;
+ usb_plat_config_data_t config_data_ptr;
cyg_uint8 i;
-
+
/*Enable USB Internal PHY Clock as 24MHz on-board Ocsillator*/
usbs_imx_otg_config_utmi_clock();
-
+
{/*Setup USB Buffer Map*/
config_data_ptr.buffer_address = (cyg_uint32)usb_buffer;
config_data_ptr.buffer_size = BUFFER_SIZE;
-
+
/* Base address of the buffer allocated to IP Layer */
g_bulkbuffer_address_base = config_data_ptr.buffer_address;
-
+
/* length of the buffer */
- g_bulkbuffer_length = config_data_ptr.buffer_size;
-
+ g_bulkbuffer_length = config_data_ptr.buffer_size;
+
/* Maximum Number of EPs to be confiured */
g_max_ep_supported = (( g_bulkbuffer_length - TOTAL_DATA_BUFFER_SIZE)/(BUFFER_USED_PER_EP)); //=(2048-1088)/256~=3.75->3
-
+
/* Base of queue Head Pointer */
- g_bulkbuffer_map.ep_dqh_base_addrs = g_bulkbuffer_address_base;
-
+ g_bulkbuffer_map.ep_dqh_base_addrs = g_bulkbuffer_address_base;
+
/* Total size of qhead */
temp = (SIZE_OF_QHD * (g_max_ep_supported * 2)); //total size of QH is 384byte
/* Base Address of dTDs */
g_bulkbuffer_map.ep_dtd_base_addrs = (g_bulkbuffer_map.ep_dqh_base_addrs + temp);
-
- /* Total size of transfer descriptor */
+
+ /* Total size of transfer descriptor */
temp = ((dTD_SIZE_EPIN * g_max_ep_supported) + (dTD_SIZE_EPOUT * g_max_ep_supported )); //total size of TD is 384 byte
-
+
/* Base Address of EP0 Buffer */
g_bulkbuffer_map.ep0_buffer_addrs = (g_bulkbuffer_map.ep_dtd_base_addrs + temp ); //256byte
-
+
/*Bulk Buffer Areas, 512byte per buffer*/
/*Actually, the dual 512 byte bulk buffers are not used, because two larger 16kB bulk buffers are used*/
- /* transfer buffer 1 */
+ /* transfer buffer 1 */
g_bulkbuffer_map.buffer1_address=(g_bulkbuffer_address_base + g_bulkbuffer_length -(BULK_BUFFER_SIZE*NUM_OF_BULK_BUFFER));
g_bulkbuffer_map.buffer1_status = BUFFER_FREE;
g_bulkbuffer_map.buffer2_address = g_bulkbuffer_map.buffer1_address + BULK_BUFFER_SIZE;
g_bulkbuffer_map.buffer2_status = BUFFER_FREE;
}
-
+
{/*Set USB OTG at device only mode*/
usbs_imx_otg_base->usbmode = 0x2; //set OTG as a device controller
temp = 0xA5A55A5A;
usbs_imx_otg_base->usbmode |= BIT3; // Disable Setup Lockout by writing '1' to SLOM in USBMODE
//usbs_imx_otg_base->usbcmd |= BIT0; // Set Run/Stop bit to Run Mode, make USB run in usbs_imx_otg_dev_ep0_start()
}
-
+
{
/* set it to be utmi interface */
temp = usbs_imx_otg_base->portsc1;
}
{// The USB OTG transaction relevant initialization.
- /* Select the common descriptors , these descriptor are independent of speed and security mode */
+ /* Select the common descriptors , these descriptor are independent of speed and security mode */
g_usb_desc.device_desc = &g_usb_device_desc ;
g_usb_desc.config_desc = &g_usb_config_desc;
g_usb_desc.sn_desc = &g_usb_serialnumber_desc;
g_usb_desc.str_desc1 = &g_usb_otg_string_desc1; //Manufacturer desc
g_usb_desc.str_desc2 = &g_usb_otg_string_desc2; //USB Name Desc
g_usb_desc.str_desc3 = &g_usb_otg_string_desc3; //Device Name Desc
-
+
/* Get Number of Endpoints supported from Configuration Descriptor*/
g_number_of_endpoints = g_usb_desc.config_desc->usb_interface_desc.number_endpoints;
-
+
/* Store the Endpoint specific information in local variable structure to this Layer */
for ( i = 0 ; i< g_number_of_endpoints ; i++)
{
g_end_pt_info[i].max_pkt_size = ((g_usb_desc.config_desc->usb_endpoint_desc[i].max_packet_lo) \
| (( g_usb_desc.config_desc->usb_endpoint_desc[i].max_packet_hi ) << 8 ));
}
-
+
g_usb_dev_state = USB_DEV_DEFAULT_STATE;
}
}
// ****************************************************************************
/*=============================================================================
// Initialization i.MX37(Marley) USB OTG Hardware
-// This function is the only extern function of this device driver, and it
-// registers the driver ISR and DSRs to the kernel.
+// This function is the only extern function of this device driver, and it
+// registers the driver ISR and DSRs to the kernel.
=============================================================================*/
void
-usbs_imx_otg_device_init(void) //works like usb port open when
-{
+usbs_imx_otg_device_init(void) //works like usb port open when
+{
USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: USB Device Driver Start Initializing...\n");
USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: USB OTG REG BASE@0x%08X\n",USB_BASE_ADDRESS);
g_usb_setup_data = ep0.common.control_buffer;
-
+
g_td_buffer_offset = 0;
#if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT)
USB_IMX_SET_TD_OFFSET(g_td_buffer_offset,1);
/*ping-pang buffer A*/
g_bulkbuffer_a.buffer = bulk_buffer;
g_bulkbuffer_a.stat = BUFFER_FREED;
-
+
/*ping-pang buffer B*/
g_bulkbuffer_b.buffer = bulk_buffer + BULK_TD_BUFFER_TOTAL_SIZE;
g_bulkbuffer_b.stat = BUFFER_FREED;
-
- usbs_imx_otg_hardware_init();
+
+ usbs_imx_otg_hardware_init();
USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: Usb Hardware Initialize Complete.\n");
usbs_imx_otg_dev_ep0_init();
USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: Usb Ep0 Initialize Complete.\n");
usbs_imx_otg_dev_ep1_init();
USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: Usb Ep1 Initialize Complete.\n");
usbs_imx_otg_dev_ep2_init();
- USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: Usb Ep2 Initialize Complete.\n");
+ USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: Usb Ep2 Initialize Complete.\n");
#if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT)
cyg_semaphore_init(&usbs_imx_otg_dev_sem, 0);
cyg_interrupt_create(IMX_IRQ_USB_DEV_SERVICE_REQUEST,
IMX_IRQ_USB_DEV_PRIORITY, // priority
0, // data
- &usbs_imx_otg_dev_isr,
+ &usbs_imx_otg_dev_isr,
&usbs_imx_otg_dev_thread_dsr,
&g_usbs_dev_intr_handle,
&g_usbs_dev_intr_data);
USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: cyg_interrupt_create@vector %d.\n",IMX_IRQ_USB_DEV_SERVICE_REQUEST);
- cyg_interrupt_attach(g_usbs_dev_intr_handle); //fill interrupt handler table for USB
+ cyg_interrupt_attach(g_usbs_dev_intr_handle); //fill interrupt handler table for USB
USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: cyg_interrupt_attach.\n");
cyg_interrupt_unmask(IMX_IRQ_USB_DEV_SERVICE_REQUEST); //enable USB interrrupt
USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: cyg_interrupt_unmask.\n");
}
-void
+void
usbs_imx_otg_device_deinit(void) //works like usb port close
{
usbs_imx_otg_base->usbcmd &= (~BIT0); // Set Run/Stop bit to Stop Mode
else
{
i++;
- if(i==0xD0000)
+ if(i==0xD0000)
{
diag_printf("no bulk buffer free\n");
break;
}
-
+
}
*/
}
if((usbs_imx_otg_base->usbsts) & IMX_USB_STS_RESET)
{
/* Handle Bus Reset */
- usbs_imx_otg_dev_handle_bus_reset();
- }
+ usbs_imx_otg_dev_handle_bus_reset();
+ }
/* Check if Reset is already received and Setup Token Received */
if((usbs_imx_otg_base->endptsetupstat) & BIT0)
{
/* Handle Setup Token */
usbs_imx_otg_dev_ep0_dsr();
}
-
+
if((usbs_imx_otg_base->endptcomplete) & ( EPOUT_COMPLETE << EP1))
{
ep1_rx_complete(res);
//(cyg_uint8*)(buf_desc.buffer) = read_ptr;
buf_desc.buffer = (void *)read_ptr;
while(data_length != 0)
- {
+ {
buf_desc.size = data_length;
buf_desc.bytes_transfered = 0;
if(g_timeout_value == USB_DOWNLOAD_TIMEOUT_LIMIT) return 0;
}
}
-
+
return ( bytes_received );
}
static usb_status_t usb_tx_processing(cyg_uint8* write_ptr, cyg_uint32 data_len)
/* Prepare the buffer descriptor for USB transfer */
usb_buffer_descriptor_t buf_desc;
- /* Prepare transfer buffer descriptor*/
+ /* Prepare transfer buffer descriptor*/
buf_desc.buffer = (void *)write_ptr;
buf_desc.size = data_len;
buf_desc.bytes_transfered = 0;
//if(g_timeout_value%1000==0) D("C");
//D("%d\n",g_timeout_value);
bytes_recvd = usb_rx_processing(sdp_payload_data, &status, SDP_CMD_MAX_LEN);
- start_command = pl_command_start();
+ start_command = pl_command_start();
if(g_timeout_value == USB_DOWNLOAD_TIMEOUT_LIMIT) return false;
}
//D("+USBDBGMSG: start_command = 0x%02X\n",start_command);
sdp_command[i] = sdp_payload_data[i-1];
}
}
- else
+ else
{
//copy starting bytes
for(i=0; i < (SDP_CMD_MAX_LEN - start_command) ; i++)
{
//receive rest of the bytes
bytes_recvd = usb_rx_processing(sdp_payload_data, &status, start_command);
-
+
if(bytes_recvd == start_command)
{
for(i=0; i <start_command; i++)
{
cyg_uint8 i=0;
static cyg_uint8 last_byte = 0;
-
+
if(last_byte != 0x0)
{
if(last_byte == sdp_payload_data[0])
(sdp_payload_data[i] == 0x07) && (sdp_payload_data[i+1] == 0x07) ||
(sdp_payload_data[i] == 0x08) && (sdp_payload_data[i+1] == 0x08) ||
(sdp_payload_data[i] == 0x09) && (sdp_payload_data[i+1] == 0x09) ||
- (sdp_payload_data[i] == 0x0A) && (sdp_payload_data[i+1] == 0x0A))
+ (sdp_payload_data[i] == 0x0A) && (sdp_payload_data[i+1] == 0x0A))
{
return i;
}
{
last_byte = 0;
}
-
+
return 0xFF;
}
static cyg_uint8 pl_handle_command(cyg_uint8 g_error_status)
{
case WRITE_FILE:
//D("+USBDBGMSG: usb download file to address 0x%08X, length %d\n",usb_download_address,ByteCount);
- pl_handle_write_file(usb_download_address, ByteCount);
+ pl_handle_write_file(usb_download_address, ByteCount);
//pl_handle_write_file(Address, ByteCount);
//if(g_load_cycle==0) usb_download_address=Address;
//g_load_cycle ++;
usb_download_address += ByteCount;
usb_download_length +=ByteCount;
D(".");
- if(ByteCount<BULK_TD_BUFFER_TOTAL_SIZE)
+ if(ByteCount<BULK_TD_BUFFER_TOTAL_SIZE)
{
status = COMPLETE;
}
}
static void pl_handle_write_file(cyg_uint32 address, cyg_uint32 total_bytes)
{
- usb_status_t status;
+ usb_status_t status;
usb_rx_processing((cyg_uint8*)address, &status, total_bytes);
}
static void pl_command_ack(cyg_uint32 ack)
{
usb_tx_processing((cyg_uint8*)&ack, SDP_CMD_ACK_LEN);
-}
+}
-void
+void
usbs_imx_otg_download(unsigned char * buffer, unsigned int length)
{
cyg_bool bytes_recvd = false;
/*TODO*/
while(g_usb_dev_state!=USB_DEV_CONFIGURED_STATE)
{
-
+
/* Check if Bus Reset Received */
if((usbs_imx_otg_base->usbsts) & IMX_USB_STS_RESET)
{
/* Handle Bus Reset */
- usbs_imx_otg_dev_handle_bus_reset();
- }
+ usbs_imx_otg_dev_handle_bus_reset();
+ }
/* Check if Reset is already received and Setup Token Received */
if((g_usb_dev_state != USB_DEV_DUMMY_STATE) && (usbs_imx_otg_base->endptsetupstat & BIT0))
{
/* Handle Setup Token */
usbs_imx_otg_dev_ep0_dsr();
- }
+ }
}
if(g_usb_dev_state==USB_DEV_CONFIGURED_STATE)
//g_load_cycle = 0;
while(1)
{
-
+
bytes_recvd = pl_get_command();
if(bytes_recvd == true)
{
- g_usb_download_state = pl_handle_command(g_error_status);
- }
-
- if((g_usb_download_state==COMPLETE)||(g_timeout_value == USB_DOWNLOAD_TIMEOUT_LIMIT))
+ g_usb_download_state = pl_handle_command(g_error_status);
+ }
+
+ if((g_usb_download_state==COMPLETE)||(g_timeout_value == USB_DOWNLOAD_TIMEOUT_LIMIT))
break;
-
+
}
diag_printf("\n");
if(g_timeout_value == USB_DOWNLOAD_TIMEOUT_LIMIT) //timeout value
D("USB file download complete\n");
//D("+usbdownload: image base 0x%08X, length %d\n",usb_download_address,usb_download_length);
}
-
}
}
#endif
#define MUX_CTL_BIT_LEN 8
#endif
-#if defined (CONFIG_ARCH_MXC91331) || defined(CONFIG_ARCH_MXC91321)
+#if defined (CONFIG_ARCH_MXC91321)
#define OTG_BASE_ADDR 0x50020000
-#elif defined (CONFIG_ARCH_MXC91231) || defined (CONFIG_ARCH_MXC91131)
-#define OTG_BASE_ADDR 0x50024000
#endif
#define OTG_CORE_BASE (OTG_BASE_ADDR+0x000)
#define OTG_EP_BASE (OTG_BASE_ADDR+0x400)
#define OTG_SYS_BASE (OTG_BASE_ADDR+0x600)
-#if defined (CONFIG_ARCH_MXC91231)
-#define OTG_DATA_BASE (OTG_BASE_ADDR+0x4000)
-#else
#define OTG_DATA_BASE (OTG_BASE_ADDR+0x1000)
-#endif
#define SYS_CTRL_OTG_WU_INT_STAT (1 << 26)
#define SYS_CTRL_FNT_WU_INT_STAT (1 << 24)
+2006-11-23 David Fernandez <dfernandez@cct.co.uk>
+
+ * src/ds17887.cxx (defines): Added check for some defines being done
+ in INL file.
+
2001-07-27 Jesper Skov <jskov@redhat.com>
* src/ds12887.cxx (init_ds_hwclock): Use BCD mode since Century is
# define DS_WRITE_UINT8(x,y) HAL_WRITE_UINT8(x,y)
#endif
+#if !defined(DS_READ) && !defined(DS_WRITE) // Allow for INL to define this
#ifdef DS_LINEAR
# ifndef DS_STEP
# define DS_STEP 0
# ifndef DS_BASE
# error "Need to know base of DS12887 part"
# endif
-# define DS_READ(offset, data) DS_READ_UINT8(DS_BASE + ((offset) << DS_STEP), (data))
-# define DS_WRITE(offset, data) DS_WRITE_UINT8(DS_BASE + ((offset) << DS_STEP), (data))
-#else
+#define DS_READ( offset, data) \
+ DS_READ_UINT8( DS_BASE + ((offset) << DS_STEP), (data))
+#define DS_WRITE(offset, data) \
+ DS_WRITE_UINT8(DS_BASE + ((offset) << DS_STEP), (data))
+#else // !DS_LINEAR
# if !defined(DS_ADDR) || !defined(DS_DATA)
# error "Need to know addr/data locations of DS12887 part"
# endif
DS_WRITE_UINT8(DS_DATA, (data)); \
CYG_MACRO_END
#endif
+#endif // ! DS_READ && ! DS_WRITE
// Registers
#define DS_SECONDS 0x00
+2006-11-23 David Fernandez <dfernandez@cct.co.uk>
+
+ * include/devices_wallclock_i386_pc.inl: Added exception for DS_READ
+ DS_WRITE. Take into account that in Intel PC platforms the 8Th bit
+ in DS_ADDR is used to enable or disable NMI gate, and therefore,
+ should be preserved.
+
2001-09-18 Rajagopalan Thiruvenkatachary <rajt@us.ibm.com>
* include/devices_wallclock_i386_pc.inl:
#define DS_ADDR CYGDAT_DEVS_WALLCLOCK_I386_PC_RTC_ADDRESS_PORT
#define DS_DATA CYGDAT_DEVS_WALLCLOCK_I386_PC_RTC_DATA_PORT
+#ifndef DS_LINEAR
+#define DS_READ(offset, data) \
+CYG_MACRO_START \
+ register CYG_BYTE btval; \
+ DS_READ_UINT8( DS_ADDR, (btval)); \
+ DS_WRITE_UINT8(DS_ADDR, ((offset)&0x7F)|(btval&0x80)); \
+ DS_READ_UINT8( DS_DATA, (data)); \
+CYG_MACRO_END
+#define DS_WRITE(offset, data) \
+CYG_MACRO_START \
+ register CYG_BYTE btval; \
+ DS_READ_UINT8( DS_ADDR, (btval)); \
+ DS_WRITE_UINT8(DS_ADDR, ((offset)&0x7F)|(btval&0x80)); \
+ DS_WRITE_UINT8(DS_DATA, (data)); \
+CYG_MACRO_END
+#endif
+
+
// EOF devs_wallclock_i386_pc.inl
+2007-08-19 Sergei Gavrikov <sg@sgs.gomel.by>
+
+ * src/watchdog_lpc2xxx.cxx: Fixed to work properly in WDINT mode.
+
2004-10-04 Jani Monoses <jani@iv.ro>
* Added watchdog driver for ARM LPC2XXX based on the AT91 code.
//==========================================================================
-static Cyg_Interrupt wdint(
+static CYGBLD_ATTRIB_INIT_PRI(CYG_INIT_DRIVERS)
+ Cyg_Interrupt wdint(
CYGNUM_HAL_INTERRUPT_WD,
INT_PRIO,
0,
wd = this;
resolution = RESOLUTION;
- wdint.configure_interrupt(CYGNUM_HAL_INTERRUPT_WD, false, true);
wdint.attach();
wdint.acknowledge_interrupt(CYGNUM_HAL_INTERRUPT_WD);
wdint.unmask_interrupt(CYGNUM_HAL_INTERRUPT_WD);
+#=============================================================================
+#
+# ecos.db
+#
+# This file is a temporary database for eCos package information.
+# It replaces the old packages and targets files, and will in turn
+# be subsumed by another file containing more inormation.
+#
+#=============================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 2004, 2005 eCosCentric Limited
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+#=============================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): bartv
+# Date: 1999-06-13
+#
+# This file contains three lots of information. It details the packages
+# in the component repository, the target boards supported by those
+# packages, and a set of templates that can be used to instantiate
+# configuration.
+#
+#####DESCRIPTIONEND####
+#===============================================================================
+
package CYGPKG_HAL {
alias { "eCos common HAL" hal hal_common }
directory hal/common
FlexCAN modules in MCF52xx ColdFire processors."
}
-package CYGPKG_IO_CAN_LOOP {
+package CYGPKG_DEVS_CAN_AT91SAM7 {
+ alias { "AT91SAM7 CAN device drivers"
+ devs_can_at91sam7 at91sam7_can_driver }
+ hardware
+ directory devs/can/arm/at91/at91sam7
+ script can_at91sam7.cdl
+ description "Atmel AT91SAM7 on-chip CAN device driver."
+}
+
+package CYGPKG_DEVS_CAN_LPC2XXX {
+ alias { "LPC2xxx CAN device drivers"
+ devs_can_lpc2xxx lpc2xxx_can_driver }
+ hardware
+ directory devs/can/arm/lpc2xxx
+ script can_lpc2xxx.cdl
+ description "LPC2xxx on-chip CAN device driver."
+}
+
+package CYGPKG_DEVS_CAN_LOOP {
alias { "Loop CAN device drivers"
devs_can_loop loop_can_driver }
directory devs/can/loop
Freescale MXC-based platforms."
}
+package CYGPKG_DEVS_MXC_I2C {
+ alias { "Support I2C on Freescale MXC platforms" fsl_mxc_i2c }
+ directory devs/i2c/arm/mxc
+ script mxc_i2c.cdl
+ hardware
+ description "
+ This package contains hardware support for I2C selections on
+ Freescale MXC-based platforms."
+}
+
+package CYGPKG_DEVS_PMIC_ARM_IMX35_3STACK {
+ alias { "Support PMIC on Freescale i.MX35 3stack platforms" fsl_imx35_pmic }
+ directory devs/pmic/arm/mx35_3stack
+ script mc9s08dz.cdl
+ hardware
+ description "
+ This package contains hardware support for PMIC selections on
+ Freescale i.MX35 3stack platforms."
+}
+
+package CYGPKG_DEVS_PMIC_ARM_IMX25_3STACK {
+ alias { "Support PMIC on Freescale i.MX25 3stack platforms" fsl_imx25_pmic }
+ directory devs/pmic/arm/mx25_3stack
+ script mc34704.cdl
+ hardware
+ description "
+ This package contains hardware support for PMIC selections on
+ Freescale i.MX25 3stack platforms."
+}
+
package CYGPKG_DEVS_MXC_SPI {
alias { "Support SPI on Freescale MXC platforms" fsl_mxc_spi }
directory devs/spi/arm/mxc
Freescale MXC-based platforms."
}
+package CYGPKG_DEVS_IMX_SPI {
+ alias { "Support SPI on Freescale i.MX platforms" fsl_imx_spi }
+ directory devs/spi/arm/imx
+ script spi.cdl
+ hardware
+ description "
+ This package contains hardware support for SPI selections on
+ Freescale i.MX based platforms."
+}
+
package CYGPKG_DEVS_FLASH_ATMEL_AT29CXXXX {
alias { "Support for Atmel AT29Cxxxx flash memory" flash_atmel_at29cxxxx }
directory devs/flash/atmel/at29cxxxx
on the ARM Evaluator-7T platform."
}
+package CYGPKG_DEVS_FLASH_EA2468 {
+ alias { "FLASH memory support for EA LPC2468 OEM board" flash_ea2468 }
+ directory devs/flash/arm/ea2468
+ script flash_ea2468.cdl
+ hardware
+ description "
+ This package contains hardware support for FLASH memory
+ on the Embedded Artists LCP2468 OEM board."
+}
+
package CYGPKG_DEVS_FLASH_SH_EDK7708 {
alias { "Support for flash memory on Hitachi/EDK7708 board" flash_sh_edk7708 }
directory devs/flash/sh/edk7708
on the Cirrus Logic EP7xxx based platform(s)."
}
+package CYGPKG_DEVS_FLASH_AT91 {
+ alias { "FLASH memory support for Atmel AT91 EFC" flash_at91 }
+ directory devs/flash/arm/at91
+ script flash_at91.cdl
+ hardware
+ description "
+ This package contains hardware support for Embedded FLASH
+ controller as found in the AT91SAM7S platform"
+}
+
package CYGPKG_DEVS_FLASH_EB40 {
alias { "FLASH memory support for Atmel AT91/EB40" flash_eb40 }
directory devs/flash/arm/eb40
on the PHYTEC phyCORE AT91M55800A platform(s)."
}
+package CYGPKG_DEVS_FLASH_PHYCORE229X {
+ alias { "FLASH memory support for Phytec phyCORE-LPC229x" flash_phycore229x }
+ directory devs/flash/arm/phycore229x
+ script flash_phycore229x.cdl
+ hardware
+ description "
+ This package contains hardware support for FLASH memory
+ on the Phytec phyCORE-LPC229x platform(s)."
+}
+
package CYGPKG_DEVS_FLASH_ASSABET {
alias { "FLASH memory support for Intel SA1110 (Assabet)" flash_assabet }
directory devs/flash/arm/assabet
on the MX31ADS platform."
}
-package CYGPKG_DEVS_FLASH_MX27ADS_SPANSION {
- alias { "FLASH memory support for MX27ADS" flash_mx27ads }
- directory devs/flash/arm/mx27ads
- script flash_board_spansion.cdl
- hardware
- description "
- This package contains hardware support for FLASH memory
- on the MX27ADS platform."
-}
-
-package CYGPKG_DEVS_FLASH_MXC30030EVB_SPANSION {
- alias { "FLASH memory support for MXC300-30" flash_mxc30030evb }
- directory devs/flash/arm/mxc30030evb
+package CYGPKG_DEVS_FLASH_IMX_3STACK_SPANSION {
+ alias { "FLASH memory support for IMX 3-Stack board" flash_imx_3stack }
+ directory devs/flash/arm/imx_3stack
script flash_board_spansion.cdl
hardware
description "
This package contains hardware support for FLASH memory
- on the MXC300-30 EVB platform."
+ on the i.MX 3-Stack platform."
}
-package CYGPKG_DEVS_FLASH_MXC30020EVB_SPANSION {
- alias { "FLASH memory support for MXC300-20" flash_mxc30020evb }
- directory devs/flash/arm/mxc30020evb
+package CYGPKG_DEVS_FLASH_MX35EVB_SPANSION {
+ alias { "FLASH memory support for MX35EVB" flash_mx35evb }
+ directory devs/flash/arm/mx35evb
script flash_board_spansion.cdl
hardware
description "
This package contains hardware support for FLASH memory
- on the MXC300-20 EVB platform."
-}
-
-package CYGPKG_DEVS_FLASH_I30030ADS {
- alias { "FLASH memory support for i.300-30 ADS" flash_i30030ads}
- directory devs/flash/arm/i30030ads
- script flash_board_strata.cdl
- hardware
- description "
- This package contains hardware support for FLASH memory
- on the i.300-30 ADS platform."
+ on the MX35EVB platform."
}
-package CYGPKG_DEVS_FLASH_MXC91131EVB_SPANSION {
- alias { "FLASH memory support for MXC91131 EVB" flash_mxc91131evb }
- directory devs/flash/arm/mxc91131evb
+package CYGPKG_DEVS_FLASH_MX27ADS_SPANSION {
+ alias { "FLASH memory support for MX27ADS" flash_mx27ads }
+ directory devs/flash/arm/mx27ads
script flash_board_spansion.cdl
hardware
description "
This package contains hardware support for FLASH memory
- on the EVB platform."
-}
-
-package CYGPKG_DEVS_FLASH_MXC27520EVB_STRATA {
- alias { "FLASH memory support for MXC27520 EVB" flash_mxc27520evb }
- directory devs/flash/arm/mxc27520evb
- script flash_board_strata.cdl
- hardware
- description "
- This package contains hardware support for FLASH memory
- on the MXC27520 EVB platform."
-}
-
-package CYGPKG_DEVS_FLASH_MXC27530EVB_STRATA {
- alias { "FLASH memory support for MXC27530EVB" flash_mxc27530evb }
- directory devs/flash/arm/mxc27530evb
- script flash_board_strata.cdl
- hardware
- description "
- This package contains hardware support for FLASH memory
- on the MXC275-30 EVB platform."
+ on the MX27ADS platform."
}
-package CYGPKG_DEVS_FLASH_MXC27520EVB_SPANSION {
- alias { "FLASH memory support for MXC27520 EVB" flash_mxc27520evb }
- directory devs/flash/arm/mxc27520evb
+package CYGPKG_DEVS_FLASH_MXC30030EVB_SPANSION {
+ alias { "FLASH memory support for MXC300-30" flash_mxc30030evb }
+ directory devs/flash/arm/mxc30030evb
script flash_board_spansion.cdl
hardware
description "
This package contains hardware support for FLASH memory
- on the MXC27520 EVB platform."
+ on the MXC300-30 EVB platform."
}
-package CYGPKG_DEVS_FLASH_MXC27530EVB_SPANSION {
- alias { "FLASH memory support for MXC27530EVB" flash_mxc27530evb }
- directory devs/flash/arm/mxc27530evb
- script flash_board_spansion.cdl
- hardware
- description "
- This package contains hardware support for FLASH memory
- on the MXC275-30 EVB platform."
+package CYGPKG_DEVS_FLASH_I30030ADS {
+ alias { "FLASH memory support for i.300-30 ADS" flash_i30030ads}
+ directory devs/flash/arm/i30030ads
+ script flash_board_strata.cdl
+ hardware
+ description "
+ This package contains hardware support for FLASH memory
+ on the i.300-30 ADS platform."
}
package CYGPKG_DEVS_FLASH_TS6 {
description "Intel StrongARM/EBSA285 serial device drivers"
}
+package CYGPKG_IO_SERIAL_ARM_XSCALE_PXA2X0 {
+ alias { "Intel XScale PXA2X0 serial driver"
+ devs_serial_arm_xscale_pxa pxa_serial_driver }
+ hardware
+ directory devs/serial/arm/pxa2x0
+ script ser_arm_xscale_pxa2x0.cdl
+ description "Intel XScale/PXA2X0 serial device drivers"
+}
+
package CYGPKG_IO_SERIAL_ARM_XSCALE_IOP310 {
alias { "Intel XScale IOP310 serial driver"
devs_serial_arm_iop310 iop310_serial_driver }
description "ARM LPC2XXX serial device drivers"
}
+package CYGPKG_IO_SERIAL_ARM_LPC24XX {
+ alias { "ARM LPC24XX serial device drivers"
+ devs_serial_arm_lpc24xx lpc24xx_serial_driver }
+ hardware
+ directory devs/serial/arm/lpc24xx
+ script ser_arm_lpc24xx.cdl
+ description "ARM LPC24XX serial device drivers"
+}
+
package CYGPKG_IO_SERIAL_POWERPC_COGENT {
alias { "Cogent PowerPC serial device drivers"
devs_serial_powerpc_cogent cogent_serial_driver }
description "Cogent PowerPC serial device drivers"
}
-package CYGPKG_IO_SERIAL_POWERPC_EC555 {
- alias { "ec555 PowerPC serial device drivers"
- devs_serial_powerpc_ec555 ec555_serial_driver }
+package CYGPKG_IO_SERIAL_POWERPC_MPC555 {
+ alias { "mpc555 PowerPC serial device drivers"
+ devs_serial_powerpc_mpc555 mpc555_serial_driver }
+ hardware
+ directory devs/serial/powerpc/mpc555
+ script ser_powerpc_mpc555.cdl
+ description "mpc555 PowerPC serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_FREESCALE_ESCI_H {
+ alias { "ESCI serial device header"
+ devs_serial_freescale_esci_h esci_serial_header }
hardware
- directory devs/serial/powerpc/ec555
- script ser_powerpc_ec555.cdl
- description "ec555 PowerPC serial device drivers"
+ directory devs/serial/freescale/esci/hdr
+ script ser_freescale_esci_h.cdl
+ description "Freescale eSCI - Enhanced Serial Communications Interface header.
+ Needed by hal_diag and ser_esci drivers."
}
-package CYGPKG_IO_SERIAL_POWERPC_CME555 {
- alias { "cme555 PowerPC serial device drivers"
- devs_serial_powerpc_cme555 cme555_serial_driver }
+package CYGPKG_IO_SERIAL_FREESCALE_ESCI {
+ alias { "ESCI serial device driver"
+ devs_serial_freescale_esci esci_serial_driver }
hardware
- directory devs/serial/powerpc/cme555
- script ser_powerpc_cme555.cdl
- description "cme555 PowerPC serial device drivers"
+ directory devs/serial/freescale/esci/drv
+ script ser_freescale_esci.cdl
+ description "Freescale eSCI - Enhanced Serial Communications Interface serial device driver"
}
package CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC {
description "SH SCIF serial device drivers"
}
+package CYGPKG_DEVS_ETH_ARM_I30030ADS {
+ alias { "Ethernet driver for Freescale i.300-30 ADS board" i30030ads_eth_driver }
+ hardware
+ directory devs/eth/arm/i30030ads
+ script board_eth_drivers.cdl
+ description "Ethernet driver for Freescale i.300-30 ADS
+ development boards."
+}
+
package CYGPKG_DEVS_ETH_PHY {
alias { "Generic PHY support" eth_phy_support }
hardware
description "Ethernet driver for NETARM."
}
+package CYGPKG_DEVS_ETH_ARM_PHYCORE229X {
+ alias { "Ethernet driver for phyCORE-LPC229x board" devs_eth_arm_phycore229x }
+ hardware
+ directory devs/eth/arm/phycore229x
+ script phycore229x_eth_drivers.cdl
+ description "Ethernet device driver for phyCORE-LPC229x board"
+}
+
package CYGPKG_IO_SERIAL_SH_EDK7708 {
alias { "SH3 EDK7708 serial device drivers"
devs_serial_sh3_edk7708
description "Support for USB peripherals that provide an ethernet-class function"
}
+package CYGPKG_IO_USB_SLAVE_SERIAL {
+ alias { "USB slave-side serial drivers" usbs_serial }
+ directory io/usb/serial/slave
+ script usbs_serial.cdl
+ description "Support for USB peripherals that present themselves
+ as serial devices to the host."
+}
+
package CYGPKG_DEVS_USB_SA11X0 {
alias { "Device-driver for the SA11X0 on-chip USB support" usb_sa11x0 }
hardware
description "A device driver for the SA11X0 on-chip USB slave port"
}
+package CYGPKG_DEVS_USB_IMX_OTG {
+ alias { "USB Device Driver for the i.MX37 or MX51 on-chip USB support" usb_otg_imx }
+ hardware
+ directory devs/usb/imx
+ script usbs_imx.cdl
+ description "A device driver for the i.MX37 or i.MX51 on-chip USB OTG device mode"
+}
+
package CYGPKG_DEVS_USB_UPD985XX {
alias { usb_upd985xx }
hardware
description "A device driver for the FSL MXC on-chip USB device"
}
+package CYGPKG_DEVS_USB_AT91 {
+ alias { usb_at91 }
+ hardware
+ directory devs/usb/at91
+ script usbs_at91.cdl
+ description "A device driver for the ATMEL AT91 on-chip USB device"
+}
+
+package CYGPKG_DEVS_USB_D12 {
+ alias { usb_d12 }
+ hardware
+ directory devs/usb/d12
+ script usbs_d12.cdl
+ description "A device driver for the Philips PDIUSBD12 full speed USB peripheral chip."
+}
+
+package CYGPKG_DEVS_USB_I386_SOROD12 {
+ alias { usb_sorod12 }
+ hardware
+ directory devs/usb/i386/SoRoD12
+ script usbs_i386_sorod12.cdl
+ description "A device driver for the SoRo PC/104 D12 USB Slave Board."
+}
+
package CYGPKG_NET {
alias { "Networking" net }
directory net/common
description "Generic networking support, including TCP/IP."
}
+package CYGPKG_NET_AUTOTEST {
+ alias { "Network Autotesting" autotest net_autotest }
+ directory net/autotest
+ script net_autotest.cdl
+ description "Automated network testing support."
+}
+
package CYGPKG_NET_OPENBSD_STACK {
alias { "OpenBSD Stack" openbsd_net }
directory net/tcpip
development boards."
}
-package CYGPKG_DEVS_ETH_ARM_MX31ADS {
- alias { "Ethernet driver for Freescale MX31 ADS board" mx31ads_eth_driver }
- hardware
- directory devs/eth/arm/mx31ads
- script board_eth_drivers.cdl
- description "Ethernet driver for Freescale MX31 ADS
- development boards."
-}
-
-package CYGPKG_DEVS_ETH_ARM_MXC30030EVB {
- alias { "Ethernet driver for Freescale MXC300-30 EVB board" mxc30030evb_eth_driver}
+package CYGPKG_DEVS_ETH_ARM_TX25 {
+ alias { "Ethernet driver for Ka-Ro electronics TX25 processor module" devs_eth_arm_tx25 }
+ directory devs/eth/arm/tx25karo
+ script tx25_eth_drivers.cdl
hardware
- directory devs/eth/arm/mxc30030evb
- script board_eth_drivers.cdl
- description "Ethernet driver for Freescale MXC300-30 EVB
- development boards."
+ description "
+ This package provides Ethernet support for the Ka-Ro electronics TX25 processor module."
}
-package CYGPKG_DEVS_ETH_ARM_MXC30020EVB {
- alias { "Ethernet driver for Freescale MXC300-20 EVB board" mxc30020evb_eth_driver}
+package CYGPKG_DEVS_ETH_ARM_TX27 {
+ alias { "Ethernet driver for Ka-Ro electronics TX27 processor module" devs_eth_arm_tx27 }
+ directory devs/eth/arm/tx27karo
+ script tx27_eth_drivers.cdl
hardware
- directory devs/eth/arm/mxc30020evb
- script board_eth_drivers.cdl
- description "Ethernet driver for Freescale MXC300-20 EVB
- development boards."
+ description "
+ This package provides Ethernet support for the Ka-Ro electronics TX27 processor module."
}
-package CYGPKG_DEVS_ETH_ARM_I30030ADS {
- alias { "Ethernet driver for Freescale i.300-30 ADS board" i30030ads_eth_driver }
+package CYGPKG_DEVS_ETH_ARM_TX37 {
+ alias { "Ethernet driver for Ka-Ro electronics TX37 processor module" devs_eth_arm_tx37 }
+ directory devs/eth/arm/tx37karo
+ script tx37_eth_drivers.cdl
hardware
- directory devs/eth/arm/i30030ads
- script board_eth_drivers.cdl
- description "Ethernet driver for Freescale i.300-30 ADS
- development boards."
+ description "
+ This package provides Ethernet support for the Ka-Ro electronics TX37 processor module."
}
-package CYGPKG_DEVS_ETH_ARM_MXC91131EVB {
- alias { "Ethernet driver for Freescale MXC91131 EVB board" mxc91131evb_eth_driver }
+package CYGPKG_DEVS_ETH_ARM_IMX_3STACK {
+ alias { "Ethernet driver for Freescale 3-Stack board" imx_3stack_eth_driver }
hardware
- directory devs/eth/arm/mxc91131evb
+ directory devs/eth/arm/imx_3stack
script board_eth_drivers.cdl
- description "Ethernet driver for Freescale MXC91131 EVB
+ description "Ethernet driver for Freescale 3-Stack
development boards."
}
-package CYGPKG_DEVS_ETH_ARM_MXC27530EVB {
- alias { "Ethernet driver for Freescale MXC275-30 EVB board" mxc27530evb_eth_driver }
+package CYGPKG_DEVS_ETH_ARM_MX31ADS {
+ alias { "Ethernet driver for Freescale MX31 ADS board" mx31ads_eth_driver }
hardware
- directory devs/eth/arm/mxc27530evb
+ directory devs/eth/arm/mx31ads
script board_eth_drivers.cdl
- description "Ethernet driver for Freescale MXC275-30 EVB
+ description "Ethernet driver for Freescale MX31 ADS
development boards."
}
-package CYGPKG_DEVS_ETH_ARM_MXC27520EVB {
- alias { "Ethernet driver for Freescale MXC275-20 EVB board" mxc27520evb_eth_driver }
+package CYGPKG_DEVS_ETH_ARM_MXC30030EVB {
+ alias { "Ethernet driver for Freescale MXC300-30 EVB board" mxc30030evb_eth_driver}
hardware
- directory devs/eth/arm/mxc27520evb
+ directory devs/eth/arm/mxc30030evb
script board_eth_drivers.cdl
- description "Ethernet driver for Freescale MXC275-20 EVB
+ description "Ethernet driver for Freescale MXC300-30 EVB
development boards."
}
description "Ethernet driver for MIPS IDT 79RC32334 reference platform."
}
+# Not sure whether this should be "hardware"; if so, it should be mentioned
+# in all targets that can use it.
package CYGPKG_DEVS_ETH_CF {
alias { "PCMCIA (Compact Flash) ethernet drivers" cf_eth_drivers }
directory devs/eth/cf
ARM AT91 CPU."
}
+package CYGPKG_DEVICES_WATCHDOG_ARM_AT91WDTC {
+ alias { "Watchdog driver for ARM AT91 WDTC" devices_watchdog_at91wdtc device_watchdog_at91wdtc }
+ directory devs/watchdog/arm/at91wdtc
+ script watchdog_at91wdtc.cdl
+ hardware
+ description "
+ This package provides a watchdog driver implementation for the
+ ARM AT91 CPUs which have the Watchdog Timer Controller."
+}
+
package CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX {
alias { "Watchdog driver for ARM LPC2XXX CPU" devices_watchdog_lpc2xxx device_watchdog_lpc2xxx }
directory devs/watchdog/arm/lpc2xxx
support for bit-banged I2C buses."
}
+package CYGPKG_DEVS_I2C_MCF52xx {
+ alias { "MCF52xx I2C driver" devs_i2c_mcf52xx mcf52xx_i2c_driver }
+ hardware
+ directory devs/i2c/m68k/mcf52xx
+ script i2c_mcf52xx.cdl
+ description "
+ This packages provides an I2C driver for the on-chip
+ device provided by the MCF52xx coldfire processor family."
+}
+
package CYGPKG_KERNEL {
alias { "eCos kernel" kernel }
directory kernel
description "ezXML, Simple XML Parser"
}
+package CYGPKG_DIAGNOSIS {
+ alias { "Diagnosis" DIAGNOSIS diagnosis }
+ directory services/diagnosis
+ script diagnosis.cdl
+ description "Diagnosis"
+}
+
package CYGPKG_UITRON {
alias { "uITRON compatibility" uitron }
directory compat/uitron
description "Microwindows."
}
+package CYGPKG_REDBOOT_WINCE_SUPPORT {
+ alias { "WinCE bootloader Support" redboot_wince }
+ directory redboot
+ script wince.cdl
+ hardware
+ description "This option enables MS Windows CE EShell support
+ and Windows CE .BIN images support"
+}
+
package CYGPKG_HAL_SH_SH7750_DREAMCAST {
alias { "SEGA Dreamcast" hal_sh_dreamcast sh_dreamcast_hal }
directory hal/sh/dreamcast
eCos on SEGA Dreamcast."
}
+# --------------------------------------------------------------------------
+# ARM packages
package CYGPKG_HAL_ARM {
alias { "ARM common HAL" hal_arm arm_hal arm_arch_hal }
directory hal/arm/arch
the Atmel evaluation board AT572D74-DK1."
}
+package CYGPKG_HAL_ARM_AT91SAM7 {
+ alias { "Atmel AT91SAM7" hal_arm_at91sam7 arm_at91_sam7 }
+ directory hal/arm/at91/at91sam7s
+ script hal_arm_at91sam7s.cdl
+ hardware
+ description "
+ The at91sam7 HAL package provides the support needed to run eCos on
+ an Atmel AT91SAM7 family of CPUs."
+}
+
+package CYGPKG_HAL_ARM_AT91SAM7SEK {
+ alias { "Atmel AT91SAM7S" hal_arm_at91sam7sek arm_at91_sam7sek }
+ directory hal/arm/at91/at91sam7sek
+ script hal_arm_at91sam7sek.cdl
+ hardware
+ description "
+ The at91sam7sek HAL package provides the support needed to run eCos on
+ an Atmel AT91SAM7S-EK development board."
+}
+
+package CYGPKG_HAL_ARM_AT91SAM7XEK {
+ alias { "Atmel AT91SAM7X" hal_arm_at91sam7xek arm_at91_sam7xek }
+ directory hal/arm/at91/at91sam7xek
+ script hal_arm_at91sam7xek.cdl
+ hardware
+ description "
+ The at91sam7xek HAL package provides the support needed to run eCos on
+ an Atmel AT91SAM7X-EK development board."
+}
+
+package CYGPKG_HAL_ARM_SAM7EX256 {
+ alias { "Olimex SAM7EX256" hal_arm_sam7ex256 arm_sam7_ex256 }
+ directory hal/arm/at91/sam7ex256
+ script hal_arm_sam7ex256.cdl
+ hardware
+ description "
+ The SAM7EX256 HAL package provides the support needed to run eCos on
+ an Olimex SAM7-EX256 development board."
+}
+
package CYGPKG_HAL_ARM_AT91_EB40 {
alias { "Atmel evaluation board (EB40)" hal_arm_at91 arm_at91_hal }
directory hal/arm/at91/eb40
Philips LPC2XXX based targets."
}
+package CYGPKG_HAL_ARM_LPC24XX {
+ alias { "NXP LPC24XX variant HAL" hal_arm_lpc24xx arm_lpc24xx_hal }
+ directory hal/arm/lpc24xx/var
+ script hal_arm_lpc24xx.cdl
+ hardware
+ description "
+ The LPC24XX HAL package provides the support needed to run eCos on
+ NXP LPC24XX based targets."
+}
+
package CYGPKG_HAL_ARM_LPC2XXX_MCB2100 {
alias { "Keil evaluation board MCB2100 " hal_mcb2100_arm }
directory hal/arm/lpc2xxx/mcb2100
LPC-2106 evaluation board from Olimex."
}
+package CYGPKG_HAL_ARM_LPC2XXX_PHYCORE229X {
+ alias { "phyCORE-LPC229x development board" arm_lpc2xxx_phycore229x }
+ directory hal/arm/lpc2xxx/phycore229x
+ script hal_arm_lpc2xxx_phycore229x.cdl
+ hardware
+ description "
+ The Phycore HAL package provides the support needed to run eCos
+ on a Phytec phyCORE-LPC229x development board."
+}
+
+package CYGPKG_HAL_ARM_LPC24XX_EA2468 {
+ alias { "Embedded Artists LPC2468 OEM board" arm_lpc2xxx_ea2468 }
+ directory hal/arm/lpc24xx/ea2468
+ script hal_arm_lpc24xx_ea2468.cdl
+ hardware
+ description "
+ The Embedded Artists LPC2468 HAL package provides the support needed
+ to run eCos on a Embbeded Artists LPC2468 OEM board."
+}
+
package CYGPKG_HAL_ARM_LPC2XXX_LPCMT {
alias { "Olimex evaluation board LPC-MT " hal_lpcmt_arm }
directory hal/arm/lpc2xxx/lpcmt
LPC-MT evaluation board from Olimex."
}
+package CYGPKG_HAL_ARM_MAC7100 {
+ alias { "Freescale MAC7100 variant HAL" hal_arm_mac7100 arm_mac7100_hal }
+ directory hal/arm/mac7100/var
+ script hal_arm_mac7100.cdl
+ hardware
+ description "
+ The mac7100 HAL package provides the support needed to run eCos on Freescale
+ MAC7100 based targets."
+}
+
+package CYGPKG_HAL_ARM_MAC7100_MACE1 {
+ alias { "MAC7100 evaluation board (MACE1)" hal_arm_mac7100_mace1 arm_mac7100_mace1_hal }
+ directory hal/arm/mac7100/mace1
+ script hal_arm_mac7100_mace1.cdl
+ hardware
+ description "
+ The MACE1 HAL package provides the support needed to run eCos on an
+ MAC7100 evaluation board (MACE1)."
+}
+
+package CYGPKG_HAL_ARM_MAC7100_MAC7100EVB {
+ alias { "MAC7100EVB evaluation board (Freescale)" hal_arm_mac7100_mac7100evb arm_mac7100_mac7100evb_hal }
+ directory hal/arm/mac7100/mac7100evb
+ script hal_arm_mac7100_mac7100evb.cdl
+ hardware
+ description "
+ The MAC7100EVB HAL package provides the support needed to run eCos on an
+ MAC7100 evaluation board (MAC7100EVB)."
+}
+
package CYGPKG_HAL_ARM_EBSA285 {
alias { "Intel EBSA285 StrongARM board" hal_arm_ebsa285 arm_ebsa285_hal }
directory hal/arm/ebsa285
description "Ethernet driver for SMSC LAN91CXX (LAN9000) controller."
}
+package CYGPKG_DEVS_ETH_SMSC_LAN92XX {
+ alias { "SMSC LAN92XX ethernet driver" lan92xx_eth_driver lan9217_eth_driver }
+ hardware
+ directory devs/eth/smsc/lan92xx
+ script smsc_lan92xx_eth_drivers.cdl
+ description "Ethernet driver for SMSC LAN92XX (LAN9217) controller."
+}
+
package CYGPKG_HAL_ARM_SA11X0_NANO {
alias { "Intel SA1110 nanoEngine eval board" hal_arm_sa11x0_nano }
directory hal/arm/sa11x0/nano
eCos on a Freescale i.MX21 ADS board."
}
+package CYGPKG_HAL_ARM_MX25 {
+ alias { "Freescale i.MX25 Chipset" hal_arm_mx25 }
+ directory hal/arm/mx25/var
+ script hal_arm_soc.cdl
+ hardware
+ description "
+ The MX25 HAL package provides the support needed to run
+ eCos on Freescale i.MX25 based systems."
+}
+
package CYGPKG_HAL_ARM_MX27 {
alias { "Freescale i.MX27 Chipset" hal_arm_mx27 }
directory hal/arm/mx27/var
eCos on a Freescale i.MX27 ADS board."
}
+package CYGPKG_HAL_ARM_MX27_3STACK {
+ alias { "Freescale i.MX27 3-Stack board" hal_arm_mx27_3stack }
+ directory hal/arm/mx27/3stack
+ script hal_arm_board.cdl
+ hardware
+ description "
+ The 3-Stack HAL package provides the support needed to run
+ eCos on a Freescale i.MX27 3-Stack board."
+}
+
package CYGPKG_HAL_ARM_MX31 {
alias { "Freescale i.MX31 Chipset" hal_arm_mx31 }
directory hal/arm/mx31/var
eCos on Freescale i.MX31 based systems."
}
-package CYGPKG_HAL_ARM_MXC92323 {
- alias { "Freescale MXC92323 Chipset" hal_arm_mxc92323 }
- directory hal/arm/mxc92323/var
+package CYGPKG_HAL_ARM_MX35 {
+ alias { "Freescale i.MX35 Chipset" hal_arm_mx35 }
+ directory hal/arm/mx35/var
script hal_arm_soc.cdl
hardware
description "
- The MXC92323 HAL package provides the support needed to run
- eCos on Freescale MXC92323 based systems."
+ The MX35 HAL package provides the support needed to run
+ eCos on Freescale i.MX35 based systems."
}
-package CYGPKG_HAL_ARM_MXC91321 {
- alias { "Freescale MXC91321 Chipset" hal_arm_mxc91321 }
- directory hal/arm/mxc91321/var
+package CYGPKG_HAL_ARM_MX35EVB {
+ alias { "Freescale i.MX35 EVB board" hal_arm_mx35evb }
+ directory hal/arm/mx35/evb
+ script hal_arm_board.cdl
+ hardware
+ description "
+ The ADS HAL package provides the support needed to run
+ eCos on a Freescale i.MX35 EVB board."
+}
+
+package CYGPKG_HAL_ARM_MX37 {
+ alias { "Freescale i.MX37 Chipset" hal_arm_mx37 }
+ directory hal/arm/mx37/var
script hal_arm_soc.cdl
hardware
description "
- The MXC91321 HAL package provides the support needed to run
- eCos on Freescale MXC91321 based systems."
+ The MX37 HAL package provides the support needed to run
+ eCos on Freescale i.MX37 based systems."
}
-package CYGPKG_HAL_ARM_MXC91311 {
- alias { "Freescale MXC91311 Chipset" hal_arm_mxc91311 }
- directory hal/arm/mxc91311/var
+package CYGPKG_HAL_ARM_MX51 {
+ alias { "Freescale i.MX51 Chipset" hal_arm_mx51 }
+ directory hal/arm/mx51/var
script hal_arm_soc.cdl
hardware
description "
- The MXC91311 HAL package provides the support needed to run
- eCos on Freescale MXC91311 based systems."
+ The MX51 HAL package provides the support needed to run
+ eCos on Freescale i.MX51 based systems."
}
-package CYGPKG_HAL_ARM_MXC91331_CHIP_DEF {
- alias { "Freescale MXC91331 Chipset" hal_arm_mxc91331_def }
+package CYGPKG_HAL_ARM_MXC91321 {
+ alias { "Freescale MXC91321 Chipset" hal_arm_mxc91321 }
directory hal/arm/mxc91321/var
- script hal_arm_mxc91331_def.cdl
+ script hal_arm_soc.cdl
hardware
description "
- MXC91331 specific defines."
+ The MXC91321 HAL package provides the support needed to run
+ eCos on Freescale MXC91321 based systems."
}
package CYGPKG_HAL_ARM_MXC91321_CHIP_DEF {
MXC91321 specific defines."
}
-package CYGPKG_HAL_ARM_MXC91131 {
- alias { "Freescale MXC91131 Chipset" hal_arm_mxc91131 }
- directory hal/arm/mxc91131/var
- script hal_arm_soc.cdl
+package CYGPKG_HAL_ARM_MX31ADS {
+ alias { "Freescale i.MX31 ADS board" hal_arm_mx31ads }
+ directory hal/arm/mx31/ads
+ script hal_arm_board.cdl
hardware
description "
- The HAL package provides the support needed to run
- eCos on Freescale based systems."
+ The ADS HAL package provides the support needed to run
+ eCos on a Freescale i.MX31 ADS board."
}
-package CYGPKG_HAL_ARM_MXC91221 {
- alias { "Freescale MXC91221 Chipset" hal_arm_mxc91221 }
- directory hal/arm/mxc91221/var
- script hal_arm_soc.cdl
+package CYGPKG_HAL_ARM_MX25_3STACK {
+ alias { "Freescale i.MX25 3-Stack board" hal_arm_mx25_3stack }
+ directory hal/arm/mx25/3stack
+ script hal_arm_board.cdl
hardware
description "
- The MXC91221 HAL package provides the support needed to run
- eCos on Freescale MXC91221 based systems."
+ The 3-Stack HAL package provides the support needed to run
+ eCos on a Freescale i.MX25 3-Stack board."
}
-package CYGPKG_HAL_ARM_MXC91231 {
- alias { "Freescale MXC91231 Chipset" hal_arm_mxc91231 }
- directory hal/arm/mxc91231/var
- script hal_arm_soc.cdl
+package CYGPKG_HAL_ARM_MX31_3STACK {
+ alias { "Freescale i.MX31 3-Stack board" hal_arm_mx31_3stack }
+ directory hal/arm/mx31/3stack
+ script hal_arm_board.cdl
hardware
description "
- The MXC91231 HAL package provides the support needed to run
- eCos on Freescale MXC91231 based systems."
+ The 3-Stack HAL package provides the support needed to run
+ eCos on a Freescale i.MX31 3-Stack board."
}
-package CYGPKG_HAL_ARM_MX31ADS {
- alias { "Freescale i.MX31 ADS board" hal_arm_mx31ads }
- directory hal/arm/mx31/ads
+package CYGPKG_HAL_ARM_MX35_3STACK {
+ alias { "Freescale i.MX35 3-Stack board" hal_arm_mx35_3stack }
+ directory hal/arm/mx35/3stack
script hal_arm_board.cdl
hardware
description "
- The ADS HAL package provides the support needed to run
- eCos on a Freescale i.MX31 ADS board."
+ The 3-Stack HAL package provides the support needed to run
+ eCos on a Freescale i.MX35 3-Stack board."
}
-package CYGPKG_HAL_ARM_I30030EVB {
- alias { "Freescale i.300-30 EVB board" hal_arm_i30030evb }
- directory hal/arm/mxc91321/evb
- script hal_arm_board_mxc91331.cdl
+package CYGPKG_HAL_ARM_MX37_3STACK {
+ alias { "Freescale i.MX37 3-Stack board" hal_arm_mx37_3stack }
+ directory hal/arm/mx37/3stack
+ script hal_arm_board.cdl
hardware
description "
- The ADS HAL package provides the support needed to run
- eCos on a Freescale i.300-30 EVB board."
+ The 3-Stack HAL package provides the support needed to run
+ eCos on a Freescale i.MX37 3-Stack board."
}
-package CYGPKG_HAL_ARM_MXC30030EVB {
- alias { "Freescale MXC300-30 EVB board" hal_arm_mxc30030evb }
- directory hal/arm/mxc91321/evb
+package CYGPKG_HAL_ARM_MX51_3STACK {
+ alias { "Freescale i.MX51 3-Stack board" hal_arm_mx51_3stack }
+ directory hal/arm/mx51/3stack
script hal_arm_board.cdl
hardware
description "
- The ADS HAL package provides the support needed to run
- eCos on a Freescale MXC300-30 EVB board."
+ The 3-Stack HAL package provides the support needed to run
+ eCos on a Freescale i.MX51 3-Stack board."
}
-package CYGPKG_HAL_ARM_MXC30020EVB {
- alias { "Freescale MXC300-20 EVB board" hal_arm_mxc30020evb }
- directory hal/arm/mxc91311/evb
+package CYGPKG_HAL_ARM_MX51_BABBAGE {
+ alias { "Freescale i.MX51 Babbage board" hal_arm_mx51_babbage }
+ directory hal/arm/mx51/babbage
script hal_arm_board.cdl
hardware
description "
- The ADS HAL package provides the support needed to run
- eCos on a Freescale MXC300-20 EVB board."
+ The babbage HAL package provides the support needed to run
+ eCos on a Freescale i.MX51 Babbage board."
}
-package CYGPKG_HAL_ARM_I30030ADS {
- alias { "Freescale i.300-30 ADS board" hal_arm_i30030ads }
- directory hal/arm/mxc91321/i30030ads
+package CYGPKG_HAL_ARM_MX51_ROCKY {
+ alias { "Freescale i.MX51 Rocky board" hal_arm_mx51_rocky }
+ directory hal/arm/mx51/rocky
script hal_arm_board.cdl
hardware
description "
- The i.300-30 ADS HAL package provides the support needed to run
- eCos on a Freescale i.300-30 ADS board."
+ The rocky HAL package provides the support needed to run
+ eCos on a Freescale i.MX51 Rocky board."
}
-package CYGPKG_HAL_ARM_MXC30031ADS {
- alias { "Freescale MXC300-31 ADS board" hal_arm_mxc30031ads }
- directory hal/arm/mxc92323/mxc30031ads
+package CYGPKG_HAL_ARM_MXC30030EVB {
+ alias { "Freescale MXC300-30 EVB board" hal_arm_mxc30030evb }
+ directory hal/arm/mxc91321/evb
script hal_arm_board.cdl
hardware
description "
- The MXC300-31 ADS HAL package provides the support needed to run
- eCos on a Freescale MXC300-31 ADS board."
+ The ADS HAL package provides the support needed to run
+ eCos on a Freescale MXC300-30 EVB board."
}
package CYGPKG_HAL_ARM_MXC30030ADS {
eCos on a Freescale MXC300-30 TOPAZ board."
}
-package CYGPKG_HAL_ARM_MXC91131EVB {
- alias { "Freescale MXC91131 EVB board" hal_arm_mxc91131evb }
- directory hal/arm/mxc91131/evb
- script hal_arm_board.cdl
- hardware
- description "
- The ADS HAL package provides the support needed to run
- eCos on a Freescale MXC91131 EVB board."
-}
-
-package CYGPKG_HAL_ARM_MXC91131EVB_MEM1 {
- alias { "Freescale MXC91131 EVB board" hal_arm_mxc91131evb_mem1 }
- directory hal/arm/mxc91131/evb
- script hal_arm_board_mem1.cdl
+package CYGPKG_HAL_ARM_TX25KARO {
+ alias { "Ka-Ro electronics TX25 processor module" hal_arm_tx25karo }
+ directory hal/arm/mx25/karo
+ script hal_arm_tx25.cdl
hardware
description "
- The EVB HAL memory specific package provides the support needed
- to run eCos on a Freescale MXC91131 EVB board with MEM1 memory card."
+ The TX25 HAL package provides the support needed to run
+ eCos on a Ka-Ro electronics TX25 processor module."
}
-package CYGPKG_HAL_ARM_MXC27520EVB {
- alias { "Freescale MXC275-20 EVB board" hal_arm_mxc27520evb }
- directory hal/arm/mxc91221/evb
- script hal_arm_board.cdl
+package CYGPKG_HAL_ARM_TX27KARO {
+ alias { "Ka-Ro electronics TX27 processor module" hal_arm_tx27karo }
+ directory hal/arm/mx27/karo
+ script hal_arm_tx27.cdl
hardware
description "
- The ADS HAL package provides the support needed to run
- eCos on a Freescale MXC275-20 EVB board."
+ The TX27 HAL package provides the support needed to run
+ eCos on a Ka-Ro electronics TX27 processor module."
}
-package CYGPKG_HAL_ARM_MXC27530EVB {
- alias { "Freescale MXC275-30 EVB board" hal_arm_mxc27530evb }
- directory hal/arm/mxc91231/evb
- script hal_arm_board.cdl
+package CYGPKG_HAL_ARM_TX37KARO {
+ alias { "KaRo electronics TX37 processor module" hal_arm_tx37karo }
+ directory hal/arm/mx37/karo
+ script hal_arm_tx37.cdl
hardware
description "
- The ADS HAL package provides the support needed to run
- eCos on a Freescale MXC275-30 EVB board."
+ The TX37 HAL package provides the support needed to run
+ eCos on a Ka-Ro electronics TX37 processor module."
}
+# --------------------------------------------------------------------------
+# SH packages
package CYGPKG_HAL_SH {
alias { "SH common HAL" hal_sh sh_hal sh_arch_hal }
directory hal/sh/arch
support for the SuperH SH4-202 MicroDev CPU board."
}
+# --------------------------------------------------------------------------
+# H8/300 packages
package CYGPKG_HAL_H8300 {
alias { "Hitachi H8300 common HAL" hal_h8300 h8300_hal}
directory hal/h8300/arch
eCos on a Hitachi Micro System Europe EDOSK-2674 Evalution board."
}
+# ==========================================================================
+# --------------------------------------------------------------------------
+# i386 packages
package CYGPKG_HAL_I386 {
alias { "i386 common HAL" hal_i386 i386_hal i386_arch_hal }
directory hal/i386/arch
PC."
}
+# --------------------------------------------------------------------------
+# Synthetic target.
package CYGPKG_HAL_SYNTH {
alias { "Linux synthetic target" linux }
directory hal/synth/arch
i386 processor-specific support for the Linux synthetic target"
}
+# --------------------------------------------------------------------------
+# SPARClite packages
package CYGPKG_HAL_SPARCLITE {
alias { "SPARClite common HAL" hal_sparclite sparclite_hal sparclite_arch_hal }
directory hal/sparclite/arch
with the SPARClite simulator."
}
+# --------------------------------------------------------------------------
+# SPARC V7/V8 packages
package CYGPKG_HAL_SPARC {
alias { "SPARC V7/V8 common HAL" hal_sparc sparc_hal sparc_arch_hal }
directory hal/sparc/arch
with both real hardware and the TSIM/LEON simulator."
}
+# --------------------------------------------------------------------------
+# PowerPC packages
package CYGPKG_HAL_POWERPC {
alias { "PowerPC common HAL" hal_powerpc powerpc_hal powerpc_arch_hal }
directory hal/powerpc/arch
the I/O devices, so device drivers cannot be used."
}
+# --------------------------------------------------------------------------
+# MIPS packages
package CYGPKG_HAL_MIPS {
alias { "MIPS common HAL" hal_mips mips_hal mips_arch_hal }
directory hal/mips/arch/
actual hardware."
}
+# --------------------------------------------------------------------------
+# MN10300 packages
package CYGPKG_HAL_MN10300 {
alias { "MN10300 common HAL" hal_mn10300 mn10300_hal mn10300_arch_hal }
directory hal/mn10300/arch
actual hardware for the AM33 ASB2305 evaluation board."
}
+# --------------------------------------------------------------------------
+# NEC packages
package CYGPKG_HAL_V85X {
alias { "NEC V85x common HAL" hal_v85x nec_arch_hal }
directory hal/v85x/arch
evaluation board."
}
+# --------------------------------------------------------------------------
+# m68k packages
package CYGPKG_HAL_M68K {
alias { "m68k common HAL" hal_m68k m68k_hal m68k_arch_hal }
directory hal/m68k/arch
for the Motorola mcf5272c3 evaluation board platform."
}
+# --------------------------------------------------------------------------
+# ColdFire packages
+
+package CYGPKG_HAL_COLDFIRE {
+ alias { "ColdFire common HAL" hal_coldfire coldfire_hal
+coldfire_arch_hal }
+ directory hal/coldfire/arch
+ script hal_coldfire.cdl
+ hardware
+
+ description "The ColdFire architecture HAL package provides generic
+ support for this processor architecture. It is also
+ necessary to select a specific target platform HAL
+ package."
+
+}
+
+package CYGPKG_HAL_COLDFIRE_MCF5272 {
+ alias { "ColdFire MCF5272 processor variant HAL"
+ hal_coldfire_mcf5272
+ coldfire_mcf5272_hal }
+ directory hal/coldfire/mcf5272
+ script hal_coldfire_mcf5272.cdl
+ hardware
+ description "The ColdFire MCF5272 processor variant HAL package
+ provides generic support for this processor architecture.
+ It is also necessary to select a specific target platform
+ HAL package."
+
+}
+
+package CYGPKG_HAL_COLDFIRE_M5272C3 {
+ alias { "Freescale M5272C3 evaluation board platform HAL"
+ hal_coldfire_m5272c3
+ coldfire_m5272c3_hal }
+ directory hal/coldfire/m5272c3
+ script hal_coldfire_m5272c3.cdl
+ hardware
+
+ description "The Freescale M5272C3 evaluation board platform HAL
+ package should be used when targeting the actual hardware
+ for the Freescale M5272C3 evaluation board platform."
+
+}
+
+package CYGPKG_IO_SERIAL_COLDFIRE_MCF5272 {
+ alias { "ColdFire MCF5272 serial device drivers"
+ devs_serial_coldfire_mcf5272_serial_driver }
+ hardware
+ directory devs/serial/coldfire/mcf5272
+ script mcf5272_serial.cdl
+ description "ColdFire MCF5272 serial device drivers."
+}
+
+# --------------------------------------------------------------------------
+# CalmRISC16 packages
package CYGPKG_HAL_CALM16 {
alias { "CalmRISC16 common HAL" hal_calm16 calm16_hal calm16_arch_hal }
directory hal/calmrisc16/arch/
The CalmRISC16 HAL package should be used when targetting the
actual hardware. "
}
+# --------------------------------------------------------------------------
+# CalmRISC32 packages
package CYGPKG_HAL_CALM32 {
alias { "CalmRISC32 common HAL" hal_calm32 calm32_hal calm32_arch_hal }
actual hardware. "
}
+# --------------------------------------------------------------------------
+# FUJITSU packages
package CYGPKG_HAL_FRV {
alias { "FR-V (Fujitsu) common HAL" hal_frv frv_hal frv_arch_hal }
directory hal/frv/arch
Davicom DM9000 ethernet interface."
}
+# FR30 packages
+package CYGPKG_HAL_FR30 {
+ alias { "Fujitsu FR30 architecture (FR30/FR50/FR60)" hal_fr30
+ fr30_hal }
+ directory hal/fr30/arch
+ script hal_fr30.cdl
+ hardware
+ description "
+The Fujitsu FR30 HAL package provides the generic support needed to run eCos on
+a FR30 based microcontroller. FR50 and FR60 architectures should also select
+this one."
+}
+
+package CYGPKG_HAL_FR30_MB91360 {
+ alias { "Fujitsu MB31360 variant (FR50)" hal_fr30_mb91360
+ fr30_mb91360_hal }
+ directory hal/fr30/mb91360
+ script hal_fr30_mb91360.cdl
+ hardware
+ description "
+The Fujitsu MB91360 HAL package provides the support needed to run eCos on
+the Phytec MB91F364G Kit board. It contains a MB91F364G
+Microcontroller from Fujitsu with a FR50 Core. So FR30 support is needed."
+}
+
+package CYGPKG_HAL_FR30_MB91301 {
+ alias { "Fujitsu MB31301 variant (FR60)" hal_fr30_mb91301
+ fr30_mb91301_hal }
+ directory hal/fr30/mb91301
+ script hal_fr30_mb91301.cdl
+ hardware
+ description "
+The Fujitsu MB91301 HAL package provides the support needed to run eCos on
+the Fujitsu Starterkit MB91302 Evaluation board. It contains a MB91302A
+Microcontroller from Fujitsu with a FR60 Core. So FR30 support is also needed."
+}
+
+package CYGPKG_HAL_FR30_MB91360_PHYTEC91F364G {
+ alias { "Phytec Fujitsu MB91F364G Kit board" hal_fr30_phytec91f364g
+ fr30_phytec91f364g_hal }
+ directory hal/fr30/phytec91f364g
+ script hal_fr30_phytec91f364g.cdl
+ hardware
+ description "
+The Phytec91f364g HAL package provides the support needed to run eCos on
+the Phytec Fujitsu MB91F364G Kit board. It contains a MB91F364G
+Microcontroller from Fujitsu with a FR50 Core. So FR30 support is needed."
+}
+
+package CYGPKG_HAL_FR30_MB91301_SKMB91302 {
+ alias { "Fujitsu Starterkit MB91302 board" hal_fr30_skmb91302
+ fr30_skmb91302_hal }
+ directory hal/fr30/skmb91302
+ script hal_fr30_skmb91302.cdl
+ hardware
+ description "
+The SKMB91302 HAL package provides the support needed to run eCos on
+the Fujitsu Starterkit MB91302 board. It contains a MB91302
+Microcontroller from Fujitsu with a FR60 Core. So FR30 support is needed."
+}
+
+package CYGPKG_DEVS_FLASH_FR30_SKMB91302 {
+ alias { "Fujitsu Starterkit MB91302 FLASH memory support" flash_skmb91302 }
+ directory devs/flash/fr30/skmb91302
+ script flash_skmb91302.cdl
+ hardware
+ description "
+ This package contains hardware support for FLASH memory
+ on the Fujitsu Starterkit MB91302 platform.
+ (AMD 29DL640E-90 Device)"
+}
+
+package CYGPKG_DEVS_ETH_ARM_AT91 {
+ alias { "AT91 Ethernet driver" at91_eth_driver }
+ directory devs/eth/arm/at91
+ script at91_eth.cdl
+ hardware
+ description "Ethernet driver for the AT91 family of chips"
+}
+
+# --------------------------------------------------------------------------
+# FRV targets
target frv400 {
alias { "Fujitsu development board (FR-V 400)" FRV400 }
packages { CYGPKG_HAL_FRV
MB93090-PD00 Portable Development Kit."
}
+# FR30 Targets
+target phytec91f364g {
+ alias { "Phytec Fujitsu MB91F364G Kit board" phytec91f364g }
+ packages { CYGPKG_HAL_FR30
+ CYGPKG_HAL_FR30_MB91360
+ CYGPKG_HAL_FR30_MB91360_PHYTEC91F364G
+}
+ description "
+The Phytec91f364g HAL package provides the support needed to run eCos on
+the Phytec Fujitsu MB91F364G Kit board. It contains a MB91F364G
+Microcontroller from Fujitsu with a FR50 Core. So FR30 support is
+included."
+}
+
+target skmb91302 {
+ alias { "Fujitsu Starterkit MB91302 board" skmb91302 }
+ packages { CYGPKG_HAL_FR30
+ CYGPKG_HAL_FR30_MB91301
+ CYGPKG_HAL_FR30_MB91301_SKMB91302
+ CYGPKG_DEVS_FLASH_FR30_SKMB91302
+ CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+}
+ description "
+The Starterkit MB91302 HAL package provides the support needed to run
+eCos on the Fujitsu Starterkit MB91302 board. It contains a MB91302
+Microcontroller from Fujitsu with a FR60 Core. So FR30 support is
+included."
+}
+
+# --------------------------------------------------------------------------
+# ARM Targets
target pid {
alias { "ARM development board (PID)" PID }
packages { CYGPKG_HAL_ARM
Diospsis evaluation board (jtst)."
}
+target at91sam7sek {
+ alias { "Atmel AT91SAM7SEK evaluation board" at91_at91sam7sek }
+ packages { CYGPKG_HAL_ARM
+ CYGPKG_HAL_ARM_AT91
+ CYGPKG_HAL_ARM_AT91SAM7
+ CYGPKG_HAL_ARM_AT91SAM7SEK
+ CYGPKG_IO_SERIAL_ARM_AT91
+ CYGPKG_DEVS_FLASH_AT91
+ CYGPKG_DEVS_SPI_ARM_AT91
+ CYGPKG_DEVICES_WATCHDOG_ARM_AT91WDTC
+ CYGPKG_DEVS_USB_AT91
+ }
+ description "
+ The at91sam7sek target provides the packages needed to run eCos on an
+ Atmel AT91SAM7S-EK evaluation board."
+}
+
+target at91sam7xek {
+ alias { "Atmel AT91SAM7XEK evaluation board" at91_at91sam7xek }
+ packages { CYGPKG_HAL_ARM
+ CYGPKG_HAL_ARM_AT91
+ CYGPKG_HAL_ARM_AT91SAM7
+ CYGPKG_HAL_ARM_AT91SAM7XEK
+ CYGPKG_IO_SERIAL_ARM_AT91
+ CYGPKG_DEVS_FLASH_AT91
+ CYGPKG_DEVS_SPI_ARM_AT91
+ CYGPKG_DEVICES_WATCHDOG_ARM_AT91WDTC
+ CYGPKG_DEVS_USB_AT91
+ CYGPKG_DEVS_ETH_PHY
+ CYGPKG_DEVS_ETH_ARM_AT91
+ }
+ description "
+ The at91sam7xek target provides the packages needed to run eCos on an
+ Atmel AT91SAM7X-EK evaluation board."
+}
+
+target sam7ex256 {
+ alias { "Olimex SAM7-EX256 evaluation board" at91_sam7ex256 }
+ packages { CYGPKG_HAL_ARM
+ CYGPKG_HAL_ARM_AT91
+ CYGPKG_HAL_ARM_AT91SAM7
+ CYGPKG_HAL_ARM_SAM7EX256
+ CYGPKG_IO_SERIAL_ARM_AT91
+ CYGPKG_DEVS_FLASH_AT91
+ CYGPKG_DEVS_SPI_ARM_AT91
+ CYGPKG_DEVICES_WATCHDOG_ARM_AT91WDTC
+ CYGPKG_DEVS_USB_AT91
+ CYGPKG_DEVS_ETH_PHY
+ CYGPKG_DEVS_ETH_ARM_AT91
+ CYGPKG_DEVS_CAN_AT91SAM7
+ }
+ description "
+ The SAM7EX256 target provides the packages needed to run eCos on an
+ Olimex SAM7-EX256 evaluation board."
+}
+
target eb40a {
alias { "Atmel evaluation board (EB40A)" at91_eb40a }
packages { CYGPKG_HAL_ARM
LPC-LPCMT evaluation board from Olimex."
}
+target phycore229x {
+ alias { "phyCORE-LPC2294/92 development board HAL" phycore229x }
+ packages { CYGPKG_HAL_ARM
+ CYGPKG_HAL_ARM_LPC2XXX
+ CYGPKG_HAL_ARM_LPC2XXX_PHYCORE229X
+ CYGPKG_IO_SERIAL_GENERIC_16X5X
+ CYGPKG_IO_SERIAL_ARM_LPC2XXX
+ CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
+ CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+ CYGPKG_DEVS_FLASH_PHYCORE229X
+ CYGPKG_DEVS_ETH_ARM_PHYCORE229X
+ CYGPKG_DEVS_ETH_SMSC_LAN91CXX
+ CYGPKG_DEVS_CAN_LPC2XXX
+ }
+ description "
+ The phyCORE-LPC229x HAL package provides the support
+ needed to run eCos on a Phytec phyCORE-LPC2294/2
+ development board."
+}
+
+target ea2468 {
+ alias { "Embedded Artists LPC2468 OEM board HAL" ea2468 }
+ packages { CYGPKG_HAL_ARM
+ CYGPKG_HAL_ARM_LPC24XX
+ CYGPKG_HAL_ARM_LPC24XX_EA2468
+ CYGPKG_IO_SERIAL_GENERIC_16X5X
+ CYGPKG_IO_SERIAL_ARM_LPC24XX
+ CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
+ CYGPKG_DEVS_CAN_LPC2XXX
+ CYGPKG_DEVS_FLASH_EA2468
+ CYGPKG_DEVS_FLASH_SST_39VFXXX
+ }
+ description "
+ The Embedded Artists LPC2468 HAL package provides the support
+ needed to run eCos on an Embedded Artists LPC2468 OEM board."
+}
+
+target mace1 {
+ alias { "MACE1 - a MAC7100 evaluation board" mac7100_mace1 }
+ packages { CYGPKG_HAL_ARM
+ CYGPKG_HAL_ARM_MAC7100
+ CYGPKG_HAL_ARM_MAC7100_MACE1
+ CYGPKG_IO_SERIAL_FREESCALE_ESCI_H
+ CYGPKG_IO_SERIAL_FREESCALE_ESCI
+ }
+ description "
+ The mace1 target provides the packages needed to run eCos
+ on MAC7100 evaluation board (MACE1). "
+}
+
+target mac7100evb {
+ alias { "MAC7100EVB - a MAC7100 evaluation board" mac7100_mac7100evb }
+ packages { CYGPKG_HAL_ARM
+ CYGPKG_HAL_ARM_MAC7100
+ CYGPKG_HAL_ARM_MAC7100_MAC7100EVB
+ CYGPKG_IO_SERIAL_FREESCALE_ESCI_H
+ CYGPKG_IO_SERIAL_FREESCALE_ESCI
+ }
+ description "
+ The MAC7100EVB target provides the packages needed to run eCos
+ on Freescale MAC7100EVB evaluation board. "
+}
+
target ebsa285 {
alias { "Intel EBSA285 StrongARM board" ebsa }
packages { CYGPKG_HAL_ARM
eCos on a Freescale i.MX21 ADS board."
}
+target mx25_3stack {
+ alias { "Freescale i.MX25 3-Stack board" mx25 mx25_3stack }
+ packages { CYGPKG_HAL_ARM
+ CYGPKG_HAL_ARM_MX25
+ CYGPKG_HAL_ARM_MX25_3STACK
+ }
+ description "
+ The mx25_3stack target provides the packages needed to run
+ eCos on a Freescale i.MX25 3-Stack board."
+}
+
target mx27ads {
alias { "Freescale i.MX27 ADS board" mx27 mx27ads }
packages { CYGPKG_HAL_ARM
eCos on a Freescale i.MX27 ADS board."
}
+target mx27_3stack {
+ alias { "Freescale i.MX27 3-Stack board" mx27_3stack }
+ packages { CYGPKG_HAL_ARM
+ CYGPKG_HAL_ARM_MX27
+ CYGPKG_HAL_ARM_MX27_3STACK
+ }
+ description "
+ The mx27_3stack target provides the packages needed to run
+ eCos on a Freescale i.MX27 3-Stack board."
+}
+
+target tx25karo {
+ alias { "Ka-Ro electronics TX25 processor module" mx25 tx25karo }
+ packages { CYGPKG_HAL_ARM
+ CYGPKG_HAL_ARM_MX25
+ CYGPKG_HAL_ARM_TX25KARO
+ }
+ description "
+ The tx25karo target provides the packages needed to run
+ eCos on a Ka-Ro electronics TX25 module equipped with a
+ Freescale i.MX25 processor."
+}
+
+target tx27karo {
+ alias { "Ka-Ro electronics TX27 processor module" mx27 tx27karo }
+ packages { CYGPKG_HAL_ARM
+ CYGPKG_HAL_ARM_MX27
+ CYGPKG_HAL_ARM_TX27KARO
+ }
+ description "
+ The tx27karo target provides the packages needed to run
+ eCos on a Ka-Ro electronics TX27 module equipped with a
+ Freescale i.MX27 processor."
+}
+
+target tx37karo {
+ alias { "Ka-Ro electronics TX37 processor module" mx37 tx37karo }
+ packages { CYGPKG_HAL_ARM
+ CYGPKG_HAL_ARM_MX37
+ CYGPKG_HAL_ARM_TX37KARO
+ }
+ description "
+ The tx37karo target provides the packages needed to run
+ eCos on a Ka-Ro electronics TX37 module equipped with a
+ Freescale i.MX37 processor."
+}
+
target mx31ads {
alias { "Freescale i.MX31 ADS board" mx31 mx31ads }
packages { CYGPKG_HAL_ARM
eCos on a Freescale i.MX31 ADS board."
}
-target i30030evb {
- alias { "Freescale i.300-30 EVB board" i30030evb}
+target mx31_3stack {
+ alias { "Freescale i.MX31 3-Stack board" mx31 mx31_3stack }
packages { CYGPKG_HAL_ARM
- CYGPKG_HAL_ARM_MXC91331_CHIP_DEF
- CYGPKG_HAL_ARM_MXC91321
- CYGPKG_HAL_ARM_I30030EVB
+ CYGPKG_HAL_ARM_MX31
+ CYGPKG_HAL_ARM_MX31_3STACK
}
description "
- The i.300-30 EVB target provides the packages needed to run
- eCos on a Freescale i.300-30 EVB board."
+ The mx31_3stack target provides the packages needed to run
+ eCos on a Freescale i.MX31 3-Stack board."
}
-target mxc30030evb {
- alias { "Freescale MXC30030 EVB board" mxc30030evb}
+target mx35_3stack {
+ alias { "Freescale i.MX35 3-Stack board" mx35 mx35_3stack }
packages { CYGPKG_HAL_ARM
- CYGPKG_HAL_ARM_MXC91321_CHIP_DEF
- CYGPKG_HAL_ARM_MXC91321
- CYGPKG_HAL_ARM_MXC30030EVB
+ CYGPKG_HAL_ARM_MX35
+ CYGPKG_HAL_ARM_MX35_3STACK
}
description "
- The MXC300-30 EVB target provides the packages needed to run
- eCos on a Freescale MXC300-30 EVB board."
+ The mx35_3stack target provides the packages needed to run
+ eCos on a Freescale i.MX35 3-Stack board."
}
-target mxc30020evb {
- alias { "Freescale MXC30020 EVB board" mxc30020evb}
+target mx35evb {
+ alias { "Freescale i.MX35 EVB board" mx35evb }
packages { CYGPKG_HAL_ARM
- CYGPKG_HAL_ARM_MXC91311
- CYGPKG_HAL_ARM_MXC30020EVB
+ CYGPKG_HAL_ARM_MX35
+ CYGPKG_HAL_ARM_MX35EVB
}
description "
- The MXC300-20 EVB target provides the packages needed to run
- eCos on a Freescale MXC300-20 EVB board."
+ The mx35evb target provides the packages needed to run
+ eCos on a Freescale i.MX35 EVB board."
}
-target i30030ads {
- alias { "Freescale i.300-30 ADS board" i30030ads }
+target mx37_3stack {
+ alias { "Freescale i.MX37 3-Stack board" mx37 mx37_3stack }
packages { CYGPKG_HAL_ARM
- CYGPKG_HAL_ARM_MXC91331_CHIP_DEF
- CYGPKG_HAL_ARM_MXC91321
- CYGPKG_HAL_ARM_I30030ADS
+ CYGPKG_HAL_ARM_MX37
+ CYGPKG_HAL_ARM_MX37_3STACK
}
description "
- The i.300-30 ADS target provides the packages needed to run
- eCos on a Freescale i.300-30 ADS board."
+ The mx37_3stack target provides the packages needed to run
+ eCos on a Freescale i.MX37 3-Stack board."
}
-target mxc30030ads {
- alias { "Freescale MXC300-30 ADS board" mxc30030ads }
+target mx51_3stack {
+ alias { "Freescale i.MX51 3-Stack board" mx51 mx51_3stack }
packages { CYGPKG_HAL_ARM
- CYGPKG_HAL_ARM_MXC91321_CHIP_DEF
- CYGPKG_HAL_ARM_MXC91321
- CYGPKG_HAL_ARM_MXC30030ADS
+ CYGPKG_HAL_ARM_MX51
+ CYGPKG_HAL_ARM_MX51_3STACK
}
description "
- The MXC300-30 ADS target provides the packages needed to run
- eCos on a Freescale MXC300-30 ADS board."
+ The mx51_3stack target provides the packages needed to run
+ eCos on a Freescale i.MX51 3-Stack board."
}
-target mxc30031ads {
- alias { "Freescale MXC300-31 ADS board" mxc30031ads }
+target mx51_babbage {
+ alias { "Freescale i.MX51 Babbage board" mx51 mx51_babbage }
packages { CYGPKG_HAL_ARM
- CYGPKG_HAL_ARM_MXC92323
- CYGPKG_HAL_ARM_MXC30031ADS
+ CYGPKG_HAL_ARM_MX51
+ CYGPKG_HAL_ARM_MX51_BABBAGE
}
description "
- The MXC300-31 ADS target provides the packages needed to run
- eCos on a Freescale MXC300-31 ADS board."
+ The mx51_babbage target provides the packages needed to run
+ eCos on a Freescale i.MX51 Babbage board."
}
-target mxc30030topaz {
- alias { "Freescale MXC300-30 TOPAZ board" mxc30030topaz }
+target mx51_rocky {
+ alias { "Freescale i.MX51 Rocky board" mx51 mx51_rocky }
packages { CYGPKG_HAL_ARM
- CYGPKG_HAL_ARM_MXC91321_CHIP_DEF
- CYGPKG_HAL_ARM_MXC91321
- CYGPKG_HAL_ARM_MXC30030TOPAZ
+ CYGPKG_HAL_ARM_MX51
+ CYGPKG_HAL_ARM_MX51_ROCKY
}
description "
- The MXC300-30 TOPAZ target provides the packages needed to run
- eCos on a Freescale MXC300-30 TOPAZ board."
+ The mx51_rocky target provides the packages needed to run
+ eCos on a Freescale i.MX51 Rocky board."
}
-target mxc91131evb {
- alias { "Freescale MXC91131 EVB board" mxc91131evb }
- packages { CYGPKG_HAL_ARM
- CYGPKG_HAL_ARM_MXC91131
- CYGPKG_HAL_ARM_MXC91131EVB
- }
- description "
- The MXC91131 EVB target provides the packages needed to run
- eCos on a Freescale MXC91131 EVB board."
-}
-
-target mxc91131evbmem1 {
- alias { "Freescale MXC91131 EVB board" mxc91131evbmem1 }
- packages { CYGPKG_HAL_ARM
- CYGPKG_HAL_ARM_MXC91131
- CYGPKG_HAL_ARM_MXC91131EVB_MEM1
+target mxc30030evb {
+ alias { "Freescale MXC30030 EVB board" mxc30030evb}
+ packages { CYGPKG_HAL_ARM
+ CYGPKG_HAL_ARM_MXC91321_CHIP_DEF
+ CYGPKG_HAL_ARM_MXC91321
+ CYGPKG_HAL_ARM_MXC30030EVB
}
description "
- The MXC91131 EVB MEM1 target provides the packages needed to run
- eCos on a Freescale MXC91131 EVB board with MEM1 memory card."
+ The MXC300-30 EVB target provides the packages needed to run
+ eCos on a Freescale MXC300-30 EVB board."
}
-target mxc27520evb {
- alias { "Freescale MXC275-20 EVB board" mxc27520evb }
+target mxc30030ads {
+ alias { "Freescale MXC300-30 ADS board" mxc30030ads }
packages { CYGPKG_HAL_ARM
- CYGPKG_HAL_ARM_MXC91221
- CYGPKG_HAL_ARM_MXC27520EVB
+ CYGPKG_HAL_ARM_MXC91321_CHIP_DEF
+ CYGPKG_HAL_ARM_MXC91321
+ CYGPKG_HAL_ARM_MXC30030ADS
}
description "
- The MXC275-20 EVB target provides the packages needed to run
- eCos on a Freescale MXC275-20 EVB board."
+ The MXC300-30 ADS target provides the packages needed to run
+ eCos on a Freescale MXC300-30 ADS board."
}
-target mxc27530evb {
- alias { "Freescale MXC275-30 EVB board" mxc27530evb }
+target mxc30030topaz {
+ alias { "Freescale MXC300-30 TOPAZ board" mxc30030topaz }
packages { CYGPKG_HAL_ARM
- CYGPKG_HAL_ARM_MXC91231
- CYGPKG_HAL_ARM_MXC27530EVB
+ CYGPKG_HAL_ARM_MXC91321_CHIP_DEF
+ CYGPKG_HAL_ARM_MXC91321
+ CYGPKG_HAL_ARM_MXC30030TOPAZ
}
description "
- The MXC275-30 EVB target provides the packages needed to run
- eCos on a Freescale MXC275-30 EVB board."
+ The MXC300-30 TOPAZ target provides the packages needed to run
+ eCos on a Freescale MXC300-30 TOPAZ board."
}
+# --------------------------------------------------------------------------
+# SH targets
target sh7708 {
alias { "Hitachi EDK/SH7708 board" edk7708 }
packages { CYGPKG_HAL_SH
eCos on a SuperH SH4-202 MicroDev CPU board."
}
+# --------------------------------------------------------------------------
+# i386 targets
target pc_i82559 {
alias { "i386 PC target with i82559 ethernet" pc }
packages { CYGPKG_HAL_I386
on a standard i386 PC under wmWare."
}
+target pc_usb_d12 {
+ alias { "i386 PC target with SoRo PC/104 D12 USB Slave" }
+ packages { CYGPKG_HAL_I386
+ CYGPKG_HAL_I386_GENERIC
+ CYGPKG_HAL_I386_PC
+ CYGPKG_HAL_I386_PCMB
+ CYGPKG_IO_PCI
+ CYGPKG_IO_SERIAL_GENERIC_16X5X
+ CYGPKG_IO_SERIAL_I386_PC
+ CYGPKG_IO_USB
+ CYGPKG_IO_USB_SLAVE
+ CYGPKG_DEVS_USB_D12
+ CYGPKG_DEVS_USB_I386_SOROD12
+ CYGPKG_IO_FILEIO
+ CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS12887
+ CYGPKG_DEVICES_WALLCLOCK_I386_PC
+ }
+ description "
+ Provides the packages needed to run eCos binaries
+ on a standard i386 PC motherboard with USB Slave support for the
+ Philips D12 chip."
+}
+
+# --------------------------------------------------------------------------
+# Synthetic targets.
target linux {
alias { "Linux synthetic target" i386linux }
packages { CYGPKG_HAL_SYNTH
Linux kernel."
}
+# --------------------------------------------------------------------------
+# SPARClite targets
target sleb {
alias { "Fujitsu MB86800-MA01 board" }
packages { CYGPKG_HAL_SPARCLITE
on the SPARClite simulator."
}
+# --------------------------------------------------------------------------
+# SPARC V7/V8 targets
target sparc_erc32 {
alias { "ERC32 processor" erc32 }
packages { CYGPKG_HAL_SPARC
on the LEON processor or TSIM/LEON simulator."
}
+# --------------------------------------------------------------------------
+# PowerPC targets
target cme555 {
alias { "Axiom's CME555 board" cme555 }
packages { CYGPKG_HAL_POWERPC
CYGPKG_HAL_POWERPC_CME555
CYGPKG_DEVS_FLASH_CME555
CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
- CYGPKG_IO_SERIAL_POWERPC_CME555
+ CYGPKG_IO_SERIAL_POWERPC_MPC555
CYGPKG_DEVICES_WALLCLOCK_MPC5xx
}
description "
CYGPKG_HAL_POWERPC_EC555
CYGPKG_DEVS_FLASH_EC555
CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
- CYGPKG_IO_SERIAL_POWERPC_EC555
+ CYGPKG_IO_SERIAL_POWERPC_MPC555
CYGPKG_DEVICES_WALLCLOCK_MPC5xx
}
description "
eCos in the PSIM simulator."
}
+##-------------------------------------------------------------------------------------------
+## Cogent CSB281 (PowerPC 8245) packages
+##
package CYGPKG_HAL_POWERPC_CSB281 {
alias { "Cogent PowerPC 8245 board" hal_powerpc_csb281 }
directory hal/powerpc/csb281
eCos on the Cogent CSB281 (8245) board."
}
+# --------------------------------------------------------------------------
+# MIPS targets
+
target jmr3904 {
alias { "Toshiba JMR-TX3904 board" jmr tx39 }
packages { CYGPKG_HAL_MIPS
eCos on a MIPS IDT IDT79S334A reference board."
}
+# --------------------------------------------------------------------------
+# MN10300 targets
target am31_sim {
alias { "MN10300 AM31 minimal simulator" }
packages { CYGPKG_HAL_MN10300
eCos on a Matsushita ASB2305 board."
}
+# --------------------------------------------------------------------------
+# NEC targets
target ceb_v850 {
alias { "Cosmo CEB-V850 board" CEB ceb_v850_sa1 }
packages { CYGPKG_HAL_V85X
Cosmo CEB-V850 evaluation board fitted with a NEC V850/SA1 or NEC V850/SB1."
}
+# --------------------------------------------------------------------------
+# m68k targets
target mcf5272c3 {
alias { "Motorola mcf5272c3 evaluation board" }
packages {
}
+# --------------------------------------------------------------------------
+# ColdFire targets
+target coldfire_m5272c3 {
+ alias { "Freescale M5272C3 evaluation board" }
+ packages {
+ CYGPKG_HAL_COLDFIRE
+ CYGPKG_HAL_COLDFIRE_MCF5272
+ CYGPKG_HAL_COLDFIRE_M5272C3
+ CYGPKG_IO_SERIAL_COLDFIRE_MCF5272
+ }
+ description "
+ The M5272C3 target provides the packages needed to run eCos on
+ the Freescale M5272C3 evaluation board."
+
+}
+
+# --------------------------------------------------------------------------
+# H8 targets
target h8300h_sim {
alias { "H8/300H minimal simulator" }
packages { CYGPKG_HAL_H8300
eCos in the Hitachi Micro System Europe EDOSK-2674 Evalution board."
}
+# --------------------------------------------------------------------------
+# CalmRISC16 targets
target calm16_ceb {
alias { "CalmRISC16 Core Eval Board" }
packages { CYGPKG_HAL_CALM16
The calm16_ceb target provides the packages needed to run
eCos on the CalmRISC16 Core Evaluation Board."
}
+# --------------------------------------------------------------------------
+# CalmRISC32 targets
target calm32_ceb {
alias { "CalmRISC32 Core Eval Board" }
eCos on the CalmRISC32 Core Evaluation Board."
}
+# --------------------------------------------------------------------------
+
package CYGPKG_HAL_POWERPC_TS1000 {
alias { "Allied Telesyn TS1000 board" hal_powerpc_ts1000 }
directory hal/powerpc/ts1000
eCos on a Allied Telesyn TS1000 (PPC855T) board."
}
+# --------------------------------------------------------------------------
+
package CYGPKG_DEVS_FLASH_UE250 {
alias { "FLASH memory support for uE250" flash_uE250 }
directory devs/flash/arm/uE250
eCos on an NMI uEngine uE250 board."
}
+# --------------------------------------------------------------------------
+
package CYGPKG_DEVS_FLASH_PICASSO {
alias { "FLASH memory support for picasso" flash_picasso }
directory devs/flash/arm/picasso
eCos on an NMI uEngine picasso board."
}
+# --------------------------------------------------------------------------
+
package CYGPKG_HAL_POWERPC_ADDER {
alias { "A&M Adder PPC85x board" hal_powerpc_adder powerpc_adder_hal }
directory hal/powerpc/adder
eCos on a A&M Adder PPC852T board."
}
+# --------------------------------------------------------------------------
+
package CYGPKG_HAL_POWERPC_RATTLER {
alias { "A&M Rattler MPC8250 board" hal_powerpc_rattler powerpc_rattler_hal }
directory hal/powerpc/rattler
eCos on an Analogue & Micro Rattler (MPC8250) board."
}
+##-------------------------------------------------------------------------------------------
+## TAMS MOAB (PowerPC 405GPr) packages
+##
package CYGPKG_HAL_POWERPC_MOAB {
alias { "TAMS PowerPC 405GP board" hal_powerpc_moab }
directory hal/powerpc/moab
The moab target provides the packages needed to run
eCos on the TAMS MOAB (405GPr) board."
}
+##-------------------------------------------------------------------------------------------
+# --------------------------------------------------------------------------
+
+# Realtek 8139 (PCI) Ethernet driver
package CYGPKG_DEVS_ETH_RLTK_8139 {
alias { "Realtek 8139 ethernet driver" rltk8139_eth_driver }
hardware
on a standard i386 PC motherboard, using a Realtek 8139 network card."
}
+# --------------------------------------------------------------------------
+
package CYGPKG_HAL_ARM_GPS4020 {
alias { "GPS4020" hal_gps4020 }
directory hal/arm/gps4020
eCos on a GPS-4020 board."
}
+# --------------------------------------------------------------------------
+
package CYGPKG_VNC_SERVER {
alias { "VNC server" vnc_server }
directory net/vnc_server
description "VNC server."
}
+# --------------------------------------------------------------------------
+
package CYGPKG_DEVS_DISK_V85X_EDB_V850 {
alias { "Elatec v850 development board disk driver" edb_v850_disk }
directory devs/disk/v85x/edb_v850
description "Disk driver for generic IDE interface."
}
+package CYGPKG_DEVS_DISK_MMC {
+ alias { "Disk driver for MMC cards" mmcdisk mmc_disk_driver }
+ directory devs/disk/generic/mmc
+ script devs_disk_mmc.cdl
+ hardware
+ description "Disk driver for MMC cards"
+}
+
package CYGPKG_IO_DISK {
alias { "Disk device drivers" disk io_disk }
directory io/disk
This package contains a FAT filesystem implementation."
}
+
+# --------------------------------------------------------------------------
+
package CYGPKG_NET_LWIP {
alias {"lwIP" lwip}
directory net/lwip_tcpip
description "Lightweight TCP/IP stack: lwIP"
}
-package CYGPKG_HAL_ARM_TX27KARO {
- alias { "Ka-Ro electronics TX27 processor module" hal_arm_tx27karo }
- directory hal/arm/mx27/karo
- script hal_arm_tx27.cdl
- hardware
- description "
- The TX27 HAL package provides the support needed to run
- eCos on a Ka-Ro electronics TX27 processor module."
-}
-
-target tx27karo {
- alias { "Ka-Ro electronics TX27 processor module" mx27 tx27karo }
- packages { CYGPKG_HAL_ARM
- CYGPKG_HAL_ARM_MX27
- CYGPKG_HAL_ARM_TX27KARO
- }
- description "
- The tx27karo target provides the packages needed to run
- eCos on a Ka-Ro electronics TX27 module equipped with a
- Freescale i.MX27 processor."
-}
-
-package CYGPKG_DEVS_ETH_ARM_TX27 {
- alias { "Ethernet driver for Ka-Ro electronics TX27 processor module" devs_eth_arm_tx27 }
- directory devs/eth/arm/tx27karo
- script tx27_eth_drivers.cdl
- hardware
- description "
- This package provides Ethernet support for the Ka-Ro electronics TX27 processor module."
+package CYGPKG_ATHTTPD {
+ alias { "ATHTTP server" athttpd }
+ directory net/athttpd
+ script httpd.cdl
+ description "Another Tiny HTTP server."
}
+2007-06-28 Gary Thomas <gary@mlbassoc.com>
+
+ * src/strerror.cxx: Add (char *) casts to make GCC 4.2.x happy.
+
2003-06-24 Andrew Lunn <andrew.lunn@ascom.ch>
* include/codes.h (ENOTEMPTY): Needed by the sysctl call in the
#ifdef ENOERR
case ENOERR:
- s = "No error";
+ s = (char *)"No error";
break;
#endif
#ifdef EPERM
case EPERM:
- s = "Not permitted";
+ s = (char *)"Not permitted";
break;
#endif
#ifdef ENOENT
case ENOENT:
- s = "No such entity";
+ s = (char *)"No such entity";
break;
#endif
#ifdef ESRCH
case ESRCH:
- s = "No such process";
+ s = (char *)"No such process";
break;
#endif
#ifdef EINTR
case EINTR:
- s = "Operation interrupted";
+ s = (char *)"Operation interrupted";
break;
#endif
#ifdef EIO
case EIO:
- s = "I/O error";
+ s = (char *)"I/O error";
break;
#endif
#ifdef EBADF
case EBADF:
- s = "Bad file handle";
+ s = (char *)"Bad file handle";
break;
#endif
#ifdef EAGAIN
case EAGAIN:
- s = "Try again later";
+ s = (char *)"Try again later";
break;
#endif
#ifdef ENOMEM
case ENOMEM:
- s = "Out of memory";
+ s = (char *)"Out of memory";
break;
#endif
#ifdef EBUSY
case EBUSY:
- s = "Resource busy";
+ s = (char *)"Resource busy";
break;
#endif
#ifdef ENODEV
case ENODEV:
- s = "No such device";
+ s = (char *)"No such device";
break;
#endif
#ifdef ENOTDIR
case ENOTDIR:
- s = "Not a directory";
+ s = (char *)"Not a directory";
break;
#endif
#ifdef EISDIR
case EISDIR:
- s = "Is a directory";
+ s = (char *)"Is a directory";
break;
#endif
#ifdef EINVAL
case EINVAL:
- s = "Invalid argument";
+ s = (char *)"Invalid argument";
break;
#endif
#ifdef ENFILE
case ENFILE:
- s = "Too many open files in system";
+ s = (char *)"Too many open files in system";
break;
#endif
#ifdef EMFILE
case EMFILE:
- s = "Too many open files";
+ s = (char *)"Too many open files";
break;
#endif
#ifdef EFBIG
case EFBIG:
- s = "File too large";
+ s = (char *)"File too large";
break;
#endif
#ifdef ENOSPC
case ENOSPC:
- s = "No space left on device";
+ s = (char *)"No space left on device";
break;
#endif
#ifdef ESPIPE
case ESPIPE:
- s = "Illegal seek";
+ s = (char *)"Illegal seek";
break;
#endif
#ifdef EROFS
case EROFS:
- s = "Read-only file system";
+ s = (char *)"Read-only file system";
break;
#endif
#ifdef EDOM
case EDOM:
- s = "Argument to math function outside valid domain";
+ s = (char *)"Argument to math function outside valid domain";
break;
#endif
#ifdef ERANGE
case ERANGE:
- s = "Math result cannot be represented";
+ s = (char *)"Math result cannot be represented";
break;
#endif
#ifdef EDEADLK
case EDEADLK:
- s = "Resource deadlock would occur";
+ s = (char *)"Resource deadlock would occur";
break;
#endif
#ifdef ENOSYS
case ENOSYS:
- s = "Function not implemented";
+ s = (char *)"Function not implemented";
break;
#endif
#ifdef ENAMETOOLONG
case ENAMETOOLONG:
- s = "File name too long";
+ s = (char *)"File name too long";
break;
#endif
#ifdef ENOTSUP
case ENOTSUP:
- s = "Not supported";
+ s = (char *)"Not supported";
break;
#endif
#ifdef EEOF
case EEOF:
- s = "End of file reached";
+ s = (char *)"End of file reached";
break;
#endif
#ifdef ENOSUPP
case ENOSUPP:
- s = "Operation not supported";
+ s = (char *)"Operation not supported";
break;
#endif
#ifdef EDEVNOSUPP
case EDEVNOSUPP:
- s = "Device does not support this operation";
+ s = (char *)"Device does not support this operation";
break;
#endif
#ifdef EXDEV
case EXDEV:
- s = "Improper link";
+ s = (char *)"Improper link";
break;
#endif
// Additional errors used by networking
#ifdef ENXIO
case ENXIO:
- s = "Device not configured";
+ s = (char *)"Device not configured";
break;
#endif
#ifdef EACCES
case EACCES:
- s = "Permission denied";
+ s = (char *)"Permission denied";
break;
#endif
#ifdef EEXIST
case EEXIST:
- s = "File exists";
+ s = (char *)"File exists";
break;
#endif
#ifdef ENOTTY
case ENOTTY:
- s = "Inappropriate ioctl for device";
+ s = (char *)"Inappropriate ioctl for device";
break;
#endif
#ifdef EPIPE
case EPIPE:
- s = "Broken pipe";
+ s = (char *)"Broken pipe";
break;
#endif
#ifdef EINPROGRESS
case EINPROGRESS:
- s = "Operation now in progress";
+ s = (char *)"Operation now in progress";
break;
#endif
#ifdef EALREADY
case EALREADY:
- s = "Operation already in progress";
+ s = (char *)"Operation already in progress";
break;
#endif
#ifdef ENOTSOCK
case ENOTSOCK:
- s = "Socket operation on non-socket";
+ s = (char *)"Socket operation on non-socket";
break;
#endif
#ifdef EDESTADDRREQ
case EDESTADDRREQ:
- s = "Destination address required";
+ s = (char *)"Destination address required";
break;
#endif
#ifdef EMSGSIZE
case EMSGSIZE:
- s = "Message too long";
+ s = (char *)"Message too long";
break;
#endif
#ifdef EPROTOTYPE
case EPROTOTYPE:
- s = "Protocol wrong type for socket";
+ s = (char *)"Protocol wrong type for socket";
break;
#endif
#ifdef ENOPROTOOPT
case ENOPROTOOPT:
- s = "Protocol not available";
+ s = (char *)"Protocol not available";
break;
#endif
#ifdef EPROTONOSUPPORT
case EPROTONOSUPPORT:
- s = "Protocol not supported";
+ s = (char *)"Protocol not supported";
break;
#endif
#ifdef ESOCKTNOSUPPORT
case ESOCKTNOSUPPORT:
- s = "Socket type not supported";
+ s = (char *)"Socket type not supported";
break;
#endif
#ifdef EOPNOTSUPP
case EOPNOTSUPP:
- s = "Operation not supported";
+ s = (char *)"Operation not supported";
break;
#endif
#ifdef EPFNOSUPPORT
case EPFNOSUPPORT:
- s = "Protocol family not supported";
+ s = (char *)"Protocol family not supported";
break;
#endif
#ifdef EAFNOSUPPORT
case EAFNOSUPPORT:
- s = "Address family not supported by protocol family";
+ s = (char *)"Address family not supported by protocol family";
break;
#endif
#ifdef EADDRINUSE
case EADDRINUSE:
- s = "Address already in use";
+ s = (char *)"Address already in use";
break;
#endif
#ifdef EADDRNOTAVAIL
case EADDRNOTAVAIL:
- s = "Can't assign requested address";
+ s = (char *)"Can't assign requested address";
break;
#endif
#ifdef ENETDOWN
case ENETDOWN:
- s = "Network is down";
+ s = (char *)"Network is down";
break;
#endif
#ifdef ENETUNREACH
case ENETUNREACH:
- s = "Network is unreachable";
+ s = (char *)"Network is unreachable";
break;
#endif
#ifdef ENETRESET
case ENETRESET:
- s = "Network dropped connection on reset";
+ s = (char *)"Network dropped connection on reset";
break;
#endif
#ifdef ECONNABORTED
case ECONNABORTED:
- s = "Software caused connection abort";
+ s = (char *)"Software caused connection abort";
break;
#endif
#ifdef ECONNRESET
case ECONNRESET:
- s = "Connection reset by peer";
+ s = (char *)"Connection reset by peer";
break;
#endif
#ifdef ENOBUFS
case ENOBUFS:
- s = "No buffer space available";
+ s = (char *)"No buffer space available";
break;
#endif
#ifdef EISCONN
case EISCONN:
- s = "Socket is already connected";
+ s = (char *)"Socket is already connected";
break;
#endif
#ifdef ENOTCONN
case ENOTCONN:
- s = "Socket is not connected";
+ s = (char *)"Socket is not connected";
break;
#endif
#ifdef ESHUTDOWN
case ESHUTDOWN:
- s = "Can't send after socket shutdown";
+ s = (char *)"Can't send after socket shutdown";
break;
#endif
#ifdef ETOOMANYREFS
case ETOOMANYREFS:
- s = "Too many references: can't splice";
+ s = (char *)"Too many references: can't splice";
break;
#endif
#ifdef ETIMEDOUT
case ETIMEDOUT:
- s = "Operation timed out";
+ s = (char *)"Operation timed out";
break;
#endif
#ifdef ECONNREFUSED
case ECONNREFUSED:
- s = "Connection refused";
+ s = (char *)"Connection refused";
break;
#endif
#ifdef EHOSTDOWN
case EHOSTDOWN:
- s = "Host is down";
+ s = (char *)"Host is down";
break;
#endif
#ifdef EHOSTUNREACH
case EHOSTUNREACH:
- s = "No route to host";
+ s = (char *)"No route to host";
break;
#endif
default:
- s = "Unknown error";
+ s = (char *)"Unknown error";
break;
} // switch
+2008-05-13 Savin Zlobec <savinz@users.sourceforge.net>
+
+ * src/fatfs.c: Fix handling of '.' and '..' nodes in dirsearch.
+
+2008-04-02 Xinghua Yang <yxinghua@sunnorth.com.cn>
+ Andrew Lunn <andrew.lunn@ascom.ch>
+ Taiyun Wang <taiyun@sunnorth.com.cn>
+
+ * cdl/fatfs.cdl: Use CYGPKG_FS_FAT_RET_DIRENT_DTYPE to control
+ whether fatfs sets file type in fatfs_fo_dirread.
+ * src/fatfs.c: Set file type in fatfs_fo_dirread
+ * test/fatfs1.c: Test the new d_type in dirent when present.
+
+2007-07-31 Hajime Ishitani <pigmon@mail.snd.co.jp>
+
+ * src/fatfs.c: When removing a directory, first remove . and
+ .. nodes.
+
+2007-02-05 Ya-Chau Yang <a8850607@stmail.fju.edu.tw>
+ Savin Zlobec <savinz@users.sourceforge.net>
+
+ * src/fatfs_supp.c: Fixed FAT32 cluster handling in
+ fatfs_delete_file and fatfs_rename_file.
+
+2007-01-27 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * tests/fatfs1.c: Fixed the format string to diag_printf()
+ to remove compiler warnings.
+
+2006-08-04 Paul Fine <pfine@dtccom.com>
+ Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/fats.c: Added functionality to the fatfs_getinfo() function
+ to return disk usage information about the filesystem, making this
+ information accessible through the cyg_fs_getinfo() interface.
+ * tests/fatfs1.c: Added code to test the disk usage.
+
2005-07-30 Andrew Lunn <andrew.lunn@ascom.ch>
* src/fatfs_supp.c: Correct types to remove compiler warnings.
description "This option controls if the FAT filesystem supports
or honors the FAT filesystem file attributes."
}
+
+ cdl_option CYGPKG_FS_FAT_RET_DIRENT_DTYPE {
+ display "Support for fileio's struct dirent d_type field"
+ flavor bool
+ default_value 0
+ active_if CYGPKG_FILEIO_DIRENT_DTYPE
+ description "This option controls whether the FAT filesystem
+ supports setting fileio's struct dirent d_type field.
+ If this option is enabled, d_type will be set."
+ }
+
# --------------------------------------------------------------------
CYG_TRACE1(TFS, "searching for dir entry '%s'", ds->name);
- // First check the cache
+ // Check for '.'
+
+ if (!strncmp(".", ds->name, ds->namelen))
+ {
+ ds->node = ds->dir;
+ return ENOERR;
+ }
+
+ // Check the cache
ds->node = fatfs_node_find(ds->disk,
ds->name,
return (err == EEOF ? ENOERR : err);
// Compare filenames
-
+
if ('\0' == dentry.filename[ds->namelen] &&
0 == strncasecmp(dentry.filename, ds->name, ds->namelen))
{
// Dir entry found - allocate new node and return
CYG_TRACE0(TFS, "dir entry found");
+
+ if (0 == strncmp(ds->name, "..", ds->namelen))
+ {
+ fatfs_dir_entry_t _dentry;
+ fatfs_data_pos_t _pos;
+
+ if (0 == dentry.cluster)
+ {
+ ds->node = ds->disk->root;
+ return ENOERR;
+ }
+
+ fatfs_initpos(ds->disk, &dentry, &_pos);
+ while (true)
+ {
+ err = fatfs_read_dir_entry(ds->disk, &dentry, &_pos, &_dentry);
+ if (err != ENOERR)
+ return err;
+ if (0 == strcmp(".", _dentry.filename))
+ break;
+ }
+
+ ds->node = fatfs_node_find(ds->disk,
+ _dentry.filename,
+ strlen(_dentry.filename),
+ _dentry.parent_cluster);
+
+ if (NULL != ds->node)
+ fatfs_node_touch(ds->disk, ds->node);
+ else
+ ds->node = fatfs_node_alloc(ds->disk, &_dentry);
+
+ if (NULL == ds->node)
+ return EMFILE;
+
+ return ENOERR;
+ }
+ else
+ ds->node = fatfs_node_alloc(ds->disk, &dentry);
- ds->node = fatfs_node_alloc(ds->disk, &dentry);
if (NULL == ds->node)
return EMFILE;
fatfs_disk_t *disk = (fatfs_disk_t *) mte->data;
fatfs_dirsearch_t ds;
int err;
+ fatfs_node_t *node;
CYG_TRACE3(TFS, "rmdir mte=%p dir=%p name='%s'", mte, dir, name);
err = fatfs_delete_file(disk, &ds.node->dentry);
if (err == ENOERR)
+ {
+ node = fatfs_node_find( disk, ".", 1, ds.node->dentry.cluster );
+ if (node != NULL)
+ fatfs_node_free(disk, node);
+
+ node = fatfs_node_find( disk, "..", 2, ds.node->dentry.cluster );
+ if (node != NULL)
+ fatfs_node_free(disk, node);
+
fatfs_node_free(disk, ds.node);
-
+ }
return err;
}
err = fatfs_get_attrib(mte, dir, name, (cyg_fs_attrib_t*)buf);
break;
#endif // CYGCFG_FS_FAT_USE_ATTRIBUTES
+#if defined(CYGSEM_FILEIO_BLOCK_USAGE)
+ case FS_INFO_BLOCK_USAGE: {
+ cyg_uint32 total_clusters;
+ cyg_uint32 free_clusters;
+ struct cyg_fs_block_usage *usage = (struct cyg_fs_block_usage *) buf;
+ fatfs_disk_t *disk = (fatfs_disk_t *) mte->data;
+
+ err = fatfs_get_disk_usage(disk, &total_clusters, &free_clusters);
+ if (err)
+ return err;
+ usage->total_blocks = total_clusters;
+ usage->free_blocks = free_clusters;
+ usage->block_size = disk->cluster_size;
+ break;
+ }
+#endif
default:
err = EINVAL;
break;
return (err == EEOF ? ENOERR : err);
strcpy(nbuf, dentry.filename);
-
+#ifdef CYGPKG_FS_FAT_RET_DIRENT_DTYPE
+ ent->d_type = dentry.mode;
+#endif
fd->node->dentry.atime = cyg_timestamp();
uio->uio_resid -= sizeof(struct dirent);
fp->f_offset++;
diag_printf("FAT: FDE acc date: %u\n", dentry->acc_date);
diag_printf("FAT: FDE wrt time: %u\n", dentry->wrt_time);
diag_printf("FAT: FDE wrt date: %u\n", dentry->wrt_date);
- diag_printf("FAT: FDE cluster: %u\n", dentry->cluster);
+ diag_printf("FAT: FDE cluster: %u\n", (dentry->cluster_HI << 16) | dentry->cluster);
diag_printf("FAT: FDE size: %u\n", dentry->size);
}
#endif // TDE
}
// Free file clusters
- free_cluster_chain(disk, raw_dentry.cluster);
+ free_cluster_chain(disk, raw_dentry.cluster | (raw_dentry.cluster_HI << 16));
raw_dentry_set_deleted(disk, &raw_dentry);
err = write_raw_dentry(disk, &file->disk_pos, &raw_dentry);
return err;
CYG_TRACE0(TDE, "different dirs");
- // Moveing around in different dirs
+ // Moving around in different dirs
fatfs_initpos(disk, dir2, &new_pos);
- CYG_TRACE0(TDE, "writting to new dir");
+ CYG_TRACE0(TDE, "writing to new dir");
// Get free dir entry in target dir
CYG_TRACE0(TDE, "deleting from old dir");
- // Deleate dentry at old location
+ // Delete dentry at old location
raw_dentry_set_deleted(disk, &raw_dentry);
raw_dentry.size = 0;
raw_dentry.cluster = 0;
+ raw_dentry.cluster_HI = 0;
err = write_raw_dentry(disk, &target->disk_pos, &raw_dentry);
if (err != ENOERR)
return err;
if (0 == strncmp("..", raw_cdentry.name, 2))
{
- raw_cdentry.cluster = dir2->cluster;
+ raw_cdentry.cluster = dir2->cluster & 0xFFFF;
+ raw_cdentry.cluster_HI = dir2->cluster >> 16;
err = write_raw_dentry(disk, &pos, &raw_cdentry);
if (err != ENOERR)
return err;
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 2003 Savin Zlobec
+// Copyright (C) 2003 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
break;
num++;
diag_printf("<INFO>: entry %14s",entry->d_name);
+#ifdef CYGPKG_FS_FAT_RET_DIRENT_DTYPE
+ diag_printf(" d_type %2x", entry->d_type);
+#endif
if( statp )
{
char fullname[PATH_MAX];
diag_printf(" [mode %08x ino %08x nlink %d size %ld]",
sbuf.st_mode,sbuf.st_ino,sbuf.st_nlink,(long)sbuf.st_size);
}
+#ifdef CYGPKG_FS_FAT_RET_DIRENT_DTYPE
+ if ((entry->d_type & S_IFMT) != (sbuf.st_mode & S_IFMT))
+ CYG_TEST_FAIL("File mode's don't match between dirent and stat");
+#endif
}
diag_printf("\n");
int i;
int err;
- diag_printf("<INFO>: create file %s size %d\n",name,size);
+ diag_printf("<INFO>: create file %s size %zd \n",name,size);
err = access( name, F_OK );
if( err < 0 && errno != EACCES ) SHOW_RESULT( access, err );
if( (size-prevsize) > 100000 )
{
- diag_printf("<INFO>: size = %d \n", size);
+ diag_printf("<INFO>: size = %zd \n", size);
prevsize = size;
}
} while( wrote == IOSIZE );
- diag_printf("<INFO>: file size == %d\n",size);
+ diag_printf("<INFO>: file size == %zd\n",size);
err = close( fd );
if( err < 0 ) SHOW_RESULT( close, err );
{
int err;
int existingdirents=-1;
+#if defined(CYGSEM_FILEIO_BLOCK_USAGE)
+ struct cyg_fs_block_usage usage;
+#endif
CYG_TEST_INIT();
listdir( "/", true, -1, &existingdirents );
// --------------------------------------------------------------
+#if defined(CYGSEM_FILEIO_BLOCK_USAGE)
+ err = cyg_fs_getinfo("/", FS_INFO_BLOCK_USAGE, &usage, sizeof(usage));
+ if( err < 0 ) SHOW_RESULT( cyg_fs_getinfo, err );
+ diag_printf("<INFO>: total size: %6lld blocks, %10lld bytes\n",
+ usage.total_blocks, usage.total_blocks * usage.block_size);
+ diag_printf("<INFO>: free size: %6lld blocks, %10lld bytes\n",
+ usage.free_blocks, usage.free_blocks * usage.block_size);
+ diag_printf("<INFO>: block size: %6u bytes\n", usage.block_size);
+#endif
+ // --------------------------------------------------------------
createfile( "/foo", 20257 );
checkfile( "foo" );
checkfile( "/bar/bundy" );
comparefiles("/fee", "bundy" );
+#if defined(CYGSEM_FILEIO_BLOCK_USAGE)
+ err = cyg_fs_getinfo("/", FS_INFO_BLOCK_USAGE, &usage, sizeof(usage));
+ if( err < 0 ) SHOW_RESULT( cyg_fs_getinfo, err );
+ diag_printf("<INFO>: total size: %6lld blocks, %10lld bytes\n",
+ usage.total_blocks, usage.total_blocks * usage.block_size);
+ diag_printf("<INFO>: free size: %6lld blocks, %10lld bytes\n",
+ usage.free_blocks, usage.free_blocks * usage.block_size);
+ diag_printf("<INFO>: block size: %6u bytes\n", usage.block_size);
+#endif
// --------------------------------------------------------------
diag_printf("<INFO>: unlink fee\n");
+2008-04-02 Xinghua Yang <yxinghua@sunnorth.com.cn>
+ Taiyun Wang <taiyun@sunnorth.com.cn>
+ Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * cdl/jffs2.cdl: Use CYGPKG_FS_JFFS2_RET_DIRENT_DTYPE to control
+ whether jffs2 sets file type in jffs2_fo_dirread.
+ * src/fs-ecos.c: Set file type in jffs2_fo_dirread.
+ * tests/jffs2_1.c: Test the new d_type in dirent when present.
+
+2006-03-09 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/fs-ecos.c: Generalise the check for broken ARM compilers
+ and add the MIPS compiler as also being broken.
+
2005-08-03 Andrew Lunn <andrew.lunn@ascom.ch>
* tests/jffs2_1.c: Include <stdio.h> to stop compiler warning.
the set of global flags if present."
}
+ cdl_option CYGPKG_FS_JFFS2_RET_DIRENT_DTYPE {
+ display "Support for fileio's struct dirent d_type field"
+ flavor bool
+ default_value 0
+ active_if CYGPKG_FILEIO_DIRENT_DTYPE
+ description "
+ This option controls whether the JFFS2 filesystem supports
+ setting fileio's struct dirent d_type field.
+ If this option is enabled, d_type will be set. Otherwise,
+ nothing will be done, d_type's value will be zero because
+ fileio already sets it."
+ }
+
# ----------------------------------------------------------------
# Tests
#include <string.h>
#include <cyg/io/config_keys.h>
-#if (__GNUC__ == 3) && (__GNUC_MINOR__ == 2) && defined (__ARM_ARCH_4__)
+#if (__GNUC__ == 3) && (__GNUC_MINOR__ == 2) && \
+ (defined (__arm__) || defined (_mips))
#error This compiler is known to be broken. Please see:
-#error http://ecos.sourceware.org/ml/ecos-patches/2003-08/msg00006.html
+#error "http://ecos.sourceware.org/ml/ecos-patches/2003-08/msg00006.html"
#endif
//==========================================================================
struct _inode *d_inode = (struct _inode *) fp->f_data;
struct dirent *ent = (struct dirent *) uio->uio_iov[0].iov_base;
char *nbuf = ent->d_name;
+#ifdef CYGPKG_FS_JFFS2_RET_DIRENT_DTYPE
+ struct _inode *c_ino;
+#endif
int nlen = sizeof (ent->d_name) - 1;
off_t len = uio->uio_iov[0].iov_len;
struct jffs2_inode_info *f;
D1(printk
(KERN_DEBUG "Dirent 0: \".\", ino #%lu\n", inode->i_ino));
filldir(nbuf, nlen, (const unsigned char *) ".", 1);
- goto out;
+#ifdef CYGPKG_FS_JFFS2_RET_DIRENT_DTYPE
+ // Flags here are the same as jffs2_mkdir. Make sure
+ // d_type is the same as st_mode of calling stat.
+ ent->d_type =
+ jemode_to_cpu(cpu_to_jemode(S_IRUGO|S_IXUGO|S_IWUSR|S_IFDIR));
+#endif
+ goto out;
}
if (offset == 1) {
filldir(nbuf, nlen, (const unsigned char *) "..", 2);
- goto out;
+#ifdef CYGPKG_FS_JFFS2_RET_DIRENT_DTYPE
+ // Flags here are the same as jffs2_mkdir. Make sure
+ // d_type is the same as st_mode of calling stat.
+ ent->d_type =
+ jemode_to_cpu(cpu_to_jemode(S_IRUGO|S_IXUGO|S_IWUSR|S_IFDIR));
+#endif
+ goto out;
}
curofs = 1;
(KERN_DEBUG "Dirent %ld: \"%s\", ino #%u, type %d\n", offset,
fd->name, fd->ino, fd->type));
filldir(nbuf, nlen, fd->name, strlen((char *)fd->name));
+#ifdef CYGPKG_FS_JFFS2_RET_DIRENT_DTYPE
+ c_ino = jffs2_iget(inode->i_sb, fd->ino);
+ if(IS_ERR(c_ino)) {
+ D1(printk(KERN_WARNING "get entry inode failed\n"));
+ // fileio already set it to zero, so not needed here
+ // ent->d_type = 0;
+ }
+ else {
+ ent->d_type = c_ino->i_mode;
+ jffs2_iput(c_ino);
+ }
+#endif
goto out_sem;
}
/* Reached the end of the directory */
break;
num++;
diag_printf("<INFO>: entry %14s",entry->d_name);
+#ifdef CYGPKG_FS_JFFS2_RET_DIRENT_DTYPE
+ diag_printf(" d_type %2d", entry->d_type);
+#endif
if( statp )
{
char fullname[PATH_MAX];
sbuf.st_mode,sbuf.st_ino,sbuf.st_nlink,
(unsigned long) sbuf.st_size);
}
+#ifdef CYGPKG_FS_JFFS2_RET_DIRENT_DTYPE
+ if ((entry->d_type & S_IFMT) != (sbuf.st_mode & S_IFMT))
+ CYG_TEST_FAIL("File mode's don't match between dirent and stat");
+#endif
}
diag_printf("\n");
+2008-04-02 Xinghua Yang <yxinghua@sunnorth.com.cn>
+ Taiyun Wang <taiyun@sunnorth.com.cn>
+
+ * cdl/ramfs.cdl: Use CYGPKG_FS_RAM_RET_DIRENT_DTYPE to control
+ whether ram sets file type in ramfs_fo_dirread.
+ * src/ramfs.c: Set file type in ramfs_fo_dirread.
+ * tests/ramfs1.c: Test the new d_type in dirent when present.
+
+2006-10-05 Andrew Lunn <andrew.lunn@ascom.ch
+ Paluch Sebastian <the_sorcerer&op.pl>
+
+ * test/ramfs3 (new): Test for lseek bug found in fileio.
+ * cdl/ramfs.cdl: Build new test.
+
+2006-06-25 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/ramfs.c (find_direntry): Don't search off the end of the
+ directory node into hyperspace.
+ * src/ramfs.c (ramfs_getinfo): Support for block usage call.
+ * tests/ramfs1.c (main): Add file system block usage test.
+
+2006-05-17 Andy Jackson <andy@grapevinetech.co.uk>
+
+ * tests/ramfs1.c (createfile): Fix compile warnings.
+
+2005-10-01 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/ramfs.c: Implement holes in files when using BLOCK
+ allocation method. This requires allowing lseek to go past the end
+ of the file.
+
+ * test/ramfs2.c: Extended the lseek test to now seek past the end
+ of the file. With the BLOCK allocation method this will create a
+ whole. With the SIMPLE allocation method is just allocates the
+ memory and fills it with zero.
+
+ * cdl/ramfs.cdl: Added in interface which both SIMPLE and BLOCK
+ implement. This allows the inference engine to work out is should
+ enable BLOCK if SIMPLE is disabled by the user.
+
+2005-10-01 Dan Jakubiec <dan.jakubiec@systech.com>
+
+ * src/ramfs.c: (ramfs_mount, ramfs_open, ramfs_mkdir) Changed the
+ permissions for files and directories created on RAMFS file systems
+ from 000 to 777. This helps ported applications which wrongly
+ assume there is some security concept and check for the existence
+ of certain file permissions.
+
2005-03-27 Andrew Lunn <andrew.lunn@ascom.ch>
* tests/ramfs1.c (SHOW_RESULT): Fixed compiler warning about format
implements CYGINT_IO_FILEIO_FS
compile -library=libextras.a ramfs.c
+
+ requires CYGINT_FS_RAM_ALLOC == 1
+
+ cdl_interface CYGINT_FS_RAM_ALLOC {
+ display "Functions to allocate RAM"
+ description "
+ This interface is implemented by functions
+ which allocate RAM to hold the contents of the files"
+ }
+
+
# ----------------------------------------------------------------------
# Simple allocation mechanism using malloc()
default_value 1
active_if !CYGPKG_FS_RAM_BLOCKS
+ implements CYGINT_FS_RAM_ALLOC
cdl_option CYGNUM_RAMFS_REALLOC_INCREMENT {
display "Size of file data storage increment"
flavor data
default_value 0
active_if !CYGPKG_FS_RAM_SIMPLE
-
+ implements CYGINT_FS_RAM_ALLOC
cdl_option CYGNUM_RAMFS_BLOCK_SIZE {
display "Size of file data storage block"
flavor data
blocks that are referenced from a file or directory node."
}
+ cdl_option CYGPKG_FS_RAM_RET_DIRENT_DTYPE {
+ display "Support for fileio's struct dirent d_type field"
+ flavor bool
+ default_value 0
+ active_if CYGPKG_FILEIO_DIRENT_DTYPE
+ description "This option controls whether the RAM filesystem supports
+ setting fileio's struct dirent d_type field.
+ If this option is enabled, d_type will be set.
+ Otherwise, nothing will be done, d_type's value will
+ be zero because fileio already sets it."
+ }
+
# ----------------------------------------------------------------
# Tests
display "RAM FS tests"
flavor data
no_define
- calculated { "tests/ramfs1 tests/ramfs2" }
+ calculated { "tests/ramfs1 tests/ramfs2 tests/ramfs3" }
description "
This option specifies the set of tests for the RAM FS package."
}
size_t *size, // returned buffer size
cyg_bool alloc) // extend allocation?
{
- if( alloc && (pos == node->datasize || node->datasize == 0) )
+ if( alloc && (pos >= node->datasize || node->datasize == 0) )
{
// If we are allowed to alloc new data, and we are at the end of the
// current data allocation, or there is no data present, allocate or
newdata = realloc( node->data, pos+CYGNUM_RAMFS_REALLOC_INCREMENT );
if( newdata == NULL ) return ENOSPC;
- else memset( newdata+pos, 0, CYGNUM_RAMFS_REALLOC_INCREMENT );
+ else memset( newdata + node->datasize, 0,
+ pos + CYGNUM_RAMFS_REALLOC_INCREMENT - node->datasize );
node->data = newdata;
node->datasize = pos+CYGNUM_RAMFS_REALLOC_INCREMENT;
ramfs_block *b;
*buffer = NULL;
- *size = 0;
+ *size = CYGNUM_RAMFS_BLOCK_SIZE - bpos;
if( bi >= nblocks )
return ENOERR;
if( b == NULL )
{
// There is no block there. If _alloc_ is true we can fill the
- // slot in with a new block. If it is false, we indicate end of
- // data with a zero size result.
+ // slot in with a new block. If it is false, we indicate there
+ // is no block and size indicates where the block would end if
+ // it existed.
if( alloc )
{
b = block_alloc();
}
*buffer = &((*b)[bpos]);
- *size = CYGNUM_RAMFS_BLOCK_SIZE - bpos;
return ENOERR;
}
ramfs_dirent *d;
cyg_uint8 *buf;
size_t size;
-
+
// look for a first name fragment
for(;;)
{
- err = findbuffer_node( dir, pos, &buf, &size, false );
+ err = findbuffer_node( dir, pos, &buf, &size, false );
if( err != ENOERR || size == 0)
return NULL;
if( size < sizeof(ramfs_dirent) || !d->inuse || !d->first )
{
pos += sizeof(ramfs_dirent);
- continue;
+ if ( pos < dir->size )
+ continue;
+ // End if directory, didn't find it.
+ return NULL;
}
break;
fraglen = d->fraglen;
// compare strings, if different, look for another
- if( memcmp( frag, d->name, fraglen ) != 0 )
- break;
-
+ if( memcmp( frag, d->name, fraglen ) != 0 ) {
+ break;
+ }
frag += fraglen;
// If we are at the last fragment, then the whole name string
// has matched and we have a successful search.
- if( d->last )
- return first;
-
+ if( d->last )
+ return first;
+
// Otherwise move on to next entry in chain
err = findbuffer_node( dir, d->next, &buf, &size, false );
if( err != ENOERR )
// Allocate a node to be the root of this filesystem and initialize it.
- root = alloc_node(__stat_mode_DIR);
+ root = alloc_node(__stat_mode_DIR|S_IRWXU|S_IRWXG|S_IRWXO);
if( root == NULL )
return ENOSPC;
// create a new one. The dir and name fields of the dirsearch
// object will have been updated so we know where to put it.
- node = alloc_node( __stat_mode_REG );
+ node = alloc_node( __stat_mode_REG|S_IRWXU|S_IRWXG|S_IRWXO);
if( node == NULL )
return ENOSPC;
// the pathname, so we can create it here.
int doterr, dotdoterr, direrr;
- node = alloc_node( __stat_mode_DIR );
+ node = alloc_node( __stat_mode_DIR | S_IRWXU|S_IRWXG|S_IRWXO);
if( node == NULL )
return ENOSPC;
// -------------------------------------------------------------------------
// ramfs_getinfo()
-// Getinfo. Currently only support pathconf().
+// Getinfo. Currently only support pathconf() and filesystem usage.
static int ramfs_getinfo ( cyg_mtab_entry *mte, cyg_dir dir, const char *name,
int key, void *buf, int len )
case FS_INFO_CONF:
err = ramfs_pathconf( ds.node, (struct cyg_pathconf_info *)buf );
break;
-
+#if defined(CYGSEM_FILEIO_BLOCK_USAGE) && defined(CYGPKG_FS_RAM_BLOCKS_ARRAY)
+ // When using malloc for storage this does not make much
+ // sense, so only implement this when using pre-allocated
+ // blocks
+ case FS_INFO_BLOCK_USAGE: {
+ struct cyg_fs_block_usage *usage = (struct cyg_fs_block_usage *) buf;
+ ramfs_block *b;
+
+ usage->total_blocks = CYGNUM_FS_RAM_BLOCKS_ARRAY_SIZE;
+ usage->free_blocks = 0;
+ // Iterate over the free list to count its size
+ b = block_free_list;
+ while(b) {
+ usage->free_blocks++;
+ b=*(ramfs_block **)b;
+ }
+ usage->block_size = CYGNUM_RAMFS_BLOCK_SIZE;
+ return ENOERR;
+ }
+#endif
default:
err = EINVAL;
}
// at present.
if( l > bsize )
l = bsize;
-
- // copy data out
- memcpy( buf, fbuf, l );
-
+
+ if (fbuf) {
+ // copy data out
+ memcpy( buf, fbuf, l );
+ } else { // hole, so return zeros here.
+ memset( buf, 0, l );
+ }
+
// Update working vars
len -= l;
buf += l;
if( fp->f_flag & CYG_FAPPEND )
pos = fp->f_offset = node->size;
- // Check that pos is within current file size, or at the very end.
- if( pos < 0 || pos > node->size )
- return EINVAL;
-
// Now loop over the iovecs until they are all done, or
// we get an error.
for( i = 0; i < uio->uio_iovcnt; i++ )
return EINVAL;
}
- // Check that pos is still within current file size, or at the
- // very end.
- if( pos < 0 || pos > node->size )
- return EINVAL;
-
// All OK, set fp offset and return new position.
*apos = fp->f_offset = pos;
memcpy( nbuf, d->name, fraglen);
nbuf += fraglen;
nlen -= fraglen;
+#ifdef CYGPKG_FS_RAM_RET_DIRENT_DTYPE
+ ent->d_type = d->node->mode;
+#endif
// if we hit the last entry, we have a successful transfer
if( d->last || nlen == 0)
#include <pkgconf/hal.h>
#include <pkgconf/kernel.h>
#include <pkgconf/io_fileio.h>
+#include <pkgconf/fs_ram.h>
#include <cyg/kernel/ktypes.h> // base kernel types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <string.h>
#include <dirent.h>
+#include <stdio.h>
#include <cyg/fileio/fileio.h>
#include <cyg/infra/testcase.h>
break;
num++;
diag_printf("<INFO>: entry %14s",entry->d_name);
+#ifdef CYGPKG_FS_RAM_RET_DIRENT_DTYPE
+ diag_printf(" d_type %2x", entry->d_type);
+#endif
if( statp )
{
char fullname[PATH_MAX];
sbuf.st_mode,sbuf.st_ino,sbuf.st_nlink,
(unsigned long) sbuf.st_size);
}
+#ifdef CYGPKG_FS_RAM_RET_DIRENT_DTYPE
+ if ((entry->d_type & S_IFMT) != (sbuf.st_mode & S_IFMT))
+ CYG_TEST_FAIL("File mode's don't match between dirent and stat");
+#endif
}
diag_printf("\n");
int i;
int err;
- diag_printf("<INFO>: create file %s size %d\n",name,size);
+ diag_printf("<INFO>: create file %s size %zd\n",name,size);
err = access( name, F_OK );
if( err < 0 && errno != EACCES ) SHOW_RESULT( access, err );
{
int err;
int existingdirents=-1;
+#if defined(CYGSEM_FILEIO_BLOCK_USAGE) && defined(CYGPKG_FS_RAM_BLOCKS_ARRAY)
+ struct cyg_fs_block_usage usage;
+#endif
CYG_TEST_INIT();
listdir( "/", true, -1, &existingdirents );
if ( existingdirents < 2 )
CYG_TEST_FAIL("Not enough dir entries\n");
-
+ // --------------------------------------------------------------
+#if defined(CYGSEM_FILEIO_BLOCK_USAGE) && defined(CYGPKG_FS_RAM_BLOCKS_ARRAY)
+ err = cyg_fs_getinfo("/", FS_INFO_BLOCK_USAGE, &usage, sizeof(usage));
+ if( err < 0 ) SHOW_RESULT( cyg_fs_getinfo, err );
+ diag_printf("<INFO>: total size: %6lld blocks, %10lld bytes\n",
+ usage.total_blocks, usage.total_blocks * usage.block_size);
+ diag_printf("<INFO>: free size: %6lld blocks, %10lld bytes\n",
+ usage.free_blocks, usage.free_blocks * usage.block_size);
+ diag_printf("<INFO>: block size: %6u bytes\n", usage.block_size);
+#endif
// --------------------------------------------------------------
createfile( "/foo", 202 );
listdir( "..", true, existingdirents+3, NULL );
// --------------------------------------------------------------
+#if defined(CYGSEM_FILEIO_BLOCK_USAGE) && defined(CYGPKG_FS_RAM_BLOCKS_ARRAY)
+ err = cyg_fs_getinfo("/", FS_INFO_BLOCK_USAGE, &usage, sizeof(usage));
+ if( err < 0 ) SHOW_RESULT( cyg_fs_getinfo, err );
+ diag_printf("<INFO>: total size: %6lld blocks, %10lld bytes\n",
+ usage.total_blocks, usage.total_blocks * usage.block_size);
+ diag_printf("<INFO>: free size: %6lld blocks, %10lld bytes\n",
+ usage.free_blocks, usage.free_blocks * usage.block_size);
+ diag_printf("<INFO>: block size: %6u bytes\n", usage.block_size);
+#endif
+ // --------------------------------------------------------------
diag_printf("<INFO>: unlink tinky\n");
err = unlink( "tinky" );
err = fclose(stream);
if (err != 0) SHOW_RESULT( fclose, err );
+ CYG_TEST_INFO("open file /fseek");
+ stream = fopen("/fseek", "r+");
+ if (!stream) {
+ diag_printf("<FAIL>: fopen() returned NULL, %s\n", strerror(errno));
+ }
+
+ CYG_TEST_INFO("fseek()ing past the end to create a hole");
+ /* Seek 1K after the end of the file */
+ err = fseek(stream, sizeof(buf), SEEK_END);
+ if ( err < 0 ) SHOW_RESULT( fseek, err );
+
+ pos = ftell(stream);
+
+ if (pos < 0) SHOW_RESULT( ftell, pos );
+ if (pos != (2*sizeof(buf))) CYG_TEST_FAIL("ftell is not telling the truth");
+
+ CYG_TEST_INFO("writing test pattern");
+ err=fwrite(buf,sizeof(buf), 1, stream);
+ if ( err < 0 ) SHOW_RESULT( fwrite, err );
+
+ pos = ftell(stream);
+
+ if (pos < 0) SHOW_RESULT( ftell, pos );
+ if (pos != (3*sizeof(buf))) CYG_TEST_FAIL("ftell is not telling the truth");
+
+ CYG_TEST_INFO("closing file");
+ err = fclose(stream);
+ if (err != 0) SHOW_RESULT( fclose, err );
+
+ CYG_TEST_INFO("open file /fseek");
+ stream = fopen("/fseek", "r+");
+ if (!stream) {
+ diag_printf("<FAIL>: fopen() returned NULL, %s\n", strerror(errno));
+ }
+
+ err = fread(buf1,sizeof(buf1),1, stream);
+ if (err != 1) SHOW_RESULT( fread, err );
+
+ CYG_TEST_INFO("Comparing contents");
+ if (memcmp(buf, buf1, sizeof(buf1))) {
+ CYG_TEST_FAIL("File contents inconsistent");
+ }
+
+ err = fread(buf1,sizeof(buf1),1, stream);
+ if (err != 1) SHOW_RESULT( fread, err );
+
+ for (i = 0; i< sizeof(buf); i++) {
+ if (buf1[i] != 0)
+ CYG_TEST_FAIL("Hole does not contain zeros");
+ }
+
+ err = fread(buf1,sizeof(buf1),1, stream);
+ if (err != 1) SHOW_RESULT( fread, err );
+
+ if (memcmp(buf, buf1, sizeof(buf1))) {
+ CYG_TEST_FAIL("File contents inconsistent");
+ }
+
+ CYG_TEST_INFO("closing file");
+
+ /* Close the file */
+ err = fclose(stream);
+ if (err != 0) SHOW_RESULT( fclose, err );
+
CYG_TEST_INFO("umount /");
err = umount( "/" );
if( err < 0 ) SHOW_RESULT( umount, err );
CYG_TEST_PASS_FINISH("ramfs2");
+
+
}
+2006-11-13 Xinghua Yang <yxinghua@sunnorth.com.cn>
+ Taiyun Wang <taiyun@sunnorth.com.cn>
+
+ * cdl/romfs.cdl: Use CYGPKG_FS_ROM_RET_DIRENT_DTYPE to control
+ whether fatfs sets file type in romfs_fo_dirread.
+ * src/romfs.c: Set file type in romfs_fo_dirread.
+ * tests/romfs1.c: Test the new d_type in dirent when present.
+
+2006-11-13 Oyvind Harboe <oyvind.harboe@zylin.com>
+
+ * support/file2c.tcl : align romdisk data to 4 bytes. With a bit
+ of bad luck, it would not be long-word aligned.
+
+2006-08-04 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/romfs.c (romfs_getinfo): Support for block usage call.
+ * tests/romfs1.c (main): Add file system block usage test.
+
+2006-02-15 Andrew Lunn <andrew.lunn@ascom.ch>
+ Peter Korsgaard <jacmet@sunsite.dk>
+
+ * support/mk_romfs.c: Use stdint.h defined types so the code is
+ 64 bit clean. Fix compiler warnings.
+
2005-07-08 Andrew Lunn <andrew.lunn@ascom.ch>
* cdl/romfs.cdl: Allow mk_romfs to be build even when the tests
used to create a rom filesystem image."
}
+ cdl_option CYGPKG_FS_ROM_RET_DIRENT_DTYPE {
+ display "Support for fileio's struct dirent d_type field"
+ flavor bool
+ default_value 0
+ active_if CYGPKG_FILEIO_DIRENT_DTYPE
+
+ description "
+ This option controls whether the ROM filesystem supports
+ setting fileio's struct dirent d_type field.
+ If this option is enabled, d_type will be set. Otherwise,
+ nothing will be done, d_type's value will be zero because
+ fileio already sets it."
+ }
+
# ----------------------------------------------------------------
# Tests
// -------------------------------------------------------------------------
// romfs_getinfo()
-// Getinfo. Currently only support pathconf().
+// Getinfo. Currently only support pathconf() and file system block usage
static int romfs_getinfo ( cyg_mtab_entry *mte, cyg_dir dir, const char *name,
int key, void *buf, int len )
case FS_INFO_CONF:
err = romfs_pathconf( ds.node, (struct cyg_pathconf_info *)buf );
break;
-
+#if defined(CYGSEM_FILEIO_BLOCK_USAGE)
+ case FS_INFO_BLOCK_USAGE: {
+ struct cyg_fs_block_usage *usage = (struct cyg_fs_block_usage *) buf;
+ struct romfs_disk *disk = (struct romfs_disk*) mte->data;
+ usage->total_blocks = disk->disksize;
+ usage->free_blocks = 0;
+ usage->block_size = 1;
+ return ENOERR;
+ }
+#endif
default:
err = EINVAL;
}
for ( i = 0 ; i < nlen && d->name[i] ; i++, nbuf++ )
*nbuf = d->name[i];
+#ifdef CYGPKG_FS_ROM_RET_DIRENT_DTYPE
+ ent->d_type = (((romfs_disk *)fp->f_mte->data)->node[d->node]).mode;
+#endif
// A successful read. Terminate the entry name with a NUL, set the
// residue and set the file offset to restart at the next
}
append result "/* This is a generated file. Do not edit. */\n\n"
-append result "static const unsigned char filedata\[\] = {\n"
+append result "static CYGBLD_ATTRIB_ALIGN(4) const unsigned char filedata\[\] = {\n"
set datalength [ string length $data ]
#include <fcntl.h>
#include <unistd.h>
#include <errno.h>
+#include <stdint.h>
//==========================================================================
//
//==========================================================================
// define LONG to be a four byte unsigned integer on the host
-#define LONG unsigned long
+#define LONG uint32_t
// define SHORT to be a two byte unsigned integer on the host
-#define SHORT unsigned short
+#define SHORT uint16_t
// All data files should be aligned to this sized boundary (minimum probably 32)
#define DATA_ALIGN 32
}
}
-static void outputlong( unsigned char *b, unsigned long w ) {
+static void outputlong( unsigned char *b, LONG w ) {
if ( bigendian ) {
b[0] = (w>>24) & 0xff;
b[1] = (w>>16) & 0xff;
}
}
-static void outputshort( unsigned char *b, unsigned short w ) {
+static void outputshort( unsigned char *b, SHORT w ) {
if ( bigendian ) {
b[0] = (w>> 8) & 0xff;
b[1] = (w ) & 0xff;
myrealloc( (void**)&parent_node->entry, (parent_node->size += this_size) );
g = (romfs_dirent *)((unsigned char *)parent_node->entry + start);
memset( (void*)g, '\0', this_size );
- outputlong( (char*)&g->node, node_num);
- outputlong( (char*)&g->next, parent_node->size);
+ outputlong( (unsigned char*)&g->node, node_num);
+ outputlong( (unsigned char*)&g->next, parent_node->size);
strcpy(g->name,name);
verb_printf( VERB_MAX, "\t%s --> node %d\n", name, node_num );
return (const char *)g->name;
static void WriteNode( int fd, node *np ) {
romfs_node anode;
char padhere[9];
- outputlong( (char*) &anode.mode, ConvertMode( np->st_mode ) );
- outputlong( (char*) &anode.nlink, np->nlink );
- outputshort((char*) &anode.uid, np->uid );
- outputshort((char*) &anode.gid, np->gid );
- outputlong( (char*) &anode.size, np->size );
- outputlong( (char*) &anode.ctime, np->ctime );
- outputlong( (char*) &anode.data_offset, np->offset );
+ outputlong( (unsigned char*) &anode.mode, ConvertMode( np->st_mode ) );
+ outputlong( (unsigned char*) &anode.nlink, np->nlink );
+ outputshort((unsigned char*) &anode.uid, np->uid );
+ outputshort((unsigned char*) &anode.gid, np->gid );
+ outputlong( (unsigned char*) &anode.size, np->size );
+ outputlong( (unsigned char*) &anode.ctime, np->ctime );
+ outputlong( (unsigned char*) &anode.data_offset, np->offset );
sprintf( padhere, "<%6d>", np->nodenum );
memcpy( anode.pad, padhere, 8 );
if ( dowrite && write( fd, (void*)&anode, sizeof(anode) ) != sizeof(anode) )
romfs_disk header;
int wnodes;
- outputlong( (char*) &header.magic, ROMFS_MAGIC );
- outputlong( (char*) &header.nodecount, nodes );
- outputlong( (char*) &header.disksize, coffset );
- outputlong( (char*) &header.dev_id, 0x01020304 );
+ outputlong( (unsigned char*) &header.magic, ROMFS_MAGIC );
+ outputlong( (unsigned char*) &header.nodecount, nodes );
+ outputlong( (unsigned char*) &header.disksize, coffset );
+ outputlong( (unsigned char*) &header.dev_id, 0x01020304 );
strcpy( header.name, "ROMFS v1.0" );
if ( dowrite && write( fd, (void*)&header, sizeof(header) ) != sizeof(header) )
fatal_error(EXIT_WRITE, "Error writing ROMFS header: %s\n", strerror(errno) );
#include <pkgconf/io_fileio.h>
#include <pkgconf/isoinfra.h>
#include <pkgconf/system.h>
+#include <pkgconf/fs_rom.h>
#include <unistd.h>
#include <fcntl.h>
//==========================================================================
#define SHOW_RESULT( _fn, _res ) \
-diag_printf("<FAIL>: " #_fn "() returned %d %s\n", _res, _res<0?strerror(errno):"");
+ diag_printf("<FAIL>: " #_fn "() returned %d %s\n", (int)_res, _res<0?strerror(errno):"");
#define CHKFAIL_TYPE( _fn, _res, _type ) { \
if ( _res != -1 ) \
- diag_printf("<FAIL>: " #_fn "() returned %d (expected -1)\n", _res); \
+ diag_printf("<FAIL>: " #_fn "() returned %d (expected -1)\n", (int)_res); \
else if ( errno != _type ) \
diag_printf("<FAIL>: " #_fn "() failed with errno %d (%s),\n expected %d (%s)\n", errno, strerror(errno), _type, strerror(_type) ); \
}
break;
diag_printf("<INFO>: entry %14s",entry->d_name);
+#ifdef CYGPKG_FS_ROM_RET_DIRENT_DTYPE
+ diag_printf(" d_type %2x", entry->d_type);
+#endif
if( statp )
{
char fullname[PATH_MAX];
}
else
{
- diag_printf(" [mode %08x ino %08x nlink %d size %d]",
+ diag_printf(" [mode %08x ino %08x nlink %d size %ld]",
sbuf.st_mode,sbuf.st_ino,sbuf.st_nlink,sbuf.st_size);
}
+#ifdef CYGPKG_FS_ROM_RET_DIRENT_DTYPE
+ if ((entry->d_type & S_IFMT) != (sbuf.st_mode & S_IFMT))
+ CYG_TEST_FAIL("File mode's don't match between dirent and stat");
+#endif
}
diag_printf("\n");
{
int err;
char address[16];
+#if defined(CYGSEM_FILEIO_BLOCK_USAGE)
+ struct cyg_fs_block_usage usage;
+#endif
CYG_TEST_INIT();
CHKFAIL_TYPE( umount, err, EINVAL );
#endif
+#if defined(CYGSEM_FILEIO_BLOCK_USAGE)
+ err = cyg_fs_getinfo("/", FS_INFO_BLOCK_USAGE, &usage, sizeof(usage));
+ if( err < 0 ) SHOW_RESULT( cyg_fs_getinfo, err );
+ diag_printf("<INFO>: total size: %6lld blocks, %10lld bytes\n",
+ usage.total_blocks, usage.total_blocks * usage.block_size);
+ diag_printf("<INFO>: free size: %6lld blocks, %10lld bytes\n",
+ usage.free_blocks, usage.free_blocks * usage.block_size);
+ diag_printf("<INFO>: block size: %6u bytes\n", usage.block_size);
+#endif
+ // --------------------------------------------------------------
+
err = umount( "/" );
if( err < 0 ) SHOW_RESULT( umount, err );
+2007-10-15 Sergei Gavrikov <w3sg@SoftHome.net>
+
+ * cdl/hal_arm.cdl: Use ACTUAL_CFLAGS whenever possible to avoid
+ warnings and complaints from newer compilers.
+
+2007-09-11 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/hal_misc.c: Include <cyg/infra/diag.h> to prevent compiler
+ warning when CYGHWR_HAL_ARM_DUMP_EXCEPTIONS is enabled.
+ Reported by Sergei Gavrikov <w3sg@SoftHome.net.
+
+2007-02-03 Sergei Gavrikov <sg@sgs.gomel.by>
+
+ * src/vectors.S: Added a possibility to fix ARM vector 0x14
+ (unused vector). Some platforms need itself in that.
+
+2007-01-09 Sergei Gavrikov <sg@sgs.gomel.by>
+
+ * src/arm-stub.c: Added string.h header (`memcpy' declaration).
+
+2006-09-06 Daniel Néri <daniel.neri@sigicom.se>
+
+ * include/basetype.h: (CYG_DOUBLE_BYTEORDER): Add proper
+ definition for VFP floating point format (uses "natural" byte
+ order) on little-endian ARM.
+
+2006-02-06 Sergei Organov <osv@javad.com>
+
+ * src/vectors.S: disable FIQ in IRQ handler to fix race condition
+ of recursively entering IRQ handler through FIQ handler. Remove
+ unreferenced handle_IRQ_or_FIQ label.
+
+2006-01-18 Jay Foster <jay@systech.com>
+
+ * src/context.S (hal_thread_switch_context): Close race condition
+ that could cause corruption of the sp or lr registers.
+
2005-04-21 Ian Campbell <icampbell@arcom.com>
* src/redboot_linux_exec.c: Added -t option which takes the
# n.b. grep does not behave itself under win32
make -priority 1 {
arm.inc : <PACKAGE>/src/hal_mk_defs.c
- $(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,arm.tmp -o hal_mk_defs.tmp -S $<
+ $(CC) $(ACTUAL_CFLAGS) $(INCLUDE_PATH) -Wp,-MD,arm.tmp -o hal_mk_defs.tmp -S $<
fgrep .equ hal_mk_defs.tmp | sed s/#// > $@
@echo $@ ": \\" > $(notdir $@).deps
@tail -n +2 arm.tmp >> $(notdir $@).deps
make {
<PREFIX>/lib/vectors.o : <PACKAGE>/src/vectors.S
- $(CC) -Wp,-MD,vectors.tmp $(INCLUDE_PATH) $(CFLAGS) -c -o $@ $<
+ $(CC) -Wp,-MD,vectors.tmp $(INCLUDE_PATH) $(ACTUAL_CFLAGS) -c -o $@ $<
@echo $@ ": \\" > $(notdir $@).deps
@tail -n +2 vectors.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
make {
<PREFIX>/lib/target.ld: <PACKAGE>/src/arm.ld
- $(CC) -E -P -Wp,-MD,target.tmp -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
+ $(CC) -E -P -Wp,-MD,target.tmp -xc $(INCLUDE_PATH) $(ACTUAL_CFLAGS) -o $@ $<
@echo $@ ": \\" > $(notdir $@).deps
@tail -n +2 target.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
#else
# define CYG_BYTEORDER CYG_LSBFIRST // Little endian
#endif
-#define CYG_DOUBLE_BYTEORDER CYG_MSBFIRST // Big? endian
+
+#if defined(__ARMEL__) && defined(__VFP_FP__)
+# define CYG_DOUBLE_BYTEORDER CYG_LSBFIRST
+#else
+# define CYG_DOUBLE_BYTEORDER CYG_MSBFIRST // Big? endian
+#endif
//-----------------------------------------------------------------------------
// ARM does not usually use labels with underscores.
(_regs_)->lr = (CYG_WORD)(_entry_); /* LR = entry point */ \
(_regs_)->pc = (CYG_WORD)(_entry_); /* PC = [initial] entry point */\
(_regs_)->cpsr = (CPSR_THREAD_INITIAL); /* PSR = Interrupt enabled */ \
- _sparg_ = (CYG_ADDRESS)_regs_; \
+ _sparg_ = (void *)_regs_; \
CYG_MACRO_END
//--------------------------------------------------------------------------
.text _vma_ : _lma_ \
{ _stext = ABSOLUTE(.); \
PROVIDE (__stext = ABSOLUTE(.)); \
- *(.text*) *(.gnu.warning) *(.gnu.linkonce.t.*) *(.init) \
+ *(.text*) *(i.*) *(.gnu.warning) *(.gnu.linkonce.t.*) *(.init) \
*(.glue_7) *(.glue_7t) \
} > _region_ \
_etext = .; PROVIDE (__etext = .);
.rodata1 _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.rodata1) } \
> _region_
+#define SECTION_extab(_region_, _vma_, _lma_) \
+ .extab _vma_ : _lma_ \
+ { FORCE_OUTPUT; *(.ARM.extab*) } \
+ > _region_
+#define SECTION_exidx(_region_, _vma_, _lma_) \
+ .exidx _vma_ : _lma_ \
+ { FORCE_OUTPUT; *(.ARM.exidx*) } \
+ > _region_
#endif // CYGPRI_PID_BE_WORKAROUND
#define SECTION_fixup(_region_, _vma_, _lma_) \
#define SECTION_data(_region_, _vma_, _lma_) \
.data _vma_ : _lma_ \
{ __ram_data_start = ABSOLUTE (.); \
- *(.data*) *(.data1) *(.gnu.linkonce.d.*) MERGE_IN_RODATA \
+ *(.data*) *(.data1) *(.constdata*) *(.gnu.linkonce.d.*) MERGE_IN_RODATA \
. = ALIGN (4); \
KEEP(*( SORT (.ecos.table.*))) ; \
. = ALIGN (4); \
//========================================================================
#include <stddef.h>
+#include <string.h>
#include <pkgconf/hal.h>
// Need to save/restore R4..R12, R13 (sp), R14 (lr)
// Note: this is a little wasteful since r0..r3 don't need to be saved.
-// They are saved here though so that the information can match the HAL_SavedRegisters
+// They are saved here though so that the information can match the
+// HAL_SavedRegisters
FUNC_START_ARM(hal_thread_switch_context, r2)
- sub ip,sp,#20 // skip svc_sp, svc_lr, vector, cpsr, and pc
- stmfd ip!,{sp,lr}
- mov sp,ip
+ mov ip,sp
+ sub sp,sp,#(ARMREG_SIZE - armreg_lr - 4) // skip svc_sp, svc_lr, vector, cpsr, and pc
+ stmfd sp!,{ip,lr}
stmfd sp!,{r0-r10,fp,ip}
mrs r2,cpsr
str r2,[sp,#armreg_cpsr]
#include <cyg/hal/hal_arch.h> // HAL header
#include <cyg/hal/hal_intr.h> // HAL header
-externC void diag_printf(const char *fmt, ...);
+#include <cyg/infra/diag.h>
/*------------------------------------------------------------------------*/
/* First level C exception handler. */
//==========================================================================
//
-// redboot_linux_boot.c
+// redboot_linux_boot.c
//
-// RedBoot command to boot Linux on ARM platforms
+// RedBoot command to boot Linux on ARM platforms
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
//####ECOSGPLCOPYRIGHTEND####
//####OTHERCOPYRIGHTBEGIN####
//
-// The structure definitions below are taken from include/asm-arm/setup.h in
-// the Linux kernel, Copyright (C) 1997-1999 Russell King. Their presence
-// here is for the express purpose of communication with the Linux kernel
-// being booted and is considered 'fair use' by the original author and
-// are included with his permission.
+// The structure definitions below are taken from include/asm-arm/setup.h in
+// the Linux kernel, Copyright (C) 1997-1999 Russell King. Their presence
+// here is for the express purpose of communication with the Linux kernel
+// being booted and is considered 'fair use' by the original author and
+// are included with his permission.
//
//####OTHERCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
-// Author(s): gthomas
+// Author(s): gthomas
// Contributors: gthomas, jskov,
-// Russell King <rmk@arm.linux.org.uk>
-// Date: 2001-02-20
-// Purpose:
-// Description:
-//
+// Russell King <rmk@arm.linux.org.uk>
+// Date: 2001-02-20
+// Purpose:
+// Description:
+//
// This code is part of RedBoot (tm).
//
//####DESCRIPTIONEND####
#include <redboot.h>
#ifdef CYGPKG_IO_ETH_DRIVERS
-#include <cyg/io/eth/eth_drv.h> // Logical driver interfaces
+#include <cyg/io/eth/eth_drv.h> // Logical driver interfaces
#endif
#include <cyg/hal/hal_intr.h>
#endif
// FIXME: This should be a CDL variable, and CYGSEM_REDBOOT_ARM_LINUX_BOOT
-// active_if CYGHWR_HAL_ARM_REDBOOT_MACHINE_TYPE>0
+// active_if CYGHWR_HAL_ARM_REDBOOT_MACHINE_TYPE>0
#ifdef HAL_PLATFORM_MACHINE_TYPE
#define CYGHWR_REDBOOT_ARM_MACHINE_TYPE HAL_PLATFORM_MACHINE_TYPE
// Exported CLI function(s)
static void do_exec(int argc, char *argv[]);
RedBoot_cmd("exec",
- "Execute an image - with MMU off",
- "[-w timeout] [-b <load addr> [-l <length>]]\n"
- " [-r <ramdisk addr> [-s <ramdisk length>]]\n"
- " [-c \"kernel command line\"] [-t <target> ] [<entry_point>]",
- do_exec
- );
+ "Execute an image - with MMU off",
+ "[-w timeout] [-b <load addr> [-l <length>]]\n"
+ " [-r <ramdisk addr> [-s <ramdisk length>]]\n"
+ " [-c \"kernel command line\"] [-t <target> ] [<entry_point>]",
+ do_exec
+ );
// CYGARC_HAL_MMU_OFF inserts code to turn off MMU and jump to a physical
// address. Some ARM implementations may need special handling and define
#ifndef CYGARC_HAL_MMU_OFF
#define __CYGARC_GET_CTLREG \
- " mrc p15,0,r0,c1,c0,0\n"
+ " mrc p15,0,r0,c1,c0,0\n"
-#define __CYGARC_CLR_MMU_BITS \
- " bic r0,r0,#0xd\n" \
- " bic r0,r0,#0x1000\n" \
+#define __CYGARC_CLR_MMU_BITS \
+ " bic r0,r0,#0xd\n" \
+ " bic r0,r0,#0x1000\n" \
#ifdef CYGHWR_HAL_ARM_BIGENDIAN
-#define __CYGARC_CLR_MMU_BITS_X \
- " bic r0,r0,#0x8d\n" \
- " bic r0,r0,#0x1000\n"
+#define __CYGARC_CLR_MMU_BITS_X \
+ " bic r0,r0,#0x8d\n" \
+ " bic r0,r0,#0x1000\n"
#else
-#define __CYGARC_CLR_MMU_BITS_X \
- " bic r0,r0,#0xd\n" \
- " bic r0,r0,#0x1000\n" \
- " orr r0,r0,#0x80\n"
+#define __CYGARC_CLR_MMU_BITS_X \
+ " bic r0,r0,#0xd\n" \
+ " bic r0,r0,#0x1000\n" \
+ " orr r0,r0,#0x80\n"
#endif
#define __CYGARC_SET_CTLREG(__paddr__) \
- " mcr p15,0,r0,c1,c0,0\n" \
- " mov pc," #__paddr__ "\n"
+ " mcr p15,0,r0,c1,c0,0\n" \
+ " mov pc," #__paddr__ "\n"
#define CYGARC_HAL_MMU_OFF(__paddr__) \
- " mcr p15,0,r0,c7,c10,4\n" \
- " mcr p15,0,r0,c7,c7,0\n" \
- __CYGARC_GET_CTLREG \
- __CYGARC_CLR_MMU_BITS \
+ " mcr p15,0,r0,c7,c10,4\n" \
+ " mcr p15,0,r0,c7,c7,0\n" \
+ __CYGARC_GET_CTLREG \
+ __CYGARC_CLR_MMU_BITS \
__CYGARC_SET_CTLREG(__paddr__)
-#define CYGARC_HAL_MMU_OFF_X(__paddr__) \
- " mcr p15,0,r0,c7,c10,4\n" \
- " mcr p15,0,r0,c7,c7,0\n" \
- __CYGARC_GET_CTLREG \
- __CYGARC_CLR_MMU_BITS_X \
+#define CYGARC_HAL_MMU_OFF_X(__paddr__) \
+ " mcr p15,0,r0,c7,c10,4\n" \
+ " mcr p15,0,r0,c7,c7,0\n" \
+ __CYGARC_GET_CTLREG \
+ __CYGARC_CLR_MMU_BITS_X \
__CYGARC_SET_CTLREG(__paddr__)
-#endif // CYGARC_HAL_MMU_OFF
+#endif // CYGARC_HAL_MMU_OFF
+#ifndef CYGARC_HAL_EXEC_FIXUP
+#define CYGARC_HAL_EXEC_FIXUP() ""
+#endif
//
// Parameter info for Linux kernel
-// ** C A U T I O N ** This setup must match "asm-arm/setup.h"
+// ** C A U T I O N ** This setup must match "asm-arm/setup.h"
//
// Info is passed at a fixed location, using a sequence of tagged
// data entries.
typedef unsigned char u8;
//=========================================================================
-// From Linux <asm-arm/setup.h>
+//
From Linux <asm-arm/setup.h>
#define ATAG_NONE 0x00000000
struct tag_header {
- u32 size; // Size of tag (hdr+data) in *longwords*
- u32 tag;
+ u32 size; // Size of tag (hdr+data) in *longwords*
+ u32 tag;
};
#define ATAG_CORE 0x54410001
struct tag_core {
- u32 flags; /* bit 0 = read-only */
- u32 pagesize;
- u32 rootdev;
+ u32 flags; /* bit 0 = read-only */
+ u32 pagesize;
+ u32 rootdev;
};
#define ATAG_MEM 0x54410002
struct tag_mem32 {
- u32 size;
- u32 start;
+ u32 size;
+ u32 start;
};
#define ATAG_VIDEOTEXT 0x54410003
struct tag_videotext {
- u8 x;
- u8 y;
- u16 video_page;
- u8 video_mode;
- u8 video_cols;
- u16 video_ega_bx;
- u8 video_lines;
- u8 video_isvga;
- u16 video_points;
+ u8 x;
+ u8 y;
+ u16 video_page;
+ u8 video_mode;
+ u8 video_cols;
+ u16 video_ega_bx;
+ u8 video_lines;
+ u8 video_isvga;
+ u16 video_points;
};
#define ATAG_RAMDISK 0x54410004
struct tag_ramdisk {
- u32 flags; /* b0 = load, b1 = prompt */
- u32 size;
- u32 start;
+ u32 flags; /* b0 = load, b1 = prompt */
+ u32 size;
+ u32 start;
};
/*
/* describes where the compressed ramdisk image lives (physical address) */
#define ATAG_INITRD2 0x54420005
struct tag_initrd {
- u32 start;
- u32 size;
+ u32 start;
+ u32 size;
};
#define ATAG_SERIAL 0x54410006
struct tag_serialnr {
- u32 low;
- u32 high;
+ u32 low;
+ u32 high;
};
#define ATAG_REVISION 0x54410007
struct tag_revision {
- u32 rev;
+ u32 rev;
};
#define ATAG_VIDEOLFB 0x54410008
struct tag_videolfb {
- u16 lfb_width;
- u16 lfb_height;
- u16 lfb_depth;
- u16 lfb_linelength;
- u32 lfb_base;
- u32 lfb_size;
- u8 red_size;
- u8 red_pos;
- u8 green_size;
- u8 green_pos;
- u8 blue_size;
- u8 blue_pos;
- u8 rsvd_size;
- u8 rsvd_pos;
+ u16 lfb_width;
+ u16 lfb_height;
+ u16 lfb_depth;
+ u16 lfb_linelength;
+ u32 lfb_base;
+ u32 lfb_size;
+ u8 red_size;
+ u8 red_pos;
+ u8 green_size;
+ u8 green_pos;
+ u8 blue_size;
+ u8 blue_pos;
+ u8 rsvd_size;
+ u8 rsvd_pos;
};
#define ATAG_CMDLINE 0x54410009
struct tag_cmdline {
- char cmdline[1];
+ char cmdline[1];
};
#define ATAG_ACORN 0x41000101
struct tag_acorn {
- u32 memc_control_reg;
- u32 vram_pages;
- u8 sounddefault;
- u8 adfsdrives;
+ u32 memc_control_reg;
+ u32 vram_pages;
+ u8 sounddefault;
+ u8 adfsdrives;
};
#define ATAG_MEMCLK 0x41000402
struct tag_memclk {
- u32 fmemclk;
+ u32 fmemclk;
};
struct tag {
- struct tag_header hdr;
- union {
- struct tag_core core;
- struct tag_mem32 mem;
- struct tag_videotext videotext;
- struct tag_ramdisk ramdisk;
- struct tag_initrd initrd;
- struct tag_serialnr serialnr;
- struct tag_revision revision;
- struct tag_videolfb videolfb;
- struct tag_cmdline cmdline;
-
- /*
- * Acorn specific
- */
- struct tag_acorn acorn;
-
- /*
- * DC21285 specific
- */
- struct tag_memclk memclk;
- } u;
+ struct tag_header hdr;
+ union {
+ struct tag_core core;
+ struct tag_mem32 mem;
+ struct tag_videotext videotext;
+ struct tag_ramdisk ramdisk;
+ struct tag_initrd initrd;
+ struct tag_serialnr serialnr;
+ struct tag_revision revision;
+ struct tag_videolfb videolfb;
+ struct tag_cmdline cmdline;
+
+ /*
+ * Acorn specific
+ */
+ struct tag_acorn acorn;
+
+ /*
+ * DC21285 specific
+ */
+ struct tag_memclk memclk;
+ } u;
};
// End of inclusion from <asm-arm/setup.h>
// Default memory layout - can be overridden by platform, typically in
// <cyg/hal/plf_io.h>
#ifndef CYGHWR_REDBOOT_LINUX_ATAG_MEM
-#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \
- CYG_MACRO_START \
- /* Next ATAG_MEM. */ \
- _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header))/sizeof(long); \
- _p_->hdr.tag = ATAG_MEM; \
- /* Round up so there's only one bit set in the memory size. \
- * Don't double it if it's already a power of two, though. \
- */ \
- _p_->u.mem.size = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE); \
- if (_p_->u.mem.size < CYGMEM_REGION_ram_SIZE) \
- _p_->u.mem.size <<= 1; \
- _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram); \
- CYG_MACRO_END
+#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \
+ CYG_MACRO_START \
+ /* Next ATAG_MEM. */ \
+ _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_MEM; \
+ /* Round up so there's only one bit set in the memory size. \
+ * Don't double it if it's already a power of two, though. \
+ */ \
+ _p_->u.mem.size = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE); \
+ if (_p_->u.mem.size < CYGMEM_REGION_ram_SIZE) \
+ _p_->u.mem.size <<= 1; \
+ _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram); \
+ CYG_MACRO_END
#endif
// Round up a quantity to a longword (32 bit) length
-#define ROUNDUP(n) (((n)+3)&~3)
+#define ROUNDUP(n) (((n) + 3) & ~3)
static void
do_exec(int argc, char *argv[])
{
- unsigned long entry;
- unsigned long target;
- unsigned long oldints;
- bool wait_time_set;
- int wait_time, res, num_opts;
- bool base_addr_set, length_set, cmd_line_set;
- bool ramdisk_addr_set, ramdisk_size_set;
- unsigned long base_addr, length;
- unsigned long ramdisk_addr, ramdisk_size;
- struct option_info opts[7];
- char line[8];
- char *cmd_line;
- struct tag *params = (struct tag *)CYGHWR_REDBOOT_ARM_LINUX_TAGS_ADDRESS;
+ unsigned long entry;
+ unsigned long target;
+ unsigned long oldints;
+ bool wait_time_set;
+ int wait_time, res, num_opts;
+ bool base_addr_set, length_set, cmd_line_set;
+ bool ramdisk_addr_set, ramdisk_size_set;
+ unsigned long base_addr, length;
+ unsigned long ramdisk_addr, ramdisk_size;
+ struct option_info opts[7];
+ char line[8];
+ char *cmd_line;
+ struct tag *params = (struct tag *)CYGHWR_REDBOOT_ARM_LINUX_TAGS_ADDRESS;
#ifdef CYGHWR_REDBOOT_LINUX_EXEC_X_SWITCH
- bool swap_endian;
- extern char __xtramp_start__[], __xtramp_end__[];
+ bool swap_endian;
+ extern char __xtramp_start__[], __xtramp_end__[];
#endif
- extern char __tramp_start__[], __tramp_end__[];
-
- // Check to see if a valid image has been loaded
- if (entry_address == (unsigned long)NO_MEMORY) {
- diag_printf("Can't execute Linux - invalid entry address\n");
- return;
- }
- // Default physical entry point for Linux is kernel base.
- entry = (unsigned long)CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS;
- target = (unsigned long)CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS;
-
- base_addr = load_address;
- length = load_address_end - load_address;
- // Round length up to the next quad word
- length = (length + 3) & ~0x3;
-
- ramdisk_size = 4096*1024;
- init_opts(&opts[0], 'w', true, OPTION_ARG_TYPE_NUM,
- &wait_time, (bool *)&wait_time_set, "wait timeout");
- init_opts(&opts[1], 'b', true, OPTION_ARG_TYPE_NUM,
- &base_addr, (bool *)&base_addr_set, "base address");
- init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM,
- &length, (bool *)&length_set, "length");
- init_opts(&opts[3], 'c', true, OPTION_ARG_TYPE_STR,
- &cmd_line, (bool *)&cmd_line_set, "kernel command line");
- init_opts(&opts[4], 'r', true, OPTION_ARG_TYPE_NUM,
- &ramdisk_addr, (bool *)&ramdisk_addr_set, "ramdisk_addr");
- init_opts(&opts[5], 's', true, OPTION_ARG_TYPE_NUM,
- &ramdisk_size, (bool *)&ramdisk_size_set, "ramdisk_size");
- init_opts(&opts[6], 't', true, OPTION_ARG_TYPE_NUM,
- &target, 0, "[physical] target address");
- num_opts = 7;
+ extern char __tramp_start__[], __tramp_end__[];
+
+ // Check to see if a valid image has been loaded
+ if (entry_address == (unsigned long)NO_MEMORY) {
+ diag_printf("Can't execute Linux - invalid entry address\n");
+ return;
+ }
+ // Default physical entry point for Linux is kernel base.
+ entry = (unsigned long)CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS;
+ target = (unsigned long)CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS;
+
+ base_addr = load_address;
+ length = load_address_end - load_address;
+ // Round length up to the next quad word
+ length = (length + 3) & ~0x3;
+
+ ramdisk_size = 4096*1024;
+ init_opts(&opts[0], 'w', true, OPTION_ARG_TYPE_NUM,
+ &wait_time, &wait_time_set, "wait timeout");
+ init_opts(&opts[1], 'b', true, OPTION_ARG_TYPE_NUM,
+ &base_addr, &base_addr_set, "base address");
+ init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM,
+ &length, &length_set, "length");
+ init_opts(&opts[3], 'c', true, OPTION_ARG_TYPE_STR,
+ &cmd_line, &cmd_line_set, "kernel command line");
+ init_opts(&opts[4], 'r', true, OPTION_ARG_TYPE_NUM,
+ &ramdisk_addr, &ramdisk_addr_set, "ramdisk_addr");
+ init_opts(&opts[5], 's', true, OPTION_ARG_TYPE_NUM,
+ &ramdisk_size, &ramdisk_size_set, "ramdisk_size");
+ init_opts(&opts[6], 't', true, OPTION_ARG_TYPE_NUM,
+ &target, 0, "[physical] target address");
+ num_opts = 7;
#ifdef CYGHWR_REDBOOT_LINUX_EXEC_X_SWITCH
- init_opts(&opts[num_opts], 'x', false, OPTION_ARG_TYPE_FLG,
- &swap_endian, 0, "swap endianess");
- ++num_opts;
+ init_opts(&opts[num_opts], 'x', false, OPTION_ARG_TYPE_FLG,
+ &swap_endian, 0, "swap endianess");
+ ++num_opts;
#endif
- if (!scan_opts(argc, argv, 1, opts, num_opts, &entry, OPTION_ARG_TYPE_NUM, "[physical] starting address"))
- {
- return;
- }
-
- // Set up parameters to pass to kernel
-
- // CORE tag must be present & first
- params->hdr.size = (sizeof(struct tag_core) + sizeof(struct tag_header))/sizeof(long);
- params->hdr.tag = ATAG_CORE;
- params->u.core.flags = 0;
- params->u.core.pagesize = 0;
- params->u.core.rootdev = 0;
- params = (struct tag *)((long *)params + params->hdr.size);
-
- // Fill in the details of the memory layout
- CYGHWR_REDBOOT_LINUX_ATAG_MEM(params);
-
- params = (struct tag *)((long *)params + params->hdr.size);
- if (ramdisk_addr_set) {
- params->hdr.size = (sizeof(struct tag_initrd) + sizeof(struct tag_header))/sizeof(long);
- params->hdr.tag = ATAG_INITRD2;
- params->u.initrd.start = CYGARC_PHYSICAL_ADDRESS(ramdisk_addr);
- params->u.initrd.size = ramdisk_size;
- params = (struct tag *)((long *)params + params->hdr.size);
- }
- if (cmd_line_set) {
- params->hdr.size = (ROUNDUP(strlen(cmd_line)) + sizeof(struct tag_header))/sizeof(long);
- params->hdr.tag = ATAG_CMDLINE;
- strcpy(params->u.cmdline.cmdline, cmd_line);
- params = (struct tag *)((long *)params + params->hdr.size);
- }
- // Mark end of parameter list
- params->hdr.size = 0;
- params->hdr.tag = ATAG_NONE;
-
- if (wait_time_set) {
- int script_timeout_ms = wait_time * 1000;
+ if (!scan_opts(argc, argv, 1, opts, num_opts, &entry,
+ OPTION_ARG_TYPE_NUM, "[physical] starting address")) {
+ return;
+ }
+
+ // Set up parameters to pass to kernel
+
+ // CORE tag must be present & first
+ params->hdr.size = (sizeof(struct tag_core) + sizeof(struct tag_header))/sizeof(long);
+ params->hdr.tag = ATAG_CORE;
+ params->u.core.flags = 0;
+ params->u.core.pagesize = 0;
+ params->u.core.rootdev = 0;
+ params = (struct tag *)((long *)params + params->hdr.size);
+
+ // Fill in the details of the memory layout
+ CYGHWR_REDBOOT_LINUX_ATAG_MEM(params);
+
+ params = (struct tag *)((long *)params + params->hdr.size);
+ if (ramdisk_addr_set) {
+ params->hdr.size = (sizeof(struct tag_initrd) + sizeof(struct tag_header))/sizeof(long);
+ params->hdr.tag = ATAG_INITRD2;
+ params->u.initrd.start = CYGARC_PHYSICAL_ADDRESS(ramdisk_addr);
+ params->u.initrd.size = ramdisk_size;
+ params = (struct tag *)((long *)params + params->hdr.size);
+ }
+ if (cmd_line_set) {
+ params->hdr.size = (ROUNDUP(strlen(cmd_line)) + sizeof(struct tag_header))/sizeof(long);
+ params->hdr.tag = ATAG_CMDLINE;
+ strcpy(params->u.cmdline.cmdline, cmd_line);
+ params = (struct tag *)((long *)params + params->hdr.size);
+ }
+ // Mark end of parameter list
+ params->hdr.size = 0;
+ params->hdr.tag = ATAG_NONE;
+
+ if (wait_time_set) {
+ int script_timeout_ms = wait_time * 1000;
#ifdef CYGFUN_REDBOOT_BOOT_SCRIPT
- unsigned char *hold_script = script;
- script = (unsigned char *)0;
+ unsigned char *hold_script = script;
+ script = NULL;
#endif
- diag_printf("About to start execution of image at %p, entry point %p - abort with ^C within %d seconds\n",
- (void *)target, (void *)entry, wait_time);
- while (script_timeout_ms >= CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT) {
- res = _rb_gets(line, sizeof(line), CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT);
- if (res == _GETS_CTRLC) {
+ diag_printf("About to start execution of image at %p, entry point %p - abort with ^C within %d seconds\n",
+ (void *)target, (void *)entry, wait_time);
+ while (script_timeout_ms >= CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT) {
+ res = _rb_gets(line, sizeof(line), CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT);
+ if (res == _GETS_CTRLC) {
#ifdef CYGFUN_REDBOOT_BOOT_SCRIPT
- script = hold_script; // Re-enable script
+ script = hold_script; // Re-enable script
#endif
- return;
- }
- script_timeout_ms -= CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT;
- }
- }
- if (!base_addr_set) {
- if ((base_addr == 0) || (length == 0)) {
- // Probably not valid - don't try it
- diag_printf("Base address unknown - use \"-b\" option\n");
- return;
- }
- diag_printf("Using base address %p and length %p\n",
- (void*)base_addr, (void*)length);
- } else if (base_addr_set && !length_set) {
- diag_printf("Length required for non-standard base address\n");
- return;
- }
+ return;
+ }
+ script_timeout_ms -= CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT;
+ }
+ }
+ if (!base_addr_set) {
+ if ((base_addr == 0) || (length == 0)) {
+ // Probably not valid - don't try it
+ diag_printf("Base address unknown - use \"-b\" option\n");
+ return;
+ }
+ diag_printf("Using base address %p and length %p\n",
+ (void*)base_addr, (void*)length);
+ } else if (base_addr_set && !length_set) {
+ diag_printf("Length required for non-standard base address\n");
+ return;
+ }
#ifdef CYGPKG_IO_ETH_DRIVERS
- eth_drv_stop();
+ eth_drv_stop();
#endif
- HAL_DISABLE_INTERRUPTS(oldints);
- HAL_DCACHE_SYNC();
- HAL_ICACHE_DISABLE();
- HAL_DCACHE_DISABLE();
- HAL_DCACHE_SYNC();
- HAL_ICACHE_INVALIDATE_ALL();
- HAL_DCACHE_INVALIDATE_ALL();
-
- // Tricky code. We are currently running with the MMU on and the
- // memory map possibly convoluted from 1-1. The trampoline code
- // between labels __tramp_start__ and __tramp_end__ must be copied
- // to RAM and then executed at the non-mapped address.
- //
- // This magic was created in order to be able to execute standard
- // Linux kernels with as little change/perturberance as possible.
+ HAL_DISABLE_INTERRUPTS(oldints);
+ HAL_DCACHE_SYNC();
+ HAL_ICACHE_DISABLE();
+ HAL_DCACHE_DISABLE();
+ HAL_DCACHE_SYNC();
+ HAL_ICACHE_INVALIDATE_ALL();
+ HAL_DCACHE_INVALIDATE_ALL();
+
+ // Tricky code. We are currently running with the MMU on and the
+ // memory map possibly convoluted from 1-1. The trampoline code
+ // between labels __tramp_start__ and __tramp_end__ must be copied
+ // to RAM and then executed at the non-mapped address.
+ //
+ // This magic was created in order to be able to execute standard
+ // Linux kernels with as little change/perturberance as possible.
#ifdef CYGHWR_REDBOOT_LINUX_EXEC_X_SWITCH
- if (swap_endian) {
- // copy the trampline code
+ if (swap_endian) {
+ // copy the trampoline code
+ memcpy((char *)CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS,
+ __xtramp_start__,
+ __xtramp_end__ - __xtramp_start__);
+
+ asm volatile (
+ CYGARC_HAL_MMU_OFF_X(%5)
+ "__xtramp_start__:\n"
+ " cmp %1,%4;\n" // Default kernel load address. Relocate
+ " beq 2f;\n" // kernel image there if necessary, and
+ " cmp %2,#0;\n" // if size is non-zero
+ " beq 2f;\n"
+ "1:\n"
+ " ldr r0,[%1],#4;\n"
+ " eor %5, r0, r0, ror #16;\n"
+ " bic %5, %5, #0x00ff0000;\n"
+ " mov r0, r0, ror #8;\n"
+ " eor r0, r0, %5, lsr #8;\n"
+ " str r0,[%4],#4;\n"
+ " subs %2,%2,#4;\n"
+ " bne 1b;\n"
+ "2:\n"
+ " mov r0,#0;\n" // Set board type
+ " mov r1,%3;\n" // Machine type
+ " mov r2,%6;\n" // Kernel parameters
+ " mov pc,%0;\n" // Jump to kernel
+ "__xtramp_end__:\n"
+ : :
+ "r"(entry),
+ "r"(CYGARC_PHYSICAL_ADDRESS(base_addr)),
+ "r"(length),
+ "r"(CYGHWR_REDBOOT_ARM_MACHINE_TYPE),
+ "r"(CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS),
+ "r"(CYGARC_PHYSICAL_ADDRESS(CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS)),
+ "r"(CYGARC_PHYSICAL_ADDRESS(CYGHWR_REDBOOT_ARM_LINUX_TAGS_ADDRESS))
+ : "r0", "r1"
+ );
+ }
+#endif // CYGHWR_REDBOOT_LINUX_EXEC_X_SWITCH
+
+ // copy the trampoline code
memcpy((char *)CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS,
- __xtramp_start__,
- __xtramp_end__ - __xtramp_start__);
+ __tramp_start__,
+ __tramp_end__ - __tramp_start__);
asm volatile (
- CYGARC_HAL_MMU_OFF_X(%5)
- "__xtramp_start__:\n"
- " cmp %1,%4;\n" // Default kernel load address. Relocate
- " beq 2f;\n" // kernel image there if necessary, and
- " cmp %2,#0;\n" // if size is non-zero
- " beq 2f;\n"
- "1:\n"
- " ldr r0,[%1],#4;\n"
- " eor %5, r0, r0, ror #16;\n"
- " bic %5, %5, #0x00ff0000;\n"
- " mov r0, r0, ror #8;\n"
- " eor r0, r0, %5, lsr #8;\n"
- " str r0,[%4],#4;\n"
- " subs %2,%2,#4;\n"
- " bne 1b;\n"
- "2:\n"
- " mov r0,#0;\n" // Set board type
- " mov r1,%3;\n" // Machine type
- " mov r2,%6;\n" // Kernel parameters
- " mov pc,%0;\n" // Jump to kernel
- "__xtramp_end__:\n"
- : :
- "r"(entry),
- "r"(CYGARC_PHYSICAL_ADDRESS(base_addr)),
- "r"(length),
- "r"(CYGHWR_REDBOOT_ARM_MACHINE_TYPE),
- "r"(CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS),
- "r"(CYGARC_PHYSICAL_ADDRESS(CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS)),
- "r"(CYGARC_PHYSICAL_ADDRESS(CYGHWR_REDBOOT_ARM_LINUX_TAGS_ADDRESS))
- : "r0", "r1"
- );
- }
-#endif // CYGHWR_REDBOOT_LINUX_EXEC_X_SWITCH
-
- // copy the trampline code
- memcpy((char *)CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS,
- __tramp_start__,
- __tramp_end__ - __tramp_start__);
-
- asm volatile (
- CYGARC_HAL_MMU_OFF(%5)
- "__tramp_start__:\n"
- " cmp %1,%4;\n" // Default kernel load address. Relocate
- " beq 2f;\n" // kernel image there if necessary, and
- " cmp %2,#0;\n" // if size is non-zero
- " beq 2f;\n"
- "1:\n"
- " ldr r0,[%1],#4;\n"
- " str r0,[%4],#4;\n"
- " subs %2,%2,#4;\n"
- " bne 1b;\n"
- "2:\n"
- " mov r0,#0;\n" // Set board type
- " mov r1,%3;\n" // Machine type
- " mov r2,%6;\n" // Kernel parameters
- " mov pc,%0;\n" // Jump to kernel
- "__tramp_end__:\n"
- : :
- "r"(entry),
- "r"(CYGARC_PHYSICAL_ADDRESS(base_addr)),
- "r"(length),
- "r"(CYGHWR_REDBOOT_ARM_MACHINE_TYPE),
- "r"(target),
- "r"(CYGARC_PHYSICAL_ADDRESS(CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS)),
- "r"(CYGARC_PHYSICAL_ADDRESS(CYGHWR_REDBOOT_ARM_LINUX_TAGS_ADDRESS))
- : "r0", "r1"
- );
+ CYGARC_HAL_MMU_OFF(%5)
+ "__tramp_start__:\n"
+ " cmp %1,%4;\n" // Default kernel load address. Relocate
+ " beq 2f;\n" // kernel image there if necessary, and
+ " cmp %2,#0;\n" // if size is non-zero
+ " beq 2f;\n"
+ "1:\n"
+ " ldr r0,[%1],#4;\n"
+ " str r0,[%4],#4;\n"
+ " subs %2,%2,#4;\n"
+ " bne 1b;\n"
+ "2:\n"
+ CYGARC_HAL_EXEC_FIXUP()
+ " mov r0,#0;\n" // Set board type
+ " mov r1,%3;\n" // Machine type
+ " mov r2,%6;\n" // Kernel parameters
+ " mov pc,%0;\n" // Jump to kernel
+ "__tramp_end__:\n"
+ : :
+ "r"(entry),
+ "r"(CYGARC_PHYSICAL_ADDRESS(base_addr)),
+ "r"(length),
+ "r"(CYGHWR_REDBOOT_ARM_MACHINE_TYPE),
+ "r"(target),
+ "r"(CYGARC_PHYSICAL_ADDRESS(CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS)),
+ "r"(CYGARC_PHYSICAL_ADDRESS(CYGHWR_REDBOOT_ARM_LINUX_TAGS_ADDRESS))
+ : "r0", "r1"
+ );
}
-
+
#endif // HAL_PLATFORM_MACHINE_TYPE - otherwise we do not support this stuff...
// EOF redboot_linux_exec.c
#ifdef __thumb__
// Switch to thumb mode
#define THUMB_MODE(_r_, _l_) \
- ldr _r_,=_l_ ## f+1 ;\
- bx _r_ ;\
- .pool ;\
- .code 16 ;\
- .thumb_func ;\
+ ldr _r_,=_l_ ## f+1 ;\
+ bx _r_ ;\
+ .pool ;\
+ .code 16 ;\
+ .thumb_func ;\
_l_:
// Call thumb function from ARM mode, return to ARM
// mode afterwards
#define THUMB_CALL(_r_, _l_, _f_) \
- ldr _r_,=_f_+1 ;\
- mov lr,pc ;\
- bx _r_ ;\
- .pool ;\
- .code 16 ;\
- .thumb_func ;\
- ldr _r_,=_l_ ## f ;\
- bx _r_ ;\
- .pool ;\
- .code 32 ;\
+ ldr _r_,=_f_+1 ;\
+ mov lr,pc ;\
+ bx _r_ ;\
+ .pool ;\
+ .code 16 ;\
+ .thumb_func ;\
+ ldr _r_,=_l_ ## f ;\
+ bx _r_ ;\
+ .pool ;\
+ .code 32 ;\
_l_:
// Switch to ARM mode
#define ARM_MODE(_r_, _l_) \
- ldr _r_,=_l_ ## f ;\
- bx _r_ ;\
- .pool ;\
- .code 32 ;\
+ ldr _r_,=_l_ ## f ;\
+ bx _r_ ;\
+ .pool ;\
+ .code 32 ;\
_l_:
// Function definition, start executing body in ARM mode
#define FUNC_START_ARM(_name_, _r_) \
- .code 16 ;\
- .thumb_func ;\
- .globl _name_ ;\
+ .code 16 ;\
+ .thumb_func ;\
+ .globl _name_ ;\
_name_: ;\
- ldr _r_,=_name_ ## _ARM ;\
- bx _r_ ;\
- .code 32 ;\
+ ldr _r_,=_name_ ## _ARM ;\
+ bx _r_ ;\
+ .code 32 ;\
_name_ ## _ARM:
#else
// Call ARM function
#define THUMB_CALL(_r_, _l_, _f_) \
- bl _f_
+ bl _f_
// Switch to ARM mode
#define ARM_MODE(_r_, _l_)
// Function definition, start executing body in ARM mode
#define FUNC_START_ARM(_name_, _r_) \
- .globl _name_; \
-_name_:
+ .globl _name_; \
+_name_:
#endif
-
+
#define PTR(name) \
.##name: .word name
// to execute at 0x50040000, then we want the reset vector to point to
// 0x0004pqrs - the unmapped ROM address of the code - rather than
// 0x0000pqrs, which is the offset into our flash block.
-//
+//
// But usually it's not defined, so the behaviour is the obvious.
-#ifndef UNMAPPED
+#ifndef UNMAPPED
#ifdef CYGHWR_HAL_ARM_HAS_MMU
# ifndef CYGHWR_HAL_ROM_VADDR
# define CYGHWR_HAL_ROM_VADDR __exception_handlers
#else
# define UNMAPPED(x) (x)
#endif
-#endif
-
+#endif
+
#define UNMAPPED_PTR(name) \
.##name: .word UNMAPPED(name)
// CYGHWR_LED_MACRO can be defined in hal_platform_setup.h. It's free to
// use r0+r1. Argument is in "\x" - cannot use macro arguments since the
-// macro may contain #-chars and use of arguments cause these to be
+// macro may contain #-chars and use of arguments cause these to be
// interpreted as CPP stringify operators.
// See example in PID hal_platform_setup.h.
#ifndef CYGHWR_LED_MACRO
#define CYGHWR_LED_MACRO
#endif
-
+
.macro LED x
CYGHWR_LED_MACRO
.endm
// Hardware exception vectors.
// This entire section will be copied to location 0x0000 at startup time.
//
- .code 32
- .section ".vectors","ax"
+ .code 32
+ .section ".vectors","ax"
// This macro allows platforms to add their own code at the very start of
-// the image. This may be required in some circumstances where eCos ROM
+// the image. This may be required in some circumstances where eCos ROM
// based code does not run immediately upon reset and/or when some sort of
-// special header is required at the start of the image.
+// special header is required at the start of the image.
#ifdef PLATFORM_PREAMBLE
- PLATFORM_PREAMBLE
+ PLATFORM_PREAMBLE
#endif
-
- .global __exception_handlers
+
+ .global __exception_handlers
__exception_handlers:
#ifdef CYGSEM_HAL_ROM_RESET_USES_JUMP
// Assumption: ROM code has these vectors at the hardware reset address.
// A simple jump removes any address-space dependencies [i.e. safer]
- b reset_vector // 0x00
-#else
- ldr pc,.reset_vector // 0x00
-#endif
- ldr pc,.undefined_instruction // 0x04
- ldr pc,.software_interrupt // 0x08 start && software int
- ldr pc,.abort_prefetch // 0x0C
- ldr pc,.abort_data // 0x10
- .word 0 // unused
- ldr pc,.IRQ // 0x18
- ldr pc,.FIQ // 0x1C
+ b reset_vector // 0x00
+#else
+ ldr pc,.reset_vector // 0x00
+#endif
+ ldr pc,.undefined_instruction // 0x04
+ ldr pc,.software_interrupt // 0x08 start && software int
+ ldr pc,.abort_prefetch // 0x0C
+ ldr pc,.abort_data // 0x10
+#ifdef CYGNUM_HAL_ARM_VECTOR_0x14
+ .word CYGNUM_HAL_ARM_VECTOR_0x14
+#else
+ .word 0 // unused
+#endif
+ ldr pc,.IRQ // 0x18
+ ldr pc,.FIQ // 0x1C
// The layout of these pointers should match the vector table above since
// they are copied in pairs.
- .global vectors
+ .global vectors
vectors:
UNMAPPED_PTR(reset_vector) // 0x20
PTR(undefined_instruction) // 0x24
PTR(software_interrupt) // 0x28
PTR(abort_prefetch) // 0x2C
PTR(abort_data) // 0x30
- .word 0 // 0x34
+ .word 0 // 0x34
PTR(IRQ) // 0x38
PTR(FIQ) // 0x3c
-#ifdef CYGSEM_HAL_ARM_PID_ANGEL_BOOT
+#ifdef CYGSEM_HAL_ARM_PID_ANGEL_BOOT
PTR(start) // This is copied to 0x28 for bootup // 0x40
-#endif
- // location 0x40 is used for storing DRAM size if known
- // for some platforms.
-
+#endif
+ // location 0x40 is used for storing DRAM size if known
+ // for some platforms.
+
//
// "Vectors" - fixed location data items
// This section contains any data which might be shared between
// an eCos application and any other environment, e.g. the debug
-// ROM.
+// ROM.
//
- .section ".fixed_vectors"
- // Interrupt/exception VSR pointers
- .globl hal_vsr_table
+ .section ".fixed_vectors"
+ // Interrupt/exception VSR pointers
+ .globl hal_vsr_table
hal_vsr_table:
- .rept 8
- .long 0
- .endr
+ .rept 8
+ .long 0
+ .endr
- .globl hal_dram_size
-hal_dram_size:
- .long 0
+ .globl hal_dram_size
+hal_dram_size:
+ .long 0
// what, if anything, hal_dram_type means is up to the platform
- .globl hal_dram_type
-hal_dram_type:
- .long 0
+ .globl hal_dram_type
+hal_dram_type:
+ .long 0
- .balign 16
+ .balign 16
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
// Vectors used to communicate between eCos and ROM environments
- .globl hal_virtual_vector_table
+ .globl hal_virtual_vector_table
hal_virtual_vector_table:
- .rept CYGNUM_CALL_IF_TABLE_SIZE
- .long 0
- .endr
+ .rept CYGNUM_CALL_IF_TABLE_SIZE
+ .long 0
+ .endr
#endif
-
+
#ifdef CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT
- .balign 16 // Should be at 0x50
+ .balign 16 // Should be at 0x50
ice_thread_vector:
- .long 0 // Must be 'MICE'
- .long 0 // Pointer to thread support vector
- .long 0 // eCos executing flag
- .long 0 // Must be 'GDB '
+ .long 0 // Must be 'MICE'
+ .long 0 // Pointer to thread support vector
+ .long 0 // eCos executing flag
+ .long 0 // Must be 'GDB '
#endif // CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT
- .balign 32
-
+ .balign 32
+
// Other vectors - this may include "fixed" locations
#ifdef PLATFORM_VECTORS
- PLATFORM_VECTORS
+ PLATFORM_VECTORS
#endif
-
- .text
+
+ .text
// Startup code which will get the machine into supervisor mode
- .global reset_vector
- .type reset_vector,function
+ .global reset_vector
+ .type reset_vector,function
reset_vector:
- PLATFORM_SETUP1 // Early stage platform initialization
- // which can set DRAM size at 0x40
- // see <cyg/hal/hal_platform_setup.h>
+ PLATFORM_SETUP1 // Early stage platform initialization
+ // which can set DRAM size at 0x40
+ // see <cyg/hal/hal_platform_setup.h>
- // Come here to reset board
-warm_reset:
+ // Come here to reset board
+warm_reset:
#if defined(CYG_HAL_STARTUP_RAM) && \
!defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
- mrs r7,cpsr // move back to IRQ mode
- and r7,r7,#CPSR_MODE_BITS
- cmp r7,#CPSR_SUPERVISOR_MODE
- beq start
+ mrs r7,cpsr // move back to IRQ mode
+ and r7,r7,#CPSR_MODE_BITS
+ cmp r7,#CPSR_SUPERVISOR_MODE
+ beq start
#endif
- // We cannot access any LED registers until after PLATFORM_SETUP1
- LED 7
+ // We cannot access any LED registers until after PLATFORM_SETUP1
+ LED 7
- mov r0,#0 // move vectors
- ldr r1,=__exception_handlers
+ mov r0,#0 // move vectors
+ ldr r1,=__exception_handlers
#ifndef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
- // Wait with this if stubs are included (see further down).
- ldr r2,[r1,#0x04] // undefined instruction
- str r2,[r0,#0x04]
- ldr r2,[r1,#0x24]
- str r2,[r0,#0x24]
+ // Wait with this if stubs are included (see further down).
+ ldr r2,[r1,#0x04] // undefined instruction
+ str r2,[r0,#0x04]
+ ldr r2,[r1,#0x24]
+ str r2,[r0,#0x24]
#endif
- ldr r2,[r1,#0x08] // software interrupt
- str r2,[r0,#0x08]
-
-#ifdef CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT
- ldr r2,=ice_thread_vector
- sub r2,r2,r1 // compute fixed (low memory) address
- ldr r3,=0x4D494345 // 'MICE'
- str r3,[r2],#4
- ldr r3,=hal_arm_ice_thread_handler
- str r3,[r2],#4
- mov r3,#1
- str r3,[r2],#4
- ldr r3,=0x47444220 // 'GDB '
- str r3,[r2],#4
+ ldr r2,[r1,#0x08] // software interrupt
+ str r2,[r0,#0x08]
+
+#ifdef CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT
+ ldr r2,=ice_thread_vector
+ sub r2,r2,r1 // compute fixed (low memory) address
+ ldr r3,=0x4D494345 // 'MICE'
+ str r3,[r2],#4
+ ldr r3,=hal_arm_ice_thread_handler
+ str r3,[r2],#4
+ mov r3,#1
+ str r3,[r2],#4
+ ldr r3,=0x47444220 // 'GDB '
+ str r3,[r2],#4
#endif // CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT
#if defined(CYGSEM_HAL_ARM_PID_ANGEL_BOOT)
// Ugly hack to get into supervisor mode
- ldr r2,[r1,#0x40]
- str r2,[r0,#0x28]
+ ldr r2,[r1,#0x40]
+ str r2,[r0,#0x28]
+
+ LED 6
- LED 6
-
- swi // switch to supervisor mode
-#endif
+ swi // switch to supervisor mode
+#endif
// =========================================================================
// Real startup code. We jump here from the reset vector to set up the world.
- .globl start
-start:
+ .globl start
+start:
- LED 5
+ LED 5
#if defined(CYG_HAL_STARTUP_RAM) && \
!defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
// If we get restarted, hang here to avoid corrupting memory
- ldr r0,.init_flag
- ldr r1,[r0]
+ ldr r0,.init_flag
+ ldr r1,[r0]
1: cmp r1,#0
- bne 1b
- ldr r1,init_done
- str r1,[r0]
+ bne 1b
+ ldr r1,init_done
+ str r1,[r0]
#endif
- // Reset software interrupt pointer
- mov r0,#0 // move vectors
- ldr r1,.__exception_handlers
+ // Reset software interrupt pointer
+ mov r0,#0 // move vectors
+ ldr r1,.__exception_handlers
#if defined(CYG_HAL_STARTUP_RAM) && \
!defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
- cmp r7,#CPSR_SUPERVISOR_MODE
- beq 10f
+ cmp r7,#CPSR_SUPERVISOR_MODE
+ beq 10f
#endif
- ldr r2,[r1,#0x28] // software interrupt
- str r2,[r0,#0x28]
+ ldr r2,[r1,#0x28] // software interrupt
+ str r2,[r0,#0x28]
10:
- ldr r2,[r1,#0x18] // IRQ
- str r2,[r0,#0x18]
- ldr r2,[r1,#0x38]
- str r2,[r0,#0x38]
- ldr r2,[r1,#0x1C] // FIQ
- str r2,[r0,#0x1C]
- ldr r2,[r1,#0x3C]
- str r2,[r0,#0x3C]
- ldr r2,[r1,#0x0C] // abort (prefetch)
- str r2,[r0,#0x0C]
- ldr r2,[r1,#0x2C]
- str r2,[r0,#0x2C]
- ldr r2,[r1,#0x10] // abort (data)
- str r2,[r0,#0x10]
- ldr r2,[r1,#0x30]
- str r2,[r0,#0x30]
-
- LED 4
+ ldr r2,[r1,#0x18] // IRQ
+ str r2,[r0,#0x18]
+ ldr r2,[r1,#0x38]
+ str r2,[r0,#0x38]
+ ldr r2,[r1,#0x1C] // FIQ
+ str r2,[r0,#0x1C]
+ ldr r2,[r1,#0x3C]
+ str r2,[r0,#0x3C]
+ ldr r2,[r1,#0x0C] // abort (prefetch)
+ str r2,[r0,#0x0C]
+ ldr r2,[r1,#0x2C]
+ str r2,[r0,#0x2C]
+ ldr r2,[r1,#0x10] // abort (data)
+ str r2,[r0,#0x10]
+ ldr r2,[r1,#0x30]
+ str r2,[r0,#0x30]
+
+ LED 4
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
- // Set up reset vector
- mov r0,#0
- ldr r1,.__exception_handlers
- ldr r2,[r1,#0x00] // reset vector intstruction
- str r2,[r0,#0x00]
- ldr r2,=warm_reset
- str r2,[r0,#0x20]
- // Relocate [copy] data from ROM to RAM
- ldr r3,.__rom_data_start
- ldr r4,.__ram_data_start
- ldr r5,.__ram_data_end
- cmp r4,r5 // jump if no data to move
- beq 2f
- sub r3,r3,#4 // loop adjustments
- sub r4,r4,#4
+ // Set up reset vector
+ mov r0,#0
+ ldr r1,.__exception_handlers
+ ldr r2,[r1,#0x00] // reset vector intstruction
+ str r2,[r0,#0x00]
+ ldr r2,=warm_reset
+ str r2,[r0,#0x20]
+ // Relocate [copy] data from ROM to RAM
+ ldr r3,.__rom_data_start
+ ldr r4,.__ram_data_start
+ ldr r5,.__ram_data_end
+ cmp r4,r5 // jump if no data to move
+ beq 2f
+ sub r3,r3,#4 // loop adjustments
+ sub r4,r4,#4
1: ldr r0,[r3,#4]! // copy info
- str r0,[r4,#4]!
- cmp r4,r5
- bne 1b
+ str r0,[r4,#4]!
+ cmp r4,r5
+ bne 1b
2:
#endif
- // initialize interrupt/exception environments
- ldr sp,.__startup_stack
- mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_IRQ_MODE)
- msr cpsr,r0
- ldr sp,.__exception_stack
- mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_UNDEF_MODE)
- msr cpsr,r0
- ldr sp,.__exception_stack
+ // initialize interrupt/exception environments
+ ldr sp,.__startup_stack
+ mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_IRQ_MODE)
+ msr cpsr,r0
+ ldr sp,.__exception_stack
+ mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_UNDEF_MODE)
+ msr cpsr,r0
+ ldr sp,.__exception_stack
- // initialize CPSR (machine state register)
- mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
- msr cpsr,r0
+ // initialize CPSR (machine state register)
+ mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
+ msr cpsr,r0
- // Note: some functions in LIBGCC1 will cause a "restore from SPSR"!!
- msr spsr,r0
+ // Note: some functions in LIBGCC1 will cause a "restore from SPSR"!!
+ msr spsr,r0
- // initialize stack
+ // initialize stack
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
- // use interrupt stack for system initialization since it's bigger
- // than the "startup" stack in this configuration
- ldr sp,.__interrupt_stack
-#else
- ldr sp,.__startup_stack
-#endif
-
- // clear BSS
- ldr r1,.__bss_start
- ldr r2,.__bss_end
- mov r0,#0
- cmp r1,r2
- beq 2f
+ // use interrupt stack for system initialization since it's bigger
+ // than the "startup" stack in this configuration
+ ldr sp,.__interrupt_stack
+#else
+ ldr sp,.__startup_stack
+#endif
+
+ // clear BSS
+ ldr r1,.__bss_start
+ ldr r2,.__bss_end
+ mov r0,#0
+ cmp r1,r2
+ beq 2f
1: str r0,[r1],#4
- cmp r1,r2
- bls 1b
+ cmp r1,r2
+ bls 1b
2:
- // Run kernel + application in THUMB mode
- THUMB_MODE(r1,10)
+ // Run kernel + application in THUMB mode
+ THUMB_MODE(r1,10)
+
+ LED 3
- LED 3
-
- // Call platform specific hardware initialization
- bl hal_hardware_init
+ // Call platform specific hardware initialization
+ bl hal_hardware_init
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
- bl initialize_stub
+ bl initialize_stub
- // Now that stub is initialized, change vector. It is possible
- // to single-step through most of the init code, except the below.
- // Put a breakpoint at the call to cyg_hal_invoke_constructors to
- // pass over this bit (s-s depends on internal state in the stub).
+ // Now that stub is initialized, change vector. It is possible
+ // to single-step through most of the init code, except the below.
+ // Put a breakpoint at the call to cyg_hal_invoke_constructors to
+ // pass over this bit (s-s depends on internal state in the stub).
#endif
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) || \
defined(CYGIMP_HAL_PROCESS_ALL_EXCEPTIONS)
- mov r0,#0 // move vectors
- ldr r1,=__exception_handlers
- ldr r2,[r1,#0x04] // undefined instruction
- str r2,[r0,#0x04]
- ldr r2,[r1,#0x24]
- str r2,[r0,#0x24]
+ mov r0,#0 // move vectors
+ ldr r1,=__exception_handlers
+ ldr r2,[r1,#0x04] // undefined instruction
+ str r2,[r0,#0x04]
+ ldr r2,[r1,#0x24]
+ str r2,[r0,#0x24]
#endif
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
|| defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
- .extern hal_ctrlc_isr_init
- bl hal_ctrlc_isr_init
+ .extern hal_ctrlc_isr_init
+ bl hal_ctrlc_isr_init
#endif
- LED 2
-
- // Run through static constructors
- bl cyg_hal_invoke_constructors
+ LED 2
+
+ // Run through static constructors
+ bl cyg_hal_invoke_constructors
- LED 1
-
- // This starts up the eCos kernel
+ LED 1
+
+ // This starts up the eCos kernel
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
- ldr r1,=__startup_stack
- mov sp,r1
-#endif
- bl cyg_start
+ ldr r1,=__startup_stack
+ mov sp,r1
+#endif
+ bl cyg_start
_start_hang:
- b _start_hang
- .code 32
-
- .global reset_platform
- .type reset_platform,function
-reset_platform:
+ b _start_hang
+ .code 32
+
+ .global reset_platform
+ .type reset_platform,function
+reset_platform:
#ifdef CYGSEM_HAL_ROM_MONITOR
- // initialize CPSR (machine state register)
- mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
- msr cpsr,r0
- b warm_reset
+ // initialize CPSR (machine state register)
+ mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
+ msr cpsr,r0
+ b warm_reset
#else
- mov r0,#0
- mov pc,r0 // Jump to reset vector
-#endif
+ mov r0,#0
+ mov pc,r0 // Jump to reset vector
+#endif
init_done:
- .long 0xDEADB00B
+ .long 0xDEADB00B
//
// Exception handlers
// except in case of standalone app. running in user mode
// (CYGOPT_HAL_ARM_WITH_USER_MODE should have been defined)
//
- .code 32
+ .code 32
undefined_instruction:
- ldr sp,.__undef_exception_stack // get good stack
- stmfd sp!,{r0-r5} // save some supervisor regs
- mrs r1,spsr
- tst r1,#CPSR_THUMB_ENABLE
- subeq r0,lr,#4 // PC at time of interrupt (ARM)
- subne r0,lr,#2 // PC at time of interrupt (thumb)
- mov r2,#CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION
- mov r3,sp
- b call_exception_handler
-
- .code 32
+ ldr sp,.__undef_exception_stack // get good stack
+ stmfd sp!,{r0-r5} // save some supervisor regs
+ mrs r1,spsr
+ tst r1,#CPSR_THUMB_ENABLE
+ subeq r0,lr,#4 // PC at time of interrupt (ARM)
+ subne r0,lr,#2 // PC at time of interrupt (thumb)
+ mov r2,#CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION
+ mov r3,sp
+ b call_exception_handler
+
+ .code 32
software_interrupt:
- stmfd sp!,{r8}
- ldr r8,.__undef_exception_stack // get good stack
- stmfd r8!,{r0-r5} // save some supervisor regs
- mov r3,r8
- ldmfd sp!,{r8}
- mrs r1,spsr
- tst r1,#CPSR_THUMB_ENABLE
- subeq r0,lr,#4 // PC at time of SWI (ARM)
- subne r0,lr,#2 // PC at time of SWI (thumb)
- mov r2,#CYGNUM_HAL_EXCEPTION_INTERRUPT
- b call_exception_handler
-
- .code 32
+ stmfd sp!,{r8}
+ ldr r8,.__undef_exception_stack // get good stack
+ stmfd r8!,{r0-r5} // save some supervisor regs
+ mov r3,r8
+ ldmfd sp!,{r8}
+ mrs r1,spsr
+ tst r1,#CPSR_THUMB_ENABLE
+ subeq r0,lr,#4 // PC at time of SWI (ARM)
+ subne r0,lr,#2 // PC at time of SWI (thumb)
+ mov r2,#CYGNUM_HAL_EXCEPTION_INTERRUPT
+ b call_exception_handler
+
+ .code 32
abort_prefetch:
- ldr sp,.__undef_exception_stack // get good stack
- stmfd sp!,{r0-r5} // save some supervisor regs
- sub r0,lr,#4 // PC at time of interrupt
- mrs r1,spsr
- mov r2,#CYGNUM_HAL_EXCEPTION_CODE_ACCESS
- mov r3,sp
- b call_exception_handler
-
- .code 32
+ ldr sp,.__undef_exception_stack // get good stack
+ stmfd sp!,{r0-r5} // save some supervisor regs
+ sub r0,lr,#4 // PC at time of interrupt
+ mrs r1,spsr
+ mov r2,#CYGNUM_HAL_EXCEPTION_CODE_ACCESS
+ mov r3,sp
+ b call_exception_handler
+
+ .code 32
abort_data:
- ldr sp,.__undef_exception_stack // get good stack
- stmfd sp!,{r0-r5} // save some supervisor regs
- sub r0,lr,#4 // PC at time of interrupt
- mrs r1,spsr
- mov r2,#CYGNUM_HAL_EXCEPTION_DATA_ACCESS
- mov r3,sp
- b call_exception_handler
-
+ ldr sp,.__undef_exception_stack // get good stack
+ stmfd sp!,{r0-r5} // save some supervisor regs
+ sub r0,lr,#4 // PC at time of interrupt
+ mrs r1,spsr
+ mov r2,#CYGNUM_HAL_EXCEPTION_DATA_ACCESS
+ mov r3,sp
+ b call_exception_handler
+
//
// Dispatch an exception handler.
- .code 32
+ .code 32
call_exception_handler:
- //
- // On Entry:
- //
- // r4,r5 = scratch
- // r3 = pointer to temp save area
- // r2 = vector number
- // r1 = exception psr
- // r0 = exception pc
- //
- // [r3+20]: exception r5
- // [r3+16]: exception r4
- // [r3+12]: exception r3
- // [r3+8] : exception r2
- // [r3+4] : exception r1
- // [r3] : exception r0
-
- mrs r4,cpsr // switch to Supervisor Mode
- bic r4,r4,#CPSR_MODE_BITS
- orr r4,r4,#CPSR_SUPERVISOR_MODE
- msr cpsr,r4
-
- mov r5,sp // save original svc sp
- mov r4,lr // and original svc lr
+ //
+ // On Entry:
+ //
+ // r4,r5 = scratch
+ // r3 = pointer to temp save area
+ // r2 = vector number
+ // r1 = exception psr
+ // r0 = exception pc
+ //
+ // [r3+20]: exception r5
+ // [r3+16]: exception r4
+ // [r3+12]: exception r3
+ // [r3+8] : exception r2
+ // [r3+4] : exception r1
+ // [r3] : exception r0
+
+ mrs r4,cpsr // switch to Supervisor Mode
+ bic r4,r4,#CPSR_MODE_BITS
+ orr r4,r4,#CPSR_SUPERVISOR_MODE
+ msr cpsr,r4
+
+ mov r5,sp // save original svc sp
+ mov r4,lr // and original svc lr
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
- // Make sure we use the GDB stack.
- ldr sp,.__GDB_stack
- cmp r5,sp // already on GDB stack?
- bhi 10f
- ldr r4,.__GDB_stack_base
- cmp r5,r4
- movhi sp,r5
+ // Make sure we use the GDB stack.
+ ldr sp,.__GDB_stack
+ cmp r5,sp // already on GDB stack?
+ bhi 10f
+ ldr r4,.__GDB_stack_base
+ cmp r5,r4
+ movhi sp,r5
10:
#endif
- //
- // r5 holds original svc sp, current sp is stack to use
- // r4 holds original svc lr, which must also be preserved
- //
+ //
+ // r5 holds original svc sp, current sp is stack to use
+ // r4 holds original svc lr, which must also be preserved
+ //
+
+ stmfd sp!,{r0-r2,r4,r5} // push svc_sp, svc_lr, vector, psr, pc
- stmfd sp!,{r0-r2,r4,r5} // push svc_sp, svc_lr, vector, psr, pc
-
#ifdef CYGOPT_HAL_ARM_WITH_USER_MODE
- // did exception occur in user mode ?
- and r2, r1, #CPSR_MODE_BITS
- cmp r2, #CPSR_USER_MODE
- bne 1f
- stmfd sp, {r8-r12, sp, lr}^ // get user mode regs
+ // did exception occur in user mode ?
+ and r2, r1, #CPSR_MODE_BITS
+ cmp r2, #CPSR_USER_MODE
+ bne 1f
+ stmfd sp, {r8-r12, sp, lr}^ // get user mode regs
nop
- sub sp, sp, #4*7
- bal 2f
+ sub sp, sp, #4*7
+ bal 2f
1:
#endif
- // switch to pre-exception mode to get banked regs
- mov r0,sp // r0 survives mode switch
- mrs r2,cpsr // Save current psr for return
- orr r1,r1,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
- bic r1,r1,#CPSR_THUMB_ENABLE
- msr cpsr,r1
- stmfd r0!,{r8-r12,sp,lr}
- msr cpsr,r2 // back to svc mode
- mov sp,r0 // update stack pointer
+ // switch to pre-exception mode to get banked regs
+ mov r0,sp // r0 survives mode switch
+ mrs r2,cpsr // Save current psr for return
+ orr r1,r1,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
+ bic r1,r1,#CPSR_THUMB_ENABLE
+ msr cpsr,r1
+ stmfd r0!,{r8-r12,sp,lr}
+ msr cpsr,r2 // back to svc mode
+ mov sp,r0 // update stack pointer
2:
- // now save pre-exception r0-r7 on current stack
- ldmfd r3,{r0-r5}
- stmfd sp!,{r0-r7}
-
- // SP needs fixing if exception occured in SVC mode.
- // The original SVC LR is still in place so that
- // does not need to be fixed here.
- ldr r1,[sp,#armreg_cpsr]
- and r1,r1,#CPSR_MODE_BITS
- cmp r1,#CPSR_SUPERVISOR_MODE
- ldreq r1,[sp,#armreg_svcsp]
- streq r1,[sp,#armreg_sp]
+ // now save pre-exception r0-r7 on current stack
+ ldmfd r3,{r0-r5}
+ stmfd sp!,{r0-r7}
+
+ // SP needs fixing if exception occured in SVC mode.
+ // The original SVC LR is still in place so that
+ // does not need to be fixed here.
+ ldr r1,[sp,#armreg_cpsr]
+ and r1,r1,#CPSR_MODE_BITS
+ cmp r1,#CPSR_SUPERVISOR_MODE
+ ldreq r1,[sp,#armreg_svcsp]
+ streq r1,[sp,#armreg_sp]
#ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS
- mov r0,sp
- ldr r1,.__dump_procs
- ldr r2,[sp,#armreg_vector]
- ldr r1,[r1,r2,lsl #2]
- THUMB_MODE(r9,10)
- mov lr,pc
- mov pc,r1
+ mov r0,sp
+ ldr r1,.__dump_procs
+ ldr r2,[sp,#armreg_vector]
+ ldr r1,[r1,r2,lsl #2]
+ THUMB_MODE(r9,10)
+ mov lr,pc
+ mov pc,r1
#else
- THUMB_MODE(r9,10)
+ THUMB_MODE(r9,10)
#endif
- // call exception handler
- mov r0,sp
- bl exception_handler
+ // call exception handler
+ mov r0,sp
+ bl exception_handler
#ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS
- mov r0,sp
- bl cyg_hal_report_exception_handler_returned
+ mov r0,sp
+ bl cyg_hal_report_exception_handler_returned
#endif
- ARM_MODE(r1,10)
+ ARM_MODE(r1,10)
- //
- // Return from exception
- //
+ //
+ // Return from exception
+ //
return_from_exception:
- ldr r0,[sp,#armreg_cpsr]
+ ldr r0,[sp,#armreg_cpsr]
- // return to supervisor mode is simple
- and r1,r0,#CPSR_MODE_BITS
- cmp r1,#CPSR_SUPERVISOR_MODE
+ // return to supervisor mode is simple
+ and r1,r0,#CPSR_MODE_BITS
+ cmp r1,#CPSR_SUPERVISOR_MODE
#ifndef CYGOPT_HAL_ARM_PRESERVE_SVC_SPSR
- msr spsr,r0
- ldmeqfd sp,{r0-r14,pc}^
+ msr spsr,r0
+ ldmeqfd sp,{r0-r14,pc}^
#else
- // we must take care of not corrupting the current (svc)
- // spsr which happens to be also the pre-exception spsr
- bne 1f
- tst r0, #CPSR_THUMB_ENABLE
-
- // when returning to thumb/svc mode, there is no easy way to preserve
- // spsr. It is possible to do so, but would add a lot of instructions.
- // The purpose of CYGOPT_HAL_ARM_PRESERVE_SVC_SPSR is to allow stepping
- // through SWI exception handling code, so not preserving spsr in this
- // case should be okay.
- msrne spsr,r0
- ldmnefd sp,{r0-r14,pc}^
-
- // we are returning to arm/svc mode thus we must restore the
- // pre-exception cpsr before returning to interrupted code
- msr cpsr, r0
- ldmfd sp, {r0-r14, pc}
+ // we must take care of not corrupting the current (svc)
+ // spsr which happens to be also the pre-exception spsr
+ bne 1f
+ tst r0, #CPSR_THUMB_ENABLE
+
+ // when returning to thumb/svc mode, there is no easy way to preserve
+ // spsr. It is possible to do so, but would add a lot of instructions.
+ // The purpose of CYGOPT_HAL_ARM_PRESERVE_SVC_SPSR is to allow stepping
+ // through SWI exception handling code, so not preserving spsr in this
+ // case should be okay.
+ msrne spsr,r0
+ ldmnefd sp,{r0-r14,pc}^
+
+ // we are returning to arm/svc mode thus we must restore the
+ // pre-exception cpsr before returning to interrupted code
+ msr cpsr, r0
+ ldmfd sp, {r0-r14, pc}
1:
- // we are not returning to svc mode thus we can safely restore
- // svc spsr
- msr spsr, r0
+ // we are not returning to svc mode thus we can safely restore
+ // svc spsr
+ msr spsr, r0
#endif
#ifdef CYGOPT_HAL_ARM_WITH_USER_MODE
- // are we returning to user mode ?
- and r2, r1, #CPSR_MODE_BITS
- cmp r2, #CPSR_USER_MODE
- add r2, sp, #armreg_r8
- bne 1f
- ldmfd r2, {r8-r14}^ // restore user mode regs
+ // are we returning to user mode ?
+ and r2, r1, #CPSR_MODE_BITS
+ cmp r2, #CPSR_USER_MODE
+ add r2, sp, #armreg_r8
+ bne 1f
+ ldmfd r2, {r8-r14}^ // restore user mode regs
nop
- bal 2f
+ bal 2f
1:
#else
- add r2, sp, #armreg_r8
+ add r2, sp, #armreg_r8
#endif
- //
- // return to other non-user modes is a little trickier
- //
-
- // switch to pre-exception mode and restore r8-r14
- mrs r1,cpsr
- orr r0,r0,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
- bic r0,r0,#CPSR_THUMB_ENABLE
- msr cpsr,r0
- ldmfd r2,{r8-r14}
- msr cpsr, r1 // back to svc mode
-
-2:
- // move sp,lr and pc for final load
- ldr r0,[sp,#armreg_svcsp]
- str r0,[sp,#armreg_r8]
- ldr r0,[sp,#armreg_svclr]
- str r0,[sp,#armreg_r9]
- ldr r0,[sp,#armreg_pc]
- str r0,[sp,#armreg_r10]
-
- // restore r0-r7,sp,lr and return from exception
- ldmfd sp,{r0-r7,sp,lr,pc}^
+ //
+ // return to other non-user modes is a little trickier
+ //
+
+ // switch to pre-exception mode and restore r8-r14
+ mrs r1,cpsr
+ orr r0,r0,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
+ bic r0,r0,#CPSR_THUMB_ENABLE
+ msr cpsr,r0
+ ldmfd r2,{r8-r14}
+ msr cpsr, r1 // back to svc mode
+
+2:
+ // move sp,lr and pc for final load
+ ldr r0,[sp,#armreg_svcsp]
+ str r0,[sp,#armreg_r8]
+ ldr r0,[sp,#armreg_svclr]
+ str r0,[sp,#armreg_r9]
+ ldr r0,[sp,#armreg_pc]
+ str r0,[sp,#armreg_r10]
+
+ // restore r0-r7,sp,lr and return from exception
+ ldmfd sp,{r0-r7,sp,lr,pc}^
#ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS
__dump_procs:
- .word 0 // placeholder for reset
- .word cyg_hal_report_undefined_instruction
- .word cyg_hal_report_software_interrupt
- .word cyg_hal_report_abort_prefetch
- .word cyg_hal_report_abort_data
- .word 0 // reserved
+ .word 0 // placeholder for reset
+ .word cyg_hal_report_undefined_instruction
+ .word cyg_hal_report_software_interrupt
+ .word cyg_hal_report_abort_prefetch
+ .word cyg_hal_report_abort_data
+ .word 0 // reserved
#endif
// Assumption: can get here from any mode, including user mode
// (spurious interrupt while standalone app. is running in user mode)
- .code 32
+ .code 32
FIQ:
- // We can get here from any non-user mode.
- mrs r8,spsr // CPSR at time of interrupt
- and r9,r8,#CPSR_MODE_BITS // isolate pre-interrupt mode
- cmp r9,#CPSR_IRQ_MODE
- bne 1f
- // If FIQ interrupted IRQ mode, just return with FIQ disabled.
- // The common interrupt handling takes care of the rest.
- orr r8,r8,#CPSR_FIQ_DISABLE
- msr spsr,r8
- subs pc,lr,#4
+ // We can get here from any non-user mode.
+ mrs r8,spsr // CPSR at time of interrupt
+ and r9,r8,#CPSR_MODE_BITS // isolate pre-interrupt mode
+ cmp r9,#CPSR_IRQ_MODE
+ bne 1f
+ // If FIQ interrupted IRQ mode, just return with FIQ disabled.
+ // The common interrupt handling takes care of the rest.
+ orr r8,r8,#CPSR_FIQ_DISABLE
+ msr spsr,r8
+ subs pc,lr,#4
1:
- // If FIQ interrupted other non-user mode, switch to IRQ mode and
- // fall through to IRQ handler.
- ldr sp,.__exception_stack // get good stack to save lr and spsr
- stmdb sp,{r8,lr}
- mov r8,#CPSR_IRQ_MODE|CPSR_FIQ_DISABLE|CPSR_IRQ_DISABLE
- msr cpsr,r8 // switch to IRQ mode
- ldr sp,.__exception_stack // get regs saved in FIQ mode
- ldmdb sp,{sp,lr}
- msr spsr,sp
-
- // now it looks like we got an IRQ instead of an FIQ except that
- // FIQ is disabled so we don't recurse.
+ // If FIQ interrupted other non-user mode, switch to IRQ mode and
+ // fall through to IRQ handler.
+ ldr sp,.__exception_stack // get good stack to save lr and spsr
+ stmdb sp,{r8,lr}
+ mov r8,#CPSR_IRQ_MODE|CPSR_FIQ_DISABLE|CPSR_IRQ_DISABLE
+ msr cpsr,r8 // switch to IRQ mode
+ ldr sp,.__exception_stack // get regs saved in FIQ mode
+ ldmdb sp,{sp,lr}
+ msr spsr,sp
+
+ // now it looks like we got an IRQ instead of an FIQ except that
+ // FIQ is disabled so we don't recurse.
IRQ:
- // Note: I use this exception stack while saving the context because
- // the current SP does not seem to be always valid in this CPU mode.
- ldr sp,.__exception_stack // get good stack
- stmfd sp!,{r0-r5} // save some supervisor regs
- sub r0,lr,#4 // PC at time of interrupt
- mrs r1,spsr
- mov r2,#CYGNUM_HAL_VECTOR_IRQ
- mov r3,sp
-
-handle_IRQ_or_FIQ:
-
- mrs r4,cpsr // switch to Supervisor Mode
- bic r4,r4,#CPSR_MODE_BITS
- orr r4,r4,#CPSR_SUPERVISOR_MODE
- msr cpsr,r4
-
- mov r5,sp // save original svc sp
+ // Note: I use this exception stack while saving the context because
+ // the current SP does not seem to be always valid in this CPU mode.
+ ldr sp,.__exception_stack // get good stack
+ stmfd sp!,{r0-r5} // save some supervisor regs
+ sub r0,lr,#4 // PC at time of interrupt
+ mrs r1,spsr
+ mov r2,#CYGNUM_HAL_VECTOR_IRQ
+ mov r3,sp
+
+ mrs r4,cpsr // switch to Supervisor Mode
+ bic r4,r4,#CPSR_MODE_BITS
+ // When handling an IRQ we must disable FIQ unless the current
+ // mode in CPSR is IRQ. If we were to get a FIQ while in another
+ // mode, the FIQ handling code would transform the FIQ into an
+ // IRQ and call the non-reentrant IRQ handler again. As a result,
+ // for example, the stack pointer would be set to the beginning
+ // of the exception_stack clobbering the registers we have just
+ // saved.
+ orr r4,r4,#CPSR_SUPERVISOR_MODE|CPSR_FIQ_DISABLE
+ msr cpsr,r4
+
+ mov r5,sp // save original svc sp
mov r4,lr // save original svc lr
- stmfd sp!,{r0-r2,r4,r5} // push svc_sp, svc_lr, vector, psr, pc
-
+ stmfd sp!,{r0-r2,r4,r5} // push svc_sp, svc_lr, vector, psr, pc
+
#ifdef CYGOPT_HAL_ARM_WITH_USER_MODE
- // did exception occur in user mode ?
- and r2, r1, #CPSR_MODE_BITS
- cmp r2, #CPSR_USER_MODE
- bne 1f
- stmfd sp, {r8-r12, sp, lr}^ // get user mode regs
+ // did exception occur in user mode ?
+ and r2, r1, #CPSR_MODE_BITS
+ cmp r2, #CPSR_USER_MODE
+ bne 1f
+ stmfd sp, {r8-r12, sp, lr}^ // get user mode regs
nop
- sub sp, sp, #4*7
- bal 2f
+ sub sp, sp, #4*7
+ bal 2f
1:
#endif
- // switch to pre-exception mode to get banked regs
- mov r0,sp // r0 survives mode switch
- mrs r2,cpsr // Save current psr for return
- orr r1,r1,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
- bic r1,r1,#CPSR_THUMB_ENABLE
- msr cpsr,r1
- stmfd r0!,{r8-r12,sp,lr}
- msr cpsr,r2 // back to svc mode
- mov sp,r0 // update stack pointer
-
+ // switch to pre-exception mode to get banked regs
+ mov r0,sp // r0 survives mode switch
+ mrs r2,cpsr // Save current psr for return
+ orr r1,r1,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
+ bic r1,r1,#CPSR_THUMB_ENABLE
+ msr cpsr,r1
+ stmfd r0!,{r8-r12,sp,lr}
+ msr cpsr,r2 // back to svc mode
+ mov sp,r0 // update stack pointer
+
2:
- // now save pre-exception r0-r7 on current stack
- ldmfd r3,{r0-r5}
- stmfd sp!,{r0-r7}
+ // now save pre-exception r0-r7 on current stack
+ ldmfd r3,{r0-r5}
+ stmfd sp!,{r0-r7}
- // sp needs fixing if exception occured in SVC mode.
- ldr r1,[sp,#armreg_cpsr]
- and r1,r1,#CPSR_MODE_BITS
- cmp r1,#CPSR_SUPERVISOR_MODE
- ldreq r1,[sp,#armreg_svcsp]
- streq r1,[sp,#armreg_sp]
+ // sp needs fixing if exception occured in SVC mode.
+ ldr r1,[sp,#armreg_cpsr]
+ and r1,r1,#CPSR_MODE_BITS
+ cmp r1,#CPSR_SUPERVISOR_MODE
+ ldreq r1,[sp,#armreg_svcsp]
+ streq r1,[sp,#armreg_sp]
- mov v6,sp // Save pointer to register frame
+ mov v6,sp // Save pointer to register frame
// mov r0,sp
// bl _show_frame_in
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
- // Switch to interrupt stack
- ldr r2,.irq_level // current number of nested interrupts
- ldr r0,[r2]
- add r1,r0,#1
- str r1,[r2] // if was zero, switch stacks
- cmp r0,#0
- moveq r1,sp // save old stack pointer
- ldreq sp,.__interrupt_stack
- stmeqfd sp!,{r1}
+ // Switch to interrupt stack
+ ldr r2,.irq_level // current number of nested interrupts
+ ldr r0,[r2]
+ add r1,r0,#1
+ str r1,[r2] // if was zero, switch stacks
+ cmp r0,#0
+ moveq r1,sp // save old stack pointer
+ ldreq sp,.__interrupt_stack
+ stmeqfd sp!,{r1}
10:
#endif
- // The entire CPU state is now stashed on the stack,
- // increment the scheduler lock and handle the interrupt
+ // The entire CPU state is now stashed on the stack,
+ // increment the scheduler lock and handle the interrupt
-#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
- .extern cyg_scheduler_sched_lock
- ldr r3,.cyg_scheduler_sched_lock
- ldr r4,[r3]
- add r4,r4,#1
- str r4,[r3]
+#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
+ .extern cyg_scheduler_sched_lock
+ ldr r3,.cyg_scheduler_sched_lock
+ ldr r4,[r3]
+ add r4,r4,#1
+ str r4,[r3]
#endif
- THUMB_MODE(r3,10)
+ THUMB_MODE(r3,10)
- mov r0,v6
- bl hal_IRQ_handler // determine interrupt source
- mov v1,r0 // returned vector #
+ mov r0,v6
+ bl hal_IRQ_handler // determine interrupt source
+ mov v1,r0 // returned vector #
#if defined(CYGPKG_KERNEL_INSTRUMENT) && \
defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
- ldr r0,=RAISE_INTR // arg0 = type = INTR,RAISE
- mov r1,v1 // arg1 = vector
- mov r2,#0 // arg2 = 0
- bl cyg_instrument // call instrument function
+ ldr r0,=RAISE_INTR // arg0 = type = INTR,RAISE
+ mov r1,v1 // arg1 = vector
+ mov r2,#0 // arg2 = 0
+ bl cyg_instrument // call instrument function
#endif
- ARM_MODE(r0,10)
+ ARM_MODE(r0,10)
- mov r0,v1 // vector #
+ mov r0,v1 // vector #
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
|| defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
- // If we are supporting Ctrl-C interrupts from GDB, we must squirrel
- // away a pointer to the save interrupt state here so that we can
- // plant a breakpoint at some later time.
+ // If we are supporting Ctrl-C interrupts from GDB, we must squirrel
+ // away a pointer to the save interrupt state here so that we can
+ // plant a breakpoint at some later time.
.extern hal_saved_interrupt_state
- ldr r2,=hal_saved_interrupt_state
- str v6,[r2]
+ ldr r2,=hal_saved_interrupt_state
+ str v6,[r2]
#endif
- cmp r0,#CYGNUM_HAL_INTERRUPT_NONE // spurious interrupt
- bne 10f
+ cmp r0,#CYGNUM_HAL_INTERRUPT_NONE // spurious interrupt
+ bne 10f
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS
- // Acknowledge the interrupt
- THUMB_CALL(r1,12,hal_interrupt_acknowledge)
+ // Acknowledge the interrupt
+ THUMB_CALL(r1,12,hal_interrupt_acknowledge)
#else
- mov r0,v6 // register frame
- THUMB_CALL(r1,12,hal_spurious_IRQ)
+ mov r0,v6 // register frame
+ THUMB_CALL(r1,12,hal_spurious_IRQ)
#endif // CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS
- b spurious_IRQ
-
+ b spurious_IRQ
+
10: ldr r1,.hal_interrupt_data
- ldr r1,[r1,v1,lsl #2] // handler data
- ldr r2,.hal_interrupt_handlers
- ldr v3,[r2,v1,lsl #2] // handler (indexed by vector #)
- mov r2,v6 // register frame (this is necessary
- // for the ISR too, for ^C detection)
+ ldr r1,[r1,v1,lsl #2] // handler data
+ ldr r2,.hal_interrupt_handlers
+ ldr v3,[r2,v1,lsl #2] // handler (indexed by vector #)
+ mov r2,v6 // register frame (this is necessary
+ // for the ISR too, for ^C detection)
#ifdef __thumb__
- ldr lr,=10f
- bx v3 // invoke handler (thumb mode)
- .pool
- .code 16
- .thumb_func
+ ldr lr,=10f
+ bx v3 // invoke handler (thumb mode)
+ .pool
+ .code 16
+ .thumb_func
IRQ_10T:
10: ldr r2,=15f
- bx r2 // switch back to ARM mode
- .pool
- .code 32
+ bx r2 // switch back to ARM mode
+ .pool
+ .code 32
15:
IRQ_15A:
#else
- mov lr,pc // invoke handler (call indirect
- mov pc,v3 // thru v3)
+ mov lr,pc // invoke handler (call indirect
+ mov pc,v3 // thru v3)
#endif
-spurious_IRQ:
+spurious_IRQ:
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
- // If we are returning from the last nested interrupt, move back
- // to the thread stack. interrupt_end() must be called on the
- // thread stack since it potentially causes a context switch.
- ldr r2,.irq_level
- ldr r3,[r2]
- subs r1,r3,#1
- str r1,[r2]
- ldreq sp,[sp] // This should be the saved stack pointer
+ // If we are returning from the last nested interrupt, move back
+ // to the thread stack. interrupt_end() must be called on the
+ // thread stack since it potentially causes a context switch.
+ ldr r2,.irq_level
+ ldr r3,[r2]
+ subs r1,r3,#1
+ str r1,[r2]
+ ldreq sp,[sp] // This should be the saved stack pointer
#endif
- // The return value from the handler (in r0) will indicate whether a
- // DSR is to be posted. Pass this together with a pointer to the
- // interrupt object we have just used to the interrupt tidy up routine.
-
- // don't run this for spurious interrupts!
- cmp v1,#CYGNUM_HAL_INTERRUPT_NONE
- beq 17f
- ldr r1,.hal_interrupt_objects
- ldr r1,[r1,v1,lsl #2]
- mov r2,v6 // register frame
-
- THUMB_MODE(r3,10)
-
- bl interrupt_end // post any bottom layer handler
- // threads and call scheduler
- ARM_MODE(r1,10)
+ // The return value from the handler (in r0) will indicate whether a
+ // DSR is to be posted. Pass this together with a pointer to the
+ // interrupt object we have just used to the interrupt tidy up routine.
+
+ // don't run this for spurious interrupts!
+ cmp v1,#CYGNUM_HAL_INTERRUPT_NONE
+ beq 17f
+ ldr r1,.hal_interrupt_objects
+ ldr r1,[r1,v1,lsl #2]
+ mov r2,v6 // register frame
+
+ THUMB_MODE(r3,10)
+
+ bl interrupt_end // post any bottom layer handler
+ // threads and call scheduler
+ ARM_MODE(r1,10)
17:
// mov r0,sp
// Execute pending DSRs the interrupt stack
// Note: this can only be called from code running on a thread stack
FUNC_START_ARM(hal_interrupt_stack_call_pending_DSRs, r1)
- stmfd sp!,{r4,r5,lr}
- // Disable interrupts
- mrs r4,cpsr // disable IRQ's
- orr r2,r4,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
- bic r5,r4,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
- msr cpsr,r2
- // Switch to interrupt stack
- mov r3,sp // save old stack pointer
- ldr sp,.__interrupt_stack
- stmfd sp!,{r3} // stored at top of interrupt stack
- ldr r2,.irq_level // current number of nested interrupts
- ldr r3,[r2]
- add r3,r3,#1 // bump nesting level
- str r3,[r2]
- msr cpsr,r5 // enable interrupts
-
- THUMB_MODE(r1,20)
-
- bl cyg_interrupt_call_pending_DSRs
-
-
- ARM_MODE(r1,22)
-
- // Disable interrupts
- mrs r1,cpsr // disable IRQ's
- orr r2,r1,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
- msr cpsr,r2
-
- // Move back to the thread stack.
- ldr r2,.irq_level
- ldr r3,[r2]
- sub r3,r3,#1 // decrement nesting level
- str r3,[r2]
- ldr sp,[sp] // This should be the saved stack pointer
- msr cpsr,r4 // restore interrupts to original state
+ stmfd sp!,{r4,r5,lr}
+ // Disable interrupts
+ mrs r4,cpsr // disable IRQ's
+ orr r2,r4,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
+ bic r5,r4,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
+ msr cpsr,r2
+ // Switch to interrupt stack
+ mov r3,sp // save old stack pointer
+ ldr sp,.__interrupt_stack
+ stmfd sp!,{r3} // stored at top of interrupt stack
+ ldr r2,.irq_level // current number of nested interrupts
+ ldr r3,[r2]
+ add r3,r3,#1 // bump nesting level
+ str r3,[r2]
+ msr cpsr,r5 // enable interrupts
+
+ THUMB_MODE(r1,20)
+
+ bl cyg_interrupt_call_pending_DSRs
+
+
+ ARM_MODE(r1,22)
+
+ // Disable interrupts
+ mrs r1,cpsr // disable IRQ's
+ orr r2,r1,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
+ msr cpsr,r2
+
+ // Move back to the thread stack.
+ ldr r2,.irq_level
+ ldr r3,[r2]
+ sub r3,r3,#1 // decrement nesting level
+ str r3,[r2]
+ ldr sp,[sp] // This should be the saved stack pointer
+ msr cpsr,r4 // restore interrupts to original state
#ifdef __thumb__
- ldmfd sp!,{r4,r5,lr} // return
- bx lr
+ ldmfd sp!,{r4,r5,lr} // return
+ bx lr
#else
- ldmfd sp!,{r4,r5,pc} // return
+ ldmfd sp!,{r4,r5,pc} // return
#endif // __thumb__
#endif // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
-
+
// Thumb-only support functions
#ifdef __thumb__
FUNC_START_ARM(hal_disable_interrupts, r1)
- mrs r0,cpsr // current state
- orr r1,r0,#0xC0 // mask both FIQ and IRQ
- msr cpsr,r1
- bx lr // exit, _old_ in r0
+ mrs r0,cpsr // current state
+ orr r1,r0,#0xC0 // mask both FIQ and IRQ
+ msr cpsr,r1
+ bx lr // exit, _old_ in r0
FUNC_START_ARM(hal_enable_interrupts, r1)
- mrs r0,cpsr // current state
- bic r1,r0,#0xC0 // mask both FIQ and IRQ
- msr cpsr,r1
- bx lr // exit
-
+ mrs r0,cpsr // current state
+ bic r1,r0,#0xC0 // mask both FIQ and IRQ
+ msr cpsr,r1
+ bx lr // exit
+
FUNC_START_ARM(hal_restore_interrupts, r1)
- mrs r1,cpsr // current state
- bic r1,r1,#0xC0 // mask out FIQ/IRQ bits
- and r0,r0,#0xC0 // keep only FIQ/IRQ
- orr r1,r1,r0 // mask both FIQ and IRQ
- msr cpsr,r1
- bx lr // exit
+ mrs r1,cpsr // current state
+ bic r1,r1,#0xC0 // mask out FIQ/IRQ bits
+ and r0,r0,#0xC0 // keep only FIQ/IRQ
+ orr r1,r1,r0 // mask both FIQ and IRQ
+ msr cpsr,r1
+ bx lr // exit
FUNC_START_ARM(hal_query_interrupts, r1)
- mrs r0,cpsr // current state
- bx lr // exit, state in r0
+ mrs r0,cpsr // current state
+ bx lr // exit, state in r0
#endif // __thumb__
// Dummy/support functions
- .global __gccmain
- .global _psr
- .global _sp
+ .global __gccmain
+ .global _psr
+ .global _sp
#ifdef __thumb__
- .code 16
- .thumb_func
+ .code 16
+ .thumb_func
__gccmain:
- bx lr
+ bx lr
- .code 16
- .thumb_func
+ .code 16
+ .thumb_func
_psr:
- ARM_MODE(r1,10)
- mrs r0,cpsr
- bx lr
+ ARM_MODE(r1,10)
+ mrs r0,cpsr
+ bx lr
- .code 16
- .thumb_func
+ .code 16
+ .thumb_func
_sp:
- mov r0,sp
- bx lr
+ mov r0,sp
+ bx lr
#else
__gccmain:
- mov pc,lr
+ mov pc,lr
_psr:
- mrs r0,cpsr
- mov pc,lr
+ mrs r0,cpsr
+ mov pc,lr
_sp:
- mov r0,sp
- mov pc,lr
-#endif
+ mov r0,sp
+ mov pc,lr
+#endif
\f
//
//
// Identification - useful to find out when a system was configured
_eCos_id:
- .asciz "eCos : " __DATE__
+ .asciz "eCos : " __DATE__
\f
// -------------------------------------------------------------------------
// generated by magic without proper dependencies in arm.inc
// Recompiling will not DTRT without manual intervention.
- .data
+ .data
init_flag:
- .balign 4
- .long 0
+ .balign 4
+ .long 0
- .extern hal_default_isr
+ .extern hal_default_isr
- .globl hal_interrupt_handlers
+ .globl hal_interrupt_handlers
hal_interrupt_handlers:
- .rept CYGNUM_HAL_ISR_COUNT
- .long hal_default_isr
- .endr
+ .rept CYGNUM_HAL_ISR_COUNT
+ .long hal_default_isr
+ .endr
- .globl hal_interrupt_data
+ .globl hal_interrupt_data
hal_interrupt_data:
- .rept CYGNUM_HAL_ISR_COUNT
- .long 0
- .endr
+ .rept CYGNUM_HAL_ISR_COUNT
+ .long 0
+ .endr
- .globl hal_interrupt_objects
+ .globl hal_interrupt_objects
hal_interrupt_objects:
- .rept CYGNUM_HAL_ISR_COUNT
- .long 0
- .endr
+ .rept CYGNUM_HAL_ISR_COUNT
+ .long 0
+ .endr
// -------------------------------------------------------------------------
// Temporary interrupt stack
-
- .section ".bss"
+
+ .section ".bss"
// Small stacks, only used for saving information between CPU modes
-__exception_stack_base:
- .rept 32
- .long 0
- .endr
+__exception_stack_base:
+ .rept 32
+ .long 0
+ .endr
__exception_stack:
- .rept 32
- .long 0
- .endr
+ .rept 32
+ .long 0
+ .endr
__undef_exception_stack:
// Runtime stack used during all interrupt processing
#define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096
#endif
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
- .balign 16
- .global cyg_interrupt_stack_base
+ .balign 16
+ .global cyg_interrupt_stack_base
cyg_interrupt_stack_base:
__interrupt_stack_base:
- .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
- .byte 0
- .endr
- .balign 16
- .global cyg_interrupt_stack
+ .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+ .byte 0
+ .endr
+ .balign 16
+ .global cyg_interrupt_stack
cyg_interrupt_stack:
__interrupt_stack:
irq_level:
- .long 0
+ .long 0
#endif
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
- .balign 16
+ .balign 16
__GDB_stack_base:
- .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE // rather than 1k
- .byte 0
- .endr
+ .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE // rather than 1k
+ .byte 0
+ .endr
__GDB_stack:
#endif
- .balign 16
+ .balign 16
__startup_stack_base:
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
- .rept 512
+ .rept 512
#else
- .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+ .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
#endif
- .byte 0
- .endr
- .balign 16
+ .byte 0
+ .endr
+ .balign 16
__startup_stack:
#ifdef PLATFORM_EXTRAS
#include PLATFORM_EXTRAS
-#endif
+#endif
// --------------------------------------------------------------------------
// end of vectors.S
+2006-02-17 Tom Chase <tchase@dtccom.com>
+
+ * include/hal_cache.h: Added support for ARM926EJ. Changed
+ ARM925T to use CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_CACHE and defined
+ CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_CACHE to clean the cache manually
+ because CYGHWR_HAL_ARM_ARM9_CLEAN_CACHE did not work for the
+ OMAP1510.
+
+ * cdl/hal_arm_arm9.cdl: Added option for ARM926EJ.
+
2003-01-08 Patrick Doyle <wpd@delcomsys.com>
* include/hal_cache.h: Changed HAL_ICACHE_LINE_SIZE and
The ARM925T has 8k data cache, 16k instruction cache, 16 word
write buffer and an MMU."
}
+
+ cdl_option CYGPKG_HAL_ARM_ARM9_ARM926EJ {
+ display "ARM ARM926EJ microprocessor"
+ implements CYGINT_HAL_ARM_ARM9_VARIANT
+ default_value 0
+ no_define
+ define -file=system.h CYGPKG_HAL_ARM_ARM9_ARM926EJ
+ description "
+ The ARM926EJ has 16k data cache, 16k instruction cache, 16 word
+ write buffer and an MMU."
+ }
cdl_option CYGPKG_HAL_ARM_ARM9_ARM940T {
display "ARM ARM940T microprocessor"
// Author(s): gthomas
// Contributors:hmt, jskov
// Travis C. Furrer <furrer@mit.edu>
-// Date: 2000-05-08
+// Tom Chase <tomc@dtccom.com>
+// Date: 2005-05-10
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
# define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
# define HAL_WRITE_BUFFER 64
+// must flush everything manually
+# define CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_DCACHE
-# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE // has instruction to clean D-cache
+#elif defined(CYGPKG_HAL_ARM_ARM9_ARM926EJ)
+# define HAL_ICACHE_SIZE 0x4000
+# define HAL_ICACHE_LINE_SIZE 32
+# define HAL_ICACHE_WAYS 4
+# define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
+
+# define HAL_DCACHE_SIZE 0x2000
+# define HAL_DCACHE_LINE_SIZE 32
+# define HAL_DCACHE_WAYS 4
+# define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
+
+# define HAL_WRITE_BUFFER 64
+
+#define CYGHWR_HAL_ARM_ARM926EJ_CLEAN_DCACHE //has instruction to clean D-cache
#elif defined(CYGPKG_HAL_ARM_ARM9_ARM940T)
# define HAL_ICACHE_SIZE 0x1000
: "r0" /* Clobber list */ \
); \
CYG_MACRO_END
+#elif defined(CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_DCACHE)
+/*
+ * 'Clean & Invalidate whole DCache'
+ */
+#define HAL_DCACHE_SYNC() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mov r0, #255 << 4;" /* 256 entries/set */ \
+ "2: " \
+ "mcr p15, 0, r0, c7, c14, 2;" \
+ "subs r0, r0, #1 << 4;" \
+ "bcs 2b;" /* entries 255 to 0 */ \
+ "mcr p15,0,r0,c7,c10,4;" /* drain the write buffer */ \
+ : \
+ : \
+ : "r0" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+#elif defined(CYGHWR_HAL_ARM_ARM926EJ_CLEAN_DCACHE)
+/*
+ * 'Clean & Invalidate whole DCache'
+ */
+#define HAL_DCACHE_SYNC() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "1: " /* clean & invalidate D index */ \
+ "mrc p15, 0, r15, c7, c14, 3;" \
+ "bne 1b;" \
+ "mcr p15,0,r0,c7,c10,4;" /* drain the write buffer */ \
+ : \
+ : \
+ : "r0" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
#else
# error "Don't know how to sync Dcache"
#endif
+2008-07-12 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/hal_diag_dcc.{ch}
+ * src/hal_diag.c
+ * src/hal_diag_dbg.c
+ * cdl/hal_arm_at91.cdl: Add support for DCC, ie the Debug
+ Communications Channel, which is part of JTAG core of AT91 and
+ most ARM processors. JTAG devices often make this available via a
+ TCP port which can be accessed via telnet. NOTE: Only output to
+ DCC has been tested via diag_printf. Code exists for input, but it
+ has not been tested.
+
+2007-03-05 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * include/var_io.h: Fix a few typos pointed out by
+ Igor B. Poretsky.
+
+2007-02-13 John Eigelaar <jeigelaar@mweb.co.za>
+
+ * include/var_io.h: Fixed up the EMAC definitions to work
+ with the brand new EMAC driver
+
+2007-02-01 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * include/var_io.h: Added PWM registers.
+
+2007-01-25 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * include/var_io.h (AT91_PITC_VALUE_MASK): New - mask to access
+ the PITC value which is a 20 bit number.
+ * src/timer_pit.c: Change all hard coded mask for the period,
+ some of which were wrong, to use AT91_PITC_VALUE_MASK.
+ When initializing the PIT, remember to decrement the period first.
+ Bugs found by Jim Seymour.
+
+2006-09-08 John Eigelaar <jeigelaar@mweb.co.za>
+
+ * include/var_io.h: Added definition for SPI MODFDIS bit
+
+2006-08-31 Oyvind Harboe <oyvind.harboe@zylin.com>
+
+ * src/at91_misc.c: Now also resets external circuitry via
+ AT91_WD_OMR_EXTEN
+
+2006-06-01 John Eigelaar <jeigelaar@mweb.co.za>
+
+ * include/var_io.h: Added SPI PDC register definitions
+
+2006-05-20 John Eigelaar <jeigelaar@mweb.co.za>
+
+ * include/var_io.h: AT91SAM7X pin definitions
+ * include/hal_platform_int.h: AT91SAM7X interrupts
+ * include/plf_io.h: AT91SAM7X device addresses.
+
+2006-05-20 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * cdl/hal_arm_at91sam7s.cdl: Rename to AT91SAM7 and add support
+ for AT91SAM7X, based on code from John Eigelaar.
+ * include/var_io.h: add CAN, TWI and ADC registers.
+
+2006-05-17 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * include/var_io.h: Add macros to manipulate the PIO controllers.
+
+2006-05-10 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * include/var_io.h: Added the Ethernet MAC registers.
+
+2006-04-26 John Eigelaar <jeigelaar@mweb.co.za>
+
+ * include/var_io.h: Fix typo's in the USB register definitions
+ and add definitions for the S2C controller.
+
+2006-03-10 Oliver Munz <munz@speag.ch>
+
+ * src/timer_pit.c: fix hal_delay_us(). hal_clock_read for
+ initializing the PIT if needed. Change hal_clock_reset() to allow
+ setting of a new period. This is required when the timer is
+ started by hal_delay_us() or hal_clock_read() before
+ hal_clock_initialize().
+
+2006-03-23 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/timer_pit.c (hal_delay_us): Start the PIT if it is not
+ running when hal_delay_us is called. This happens when the kernel
+ is not used. Problem found by Oliver Munz.
+
+2006-03-10 Oliver Munz <munz@speag.ch>
+
+ * src/hal_diag.c (cyg_hal_plf_serial_isr): Change the #ifdefs to
+ cleanly match the CDL.
+
+2006-02-28 Andrew Lunn <andrew.lunn@ascom.ch>
+ Oliver Munz <munz@speag.ch>
+
+ * include/var_io.h (AT91_US_PTCR_RXTDIS): Add bit fields for the
+ USART DMA control register.
+
+2006-02-25 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * include/var_io.h: Added the USB device registers.
+
+2006-02-19 Andrew Lunn <andrew.lunn@ascom.ch>
+ Oliver Munz <munz@speag.ch>
+
+ * cdl/hal_arm_at9a.cdl: Add the AT91SAM7S variant and control
+ for new timer and debug usart code.
+ * include/var_io.h: Register definitions for AT91SAM7S
+ * include/var_arch.h: Idle action for AT91SAM7S
+ * src/at91_misc.c (hal_hardware_init): Call HAL_PLF_HARDWARE_INIT
+ for any platform specific initialization
+ * src/at91_misc.c (hal_at91_reset_cpu): Use the reset controller
+ if it exists.
+ * src/at91_misc.c (hal_IRQ_handler): Decode interrupts from
+ the system controller if it exists.
+ * src/timer_tc.c (NEW) eCos timer using the Timer Counter
+ * src/timer_pit.c (NEW) eCos timer using Periodic Interval Timer
+ * src/hal_diag_dbg.c (NEW) Debug output via debug UART.
+ * src/hal_diag.h: Indicate hal_at91_reset_cpu() is a C function
+ otherwise we have problems with the watchdog driver which is C++.
2005-05-30 Ezequiel Conde <ezeq@cc.isel.ipl.pt>
The AT91 HAL package provides the support needed to run
eCos on Atmel AT91 based targets."
- compile hal_diag.c at91_misc.c
+ compile at91_misc.c
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
display "AT91 variant used"
flavor data
default_value {"R40807"}
- legal_values {"R40807" "R40008" "M42800A" "M55800A" "JTST"}
+ legal_values {"R40807" "R40008" "M42800A" "M55800A" "JTST"
+ "AT91SAM7S" }
description "The AT91 microcontroller family has several variants,
the main differences being the amount of on-chip SRAM,
peripherals and their layout. This option allows the
normal way, i.e. a FIQ interrupt will be treated as a normal IRQ
using the highest priority"
}
-}
+
+ cdl_interface CYGINT_HAL_ARM_AT91_SYS_INTERRUPT {
+ display "AT91 core has multiplexed system interrupts"
+ description "
+ Some AT91 cores have a system controller which multiplexes
+ many interrupts onto the system interrupt. When this interface
+ is enabled the variant hal will perform a second level
+ expansion of these interrupts"
+ }
+
+ cdl_interface CYGINT_HAL_ARM_AT91_PIT_HW {
+ display "Platform has a Periodic Interval Timer"
+ description "
+ This interface if implemented by HALs for CPU cores which
+ have the Periodic Interval Timer."
+ }
+
+ cdl_option CYGBLD_HAL_ARM_AT91_TIMER_TC {
+ display "Use Timer Counter for eCos Clock"
+ flavor bool
+ default_value 1
+ requires !CYGBLD_HAL_ARM_AT91_TIMER_PIT
+ compile timer_tc.c
+ description "
+ Use a Timer Counter Channel to generate the eCos Clock."
+ }
+
+ cdl_option CYGBLD_HAL_ARM_AT91_TIMER_PIT {
+ display "Use Periodic Interval Timer for eCos Clock"
+ flavor bool
+ default_value !CYGBLD_HAL_ARM_AT91_TIMER_TC
+ requires !CYGBLD_HAL_ARM_AT91_TIMER_TC
+ active_if CYGINT_HAL_ARM_AT91_PIT_HW
+ compile timer_pit.c
+ description "
+ Use Periodic Interval Timer to generate the eCos Clock."
+ }
+
+ cdl_interface CYGINT_HAL_ARM_AT91_SERIAL_DBG_HW {
+ display "Platform has the DBG serial port"
+ description "
+ Some varients of the AT91 have a dedicated debug serial
+ port. The HALs of such a varient should implement this interface
+ so allowing the serial driver to the compiled"
+ }
+
+ cdl_option CYGBLD_HAL_ARM_AT91_SERIAL_DBG {
+ display "Enable the use of the DBG serial port"
+ flavor bool
+ active_if CYGINT_HAL_ARM_AT91_SERIAL_DBG_HW
+ active_if !CYGBLD_HAL_ARM_AT91_SERIAL_UART
+ requires CYGINT_HAL_ARM_AT91_SYS_INTERRUPT
+ default_value 1
+
+ compile hal_diag_dbg.c
+ requires CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL == 0
+ requires CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0
+
+ description "
+ The driver for the dedicated DBG UART will be compiled in the
+ varient HAL when this option is enabled."
+ }
+
+ cdl_option CYGBLD_HAL_ARM_AT91_SERIAL_UART {
+ display "Enable the use of the UARTS for debug output"
+ flavor bool
+ default_value 1
+ compile hal_diag.c
+ requires !CYGBLD_HAL_ARM_AT91_SERIAL_DBG
+ description "
+ The driver for using the UARTS will be compiled in the
+ varient HAL when this option is enabled."
+ }
+
+ cdl_component CYGBLD_HAL_ARM_AT91_DCC {
+ display "Enable the use of the DCC for debug output"
+ flavor bool
+ default_value 0
+ compile hal_diag_dcc.c
+ description "
+ A <serial> driver will be compiled and inserted into the
+ vector table which does I/O via the DCC. The DCC is part of
+ the JTAG interface and some JTAG devices made this interface
+ available via telnet etc."
+
+ cdl_option CYGBLD_HAL_ARM_AT91_DCC_CHANNEL {
+ display "Channel the DCC port should use in the VV table"
+ flavor data
+ default_value 2
+ description "
+ The DCC driver has to be registered in the VV table of
+ drivers. This option determines which entry in the
+ table it will take. The default value will overwride
+ the first serial port. "
+ }
+ }
+}
\ No newline at end of file
//-----------------------------------------------------------------------------
// reset
-extern void hal_at91_reset_cpu(void);
+externC void hal_at91_reset_cpu(void);
//-----------------------------------------------------------------------------
// end of hal_diag.h
CYG_MACRO_END
#elif defined(CYGHWR_HAL_ARM_AT91_M42800A) || \
- defined(CYGHWR_HAL_ARM_AT91_M55800A)
+ defined(CYGHWR_HAL_ARM_AT91_M55800A) || \
+ defined(CYGHWR_HAL_ARM_AT91SAM7)
#define HAL_IDLE_THREAD_ACTION(_count_) \
CYG_MACRO_START \
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+// Copyright (C) 2005, 2006 Andrew Lunn (andrew.lunn@ascom.ch>
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
-// Contributors:jskov, gthomas, tkoeller, tdrury, nickg
+// Contributors:jskov, gthomas, tkoeller, tdrury, nickg, asl, John Eigelaar
// Date: 2001-07-12
// Purpose: AT91 variant specific registers
// Description:
#define AT91_US_TCR 0x3c // Transmit counter register
#endif
+// PDC Control register bits
+#define AT91_US_PTCR_RXTEN (1 << 0)
+#define AT91_US_PTCR_RXTDIS (1 << 1)
+#define AT91_US_PTCR_TXTEN (1 << 8)
+#define AT91_US_PTCR_TXTDIS (1 << 9)
+
// macro could be different from target to target (i.e jtst)
#ifndef AT91_US_BAUD
#define AT91_US_BAUD(baud) ((CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(8*(baud))+1)/2)
#define AT91_PIO 0xFFFF0000
#endif
+#define AT91_PIN(_ctrl_, _periph_, _pin_) \
+ ((_ctrl_ << 16) | (_periph_ << 8) | (_pin_))
+
#define AT91_PIO_PER 0x00 // PIO enable
#define AT91_PIO_PDR 0x04 // PIO disable
#define AT91_PIO_PSR 0x08 // PIO status
+// GPIO pins on PIO A.
+#define AT91_GPIO_PA0 AT91_PIN(0,0, 0)
+#define AT91_GPIO_PA1 AT91_PIN(0,0, 1)
+#define AT91_GPIO_PA2 AT91_PIN(0,0, 2)
+#define AT91_GPIO_PA3 AT91_PIN(0,0, 3)
+#define AT91_GPIO_PA4 AT91_PIN(0,0, 4)
+#define AT91_GPIO_PA5 AT91_PIN(0,0, 5)
+#define AT91_GPIO_PA6 AT91_PIN(0,0, 6)
+#define AT91_GPIO_PA7 AT91_PIN(0,0, 7)
+#define AT91_GPIO_PA8 AT91_PIN(0,0, 8)
+#define AT91_GPIO_PA9 AT91_PIN(0,0, 9)
+#define AT91_GPIO_PA10 AT91_PIN(0,0,10)
+#define AT91_GPIO_PA11 AT91_PIN(0,0,11)
+#define AT91_GPIO_PA12 AT91_PIN(0,0,12)
+#define AT91_GPIO_PA13 AT91_PIN(0,0,13)
+#define AT91_GPIO_PA14 AT91_PIN(0,0,14)
+#define AT91_GPIO_PA15 AT91_PIN(0,0,15)
+#define AT91_GPIO_PA16 AT91_PIN(0,0,16)
+#define AT91_GPIO_PA17 AT91_PIN(0,0,17)
+#define AT91_GPIO_PA18 AT91_PIN(0,0,18)
+#define AT91_GPIO_PA19 AT91_PIN(0,0,19)
+#define AT91_GPIO_PA20 AT91_PIN(0,0,20)
+#define AT91_GPIO_PA21 AT91_PIN(0,0,21)
+#define AT91_GPIO_PA22 AT91_PIN(0,0,22)
+#define AT91_GPIO_PA23 AT91_PIN(0,0,23)
+#define AT91_GPIO_PA24 AT91_PIN(0,0,24)
+#define AT91_GPIO_PA25 AT91_PIN(0,0,25)
+#define AT91_GPIO_PA26 AT91_PIN(0,0,26)
+#define AT91_GPIO_PA27 AT91_PIN(0,0,27)
+#define AT91_GPIO_PA28 AT91_PIN(0,0,28)
+#define AT91_GPIO_PA29 AT91_PIN(0,0,29)
+#define AT91_GPIO_PA30 AT91_PIN(0,0,30)
+#define AT91_GPIO_PA31 AT91_PIN(0,0,31)
+
+#ifdef AT91_PIOB
+// GPIO pins on PIOB.
+#define AT91_GPIO_PB0 AT91_PIN(1,0, 0)
+#define AT91_GPIO_PB1 AT91_PIN(1,0, 1)
+#define AT91_GPIO_PB2 AT91_PIN(1,0, 2)
+#define AT91_GPIO_PB3 AT91_PIN(1,0, 3)
+#define AT91_GPIO_PB4 AT91_PIN(1,0, 4)
+#define AT91_GPIO_PB5 AT91_PIN(1,0, 5)
+#define AT91_GPIO_PB6 AT91_PIN(1,0, 6)
+#define AT91_GPIO_PB7 AT91_PIN(1,0, 7)
+#define AT91_GPIO_PB8 AT91_PIN(1,0, 8)
+#define AT91_GPIO_PB9 AT91_PIN(1,0, 9)
+#define AT91_GPIO_PB10 AT91_PIN(1,0,10)
+#define AT91_GPIO_PB11 AT91_PIN(1,0,11)
+#define AT91_GPIO_PB12 AT91_PIN(1,0,12)
+#define AT91_GPIO_PB13 AT91_PIN(1,0,13)
+#define AT91_GPIO_PB14 AT91_PIN(1,0,14)
+#define AT91_GPIO_PB15 AT91_PIN(1,0,15)
+#define AT91_GPIO_PB16 AT91_PIN(1,0,16)
+#define AT91_GPIO_PB17 AT91_PIN(1,0,17)
+#define AT91_GPIO_PB18 AT91_PIN(1,0,18)
+#define AT91_GPIO_PB19 AT91_PIN(1,0,19)
+#define AT91_GPIO_PB20 AT91_PIN(1,0,20)
+#define AT91_GPIO_PB21 AT91_PIN(1,0,21)
+#define AT91_GPIO_PB22 AT91_PIN(1,0,22)
+#define AT91_GPIO_PB23 AT91_PIN(1,0,23)
+#define AT91_GPIO_PB24 AT91_PIN(1,0,24)
+#define AT91_GPIO_PB25 AT91_PIN(1,0,25)
+#define AT91_GPIO_PB26 AT91_PIN(1,0,26)
+#define AT91_GPIO_PB27 AT91_PIN(1,0,27)
+#define AT91_GPIO_PB28 AT91_PIN(1,0,28)
+#define AT91_GPIO_PB29 AT91_PIN(1,0,29)
+#define AT91_GPIO_PB30 AT91_PIN(1,0,30)
+#define AT91_GPIO_PB31 AT91_PIN(1,0,31)
+#endif //AT91_PIOB
+
#if defined(CYGHWR_HAL_ARM_AT91_M55800A)
+#define AT91_TC_TCLK3 AT91_PIN(0,0, 0) // Timer 3 Clock signal
+#define AT91_TC_TIOA3 AT91_PIN(0,0, 1) // Timer 3 Signal A
+#define AT91_TC_TIOB3 AT91_PIN(0,0, 2) // Timer 3 Signal B
+#define AT91_TC_TCLK4 AT91_PIN(0,0, 3) // Timer 4 Clock signal
+#define AT91_TC_TIOA4 AT91_PIN(0,0, 4) // Timer 4 Signal A
+#define AT91_TC_TIOB4 AT91_PIN(0,0, 5) // Timer 4 Signal B
+#define AT91_TC_TCLK5 AT91_PIN(0,0, 6) // Timer 5 Clock signal
+#define AT91_TC_TIOA5 AT91_PIN(0,0, 7) // Timer 5 Signal A
+#define AT91_TC_TIOB5 AT91_PIN(0,0, 8) // Timer 5 Signal B
+#define AT91_INT_IRQ0 AT91_PIN(0,0, 9) // External Interrupt 0
+#define AT91_INT_IRQ1 AT91_PIN(0,0,10) // External Interrupt 1
+#define AT91_INT_IRQ2 AT91_PIN(0,0,11) // External Interrupt 2
+#define AT91_INT_IRQ3 AT91_PIN(0,0,12) // External Interrupt 3
+#define AT91_INT_FIQ AT91_PIN(0,0,13) // Fast Interrupt
+#define AT91_USART_SCK0 AT91_PIN(0,0,14) // USART 0 Clock signal
+#define AT91_USART_TXD0 AT91_PIN(0,0,15) // USART 0 transmit data
+#define AT91_USART_RXD0 AT91_PIN(0,0,16) // USART 0 receive data
+#define AT91_USART_SCK1 AT91_PIN(0,0,17) // USART 1 Clock signal
+#define AT91_USART_TXD1 AT91_PIN(0,0,18) // USART 1 transmit data
+#define AT91_USART_RXD1 AT91_PIN(0,0,19) // USART 1 receive data
+#define AT91_USART_SCK2 AT91_PIN(0,0,20) // USART 2 Clock signal
+#define AT91_USART_TXD2 AT91_PIN(0,0,21) // USART 2 transmit data
+#define AT91_USART_RXD2 AT91_PIN(0,0,22) // USART 2 receive data
+#define AT91_SPI_SPCK AT91_PIN(0,0,23) // SPI Clock signal
+#define AT91_SPI_MISO AT91_PIN(0,0,24) // SPI Master In Slave Out
+#define AT91_SPI_MOIS AT91_PIN(0,0,25) // SPI Master Out Slave In
+#define AT91_SPI_NPCS0 AT91_PIN(0,0,26) // SPI Peripheral Chip Select 0
+#define AT91_SPI_NPCS1 AT91_PIN(0,0,27) // SPI Peripheral Chip Select 1
+#define AT91_SPI_NPCS2 AT91_PIN(0,0,28) // SPI Peripheral Chip Select 2
+#define AT91_SPI_NPCS3 AT91_PIN(0,0,29) // SPI Peripheral Chip Select 3
+
+#define AT91_INT_IRQ4 AT91_PIN(1,0, 3) // External Interrupt 4
+#define AT91_INT_IRQ5 AT91_PIN(1,0, 4) // External Interrupt 5
+#define AT91_ADC_AD0TRIG AT91_PIN(1,0, 6) // ADC0 External Trigger
+#define AT91_ADC_AD1TRIG AT91_PIN(1,0, 7) // ADC1 External Trigger
+#define AT91_BOOT_BMS AT91_PIN(1,0,12) // Boot Mode Select
+#define AT91_TC_TCLK0 AT91_PIN(1,0,14) // Timer 0 Clock signal
+#define AT91_TC_TIOA0 AT91_PIN(1,0,15) // Timer 0 Signal A
+#define AT91_TC_TIOB0 AT91_PIN(1,0,16) // Timer 0 Signal B
+#define AT91_TC_TCLK1 AT91_PIN(1,0,17) // Timer 1 Clock signal
+#define AT91_TC_TIOA1 AT91_PIN(1,0,18) // Timer 1 Signal A
+#define AT91_TC_TIOB1 AT91_PIN(1,0,19) // Timer 1 Signal B
+#define AT91_TC_TCLK2 AT91_PIN(1,0,20) // Timer 2 Clock signal
+#define AT91_TC_TIOA2 AT91_PIN(1,0,21) // Timer 2 Signal A
+#define AT91_TC_TIOB2 AT91_PIN(1,0,22) // Timer 2 Signal B
+
// PIOA
#define AT91_PIO_PSR_TCLK3 0x00000001 // Timer 3 Clock signal
#define AT91_PIO_PSR_TIOA3 0x00000002 // Timer 3 Signal A
#define AT91_PIO_PSR_TIOA2 0x04000000 // Timer 2 Signal A
#define AT91_PIO_PSR_TIOB2 0x08000000 // Timer 2 Signal B
+#elif defined (CYGHWR_HAL_ARM_AT91SAM7)
+#include <pkgconf/hal_arm_at91sam7.h>
+
+#ifdef CYGHWR_HAL_ARM_AT91SAM7S
+#define AT91_PWM_PWM0 AT91_PIN(0,0, 0) // Pulse Width Modulation 0
+#define AT91_PWM_PWM1 AT91_PIN(0,0, 1) // Pulse Width Modulation 1
+#define AT91_PWM_PWM2 AT91_PIN(0,0, 2) // Pulse Width Modulation 2
+#define AT91_TWI_TWD AT91_PIN(0,0, 3) // Two Wire Data
+#define AT91_TWI_TWCK AT91_PIN(0,0, 4) // Two Wire Clock
+#define AT91_USART_RXD0 AT91_PIN(0,0, 5) // USART 0 Receive Data
+#define AT91_USART_TXD0 AT91_PIN(0,0, 6) // USART 0 Transmit Data
+#define AT91_USART_RTS0 AT91_PIN(0,0, 7) // USART 0 Ready To Send
+#define AT91_USART_CTS0 AT91_PIN(0,0, 8) // USART 0 Clear To Send
+#define AT91_DBG_DRXD AT91_PIN(0,0, 9) // Debug UART Receive
+#define AT91_DBG_DTXD AT91_PIN(0,0,10) // Debug UART Transmit
+#define AT91_SPI_NPCS0 AT91_PIN(0,0,11) // SPI Chip Select 0
+#define AT91_SPI_MISO AT91_PIN(0,0,12) // SPI Input
+#define AT91_SPI_MOIS AT91_PIN(0,0,13) // SPI Output
+#define AT91_SPI_SPCK AT91_PIN(0,0,14) // SPI clock
+#define AT91_S2C_TF AT91_PIN(0,0,15) // S2C Transmit Frame Sync
+#define AT91_S2C_TK AT91_PIN(0,0,16) // S2C Transmit Clock
+#define AT91_S2C_TD AT91_PIN(0,0,17) // S2C Transmit Data
+#define AT91_S2C_RD AT91_PIN(0,0,18) // S2C Receive Data
+#define AT91_S2C_RK AT91_PIN(0,0,19) // S2C Receive Clock
+#define AT91_S2C_RF AT91_PIN(0,0,20) // S2C Receive Frame Sync
+#if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
+#define AT91_USART_RXD1 AT91_PIN(0,0,21) // USART 1 Receive Data
+#define AT91_USART_TXD1 AT91_PIN(0,0,22) // USART 1 Transmit Data
+#define AT91_USART_SCK1 AT91_PIN(0,0,23) // USART 1 Serial Clock
+#define AT91_USART_RTS1 AT91_PIN(0,0,24) // USART 1 Ready To Send
+#define AT91_USART_CTS1 AT91_PIN(0,0,25) // USART 1 Clear To Send
+#define AT91_USART_DVD1 AT91_PIN(0,0,26) // USART 1 Data Carrier Detect
+#define AT91_USART_DTR1 AT91_PIN(0,0,27) // USART 1 Data Terminal Ready
+#define AT91_USART_DSR1 AT91_PIN(0,0,28) // USART 1 Data Set Ready
+#define AT91_USART_RI1 AT91_PIN(0,0,29) // USART 2 Ring Indicator
+#define AT91_INT_IRQ1 AT91_PIN(0,0,30) // Interrupt Request 1
+#define AT91_SPI_NPCS1 AT91_PIN(0,0,31) // SPI Chip Select 1
+#endif
+
+#define AT91_TC_TIOA0 AT91_PIN(0,1, 0) // Timer/Counter 0 IO Line A
+#define AT91_TC_TIOB0 AT91_PIN(0,1, 1) // Timer/Counter 0 IO Line B
+#define AT91_USART_SCK0 AT91_PIN(0,1, 2) // USART 0 Serial Clock
+#define AT91_SPI_NPCS3 AT91_PIN(0,1, 3) // SPI Chip Select 3
+#define AT91_TC_TCLK0 AT91_PIN(0,1, 4) // Timer/Counter 0 Clock Input
+#define AT91_SPI_NPCS3X AT91_PIN(0,1, 5) // SPI Chip Select 3 (again)
+#define AT91_PCK_PCK0 AT91_PIN(0,1, 6) // Programmable Clock Output 0
+#define AT91_PWM_PWM3 AT91_PIN(0,1, 7) // Pulse Width Modulation #3
+#define AT91_ADC_ADTRG AT91_PIN(0,1, 8) // ADC Trigger
+#define AT91_SPI_NPCS1X AT91_PIN(0,1, 9) // SPI Chip Select 1
+#define AT91_SPI_NPCS2 AT91_PIN(0,1,10) // SPI Chip Select 2
+#define AT91_PWM_PWM0X AT91_PIN(0,1,11) // Pulse Width Modulation #0
+#define AT91_PIO_PWM_PWM1X AT91_PIN(0,1,12) // Pulse Width Modulation #1
+#define AT91_PIO_PWM_PWM2X AT91_PIN(0,1,13) // Pulse Width Modulation #2
+#define AT91_PIO_PWM_PWM4X AT91_PIN(0,1,14) // Pulse Width Modulation #4
+#define AT91_TC_TIOA1 AT91_PIN(0,1,15) // Timer/Counter 1 IO Line A
+#define AT91_TC_TIOB1 AT91_PIN(0,1,16) // Timer/Counter 1 IO Line B
+#define AT91_PCK_PCK1 AT91_PIN(0,1,17) // Programmable Clock Output 1
+#define AT91_PCK_PCK2 AT91_PIN(0,1,18) // Programmable Clock Output 2
+#define AT91_INT_FIQ AT91_PIN(0,1,19) // Fast Interrupt Request
+#define AT91_INT_IRQ0 AT91_PIN(0,1,20) // Interrupt Request 0
+#if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
+#define AT91_PCK_PCK1X AT91_PIN(0,1,21) // Programmable Clock Output 1
+#define AT91_SPI_NPCS3XX AT91_PIN(0,1,22) // SPI Chip Select 3 (yet again)
+#define AT91_PWM_PWM0XX AT91_PIN(0,1,23) // Pulse Width Modulation #0
+#define AT91_PWM_PWM1XX AT91_PIN(0,1,24) // Pulse Width Modulation #1
+#define AT91_PWM_PWM2XX AT91_PIN(0,1,25) // Pulse Width Modulation 2
+#define AT91_TC_TIOA2 AT91_PIN(0,1,26) // Timer/Counter 2 IO Line A
+#define AT91_TC_TIOB2 AT91_PIN(0,1,27) // Timer/Counter 2 IO Line B
+#define AT91_TC_TCLK1 AT91_PIN(0,1,28) // External Clock Input 1
+#define AT91_TC_TCLK2 AT91_PIN(0,1,29) // External Clock Input 2
+#define AT91_SPI_NPCS2X AT91_PIN(0,1,30) // SPI Chip Select 2 (again)
+#define AT91_PCK_PCK2X AT91_PIN(0,1,31) // Programmable Clock Output 2
+#endif //!defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
+
+// PIO Peripheral A
+#define AT91_PIO_PSR_PWM0 0x00000001 // Pulse Width Modulation 0
+#define AT91_PIO_PSR_PWM1 0x00000002 // Pulse Width Modulation 1
+#define AT91_PIO_PSR_PWM2 0x00000004 // Pulse Width Modulation 2
+#define AT91_PIO_PSR_TWD 0x00000008 // Two Wire Data
+#define AT91_PIO_PSR_TWCK 0x00000010 // Two Wire Clock
+#define AT91_PIO_PSR_RXD0 0x00000020 // USART 0 Receive Data
+#define AT91_PIO_PSR_TXD0 0x00000040 // USART 0 Transmit Data
+#define AT91_PIO_PSR_RTS0 0x00000080 // USART 0 Ready To Send
+#define AT91_PIO_PSR_CTS0 0x00000100 // USART 0 Clear To Send
+#define AT91_PIO_PSR_DRXD 0x00000200 // Debug UART Receive
+#define AT91_PIO_PSR_DTXD 0x00000400 // Debug UART Transmit
+#define AT91_PIO_PSR_NPCS0 0x00000800 // SPI Chip Select 0
+#define AT91_PIO_PSR_MISO 0x00001000 // SPI Input
+#define AT91_PIO_PSR_MOIS 0x00002000 // SPI Output
+#define AT91_PIO_PSR_SPCK 0x00004000 // SPI clock
+#define AT91_PIO_PSR_TF 0x00008000 // S2C Transmit Frame Sync
+#define AT91_PIO_PSR_TK 0x00010000 // S2C Transmit Clock
+#define AT91_PIO_PSR_TD 0x00020000 // S2C Transmit Data
+#define AT91_PIO_PSR_RD 0x00040000 // S2C Receive Data
+#define AT91_PIO_PSR_RK 0x00080000 // S2C Receive Clock
+#define AT91_PIO_PSR_RF 0x00100000 // S2C Receive Frame Sync
+#if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
+#define AT91_PIO_PSR_RXD1 0x00200000 // USART 1 Receive Data
+#define AT91_PIO_PSR_TXD1 0x00400000 // USART 1 Transmit Data
+#define AT91_PIO_PSR_SCK1 0x00800000 // USART 1 Serial Clock
+#define AT91_PIO_PSR_RTS1 0x01000000 // USART 1 Ready To Send
+#define AT91_PIO_PSR_CTS1 0x02000000 // USART 1 Clear To Send
+#define AT91_PIO_PSR_DCD1 0x04000000 // USART 1 Data Carrier Detect
+#define AT91_PIO_PSR_DTR1 0x08000000 // USART 1 Data Terminal Ready
+#define AT91_PIO_PSR_DSR1 0x10000000 // USART 1 Data Set Ready
+#define AT91_PIO_PSR_RI1 0x20000000 // USART 2 Ring Indicator
+#define AT91_PIO_PSR_IRQ1 0x40000000 // Interrupt Request 1
+#define AT91_PIO_PSR_NPCS1 0x80000000 // SPI Chip Select 1
+#endif // !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s64)
+
+// PIO Peripheral B
+#define AT91_PIO_PSR_TIOA0 0x00000001 // Timer/Counter 0 IO Line A
+#define AT91_PIO_PSR_TIOB0 0x00000002 // Timer/Counter 0 IO Line B
+#define AT91_PIO_PSR_SCK0 0x00000004 // USART 0 Serial Clock
+#define AT91_PIO_PSR_NPCS3 0x00000008 // SPI Chip Select 3
+#define AT91_PIO_PSR_TCLK0 0x00000010 // Timer/Counter 0 Clock Input
+#define AT91_PIO_PSR_NPCS3X 0x00000020 // SPI Chip Select 3 (again)
+#define AT91_PIO_PSR_PCK0 0x00000040 // Programmable Clock Output 0
+#define AT91_PIO_PSR_PWM3 0x00000080 // Pulse Width Modulation #3
+#define AT91_PIO_PSR_ADTRG 0x00000100 // ADC Trigger
+#define AT91_PIO_PSR_NPCS1X 0x00000200 // SPI Chip Select 1 (again)
+#define AT91_PIO_PSR_NPCS2 0x00000400 // SPI Chip Select 2
+#define AT91_PIO_PSR_PWMOX 0x00000800 // Pulse Width Modulation #0 (again)
+#define AT91_PIO_PSR_PWM1X 0x00001000 // Pulse Width Modulation #1 (again)
+#define AT91_PIO_PSR_PWM2X 0x00002000 // Pulse Width Modulation #2 (again)
+#define AT91_PIO_PSR_PWM3X 0x00004000 // Pulse Width Modulation #4 (again)
+#define AT91_PIO_PSR_TIOA1 0x00008000 // Timer/Counter 1 IO Line A
+#define AT91_PIO_PSR_TIOB1 0x00010000 // Timer/Counter 1 IO Line B
+#define AT91_PIO_PSR_PCK1 0x00020000 // Programmable Clock Output 1
+#define AT91_PIO_PSR_PCK2 0x00040000 // Programmable Clock Output 2
+#define AT91_PIO_PSR_FIQ 0x00080000 // Fast Interrupt Request
+#define AT91_PIO_PSR_IRQ0 0x00100000 // Interrupt Request 0
+#if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
+#define AT91_PIO_PSR_PCK1X 0x00200000 // Programmable Clock Output 1(again)
+#define AT91_PIO_PSR_NPCS3XX 0x00400000 // SPI Chip Select 3 (yet again)
+#define AT91_PIO_PSR_PWMOXX 0x00800000 // Pulse Width Modulation #0 (again)
+#define AT91_PIO_PSR_PWM1XX 0x01000000 // Pulse Width Modulation #1 (again)
+#define AT91_PIO_PSR_PWM2XX 0x02000000 // Pulse Width Modulation #2 (again)
+#define AT91_PIO_PSR_TIOA2 0x04000000 // Timer/Counter 2 IO Line A
+#define AT91_PIO_PSR_TIOB2 0x08000000 // Timer/Counter 2 IO Line B
+#define AT91_PIO_PSR_TCLK1 0x10000000 // External Clock Input 1
+#define AT91_PIO_PSR_TCLK2 0x20000000 // External Clock Input 2
+#define AT91_PIO_PSR_NPCS2X 0x40000000 // SPI Chip Select 2 (again)
+#define AT91_PIO_PSR_PCK2X 0x80000000 // Programmable Clock Output 2(again)
+#endif // !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s64)
+#endif // CYGHWR_HAL_ARM_AT91SAM7S
+
+#ifdef CYGHWR_HAL_ARM_AT91SAM7X
+
+// PIO Controller A, peripheral A
+#define AT91_USART_RXD0 AT91_PIN(0,0, 0) // USART 0 Receive Data
+#define AT91_USART_TXD0 AT91_PIN(0,0, 1) // USART 0 Transmit Data
+#define AT91_USART_SCK0 AT91_PIN(0,0, 2) // USART 0 Serial Clock
+#define AT91_USART_RTS0 AT91_PIN(0,0, 3) // USART 0 Request To Send
+#define AT91_USART_CTS0 AT91_PIN(0,0, 4) // USART 0 Clear To Send
+#define AT91_USART_RXD1 AT91_PIN(0,0, 5) // USART 1 Receive Data
+#define AT91_USART_TXD1 AT91_PIN(0,0, 6) // USART 1 Transmit Data
+#define AT91_USART_SCK1 AT91_PIN(0,0, 7) // USART 1 Serial Clock
+#define AT91_USART_RTS1 AT91_PIN(0,0, 8) // USART 1 Request To Send
+#define AT91_USART_CTS1 AT91_PIN(0,0, 9) // USART 1 Clear To Send
+#define AT91_TWI_TWD AT91_PIN(0,0,10) // Two Wire Data
+#define AT91_TWI_TWCK AT91_PIN(0,0,11) // Two Wire Clock
+#define AT91_SPI_NPCS0 AT91_PIN(0,0,12) // SPI 0 Chip Select 0
+#define AT91_SPI_NPCS1 AT91_PIN(0,0,13) // SPI 0 Chip Select 1
+#define AT91_SPI_NPCS2 AT91_PIN(0,0,14) // SPI 0 Chip Select 2
+#define AT91_SPI_NPCS3 AT91_PIN(0,0,15) // SPI 0 Chip Select 3
+#define AT91_SPI_MISO AT91_PIN(0,0,16) // SPI 0 Master In Slave Out
+#define AT91_SPI_MOIS AT91_PIN(0,0,17) // SPI 0 Master Out Slave In
+#define AT91_SPI_SPCK AT91_PIN(0,0,18) // SPI 0 Clock
+#define AT91_CAN_CANRX AT91_PIN(0,0,19) // CAN Receive
+#define AT91_CAN_CANTX AT91_PIN(0,0,20) // CAN Transmit
+#define AT91_SSC_TF AT91_PIN(0,0,21) // SSC Transmit Frame Sync
+#define AT91_S2C_TK AT91_PIN(0,0,22) // SSC Transmit Clock
+#define AT91_S2C_TD AT91_PIN(0,0,23) // SSC Transmit Data
+#define AT91_S2C_RD AT91_PIN(0,0,24) // SSC Receive Data
+#define AT91_S2C_RK AT91_PIN(0,0,25) // SSC Receive Clock
+#define AT91_S2C_RF AT91_PIN(0,0,26) // SSC Receive Frame Sync
+#define AT91_DBG_DRXD AT91_PIN(0,0,27) // DBGU Receive Data
+#define AT91_DBG_DTXD AT91_PIN(0,0,28) // DBGU Transmit Data
+#define AT91_INT_FIQ AT91_PIN(0,0,29) // Fast Interrupt Request
+#define AT91_INT_IRQ0 AT91_PIN(0,0,30) // Interrupt Request 0
+
+//PIO controller A, peripheral B
+#define AT91_SPI1_NPCS1 AT91_PIN(0,1, 2) // SPI 1 Chip Select 1
+#define AT91_SPI1_NPCS2 AT91_PIN(0,1, 3) // SPI 1 Chip Select 2
+#define AT91_SPI1_NPCS3 AT91_PIN(0,1, 4) // SPI 1 Chip Select 3
+#define AT91_SPI_NPCS1X AT91_PIN(0,1, 7) // SPI 0 Chip Select 1
+#define AT91_SPI_NPCS2X AT91_PIN(0,1, 8) // SPI 0 Chip Select 2
+#define AT91_SPI_NPCS3X AT91_PIN(0,1, 9) // SPI 0 Chip Select 3
+#define AT91_PCK_PCK1 AT91_PIN(0,1,13) // Programmable Clock Output 1
+#define AT91_INT_IRQ1 AT91_PIN(0,1,14) // Interrupt Request 1
+#define AT91_TC_TCLK1 AT91_PIN(0,1,15) // Timer/Counter 1 Clock Input
+#define AT91_SPI1_NPCS0 AT91_PIN(0,1,21) // SPI 1 Chip Select 0
+#define AT91_SPI1_SPCK AT91_PIN(0,1,22) // SPI 1 Clock
+#define AT91_SPI1_MOSI AT91_PIN(0,1,23) // SPI 1 Master Out Slave In
+#define AT91_SPI1_MISO AT91_PIN(0,1,24) // SPI 0 Master In Slave Out
+#define AT91_SPI1_NPCS1X AT91_PIN(0,1,25) // SPI 1 Chip Select 1
+#define AT91_SPI1_NPCS2X AT91_PIN(0,1,26) // SPI 1 Chip Select 2
+#define AT91_PCK_PCK3 AT91_PIN(0,1,27) // Programmable Clock Output 3
+#define AT91_SPI1_NPCS3X AT91_PIN(0,1,29) // SPI 1 Chip Select 3
+#define AT91_PCK_PCK2 AT91_PIN(0,1,30) // Programmable Clock Output 2
+
+//PIO Controller B, Peripheral A
+#define AT91_EMAC_EREFCK AT91_PIN(1,0, 0) // EMAC Reference Clock
+#define AT91_EMAC_ETXEN AT91_PIN(1,0, 1) // EMAC Transmit Enable
+#define AT91_EMAC_ETX0 AT91_PIN(1,0, 2) // EMAC Transmit Data 0
+#define AT91_EMAC_ETX1 AT91_PIN(1,0, 3) // EMAC Transmit Data 1
+#define AT91_EMAC_ECRS AT91_PIN(1,0, 4) // EMAC Carrier Sense
+#define AT91_EMAC_ERX0 AT91_PIN(1,0, 5) // EMAC Receive Data 0
+#define AT91_EMAC_ERX1 AT91_PIN(1,0, 6) // EMAC Receive Data 1
+#define AT91_EMAC_ERXER AT91_PIN(1,0, 7) // EMAC Receive Error
+#define AT91_EMAC_EMDC AT91_PIN(1,0, 8) // EMAC Management Data Clock
+#define AT91_EMAC_EMDIO AT91_PIN(1,0, 9) // EMAC Management Data IO
+#define AT91_EMAC_ETX2 AT91_PIN(1,0,10) // EMAC Transmit Data 2
+#define AT91_EMAC_ETX3 AT91_PIN(1,0,11) // EMAC Transmit Data 3
+#define AT91_EMAC_ETXER AT91_PIN(1,0,12) // EMAC Transmit Coding Error
+#define AT91_EMAC_ERX2 AT91_PIN(1,0,13) // EMAC Receive Data 2
+#define AT91_EMAC_ERX3 AT91_PIN(1,0,14) // EMAC Receive Data 3
+#define AT91_EMAC_ECRSDV AT91_PIN(1,0,15) // EMAC Carrier Sense And Data Valid
+#define AT91_EMAC_ERXDV AT91_PIN(1,0,15) // EMAC Receive Data Valid
+#define AT91_EMAC_ECOL AT91_PIN(1,0,16) // EMAC Collision Detected
+#define AT91_EMAC_ERXCK AT91_PIN(1,0,17) // EMAC Receive Clock
+#define AT91_EMAC_EF100 AT91_PIN(1,0,18) // EMAC Force 100Mb/s
+#define AT91_PWM_PWM0 AT91_PIN(1,0,19) // Pulse Width Modulation #0
+#define AT91_PWM_PWM1 AT91_PIN(1,0,20) // Pulse Width Modulation #1
+#define AT91_PWM_PWM2 AT91_PIN(1,0,21) // Pulse Width Modulation #2
+#define AT91_PWM_PWM3 AT91_PIN(1,0,22) // Pulse Width Modulation #3
+#define AT91_TC_TIOA0 AT91_PIN(1,0,23) // Timer/Counter 0 IO Line A
+#define AT91_TC_TIOB0 AT91_PIN(1,0,24) // Timer/Counter 0 IO Line B
+#define AT91_TC_TIOA1 AT91_PIN(1,0,25) // Timer/Counter 1 IO Line A
+#define AT91_TC_TIOB1 AT91_PIN(1,0,26) // Timer/Counter 1 IO Line B
+#define AT91_TC_TIOA2 AT91_PIN(1,0,27) // Timer/Counter 2 IO Line A
+#define AT91_TC_TIOB2 AT91_PIN(1,0,28) // Timer/Counter 2 IO Line B
+#define AT91_PCK_PCK1X AT91_PIN(1,0,29) // Programmable Clock Output 1
+#define AT91_PCK_PCK2X AT91_PIN(1,0,30) // Programmable Clock Output 2
+
+//PIO Controller B Peripheral B
+#define AT91_PCK_PCK0 AT91_PIN(1,1, 0) // Programmable Clock Output 0
+#define AT91_SPI1_NPCS1XX AT91_PIN(1,1,10) // SPI 1 Chip Select 1
+#define AT91_SPI1_NPCS2XX AT91_PIN(1,1,11) // SPI 1 Chip Select 2
+#define AT91_TC_TCLK0 AT91_PIN(1,1,12) // Timer/Counter 0 Clock Input
+#define AT91_SPI_NPCS1XX AT91_PIN(1,1,13) // SPI 0 Chip Select 1
+#define AT91_SPI_NPCS2XX AT91_PIN(1,1,14) // SPI 0 Chip Select 2
+#define AT91_SPI1_NPCS3XX AT91_PIN(1,1,16) // SPI 1 Chip Select 3
+#define AT91_SPI_NPCS3XX AT91_PIN(1,1,17) // SPI 0 Chip Select 3
+#define AT91_ADC_ADTRG AT91_PIN(1,1,18) // ADC Trigger
+#define AT91_TC_TCLK1X AT91_PIN(1,1,19) // Timer/Counter 1 Clock Input
+#define AT91_PCK_PCK0X AT91_PIN(1,1,20) // Programmable Clock Output 0
+#define AT91_PCK_PCK1XX AT91_PIN(1,1,21) // Programmable Clock Output 1
+#define AT91_PCK_PCK2XX AT91_PIN(1,1,22) // Programmable Clock Output 2
+#define AT91_USART_DCD1 AT91_PIN(1,1,23) // USART 1 Data Carrier Detect
+#define AT91_USART_DSR1 AT91_PIN(1,1,24) // USART 1 Data Set Ready
+#define AT91_USART_DTR1 AT91_PIN(1,1,25) // USART 1 Data Terminal Ready
+#define AT91_USART_RI1 AT91_PIN(1,1,26) // USART 1 Ring Indication
+#define AT91_PWM_PWM0X AT91_PIN(1,1,27) // Pulse Width Modulation #0
+#define AT91_PWM_PWM1X AT91_PIN(1,1,28) // Pulse Width Modulation #1
+#define AT91_PWM_PWM2X AT91_PIN(1,1,29) // Pulse Width Modulation #2
+#define AT91_PWM_PWM3X AT91_PIN(1,1,30) // Pulse Width Modulation #3
+
+// PIO Controller A, peripheral A
+#define AT91_PIO_PSR_RXD0 (1<< 0) // USART 0 Receive Data
+#define AT91_PIO_PSR_TXD0 (1<< 1) // USART 0 Transmit Data
+#define AT91_PIO_PSR_SCK0 (1<< 2) // USART 0 Serial Clock
+#define AT91_PIO_PSR_RTS0 (1<< 3) // USART 0 Request To Send
+#define AT91_PIO_PSR_CTS0 (1<< 4) // USART 0 Clear To Send
+#define AT91_PIO_PSR_RXD1 (1<< 5) // USART 1 Receive Data
+#define AT91_PIO_PSR_TXD1 (1<< 6) // USART 1 Transmit Data
+#define AT91_PIO_PSR_SCK1 (1<< 7) // USART 1 Serial Clock
+#define AT91_PIO_PSR_RTS1 (1<< 8) // USART 1 Request To Send
+#define AT91_PIO_PSR_CTS1 (1<< 9) // USART 1 Clear To Send
+#define AT91_PIO_PSR_TWD (1<<10) // Two Wire Data
+#define AT91_PIO_PSR_TWCK (1<<11) // Two Wire Clock
+#define AT91_PIO_PSR_SPI_NPCS0 (1<<12) // SPI 0 Chip Select 0
+#define AT91_PIO_PSR_SPI_NPCS1 (1<<13) // SPI 0 Chip Select 1
+#define AT91_PIO_PSR_SPI_NPCS2 (1<<14) // SPI 0 Chip Select 2
+#define AT91_PIO_PSR_SPI_NPCS3 (1<<15) // SPI 0 Chip Select 3
+#define AT91_PIO_PSR_SPI_MISO (1<<16) // SPI 0 Master In Slave Out
+#define AT91_PIO_PSR_SPI_MOSI (1<<17) // SPI 0 Master Out Slave In
+#define AT91_PIO_PSR_SPI_SPCK (1<<18) // SPI 0 Clock
+#define AT91_PIO_PSR_CANRX (1<<19) // CAN Receive
+#define AT91_PIO_PSR_CANTX (1<<20) // CAN Transmit
+#define AT91_PIO_PSR_TF (1<<21) // SSC Transmit Frame Sync
+#define AT91_PIO_PSR_TK (1<<22) // SSC Transmit Clock
+#define AT91_PIO_PSR_TD (1<<23) // SSC Transmit Data
+#define AT91_PIO_PSR_RD (1<<24) // SSC Receive Data
+#define AT91_PIO_PSR_RK (1<<25) // SSC Receive Clock
+#define AT91_PIO_PSR_RF (1<<26) // SSC Receive Frame Sync
+#define AT91_PIO_PSR_DRXD (1<<27) // DBGU Receive Data
+#define AT91_PIO_PSR_DTXD (1<<28) // DBGU Transmit Data
+#define AT91_PIO_PSR_FIQ (1<<29) // Fast Interrupt Request
+#define AT91_PIO_PSR_IRQ0 (1<<30) // Interrupt Request 0
+
+//PIO controller A, peripheral B
+#define AT91_PIO_PSR_SPI1_NPCS1 (1<< 2) // SPI 1 Chip Select 1
+#define AT91_PIO_PSR_SPI1_NPCS2 (1<< 3) // SPI 1 Chip Select 2
+#define AT91_PIO_PSR_SPI1_NPCS3 (1<< 4) // SPI 1 Chip Select 3
+#define AT91_PIO_PSR_SPI_NPCS1X (1<< 7) // SPI 0 Chip Select 1
+#define AT91_PIO_PSR_SPI_NPCS2X (1<< 8) // SPI 0 Chip Select 2
+#define AT91_PIO_PSR_SPI_NPCS3X (1<< 9) // SPI 0 Chip Select 3
+#define AT91_PIO_PSR_PCK1 (1<<13) // Programmable Clock Output 1
+#define AT91_PIO_PSR_IRQ1 (1<<14) // Interrupt Request 1
+#define AT91_PIO_PSR_TCLK1 (1<<15) // Timer/Counter 1 Clock Input
+#define AT91_PIO_PSR_SPI1_NPCS0 (1<<21) // SPI 1 Chip Select 0
+#define AT91_PIO_PSR_SPI1_SPCK (1<<22) // SPI 1 Clock
+#define AT91_PIO_PSR_SPI1_MOSI (1<<23) // SPI 1 Master Out Slave In
+#define AT91_PIO_PSR_SPI1_MISO (1<<24) // SPI 0 Master In Slave Out
+#define AT91_PIO_PSR_SPI1_NPCS1X (1<<25) // SPI 1 Chip Select 1
+#define AT91_PIO_PSR_SPI1_NPCS2X (1<<26) // SPI 1 Chip Select 2
+#define AT91_PIO_PSR_PCK3 (1<<27) // Programmable Clock Output 3
+#define AT91_PIO_PSR_SPI1_NPCS3X (1<<29) // SPI 1 Chip Select 3
+#define AT91_PIO_PSR_PCK2 (1<<30) // Programmable Clock Output 2
+
+//PIO Controller B, Peripheral A
+#define AT91_PIO_PSR_EREFCK (1<< 0) // EMAC Reference Clock
+#define AT91_PIO_PSR_ETXEN (1<< 1) // EMAC Transmit Enable
+#define AT91_PIO_PSR_ETX0 (1<< 2) // EMAC Transmit Data 0
+#define AT91_PIO_PSR_ETX1 (1<< 3) // EMAC Transmit Data 1
+#define AT91_PIO_PSR_ECRS (1<< 4) // EMAC Carrier Sense
+#define AT91_PIO_PSR_ERX0 (1<< 5) // EMAC Receive Data 0
+#define AT91_PIO_PSR_ERX1 (1<< 6) // EMAC Receive Data 1
+#define AT91_PIO_PSR_ERXER (1<< 7) // EMAC Receive Error
+#define AT91_PIO_PSR_EMDC (1<< 8) // EMAC Management Data Clock
+#define AT91_PIO_PSR_EMDIO (1<< 9) // EMAC Management Data IO
+#define AT91_PIO_PSR_ETX2 (1<<10) // EMAC Transmit Data 2
+#define AT91_PIO_PSR_ETX3 (1<<11) // EMAC Transmit Data 3
+#define AT91_PIO_PSR_ETXER (1<<12) // EMAC Transmit Coding Error
+#define AT91_PIO_PSR_ERX2 (1<<13) // EMAC Receive Data 2
+#define AT91_PIO_PSR_ERX3 (1<<14) // EMAC Receive Data 3
+#define AT91_PIO_PSR_ECRSDV (1<<15) // EMAC Carrier Sense And Data Valid
+#define AT91_PIO_PSR_ECOL (1<<16) // EMAC Collision Detected
+#define AT91_PIO_PSR_ERXCK (1<<17) // EMAC Receive Clock
+#define AT91_PIO_PSR_EF100 (1<<18) // EMAC Force 100Mb/s
+#define AT91_PIO_PSR_PWM0 (1<<19) // Pulse Width Modulation #0
+#define AT91_PIO_PSR_PWM1 (1<<20) // Pulse Width Modulation #1
+#define AT91_PIO_PSR_PWM2 (1<<21) // Pulse Width Modulation #2
+#define AT91_PIO_PSR_PWM3 (1<<22) // Pulse Width Modulation #3
+#define AT91_PIO_PSR_TIOA0 (1<<23) // Timer/Counter 0 IO Line A
+#define AT91_PIO_PSR_TIOB0 (1<<24) // Timer/Counter 0 IO Line B
+#define AT91_PIO_PSR_TIOA1 (1<<25) // Timer/Counter 1 IO Line A
+#define AT91_PIO_PSR_TIOB1 (1<<26) // Timer/Counter 1 IO Line B
+#define AT91_PIO_PSR_TIOA2 (1<<27) // Timer/Counter 2 IO Line A
+#define AT91_PIO_PSR_TIOB2 (1<<28) // Timer/Counter 2 IO Line B
+#define AT91_PIO_PSR_PCK1X (1<<29) // Programmable Clock Output 1
+#define AT91_PIO_PSR_PCK2 (1<<30) // Programmable Clock Output 2
+
+//PIO Controller B Peripheral B
+#define AT91_PIO_PSR_PCK0 (1<< 0) // Programmable Clock Output 0
+#define AT91_PIO_PSR_SPI1_NPCS1XX (1<<10) // SPI 1 Chip Select 1
+#define AT91_PIO_PSR_SPI1_NPCS2XX (1<<11) // SPI 1 Chip Select 2
+#define AT91_PIO_PSR_TCLK0 (1<<12) // Timer/Counter 0 Clock Input
+#define AT91_PIO_PSR_SPI_NPCS1 (1<<13) // SPI 0 Chip Select 1
+#define AT91_PIO_PSR_SPI_NPCS2 (1<<14) // SPI 0 Chip Select 2
+#define AT91_PIO_PSR_SPI1_NPCS3XX (1<<16) // SPI 1 Chip Select 3
+#define AT91_PIO_PSR_SPI_NPCS3XX (1<<17) // SPI 0 Chip Select 3
+#define AT91_PIO_PSR_ADTRG (1<<18) // ADC Trigger
+#define AT91_PIO_PSR_TCLK1X (1<<19) // Timer/Counter 1 Clock Input
+#define AT91_PIO_PSR_PCK0X (1<<20) // Programmable Clock Output 0
+#define AT91_PIO_PSR_PCK1XX (1<<21) // Programmable Clock Output 1
+#define AT91_PIO_PSR_PCK2X (1<<22) // Programmable Clock Output 2
+#define AT91_PIO_PSR_DCD1 (1<<23) // USART 1 Data Carrier Detect
+#define AT91_PIO_PSR_DSR1 (1<<24) // USART 1 Data Set Ready
+#define AT91_PIO_PSR_DTR1 (1<<25) // USART 1 Data Terminal Ready
+#define AT91_PIO_PSR_RI1 (1<<26) // USART 1 Ring Indication
+#define AT91_PIO_PSR_PWM0X (1<<27) // Pulse Width Modulation #0
+#define AT91_PIO_PSR_PWM1X (1<<28) // Pulse Width Modulation #1
+#define AT91_PIO_PSR_PWM2X (1<<29) // Pulse Width Modulation #2
+#define AT91_PIO_PSR_PWM3X (1<<30) // Pulse Width Modulation #3
+#endif
+
+#ifdef CYGHWR_HAL_ARM_AT91SAM7XC
+#error Sorry, still missing. Happy typing
+#endif
+
#else
+#define AT91_TC_TCLK0 AT91_PIN(0,0, 0) // Timer #0 clock
+#define AT91_TC_TIOA0 AT91_PIN(0,0, 1) // Timer #0 signal A
+#define AT91_TC_TIOB0 AT91_PIN(0,0, 2) // Timer #0 signal B
+#define AT91_TC_TCLK1 AT91_PIN(0,0, 3) // Timer #1 clock
+#define AT91_TC_TIOA1 AT91_PIN(0,0, 4) // Timer #1 signal A
+#define AT91_TC_TIOB1 AT91_PIN(0,0, 5) // Timer #1 signal B
+#define AT91_TC_TCLK2 AT91_PIN(0,0, 6) // Timer #2 clock
+#define AT91_TC_TIOA2 AT91_PIN(0,0, 7) // Timer #2 signal A
+#define AT91_TC_TIOB2 AT91_PIN(0,0, 8) // Timer #2 signal B
+#define AT91_INT_IRQ0 AT91_PIN(0,0, 9) // IRQ #0
+#define AT91_INT_IRQ1 AT91_PIN(0,0,10) // IRQ #1
+#define AT91_INT_IRQ2 AT91_PIN(0,0,11) // IRQ #2
+#define AT91_INT_FIQ AT91_PIN(0,0,12) // FIQ
+#define AT91_USART_SCK0 AT91_PIN(0,0,13) // Serial port #0 clock
+#define AT91_USART_TXD0 AT91_PIN(0,0,14) // Serial port #0 TxD
+#define AT91_USART_RXD0 AT91_PIN(0,0,15) // Serial port #0 RxD
+#define AT91_USART_SCK1 AT91_PIN(0,0,20) // Serial port #1 clock
+#define AT91_USART_TXD1 AT91_PIN(0,0,21) // Serial port #1 TxD
+#define AT91_USART_RXD1 AT91_PIN(0,0,22) // Serial port #1 RxD
+#define AT91_CLK_MCKO AT91_PIN(0,0,25) // Master clock out
#define AT91_PIO_PSR_TCLK0 0x00000001 // Timer #0 clock
#define AT91_PIO_PSR_TIOA0 0x00000002 // Timer #0 signal A
#define AT91_PIO_PSR_CS6_A21 0x20000000 // Chip select #6 or A21
#define AT91_PIO_PSR_CS5_A22 0x40000000 // Chip select #5 or A22
#define AT91_PIO_PSR_CS4_A23 0x80000000 // Chip select #4 or A23
-
#endif
#define AT91_PIO_OER 0x10 // Output enable
#define AT91_PIO_IMR 0x48 // Interrupt mask
#define AT91_PIO_ISR 0x4C // Interrupt status
+#if defined(CYGHWR_HAL_ARM_AT91SAM7)
+#define AT91_PIO_MDER 0x50 // Multi-drive Enable Register
+#define AT91_PIO_MDDR 0x54 // Multi-drive Disable Register
+#define AT91_PIO_MDSR 0x58 // Multi-drive Status Register
+#define AT91_PIO_PPUDR 0x60 // Pad Pull-up Disable Register
+#define AT91_PIO_PPUER 0x64 // Pad Pull-up Enable Register
+#define AT91_PIO_PPUSR 0x68 // Pad Pull-Up Status Register
+#define AT91_PIO_ASR 0x70 // Select A Register
+#define AT91_PIO_BSR 0x74 // Select B Regsiter
+#define AT91_PIO_ABS 0x78 // AB Select Regsiter
+#define AT91_PIO_OWER 0xa0 // Output Write Enable Register
+#define AT91_PIO_OWDR 0xa4 // Output Write Disable Register
+#define AT91_PIO_OWSR 0xa8 // Output Write Status Register
+#endif // CYGHWR_HAL_ARM_AT91SAM7
+
//=============================================================================
// Advanced Interrupt Controller (AIC)
#define AT91_AIC_EOI 0x130
#define AT91_AIC_SVR 0x134
+#ifdef CYGHWR_HAL_ARM_AT91SAM7
+#define AT91_AIC_DCR 0x138 // Debug Control Register
+#define AT91_AIC_FFER 0x140 // Fast Forcing Enable Register
+#define AT91_AIC_FFDR 0x144 // Fast Forcing Enable Register
+#define AT91_AIC_FFSR 0x148 // Fast Forcing Enable Register
+#endif // CYGHWR_HAL_ARM_AT91SAM7
+
//=============================================================================
// Timer / counter
#endif
#define AT91_TC_TC0 0x00
+#define AT91_TC_TC1 0x40
+#define AT91_TC_TC2 0x80
+#define AT91_TC_TC_SIZE 0x40
+
#define AT91_TC_CCR 0x00
#define AT91_TC_CCR_CLKEN 0x01
#define AT91_TC_CCR_CLKDIS 0x02
#define AT91_TC_BCR 0xC0
#define AT91_TC_BCR_SYNC 0x01
#define AT91_TC_BMR 0xC4
+#define AT91_TC_BMR_MASK (0x3f)
+#define AT91_TC_BMR_TC0XC0S_TCLK0 (0 << 0) // XC0S = TCLK0
+#define AT91_TC_BMR_TC0XC0S_NONE (1 << 0) // XC0S = none
+#define AT91_TC_BMR_TC0XC0S_TIOA1 (2 << 0) // XC0S = TIOA1
+#define AT91_TC_BMR_TC0XC0S_TIOA2 (3 << 0) // XC0S = TIOA2
+#define AT91_TC_BMR_TC1XC1S_TCLK1 (0 << 2) // XC1S = TCLK1
+#define AT91_TC_BMR_TC1XC1S_NONE (1 << 2) // XC1S = none
+#define AT91_TC_BMR_TC1XC1S_TIOA0 (2 << 2) // XC1S = TIOA0
+#define AT91_TC_BMR_TC1XC1S_TIOA2 (3 << 2) // XC1S = TIOA2
+#define AT91_TC_BMR_TC2XC2S_TCLK2 (0 << 4) // XC2S = TCLK2
+#define AT91_TC_BMR_TC2XC2S_NONE (1 << 4) // XC2S = none
+#define AT91_TC_BMR_TC2XC2S_TIOA0 (2 << 4) // XC2S = TIOA0
+#define AT91_TC_BMR_TC2XC2S_TIOA1 (3 << 4) // XC2S = TIOA1
+
+
//=============================================================================
// External Bus Interface
#define AT91_EBI_MCR_ALE_1M 0x7 // Address line enable
#define AT91_EBI_MCR_DRP (0x1 << 4) // Data read protocol
-
//=============================================================================
// Power Saving or Management
#define AT91_PS_PCSR 0x00c // Peripheral clock status
#elif defined(CYGHWR_HAL_ARM_AT91_M42800A) || \
- defined(CYGHWR_HAL_ARM_AT91_M55800A)
+ defined(CYGHWR_HAL_ARM_AT91_M55800A) || \
+ defined(CYGHWR_HAL_ARM_AT91SAM7)
// (Advanced) Power Management
#define AT91_PMC_PCSR 0x18
#define AT91_PMC_CGMR 0x20
-
+
+#ifndef AT91_PMC_SR
#define AT91_PMC_SR 0x30
+#endif
+
+#ifndef AT91_PMC_IER
#define AT91_PMC_IER 0x34
+#endif
+
+#ifndef AT91_PMC_IDR
#define AT91_PMC_IDR 0x38
+#endif
+
+#ifndef AT91_PMC_IMR
#define AT91_PMC_IMR 0x3c
+#endif
#if defined(CYGHWR_HAL_ARM_AT91_M42800A)
#define AT91_PMC_SR_MOSCS 0x01
#define AT91_PMC_SR_LOCK 0x02
-#endif
-
#elif defined(CYGHWR_HAL_ARM_AT91_JTST)
-// Now power management control for the JTST
-#else
+// No power management control for the JTST
-#error Unknown AT91 variant
+#elif defined(CYGHWR_HAL_ARM_AT91SAM7S)
+#define AT91_PMC_SCER_PCK (1 << 0) // Processor Clock
+#define AT91_PMC_SCER_UDP (1 << 7) // USB Device Clock
+#define AT91_PMC_SCER_PCK0 (1 << 8) // Programmable Clock Output
+#define AT91_PMC_SCER_PCK1 (1 << 9) // Programmable Clock Output
+#define AT91_PMC_SCER_PCK2 (1 << 10) // Programmable Clock Output
+#define AT91_PMC_SCER_PCK3 (1 << 11) // Programmable Clock Output
-#endif
+#define AT91_PMC_PCER_PIOA (1 << 2) // Parallel IO Controller
+#define AT91_PMC_PCER_ADC (1 << 4) // Analog-to-Digital Conveter
+#define AT91_PMC_PCER_SPI (1 << 5) // Serial Peripheral Interface
+#define AT91_PMC_PCER_US0 (1 << 6) // USART 0
+#define AT91_PMC_PCER_US1 (1 << 7) // USART 1
+#define AT91_PMC_PCER_SSC (1 << 8) // Serial Synchronous Controller
+#define AT91_PMC_PCER_TWI (1 << 9) // Two-Wire Interface
+#define AT91_PMC_PCER_PWMC (1 <<10) // PWM Controller
+#define AT91_PMC_PCER_UDP (1 <<11) // USB Device Port
+#define AT91_PMC_PCER_TC0 (1 <<12) // Timer Counter 0
+#define AT91_PMC_PCER_TC1 (1 <<13) // Timer Counter 1
+#define AT91_PMC_PCER_TC2 (1 <<14) // Timer Counter 2
+
+#elif defined(CYGHWR_HAL_ARM_AT91SAM7X)
+#define AT91_PMC_SCER_PCK (1 << 0) // Processor Clock
+#define AT91_PMC_SCER_UDP (1 << 7) // USB Device Clock
+#define AT91_PMC_SCER_PCK0 (1 << 8) // Programmable Clock Output
+#define AT91_PMC_SCER_PCK1 (1 << 9) // Programmable Clock Output
+#define AT91_PMC_SCER_PCK2 (1 << 10) // Programmable Clock Output
+#define AT91_PMC_SCER_PCK3 (1 << 11) // Programmable Clock Output
+#define AT91_PMC_PCER_PIOA (1 << 2) // Parallel IO Controller
+#define AT91_PMC_PCER_PIOB (1 << 3) // Parallel IO Controller
+#define AT91_PMC_PCER_SPI (1 << 4) // Serial Peripheral Interface
+#define AT91_PMC_PCER_SPI1 (1 << 5) // Serial Peripheral Interface
+#define AT91_PMC_PCER_US0 (1 << 6) // USART 0
+#define AT91_PMC_PCER_US1 (1 << 7) // USART 1
+#define AT91_PMC_PCER_SSC (1 << 8) // Serial Synchronous Controller
+#define AT91_PMC_PCER_TWI (1 << 9) // Two-Wire Interface
+#define AT91_PMC_PCER_PWMC (1 <<10) // PWM Controller
+#define AT91_PMC_PCER_UDP (1 <<11) // USB Device Port
+#define AT91_PMC_PCER_TC0 (1 <<12) // Timer Counter 0
+#define AT91_PMC_PCER_TC1 (1 <<13) // Timer Counter 1
+#define AT91_PMC_PCER_TC2 (1 <<14) // Timer Counter 2
+#define AT91_PMC_PCER_CAN (1 <<15) // Controller Area Network
+#define AT91_PMC_PCER_EMAC (1 <<16) // Ethernet MAC
+#define AT91_PMC_PCER_ADC (1 <<17) // Analog-to-Digital Conveter
+#else // Something unknown
+
+#error Unknown AT91 variant
+
+#endif
+#endif
//=============================================================================
// Watchdog
#define AT91_SPI_MR_PS 0x00000002 // Peripheral Select
#define AT91_SPI_MR_PCSDEC 0x00000004 // Chip Select Decode
#define AT91_SPI_MR_DIV32 0x00000008 // Clock Selection
+#if defined(CYGHWR_HAL_ARM_AT91SAM7)
+#define AT91_SPI_MR_MODFDIS (1<<4) // Mode Failure Detect Disable
+#endif
#define AT91_SPI_MR_LLB 0x00000080 // Local Loopback Enable
#define AT91_SPI_MR_PCS(x) (((x)&0x0F)<<16) // Peripheral Chip Select
#define AT91_SPI_MR_DLYBCS(x) (((x)&0xFF)<<24) // Delay Between Chip Selects
#define AT91_SPI_TDR 0x0C // Transmit Data Register
#define AT91_SPI_SR 0x10 // Status Register
#define AT91_SPI_SR_RDRF 0x00000001 // Receive Data Register Full
-#define AT91_SPI_SR_TDRE 0x00000002 // Transmit Data Register Empty
+#define AT91_SPI_SR_TDRE 0x00000002 // Tx Data Register Empty
#define AT91_SPI_SR_MODF 0x00000004 // Mode Fault Error
#define AT91_SPI_SR_OVRES 0x00000008 // Overrun Error Status
#define AT91_SPI_SR_ENDRX 0x00000010 // End of Receiver Transfer
#ifndef AT91_SPI_TCR
#define AT91_SPI_TCR 0x2C // Transmit Counter Register
#endif
+
+// PDC Control register bits
+#define AT91_SPI_PTCR_RXTEN (1 << 0)
+#define AT91_SPI_PTCR_RXTDIS (1 << 1)
+#define AT91_SPI_PTCR_TXTEN (1 << 8)
+#define AT91_SPI_PTCR_TXTDIS (1 << 9)
+
#define AT91_SPI_CSR0 0x30 // Chip Select Register 0
#define AT91_SPI_CSR1 0x34 // Chip Select Register 1
#define AT91_SPI_CSR2 0x38 // Chip Select Register 2
#define AT91_SPI_CSR_SCBR(x) (((x)&0xFF)<<8) // Serial Clock Baud Rate
#define AT91_SPI_CSR_DLYBS(x) (((x)&0xFF)<<16) // Delay Before SPCK
#define AT91_SPI_CSR_DLYBCT(x) (((x)&0xFF)<<24) // Delay Between two transfers
-
-#if defined(CYGHWR_HAL_ARM_AT91_M55800A)
-
-#define AT91_SPI_PIO AT91_PIOA
-#define AT91_SPI_PIO_NPCS(x) (((x)&0x0F)<<26)
+
+//=============================================================================
+// Watchdog Timer Controller
+
+#if defined(CYGHWR_HAL_ARM_AT91SAM7)
+
+#ifndef AT91_WDTC
+#define AT91_WDTC 0xFFFFFD40
+#endif
+
+#define AT91_WDTC_WDCR 0x00 // Watchdog Control Register
+#define AT91_WDTC_WDCR_RELOAD (1 << 0) // Reload the watchdog
+#define AT91_WDTC_WDCR_KEY (0xa5 << 24) // Password for the write op
+#define AT91_WDTC_WDMR 0x04 // Watchdog Mode Register
+#define AT91_WDTC_WDMR_FIEN (1 << 12) // Fault Interrupt Mode Enable
+#define AT91_WDTC_WDMR_RSTEN (1 << 13) // Reset Enable
+#define AT91_WDTC_WDMR_RPROC (1 << 14) // Trigger a processor reset
+#define AT91_WDTC_WDMR_DIS (1 << 15) // Disable
+#define AT91_WDTC_WDMR_WDD_SHIFT (16) // Delta Value shift
+#define AT91_WDTC_WDMR_DBGHLT (1 << 28) // Stop when in debug state
+#define AT91_WDTC_WDMR_IDLEHLT (1 << 29) // Stop when in idle more
+#define AT91_WDTC_WDSR 0x08 // Watchdog Status Register
+#define AT91_WDTC_WDSR_UNDER (1 << 0) // Underflow has occurred
+#define AT91_WDTC_WDSR_ERROR (1 << 1) // Error has occurred
+#endif //CYGHWR_HAL_ARM_AT91SAM7
+
+//=============================================================================
+// Reset Controller
+
+#if defined(CYGHWR_HAL_ARM_AT91SAM7)
+
+#ifndef AT91_RST
+#define AT91_RST 0xFFFFFD00
+#endif
+
+#define AT91_RST_RCR 0x00 // Reset Control Register
+#define AT91_RST_RCR_PROCRST (1 << 0) // Processor Reset
+#define AT91_RST_RCR_ICERST (1 << 1) // ICE Reset
+#define AT91_RST_RCR_PERRST (1 << 2) // Peripheral Reset
+#define AT91_RST_RCR_EXTRST (1 << 3) // External Reset
+#define AT91_RST_RCR_KEY (0xA5 << 24) // Key
+#define AT91_RST_RSR 0x04 // Reset Status Register
+#define AT91_RST_RSR_USER (1 << 0) // User Reset
+#define AT91_RST_RSR_BROWN (1 << 1) // Brownout detected
+#define AT91_RST_RSR_TYPE_POWERUP (0 << 8) // Power on Reset
+#define AT91_RST_RSR_TYPE_WATCHDOG (2 << 8) // Watchdog Reset
+#define AT91_RST_RSR_TYPE_SW (3 << 8) // Software Reset
+#define AT91_RST_RSR_TYPE_USER (4 << 8) // NRST pin Reset
+#define AT91_RST_RSR_TYPE_BROWNOUT (5 << 8) // Brown-out Reset
+#define AT91_RST_RSR_NRST_SET (1 << 16) // NRST pin set
+#define AT91_RST_RSR_SRCMP (1 << 17) // Software reset in progress
+#define AT91_RST_RMR 0x08 // Reset Mode Register
+#define AT91_RST_RMR_URSTEN (1 << 0) // User Reset Enabled
+#define AT91_RST_RMR_URSTIEN (1 << 4) // User Reset Interrupt Enabled
+#define AT91_RST_RMR_BODIEN (1 << 16) // Brownout Dection Interrupt Enabled
+#define AT91_RST_RMR_KEY (0xA5 << 24) // Key
+
+#endif
+
+//=============================================================================
+// Memory Controller
+
+#if defined(CYGHWR_HAL_ARM_AT91SAM7)
+
+#ifndef AT91_MC
+#define AT91_MC 0xFFFFFF00
+#endif
+
+#define AT91_MC_RCR 0x00 // Remap Control Register
+#define AT91_MC_ASR 0x04 // Abort Status Register
+#define AT91_MC_AASR 0x08 // Abort Address Status Register
+#define AT91_MC_FMR 0x60 // Flash Mode Register
+#define AT91_MC_FMR_FRDY (1 << 0) // Enable interrupt for Flash Ready
+#define AT91_MC_FMR_LOCKE (1 << 2) // Enable interrupt for Flash Lock Error
+#define AT91_MC_FMR_PROGE (1 << 3) // Enable interrupt for Flash Prog Error
+#define AT91_MC_FMR_NEBP (1 << 7) // No erase before programming
+#define AT91_MC_FMR_0FWS (0 << 8) // 1R,2W wait states
+#define AT91_MC_FMR_1FWS (1 << 8) // 2R,3W wait states
+#define AT91_MC_FMR_2FWS (2 << 8) // 3R,4W wait states
+#define AT91_MC_FMR_3FWS (3 << 8) // 4R,4W wait states
+#define AT91_MC_FMR_FMCN_MASK (0xff << 16)
+#define AT91_MC_FMR_FMCN_SHIFT 16
+#define AT91_MC_FCR 0x64 // Flash Command Register
+#define AT91_MC_FCR_START_PROG (0x1 << 0) // Start Programming of Page
+#define AT91_MC_FCR_LOCK (0x2 << 0) // Lock sector
+#define AT91_MC_FCR_PROG_LOCK (0x3 << 0) // Program and Lock
+#define AT91_MC_FCR_UNLOCK (0x4 << 0) // Unlock a segment
+#define AT91_MC_FCR_ERASE_ALL (0x8 << 0) // Erase everything
+#define AT91_MC_FCR_SET_GP_NVM (0xb << 0) // Set general purpose NVM bits
+#define AT91_MC_FCR_CLR_GP_NVM (0xd << 0) // Clear general purpose NVM bits
+#define AT91_MC_FCR_SET_SECURITY (0xf << 0) // Set security bit
+#define AT91_MC_FCR_PAGE_MASK (0x3ff)
+#define AT91_MC_FCR_PAGE_SHIFT 8
+#define AT91_MC_FCR_KEY (0x5a << 24) // Key to enable command
+#define AT91_MC_FSR 0x68 // Flash Status Register
+#define AT91_MC_FSR_FRDY (1 << 0) // Flash Ready for next command
+#define AT91_MC_FSR_LOCKE (1 << 2) // Programming of a locked block
+#define AT91_MC_FSR_PROGE (1 << 3) // Programming error
+#define AT91_MC_FSR_SECURITY (1 << 4) // Security bit is set
+#define AT91_MC_FSR_GPNVM0 (1 << 8) // General purpose NVM bit 0
+#define AT91_MC_FSR_GPNVM1 (1 << 9) // General purpose NVM bit 1
+#endif
+
+//=============================================================================
+// Debug Unit
+
+#if defined(CYGHWR_HAL_ARM_AT91SAM7)
+
+#ifndef AT91_DBG
+#define AT91_DBG 0xFFFFF200
+#endif
+
+#define AT91_DBG_CR 0x00 // Control Register
+#define AT91_DBG_CR_RSTRX (0x1 << 2) // Reset Receiver
+#define AT91_DBG_CR_RSTTX (0x1 << 3) // Reset Transmitter
+#define AT91_DBG_CR_RXEN (0x1 << 4) // Receiver Enable
+#define AT91_DBG_CR_RXDIS (0x1 << 5) // Receiver Disable
+#define AT91_DBG_CR_TXEN (0x1 << 6) // Transmitter Enable
+#define AT91_DBG_CR_TXDIS (0x1 << 7) // Transmitter Disable
+#define AT91_DBG_CR_RSTSTA (0x1 << 8) // Reset Status Bits
+#define AT91_DBG_MR 0x04 // Mode Register
+#define AT91_DBG_MR_PAR_EVEN (0x0 << 9) // Even Parity
+#define AT91_DBG_MR_PAR_ODD (0x1 << 9) // Odd Parity
+#define AT91_DBG_MR_PAR_SPACE (0x2 << 9) // Parity forced to Space
+#define AT91_DBG_MR_PAR_MARK (0x3 << 9) // Parity forced to Mark
+#define AT91_DBG_MR_PAR_NONE (0x4 << 9) // No Parity
+#define AT91_DBG_MR_PAR_MULTI (0x6 << 9) // Multi-drop mode
+#define AT91_DBG_MR_CHMODE_NORMAL (0x0 << 14) // Normal mode
+#define AT91_DBG_MR_CHMODE_AUTO (0x1 << 14) // Automatic Echo
+#define AT91_DBG_MR_CHMODE_LOCAL (0x2 << 14) // Local Loopback
+#define AT91_DBG_MR_CHMODE_REMOTE (0x3 << 14) // Remote Loopback
+#define AT91_DBG_IER 0x08 // Interrupt Enable Register
+#define AT91_DBG_IDR 0x0c // Interrupt Disable Register
+#define AT91_DBG_IMR 0x10 // Interrupt Mask Register
+#define AT91_DBG_CSR 0x14 // Channel Status Register
+#define AT91_DBG_CSR_RXRDY (1 << 0) // Receiver Ready
+#define AT91_DBG_CSR_TXRDY (1 << 1) // Transmitter Ready
+#define AT91_DBG_RHR 0x18 // Receiver Holding Register
+#define AT91_DBG_THR 0x1c // Transmitter Holding Register
+#define AT91_DBG_BRGR 0x20 // Baud Rate Generator Register
+#define AT91_DBG_C1R 0x40 // Chip ID1 register
+#define AT91_DBG_C1R_ARM945ES (1 << 5)
+#define AT91_DBG_C1R_ARM7TDMI (2 << 5)
+#define AT91_DBG_C1R_ARM920T (4 << 5)
+#define AT91_DBG_C1R_ARM926EJ (5 << 5)
+#define AT91_DBG_C1R_CPU_MASK (0x7 << 5)
+#define AT91_DBG_C1R_FLASH_0K (0x0 << 8)
+#define AT91_DBG_C1R_FLASH_8K (0x1 << 8)
+#define AT91_DBG_C1R_FLASH_16K (0x2 << 8)
+#define AT91_DBG_C1R_FLASH_32K (0x3 << 8)
+#define AT91_DBG_C1R_FLASH_64K (0x5 << 8)
+#define AT91_DBG_C1R_FLASH_128K (0x7 << 8)
+#define AT91_DBG_C1R_FLASH_256K (0x9 << 8)
+#define AT91_DBG_C1R_FLASH_512K (0xa << 8)
+#define AT91_DBG_C1R_FLASH_1024K (0xc << 8)
+#define AT91_DBG_C1R_FLASH_2048K (0xe << 8)
+#define AT91_DBG_C1R_FLASH_MASK (0xf << 8)
+#define AT91_DBG_C1R_FLASH2_0K (0x0 << 12)
+#define AT91_DBG_C1R_FLASH2_8K (0x1 << 12)
+#define AT91_DBG_C1R_FLASH2_16K (0x2 << 12)
+#define AT91_DBG_C1R_FLASH2_32K (0x3 << 12)
+#define AT91_DBG_C1R_FLASH2_64K (0x5 << 12)
+#define AT91_DBG_C1R_FLASH2_128K (0x7 << 12)
+#define AT91_DBG_C1R_FLASH2_256K (0x9 << 12)
+#define AT91_DBG_C1R_FLASH2_512K (0xa << 12)
+#define AT91_DBG_C1R_FLASH2_1024K (0xc << 12)
+#define AT91_DBG_C1R_FLASH2_2048K (0xe << 12)
+#define AT91_DBG_C1R_FLASH2_MASK (0xf << 12)
+#define AT91_DBG_C1R_SRAM_1K (0x1 << 16)
+#define AT91_DBG_C1R_SRAM_2K (0x2 << 16)
+#define AT91_DBG_C1R_SRAM_112K (0x4 << 16)
+#define AT91_DBG_C1R_SRAM_4K (0x5 << 16)
+#define AT91_DBG_C1R_SRAM_80K (0x6 << 16)
+#define AT91_DBG_C1R_SRAM_160K (0x7 << 16)
+#define AT91_DBG_C1R_SRAM_8K (0x8 << 16)
+#define AT91_DBG_C1R_SRAM_16K (0x9 << 16)
+#define AT91_DBG_C1R_SRAM_32K (0xa << 16)
+#define AT91_DBG_C1R_SRAM_64K (0xb << 16)
+#define AT91_DBG_C1R_SRAM_128K (0xc << 16)
+#define AT91_DBG_C1R_SRAM_256K (0xd << 16)
+#define AT91_DBG_C1R_SRAM_96K (0xe << 16)
+#define AT91_DBG_C1R_SRAM_512K (0xf << 16)
+#define AT91_DBG_C1R_SRAM_MASK (0xf << 16)
+#define AT91_DBG_C1R_ARCH_AT75Cxx (0xf0 << 20)
+#define AT91_DBG_C1R_ARCH_AT91x40 (0x40 << 20)
+#define AT91_DBG_C1R_ARCH_AT91x63 (0x63 << 20)
+#define AT91_DBG_C1R_ARCH_AT91x55 (0x55 << 20)
+#define AT91_DBG_C1R_ARCH_AT91x42 (0x42 << 20)
+#define AT91_DBG_C1R_ARCH_AT91x92 (0x92 << 20)
+#define AT91_DBG_C1R_ARCH_AT91x34 (0x24 << 20)
+#define AT91_DBG_C1R_ARCH_AT91SAM7Axx (0x60 << 20)
+#define AT91_DBG_C1R_ARCH_AT91SAM7Sxx (0x70 << 20)
+#define AT91_DBG_C1R_ARCH_AT91SAM7XC (0x71 << 20)
+#define AT91_DBG_C1R_ARCH_AT91SAM7SExx (0x72 << 20)
+#define AT91_DBG_C1R_ARCH_AT91SAM7Lxx (0x73 << 20)
+#define AT91_DBG_C1R_ARCH_AT91SAM7Xxx (0x75 << 20)
+#define AT91_DBG_C1R_ARCH_AT91SAM9xx (0x19 << 20)
+#define AT91_DBG_C1R_ARCH_MASK (0xff << 20)
+#define AT91_DBG_C1R_NVPTYP_ROM (0 << 28) // ROM only
+#define AT91_DBG_C1R_NVPTYP_RLOCF (1 << 28) // ROMless of on chip Flash
+#define AT91_DBG_C1R_NVPTYP_SRAMROM (4 << 28) // SRAM emulating ROM
+#define AT91_DBG_C1R_NVPTYP_EFLASH (2 << 28) // Embedded Flash
+#define AT91_DBG_C1R_NVPTYP_ROMFLASH (3 << 28) // ROM & FLASH
+#define AT91_DBG_C1R_NVPTYP_MASK (7 << 28)
+#define AT91_DBG_C1R_EXT (1 << 31) // Extension Register Exists
+#define AT91_DBG_C2R 0x44 // Chip ID2 register
+#define AT91_DBG_FNTR 0x48 // Force NTRST Register
+#define AT91_DBG_RPR 0x100 // Receiver Pointer Register
+#define AT91_DBG_RCR 0x104 // Receiver Counter Register
+#define AT91_DBG_TPR 0x108 // Transmit Pointer Register
+#define AT91_DBG_TCR 0x10c // Transmit Counter Register
+#define AT91_DBG_RNPR 0x110 // Receiver Next Pointer Register
+#define AT91_DBG_RNCR 0x114 // Receiver Next Counter Register
+#define AT91_DBG_TNPR 0x118 // Transmit Next Pointer Register
+#define AT91_DBG_TNCR 0x11c // Transmit Next Counter Register
+#define AT91_DBG_PTCR 0x120 // PDC Transfer Control Register
+#define AT91_DBG_PTSR 0x124 // PDC Transfer Status Register
+#endif
+
+//=============================================================================
+// Periodic Interval Timer Controller
+
+#if defined(CYGHWR_HAL_ARM_AT91SAM7)
+
+#ifndef AT91_PITC
+#define AT91_PITC 0xfffffd30
+#endif
+
+#define AT91_PITC_PIMR 0x00 // Period Interval Mode Register
+#define AT91_PITC_PIMR_PITEN (1 << 24) // Periodic Interval Timer Enable
+#define AT91_PITC_PIMR_PITIEN (1 << 25) // Periodic Interval Timer Intr Enable
+#define AT91_PITC_PISR 0x04 // Period Interval Status Register
+#define AT91_PITC_PISR_PITS (1 << 0) // Periodic Interval Timer Status
+#define AT91_PITC_PIVR 0x08 // Period Interval Status Register
+#define AT91_PITC_PIIR 0x0C // Period Interval Image Register
+#define AT91_PITC_VALUE_MASK 0x000fffff // 20-bit period value
+#endif
+
+//=============================================================================
+// Real Time Timer Controller
+
+#if defined(CYGHWR_HAL_ARM_AT91SAM7)
+
+#ifndef AT91_RTTC
+#define AT91_RTTC 0xFFFFFD20
+#endif
+
+#define AT91_RTTC_RTMR 0x00 // Real Time Mode Register
+#define AT91_RTTC_RTMR_ALMIEN (1 << 16) // Alarm Interrupt Enable
+#define AT91_RTTC_RTMR_RTTINCIEN (1 << 17) // Timer Increment Interrupt Enable
+#define AT91_RTTC_RTMR_RTTRST (1 << 18) // Timer Reset
+#define AT91_RTTC_RTAR 0x04 // Real Time Alarm Register
+#define AT91_RTTC_RTVR 0x08 // Real Time Value Register
+#define AT91_RTTC_RTSR 0x0C // Real Time Status Register
+#define AT91_RTTC_RTSR_ALMS (1 << 0) // Alarm Status
+#define AT91_RTTC_RTSR_RTTINC (1 << 1) // Timer Increment
+#endif
+
+//=============================================================================
+// USB Device Port
+
+#if defined(CYGHWR_HAL_ARM_AT91SAM7)
+
+#ifndef AT91_UDP
+#define AT91_UDP 0xFFFB0000
+#endif
+
+#define AT91_UDP_FRM_NUM 0x00 // Frame Number
+#define AT91_UDP_FRM_ERR (1 << 16) // Frame Error
+#define AT91_UDP_FRM_OK (1 << 17) // Frame OK
+#define AT91_UDP_GLB_STATE 0x04 // Global State
+#define AT91_UDP_GLB_FADDEN (1 << 0) // Function Address Enable
+#define AT91_UDP_GLB_CONFG (1 << 1) // Configured
+#define AT91_UDP_GLB_ESR (1 << 2) // Enable Send Resume
+#define AT91_UDP_GLB_RSMINPR (1 << 3) // A Resume has been seen
+#define AT91_UDP_GLB_RMWUPE (1 << 4) // Remote Wake Up Enable
+#define AT91_UDP_FADDR 0x08 // Function Address
+#define AT91_UDP_FADDR_FEN (1 << 8) // Function Enable
+#define AT91_UDP_IER 0x10 // Interrupt Enable
+#define AT91_UDP_EPINT0 (1 << 0) // Endpoint 0 Interrupt
+#define AT91_UDP_EPINT1 (1 << 1) // Endpoint 1 Interrupt
+#define AT91_UDP_EPINT2 (1 << 2) // Endpoint 2 Interrupt
+#define AT91_UDP_EPINT3 (1 << 3) // Endpoint 3 Interrupt
+#define AT91_UDP_EPINT4 (1 << 4) // Endpoint 4 Interrupt
+#define AT91_UDP_EPINT5 (1 << 5) // Endpoint 5 Interrupt
+#define AT91_UDP_EPINT6 (1 << 6) // Endpoint 6 Interrupt
+#define AT91_UDP_EPINT7 (1 << 7) // Endpoint 7 Interrupt
+#define AT91_UDP_RXSUSP (1 << 8) // USB Suspend Interrupt
+#define AT91_UDP_RXRSM (1 << 9) // USB Resume Interrupt
+#define AT91_UDP_EXTRSM (1 << 10) // USB External Resume Interrupt
+#define AT91_UDP_SOFINT (1 << 11) // USB start of frame Interrupt
+#define AT91_UDP_ENDBUSRES (1 << 12) // USB End of Bus Reset Interrupt
+#define AT91_UDP_WAKEUP (1 << 13) // USB Resume Interrupt
+#define AT91_UDP_IDR 0x14 // Interrupt Disable
+#define AT91_UDP_IMR 0x18 // Interrupt Mask
+#define AT91_UDP_ISR 0x1C // Interrupt Status
+#define AT91_UDP_ICR 0x20 // Interrupt Clear
+#define AT91_UDP_RST_EP 0x28 // Reset Endpoint
+#define AT91_UDP_CSR 0x30 // Endpoint Control and Status
+#define AT91_UDP_CSR_TXCOMP (1 << 0) // Generates an IN packet
+#define AT91_UDP_CSR_RX_DATA_BK0 (1 << 1) // Receive Data Bank 0
+#define AT91_UDP_CSR_RXSETUP (1 << 2) // Sends a STALL to the host
+#define AT91_UDP_CSR_ISOERROR (1 << 3) // Isochronous error
+#define AT91_UDP_CSR_TXPKTRDY (1 << 4) // Transmit Packet Ready
+#define AT91_UDP_CSR_FORCESTALL (1 << 5) // Force Stall
+#define AT91_UDP_CSR_RX_DATA_BK1 (1 << 6) // Receive Data Bank 1
+#define AT91_UDP_CSR_DIR (1 << 7) // Transfer Direction
+#define AT91_UDP_CSR_DIR_OUT (0 << 7) // Transfer Direction OUT
+#define AT91_UDP_CSR_DIR_IN (1 << 7) // Transfer Direction IN
+#define AT91_UDP_CSR_EPTYPE_CTRL (0 << 8) // Control
+#define AT91_UDP_CSR_EPTYPE_ISO_OUT (1 << 8) // Isochronous OUT
+#define AT91_UDP_CSR_EPTYPE_BULK_OUT (2 << 8) // Bulk OUT
+#define AT91_UDP_CSR_EPTYPE_INT_OUT (3 << 8) // Interrupt OUT
+#define AT91_UDP_CSR_EPTYPE_ISO_IN (5 << 8) // Isochronous IN
+#define AT91_UDP_CSR_EPTYPE_BULK_IN (6 << 8) // Bulk IN
+#define AT91_UDP_CSR_EPTYPE_INT_IN (7 << 8) // Interrupt IN
+#define AT91_UDP_CSR_DTGLE (1 << 11) // Data Toggle
+#define AT91_UDP_CSR_EPEDS (1 << 15) // Endpoint Enable Disable
+#define AT91_UDP_FDR 0x50 // Endpoint FIFO Data
+#define AT91_UDP_TXVC 0x74 // Transceiver Control
+#define AT91_UDP_TXVC_TXVDIS (1 << 8) // Disable Transceiver
+#define AT91_UDP_TXVC_PUON (1 << 9) // Pull-up ON
+#endif
+
+//=============================================================================
+// Synchronous Serial Controller (SSC)
+
+#if defined(CYGHWR_HAL_ARM_AT91SAM7)
+
+#ifndef AT91_SSC
+#define AT91_SSC 0xFFFD4000
+#endif
+
+#define AT91_SSC_CR (0x00)
+#define AT91_SSC_CR_RXEN (1<<0) //Enable Receiver
+#define AT91_SSC_CR_RXDIS (1<<1) //Disable Receiver
+#define AT91_SSC_CR_TXEN (1<<8) //Enable Transmitter
+#define AT91_SSC_CR_TXDIS (1<<9) //Disable Transmitter
+#define AT91_SSC_CR_SWRST (1<<15) //Soft Reset
+#define AT91_SSC_CMR (0x04)
+#define AT91_SSC_RCMR (0x10)
+#define AT91_SSC_RCMR_CKS_DIV (0<<0) //Select Divider Clock
+#define AT91_SSC_RCMR_CKS_TX (1<<0) //Select Transmit Clock
+#define AT91_SSC_RCMR_CKS_RK (2<<0) //Select Receiver Clock
+#define AT91_SSC_RCMR_CKO_NONE (0<<2) //No Clock Output
+#define AT91_SSC_RCMR_CKO_CONT (1<<2) //Continuous Clock Output
+#define AT91_SSC_RCMR_CKO_TFER (2<<2) //Clock Output During Transfer only
+#define AT91_SSC_RCMR_CKI (1<<5) //Clock Invert
+#define AT91_SSC_RCMR_CKG_NONE (0<<6) //No Clock Gating, Continuous Clock
+#define AT91_SSC_RCMR_CKG_RFLOW (1<<6) //Clock Enabled by RF Low
+#define AT91_SSC_RCMR_CKG_RFHIGH (2<<6) //Clock Enabled by RF HIGH
+#define AT91_SSC_RCMR_START_CONT (0<<8) //Start when data in RHR, Continuous
+#define AT91_SSC_RCMR_START_TX (1<<8) //Start when TX Start
+#define AT91_SSC_RCMR_START_RFLOW (2<<8) //Start when LOW level on RF
+#define AT91_SSC_RCMR_START_RFHIGH (3<<8) //Start when HIGH level on RF
+#define AT91_SSC_RCMR_START_RFFALL (4<<8) //Start when Falling Edge on RF
+#define AT91_SSC_RCMR_START_RFRISE (5<<8) //Start when Rising Edge on RF
+#define AT91_SSC_RCMR_START_RFLEVEL (6<<8) //Start when any Level Change on RF
+#define AT91_SSC_RCMR_START_RFEDGE (7<<8) //Start when any Edge on RF
+#define AT91_SSC_RCMR_START_CMP0 (8<<8) //Start when Compare 0 match
+#define AT91_SSC_RCMR_STOP_CMP1 (1<<12) //Stop when Compare 1 Match
+#define AT91_SSC_RCMR_STTDLY(x) ((x&0xFF)<<16) //Start Delay
+#define AT91_SSC_RCMR_PERIOD(x) ((x&0xFF)<<24) //Frame Period
+#define AT91_SSC_RFMR (0x14)
+#define AT91_SSC_RFMR_DATLEN(x) (x&0x1F) //Data word length
+#define AT91_SSC_RFMR_LOOP (1<<5) //Loop Mode
+#define AT91_SSC_RFMR_MSBF (1<<7) //MSB First
+#define AT91_SSC_RFMR_DATNB(x) ((x&0xf)<<8) //Data Number, # words per frame
+#define AT91_SSC_RFMR_FSLEN(x) ((x&0xf)<<16) //Frame sync length
+#define AT91_SSC_RFMR_FSOS_NONE (0<<16) //No Frame Synch Output
+#define AT91_SSC_RFMR_FSOS_NEGPULSE (1<<16) //Negative Pulse Frame Sync Output
+#define AT91_SSC_RFMR_FSOS_POSPULSE (2<<16) //Positive Pulse Frame Sync Output
+#define AT91_SSC_RFMR_FSOS_LOW (3<<16) //Low Level Frame Synch Output
+#define AT91_SSC_RFMR_FSOS_HIGH (4<<16) //High Level Frame Synch Output
+#define AT91_SSC_RFMR_FSOS_TOGGLE (5<<16) //Toggle Frame Synch Output
+#define AT91_SSC_RFMR_FSEDGE_POS (0<<24) //Intr on +ve edge of Frame Sync
+#define AT91_SSC_RFMR_FSEDGE_NEG (1<<24) //Intr on -ve edge of Frame Sync
+#define AT91_SSC_TCMR (0x18)
+#define AT91_SSC_TCMR_CKS_DIV (0<<0) //Select Divider Clock
+#define AT91_SSC_TCMR_CKS_TX (1<<0) //Select Transmit Clock
+#define AT91_SSC_TCMR_CKS_RK (2<<0) //Select Receiver Clock
+#define AT91_SSC_TCMR_CKO_NONE (0<<2) //No Clock Output
+#define AT91_SSC_TCMR_CKO_CONT (1<<2) //Continuous Clock Output
+#define AT91_SSC_TCMR_CKO_TFER (2<<2) //Clock Output During Transfer only
+#define AT91_SSC_TCMR_CKI (1<<5) //Clock Invert
+#define AT91_SSC_TCMR_CKG_NONE (0<<6) //No Clock Gating, Continuous Clock
+#define AT91_SSC_TCMR_CKG_RFLOW (1<<6) //Clock Enabled by RF Low
+#define AT91_SSC_TCMR_CKG_RFHIGH (2<<6) //Clock Enabled by RF HIGH
+#define AT91_SSC_TCMR_START_CONT (0<<8) //Start when data in THR, Continuous
+#define AT91_SSC_TCMR_START_TX (1<<8) //Start when TX Start
+#define AT91_SSC_TCMR_START_RFLOW (2<<8) //Start when LOW level on RF
+#define AT91_SSC_TCMR_START_RFHIGH (3<<8) //Start when HIGH level on RF
+#define AT91_SSC_TCMR_START_RFFALL (4<<8) //Start when Falling Edge on RF
+#define AT91_SSC_TCMR_START_RFRISE (5<<8) //Start when Rising Edge on RF
+#define AT91_SSC_TCMR_START_RFLEVEL (6<<8) //Start when any Level Change on RF
+#define AT91_SSC_TCMR_START_RFEDGE (6<<8) //Start when any Edge on RF
+#define AT91_SSC_TCMR_STDDLY(x) ((x&0xFF)<<16) //Start Delay
+#define AT91_SSC_TCMR_PERIOD(x) ((x&0xFF)<<24) //Frame Period
+#define AT91_SSC_TFMR (0x1C)
+#define AT91_SSC_TFMR_DATLEN(x) (x&0x1F) //Data word length
+#define AT91_SSC_TFMR_DATDEF (1<<5) //Default Data is 1's
+#define AT91_SSC_TFMR_MSBF (1<<7) //MSB First
+#define AT91_SSC_TFMR_DATNB(x) ((x&0xf)<<8) //Data Number, # words per frame
+#define AT91_SSC_TFMR_FSLEN(x) ((x&0xf)<<16) //Frame sync length
+#define AT91_SSC_TFMR_FSOS_NONE (0<<16) //No Frame Synch Output
+#define AT91_SSC_TFMR_FSOS_NEGPULSE (1<<16) //Negative Pulse Frame Sync Output
+#define AT91_SSC_TFMR_FSOS_POSPULSE (2<<16) //Positive Pulse Frame Sync Output
+#define AT91_SSC_TFMR_FSOS_LOW (3<<16) //Low Level Frame Synch Output
+#define AT91_SSC_TFMR_FSOS_HIGH (4<<16) //High Level Frame Synch Output
+#define AT91_SSC_TFMR_FSOS_TOGGLE (5<<16) //Toggle Frame Synch Output
+#define AT91_SSC_RFMR_FSDEN_DEF (0<<23) //Frame Sync is Default Data
+#define AT91_SSC_RFMR_FSDEN_TSHR (1<<23) //Frame Sync is TSHR Data
+#define AT91_SSC_RFMR_FSEDGE_POS (0<<24) //Intr on +ve edge of Frame Sync
+#define AT91_SSC_RFMR_FSEDGE_NEG (1<<24) //Intr on -ve edge of Frame Sync
+#define AT91_SSC_RHR (0x20)
+#define AT91_SSC_THR (0x24)
+#define AT91_SSC_RSHR (0x30)
+#define AT91_SSC_TSHR (0x34)
+#define AT91_SSC_RC0R (0x38)
+#define AT91_SSC_RC1R (0x3C)
+#define AT91_SSC_SR (0x40)
+#define AT91_SSC_SR_TXRDY (1<<0) //Transmit Ready
+#define AT91_SSC_SR_TXEMPTY (1<<1) //Transmit Empty
+#define AT91_SSC_SR_ENDTX (1<<2) //End of Transmission
+#define AT91_SSC_SR_TXBUFE (1<<3) //Transmit Buffer Empty
+#define AT91_SSC_SR_RXRDY (1<<4) //Receiver Ready
+#define AT91_SSC_SR_OVRUN (1<<5) //Receiver Overrun
+#define AT91_SSC_SR_ENDRX (1<<6) //End of Reception
+#define AT91_SSC_SR_RXBUFF (1<<7) //Receive Buffer Full
+#define AT91_SSC_SR_CP0 (1<<8) //Compare 0 match
+#define AT91_SSC_SR_CP1 (1<<9) //Compare 1 Match
+#define AT91_SSC_SR_TXSYN (1<<10) //Transmit Frame Sync
+#define AT91_SSC_SR_RXSYN (1<<11) //Receive Frame Sync
+#define AT91_SSC_SR_TXEN (1<<16) //Transmitter Enabled
+#define AT91_SSC_SR_RXEN (1<<17) //Receiver Enabled
+#define AT91_SSC_IER (0x44)
+#define AT91_SSC_IDR (0x48)
+#define AT91_SSC_IMR (0x4C)
+
+#define AT91_SSC_RPR 0x100 // Receiver Pointer Register
+#define AT91_SSC_RCR 0x104 // Receiver Counter Register
+#define AT91_SSC_TPR 0x108 // Transmit Pointer Register
+#define AT91_SSC_TCR 0x10c // Transmit Counter Register
+#define AT91_SSC_RNPR 0x110 // Receiver Next Pointer Register
+#define AT91_SSC_RNCR 0x114 // Receiver Next Counter Register
+#define AT91_SSC_TNPR 0x118 // Transmit Next Pointer Register
+#define AT91_SSC_TNCR 0x11c // Transmit Next Counter Register
+#define AT91_SSC_PTCR 0x120 // PDC Transfer Control Register
+#define AT91_SSC_PTSR 0x124 // PDC Transfer Status Register
+
+#define AT91_SSC_PTCR_RXTEN (1 << 0) //Receive Transfers Enabled
+#define AT91_SSC_PTCR_RXTDIS (1 << 1) //Receive Transfers Disabled
+#define AT91_SSC_PTCR_TXTEN (1 << 8) //Receive Transfers Enabled
+#define AT91_SSC_PTCR_TXTDIS (1 << 9) //Receive Transfers Disabled
+
+#endif
+
+//=============================================================================
+// Ethernet Controller (EMAC)
+
+#if defined(CYGHWR_HAL_ARM_AT91SAM7X)
+
+#ifndef AT91_EMAC
+#define AT91_EMAC 0xFFFBC000
+#endif
+
+#define AT91_EMAC_NCR (0x00) // Network Control
+#define AT91_EMAC_NCR_LB (1 << 0) // Loopback
+#define AT91_EMAC_NCR_LBL (1 << 1) // Loopback Local
+#define AT91_EMAC_NCR_RE (1 << 2) // Receiver Enable
+#define AT91_EMAC_NCR_TX (1 << 3) // Transmit Enable
+#define AT91_EMAC_NCR_MPE (1 << 4) // Management Port Enable
+#define AT91_EMAC_NCR_CSR (1 << 5) // Clear Statistics Registers
+#define AT91_EMAC_NCR_ISR (1 << 6) // Increment Statistics Registers
+#define AT91_EMAC_NCR_WES (1 << 7) // Write Enable for Statistics Registers
+#define AT91_EMAC_NCR_BP (1 << 8) // Back Pressure
+#define AT91_EMAC_NCR_TSTART (1 << 9) // Start Transmitter
+#define AT91_EMAC_NCR_THALT (1 << 10) // Halt Transmitter
+
+#define AT91_EMAC_NCFG (0x04) // Network Configuration
+#define AT91_EMAC_NCFG_SPD_10Mbps (0 << 0) // 10Mbps line speed
+#define AT91_EMAC_NCFG_SPD_100Mbps (1 << 0) // 100Mbps line speed
+#define AT91_EMAC_NCFG_FD (1 << 1) // Full Deplex
+#define AT91_EMAC_NCFG_BR (1 << 2) // Bit Rate
+#define AT91_EMAC_NCFG_CAF (1 << 4) // Copy All Frames
+#define AT91_EMAC_NCFG_NBC (1 << 5) // Don't receiver Broadcasts
+#define AT91_EMAC_NCFG_MTI (1 << 6) // Multicast Hash Enable
+#define AT91_EMAC_NCFG_UNI (1 << 7) // Unicast hash enable
+#define AT91_EMAC_NCFG_BIG (1 << 8) // Receive upto 1522 byte frames
+#define AT91_EMAC_NCFG_EAE (1 << 9) // External Address match Enable
+#define AT91_EMAC_NCFG_CLK_HCLK_8 (0 << 10) // HCLK divided by 8
+#define AT91_EMAC_NCFG_CLK_HCLK_16 (1 << 10) // HCLK divided by 16
+#define AT91_EMAC_NCFG_CLK_HCLK_32 (2 << 10) // HCLK divided by 32
+#define AT91_EMAC_NCFG_CLK_HCLK_64 (3 << 10) // HCLK divided by 64
+#define AT91_EMAC_NCFG_CLK_MASK (3 << 10) // HCLK mask
+#define AT91_EMAC_NCFG_CLK_RTY (1 << 12) // Retry Test
+#define AT91_EMAC_NCFG_CLK_RMII (1 << 13) // Enable RMII mode
+#define AT91_EMAC_NCFG_CLK_MII (0 << 13) // Enable MII mode
+#define AT91_EMAC_NCFG_RLCE (0 << 16) // Receive Length Check Enable
+
+#define AT91_EMAC_NSR (0x08) // Network Status
+#define AT91_EMAC_NSR_MDIO_MASK (1 << 1) // MDIO Pin status
+#define AT91_EMAC_NSR_IDLE (1 << 2) // PHY logical is idle
+
+#define AT91_EMAC_TSR (0x14) // Transmit Status
+#define AT91_EMAC_TSR_OVR (1 << 0) // Overrun
+#define AT91_EMAC_TSR_COL (1 << 1) // Collision occurred
+#define AT91_EMAC_TSR_RLE (1 << 2) // Retry Limit Exceeded
+#define AT91_EMAC_TSR_TXIDLE (1 << 3) // Transmitter Idle
+#define AT91_EMAC_TSR_BNQ (1 << 4) // Buffer Not Queues
+#define AT91_EMAC_TSR_COMP (1 << 5) // Transmission Complete
+#define AT91_EMAC_TSR_UND (1 << 6) // Transmit Underrun
+
+#define AT91_EMAC_RBQP (0x18) // Receiver Buffer Queue Pointer
+#define AT91_EMAC_TBQP (0x1c) // Transmit Buffer Queue Pointer
+
+#define AT91_EMAC_RSR (0x20) // Receiver Status
+#define AT91_EMAC_RSR_BNA (1 << 0) // Buffer Not Available
+#define AT91_EMAC_RSR_REC (1 << 1) // Frame Received
+#define AT91_EMAC_RSR_OVR (1 << 2) // Transmit Buffer Overrun
+
+#define AT91_EMAC_ISR (0x24) // Interrupt Status
+#define AT91_EMAC_ISR_DONE (1 << 0) // Management Done
+#define AT91_EMAC_ISR_RCOM (1 << 1) // Receiver Complete
+#define AT91_EMAC_ISR_RBNA (1 << 2) // Receiver Buffer Not Available
+#define AT91_EMAC_ISR_TOVR (1 << 3) // Transmit Buffer Overrun
+#define AT91_EMAC_ISR_TUND (1 << 4) // Transmit Error: Buffer under run
+#define AT91_EMAC_ISR_RTRY (1 << 5) // Transmit Error: Retry Limit Exceeded
+#define AT91_EMAC_ISR_TBRE (1 << 6) // Transmit Buffer Register Empty
+#define AT91_EMAC_ISR_TCOM (1 << 7) // Transmit Complete
+#define AT91_EMAC_ISR_TIDLE (1 << 8) // Transmitter Idle
+#define AT91_EMAC_ISR_LINK (1 << 9) // Link pin changed state
+#define AT91_EMAC_ISR_ROVR (1 << 10) // Receiver Overrun
+#define AT91_EMAC_ISR_HRESP (1 << 11) // HRESP not OK
+#define AT91_EMAC_IER (0x28) // Interrupt Enable
+#define AT91_EMAC_IDR (0x2c) // Interrupt Disable
+#define AT91_EMAC_IMR (0x30) // Interrupt Mask
+
+#define AT91_EMAC_MAN (0x34) // PHY Maintenance
+#define AT91_EMAC_MAN_DATA_MASK (0xffff<<0) // Data to/from PHY
+#define AT91_EMAC_MAN_CODE (2<<16) // Code
+#define AT91_EMAC_MAN_REGA_MASK (0x1f<<18) // Register Address Mask
+#define AT91_EMAC_MAN_REGA_SHIFT (18) // Register Address Shift
+#define AT91_EMAC_MAN_PHY_MASK (0x1f<<23) // PHY Address Mask
+#define AT91_EMAC_MAN_PHY_SHIFT (23) // PHY Address Shift
+#define AT91_EMAC_MAN_RD (2<<28) // Read operation
+#define AT91_EMAC_MAN_WR (1<<28) // Write Operation
+#define AT91_EMAC_MAN_SOF (1<<30) // Must be set to 01
+#define AT91_EMAC_MAN_PHYA(x) ((x&0x1f)<<23) // Create a PHY Address
+#define AT91_EMAC_MAN_REGA(x) ((x&0x1f)<<18) // Create a Register Address
+#define AT91_EMAC_MAN_DATA(x) (x&0xffff) // Create a Data word
+
+
+#define AT91_EMAC_PTR (0x38) // Pause Time Register
+#define AT91_EMAC_PFR (0x3C) // Pause Frames Received
+#define AT91_EMAC_FTO (0x40) // Frames Transmitted OK
+#define AT91_EMAC_SCF (0x44) // Single Collision Frame
+#define AT91_EMAC_MCF (0x48) // Multiple Collision Frame
+#define AT91_EMAC_FRO (0x4c) // Frames Received OK
+#define AT91_EMAC_FCSE (0x50) // Frame Check Sequence Error
+#define AT91_EMAC_ALE (0x54) // Alignment Error
+#define AT91_EMAC_DTR (0x58) // Deferred Transmission Frame
+#define AT91_EMAC_LCOL (0x5c) // Late Collision
+#define AT91_EMAC_XCOL (0x60) // Excessive Collisions - ECOL!!
+#define AT91_EMAC_TUND (0x64) // Transmit Underrun Error
+#define AT91_EMAC_CSE (0x68) // Carrier Sense Error
+#define AT91_EMAC_RRE (0x6c) // Receive Resource Errors
+#define AT91_EMAC_ROV (0x70) // Receive Overrun
+#define AT91_EMAC_RSE (0x74) // Receiver Symbol erros
+#define AT91_EMAC_ELE (0x78) // Excessive Length Errors
+#define AT91_EMAC_RJE (0x7c) // Receive Jabber Errors
+#define AT91_EMAC_USF (0x80) // Undersize Frame Errors
+#define AT91_EMAC_STE (0x84) // SQE Test Errors
+#define AT91_EMAC_RLE (0x88) // Receive Length Field Mismatch
+
+#define AT91_EMAC_HRB (0x90) // Hash Address Low [31:0]
+#define AT91_EMAC_HRT (0x94) // Hash Address High [63:32]
+#define AT91_EMAC_SA1L (0x98) // Specific Address 1 Low, First 4 bytes
+#define AT91_EMAC_SA1H (0x9c) // Specific Address 1 High, Last 2 bytes
+#define AT91_EMAC_SA2L (0xa0) // Specific Address 2 Low, First 4 bytes
+#define AT91_EMAC_SA2H (0xa4) // Specific Address 2 High, Last 2 bytes
+#define AT91_EMAC_SA3L (0xa8) // Specific Address 3 Low, First 4 bytes
+#define AT91_EMAC_SA3H (0xac) // Specific Address 3 High, Last 2 bytes
+#define AT91_EMAC_SA4L (0xb0) // Specific Address 4 Low, First 4 bytes
+#define AT91_EMAC_SA4H (0xb4) // Specific Address 4 High, Last 2 bytes
+#define AT91_EMAC_TID (0xb8) // Type ID Checking Register
+
+#define AT91_EMAC_USRIO (0xc0) // User IO Register
+#define AT91_EMAC_USRIO_RMII (1<<0) // RMII Mode
+#define AT91_EMAC_USRIO_CLKEN (1<<1) // Clock Enable
+
+// Receiver Buffer Descriptor
+#define AT91_EMAC_RBD_ADDR 0x0 // Address to beginning of buffer
+#define AT91_EMAC_RBD_ADDR_MASK (0xFFFFFFFC) // Address Mask masking the reserved bits
+#define AT91_EMAC_RBD_ADDR_OWNER_EMAC (0 << 0) // EMAC owns receiver buffer
+#define AT91_EMAC_RBD_ADDR_OWNER_SW (1 << 0) // SW owns receiver buffer
+#define AT91_EMAC_RBD_ADDR_WRAP (1 << 1) // Last receiver buffer
+#define AT91_EMAC_RBD_SR 0x1 // Buffer Status
+#define AT91_EMAC_RBD_SR_LEN_MASK (0xfff) // Length of data
+#define AT91_EMAC_RBD_SR_SOF (1 << 14) // Start of Frame
+#define AT91_EMAC_RBD_SR_EOF (1 << 15) // End of Frame
+#define AT91_EMAC_RBD_SR_CFI (1 << 16) // Concatination Format Ind
+#define AT91_EMAC_RDB_SR_VLAN_SHIFT (17) // VLAN priority tag
+#define AT91_EMAC_RDB_SR_VLAN_MASK (7 << 17)
+#define AT91_EMAC_RDB_SR_PRIORTY_TAG (1 << 20) // Priority Tag Detected
+#define AT91_EMAC_RDB_SR_VLAN_TAG (1 << 21) // Priority Tag Detected
+#define AT91_EMAC_RBD_SR_TYPE_ID (1 << 22) // Type ID match
+#define AT91_EMAC_RBD_SR_SA4M (1 << 23) // Specific Address 4 match
+#define AT91_EMAC_RBD_SR_SA3M (1 << 24) // Specific Address 3 match
+#define AT91_EMAC_RBD_SR_SA2M (1 << 25) // Specific Address 2 match
+#define AT91_EMAC_RBD_SR_SA1M (1 << 26) // Specific Address 1 match
+#define AT91_EMAC_RBD_SR_EXTNM (1 << 28) // External Address match
+#define AT91_EMAC_RBD_SR_UNICAST (1 << 29) // Unicast hash match
+#define AT91_EMAC_RBD_SR_MULTICAST (1 << 30) // Multicast hash match
+#define AT91_EMAC_RBD_SR_BROADCAST (1 << 31) // Broadcast
+
+// Transmit Buffer Descriptor
+#define AT91_EMAC_TBD_ADDR 0x0 // Address to beginning of buffer
+#define AT91_EMAC_TBD_SR 0x1 // Buffer Status
+#define AT91_EMAC_TBD_SR_LEN_MASK (0xfff) // Length of data
+#define AT91_EMAC_TBD_SR_EOF (1 << 15) // End of Frame
+#define AT91_EMAC_TBD_SR_NCRC (1 << 16) // No CRC added by EMAC
+#define AT91_EMAC_TBD_SR_EXHAUST (1 << 27) // Buffers exhausted
+#define AT91_EMAC_TBD_SR_TXUNDER (1 << 28) // Transmit Underrun
+#define AT91_EMAC_TBD_SR_RTRY (1 << 29) // Retry limit exceeded
+#define AT91_EMAC_TBD_SR_WRAP (1 << 30) // Marks last descriptor
+#define AT91_EMAC_TBD_SR_USED (1 << 31) // Buffer used
+
+#endif
+
+//=============================================================================
+// Two Wire Interface (TWI)
+
+#if defined(CYGHWR_HAL_ARM_AT91SAM7)
+
+#ifndef AT91_TWI
+#define AT91_TWI 0xFFFB8000
+#endif
+
+#define AT91_TWI_CR 0x00 // Control
+#define AT91_TWI_CR_START (1 << 0) // Send a Start
+#define AT91_TWI_CR_STOP (1 << 1) // Send a Stop
+#define AT91_TWI_CR_MSEN (1 << 2) // Master Transfer Enable
+#define AT91_TWI_CR_MSDIS (1 << 3) // Master Transfer Disable
+#define AT91_TWI_CR_SVEN (1 << 4) // Slave Transfer Enable
+#define AT91_TWI_CR_SDIS (1 << 5) // Slave Transfer Disable
+#define AT91_TWI_CR_SWRST (1 << 7) // Software Reset
+#define AT91_TWI_MMR 0x04 // Master Mode
+#define AT91_TWI_MMR_IADRZ_NO (0 << 8) // Internal Device Address size 0Bytes
+#define AT91_TWI_MMR_IADRZ_1 (1 << 8) // Internal Device Address size 1Byte
+#define AT91_TWI_MMR_IADRZ_2 (2 << 8) // Internal Device Address size 2Bytes
+#define AT91_TWI_MMR_IADRZ_3 (3 << 8) // Internal Device Address size 3Bytes
+#define AT91_TWI_MMR_MWRITE (0 << 12) // Master Write
+#define AT91_TWI_MMR_MREAD (1 << 12) // Master Read
+#define AT91_TWI_MMR_DADR_MASK (0x3f << 16) // Device Address Mask
+#define AT91_TWI_MMR_DADR_SHIFT (16) // Device Address Shift
+#define AT91_TWI_SMR 0x08 // Slave Mode
+#define AT91_TWI_SMR_SADR_MASK (0x3f << 16) // Slave Device Address Mask
+#define AT91_TWI_SMR_SADR_SHIFT (16) // Slave Device Address Shift
+#define AT91_TWI_IADR 0x0C // Internal Address
+#define AT91_TWI_CWGR 0x10 // Clock Waveform Generator
+#define AT91_TWI_CWGR_CLDIV_MASK (0xf << 0) // Clock Low Divider Mask
+#define AT91_TWI_CWGR_CLDIV_SHIFT (00) // Clock Low Divider Shift
+#define AT91_TWI_CWGR_CHDIV_MASK (0xf << 8) // Clock High Divider Mask
+#define AT91_TWI_CWGR_CHDIV_SHIFT (08) // Clock High Divider Shift
+#define AT91_TWI_CWGR_CKDIV_MASK (0x7 << 16) // Clock Divider Mask
+#define AT91_TWI_CWGR_CKDIV_SHIFT (16) // Clock Divider Shift
+#define AT91_TWI_SR 0x20 // Status
+#define AT91_TWI_SR_TXCOMP (1 << 0) // Transmission Completed
+#define AT91_TWI_SR_RXRDY (1 << 1) // Receiver Holding Register Ready
+#define AT91_TWI_SR_TXRDY (1 << 2) // Transmit Holding Register Ready
+#define AT91_TWI_SR_SVREAD (1 << 3) // Slave Read
+#define AT91_TWI_SR_SVACC (1 << 4) // Slave Access
+#define AT91_TWI_SR_GCACC (1 << 5) // General Call Access
+#define AT91_TWI_SR_OVRE (1 << 6) // Overrun Error
+#define AT91_TWI_SR_UNRE (1 << 7) // Underrun Error
+#define AT91_TWI_SR_NACK (1 << 8) // Not Acknowledged
+#define AT91_TWI_SR_ARBLST (1 << 9) // Arbitration Lost
+#define AT91_TWI_IER 0x24 // Interrupt Enable
+#define AT91_TWI_IDR 0x28 // Interrupt Disable
+#define AT91_TWI_IMR 0x2C // Interrupt Mask
+#define AT91_TWI_RHR 0x30 // Receiver Holding
+#define AT91_TWI_THR 0x34 // Transmit Holding
+#endif
+
+//=============================================================================
+// Analog to Digital Convertor (ADC)
+
+#if defined(CYGHWR_HAL_ARM_AT91SAM7)
+
+#ifndef AT91_ADC
+#define AT91_ADC 0xFFFD8000
+#endif
+
+#define AT91_ADC_CR 0x00 // Control
+#define AT91_ADC_CR_SWRST (1 << 0) // Software Reset
+#define AT91_ADC_CR_START (1 << 1) // Start Conversion
+#define AT91_ADC_MR 0x04 // Mode
+#define AT91_ADC_MR_TRGSEL_TIOA0 (0 << 1) // Trigger = TIAO0
+#define AT91_ADC_MR_TRGSEL_TIOA1 (1 << 1) // Trigger = TIAO1
+#define AT91_ADC_MR_TRGSEL_TIOA2 (2 << 1) // Trigger = TIAO2
+#define AT91_ADC_MR_TRGSEL_TIOA3 (3 << 1) // Trigger = TIAO3
+#define AT91_ADC_MR_TRGSEL_TIOA4 (4 << 1) // Trigger = TIAO4
+#define AT91_ADC_MR_TRGSEL_TIOA5 (5 << 1) // Trigger = TIAO5
+#define AT91_ADC_MR_TRGSEL_EXT (6 << 1) // Trigger = External
+#define AT91_ADC_MR_LOWREC_10BITS (0 << 4) // 10-bit Resolution
+#define AT91_ADC_MR_LOWRES_8BITS (1 << 4) // 8-bit resolution
+#define AT91_ADC_MR_SLEEP_ON (1 << 5) // Sleep mode on
+#define AT91_ADC_MR_SLEEP_OFF (0 << 5) // Sleep mode off
+#define AT91_ADC_MR_PRESCAL_MASK (0x3f << 8) // Prescale Mask
+#define AT91_ADC_MR_PRESCAL_SHIFT (8) // Prescale Shift
+#define AT91_ADC_MR_STARTUP_MASK (0x0f << 16) // Startup Time Mask
+#define AT91_ADC_MR_STARTUP_SHIFT (16) // Startup Time Mask
+#define AT91_ADC_MR_SHTIM_MASK (0x0f << 24) // Sample & Hold Time Mask
+#define AT91_ADC_MR_SHTIM_SHIFT (24) // Sample & Hold Time Shift
+#define AT91_ADC_CHER 0x10 // Channel Enable
+#define AT91_ADC_CHER_CH0 (1 << 0) // Channel 0
+#define AT91_ADC_CHER_CH1 (1 << 1) // Channel 1
+#define AT91_ADC_CHER_CH2 (1 << 2) // Channel 2
+#define AT91_ADC_CHER_CH3 (1 << 3) // Channel 3
+#define AT91_ADC_CHER_CH4 (1 << 4) // Channel 4
+#define AT91_ADC_CHER_CH5 (1 << 5) // Channel 5
+#define AT91_ADC_CHER_CH6 (1 << 6) // Channel 6
+#define AT91_ADC_CHER_CH7 (1 << 7) // Channel 7
+#define AT91_ADC_CHDR 0x14 // Channel Disable
+#define AT91_ADC_CHSR 0x18 // Channel Status
+#define AT91_ADC_SR 0x1c // Status
+#define AT91_ADC_CHSR_EOC0 (1 << 0) // Channel 0 End of Conversion
+#define AT91_ADC_CHSR_EOC1 (1 << 1) // Channel 1 End of Conversion
+#define AT91_ADC_CHSR_EOC2 (1 << 2) // Channel 2 End of Conversion
+#define AT91_ADC_CHSR_EOC3 (1 << 3) // Channel 3 End of Conversion
+#define AT91_ADC_CHSR_EOC4 (1 << 4) // Channel 4 End of Conversion
+#define AT91_ADC_CHSR_EOC5 (1 << 5) // Channel 5 End of Conversion
+#define AT91_ADC_CHSR_EOC6 (1 << 6) // Channel 6 End of Conversion
+#define AT91_ADC_CHSR_EOC7 (1 << 7) // Channel 7 End of Conversion
+#define AT91_ADC_CHSR_OVRE0 (1 << 8) // Channel 0 Overrun Error
+#define AT91_ADC_CHSR_OVRE1 (1 << 9) // Channel 1 Overrun Error
+#define AT91_ADC_CHSR_OVRE2 (1 << 10) // Channel 2 Overrun Error
+#define AT91_ADC_CHSR_OVRE3 (1 << 11) // Channel 3 Overrun Error
+#define AT91_ADC_CHSR_OVRE4 (1 << 12) // Channel 4 Overrun Error
+#define AT91_ADC_CHSR_OVRE5 (1 << 13) // Channel 5 Overrun Error
+#define AT91_ADC_CHSR_OVRE6 (1 << 14) // Channel 6 Overrun Error
+#define AT91_ADC_CHSR_OVRE7 (1 << 15) // Channel 7 Overrun Error
+#define AT91_ADC_CHSR_DRDY (1 << 16) // Data Ready
+#define AT91_ADC_CHSR_GOVER (1 << 17) // General Overrun
+#define AT91_ADC_CHSR_EDNRX (1 << 18) // End of Receiver Transfer
+#define AT91_ADC_CHSR_RXBUFF (1 << 19) // RXBUFFER Interrupt
+#define AT91_ADC_LCDR 0x20 // Last Converted Data
+#define AT91_ADC_IER 0x24 // Interrupt Enable
+#define AT91_ADC_IDR 0x28 // Interrupt Disable
+#define AT91_ADC_IMR 0x2c // Interrupt Mask
+#define AT91_ADC_CDR0 0x30 // Channel Data 0
+#define AT91_ADC_CDR1 0x34 // Channel Data 1
+#define AT91_ADC_CDR2 0x38 // Channel Data 2
+#define AT91_ADC_CDR3 0x3c // Channel Data 3
+#define AT91_ADC_CDR4 0x40 // Channel Data 4
+#define AT91_ADC_CDR5 0x44 // Channel Data 5
+#define AT91_ADC_CDR6 0x48 // Channel Data 6
+#define AT91_ADC_CDR7 0x4c // Channel Data 7
+#define AT91_ADC_RPR 0x100 // Receive Pointer
+#define AT91_ADC_RCR 0x104 // Receive Counter
+#define AT91_ADC_TPR 0x108 // Transmit Pointer
+#define AT91_ADC_TCR 0x10C // Transmit Counter
+#define AT91_ADC_RNPR 0x110 // Receive Next Pointer
+#define AT91_ADC_RNCR 0x114 // Receive Next Counter
+#define AT91_ADC_TNPR 0x118 // Transmit Next Pointer
+#define AT91_ADC_TNCR 0x11C // Transmit Next Counter
+#define AT91_ADC_PTCR 0x120 // PDC Transfer Control
+#define AT91_ADC_PTSR 0x124 // PDC Transfer Status
+
+#endif
+
+//=============================================================================
+// Controller Area Network (CAN)
+
+#if defined(CYGHWR_HAL_ARM_AT91SAM7X)
+
+#ifndef AT91_CAN
+#define AT91_CAN 0xFFFD8000
+#endif
+
+#define AT91_CAN_MR 0x000 // Mode
+#define AT91_CAN_MR_CANEN (1 << 0) // Enable
+#define AT91_CAN_MR_LPM (1 << 1) // Enable Low Power Mode
+#define AT91_CAN_MR_ABM (1 << 2) // Enable Autobaud/Listen mode
+#define AT91_CAN_MR_OVL (1 << 3) // Enable Overload Frame
+#define AT91_CAN_MR_TEOF (1 << 4) // Timestamp at End Of Trame
+#define AT91_CAN_MR_TTM (1 << 5) // Enable Time Triggered Mode
+#define AT91_CAN_MR_TIMFRZ (1 << 6) // Enable Timer Freeze
+#define AT91_CAN_MR_DRPT (1 << 7) // Disable Repeat
+#define AT91_CAN_IER 0x004 // Interrupt Enable
+#define AT91_CAM_IER_MB0 (1 << 0) // Mailbox 0
+#define AT91_CAM_IER_MB1 (1 << 1) // Mailbox 1
+#define AT91_CAM_IER_MB2 (1 << 2) // Mailbox 2
+#define AT91_CAM_IER_MB3 (1 << 3) // Mailbox 3
+#define AT91_CAM_IER_MB4 (1 << 4) // Mailbox 4
+#define AT91_CAM_IER_MB5 (1 << 5) // Mailbox 5
+#define AT91_CAM_IER_MB6 (1 << 6) // Mailbox 6
+#define AT91_CAM_IER_MB7 (1 << 7) // Mailbox 7
+#define AT91_CAM_IER_ERRA (1 << 16) // Error Active Mode
+#define AT91_CAM_IER_WARN (1 << 17) // Warning Limit
+#define AT91_CAM_IER_ERRO (1 << 18) // Error Passive Mode
+#define AT91_CAM_IER_BOFF (1 << 19) // Bus-Off Mode
+#define AT91_CAM_IER_SLEEP (1 << 20) // Sleep
+#define AT91_CAM_IER_WAKEUP (1 << 21) // Wakeup
+#define AT91_CAM_IER_TOVF (1 << 22) // Timer Overflow
+#define AT91_CAM_IER_TSTP (1 << 23) // TimeStamp
+#define AT91_CAM_IER_CERR (1 << 24) // CRC Error
+#define AT91_CAM_IER_SERR (1 << 25) // Stuffing Error
+#define AT91_CAM_IER_AERR (1 << 26) // Acknowledgement Error
+#define AT91_CAM_IER_FERR (1 << 27) // Form Error
+#define AT91_CAM_IER_BERR (1 << 28) // Bit Error
+#define AT91_CAN_IDR 0x008 // Interrupt Disable
+#define AT91_CAN_IMR 0x00C // Interrupt Mask
+#define AT91_CAN_SR 0x010 // Status
+#define AT91_CAN_SR_RBSY (1 << 29) // Receiver busy
+#define AT91_CAM_SR_TBSY (1 << 30) // Transmitter busy
+#define AT91_CAM_IER_OVLSY (1 << 31) // Overload Busy
+#define AT91_CAN_BR 0x014 // Baudrate
+#define AT91_CAN_BR_PHASE1_MASK (0x7 << 4) // Phase 1 Segment mask
+#define AT91_CAN_BR_PHASE1_SHIFT (4) // Phase 1 Segment shift
+#define AT91_CAN_BR_PHASE2_MASK (0x7 << 0) // Phase 2 Segment mask
+#define AT91_CAN_BR_PHASE2_SHIFT (0) // Phase 2 Segment shift
+#define AT91_CAN_BR_PROPAG_MASK (0x7 << 8) // Programming Time Segment mask
+#define AT91_CAN_BR_PROPAG_SHIFT (8) // Programming Time Segment shift
+#define AT91_CAN_BR_SJW_MASK (0x3 << 12) // Re-Sync jump width mask
+#define AT91_CAN_BR_SJW_SHIFT (12) // Re-Sync jump width shift
+#define AT91_CAN_BR_BRP_MASK (0x7f << 16) // Baudrate Prescaler mask
+#define AT91_CAN_BR_BRP_SHIFT (16) // Baudrate Prescaler mask
+#define AT91_CAN_BR_SMP_ONCE (0 << 24) // Sampling once
+#define AT91_CAN_BR_SMP_THRICE (1 << 24) // Sampling three times
+#define AT91_CAN_TIM 0x018 // Timer
+#define AT91_CAN_TIMESTP 0x01c // Timestamp
+#define AT91_CAN_ECR 0x020 // Error Counter
+#define AT91_CAN_ECR_REC_MASK (0xf << 0) // Receiver Error Counter mask
+#define AT91_CAN_ECR_REC_SHIFT (00) // Receiver Error Counter shift
+#define AT91_CAN_ECR_TEC_MASK (0xf << 16) // Transmit Error Counter mask
+#define AT91_CAN_ECR_TEC_SHIFT (00) // Transmit Error Counter shift
+#define AT91_CAN_TCR 0x024 // Transfer Command
+#define AT91_CAN_TCR_TIMRST (1 << 31) // Timer Reset
+#define AT91_CAN_ACR 0x028 // Abort Command
+#define AT91_CAN_MMR0 0x200 // Mailbox 0 Mode
+#define AT91_CAN_MMR_PRIOR_MASK (0xf << 16) // Priority Mask
+#define AT91_CAN_MMR_PRIOR_SHIFT (16) // Priority Shift
+#define AT91_CAN_MMR_MOT_DISABLED (0 << 24) // Mailbox disabled
+#define AT91_CAN_MMR_MOT_RECEPTION (1 << 24) // Reception Mailbox
+#define AT91_CAN_MMR_MOT_RECEPTION_OVER (2 << 24) // Reception with Overwrite
+#define AT91_CAM_MMR_MOT_TRANSMIT (3 << 24) // Transmit Mailbox
+#define AT91_CAM_MMR_MOT_CONSUMER (4 << 24) // Transmit Mailbox
+#define AT91_CAM_MMR_MOT_PRODUCER (5 << 24) // Transmit Mailbox
+#define AT91_CAN_MAM0 0x204 // Mailbox 0 Acceptance Mask
+#define AT91_CAM_MAM_MIDvB_MASK (0x3ffff << 0) // MIDvB mask
+#define AT91_CAM_MAM_MIDvB_SHIFT (0) // MIDvB shift
+#define AT91_CAM_MAM_MIDvA_MASK (0x7ff << 18) // MIDvB mask
+#define AT91_CAM_MAM_MIDvA_SHIFT (18) // MIDvB shift
+#define AT91_CAM_MAM_MIDE (1 << 29) // Identifier Version
+#define AT91_CAN_MID0 0x208 // Mailbox 0 ID
+#define AT91_CAN_MFID0 0x20C // Mailbox 0 Family ID
+#define AT91_CAN_MSR0 0x210 // Mailbox 0 Status
+#define AT91_CAM_MSR_MDLC_MASK (0xf << 16) // Mailbox Data Length Code mask
+#define AT91_CAM_MSR_MDLC_SHIFT (16) // Mailbox Data Length Code shift
+#define AT91_CAM_MSR_MRTR (1 << 20) // Mailbox Remote Tx Request
+#define AT91_CAM_MSR_MABT (1 << 22) // Mailbox Abort
+#define AT91_CAM_MSR_MRDY (1 << 23) // Mailbox Ready
+#define AT91_CAM_MSR_MMI (1 << 24) // Mailbox Message Ignored
+#define AT91_CAN_MDL0 0x214 // Mailbox 0 Data Low
+#define AT91_CAN_MDH0 0x218 // Mailbox 0 Data High
+#define AT91_CAN_MCR0 0x21c // Mailbox 0 Control
+#define AT91_CAM_MCR_MDLC_MASK (0xf << 16) // Mailbox Data Length Code mask
+#define AT91_CAM_MCR_MDLC_SHIFT (16) // Mailbox Data Length Code shift
+#define AT91_CAM_MCR_MRTR (1 << 20) // Mailbox Remote Tx Request
+#define AT91_CAM_MCR_MACR (1 << 22) // Mailbox Abort Request
+#define AT91_CAM_MCR_MTCR (1 << 23) // Mailbox Transfer Command
+#define AT91_CAN_MMR1 0x220 // Mailbox 1 Mode
+#define AT91_CAN_MAM1 0x224 // Mailbox 1 Acceptance Mask
+#define AT91_CAN_MID1 0x228 // Mailbox 1 ID
+#define AT91_CAN_MFID1 0x22C // Mailbox 1 Family ID
+#define AT91_CAN_MSR1 0x230 // Mailbox 1 Status
+#define AT91_CAN_MDL1 0x234 // Mailbox 1 Data Low
+#define AT91_CAN_MDH1 0x238 // Mailbox 1 Data High
+#define AT91_CAN_MCR1 0x23c // Mailbox 1 Control
+
+#endif
+
+//=============================================================================
+// Pulse Width Modulation (PWM)
+
+#if defined(CYGHWR_HAL_ARM_AT91SAM7)
+
+#ifndef AT91_PWM
+#define AT91_PWM 0XFFFCC000
+#define AT91_PWM_CH0 0xFFFCC200
+#define AT91_PWM_CH1 0xFFFCC220
+#define AT91_PWM_CH2 0xFFFCC240
+#define AT91_PWM_CH3 0xFFFCC260
+#define AT91_PWM_CH_SIZE 0x20
+#endif
+
+#if defined(CYGHWR_HAL_ARM_AT91SAM7)
+#define AT91_PWM_CHANNELS 4
+#endif
+
+#define AT91_PWM_MR (0x00) // Mode
+#define AT91_PWM_MR_DIVA_MASK (0xff) // CLKA divide factor mask
+#define AT91_PWM_MR_DIVA_SHIFT (00) // CLKA divide factor shirt
+#define AT91_PWM_MR_PREA_MCK_BY_1 ( 0 << 8) // Prescale A MCLK / 1
+#define AT91_PWM_MR_PREA_MCK_BY_2 ( 1 << 8) // Prescale A MCLK / 2
+#define AT91_PWM_MR_PREA_MCK_BY_4 ( 2 << 8) // Prescale A MCLK / 4
+#define AT91_PWM_MR_PREA_MCK_BY_8 ( 3 << 8) // Prescale A MCLK / 8
+#define AT91_PWM_MR_PREA_MCK_BY_16 ( 4 << 8) // Prescale A MCLK / 16
+#define AT91_PWM_MR_PREA_MCK_BY_32 ( 5 << 8) // Prescale A MCLK / 32
+#define AT91_PWM_MR_PREA_MCK_BY_64 ( 6 << 8) // Prescale A MCLK / 64
+#define AT91_PWM_MR_PREA_MCK_BY_128 ( 7 << 8) // Prescale A MCLK / 128
+#define AT91_PWM_MR_PREA_MCK_BY_256 ( 8 << 8) // Prescale A MCLK / 256
+#define AT91_PWM_MR_PREA_MCK_BY_512 ( 9 << 8) // Prescale A MCLK / 512
+#define AT91_PWM_MR_PREA_MCK_BY_1024 (10 << 8) // Prescale A MCLK / 1024
+
+#define AT91_PWM_MR_DIVB_MASK (0xff) // CLKB divide factor mask
+#define AT91_PWM_MR_DIVB_SHIFT (16) // CLKB divide factor shirt
+#define AT91_PWM_MR_PREB_MCK_BY_1 ( 0 << 24) // Prescale B MCLK / 1
+#define AT91_PWM_MR_PREB_MCK_BY_2 ( 1 << 24) // Prescale B MCLK / 2
+#define AT91_PWM_MR_PREB_MCK_BY_4 ( 2 << 24) // Prescale B MCLK / 4
+#define AT91_PWM_MR_PREB_MCK_BY_8 ( 3 << 24) // Prescale B MCLK / 8
+#define AT91_PWM_MR_PREB_MCK_BY_16 ( 4 << 24) // Prescale B MCLK / 16
+#define AT91_PWM_MR_PREB_MCK_BY_32 ( 5 << 24) // Prescale B MCLK / 32
+#define AT91_PWM_MR_PREB_MCK_BY_64 ( 6 << 24) // Prescale B MCLK / 64
+#define AT91_PWM_MR_PREB_MCK_BY_128 ( 7 << 24) // Prescale B MCLK / 128
+#define AT91_PWM_MR_PREB_MCK_BY_256 ( 8 << 24) // Prescale B MCLK / 256
+#define AT91_PWM_MR_PREB_MCK_BY_512 ( 9 << 24) // Prescale B MCLK / 512
+#define AT91_PWM_MR_PREB_MCK_BY_1024 (10 << 24) // Prescale B MCLK / 1024
+#define AT91_PWM_ENA (0x04) // Enable
+#define AT91_PWM_CHANNEL_ID_0 (0) // Channel ID 0
+#define AT91_PWM_CHANNEL_ID_1 (1) // Channel ID 1
+#define AT91_PWM_CHANNEL_ID_2 (2) // Channel ID 2
+#define AT91_PWM_CHANNEL_ID_3 (3) // Channel ID 3
+#define AT91_PWM_CHANNEL_ID_4 (4) // Channel ID 4
+#define AT91_PWM_CHANNEL_ID_5 (5) // Channel ID 5
+#define AT91_PWM_CHANNEL_ID_6 (6) // Channel ID 6
+#define AT91_PWM_CHANNEL_ID_7 (7) // Channel ID 7
+#define AT91_PWM_DIS (0x08) // Disable
+#define AT91_PWM_SR (0x0c) // Status
+#define AT91_PWM_IER (0x10) // Interrupt Enable
+#define AT91_PWM_IDR (0x14) // Interrupt Disable
+#define AT91_PWM_IMR (0x18) // Interrupt Mask
+#define AT91_PWM_ISR (0x1c) // Interrupt Status
+#define AT91_PWM_VR (0xfc) // Version
+
+// Channel registers.
+#define AT91_PWM_CMR (0x00) // Channel Mode
+#define AT91_PWM_CMR_CPRE_MCK_BY_1 0 // Channel Prescale MCL / 1
+#define AT91_PWM_CMR_CPRE_MCK_BY_2 1 // Channel Prescale MCL / 2
+#define AT91_PWM_CMR_CPRE_MCK_BY_4 2 // Channel Prescale MCL / 4
+#define AT91_PWM_CMR_CPRE_MCK_BY_8 3 // Channel Prescale MCL / 8
+#define AT91_PWM_CMR_CPRE_MCK_BY_16 4 // Channel Prescale MCL / 16
+#define AT91_PWM_CMR_CPRE_MCK_BY_32 5 // Channel Prescale MCL / 32
+#define AT91_PWM_CMR_CPRE_MCK_BY_64 6 // Channel Prescale MCL / 64
+#define AT91_PWM_CMR_CPRE_MCK_BY_128 7 // Channel Prescale MCL / 128
+#define AT91_PWM_CMR_CPRE_MCK_BY_256 8 // Channel Prescale MCL / 256
+#define AT91_PWM_CMR_CPRE_MCK_BY_512 9 // Channel Prescale MCL / 512
+#define AT91_PWM_CMR_CPRE_MCK_BY_1024 10 // Channel Prescale MCL / 1024
+#define AT91_PWM_CMR_CPRE_MCK_A 11 // Channel MCLK A
+#define AT91_PWM_CMR_CPRE_MCK_B 12 // Channel MCLK B
+#define AT91_PWM_CMR_CALG_LEFT (0 << 8) // Left align period
+#define AT91_PWM_CMR_CALG_CENTER (1 << 8) // Center align period
+#define AT91_PWM_CMR_CPOL_LOW (0 << 9) // Low to start with
+#define AT91_PWM_CMR_CPOL_HIGH (1 << 9) // High to start with
+#define AT91_PWM_CPD_DUTY (0 << 10) // Notify the duty cycle
+#define AT91_PWM_CPD_PERIOD (1 << 10) // Notify the period
+#define AT91_PWM_CDTY (0x04) // Channel Duty Cycle
+#define AT91_PWM_CPRDR (0x08) // Channel Period
+#define AT91_PWM_CCNTR (0x0C) // Channel Counter
+#define AT91_PWM_CUPDR (0x10) // Channel Update
+
#endif
//=============================================================================
// FIQ interrupt vector which is shared by all HAL varients.
#define CYGNUM_HAL_INTERRUPT_FIQ 0
+
+//=============================================================================
+// Macros for access the GPIO lines and configuring peripheral pins
+
+// Given a pin description, determine which PIO controller it is on
+#define HAL_ARM_AT91_PIO_CTRL(_pin_) \
+ ((_pin_ >> 16) & 0xff)
+
+// Given a pin description, determine which PIO bit controls this pin
+#define HAL_ARM_AT91_PIO_BIT(_pin_) \
+ (1 << (_pin_ & 0xff))
+
+// Evaluate to true if the pin is using peripheral A
+#define HAL_ARM_AT91_PIO_A(_pin_) \
+ (((_pin_ >> 8) & 0xff) == 0)
+
+// Configure a peripheral pin on a specific PIO controller.
+#ifdef AT91_PIO_ASR
+#define HAL_ARM_AT91_PIOX_CFG(_pin_, _nr_, _pio_base_) \
+ CYG_MACRO_START \
+ if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
+ HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_PDR, \
+ HAL_ARM_AT91_PIO_BIT(_pin_)); \
+ if (HAL_ARM_AT91_PIO_A(_pin_)) { \
+ HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_ASR, \
+ HAL_ARM_AT91_PIO_BIT(_pin_)); \
+ } else { \
+ HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_BSR, \
+ HAL_ARM_AT91_PIO_BIT(_pin_)); \
+ } \
+ } \
+ CYG_MACRO_END
+#else // AT91_PIO_ASR
+#define HAL_ARM_AT91_PIOX_CFG(_pin_, _nr_, _pio_base_) \
+ CYG_MACRO_START \
+ if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
+ HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_PDR, \
+ HAL_ARM_AT91_PIO_BIT(_pin_)); \
+ } \
+ CYG_MACRO_END
+#endif // !AT91_PIO_ASR
+
+// Configure a GPIO pin direction on a specific PIO controller.
+#define HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, _nr_, _pio_base_) \
+ CYG_MACRO_START \
+ if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
+ HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_PER, \
+ HAL_ARM_AT91_PIO_BIT(_pin_)); \
+ if ((_dir_) == AT91_PIN_IN) { \
+ HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_ODR, \
+ HAL_ARM_AT91_PIO_BIT(_pin_)); \
+ } else { \
+ HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_OER, \
+ HAL_ARM_AT91_PIO_BIT(_pin_)); \
+ } \
+ } \
+ CYG_MACRO_END
+
+// Configure a GPIO pin pullup on a specific PIO controller.
+#define HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, _nr_, _pio_base_) \
+ CYG_MACRO_START \
+ if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
+ if (_enable_) { \
+ HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_PPUER, \
+ HAL_ARM_AT91_PIO_BIT(_pin_)); \
+ } else { \
+ HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_PPUDR, \
+ HAL_ARM_AT91_PIO_BIT(_pin_)); \
+ } \
+ } \
+ CYG_MACRO_END
+
+// Set a GPIO pin on a specific PIO controller to generate interrupts
+#define HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, _nr_, _pio_base_) \
+ CYG_MACRO_START \
+ if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
+ if (_enable_) { \
+ HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_IER, \
+ HAL_ARM_AT91_PIO_BIT(_pin_)); \
+ } else { \
+ HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_IDR, \
+ HAL_ARM_AT91_PIO_BIT(_pin_)); \
+ } \
+ } \
+ CYG_MACRO_END
+
+// Set a GPIO pin on a specific PIO controller.
+#define HAL_ARM_AT91_GPIOX_SET(_pin_, _nr_, _pio_base_) \
+ CYG_MACRO_START \
+ if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
+ HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_SODR, \
+ HAL_ARM_AT91_PIO_BIT(_pin_)); \
+ } \
+ CYG_MACRO_END
+
+// Reset a GPIO pin on a specific PIO controller.
+#define HAL_ARM_AT91_GPIOX_RESET(_pin_, _nr_, _pio_base_) \
+ CYG_MACRO_START \
+ if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
+ HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_CODR, \
+ HAL_ARM_AT91_PIO_BIT(_pin_)); \
+ } \
+ CYG_MACRO_END
+
+// Get a GPIO pin on a specific PIO controller.
+#define HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, _nr_, _pio_base_) \
+ CYG_MACRO_START \
+ cyg_uint32 _pdsr_; \
+ if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
+ HAL_READ_UINT32((_pio_base_)+AT91_PIO_PDSR, _pdsr_); \
+ (_value_) = (_pdsr_ & HAL_ARM_AT91_PIO_BIT(_pin_) ? 1 : 0); \
+ } \
+ CYG_MACRO_END
+
+#define AT91_PIN_IN 1
+#define AT91_PIN_OUT 0
+#define AT91_PIN_PULLUP_ENABLE 1
+#define AT91_PIN_PULLUP_DISABLE 0
+#define AT91_PIN_INTERRUPT_ENABLE 1
+#define AT91_PIN_INTERRUPT_DISABLE 0
+
+#ifndef AT91_PIOB
+// Only one PIO controller
+
+// Configure a peripheral pin for peripheral operation
+#define HAL_ARM_AT91_PIO_CFG(_pin_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_PIOX_CFG(_pin_, 0, AT91_PIO); \
+ CYG_MACRO_END
+
+// Configure a GPIO pin direction
+#define HAL_ARM_AT91_GPIO_CFG_DIRECTION(_pin_, _dir_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, 0, AT91_PIO); \
+ CYG_MACRO_END
+
+// Configure a GPIO pin pullup resistor
+#define HAL_ARM_AT91_GPIO_CFG_PULLUP(_pin_, _enable_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, 0, AT91_PIO); \
+ CYG_MACRO_END
+
+// Configure a GPIO pin to generate interrupts
+#define HAL_ARM_AT91_GPIO_CFG_INTERRUPT(_pin_, _enable_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, 0, AT91_PIO); \
+ CYG_MACRO_END
+
+// Set a GPIO pin to one
+#define HAL_ARM_AT91_GPIO_SET(_pin_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_GPIOX_SET(_pin_, 0, AT91_PIO); \
+ CYG_MACRO_END
+
+// Reset a GPIO pin to zero
+#define HAL_ARM_AT91_GPIO_RESET(_pin_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_GPIOX_RESET(_pin_, 0, AT91_PIO); \
+ CYG_MACRO_END
+
+// Get the state of a GPIO pin
+#define HAL_ARM_AT91_GPIO_GET(_pin_, _value_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 0, AT91_PIO); \
+ CYG_MACRO_END
+
+#else // !AT91_PIOB
+// Two PIO controllers
+
+// Configure a peripheral pin for peripheral operation
+#define HAL_ARM_AT91_PIO_CFG(_pin_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_PIOX_CFG(_pin_, 0, AT91_PIO); \
+ HAL_ARM_AT91_PIOX_CFG(_pin_, 1, AT91_PIOB); \
+CYG_MACRO_END
+
+// Configure a GPIO pin direction
+#define HAL_ARM_AT91_GPIO_CFG_DIRECTION(_pin_, _dir_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, 0, AT91_PIO); \
+ HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, 1, AT91_PIOB); \
+ CYG_MACRO_END
+
+// Configure a GPIO pin pullup resistor
+#define HAL_ARM_AT91_GPIO_CFG_PULLUP(_pin_, _enable_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, 0, AT91_PIO); \
+ HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, 1, AT91_PIOB); \
+ CYG_MACRO_END
+
+// Configure a GPIO pin to generate interrupts
+#define HAL_ARM_AT91_GPIO_CFG_INTERRUPT(_pin_, _enable_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, 0, AT91_PIO); \
+ HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, 1, AT91_PIOB); \
+ CYG_MACRO_END
+
+// Set a GPIO pin to 1
+#define HAL_ARM_AT91_GPIO_SET(_pin_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_GPIOX_SET(_pin_, 0, AT91_PIO); \
+ HAL_ARM_AT91_GPIOX_SET(_pin_, 1, AT91_PIOB); \
+ CYG_MACRO_END
+
+// Reset a GPIO pin to 0
+#define HAL_ARM_AT91_GPIO_RESET(_pin_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_GPIOX_RESET(_pin_, 0, AT91_PIO); \
+ HAL_ARM_AT91_GPIOX_RESET(_pin_, 1, AT91_PIOB); \
+ CYG_MACRO_END
+
+// Get the state of a GPIO pin
+#define HAL_ARM_AT91_GPIO_GET(_pin_, _value_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 0, AT91_PIO); \
+ HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 1, AT91_PIOB); \
+ CYG_MACRO_END
+#endif //!AT91_PIOB
+
+// Put a GPIO pin to a given state
+#define HAL_ARM_AT91_GPIO_PUT(_pin_, _state_) \
+ CYG_MACRO_START \
+ if (_state_) { \
+ HAL_ARM_AT91_GPIO_SET(_pin_); \
+ } else { \
+ HAL_ARM_AT91_GPIO_RESET(_pin_); \
+ } \
+ CYG_MACRO_END
+
//-----------------------------------------------------------------------------
// end of var_io.h
#endif // CYGONCE_HAL_VAR_IO_H
#include <cyg/hal/var_io.h> // platform registers
// -------------------------------------------------------------------------
-// Clock support
-
-static cyg_uint32 _period;
-
-void hal_clock_initialize(cyg_uint32 period)
-{
- CYG_ADDRESS timer = AT91_TC+AT91_TC_TC0;
-
- CYG_ASSERT(period < 0x10000, "Invalid clock period");
-
- // Disable counter
- HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_CLKDIS);
-
- // Set registers
- HAL_WRITE_UINT32(timer+AT91_TC_CMR, AT91_TC_CMR_CPCTRG | // Reset counter on CPC
- AT91_TC_CMR_CLKS_MCK32); // 1 MHz
- HAL_WRITE_UINT32(timer+AT91_TC_RC, period);
-
- // Start timer
- HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_TRIG | AT91_TC_CCR_CLKEN);
-
- // Enable timer 0 interrupt
- HAL_WRITE_UINT32(timer+AT91_TC_IER, AT91_TC_IER_CPC);
-}
+// Hardware init
-void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
+void hal_hardware_init(void)
{
- CYG_ADDRESS timer = AT91_TC+AT91_TC_TC0;
- cyg_uint32 sr;
-
- CYG_ASSERT(period < 0x10000, "Invalid clock period");
-
- HAL_READ_UINT32(timer+AT91_TC_SR, sr); // Clear interrupt
+ unsigned i;
- if (period != _period) {
- hal_clock_initialize(period);
- }
- _period = period;
+ // Reset all interrupts
+ HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IDCR, 0xFFFFFFFF);
-}
+ // Flush internal priority level stack
+ for (i = 0; i < 8; ++i)
+ HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_EOI, 0xFFFFFFFF);
-void hal_clock_read(cyg_uint32 *pvalue)
-{
- CYG_ADDRESS timer = AT91_TC+AT91_TC_TC0;
- cyg_uint32 val;
+#ifdef HAL_PLF_HARDWARE_INIT
+ // Perform any platform specific initializations
+ HAL_PLF_HARDWARE_INIT();
+#endif
- HAL_READ_UINT32(timer+AT91_TC_CV, val);
- *pvalue = val;
+ // Set up eCos/ROM interfaces
+ hal_if_init();
}
-// -------------------------------------------------------------------------
-//
-// Delay for some number of micro-seconds
-// Use timer #2 in MCLOCK/32 mode.
-//
-void hal_delay_us(cyg_int32 usecs)
+#if CYGINT_HAL_ARM_AT91_SYS_INTERRUPT
+// Decode a system interrupt. Not all systems have all interrupts. So
+// code will only be generated for those interrupts which have a
+// defined value.
+static int sys_irq_handler(void)
{
- cyg_uint32 stat;
- cyg_uint64 ticks;
-#if defined(CYGHWR_HAL_ARM_AT91_JTST)
- // TC2 is reserved for AD/DA. Use TC1 instead.
- CYG_ADDRESS timer = AT91_TC+AT91_TC_TC1;
-#else
- CYG_ADDRESS timer = AT91_TC+AT91_TC_TC2;
+ cyg_uint32 sr, mr;
+
+#ifdef CYGNUM_HAL_INTERRUPT_PITC
+ // Periodic Interrupt Timer Controller
+ HAL_READ_UINT32((AT91_PITC+AT91_PITC_PISR), sr);
+ if (sr & AT91_PITC_PISR_PITS) {
+ return CYGNUM_HAL_INTERRUPT_PITC;
+ }
#endif
- // Calculate how many timer ticks the required number of
- // microseconds equate to. We do this calculation in 64 bit
- // arithmetic to avoid overflow.
- ticks = (((cyg_uint64)usecs) * ((cyg_uint64)CYGNUM_HAL_ARM_AT91_CLOCK_SPEED))/32000000LL;
-
- // Disable counter
- HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_CLKDIS);
-
- // Set registers
- HAL_WRITE_UINT32(timer+AT91_TC_CMR, AT91_TC_CMR_CLKS_MCK32); // 1MHz
- HAL_WRITE_UINT32(timer+AT91_TC_RA, 0);
- HAL_WRITE_UINT32(timer+AT91_TC_RC, ticks);
- // Clear status flags
- HAL_READ_UINT32(timer+AT91_TC_SR, stat);
-
- // Start timer
- HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_TRIG | AT91_TC_CCR_CLKEN);
-
- // Wait for the compare
- do {
- HAL_READ_UINT32(timer+AT91_TC_SR, stat);
- } while ((stat & AT91_TC_SR_CPC) == 0);
-}
+#ifdef CYGNUM_HAL_INTERRUPT_DBG
+ // Debug Unit
+ HAL_READ_UINT32((AT91_DBG + AT91_DBG_CSR), sr);
+ HAL_READ_UINT32((AT91_DBG + AT91_DBG_IMR), mr);
+ if (sr & mr) {
+ return CYGNUM_HAL_INTERRUPT_DBG;
+ }
+#endif
-// -------------------------------------------------------------------------
-// Hardware init
+#ifdef CYGNUM_HAL_INTERRUPT_RTTC
+ /* Real Time Timer. Check the interrupt is enabled, not that just
+ the status indicates there is an interrupt. It takes a while for
+ the status bit to clear. */
+ HAL_READ_UINT32((AT91_RTTC+AT91_RTTC_RTSR), sr);
+ HAL_READ_UINT32((AT91_RTTC+AT91_RTTC_RTMR), mr);
+ if (((mr & AT91_RTTC_RTMR_ALMIEN) &&
+ (sr & AT91_RTTC_RTSR_ALMS)) ||
+ ((mr & AT91_RTTC_RTMR_RTTINCIEN) &&
+ (sr & AT91_RTTC_RTSR_RTTINC))) {
+ return CYGNUM_HAL_INTERRUPT_RTTC;
+ }
+#endif
-void hal_hardware_init(void)
-{
- unsigned i;
+#ifdef CYGNUM_HAL_INTERRUPT_PMC
+ // Power Management Controller
+ HAL_READ_UINT32((AT91_PMC+AT91_PMC_IMR), mr);
+ HAL_READ_UINT32((AT91_PMC+AT91_PMC_SR), sr);
+ if ((sr & mr) &
+ (AT91_PMC_SR_MOSCS |
+ AT91_PMC_SR_LOCK |
+ AT91_PMC_SR_MCKRDY |
+ AT91_PMC_SR_PCK0RDY |
+ AT91_PMC_SR_PCK1RDY |
+ AT91_PMC_SR_PCK2RDY |
+ AT91_PMC_SR_PCK3RDY)) {
+ return CYGNUM_HAL_INTERRUPT_PMC;
+ }
+#endif
- // Reset all interrupts
- HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IDCR, 0xFFFFFFFF);
+#ifdef CYGNUM_HAL_INTERRUPT_MC
+ // Memory controller
+ HAL_READ_UINT32((AT91_MC+AT91_MC_FMR), mr);
+ HAL_READ_UINT32((AT91_MC+AT91_MC_FSR), sr);
+ if ((sr & mr) &
+ (AT91_MC_FSR_FRDY |
+ AT91_MC_FSR_LOCKE |
+ AT91_MC_FSR_PROGE)) {
+ return CYGNUM_HAL_INTERRUPT_MC;
+ }
+#endif
- // Flush internal priority level stack
- for (i = 0; i < 8; ++i)
- HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_EOI, 0xFFFFFFFF);
-
- // Set up eCos/ROM interfaces
- hal_if_init();
+#ifdef CYGNUM_HAL_INTERRUPT_WDTC
+ // Watchdog Timer Controller
+ HAL_READ_UINT32((AT91_WDTC+AT91_WDTC_WDSR), sr);
+ HAL_READ_UINT32((AT91_WDTC+AT91_WDTC_WDMR), mr);
+ if ((mr & AT91_WDTC_WDMR_FIEN) &&
+ sr & (AT91_WDTC_WDSR_UNDER |
+ AT91_WDTC_WDSR_ERROR)) {
+ return CYGNUM_HAL_INTERRUPT_WDTC;
+ }
+#endif
+#ifdef CYGNUM_HAL_INTERRUPT_RSTC
+ // Reset Controller
+ HAL_READ_UINT32((AT91_RST + AT91_RST_RSR), sr);
+ HAL_READ_UINT32((AT91_RST + AT91_RST_RMR), mr);
+ if (((mr & AT91_RST_RMR_URSTIEN) && (sr & AT91_RST_RSR_USER)) ||
+ ((mr & AT91_RST_RMR_BODIEN) && (sr & AT91_RST_RSR_BROWN)))
+ return CYGNUM_HAL_INTERRUPT_RSTC;
+#endif
+
+ return CYGNUM_HAL_INTERRUPT_NONE;
}
+#endif
// -------------------------------------------------------------------------
// This routine is called to respond to a hardware interrupt (IRQ). It
HAL_READ_UINT32(AT91_AIC+AT91_AIC_ISR, irq_num);
- // An invalid interrrupt source is treated as a spurious interrupt
+#if CYGINT_HAL_ARM_AT91_SYS_INTERRUPT
+ if (irq_num == CYGNUM_HAL_INTERRUPT_SYS) {
+ // determine the source of the system interrupt
+ irq_num = sys_irq_handler();
+ }
+#endif
+ // An invalid interrupt source is treated as a spurious interrupt
if (irq_num < CYGNUM_HAL_ISR_MIN || irq_num > CYGNUM_HAL_ISR_MAX)
irq_num = CYGNUM_HAL_INTERRUPT_NONE;
CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
+#if CYGINT_HAL_ARM_AT91_SYS_INTERRUPT
+ if (vector >= 32) {
+ HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IDCR,
+ (1 << CYGINT_HAL_ARM_AT91_SYS_INTERRUPT));
+ return;
+ }
+#endif
HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IDCR, (1<<vector));
}
CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
+#if CYGINT_HAL_ARM_AT91_SYS_INTERRUPT
+ if (vector >= 32) {
+ hal_interrupt_configure(CYGINT_HAL_ARM_AT91_SYS_INTERRUPT, true, true);
+ HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IECR,
+ (1 <<CYGINT_HAL_ARM_AT91_SYS_INTERRUPT));
+ return;
+ }
+#endif
HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IECR, (1<<vector));
}
CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
+#if CYGINT_HAL_ARM_AT91_SYS_INTERRUPT
+ if (vector >= 32)
+ return;
+#endif
if (level) {
if (up) {
mode = AT91_AIC_SMR_LEVEL_HI;
vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
CYG_ASSERT(level >= 0 && level <= 7, "Invalid level");
+#if CYGINT_HAL_ARM_AT91_SYS_INTERRUPT
+ if (vector >= 32)
+ return;
+#endif
+
HAL_READ_UINT32(AT91_AIC+(AT91_AIC_SMR0+(vector*4)), mode);
mode = (mode & ~AT91_AIC_SMR_PRIORITY) | level;
HAL_WRITE_UINT32(AT91_AIC+(AT91_AIC_SMR0+(vector*4)), mode);
}
+#ifndef AT91_RST
/* Use the watchdog to generate a reset */
void hal_at91_reset_cpu(void)
{
HAL_WRITE_UINT32(AT91_WD + AT91_WD_OMR, AT91_WD_OMR_OKEY);
HAL_WRITE_UINT32(AT91_WD + AT91_WD_CMR, AT91_WD_CMR_CKEY);
HAL_WRITE_UINT32(AT91_WD + AT91_WD_CR, AT91_WD_CR_RSTKEY);
- HAL_WRITE_UINT32(AT91_WD + AT91_WD_OMR, AT91_WD_OMR_OKEY | AT91_WD_OMR_RSTEN | AT91_WD_OMR_WDEN);
+ HAL_WRITE_UINT32(AT91_WD + AT91_WD_OMR,
+ (AT91_WD_OMR_OKEY |
+ AT91_WD_OMR_RSTEN |
+ AT91_WD_OMR_EXTEN | // also reset external circuitry
+ AT91_WD_OMR_WDEN));
while(1) CYG_EMPTY_STATEMENT;
}
-
+#else
+/* Use the Reset Controller to generate a reset */
+void hal_at91_reset_cpu(void)
+{
+ HAL_WRITE_UINT32(AT91_RST + AT91_RST_RCR,
+ AT91_RST_RCR_PROCRST |
+ AT91_RST_RCR_ICERST |
+ AT91_RST_RCR_PERRST |
+ AT91_RST_RCR_KEY);
+ while(1) CYG_EMPTY_STATEMENT;
+}
+#endif
//--------------------------------------------------------------------------
// EOF at91_misc.c
#include <cyg/hal/var_io.h> // USART registers
+#include "hal_diag_dcc.h" // DCC initialization file
//-----------------------------------------------------------------------------
typedef struct {
cyg_uint8* base;
return res;
}
-static channel_data_t at91_ser_channels[3] = {
+static channel_data_t at91_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS] = {
+#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 0
{ (cyg_uint8*)AT91_USART0, 1000, CYGNUM_HAL_INTERRUPT_USART0, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
{ (cyg_uint8*)AT91_USART1, 1000, CYGNUM_HAL_INTERRUPT_USART1, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
-#ifdef AT91_USART2
+#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 2
{ (cyg_uint8*)AT91_USART2, 1000, CYGNUM_HAL_INTERRUPT_USART2, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD}
#endif
+#endif
+#endif
};
static void
cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
// Init channels
+#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 0
cyg_hal_plf_serial_init_channel(&at91_ser_channels[0]);
#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
cyg_hal_plf_serial_init_channel(&at91_ser_channels[1]);
-#endif
#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 2
cyg_hal_plf_serial_init_channel(&at91_ser_channels[2]);
+#endif
+#endif
#endif
// Setup procs in the vector table
// Set channel 0
+#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &at91_ser_channels[0]);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
-#endif
+
#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 2
CYGACC_CALL_IF_SET_CONSOLE_COMM(2);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+#endif
+#endif
#endif
// Restore original console
initialized = 1;
cyg_hal_plf_serial_init();
+
+#ifdef CYGBLD_HAL_ARM_AT91_DCC
+ cyg_hal_plf_dcc_init(CYGBLD_HAL_ARM_AT91_DCC_CHANNEL);
+#endif
}
void
+2008-07-21 Uwe Kindler <uwe_kindler@web.de>
+
+ * cdl/hal_arm_lpc2xxx.cdl: Added option
+ CYGHWR_HAL_ARM_LPC2XXX_VARIANT_VERSION to identify the variant version
+ because some on-chip peripherals changed slightly in newer veriants.
+ CYGNUM_HAL_ARM_LPC2XXX_PCLK is the pre calculated peripheral clock
+ value. CYGNUM_HAL_ARM_LPC2XXX_XCLK is the pre calculated XCLK
+ value.
+ * include/lpc2xxx_misc.h: Added HAL_LPC2XXX_INIT_CAN() macro fo
+ initialisation of CAN channels (required by CAN driver). Added
+ CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK to define the CAN peripheral clock
+ for CAN driver.
+ * include/lpc2xxx_misc.c: Removed functions hal_lpc_get_cclk()
+ hal_lpc_get_pclk() and hal_lpc_get_xclk() because they are not
+ required and all clock values (CCLK, PCLK and XCLK) are
+ configuration values and pre calculated in CDL file.
+ Added hal_lpc_can_init() function for initialisation of CAN
+ channels.
+
+2008-05-23 Alexey Shusharin <mrfinch@mail.ru>
+
+ * cdl/hal_arm_lpc2xxx.cdl: add suffix option to denote
+ different versions of LPC2XXX
+
+2007-08-23 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
+
+ * include/hal_var_ints.h: use interrupt priority 16 for
+ kernel test intr0/kintr0 interrupts
+
+2007-08-17 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
+
+ * cdl/hal_arm_lpc2xxx.cdl: added VIC component to support
+ configuration of individual interrupt priorities
+
+2007-07-10 Uwe Kindler <uwe_kindler@web.de>
+
+ * cdl/hal_arm_lpc2xxx.cdl: Added option
+ CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY for
+ configuration of priority of system clock interrupts.
+
+ * src/lpc2xxx_misc.c: Added support for vectored interrupt
+ controller and up to 17 interrupt priorities. This improves
+ interrupt processing time and makes processing of vectored
+ interrupts more determenistic because no for loop is required
+ for detection of interrupt source.
+
+2007-06-04 Alexey Shusharin <mrfinch@mail.ru>
+
+ * src/hal_diag.c (cyg_hal_plf_serial_isr): Fixed issue with UART
+ ISR handling. Old handler doesn't read the UxIIR register in order
+ to clear the interrupt flag. The resulted in endless interrupts
+ and the DSR never got to run.
+
+2006-02-03 Sergei Gavrikov <sg@sgs.gomel.by>
+
+ * cdl/hal_arm_lpc2xxx.cdl: Added CYGNUM_HAL_ARM_VECTOR_0x14. That
+ gives us a chance to correct a LPC2XXX program signature (ARM
+ unused vector at 0x14). The program signature is the two's
+ compliment of the checksum of the ARM7 vector table. Note:
+ you can quite overwrite that CDL value in your plf. startup
+ code (hal_platform_setup.h).
+
+2006-05-08 Andy Jackson <andy@grapevinetech.co.uk>
+
+ * src/lpc2xxx_misc.c: Fixed issue with VPBDIV initialisation on
+ non lpc22xx parts code.
+
+2006-05-08 Sergei Gavrikov <sg@belvok.com>
+
+ * src/lpc2xxx.misc (hal_hardware_init): Call HAL_PLF_HARDWARE_INIT
+ for any platform specific initialization.
+
+2006-05-07 Andy Jackson <andy@grapevinetech.co.uk>
+
+ * cdl/hal_arm_lpc2xxx.cdl: Added CYGHWR_HAL_ARM_LPC2XXX_FAMILY,
+ CYGNUM_HAL_ARM_LPC2XXX_VPBDIV, CYGNUM_HAL_ARM_LPC2XXX_XCLKDIV
+ and CYGHWR_HAL_ARM_LPC2XXX_IDLE_PWRSAVE. Changed
+ CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA to a bool.
+ * include/hal_var_ints.h: Removed lpc2xxx misc functions and
+ added an include for lpc2xxx_misc.h to avoid breaking things.
+ * include/lpc2xxx_misc.h: New header file for all the lpc2xxx
+ miscellaneous functions.
+ * include/var_arch.h: Made idle powerdown CDL controlled.
+ * include/var_io.h: Changed to use family CDL variables.
+ * src/lpc2xxx_misc.c: Changes to interrupt and VPBDIV code.
+
2004-09-12 Jani Monoses <jani@iv.ro>
* src/hal_diag.c:
puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_ARCH_H"
}
- cdl_option CYGHWR_HAL_ARM_LPC2XXX {
+ # This is going to get really messy before long as the number of parts
+ # explodes. Its useful to know the actual part in use, but its just as
+ # useful to know which family it belongs to. LPC210x shouldn't really
+ # be in the list of devices, but will probably break something if removed.
+ cdl_component CYGHWR_HAL_ARM_LPC2XXX {
display "LPC2XXX variant used"
flavor data
- default_value {"LPC210x"}
- legal_values {"LPC210x"
- "LPC2114" "LPC2119" "LPC2124" "LPC2129" "LPC2132"
- "LPC2138" "LPC2194" "LPC2212" "LPC2214" "LPC2290"
- "LPC2292" "LPC2294"}
+ default_value { "LPC210x" }
+ legal_values { "LPC210x"
+ "LPC2101" "LPC2102" "LPC2103" "LPC2104" "LPC2105" "LPC2106"
+ "LPC2114" "LPC2119" "LPC2124" "LPC2129" "LPC2131" "LPC2132"
+ "LPC2134" "LPC2136" "LPC2138" "LPC2141" "LPC2142" "LPC2144"
+ "LPC2146" "LPC2148" "LPC2194" "LPC2210" "LPC2212" "LPC2214"
+ "LPC2220" "LPC2290" "LPC2292" "LPC2294" }
+ description "
+ The LPC2XXX microcontroller family has several variants,
+ the main differences being the amount of on-chip RAM,
+ flash and peripherals. This option allows the platform
+ HALs to select the specific microcontroller being used."
- description "The LPC2XXX microcontroller family has several
- variants, the main differences being the amount of
- on-chip RAM, flash and peripherals. This option allows
- the platform HALs to select the specific
- microcontroller being used."
+ cdl_option CYGHWR_HAL_ARM_LPC2XXX_FAMILY {
+ display "LPC2XXX variant family"
+ flavor data
+ calculated {
+ is_substr(CYGHWR_HAL_ARM_LPC2XXX, "LPC22") ? "LPC22XX" :
+ is_substr(CYGHWR_HAL_ARM_LPC2XXX, "LPC213") ? "LPC213X" :
+ is_substr(CYGHWR_HAL_ARM_LPC2XXX, "LPC214") ? "LPC214X" :
+ is_substr(CYGHWR_HAL_ARM_LPC2XXX, "LPC210") ? "LPC210X" :
+ "LPC21XX"
+ }
+ description "
+ This specifies the family that the processor
+ belongs to. This is useful as it defines certain common
+ characteristics (e.g lpc22xx has the external bus and
+ lpc214x has USB) which affect which features should be
+ available in the HAL."
+ }
+
+ cdl_option CYGHWR_HAL_ARM_LPC2XXX_VARIANT_VERSION {
+ display "LPC2XXX variant version"
+ flavor data
+ calculated {
+ is_substr(CYGHWR_HAL_ARM_LPC2XXX, "LPC21") ? 1 :
+ is_substr(CYGHWR_HAL_ARM_LPC2XXX, "LPC22") ? 2 :
+ is_substr(CYGHWR_HAL_ARM_LPC2XXX, "LPC24") ? 4 : 0
+ }
+ description "
+ This specifies the variant version that the processor
+ belongs to. Some common characteristics may be
+ different in newer LPC2xxx versions. I.e. the LPC24xx variants
+ are significant different from former LPC2xxx variants."
+ }
+
+ cdl_option CYGHWR_HAL_ARM_LPC2XXX_SUFFIX {
+ display "Suffix of LPC2XXX device"
+ flavor data
+ legal_values { "no_suffix" "00" "01" }
+ default_value { "no_suffix" }
+ description "
+ This option sets the version number of LPC2XXX microcontroller.
+ To denote different version of LPC2XXX the following suffixes
+ are used: no suffix, /00, /01. All /01 version contain
+ enhanced features."
+ }
+ }
+
+ # Important! Be very careful changing this value. That will always
+ # enter the LPC2XXX bootloader after reset and consequently will
+ # never run your code. You must know what you are doing. Look at
+ # arch. vectors.S for details.
+ cdl_option CYGNUM_HAL_ARM_VECTOR_0x14 {
+ display "ARM vector at 0x14"
+ flavor data
+ default_value 0xB4405F62
+ legal_values 0 to 0xFFFFFFFF
+ description "
+ In order to detect if a valid program is present, every
+ user program must have a program signature. This signature
+ is a word-wide number that is stored in the unused
+ location in the ARM7 vector table at 0x00000014. The
+ program signature is the two's compliment of the checksum
+ of the ARM vector table."
+ }
+
+ cdl_component CYGNUM_HAL_ARM_LPC2XXX_VPBDIV {
+ display "VPB clock divisor"
+ flavor data
+ legal_values { 4 2 1 }
+ default_value { 4 }
+ description "
+ The VPB Divider determines the relationship between the
+ processor clock (cclk) and the clock used by peripheral
+ devices (pclk). The VPB Divider serves two purposes.
+ The first is to provides peripherals with desired pclk
+ via VPB bus so that they can operate at the speed chosen for the ARM
+ processor. In order to achieve this, the VPB bus may be slowed down
+ to one half or one fourth of the processor clock rate.
+ Because the VPB bus must work properly at power up (and its timing
+ cannot be altered if it does not work since the VPB divider control
+ registers reside on the VPB bus), the default condition at reset is
+ for the VPB bus to run at one quarter speed. The second purpose of
+ the VPB Divider is to allow power savings when an application
+ does not require any peripherals to run at the full processor rate.
+ This option sets the divisor for the VPB clock relative to
+ the processor clock. 4 means that the VPB clock runs at
+ one fourth the processor clock, 2 means that it runs at
+ one half of the processor clock and 1 means that it is the
+ same as the processor clock."
+
+ cdl_option CYGNUM_HAL_ARM_LPC2XXX_PCLK {
+ display "Peripheral clock"
+ flavor data
+ calculated {CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED / CYGNUM_HAL_ARM_LPC2XXX_VPBDIV}
+ description "
+ The peripheral clock is the clock derived from the processor clock
+ speed divided by the VPB clock divisor."
+ }
+ }
+
+ cdl_component CYGNUM_HAL_ARM_LPC2XXX_XCLKDIV {
+ display "XCLK clock divisor"
+ flavor data
+ legal_values { 4 2 1 }
+ default_value { 4 }
+ active_if { CYGHWR_HAL_ARM_LPC2XXX_FAMILY == "LPC22XX" }
+ description "
+ This option sets the divisor for the XCLK clock relative
+ to the processor clock. 4 means that the XCLK clock runs
+ at one fourth the processor clock, 2 means that it runs at
+ one half of the processor clock and 1 means that it is the
+ same as the processor clock."
+
+ cdl_option CYGNUM_HAL_ARM_LPC2XXX_XCLK {
+ display "Clock on XCLK pin"
+ flavor data
+ calculated {CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED / CYGNUM_HAL_ARM_LPC2XXX_VPBDIV}
+ description "
+ This option controls the clock that can be driven onto the
+ A23/XCLK pin"
+ }
}
cdl_component CYGNUM_HAL_RTC_CONSTANTS {
}
}
+ # Enable this by default, as I believe it won't affect parts that
+ # don't have the problem (other than slowing them down slightly)
+ # but causes a lock-up on those that do...
cdl_option CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA {
display "EXTINT.1 errata workaround"
- flavor data
- default_value 0
- description "On some chips writing to the EXTPOLAR or EXTMODE
- registers while VPBDIV is non-zero can corrupt the
- latter. Also reading them will yield incorrect values.
- Enable this option to work around the problem."
+ flavor bool
+ default_value 1
+ description "
+
+ On some chips writing to the EXTPOLAR or EXTMODE registers
+ while VPBDIV is non-zero can corrupt the latter. Also
+ reading them will yield incorrect values. Enable this
+ option to work around the problem."
+ }
+
+ cdl_option CYGHWR_HAL_ARM_LPC2XXX_IDLE_PWRSAVE {
+ display "Stop clock in idle loop to save power"
+ flavor bool
+ default_value { is_active(CYGPKG_REDBOOT) ? 0 : 1 }
+ description "
+ Select this option when it is desired to save power by
+ stoping the processor clock in the idle loop. This is
+ controlled by the PCON register. Generally this is a good
+ thing, but it may be necessary to disable this when
+ debugging via JTAG, as stopping the clock can prevent the
+ debugger getting control of the system."
}
+
+ cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY {
+ display "Default priority for system clock interrupts"
+ flavor data
+ legal_values { 0 to 16 }
+ default_value 0
+ description "
+ The LPC2xxx eCos HAL supports up to 17 interrupt levels.
+ Interrupt levels 0 - 15 are vectored IRQs. Vectored IRQs
+ have a higher priority then non vectored IRQs and they
+ are processed faster. Non vectored IRQs are all chained together
+ into one single slot and the ISR need to find out which interrupt
+ occured. The default value for the system clock interrupts is 0 -
+ this is the highest priority IRQ."
+ }
+
}
#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1)
-__externC cyg_uint32 hal_lpc_get_pclk(void);
-#define CYG_HAL_ARM_LPC2XXX_PCLK() hal_lpc_get_pclk()
-#define CYG_HAL_ARM_LPC2XXX_BAUD_GENERATOR(baud) \
- (CYG_HAL_ARM_LPC2XXX_PCLK()/((baud)*16))
+/* use non-vectored interrupts in kernel tests intr0/kintr0 */
+#define HAL_INTR_TEST_PRIO_A 16
+#define HAL_INTR_TEST_PRIO_B 16
+#define HAL_INTR_TEST_PRIO_C 16
//The vector used by the Real time clock
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0
-__externC void hal_lpc_watchdog_reset(void);
-#define HAL_PLATFORM_RESET() hal_lpc_watchdog_reset()
-#define HAL_PLATFORM_RESET_ENTRY 0
+// Other entries here moved to variant specific include file
+// This is included here to avoid breaking anything
+#include <cyg/hal/lpc2xxx_misc.h>
#endif // CYGONCE_HAL_VAR_INTS_H
// chance to insert code. Typical idle thread behaviour might be to halt the
// processor. These implementations halt the system core clock.
-#ifndef HAL_IDLE_THREAD_ACTION
+#ifdef CYGHWR_HAL_ARM_LPC2XXX_IDLE_PWRSAVE
+#ifndef HAL_IDLE_THREAD_ACTION
#define HAL_IDLE_THREAD_ACTION(_count_) \
CYG_MACRO_START \
CYGARC_HAL_LPC2XXX_REG_PCON_IDL); \
CYG_MACRO_END
+#endif // HAL_IDLE_THREAD_ACTION
-#endif
+#endif // CYGHWR_HAL_ARM_LPC2XXX_IDLE_MODE
//-----------------------------------------------------------------------------
// end of var_arch.h
#define CYGARC_HAL_LPC2XXX_REG_IO_BASE 0xE0028000
-
-#if defined(CYGHWR_HAL_ARM_LPC2XXX_LPC210x)
+#if defined(CYGHWR_HAL_ARM_LPC2XXX_FAMILY_LPC210X)
// Registers are offsets from base of this subsystem
#define CYGARC_HAL_LPC2XXX_REG_IOPIN 0x000
//=============================================================================
// External Memory Controller
-#if defined(CYGHWR_HAL_ARM_LPC2XXX_LPC2212) || \
- defined(CYGHWR_HAL_ARM_LPC2XXX_LPC2214)
+#if defined(CYGHWR_HAL_ARM_LPC2XXX_FAMILY_LPC22XX)
#define CYGARC_HAL_LPC2XXX_REG_BCFG0 0xFFE00000
#define CYGARC_HAL_LPC2XXX_REG_BCFG1 0xFFE00004
int res = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8 c;
- cyg_uint8 stat;
+ cyg_uint8 iir;
+
CYGARC_HAL_SAVE_GP();
*__ctrlc = 0;
- HAL_READ_UINT32(chan->base+CYGARC_HAL_LPC2XXX_REG_UxLSR, stat);
- if ( (stat & CYGARC_HAL_LPC2XXX_REG_UxLSR_RDR) != 0 ) {
+ HAL_READ_UINT32(chan->base + CYGARC_HAL_LPC2XXX_REG_UxIIR, iir);
+
+ if((iir & (CYGARC_HAL_LPC2XXX_REG_UxIIR_IIR0 | CYGARC_HAL_LPC2XXX_REG_UxIIR_IIR1 |
+ CYGARC_HAL_LPC2XXX_REG_UxIIR_IIR2)) == CYGARC_HAL_LPC2XXX_REG_UxIIR_IIR2)
+ {
+ // Rx data available or character timeout
+ // Read data in order to clear interrupt
HAL_READ_UINT32(chan->base+CYGARC_HAL_LPC2XXX_REG_UxRBR, c);
- if( cyg_hal_is_break( &c , 1 ) )
- *__ctrlc = 1;
+ if( cyg_hal_is_break( &c , 1 ) ) *__ctrlc = 1;
res = CYG_ISR_HANDLED;
}
//========================================================================*/
#include <pkgconf/hal.h>
+#include <pkgconf/hal_arm_lpc2xxx.h>
#include <cyg/infra/cyg_type.h> // base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#endif
#include <cyg/hal/var_io.h> // platform registers
-static cyg_uint32 lpc_cclk; //CPU clock frequency
-static cyg_uint32 lpc_pclk; //peripheral devices clock speed
- //(equal to, half, or quarter of CPU
- //clock)
+#include <cyg/infra/diag.h> // For diagnostic printing
+
-cyg_uint32 hal_lpc_get_pclk(void)
-{
- return lpc_pclk;
-}
// -------------------------------------------------------------------------
-// Clock support
+// eCos clock support
// Use TIMER0
static cyg_uint32 _period;
{
CYG_ADDRESS timer = CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE;
- period = period/(lpc_cclk/lpc_pclk);
+ period = period / (CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED / CYGNUM_HAL_ARM_LPC2XXX_PCLK);
// Disable and reset counter
HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTCR, 2);
// Calculate how many timer ticks the required number of
// microseconds equate to. We do this calculation in 64 bit
// arithmetic to avoid overflow.
- ticks = (((cyg_uint64)usecs) * ((cyg_uint64)lpc_pclk))/1000000LL;
+ ticks = CYGNUM_HAL_ARM_LPC2XXX_PCLK;
+ ticks = (((cyg_uint64)usecs) * (ticks))/1000000LL;
// Disable and reset counter
HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTCR, 2);
// we need to read twice consecutively to get correct value
cyg_uint32 lpc_get_vpbdiv(void)
{
- cyg_uint32 div;
+ cyg_uint32 vpbdiv_reg;
+
HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
- CYGARC_HAL_LPC2XXX_REG_VPBDIV, div);
+ CYGARC_HAL_LPC2XXX_REG_VPBDIV, vpbdiv_reg);
HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
- CYGARC_HAL_LPC2XXX_REG_VPBDIV, div);
+ CYGARC_HAL_LPC2XXX_REG_VPBDIV, vpbdiv_reg);
- return div;
+ return (vpbdiv_reg);
}
-//Set the two bits in VPBDIV which control peripheral clock division
-//div must be 1,2 or 4
-void lpc_set_vpbdiv(int div)
-{
- cyg_uint8 orig = lpc_get_vpbdiv();
-
- // update VPBDIV register
+// Set the VPBDIV register. The vpb bits are 1:0 and the xclk bits are 5:4. The
+// mapping of values passed to this routine to field values is:
+// 4 = divide by 4 (register bits 00)
+// 2 = divide by 2 (register bits 10)
+// 1 = divide by 1 (register bits 01)
+// This routine assumes that only these values can occur. As they are
+// generated in the CDL hopefully this should be the case. Fortunately
+// writing 11 merely causes the previous value to be retained.
+void lpc_set_vpbdiv(int vpbdiv, int xclkdiv)
+{
+ CYG_ASSERT(((vpbdiv & 0x3) != 3) && ((xclkdiv & 0x3) != 3),
+ "illegal VPBDIV register value");
+
+ // Update VPBDIV register
+#ifdef CYGHWR_HAL_ARM_LPC2XXX_FAMILY_LPC22XX
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
+ CYGARC_HAL_LPC2XXX_REG_VPBDIV,
+ ((xclkdiv & 0x3) << 4) | (vpbdiv & 0x3));
+#else
HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
- CYGARC_HAL_LPC2XXX_REG_VPBDIV, (div % 4) | (orig & 0xFC));
-
- lpc_pclk = lpc_cclk/div;
+ CYGARC_HAL_LPC2XXX_REG_VPBDIV, vpbdiv & 0x3);
+#endif
}
+// Perform variant setup. This optionally calls into the platform
+// HAL if it has defined HAL_PLF_HARDWARE_INIT.
void hal_hardware_init(void)
{
- lpc_cclk = CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED;
- lpc_set_vpbdiv(4);
+#ifdef CYGHWR_HAL_ARM_LPC2XXX_FAMILY_LPC22XX
+ lpc_set_vpbdiv(CYGNUM_HAL_ARM_LPC2XXX_VPBDIV,
+ CYGNUM_HAL_ARM_LPC2XXX_XCLKDIV);
+#else
+ lpc_set_vpbdiv(CYGNUM_HAL_ARM_LPC2XXX_VPBDIV, 1);
+#endif
+
+ //
+ // 0xFFFFFFFF indicates that this is a non vectored ISR
+ // This is the default setting for all interrupts
+ //
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_VIC_BASE +
+ CYGARC_HAL_LPC2XXX_REG_VICDEFVECTADDR, 0xFFFFFFFF);
+
+#ifdef HAL_PLF_HARDWARE_INIT
+ // Perform any platform specific initializations
+ HAL_PLF_HARDWARE_INIT();
+#endif
+
// Set up eCos/ROM interfaces
hal_if_init();
-
}
// -------------------------------------------------------------------------
// should interrogate the hardware and return the IRQ vector number.
int hal_IRQ_handler(void)
{
- cyg_uint32 irq_num,irq_stat;
- // Find out which interrupt caused the IRQ
- // picks the lowest if there are more.
- // FIXME:try to make use of the VIC for better latency.
- // That will probably need changes to vectors.S and
- // other int-related code
+ cyg_uint32 irq_num;
+
HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_VIC_BASE +
- CYGARC_HAL_LPC2XXX_REG_VICIRQSTAT, irq_stat);
- for (irq_num = 0; irq_num < 32; irq_num++)
- if (irq_stat & (1<<irq_num)) break;
- // No valid interrrupt source, treat as spurious interrupt
- if (irq_num < CYGNUM_HAL_ISR_MIN || irq_num > CYGNUM_HAL_ISR_MAX)
- irq_num = CYGNUM_HAL_INTERRUPT_NONE;
+ CYGARC_HAL_LPC2XXX_REG_VICVECTADDR, irq_num);
+ //
+ // if this is a non vectored ISR then we need to find out which interrupt
+ // caused the IRQ
+ //
+ if (0xFFFFFFFF == irq_num)
+ {
+ cyg_uint32 irq_stat;
+
+ // Find out which interrupt caused the IRQ. This picks the lowest
+ // if there are more than 1.
+ HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_VIC_BASE +
+ CYGARC_HAL_LPC2XXX_REG_VICIRQSTAT, irq_stat);
+ irq_num = 0;
+ while (!(irq_stat & 0x01))
+ {
+ irq_stat >>= 1;
+ irq_num++;
+ }
+
+ // If not a valid interrrupt source, treat as spurious interrupt
+ if (irq_num < CYGNUM_HAL_ISR_MIN || irq_num > CYGNUM_HAL_ISR_MAX)
+ {
+ irq_num = CYGNUM_HAL_INTERRUPT_NONE;
+ }
+ } // if (0xFFFFFFFF == irq_num)
- return irq_num;
+ return (irq_num);
}
// -------------------------------------------------------------------------
// Interrupt control
//
+// Block the the interrupt associated with the vector
void hal_interrupt_mask(int vector)
{
CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_VIC_BASE +
- CYGARC_HAL_LPC2XXX_REG_VICINTENCLEAR, 1<<vector);
+ CYGARC_HAL_LPC2XXX_REG_VICINTENCLEAR, 1 << vector);
}
+// Unblock the the interrupt associated with the vector
void hal_interrupt_unmask(int vector)
{
CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_VIC_BASE +
- CYGARC_HAL_LPC2XXX_REG_VICINTENABLE, 1<<vector);
+ CYGARC_HAL_LPC2XXX_REG_VICINTENABLE, 1 << vector);
}
+// Acknowledge the the interrupt associated with the vector. This
+// clears the interrupt but may result in another interrupt being
+// delivered
void hal_interrupt_acknowledge(int vector)
{
+
+ // External interrupts have to be cleared from the EXTINT register
+ if (vector >= CYGNUM_HAL_INTERRUPT_EINT0 &&
+ vector <= CYGNUM_HAL_INTERRUPT_EINT3)
+ {
+ // Map int vector to corresponding bit (0..3)
+ vector = 1 << (vector - CYGNUM_HAL_INTERRUPT_EINT0);
+
+ // Clear the external interrupt
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
+ CYGARC_HAL_LPC2XXX_REG_EXTINT, vector);
+ }
+
+ // Acknowledge interrupt in the VIC
HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_VIC_BASE +
CYGARC_HAL_LPC2XXX_REG_VICVECTADDR, 0);
}
+// This provides control over how an interrupt signal is detected.
+// Options are between level or edge sensitive (level) and high/low
+// level or rising/falling edge triggered (up).
+//
+// This should be simple, but unfortunately on some processor revisions,
+// it trips up on two errata issues (for the LPC2294 Rev.A these are
+// EXTINT.1 and VPBDIV.1) and so on these devices a somewhat convoluted
+// sequence in order to work properly. There is nothing in the errata
+// sequence that won't work on a processor without these issues.
void hal_interrupt_configure(int vector, int level, int up)
{
- cyg_uint32 mode;
- cyg_uint32 pol;
- // only external interrupts are configurable
+ cyg_uint32 regval, saved_vpbdiv;
+
+ // Only external interrupts are configurable
CYG_ASSERT(vector <= CYGNUM_HAL_INTERRUPT_EINT3 &&
vector >= CYGNUM_HAL_INTERRUPT_EINT0 , "Invalid vector");
-#if CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA
- // Errata sheet says VPBDIV is corrupted when accessing EXTPOL or EXTMOD
- // Must be written as 0 and at the end restored to original value
+
+ // Map int vector to corresponding bit (0..3)
+ vector = 1 << (vector - CYGNUM_HAL_INTERRUPT_EINT0);
+
+#ifdef CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA
+ // From discussions with the Philips applications engineers on the
+ // Yahoo LPC2000 forum, it appears that in order up change both
+ // EXTMODE and EXTPOLAR, the operations have to be performed in
+ // two passes as follows:
+ // old=VPBDIV (x2),
+ // VPBDIV=0, EXTMODE=n, VPBDIV=n, VPBDIV=0, EXTPOLAR=y, VPBDIV=y
+ // VPCDIV=old
+ // Save current VPBDIV register settings
+ saved_vpbdiv = lpc_get_vpbdiv();
+
+ // Clear VPBDIV register
HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
CYGARC_HAL_LPC2XXX_REG_VPBDIV, 0);
-#endif
- HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
- CYGARC_HAL_LPC2XXX_REG_EXTMODE, mode);
+
+ // Read current mode and update for level (0) or edge detection (1)
HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
- CYGARC_HAL_LPC2XXX_REG_EXTPOLAR, pol);
+ CYGARC_HAL_LPC2XXX_REG_EXTMODE, regval);
+ if (level)
+ regval &= ~vector;
+ else
+ regval |= vector;
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
+ CYGARC_HAL_LPC2XXX_REG_EXTMODE, regval);
- // map int vector to corresponding bit (0..3)
- vector = 1 << (vector - CYGNUM_HAL_INTERRUPT_EINT0);
+ // Set VPBDIV register to same value as mode
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
+ CYGARC_HAL_LPC2XXX_REG_VPBDIV, regval);
- // level or edge
- if (level) {
- mode &= ~vector;
- } else {
- mode |= vector;
- }
+ // Clear VPBDIV register
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
+ CYGARC_HAL_LPC2XXX_REG_VPBDIV, 0);
- // high/low or falling/rising
- if (up) {
- pol |= vector;
- } else {
- pol &= ~vector;
- }
+ // Read current polarity and update for trigger level or edge
+ // level: high (1), low (0) edge: rising (1), falling (0)
+ HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
+ CYGARC_HAL_LPC2XXX_REG_EXTPOLAR, regval);
+ if (up)
+ regval |= vector;
+ else
+ regval &= ~vector;
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
+ CYGARC_HAL_LPC2XXX_REG_EXTPOLAR, regval);
+
+ // Set VPBDIV register to same value as mode
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
+ CYGARC_HAL_LPC2XXX_REG_VPBDIV, regval);
+ // Restore saved VPBDIV register
HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
- CYGARC_HAL_LPC2XXX_REG_EXTMODE, mode);
+ CYGARC_HAL_LPC2XXX_REG_VPBDIV, saved_vpbdiv);
+#else
+ // Read current mode and update for level (0) or edge detection (1)
+ HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
+ CYGARC_HAL_LPC2XXX_REG_EXTMODE, regval);
+ if (level)
+ regval &= ~vector;
+ else
+ regval |= vector;
HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
- CYGARC_HAL_LPC2XXX_REG_EXTPOLAR, pol);
+ CYGARC_HAL_LPC2XXX_REG_EXTMODE, regval);
-#if CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA
- // we know this was the original value
- lpc_set_vpbdiv(lpc_cclk/lpc_pclk);
+ // Read current polarity and update for trigger level or edge
+ // level: high (1), low (0) edge: rising (1), falling (0)
+ HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
+ CYGARC_HAL_LPC2XXX_REG_EXTPOLAR, regval);
+ if (up)
+ regval |= vector;
+ else
+ regval &= ~vector;
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
+ CYGARC_HAL_LPC2XXX_REG_EXTPOLAR, regval);
#endif
+ // Clear any spurious interrupt that might have been generated
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
+ CYGARC_HAL_LPC2XXX_REG_EXTINT, vector);
}
+//
+// We support up to 17 interrupt levels
+// Interrupts 0 - 15 are vectored interrupt requests. Vectored IRQs have
+// the higher priority then non vectored IRQs, but only 16 of the 32 requests
+// can be assigned to this category. Any of the 32 requests can be assigned
+// to any of the 16 vectored IRQ slots, among which slot 0 has the highest
+// priority and slot 15 has the lowest. Priority 16 indicates a non vectored
+// IRQ.
+//
void hal_interrupt_set_level(int vector, int level)
{
CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
- CYG_ASSERT(level >= 0 && level <= 15, "Invalid level");
-
+ CYG_ASSERT(level >= 0 && level <= 16, "Invalid level");
+
+ //
+ // If level is < 16 then this is a vectored ISR and we try to write
+ // the vector number of this ISR in the right slot of the vectored
+ // interrupt controller
+ //
+ if (level < 16)
+ {
+ cyg_uint32 addr_offset = level << 2;
+ cyg_uint32 reg_val;
+
+ HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_VIC_BASE +
+ CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL0 +
+ addr_offset, reg_val);
+ CYG_ASSERT((reg_val == 0) || (reg_val == (vector | 0x20)),
+ "Priority already used by another vector");
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_VIC_BASE +
+ CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL0 +
+ addr_offset, vector | 0x20);
+ //
+ // We do not store the adress of the ISR here but we store the
+ // vector number The hal_IRQ_handler then can faster determine
+ // the right vector number
+ //
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_VIC_BASE +
+ CYGARC_HAL_LPC2XXX_REG_VICVECTADDR0 +
+ addr_offset, vector);
+ }
}
// Use the watchdog to generate a reset
CYGARC_HAL_LPC2XXX_REG_WDFEED,
CYGARC_HAL_LPC2XXX_REG_WDFEED_MAGIC2);
- while(1);
+ while(1)
+ continue;
+}
+
+#ifdef CYGPKG_DEVS_CAN_LPC2XXX
+//===========================================================================
+// Do varianat specific CAN initialisation
+//===========================================================================
+void hal_lpc_can_init(cyg_uint8 can_chan_no)
+{
+ typedef struct
+ {
+ cyg_uint32 pin_mask;
+ cyg_uint16 reg;
+ } canpincfg;
+
+ static const canpincfg canpincfg_tbl[] =
+ {
+ {0x00040000L, CYGARC_HAL_LPC2XXX_REG_PINSEL1},
+ {0x00014000L, CYGARC_HAL_LPC2XXX_REG_PINSEL1},
+ {0x00001800L, CYGARC_HAL_LPC2XXX_REG_PINSEL1},
+ {0x0F000000L, CYGARC_HAL_LPC2XXX_REG_PINSEL0},
+ };
+
+ CYG_ASSERT(can_chan_no < 4, "CAN channel number out of bounds");
+ canpincfg *pincfg = (canpincfg *)&canpincfg_tbl[can_chan_no];
+ cyg_uint32 regval;
+
+ HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_PIN_BASE + pincfg->reg, regval);
+ regval |= pincfg->pin_mask;
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_PIN_BASE + pincfg->reg, regval);
}
+#endif // CYGPKG_DEVS_CAN_LPC2XXX
//--------------------------------------------------------------------------
// EOF lpc_misc.c
display "Global command prefix"
flavor data
no_define
- default_value { "arm-elf" }
+ default_value { "arm-none-eabi" }
description "
This option specifies the command prefix used when
invoking the build tools."
display "Global compiler flags"
flavor data
no_define
- default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
description "
This option controls the global compiler flags which are used to
compile all packages by default. Individual packages may define
SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
};
cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
- user_value 1 "FSL 200740"
+ user_value 1 "FSL 200904"
};
int stat;
if (IS_FIS_FROM_NAND()) {
- base_addr = (void*)MXC_NAND_BASE_DUMMY;
+ base_addr = (void*)0;
diag_printf("Updating ROM in NAND flash\n");
} else if (IS_FIS_FROM_NOR()) {
base_addr = (void*)BOARD_FLASH_START;
description "
The processor can run at various frequencies.
These values are expressed in KHz. Note that there are
- several steppings of the rated to run at different
+ several steppings of the rate to run at different
maximum frequencies. Check the specs to make sure that your
particular processor can run at the rate you select here."
}
#define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0)
#define FDO_PAGE_SPARE_VAL 0x8
-#define MXC_NAND_BASE_DUMMY 0xE0000000
-#define NOR_FLASH_BOOT 0
-#define NAND_FLASH_BOOT 0x10
-#define SDRAM_NON_FLASH_BOOT 0x20
+#define NOR_FLASH_BOOT 0
+#define NAND_FLASH_BOOT 0x10
+#define SDRAM_NON_FLASH_BOOT 0x20
+#define MMC_BOOT 0x40
#define MXCBOOT_FLAG_REG (MX21_AITC_BASE + 0x20)
#define MXCFIS_NOTHING 0x00000000
#define MXCFIS_NAND 0x10000000
#define MXCFIS_NOR 0x20000000
+#define MXCFIS_MMC 0x40000000
#define MXCFIS_FLAG_REG (MX21_AITC_BASE + 0x24)
#define IS_BOOTING_FROM_NAND() (readl(MXCBOOT_FLAG_REG) == NAND_FLASH_BOOT)
#define IS_BOOTING_FROM_NOR() (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
#define IS_BOOTING_FROM_SDRAM() (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
+#define IS_BOOTING_FROM_MMC() (readl(MXCBOOT_FLAG_REG) == MMC_BOOT)
#ifndef MXCFLASH_SELECT_NAND
#define IS_FIS_FROM_NAND() 0
#ifndef MXCFLASH_SELECT_NOR
#define IS_FIS_FROM_NOR() 0
#else
-#define IS_FIS_FROM_NOR() (!IS_FIS_FROM_NAND())
+#define IS_FIS_FROM_NOR() (readl(MXCFIS_FLAG_REG) == MXCFIS_NOR)
+#endif
+
+#ifndef MXCFLASH_SELECT_MMC
+#define IS_FIS_FROM_MMC() 0
+#else
+#define IS_FIS_FROM_MMC() (readl(MXCFIS_FLAG_REG) == MXCFIS_MMC)
#endif
#define MXC_ASSERT_NOR_BOOT() writel(MXCFIS_NOR, MXCFIS_FLAG_REG)
-#define MXC_ASSERT_NAND_BOOT() writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
+#define MXC_ASSERT_NAND_BOOT() writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
+#define MXC_ASSERT_MMC_BOOT() writel(MXCFIS_MMC, MXCFIS_FLAG_REG)
#define SERIAL_DOWNLOAD_MAGIC 0x000000AA
#define SERIAL_DOWNLOAD_MAGIC_REG MX21_AITC_NIPRIORITY3
SSI2_BAUD,
};
-enum {
- MXC_NFC_V1,
- MXC_NFC_V2,
-};
-
-typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int);
+typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
#endif //#if !defined(__ASSEMBLER__)
{
static int init = 0;
char *msg = "\n\rARM eCos\n\r";
- uart_width lcr;
if (init++) return;
--- /dev/null
+# ====================================================================
+#
+# hal_arm_tx25.cdl
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+
+cdl_package CYGPKG_HAL_ARM_TX25KARO {
+ display "Ka-Ro TX25 module"
+ parent CYGPKG_HAL_ARM_MX25
+ requires CYGINT_ISO_CTYPE
+ hardware
+ include_dir cyg/hal
+ define_header hal_arm_tx25.h
+ description "
+ This HAL platform package provides generic
+ support for the Ka-Ro electronics TX25 module."
+
+ compile tx25_misc.c tx25_diag.c
+ implements CYGINT_HAL_DEBUG_GDB_STUBS
+ implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+ implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+
+ implements CYGHWR_HAL_ARM_SOC_UART1
+ implements CYGHWR_HAL_ARM_SOC_UART2
+ implements CYGHWR_HAL_ARM_SOC_UART3
+ implements CYGHWR_HAL_ARM_SOC_UART4
+
+ requires {CYGBLD_BUILD_REDBOOT == 1}
+
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_soc.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_tx25.h>"
+ puts $::cdl_header "#define HAL_PLATFORM_CPU \"Freescale i.MX25 based\""
+ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Ka-Ro TX25 processor module\""
+ puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 2177"
+ puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK tx25_program_new_stack"
+ }
+
+ cdl_component CYG_HAL_STARTUP {
+ display "Startup type"
+ flavor data
+ default_value { "ROMRAM" }
+ legal_values { "ROMRAM" }
+ no_define
+ define -file system.h CYG_HAL_STARTUP
+ description "
+ The only startup type allowed is ROMRAM, since this will allow
+ the program to exist in ROM, but be copied to RAM during startup
+ which is required to boot from NAND flash."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ display "Diagnostic serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the console port.
+ Note: this should match the value chosen for the GDB port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ display "GDB serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the GDB port.
+ Note: this should match the value chosen for the console port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the TX25"
+ flavor data
+ calculated 3
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ The TX25 provides access to three serial ports. This option
+ chooses which port will be used to connect to a host
+ running GDB."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+ display "Default console channel."
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ calculated 0
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Console serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ description "
+ The TX25 provides access to three serial ports. This option
+ chooses which port will be used for console output."
+ }
+
+ cdl_component CYGBLD_GLOBAL_OPTIONS {
+ display "Global build options"
+ flavor none
+ no_define
+ description "
+ Global build options including control over
+ compiler flags, linker flags and choice of toolchain."
+
+
+ parent CYGPKG_NONE
+
+ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ display "Global command prefix"
+ flavor data
+ no_define
+ default_value { "arm-926ejs-linux-gnu" }
+ description "
+ This option specifies the command prefix used when
+ invoking the build tools."
+ }
+
+ cdl_option CYGBLD_GLOBAL_CFLAGS {
+ display "Global compiler flags"
+ flavor data
+ no_define
+ requires CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS
+ default_value { "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe" }
+ description "
+ This option controls the global compiler flags which are used to
+ compile all packages by default. Individual packages may define
+ options which override these global flags."
+ }
+
+ cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ display "Global linker flags"
+ flavor data
+ no_define
+ default_value { "-Wl,--gc-sections -Wl,-static -O2 -nostdlib" }
+ description "
+ This option controls the global linker flags. Individual
+ packages may define options which override these global flags."
+ }
+ }
+
+ cdl_component CYGPKG_HAL_ARM_TX25_OPTIONS {
+ display "Ka-Ro electronics TX25 module build options"
+ flavor none
+ no_define
+ requires { CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0 }
+ description "
+ Package specific build options including control over
+ compiler flags used only in building this package,
+ and details of which tests are built."
+
+ cdl_option CYGNUM_HAL_ARM_TX25_SDRAM_SIZE {
+ display "SDRAM size"
+ flavor data
+ legal_values { 0x02000000 0x04000000 0x08000000 }
+ default_value { 0x04000000 }
+# This is what I would like to do, but define_proc currently does not allow for
+# accessing variables
+# display "SDRAM size in MiB"
+# legal_values { 64 128 }
+# default_value { 64 }
+# define_proc {
+# puts $::cdl_header "#define CYGNUM_HAL_ARM_TX25_SDRAM_SIZE \
+# [format "0x%08x" [expr $CYGNUM_HAL_ARM_TX25_SDRAM_SIZE * 1048576]]"
+# }
+ description "
+ This option specifies the SDRAM size of the TX25 module."
+ }
+
+ cdl_option CYGOPT_HAL_ARM_TX25_DEBUG {
+ display "Enable low level debugging with LED"
+ flavor bool
+ default_value { false }
+ description "
+ This option enables low level debugging by blink codes
+ of the LED on STK5."
+ }
+
+ cdl_option CYGPKG_HAL_ARM_TX25_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the TX25 HAL. These flags are used in addition
+ to the set of global flags."
+ }
+
+ cdl_option CYGPKG_HAL_ARM_TX25_CFLAGS_REMOVE {
+ display "Suppressed compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the TX25 HAL. These flags are removed from
+ the set of global flags if present."
+ }
+
+ }
+
+ cdl_component CYGHWR_MEMORY_LAYOUT {
+ display "Memory layout"
+ flavor data
+ no_define
+ calculated { "arm_tx25_romram" }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ display "Memory layout linker script fragment"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+ calculated { "<pkgconf/mlt_arm_tx25_romram.ldi>" }
+ }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ display "Memory layout header file"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_H
+ calculated { "<pkgconf/mlt_arm_tx25_romram.h>" }
+ }
+ }
+
+ cdl_option CYGSEM_HAL_ROM_MONITOR {
+ display "Behave as a ROM monitor"
+ flavor bool
+ default_value 0
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+ description "
+ Enable this option if this program is to be used as a ROM monitor,
+ i.e. applications will be loaded into RAM on the TX25 module, and this
+ ROM monitor may process exceptions or interrupts generated from the
+ application. This enables features such as utilizing a separate
+ interrupt stack when exceptions are generated."
+ }
+
+ cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ display "Work with a ROM monitor"
+ flavor booldata
+ legal_values { "Generic" "GDB_stubs" }
+ default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "RAM" }
+ description "
+ Support can be enabled for different varieties of ROM monitor.
+ This support changes various eCos semantics such as the encoding
+ of diagnostic output, or the overriding of hardware interrupt
+ vectors.
+ Firstly there is \"Generic\" support which prevents the HAL
+ from overriding the hardware vectors that it does not use, to
+ instead allow an installed ROM monitor to handle them. This is
+ the most basic support which is likely to be common to most
+ implementations of ROM monitor.
+ \"GDB_stubs\" provides support when GDB stubs are included in
+ the ROM monitor or boot ROM."
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ display "Redboot HAL options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+ description "
+ This option lists the target's requirements for a valid Redboot
+ configuration."
+
+ compile -library=libextras.a redboot_cmds.c
+
+ cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ display "Build Redboot ROM binary image"
+ active_if CYGBLD_BUILD_REDBOOT
+ default_value 1
+ no_define
+ description "This option enables the conversion of the Redboot ELF
+ image to a binary image suitable for ROM programming."
+
+ make -priority 325 {
+ <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+ $(OBJCOPY) -O binary $< $@
+ $(COMMAND_PREFIX)nm $< | awk 'NF == 3 {print}' | sort > $(<:.elf=.map)
+ }
+ }
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_TX25_OPTIONS {
+ display "Redboot HAL variant options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+
+ # RedBoot details
+ requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x80108000 }
+ define_proc {
+ puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00"
+ }
+ }
+}
--- /dev/null
+#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
+#define CYGONCE_HAL_PLATFORM_SETUP_H
+
+//=============================================================================
+//
+// hal_platform_setup.h
+//
+// Platform specific support for HAL (assembly code)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <pkgconf/system.h> // System-wide configuration info
+#include CYGBLD_HAL_VARIANT_H // Variant specific configuration
+#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
+#include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
+#include <cyg/hal/hal_mmu.h> // MMU definitions
+#include <cyg/hal/karo_tx25.h> // Platform specific hardware definitions
+#include CYGHWR_MEMORY_LAYOUT_H
+
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1 _platform_setup1
+#define CYGHWR_HAL_ARM_HAS_MMU
+
+//#define INTERNAL_BOOT_MODE
+
+#if defined(INTERNAL_BOOT_MODE)
+#define PLATFORM_PREAMBLE setup_flash_header
+#endif
+
+#ifdef CYG_HAL_STARTUP_ROMRAM
+#define CYGSEM_HAL_ROM_RESET_USES_JUMP
+#endif
+
+#define TX25_NAND_PAGE_SIZE 2048
+#define TX25_NAND_BLKS_PER_PAGE 64
+
+#define DEBUG_LED_BIT 7
+
+#ifndef CYGOPT_HAL_ARM_TX25_DEBUG
+ .macro LED_CTRL,val
+ .endm
+ .macro LED_BLINK,val
+ .endm
+ .macro DELAY,ms
+ .endm
+#else
+#define USE_SERIAL
+#define CYGHWR_LED_MACRO LED_BLINK #\x
+ .macro DELAY,ms
+ ldr r10, =\ms
+111:
+ subs r10, r10, #1
+ bmi 113f
+ ldr r9, =3600
+112:
+ subs r9, r9, #1
+ bne 112b
+ b 111b
+ .ltorg
+113:
+ .endm
+
+ .macro LED_CTRL,val
+ // switch user LED (GPIO2[7] PAD A21) on STK5
+ ldr r10, GPIO2_BASE_ADDR_W
+ // GPIO_DR
+ mov r9, \val
+ cmp r9, #0
+ movne r9, #(1 << DEBUG_LED_BIT) // LED ON
+ moveq r9, #0 // LED OFF
+ str r9, [r10, #GPIO_DR]
+ .endm
+
+ .macro LED_BLINK,val
+ mov r3, \val
+211:
+ subs r3, r3, #1
+ bmi 212f
+ LED_CTRL #1
+ DELAY 200
+ LED_CTRL #0
+ DELAY 300
+ b 211b
+212:
+ DELAY 1000
+ .endm
+#endif
+
+#ifdef USE_SERIAL
+ .macro early_uart_setup
+ ldr r1, IOMUXC_BASE_ADDR_W
+ mov r0, #0
+ str r0, [r1, #0x170]
+ str r0, [r1, #0x17c]
+ str r0, [r1, #0x174]
+ str r0, [r1, #0x178]
+ mov r0, #0x1e0
+ str r0, [r1, #0x368]
+ str r0, [r1, #0x370]
+ mov r0, #0x040
+ str r0, [r1, #0x36c]
+ str r0, [r1, #0x374]
+
+ ldr r1, UART1_BASE_ADDR_W
+ mov r0, #(1 << 0) @ UART_EN
+// orr r0, r0, #(1 << 14) @ ADEN
+ str r0, [r1, #0x80] @ UCR1
+
+ mov r0, #(1 << 14) @ IRTS
+ orr r0, r0, #((1 << 5) | (1 << 2) | (1 << 1)) @ word size 8bit, TXEN, RXEN
+ str r0, [r1, #0x84] @ UCR2
+
+ ldr r0, [r1, #0x88] @ UCR3
+ orr r0, r0, #(1 << 2) @ RXDMUXSEL
+ str r0, [r1, #0x88] @ UCR3
+
+ ldr r0, UART1_UBIR_W
+ str r0, [r1, #0xa4] @ UBIR
+
+ ldr r0, UART1_UBMR_W
+ str r0, [r1, #0xa8] @ UBMR
+#if 0
+1:
+#if 0
+ ldr r0, [r1, #0x94] @ USR1
+ tst r0, #(1 << 4) @ AWAKE
+ beq 1b
+#else
+ ldr r0, [r1, #0x98] @ USR2
+ tst r0, #(1 << 15) @ ADET
+ beq 1b
+#endif
+ mov r0, #'*'
+ str r0, [r1, #0x40] @TXFIFO
+#if 0
+ mov r2, #RAM_BANK1_BASE
+ ldr r0, [r1, #0xa4] @ UBIR
+ str r0, [r2], #4
+ ldr r0, [r1, #0xa8] @ UBMR
+ str r0, [r2], #4
+#endif
+#endif
+ .endm
+
+ .macro uart_putc,c
+ ldr r9, UART1_BASE_ADDR_W
+111:
+ ldr r10, [r9, #0xb4] @ UTS
+ tst r10, #(1 << 4) @ TXFULL
+ bne 111b
+ mov r10, \c
+ str r10, [r9, #0x40]
+ .endm
+
+ .set progress_ind, 'A'
+ .macro progress
+ uart_putc #progress_ind
+ .set progress_ind, progress_ind + 1
+ .endm
+#else
+ .macro early_uart_setup
+ .endm
+ .macro uart_putc,c
+ .endm
+ .macro progress
+ .endm
+#endif
+
+ .macro LED_INIT
+ // initialize GPIO2[7] (Pad A21) for LED on STK5
+ ldr r10, GPIO2_BASE_ADDR_W
+ // GPIO_GDIR
+ mov r9, #(1 << DEBUG_LED_BIT)
+ str r9, [r10, #GPIO_GDIR]
+
+ ldr r10, IOMUXC_BASE_ADDR_W
+ mov r9, #0x15
+ str r9, [r10, #0x2c]
+
+ ldr r10, GPIO2_BASE_ADDR_W
+ // GPIO_DR
+ mov r9, #(1 << DEBUG_LED_BIT) // LED ON
+ str r9, [r10, #GPIO_DR]
+ .endm
+
+// This macro represents the initial startup code for the platform
+// r11 is reserved to contain chip rev info in this file
+ .macro _platform_setup1
+KARO_TX25_SETUP_START:
+ // invalidate I/D cache/TLB
+ mov r0, #0
+ mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
+ mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+ mcr 15, 0, r0, c7, c10, 4 /* Data Write Barrier */
+
+init_spba_start:
+ init_spba
+init_aips_start:
+ init_aips
+init_max_start:
+ init_max
+init_m3if_start:
+ init_m3if
+
+#ifndef INTERNAL_BOOT_MODE
+ // check if sdram has been setup
+#ifdef RAM_BANK1_SIZE
+ cmp pc, #RAM_BANK1_BASE
+ blo init_clock_start
+ cmp pc, #(RAM_BANK1_BASE + RAM_BANK1_SIZE)
+ blo HWInitialise_skip_SDRAM_setup
+#else
+ cmp pc, #RAM_BANK0_BASE
+ blo init_clock_start
+ cmp pc, #(RAM_BANK0_BASE + RAM_BANK0_SIZE)
+ blo HWInitialise_skip_SDRAM_setup
+#endif // RAM_BANK1_SIZE
+#endif // INTERNAL_BOOT_MODE
+init_clock_start:
+ init_clock
+
+ LED_INIT
+ LED_BLINK #1
+
+ early_uart_setup
+
+#ifndef INTERNAL_BOOT_MODE
+
+init_sdram_start:
+ setup_sdram
+ LED_BLINK #2
+
+ progress
+#endif
+
+HWInitialise_skip_SDRAM_setup:
+ mov r0, #NFC_BASE
+ add r2, r0, #0x0800 // 2K window
+ cmp pc, r0
+ blo Normal_Boot_Continue
+ cmp pc, r2
+ bhi Normal_Boot_Continue
+
+NAND_Boot_Start:
+ progress
+ /* Copy image from NFC buffer to SDRAM first */
+ ldr r1, MXC_REDBOOT_RAM_START
+1:
+ ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ blo 1b
+
+ progress
+
+ bl jump_to_sdram
+ progress
+
+NAND_Copy_Main:
+ mov r0, #NFC_BASE // r0: nfc base. Reloaded after each page copy
+ add r12, r0, #0x1E00 // r12: NFC register base. Doesn't change
+ ldrh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+ orr r3, r3, #0x1
+
+ /* Setting NFC */
+ ldr r7, CCM_BASE_ADDR_W
+ ldr r1, [r7, #CLKCTL_RCSR]
+ /* BUS WIDTH setting */
+ tst r1, #(1 << 24)// Freescale: 0x20000000
+ orrne r1, r1, #(1 << 14)
+ biceq r1, r1, #(1 << 14)
+
+ /* 4K PAGE */
+ tst r1, #(1 << 27)// Freescale: 0x10000000
+ orrne r1, r1, #(1 << 9)
+ bne 1f
+ /* 2K PAGE */
+ bic r1, r1, #(1 << 9)
+ tst r1, #(1 << 26)// Freescale: 0x08000000
+ orrne r1, r1, #(1 << 8) /* 2KB page size */
+ biceq r1, r1, #(1 << 8) /* 512B page size */
+ movne r2, #(64 >> 1) /* 64 bytes */
+ moveq r2, #8 /* 16 bytes */
+ b NAND_setup
+1:
+ tst r1, #(1 << 26)// Freescale: 0x08000000
+ bicne r3, r3, #1 /* Enable 8bit ECC mode */
+ movne r2, #109 /* 218 bytes */
+ moveq r2, #(128 >> 1) /* 128 bytes */
+NAND_setup:
+ str r1, [r7, #CLKCTL_RCSR]
+ strh r2, [r12, #ECC_RSLT_SPARE_AREA_REG_OFF]
+ strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+
+ //unlock internal buffer
+ mov r3, #0x2
+ strh r3, [r12, #NFC_CONFIGURATION_REG_OFF]
+ //unlock nand device
+ mov r3, #0
+ strh r3, [r12, #UNLOCK_START_BLK_ADD_REG_OFF]
+ sub r3, r3, #1
+ strh r3, [r12, #UNLOCK_END_BLK_ADD_REG_OFF]
+ mov r3, #4
+ strh r3, [r12, #NF_WR_PROT_REG_OFF]
+
+ /* r0: NFC base address. RAM buffer base address. [Updated constantly]
+ * r1: starting flash address to be copied. [Updated constantly]
+ * r2: page size. [Doesn't change]
+ * r3: used as argument.
+ * r11: starting SDRAM address for copying. [Updated constantly].
+ * r12: NFC register base address. [Updated constantly].
+ * r13: end of SDRAM address for copying. [Doesn't change].
+ */
+ mov r1, #0x1000
+ ldr r3, [r7, #CLKCTL_RCSR]
+ tst r3, #(1 << 9)
+ movne r2, #0x1000
+ bne 1f
+ tst r3, #(1 << 8)
+ mov r1, #0x800
+ movne r2, #0x800
+ moveq r2, #0x200
+1:
+ /* Update the indicator of copy area */
+ ldr r11, MXC_REDBOOT_RAM_START
+ add r13, r11, #REDBOOT_IMAGE_SIZE
+ add r11, r11, r1
+
+Nfc_Read_Page:
+ mov r3, #0x0
+ nfc_cmd_input
+
+ cmp r2, #0x800
+ bhi nfc_addr_ops_4kb
+ beq nfc_addr_ops_2kb
+
+ mov r3, r1
+ do_addr_input //1st addr cycle
+ mov r3, r1, lsr #9
+ do_addr_input //2nd addr cycle
+ mov r3, r1, lsr #17
+ do_addr_input //3rd addr cycle
+ mov r3, r1, lsr #25
+ do_addr_input //4th addr cycle
+ b end_of_nfc_addr_ops
+
+nfc_addr_ops_2kb:
+ mov r3, #0
+ do_addr_input //1st addr cycle
+ mov r3, #0
+ do_addr_input //2nd addr cycle
+ mov r3, r1, lsr #11
+ do_addr_input //3rd addr cycle
+ mov r3, r1, lsr #19
+ do_addr_input //4th addr cycle
+ mov r3, r1, lsr #27
+ do_addr_input //5th addr cycle
+
+ mov r3, #0x30
+ nfc_cmd_input
+ b end_of_nfc_addr_ops
+
+nfc_addr_ops_4kb:
+ mov r3, #0
+ do_addr_input //1st addr cycle
+ mov r3, #0
+ do_addr_input //2nd addr cycle
+ mov r3, r1, lsr #12
+ do_addr_input //3rd addr cycle
+ mov r3, r1, lsr #20
+ do_addr_input //4th addr cycle
+ mov r3, r1, lsr #27
+ do_addr_input //5th addr cycle
+
+ mov r3, #0x30
+ nfc_cmd_input
+
+end_of_nfc_addr_ops:
+ mov r8, #0
+ bl nfc_data_output
+ bl do_wait_op_done
+ // Check if x16/2kb page
+ cmp r2, #0x800
+ bhi nfc_addr_data_output_done_4k
+ beq nfc_addr_data_output_done_2k
+ beq nfc_addr_data_output_done_512
+
+ // check for bad block
+// mov r3, r1, lsl #(32-17) // get rid of block number
+// cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
+ b nfc_addr_data_output_done
+
+nfc_addr_data_output_done_4k:
+//TODO
+ b nfc_addr_data_output_done
+
+nfc_addr_data_output_done_2k:
+ // check for bad block
+//TODO: mov r3, r1, lsl #(32-17) // get rid of block number
+// cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
+ b nfc_addr_data_output_done
+
+nfc_addr_data_output_done_512:
+ // check for bad block
+// TODO: mov r3, r1, lsl #(32-5-9) // get rid of block number
+// TODO: cmp r3, #(512 << (32-5-9)) // check if not page 0 or 1
+
+nfc_addr_data_output_done:
+#if 0
+ bhi Copy_Good_Blk
+ add r4, r0, #0x1000 //r3 -> spare area buf 0
+ ldrh r4, [r4, #0x4]
+ and r4, r4, #0xFF00
+ cmp r4, #0xFF00
+ beq Copy_Good_Blk
+ // really sucks. Bad block!!!!
+ cmp r3, #0x0
+ beq Skip_bad_block
+ // even suckier since we already read the first page!
+ // Check if x16/2kb page
+ cmp r2, #0x800
+ // for 4k page
+ subhi r11, r11, #0x1000 //rewind 1 page for the sdram pointer
+ subhi r1, r1, #0x1000 //rewind 1 page for the flash pointer
+ // for 2k page
+ subeq r11, r11, #0x800 //rewind 1 page for the sdram pointer
+ subeq r1, r1, #0x800 //rewind 1 page for the flash pointer
+ // for 512 page
+ sublo r11, r11, #512 //rewind 1 page for the sdram pointer
+ sublo r1, r1, #512 //rewind 1 page for the flash pointer
+Skip_bad_block:
+ // Check if x16/2kb page
+ ldr r7, CCM_BASE_ADDR_W
+ ldr r7, [r7, #CLKCTL_RCSR]
+ tst r7, #0x200
+ addne r1, r1, #(128 * 4096)
+ bne Skip_bad_block_done
+ tst r7, #0x100
+ addeq r1, r1, #(32 * 512)
+ addne r1, r1, #(64 * 2048)
+Skip_bad_block_done:
+ b Nfc_Read_Page
+#endif
+Copy_Good_Blk:
+ uart_putc #'.'
+ // copying page
+ add r2, r2, #NFC_BASE
+1:
+ ldmia r0!, {r3-r10}
+ stmia r11!, {r3-r10}
+ cmp r0, r2
+ blo 1b
+ sub r2, r2, #NFC_BASE
+
+ cmp r11, r13
+ bge NAND_Copy_Main_done
+ // Check if x16/2kb page
+ add r1, r1, r2
+ mov r0, #NFC_BASE
+ b Nfc_Read_Page
+
+NAND_Copy_Main_done:
+Normal_Boot_Continue:
+Now_in_SDRAM:
+ LED_BLINK #4
+
+STACK_Setup:
+ // Set up a stack [for calling C code]
+ ldr sp, =__startup_stack
+
+ // Create MMU tables
+ bl hal_mmu_init
+ LED_BLINK #5
+
+ // Enable MMU
+ ldr r2, =10f
+ mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
+ orr r1, r1, #7 // enable MMU bit
+
+ mcr MMU_CP, 0, r1, MMU_Control, c0
+ mov pc, r2 /* Change address spaces */
+ nop
+10:
+ LED_BLINK #6
+ .endm // _platform_setup1
+
+jump_to_sdram:
+ ldr r0, SDRAM_ADDR_MASK
+ ldr r1, MXC_REDBOOT_RAM_START
+ and r0, lr, r0
+ sub r0, r1, r0
+ add lr, lr, r0
+ mov pc, lr
+
+do_wait_op_done:
+ ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
+ beq do_wait_op_done
+ bx lr // do_wait_op_done
+
+nfc_data_output:
+ ldrh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+ orr r3, r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
+ strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+
+ strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
+
+ mov r3, #FDO_PAGE_SPARE_VAL
+ strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ bx lr
+
+#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1
+#endif
+
+ /* Do nothing */
+ .macro init_spba
+ .endm /* init_spba */
+
+ /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
+ .macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, AIPS1_CTRL_BASE_ADDR_W
+ ldr r1, AIPS1_PARAM_W
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ ldr r0, AIPS2_CTRL_BASE_ADDR_W
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ .endm /* init_aips */
+
+ /* MAX (Multi-Layer AHB Crossbar Switch) setup */
+ .macro init_max
+ ldr r0, MAX_BASE_ADDR_W
+ /* MPR - priority for MX25 is IAHB>DAHB>USBOTG>RTIC>(SDHC2/SDMA) */
+ ldr r1, MAX_PARAM1
+ str r1, [r0, #0x000] /* for S0 */
+ str r1, [r0, #0x100] /* for S1 */
+ str r1, [r0, #0x200] /* for S2 */
+ str r1, [r0, #0x300] /* for S3 */
+ str r1, [r0, #0x400] /* for S4 */
+ /* SGPCR - always park on last master */
+ ldr r1, =0x10
+ str r1, [r0, #0x010] /* for S0 */
+ str r1, [r0, #0x110] /* for S1 */
+ str r1, [r0, #0x210] /* for S2 */
+ str r1, [r0, #0x310] /* for S3 */
+ str r1, [r0, #0x410] /* for S4 */
+ /* MGPCR - restore default values */
+ ldr r1, =0x0
+ str r1, [r0, #0x800] /* for M0 */
+ str r1, [r0, #0x900] /* for M1 */
+ str r1, [r0, #0xA00] /* for M2 */
+ str r1, [r0, #0xB00] /* for M3 */
+ str r1, [r0, #0xC00] /* for M4 */
+ .endm /* init_max */
+
+ /* Clock setup */
+ .macro init_clock
+ ldr r0, CCM_BASE_ADDR_W
+
+ /* default CLKO to 1/6 of the USB PLL */
+ ldr r1, [r0, #CLKCTL_MCR]
+ bic r1, r1, #0x00F00000
+ bic r1, r1, #0x7F000000
+ mov r2, #0x45000000 /* set CLKO divider to 6 */
+ add r2, r2, #0x00600000 /* select usb_clk clock source for CLKO */
+ orr r1, r1, r2
+ str r1, [r0, #CLKCTL_MCR]
+
+ ldr r1, CCM_CCTL_VAL_W
+ str r1, [r0, #CLKCTL_CCTL] /* configure ARM clk */
+
+ /* enable all the clocks */
+ ldr r2, CCM_CGR0_W
+ str r2, [r0, #CLKCTL_CGR0]
+ ldr r2, CCM_CGR1_W
+ str r2, [r0, #CLKCTL_CGR1]
+ ldr r2, CCM_CGR2_W
+ str r2, [r0, #CLKCTL_CGR2]
+ .endm /* init_clock */
+
+ /* M3IF setup */
+ .macro init_m3if
+ /* Configure M3IF registers */
+ ldr r1, M3IF_BASE_W
+ /*
+ * M3IF Control Register (M3IFCTL) for MX25
+ * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
+ * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
+ * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
+ * MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
+ * MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000
+ * MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000
+ * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
+ * ----------
+ * 0x00000001
+ */
+ ldr r0, =0x00000001
+ str r0, [r1] /* M3IF control reg */
+ .endm /* init_m3if */
+
+ .macro setup_sdram
+ ldr r0, IOMUXC_BASE_ADDR_W
+ mov r1, #0x800
+ str r1, [r0, #0x454]
+
+ ldr r0, ESDCTL_BASE_W
+ mov r1, #RAM_BANK0_BASE
+ bl setup_sdram_bank
+#ifdef RAM_BANK1_SIZE
+ mov r1, #RAM_BANK1_BASE
+ bl setup_sdram_bank
+#endif
+ .endm
+
+ .macro nfc_cmd_input
+ strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
+ mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
+ strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ bl do_wait_op_done
+ .endm // nfc_cmd_input
+
+ .macro do_addr_input
+ and r3, r3, #0xFF
+ strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
+ mov r3, #NAND_FLASH_CONFIG2_FADD_EN
+ strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ bl do_wait_op_done
+ .endm // do_addr_input
+
+ /* To support 133MHz DDR */
+ .macro init_iomuxc
+ mov r0, #0x2
+ ldr r1, IOMUXC_BASE_ADDR_W
+ add r1, r1, #0x368
+ add r2, r1, #0x4C8 - 0x368
+1:
+ str r0, [r1], #4
+ cmp r1, r2
+ ble 1b
+ .endm /* init_iomuxc */
+
+#define ESDCTL_NORMAL (0 << 28)
+#define ESDCTL_PCHG (1 << 28)
+#define ESDCTL_AREF (2 << 28)
+#define ESDCTL_LMOD (3 << 28)
+#define ESDCTL_SLFRFSH (4 << 28)
+
+#define RA_BITS 2 /* row addr bits - 11 */
+#define CA_BITS 1 /* 0-2: col addr bits - 8 3: rsrvd */
+#define DSIZ 1 /* 0: D[31..16] 1: D[15..D0] 2: D[31..0] 3: rsrvd */
+#define SREFR 3 /* 0: disabled 1-5: 2^n rows/clock *: rsrvd */
+#define PWDT 1 /* 0: disabled 1: precharge pwdn
+ 2: pwdn after 64 clocks 3: pwdn after 128 clocks */
+#define FP 1 /* 0: not full page 1: full page */
+#define BL 1 /* 0: 4(not for LPDDR) 1: 8 */
+#define PRCT 0 /* 0: disabled *: clks / 2 (0..63) */
+#define ESDCTLVAL (0x80000000 | (RA_BITS << 24) | (CA_BITS << 20) | \
+ (DSIZ << 16) | (SREFR << 13) | (PWDT << 10) | (FP << 8) | \
+ (BL << 7) | (PRCT << 0))
+
+#define tXP 0 /* clks - 1 (0..3) */ // N/A
+#define tWTR 0 /* clks - 1 (0..1) */ // N/A
+#define tRP 2 /* clks - 1 (0..3) */ // 2
+#define tMRD 1 /* clks - 1 (0..3) */ // 1
+#define tWR 0 /* clks - 2 (0..1) */ // 0
+#define tRAS 5 /* clks - 1 (0..7) */ // 5
+#define tRRD 1 /* clks - 1 (0..3) */ // 1
+#define tCAS 2 /* 0: 3 clks[LPDDR] 1: rsrvd *: clks (2..3) */ // 3
+#define tRCD 2 /* clks - 1 (0..7) */ // 2
+#define tRC 7 /* 0: 20 *: clks - 1 (0..15) */ // 8
+
+#define ESDCFGVAL ((tXP << 21) | (tWTR << 20) | (tRP << 18) | (tMRD << 16) | \
+ (tWR << 15) | (tRAS << 12) | (tRRD << 10) | (tCAS << 8) | \
+ (tRCD << 4) | (tRC << 0))
+
+/*
+ * r0: control base, r1: ram bank base
+ * r3, r4: working
+ */
+setup_sdram_bank:
+ mov r3, #(1 << 1) /* SDRAM controller reset */
+ str r3, [r0, #ESDCTL_ESDMISC]
+1:
+ ldr r3, [r0, #ESDCTL_ESDMISC]
+ tst r3, #(1 << 31)
+ beq 1b
+
+ ldr r3, ESDCTL_CONFIG
+ cmp r1, #RAM_BANK1_BASE
+ movhs r2, #0xc // bank 1 ESDCFG offset
+ movlo r2, #0x4 // bank 0 ESDCFG offset
+ str r3, [r0, r2]
+ sub r2, r2, #4 // adjust to ESDCTL offset
+
+ ldr r3, ESDCTL_CMD_PRECHARGE
+ str r3, [r0, r2]
+ str r3, [r1, #(1 << 10)] // precharge all command
+
+ ldr r3, ESDCTL_CMD_AUTOREFR
+ str r3, [r0, r2]
+ .rept 2
+ ldrb r3, [r1] // perform auto refresh cycles
+ .endr
+
+ ldr r3, ESDCTL_CMD_MODEREG
+ str r3, [r0, r2]
+ strb r3, [r1, #((tCAS << 4) | (FP << 2) | 0x03)] // load mode reg via A0..A11
+
+ ldr r3, ESDCTL_CMD_NORMAL
+ str r3, [r0, r2]
+
+ mov pc, lr
+
+#define PLATFORM_VECTORS _platform_vectors
+ .macro _platform_vectors
+ .endm
+
+//Internal Boot, from MMC/SD cards or NAND flash
+#ifdef INTERNAL_BOOT_MODE
+#define DCDGEN(type, addr, data) \
+ .long type ;\
+ .long addr ;\
+ .long data
+
+#define FHEADER_OFFSET 0x400
+
+#ifdef RAM_BANK1_SIZE
+#define PHYS_ADDR(a) ((a) - RAM_BANK0_BASE - RAM_BANK0_SIZE + RAM_BANK1_BASE)
+#else
+#define PHYS_ADDR(a) (a)
+#endif
+
+ .macro setup_flash_header
+ b reset_vector
+#if defined(FHEADER_OFFSET)
+ .org FHEADER_OFFSET
+#endif
+app_code_jump_v: .long PHYS_ADDR(reset_vector)
+app_code_barker: .long 0xB1
+app_code_csf: .long 0
+hwcfg_ptr_ptr: .long PHYS_ADDR(hwcfg_ptr)
+super_root_key: .long 0
+hwcfg_ptr: .long PHYS_ADDR(dcd_data)
+#ifdef RAM_BANK1_SIZE
+app_dest_ptr: .long RAM_BANK1_BASE + RAM_BANK1_SIZE - REDBOOT_OFFSET
+#else
+app_dest_ptr: .long RAM_BANK0_BASE + RAM_BANK0_SIZE - REDBOOT_OFFSET
+#endif
+dcd_data: .long 0xB17219E9
+ .long (dcd_end - .)
+
+// real dcd data table
+// SDRAM
+DCDGEN(4, 0xB8001010, 0x00000000) // disable mDDR
+DCDGEN(4, 0xB8001000, 0x92100000) // precharge command
+DCDGEN(1, 0x80000400, 0x00000000) // precharge all dummy write
+DCDGEN(4, 0xB8001000, 0xA2100000) // auto-refresh command
+DCDGEN(4, 0x80000000, 0x00000000) // dummy write for refresh
+DCDGEN(4, 0x80000000, 0x00000000) // dummy write for refresh
+DCDGEN(4, 0x80000000, 0x00000000) // dummy write for refresh
+DCDGEN(4, 0x80000000, 0x00000000) // dummy write for refresh
+DCDGEN(4, 0x80000000, 0x00000000) // dummy write for refresh
+DCDGEN(4, 0x80000000, 0x00000000) // dummy write for refresh
+DCDGEN(4, 0x80000000, 0x00000000) // dummy write for refresh
+DCDGEN(4, 0x80000000, 0x00000000) // dummy write for refresh
+DCDGEN(4, 0xB8001000, 0xB2100000) // Load Mode Register command - cas=3 bl=8
+DCDGEN(1, 0x80000033, 0x00) // dummy write -- address has the mode bits
+//
+// For DDR clock speed max = 133 MHz, HYB18M1G320BF-7.5 memory
+// based on data sheet HYx18M1G16x_BF_rev100.pdf.
+//
+// ESDCTL0=0x82216880:
+// SDE=1 ESDRAM Controller Enable: Enabled
+// SMODE=000 SDRAM Controller Operating Mode: Normal Read/Write
+// SP=0 Supervisor Protect: User mode accesses allowed
+// ROW=010 Row Address Width: 13 Row Addresses
+// COL=10 Column Address Width: 10 Column Addresses
+// DSIZ=01 SDRAM Memory Data Width: 16-bit memory width aligned to D[15:0]
+// SREFR=011 SDRAM Refresh Rate: 4 rows each refresh clock,
+// 8192 rows/64 mS @ 32 kHz
+// 7.81 uS row rate at 32 kHz
+// PWDT=10 Power Down Timer: 64 clocks (HCLK) after completion of last access
+// with Active Power Down (most aggressive)
+// FP=0 Full Page: Not Full Page
+// BL=1 Burst Length: 8
+// PRCT=000000 Precharge Timer: Disabled
+//
+DCDGEN(4, 0xB8001000, ESDCTLVAL)
+//
+// ESDCFG0=0x00295728:
+// tXP=01 LPDDR exit power down to next valid command delay: 2 clocks
+// tWTR=0 LPDDR WRITE to READ Command Delay: 1 clock
+// tRP=10 SDRAM Row Precharge Delay: 3 clocks
+// tMRD=01 SDRAM Load Mode Register to ACTIVE Command: 2 clocks
+// tWR=0 SDRAM WRITE to PRECHARGE Command: 2 clocks
+// tRAS=101 SDRAM ACTIVE to PRECHARGE Command: 6 clocks
+// tRRD=01 ACTIVE Bank A to ACTIVE Bank B Command: 2 clocks
+// tCAS=11 SDRAM CAS Latency: 3 clocks
+// tRCD=010 SDRAM Row to Column Delay: 3 clocks
+// tRC=1000 SDRAM Row Cycle Delay: 9 clocks
+//
+DCDGEN(4, 0xB8001004, ESDCFGVAL)
+
+// CLK
+DCDGEN(4, 0x53F80008, 0x20034000) // CLKCTL ARM=400 AHB=133
+dcd_end:
+
+//CARD_FLASH_CFG_PARMS_T---length
+card_cfg:
+ .long REDBOOT_IMAGE_SIZE
+ .endm
+#endif
+
+SDRAM_ADDR_MASK: .word 0xFFFC0000
+#ifdef RAM_BANK1_SIZE
+MXC_REDBOOT_RAM_START: .word RAM_BANK1_BASE + RAM_BANK1_SIZE - REDBOOT_OFFSET
+#else
+MXC_REDBOOT_RAM_START: .word RAM_BANK0_BASE + RAM_BANK0_SIZE - REDBOOT_OFFSET
+#endif
+AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
+AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
+AIPS1_PARAM_W: .word 0x77777777
+MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
+MAX_PARAM1: .word 0x00043210
+ESDCTL_BASE_W: .word ESDCTL_BASE_ADDR
+M3IF_BASE_W: .word M3IF_BASE
+ESDCTL_CMD_NORMAL: .word ESDCTLVAL | ESDCTL_NORMAL
+ESDCTL_CMD_AUTOREFR: .word ESDCTLVAL | ESDCTL_AREF
+ESDCTL_CMD_PRECHARGE: .word ESDCTLVAL | ESDCTL_PCHG
+ESDCTL_CMD_MODEREG: .word ESDCTLVAL | ESDCTL_LMOD
+ESDCTL_CONFIG: .word ESDCFGVAL
+IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
+GPIO2_BASE_ADDR_W: .word GPIO2_BASE_ADDR
+#ifdef USE_SERIAL
+UART1_BASE_ADDR_W: .word UART1_BASE_ADDR
+UART1_UBIR_W: .word 0x0f
+UART1_UBMR_W: .word 0x2e
+#endif
+CCM_CGR0_W: .word 0x1FFFFFFF
+CCM_CGR1_W: .word 0xFFFFFFFF
+CCM_CGR2_W: .word 0x000FDFFF
+CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
+CCM_CCTL_VAL_W: .word 0x30030000
+/*-----------------------------------------------------------------------*/
+/* end of hal_platform_setup.h */
+#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
--- /dev/null
+#ifndef CYGONCE_KARO_TX25_H
+#define CYGONCE_KARO_TX25_H
+
+//=============================================================================
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+#define SZ_1K 0x00000400
+#define SZ_2K 0x00000800
+#define SZ_4K 0x00001000
+#define SZ_8K 0x00002000
+#define SZ_16K 0x00004000
+#define SZ_32K 0x00008000
+#define SZ_64K 0x00010000
+#define SZ_128K 0x00020000
+#define SZ_256K 0x00040000
+#define SZ_512K 0x00080000
+#define SZ_1M 0x00100000
+#define SZ_2M 0x00200000
+#define SZ_4M 0x00400000
+#define SZ_8M 0x00800000
+#define SZ_16M 0x01000000
+#define SZ_32M 0x02000000
+#define SZ_64M 0x04000000
+#define SZ_128M 0x08000000
+#define SZ_256M 0x10000000
+#define SZ_512M 0x20000000
+#define SZ_1G 0x40000000
+
+#define RAM_BANK0_BASE CSD0_BASE_ADDR
+#define RAM_BANK1_BASE CSD1_BASE_ADDR
+#if SDRAM_SIZE > SZ_32M
+#define RAM_BANK0_SIZE (SDRAM_SIZE / 2)
+#define RAM_BANK1_SIZE (SDRAM_SIZE / 2)
+#else
+#define RAM_BANK0_SIZE SDRAM_SIZE
+#endif
+#define TX25_SDRAM_SIZE SDRAM_SIZE
+
+#define TX25_LED_MASK (1 << 7)
+#define TX25_LED_REG_ADDR (GPIO2_BASE_ADDR + GPIO_DR)
+
+#define LED_MAX_NUM 1
+
+#define LED_IS_ON(n) ({ \
+ CYG_WORD32 __val; \
+ HAL_READ_UINT32(TX25_LED_REG_ADDR, __val); \
+ __val & TX25_LED_MASK; \
+})
+
+#define TURN_LED_ON(n) \
+ CYG_MACRO_START \
+ CYG_WORD32 __val; \
+ HAL_READ_UINT32(TX25_LED_REG_ADDR, __val); \
+ __val |= TX25_LED_MASK; \
+ HAL_WRITE_UINT32(TX25_LED_REG_ADDR, __val); \
+ CYG_MACRO_END
+
+#define TURN_LED_OFF(n) \
+ CYG_MACRO_START \
+ CYG_WORD32 __val; \
+ HAL_READ_UINT32(TX25_LED_REG_ADDR, __val); \
+ __val &= ~TX25_LED_MASK; \
+ HAL_WRITE_UINT32(TX25_LED_REG_ADDR, __val); \
+ CYG_MACRO_END
+
+#define BOARD_DEBUG_LED(n) \
+ CYG_MACRO_START \
+ if (n >= 0 && n < LED_MAX_NUM) { \
+ if (LED_IS_ON(n)) \
+ TURN_LED_OFF(n); \
+ else \
+ TURN_LED_ON(n); \
+ } \
+ CYG_MACRO_END
+
+#define BLINK_LED(l, n) \
+ CYG_MACRO_START \
+ int _i; \
+ for (_i = 0; _i < (n); _i++) { \
+ BOARD_DEBUG_LED(l); \
+ HAL_DELAY_US(200000); \
+ BOARD_DEBUG_LED(l); \
+ HAL_DELAY_US(300000); \
+ } \
+ HAL_DELAY_US(1000000); \
+ CYG_MACRO_END
+
+#if !defined(__ASSEMBLER__)
+enum {
+ BOARD_TYPE_TX25KARO,
+};
+
+#define gpio_tst_bit(grp, gpio) _gpio_tst_bit(grp, gpio, __FUNCTION__, __LINE__)
+static inline int _gpio_tst_bit(int grp, int gpio, const char *func, int line)
+{
+ unsigned long val;
+ CYG_ADDRESS reg;
+
+ switch (grp) {
+ case 1:
+ reg = GPIO1_BASE_ADDR;
+ break;
+ case 2:
+ reg = GPIO2_BASE_ADDR;
+ break;
+ case 3:
+ reg = GPIO3_BASE_ADDR;
+ break;
+ case 4:
+ reg = GPIO4_BASE_ADDR;
+ break;
+ default:
+ return 0;
+ }
+
+ if (gpio < 0 || gpio > 31) {
+ return 0;
+ }
+ val = readl(reg + GPIO_PSR0);
+ return !!(val & (1 << gpio));
+}
+
+static inline void gpio_set_bit(int grp, int gpio)
+{
+ unsigned long val;
+ CYG_ADDRESS reg;
+
+ switch (grp) {
+ case 1:
+ reg = GPIO1_BASE_ADDR;
+ break;
+ case 2:
+ reg = GPIO2_BASE_ADDR;
+ break;
+ case 3:
+ reg = GPIO3_BASE_ADDR;
+ break;
+ case 4:
+ reg = GPIO4_BASE_ADDR;
+ break;
+ default:
+ return;
+ }
+
+ if (gpio < 0 || gpio > 31) {
+ return;
+ }
+ val = readl(reg + GPIO_DR);
+ writel(val | (1 << gpio), reg + GPIO_DR);
+}
+
+static inline void gpio_clr_bit(int grp, int gpio)
+{
+ unsigned long val;
+ CYG_ADDRESS reg;
+
+ switch (grp) {
+ case 1:
+ reg = GPIO1_BASE_ADDR;
+ break;
+ case 2:
+ reg = GPIO2_BASE_ADDR;
+ break;
+ case 3:
+ reg = GPIO3_BASE_ADDR;
+ break;
+ case 4:
+ reg = GPIO4_BASE_ADDR;
+ break;
+ default:
+ return;
+ }
+
+ if (gpio < 0 || gpio > 31) {
+ return;
+ }
+ val = readl(reg + GPIO_DR);
+ writel(val & ~(1 << gpio), reg + GPIO_DR);
+}
+#endif
+
+#endif /* CYGONCE_KARO_TX25_H */
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+//#define REDBOOT_BOTTOM
+
+// This is a generated file - do not edit
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_VARIANT_H
+#include CYGBLD_HAL_PLATFORM_H
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+
+#define SDRAM_BASE_ADDR CSD0_BASE_ADDR
+#define SDRAM_SIZE CYGNUM_HAL_ARM_TX25_SDRAM_SIZE
+
+#define REDBOOT_IMAGE_SIZE 0x00040000
+
+#ifndef REDBOOT_BOTTOM
+#define REDBOOT_OFFSET REDBOOT_IMAGE_SIZE
+#define CYGMEM_REGION_ram SDRAM_BASE_ADDR
+#define CYGMEM_REGION_rom (CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE)
+#else
+#define REDBOOT_OFFSET 0x00100000
+#define CYGMEM_REGION_ram (SDRAM_BASE_ADDR + REDBOOT_OFFSET)
+#define CYGMEM_REGION_rom SDRAM_BASE_ADDR
+#endif
+
+#define CYGMEM_REGION_ram_SIZE (SDRAM_SIZE - REDBOOT_OFFSET)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_rom_SIZE REDBOOT_OFFSET
+#define CYGMEM_REGION_rom_ATTR CYGMEM_REGION_ATTR_R
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME(__heap1)[];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME(__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_rom - (size_t)CYG_LABEL_NAME(__heap1))
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+#define __ASSEMBLER__
+#include CYGHWR_MEMORY_LAYOUT_H
+
+MEMORY
+{
+ ram : ORIGIN = CYGMEM_REGION_ram, LENGTH = CYGMEM_REGION_ram_SIZE
+ rom : ORIGIN = CYGMEM_REGION_rom, LENGTH = CYGMEM_REGION_rom_SIZE
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_rom_vectors (rom, CYGMEM_REGION_rom, LMA_EQ_VMA)
+ SECTION_RELOCS(rom, ALIGN (0x1), LMA_EQ_VMA)
+ SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixed_vectors (ram, CYGMEM_REGION_ram + 0x20, LMA_EQ_VMA)
+ SECTION_data (ram, CYGMEM_REGION_ram + 0x8000, FOLLOWING (.gcc_except_table))
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
--- /dev/null
+#ifndef CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+#define CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+
+//=============================================================================
+//
+// plf_io.h
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/hal/karo_tx25.h>
+#include <cyg/hal/hal_soc.h>
+#include <redboot.h>
+
+#ifdef RAM_BANK1_SIZE
+#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \
+ CYG_MACRO_START \
+ { \
+ extern unsigned int system_rev; \
+ /* Next ATAG_MEM. */ \
+ _p_->hdr.size = (sizeof(struct tag_mem32) + \
+ sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_MEM; \
+ /* Round up so there's only one bit set in the memory size. \
+ * Don't double it if it's already a power of two, though. \
+ */ \
+ _p_->u.mem.size = 1<<hal_msbindex(RAM_BANK0_SIZE); \
+ if (_p_->u.mem.size < RAM_BANK0_SIZE) \
+ _p_->u.mem.size <<= 1; \
+ _p_->u.mem.start = RAM_BANK0_BASE; \
+ \
+ _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size); \
+ \
+ /* Next ATAG_MEM. */ \
+ _p_->hdr.size = (sizeof(struct tag_mem32) + \
+ sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_MEM; \
+ /* Round up so there's only one bit set in the memory size. \
+ * Don't double it if it's already a power of two, though. \
+ */ \
+ _p_->u.mem.size = 1<<hal_msbindex(RAM_BANK1_SIZE); \
+ if (_p_->u.mem.size < RAM_BANK1_SIZE) \
+ _p_->u.mem.size <<= 1; \
+ _p_->u.mem.start = RAM_BANK1_BASE; \
+ \
+ _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size); \
+ \
+ _p_->hdr.size = ((sizeof(struct tag_revision)) + \
+ sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_REVISION; \
+ _p_->u.revision.rev = system_rev; \
+ } \
+ CYG_MACRO_END
+#else
+#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \
+ CYG_MACRO_START \
+ { \
+ extern unsigned int system_rev; \
+ /* Next ATAG_MEM. */ \
+ _p_->hdr.size = (sizeof(struct tag_mem32) + \
+ sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_MEM; \
+ /* Round up so there's only one bit set in the memory size. \
+ * Don't double it if it's already a power of two, though. \
+ */ \
+ _p_->u.mem.size = 1<<hal_msbindex(RAM_BANK0_SIZE); \
+ if (_p_->u.mem.size < RAM_BANK0_SIZE) \
+ _p_->u.mem.size <<= 1; \
+ _p_->u.mem.start = RAM_BANK0_BASE; \
+ \
+ _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size); \
+ \
+ _p_->hdr.size = ((sizeof(struct tag_revision)) + \
+ sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_REVISION; \
+ _p_->u.revision.rev = system_rev; \
+ } \
+ CYG_MACRO_END
+#endif
+
+#endif // CYGONCE_HAL_ARM_BOARD_PLF_IO_H
--- /dev/null
+#ifndef CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+#define CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+//=============================================================================
+//
+// plf_mmap.h
+//
+// Platform specific memory map support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_misc.h>
+
+// Get the pagesize for a particular virtual address:
+
+// This does not depend on the vaddr.
+#define HAL_MM_PAGESIZE(vaddr, pagesize) CYG_MACRO_START \
+ (pagesize) = SZ_1M; \
+CYG_MACRO_END
+
+// Get the physical address from a virtual address:
+
+#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START \
+ cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
+ if ( _v_ < 128 * SZ_1M ) /* SDRAM */ \
+ _v_ += SDRAM_BASE_ADDR; \
+ else /* Rest of it */ \
+ /* no change */ ; \
+ (paddr) = _v_; \
+CYG_MACRO_END
+
+/*
+ * translate the virtual address of ram space to physical address
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
+{
+ if(virt < 0x08000000) {
+ return virt|0x80000000;
+ }
+ if((virt & 0xF0000000) == 0x80000000) {
+ return virt&(~0x08000000);
+ }
+ return virt;
+}
+
+/*
+ * remap the physical address of ram space to uncacheable virtual address space
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
+{
+ /* 0x88000000~0x87FFFFFF is uncacheable meory space which is mapped to SDRAM*/
+ if((phy & 0xF0000000) == 0x80000000) {
+ phy |= 0x08000000;
+ }
+ return phy;
+}
+
+//---------------------------------------------------------------------------
+#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
--- /dev/null
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "RedBoot configuration for Ka-Ro TX25 processor module" ;
+
+ # These fields should not be modified.
+ hardware tx25karo ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM current ;
+ package -hardware CYGPKG_HAL_ARM_MX25 current ;
+ package -hardware CYGPKG_HAL_ARM_TX25KARO current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_TX25 current ;
+ package -hardware CYGPKG_DEVS_ETH_FEC current ;
+ package -hardware CYGPKG_COMPRESS_ZLIB current ;
+ package -hardware CYGPKG_IO_FLASH current ;
+ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+ package -template CYGPKG_MEMALLOC current ;
+ package -template CYGPKG_DEVS_ETH_PHY current ;
+ package -template CYGPKG_LIBC_I18N current ;
+ package -template CYGPKG_LIBC_STDLIB current ;
+ package -template CYGPKG_ERROR current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_ETH_PHY_LAN8700 {
+ inferred_value 1
+};
+
+cdl_option CYGIMP_LIBC_RAND_SIMPLE1 {
+ user_value 0
+};
+
+cdl_option CYGIMP_LIBC_RAND_KNUTH1 {
+ user_value 1
+};
+
+cdl_option CYGFUN_LIBC_STDLIB_CONV_LONGLONG {
+ user_value 0
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 0
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ inferred_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_GDB {
+ inferred_value 0
+};
+
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+ inferred_value 1 "Ka-Ro [exec date -I]"
+};
+
+cdl_option CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+ inferred_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_WINCE_SUPPORT {
+ user_value 1
+};
+
+cdl_option CYGSEM_REDBOOT_NET_HTTP_DOWNLOAD {
+ user_value 0
+};
+
+cdl_option CYGPKG_REDBOOT_ANY_CONSOLE {
+ inferred_value 0
+};
+
+cdl_option CYGSEM_REDBOOT_PLF_ESA_VALIDATE {
+ inferred_value 1
+};
+
+cdl_option CYGPKG_REDBOOT_MAX_CMD_LINE {
+ inferred_value 1024
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ inferred_value 0x00040000
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_SCRIPT_SIZE {
+ inferred_value 2048
+};
+
+cdl_component CYGPKG_REDBOOT_DISK {
+ user_value 0
+};
+
+cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_TIMEOUT_RESOLUTION {
+ inferred_value 10
+};
+
+cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_DEFAULT_TIMEOUT {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+ inferred_value 0x80108000
+};
+
+cdl_option CYGBLD_ISO_CTYPE_HEADER {
+ inferred_value 1 <cyg/libc/i18n/ctype.inl>
+};
+
+cdl_option CYGBLD_ISO_ERRNO_CODES_HEADER {
+ inferred_value 1 <cyg/error/codes.h>
+};
+
+cdl_option CYGBLD_ISO_ERRNO_HEADER {
+ inferred_value 1 <cyg/error/errno.h>
+};
+
+cdl_option CYGBLD_ISO_STDLIB_STRCONV_HEADER {
+ inferred_value 1 <cyg/libc/stdlib/atox.inl>
+};
+
+cdl_option CYGBLD_ISO_STDLIB_ABS_HEADER {
+ inferred_value 1 <cyg/libc/stdlib/abs.inl>
+};
+
+cdl_option CYGBLD_ISO_STDLIB_DIV_HEADER {
+ inferred_value 1 <cyg/libc/stdlib/div.inl>
+};
+
+cdl_option CYGBLD_ISO_STRERROR_HEADER {
+ inferred_value 1 <cyg/error/strerror.h>
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGSEM_IO_FLASH_READ_INDIRECT {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_IO_FLASH_VERIFY_PROGRAM {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+ inferred_value 1
+};
+
+cdl_component CYGHWR_FLASH_NAND_BBT_HEADER {
+ inferred_value 1 <cyg/io/tx25_nand_bbt.h>
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_MULTI {
+ inferred_value 0
+};
+
+cdl_option CYGSEM_ERROR_PER_THREAD_ERRNO {
+ inferred_value 0
+};
+
--- /dev/null
+//==========================================================================
+//
+// redboot_cmds.c
+//
+// Board [platform] specific RedBoot commands
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+#include <redboot.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/plf_mmap.h>
+#include <cyg/hal/karo_tx25.h> // Platform specific hardware definitions
+
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <flash_config.h>
+
+#if (REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE)
+#error REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE
+#endif
+
+#endif //CYGSEM_REDBOOT_FLASH_CONFIG
+
+#ifdef CYGPKG_IO_FLASH
+#include <cyg/io/flash.h>
+#endif
+char HAL_PLATFORM_EXTRA[55] = "PASS x.x [x16 SDRAM]";
+
+static void runImg(int argc, char *argv[]);
+static void do_mem(int argc, char *argv[]);
+
+RedBoot_cmd("mem",
+ "Set a memory location",
+ "[-h|-b] [-n] [-a <address>] <data>",
+ do_mem
+ );
+
+RedBoot_cmd("run",
+ "Run an image at a location with MMU off",
+ "[<virtual addr>]",
+ runImg
+ );
+
+static void do_mem(int argc, char *argv[])
+{
+ struct option_info opts[4];
+ bool mem_half_word, mem_byte;
+ bool no_verify;
+ bool addr_set;
+ unsigned long address;
+ unsigned int value;
+ int ret;
+ init_opts(&opts[0], 'b', false, OPTION_ARG_TYPE_FLG,
+ &mem_byte, NULL, "write a byte");
+ init_opts(&opts[1], 'h', false, OPTION_ARG_TYPE_FLG,
+ &mem_half_word, NULL, "write a half-word");
+ init_opts(&opts[2], 'a', true, OPTION_ARG_TYPE_NUM,
+ &address, &addr_set, "address to write to");
+ init_opts(&opts[3], 'n', false, OPTION_ARG_TYPE_FLG,
+ &no_verify, NULL, "noverify");
+
+ ret = scan_opts(argc, argv, 1, opts, sizeof(opts) / sizeof(opts[0]),
+ &value, OPTION_ARG_TYPE_NUM, "value to be written");
+ if (ret == 0) {
+ return;
+ }
+ if (!addr_set) {
+ diag_printf("** Error: '-a <address>' must be specified\n");
+ return;
+ }
+ if (ret == argc + 1) {
+ diag_printf("** Error: non-option argument '<value>' must be specified\n");
+ return;
+ }
+ if (mem_byte && mem_half_word) {
+ diag_printf("** Error: Should not specify both byte and half-word access\n");
+ } else if (mem_byte) {
+ value &= 0xff;
+ *(volatile cyg_uint8*)address = (cyg_uint8)value;
+ if (no_verify) {
+ diag_printf(" Set 0x%08lX to 0x%02X\n", address, value);
+ } else {
+ diag_printf(" Set 0x%08lX to 0x%02X (result 0x%02X)\n",
+ address, value, (int)*(cyg_uint8*)address );
+ }
+ } else if (mem_half_word) {
+ if (address & 1) {
+ diag_printf("** Error: address for half-word access must be half-word aligned\n");
+ } else {
+ value &= 0xffff;
+ *(volatile cyg_uint16*)address = (cyg_uint16)value;
+ if (no_verify) {
+ diag_printf(" Set 0x%08lX to 0x%04X\n", address, value);
+ } else {
+ diag_printf(" Set 0x%08lX to 0x%04X (result 0x%04X)\n",
+ address, value, (int)*(cyg_uint16*)address);
+ }
+ }
+ } else {
+ if (address & 3) {
+ diag_printf("** Error: address for word access must be word aligned\n");
+ } else {
+ *(volatile cyg_uint32*)address = (cyg_uint32)value;
+ if (no_verify) {
+ diag_printf(" Set 0x%08lX to 0x%08X\n", address, value);
+ } else {
+ diag_printf(" Set 0x%08lX to 0x%08X (result 0x%08X)\n",
+ address, value, (int)*(cyg_uint32*)address);
+ }
+ }
+ }
+}
+
+void launchRunImg(unsigned long addr)
+{
+ asm volatile ("mov r12, r0;");
+ HAL_MMU_OFF();
+ asm volatile (
+ "mov r0, #0;"
+ "mov r1, r12;"
+ "mov r11, #0;"
+ "mov r12, #0;"
+ "mrs r10, cpsr;"
+ "bic r10, r10, #0xF0000000;"
+ "msr cpsr_f, r10;"
+ "mov pc, r1"
+ );
+}
+
+static void runImg(int argc,char *argv[])
+{
+ unsigned int virt_addr, phys_addr;
+
+ // Default physical entry point for Symbian
+ if (entry_address == 0xFFFFFFFF)
+ virt_addr = 0x800000;
+ else
+ virt_addr = entry_address;
+
+ if (!scan_opts(argc, argv, 1, 0, 0, &virt_addr,
+ OPTION_ARG_TYPE_NUM, "virtual address"))
+ return;
+
+ if (entry_address != 0xFFFFFFFF)
+ diag_printf("load entry_address=0x%lx\n", entry_address);
+ HAL_VIRT_TO_PHYS_ADDRESS(virt_addr, phys_addr);
+
+ diag_printf("virt_addr=0x%x\n",virt_addr);
+ diag_printf("phys_addr=0x%x\n",phys_addr);
+
+ launchRunImg(phys_addr);
+}
+
+#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYG_HAL_STARTUP_ROMRAM)
+
+RedBoot_cmd("romupdate",
+ "Update Redboot with currently running image",
+ "",
+ romupdate
+ );
+
+#ifdef CYGPKG_IO_FLASH
+void romupdate(int argc, char *argv[])
+{
+ void *err_addr, *base_addr;
+ int stat;
+
+ base_addr = (void*)(MXC_NAND_BASE_DUMMY + CYGBLD_REDBOOT_FLASH_BOOT_OFFSET);
+ diag_printf("Updating RedBoot in NAND flash\n");
+
+ // Erase area to be programmed
+ if ((stat = flash_erase(base_addr, CYGBLD_REDBOOT_MIN_IMAGE_SIZE, &err_addr)) != 0) {
+ diag_printf("Can't erase region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ return;
+ }
+ // Now program it
+ if ((stat = flash_program(base_addr, ram_end,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE, &err_addr)) != 0) {
+ diag_printf("Can't program region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ }
+}
+#endif //CYGPKG_IO_FLASH
+#endif /* CYG_HAL_STARTUP_ROMRAM */
--- /dev/null
+/*=============================================================================
+//
+// board_diag.c
+//
+// HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_arch.h> // basic machine info
+#include <cyg/hal/hal_intr.h> // interrupt macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_if.h> // Calling-if API
+#include <cyg/hal/drv_api.h> // driver API
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/karo_tx25.h> // Platform specifics
+
+extern void cyg_hal_plf_serial_init(void);
+
+void cyg_hal_plf_comms_init(void)
+{
+ static int initialized = 0;
+
+ if (initialized) {
+ return;
+ }
+ initialized = 1;
+ cyg_hal_plf_serial_init();
+}
+
+//-----------------------------------------------------------------------------
+// Based on 3.6864 MHz xtal
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x18
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x0C
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x06
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x04
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x02
+#endif
+
+#ifndef CYG_DEV_SERIAL_BAUD_MSB
+#error Missing/incorrect serial baud rate defined - CDL error?
+#endif
+
+//-----------------------------------------------------------------------------
+// Define the serial registers. The board is equipped with a 16552
+// serial chip.
+
+#if defined (EXT_UART_x16)
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT16
+#define HAL_READ_UINT_UART HAL_READ_UINT16
+typedef cyg_uint16 uart_width;
+#elif defined (EXT_UART_x32)
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT32
+#define HAL_READ_UINT_UART HAL_READ_UINT32
+typedef cyg_uint32 uart_width;
+#else //_x8
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT8
+#define HAL_READ_UINT_UART HAL_READ_UINT8
+typedef cyg_uint8 uart_width;
+#endif
+
+#define CYG_DEV_SERIAL_RHR 0x00 // receiver buffer register, read, dlab = 0
+#define CYG_DEV_SERIAL_THR 0x00 // transmitter holding register, write, dlab = 0
+#define CYG_DEV_SERIAL_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IER 0x01 // interrupt enable register, read/write, dlab = 0
+#define CYG_DEV_SERIAL_DLM 0x01 // divisor latch (MS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IIR 0x02 // interrupt identification register, read, dlab = 0
+#define CYG_DEV_SERIAL_FCR 0x02 // fifo control register, write, dlab = 0
+#define CYG_DEV_SERIAL_AFR 0x02 // alternate function register, read/write, dlab = 1
+#define CYG_DEV_SERIAL_LCR 0x03 // line control register, read/write
+#define CYG_DEV_SERIAL_MCR 0x04
+#define CYG_DEV_SERIAL_MCR_A 0x04
+#define CYG_DEV_SERIAL_MCR_B 0x04
+#define CYG_DEV_SERIAL_LSR 0x05 // line status register, read
+#define CYG_DEV_SERIAL_MSR 0x06 // modem status register, read
+#define CYG_DEV_SERIAL_SCR 0x07 // scratch pad register
+
+// The interrupt enable register bits.
+#define SIO_IER_ERDAI 0x01 // enable received data available irq
+#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
+#define SIO_IER_ELSI 0x04 // enable receiver line status irq
+#define SIO_IER_EMSI 0x08 // enable modem status interrupt
+
+// The interrupt identification register bits.
+#define SIO_IIR_IP 0x01 // 0 if interrupt pending
+#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
+#define ISR_Tx 0x02
+#define ISR_Rx 0x04
+
+// The line status register bits.
+#define SIO_LSR_DR 0x01 // data ready
+#define SIO_LSR_OE 0x02 // overrun error
+#define SIO_LSR_PE 0x04 // parity error
+#define SIO_LSR_FE 0x08 // framing error
+#define SIO_LSR_BI 0x10 // break interrupt
+#define SIO_LSR_THRE 0x20 // transmitter holding register empty
+#define SIO_LSR_TEMT 0x40 // transmitter register empty
+#define SIO_LSR_ERR 0x80 // any error condition
+
+// The modem status register bits.
+#define SIO_MSR_DCTS 0x01 // delta clear to send
+#define SIO_MSR_DDSR 0x02 // delta data set ready
+#define SIO_MSR_TERI 0x04 // trailing edge ring indicator
+#define SIO_MSR_DDCD 0x08 // delta data carrier detect
+#define SIO_MSR_CTS 0x10 // clear to send
+#define SIO_MSR_DSR 0x20 // data set ready
+#define SIO_MSR_RI 0x40 // ring indicator
+#define SIO_MSR_DCD 0x80 // data carrier detect
+
+// The line control register bits.
+#define SIO_LCR_WLS0 0x01 // word length select bit 0
+#define SIO_LCR_WLS1 0x02 // word length select bit 1
+#define SIO_LCR_STB 0x04 // number of stop bits
+#define SIO_LCR_PEN 0x08 // parity enable
+#define SIO_LCR_EPS 0x10 // even parity select
+#define SIO_LCR_SP 0x20 // stick parity
+#define SIO_LCR_SB 0x40 // set break
+#define SIO_LCR_DLAB 0x80 // divisor latch access bit
+
+// The FIFO control register
+#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
+#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
+#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
+
+//-----------------------------------------------------------------------------
+
+//#define x_debug_uart_log_buf
+#ifdef x_debug_uart_log_buf
+#define x_DIAG_BUFSIZE 2048
+static char __x_log_buf[x_DIAG_BUFSIZE];
+static int x_diag_bp = 0;
+#endif
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
+
+#ifdef __BASE
+
+#ifdef CYGSEM_HAL_ROM_MONITOR
+#define CYG_HAL_STARTUP_ROM
+#define CYG_HAL_STARTUP_ROMRAM
+#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#endif
+
+#if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define HAL_DIAG_USES_HARDWARE
+#elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
+#define HAL_DIAG_USES_HARDWARE
+#elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+#define HAL_DIAG_USES_HARDWARE
+#endif
+
+static channel_data_t channel = {
+ (uart_width*) _BASE, 0, 0
+};
+
+#ifdef HAL_DIAG_USES_HARDWARE
+
+void hal_diag_init(void)
+{
+ static int init = 0;
+ char *msg = "\n\rARM eCos\n\r";
+ uart_width lcr;
+
+ if (init++) return;
+
+ init_duart_channel(&channel);
+
+ while (*msg) hal_diag_write_char(*msg++);
+}
+
+#ifdef DEBUG_DIAG
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define DIAG_BUFSIZE 32
+#else
+#define DIAG_BUFSIZE 2048
+#endif
+static char diag_buffer[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+
+void hal_diag_write_char(char c)
+{
+ uart_width lsr;
+
+ hal_diag_init();
+
+ cyg_hal_plf_duart_putc(&channel, c)
+
+#ifdef DEBUG_DIAG
+ diag_buffer[diag_bp++] = c;
+ if (diag_bp == DIAG_BUFSIZE) {
+ while (1) ;
+ diag_bp = 0;
+ }
+#endif
+}
+
+void hal_diag_read_char(char *c)
+{
+ *c = cyg_hal_plf_duart_getc(&channel);
+}
+
+#else // HAL_DIAG relies on GDB
+
+// Initialize diag port - assume GDB channel is already set up
+void hal_diag_init(void)
+{
+ if (0) init_duart_channel(&channel); // avoid warning
+}
+
+// Actually send character down the wire
+static void hal_diag_write_char_serial(char c)
+{
+ cyg_hal_plf_duart_putc(&channel, c);
+}
+
+static bool hal_diag_read_serial(char *c)
+{
+ long timeout = 1000000000; // A long time...
+
+ while (!cyg_hal_plf_duart_getc_nonblock(&channel, c))
+ if (0 == --timeout) return false;
+
+ return true;
+}
+
+void hal_diag_read_char(char *c)
+{
+ while (!hal_diag_read_serial(c)) ;
+}
+
+void hal_diag_write_char(char c)
+{
+ static char line[100];
+ static int pos = 0;
+
+ // No need to send CRs
+ if (c == '\r') return;
+
+ line[pos++] = c;
+
+ if (c == '\n' || pos == sizeof(line)) {
+ CYG_INTERRUPT_STATE old;
+
+ // Disable interrupts. This prevents GDB trying to interrupt us
+ // while we are in the middle of sending a packet. The serial
+ // receive interrupt will be seen when we re-enable interrupts
+ // later.
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+#else
+ HAL_DISABLE_INTERRUPTS(old);
+#endif
+
+ while (1) {
+ static char hex[] = "0123456789ABCDEF";
+ cyg_uint8 csum = 0;
+ int i;
+ char c1;
+
+ hal_diag_write_char_serial('$');
+ hal_diag_write_char_serial('O');
+ csum += 'O';
+ for (i = 0; i < pos; i++) {
+ char ch = line[i];
+ char h = hex[(ch>>4)&0xF];
+ char l = hex[ch&0xF];
+ hal_diag_write_char_serial(h);
+ hal_diag_write_char_serial(l);
+ csum += h;
+ csum += l;
+ }
+ hal_diag_write_char_serial('#');
+ hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
+ hal_diag_write_char_serial(hex[csum&0xF]);
+
+ // Wait for the ACK character '+' from GDB here and handle
+ // receiving a ^C instead. This is the reason for this clause
+ // being a loop.
+ if (!hal_diag_read_serial(&c1))
+ continue; // No response - try sending packet again
+
+ if ( c1 == '+' )
+ break; // a good acknowledge
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
+ if ( c1 == 3 ) {
+ // Ctrl-C: breakpoint.
+ cyg_hal_gdb_interrupt (__builtin_return_address(0));
+ break;
+ }
+#endif
+ // otherwise, loop round again
+ }
+
+ pos = 0;
+
+ // And re-enable interrupts
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+#else
+ HAL_RESTORE_INTERRUPTS(old);
+#endif
+
+ }
+}
+#endif
+
+#endif // __BASE
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
--- /dev/null
+//==========================================================================
+//
+// tx25_misc.c
+//
+// HAL misc board support code for the tx25
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#include <stdlib.h>
+#include <redboot.h>
+#include <string.h>
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h> // Interrupt names
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/karo_tx25.h> // Platform specifics
+
+#include <cyg/infra/diag.h> // diag_printf
+
+// All the MM table layout is here:
+#include <cyg/hal/hal_mm.h>
+
+//#define EARLY_SERIAL_SETUP
+
+#ifdef EARLY_SERIAL_SETUP
+static void mxc_serial_setup(void);
+
+static void uart_putc(int c)
+{
+ while (readl(UART1_BASE_ADDR + 0xb4) & (1 << 4)) {
+ /* wait for !TX_FULL */
+ }
+ writel(c, UART1_BASE_ADDR + 0x40);
+}
+
+static void putcr(void)
+{
+ uart_putc('\r');
+ uart_putc('\n');
+}
+
+static void printhex(unsigned int x, int len)
+{
+ int i;
+
+ for (i = len - 1; i >= 0; i--) {
+ int c = (x >> (i * 4)) & 0xf;
+ if (c > 9) {
+ c += 'A' - 10;
+ } else {
+ c += '0';
+ }
+ uart_putc(c);
+ }
+}
+
+static void dump_reg(unsigned long addr)
+{
+ printhex(addr, 8);
+ uart_putc('=');
+ printhex(readl(addr), 8);
+ putcr();
+}
+#endif
+
+#define SD_SZ (RAM_BANK0_SIZE >> 20)
+#define SD_B0 0x800
+#define SD_B1 (0x800 + SD_SZ)
+#define SD_B2 (0x880 + SD_SZ)
+#ifdef RAM_BANK1_SIZE
+#define SD_HI (0x900 + ((RAM_BANK1_SIZE >> 20) - 1))
+#endif
+
+void hal_mmu_init(void)
+{
+ unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
+ unsigned long i;
+
+ /*
+ * Set the TTB register
+ */
+ asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(ttb_base));
+
+ /*
+ * Set the Domain Access Control Register
+ */
+ i = ARM_ACCESS_DACR_DEFAULT;
+ asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(i));
+
+ /*
+ * First clear all TT entries - ie Set them to Faulting
+ */
+ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+
+ /* Phys Virt Size Attributes Function */
+ /* Base Base MB cached? buffered? access permissions */
+ /* xxx00000 */
+ X_ARM_MMU_SECTION(0x000, 0xF00, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Boot Rom */
+ X_ARM_MMU_SECTION(0x43f, 0x43f, 0x3c1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Internal Registers */
+ X_ARM_MMU_SECTION(0x800, 0x000, SD_SZ, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0x800, 0x800, SD_SZ, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0x800, 0x880, SD_SZ, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+#ifdef RAM_BANK1_SIZE
+ X_ARM_MMU_SECTION(0x900, SD_SZ, SD_SZ, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0x900, SD_B1, SD_SZ, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0x900, SD_B2, SD_SZ, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ /* make sure the last MiB in the upper bank of SDRAM (where RedBoot resides)
+ * has a unity mapping (required when switching MMU on) */
+ X_ARM_MMU_SECTION(SD_HI, SD_HI, 0x001, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RO_RO); /* SDRAM bank1 identity mapping */
+#endif
+ X_ARM_MMU_SECTION(0xB20, 0xB20, 0x0E0, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ESDCTL, WEIM, M3IF, EMI, NFC, External I/O */
+#ifdef EARLY_SERIAL_SETUP
+ mxc_serial_setup();
+#endif
+}
+
+static inline void set_reg(unsigned long addr, CYG_WORD32 set, CYG_WORD32 clr)
+{
+ CYG_WORD32 val;
+ HAL_READ_UINT32(addr, val);
+ val = (val & ~clr) | set;
+ HAL_WRITE_UINT32(addr, val);
+}
+
+//
+// Platform specific initialization
+//
+static void fec_gpio_init(void)
+{
+ /* GPIOs to set up for TX25/Starterkit-5:
+ Function GPIO Dir act. FCT
+ Lvl
+ FEC_RESET PB30 OUT LOW GPIO
+ FEC_ENABLE PB27 OUT HIGH GPIO
+ OSCM26_ENABLE PB22 OUT HIGH GPIO
+ EXT_WAKEUP PB24 IN HIGH GPIO
+ FEC_TXEN PF23 OUT OUT AIN
+ FEC_TXCLK PD11 OUT IN AOUT
+ ...
+ */
+#define OCR_SHIFT(bit) (((bit) * 2) % 32)
+#define OCR_MASK(bit) (3 << (OCR_SHIFT(bit)))
+#define OCR_VAL(bit,val) (((val) << (OCR_SHIFT(bit))) & (OCR_MASK(bit)))
+#define GPR_SHIFT(bit) (bit)
+#define GPR_MASK(bit) (1 << (GPR_SHIFT(bit)))
+#define GPR_VAL(bit,val) (((val) << (GPR_SHIFT(bit))) & (GPR_MASK(bit)))
+#define ICONF_SHIFT(bit) (((bit) * 2) % 32)
+#define ICONF_MASK(bit) (3 << (ICONF_SHIFT(bit)))
+#define ICONF_VAL(bit,val) (((val) << (ICONF_SHIFT(bit))) & (ICONF_MASK(bit)))
+
+ /*
+ * make sure the ETH PHY strap pins are pulled to the right voltage
+ * before deasserting the PHY reset GPIO
+ */
+ unsigned long val;
+
+ /* FEC_TX_CLK */
+ writel(0, IOMUXC_BASE_ADDR + 0x01E8);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x03E0);
+
+ /* FEC_RX_DV */
+ writel(0, IOMUXC_BASE_ADDR + 0x01E4);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x03DC);
+
+ /* FEC_RDATA0 */
+ writel(0, IOMUXC_BASE_ADDR + 0x01DC);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x03D4);
+
+ /* FEC_TDATA0 */
+ writel(0, IOMUXC_BASE_ADDR + 0x01D0);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x03C8);
+
+ /* FEC_TX_EN */
+ writel(0, IOMUXC_BASE_ADDR + 0x01D8);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x03D0);
+
+ /* FEC_MDC */
+ writel(0, IOMUXC_BASE_ADDR + 0x01C8);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x03C0);
+
+ /* FEC_MDIO */
+ writel(0, IOMUXC_BASE_ADDR + 0x01CC);
+ writel(0x1F0, IOMUXC_BASE_ADDR + 0x03C4);
+
+ /* FEC_RDATA1 */
+ writel(0, IOMUXC_BASE_ADDR + 0x01E0);
+ writel(0x1C0, IOMUXC_BASE_ADDR + 0x03D8);
+
+ /* FEC_TDATA1 */
+ writel(0, IOMUXC_BASE_ADDR + 0x01D4);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x03CC);
+
+ /*
+ * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins.
+ * Assert FEC_RESET_B, then power up the PHY by asserting
+ * FEC_ENABLE, at the same time lifting FEC_RESET_B.
+ *
+ * FEC_RESET_B: gpio4[7] is ALT 5 mode of pin D13
+ * FEC_ENABLE_B: gpio4[9] is ALT 5 mode of pin D11
+ */
+ writel(0x15, IOMUXC_BASE_ADDR + 0x0090);
+ writel(0x15, IOMUXC_BASE_ADDR + 0x0098);
+
+ writel(0x8, IOMUXC_BASE_ADDR + 0x0288); // open drain
+ writel(0x0, IOMUXC_BASE_ADDR + 0x0290); // cmos, no pu/pd
+
+ /* drop PHY power and assert reset (low) */
+ val = readl(GPIO4_BASE_ADDR + GPIO_DR) & ~((1 << 7) | (1 << 9));
+ writel(val, GPIO4_BASE_ADDR + GPIO_DR);
+
+ /* make the pins output */
+ val = readl(GPIO4_BASE_ADDR + GPIO_GDIR) | (1 << 7) | (1 << 9);
+ writel(val, GPIO4_BASE_ADDR + GPIO_GDIR);
+}
+
+//
+// Platform specific initialization
+//
+
+unsigned int g_clock_src;
+unsigned int g_board_type = BOARD_TYPE_TX25KARO;
+
+static void mxc_serial_setup(void)
+{
+ // UART1
+ /*RXD1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x170);
+ writel(0x1E0, IOMUXC_BASE_ADDR + 0x368);
+
+ /*TXD1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x174);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x36c);
+
+ /*RTS1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x178);
+ writel(0x1E0, IOMUXC_BASE_ADDR + 0x370);
+
+ /*CTS1*/
+ writel(0, IOMUXC_BASE_ADDR + 0x17c);
+ writel(0x40, IOMUXC_BASE_ADDR + 0x374);
+}
+
+void plf_hardware_init(void)
+{
+ g_clock_src = FREQ_24MHZ;
+ mxc_serial_setup();
+ fec_gpio_init();
+}
+
+#define SOC_FBAC0_REG IIM_BASE_ADDR
+#define SOC_MAC_ADDR_LOCK_BIT 2
+
+extern int fuse_blow(int bank, int row, int bit);
+
+int tx25_mac_addr_program(unsigned char mac_addr[ETHER_ADDR_LEN])
+{
+ int ret = 0;
+ int i;
+
+ for (i = 0; i < ETHER_ADDR_LEN; i++) {
+ unsigned char fuse = readl(SOC_MAC_ADDR_BASE + (i << 2));
+
+ if ((fuse | mac_addr[i]) != mac_addr[i]) {
+ diag_printf("MAC address fuse cannot be programmed: fuse[%d]=0x%02x -> 0x%02x\n",
+ i, fuse, mac_addr[i]);
+ return -1;
+ }
+ if (fuse != mac_addr[i]) {
+ ret = 1;
+ }
+ }
+ if (ret == 0) {
+ return ret;
+ }
+ if (readl(SOC_FBAC0_REG) & (1 << SOC_MAC_ADDR_LOCK_BIT)) {
+ diag_printf("MAC address is locked\n");
+ return -1;
+ }
+ for (i = 0; i < ETHER_ADDR_LEN; i++) {
+ int bit;
+ unsigned char fuse = readl(SOC_MAC_ADDR_BASE + (i << 2));
+
+ for (bit = 0; bit < 8; bit++) {
+ if (((mac_addr[i] >> bit) & 0x1) == 0)
+ continue;
+ if (((mac_addr[i] >> bit) & 1) == ((fuse >> bit) & 1)) {
+ continue;
+ }
+ if (fuse_blow(0, i + ((SOC_MAC_ADDR_BASE & 0xff) >> 2), bit)) {
+ diag_printf("Failed to blow fuse bank 0 row %d bit %d\n",
+ i, bit);
+ ret = -1;
+ goto out;
+ }
+ }
+ if ((fuse = readl(SOC_MAC_ADDR_BASE + (i << 2))) != mac_addr[i]) {
+ diag_printf("Fuse[%d] verify failed; wrote: 0x%02x read: 0x%02x\n",
+ i + 26, mac_addr[i], fuse);
+ ret = -1;
+ goto out;
+ }
+ }
+ fuse_blow(0, 0, SOC_MAC_ADDR_LOCK_BIT);
+out:
+ return ret;
+}
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+typedef void code_fun(void);
+
+void tx25_program_new_stack(void *func)
+{
+ register CYG_ADDRESS stack_ptr asm("sp");
+ register CYG_ADDRESS old_stack asm("r4");
+ register code_fun *new_func asm("r0");
+ old_stack = stack_ptr;
+ stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
+ new_func = (code_fun*)func;
+ new_func();
+ stack_ptr = old_stack;
+}
+
+static void display_clock_src(void)
+{
+ diag_printf("Clock input is 24 MHz\n");
+}
+
+#define WDOG_WRSR ((CYG_WORD16 *)(WDOG_BASE_ADDR + 0x4))
+#define CRM_RCSR ((CYG_WORD32 *)(CCM_BASE_ADDR + 0x28))
+
+static unsigned long random;
+extern unsigned int hal_timer_count(void);
+/* provide at least _some_ sort of randomness */
+static void random_init(void)
+{
+ do {
+ srand(random + hal_timer_count());
+ random = rand();
+ } while ((hal_timer_count() < 5) || (hal_timer_count() & 0x47110815));
+}
+RedBoot_init(random_init, RedBoot_INIT_FIRST);
+
+static void display_board_type(void)
+{
+ diag_printf("\nBoard Type: Ka-Ro TX25\n");
+}
+
+static void display_board_info(void)
+{
+ display_board_type();
+ display_clock_src();
+}
+RedBoot_init(display_board_info, RedBoot_INIT_LAST);
description "
The processor can run at various frequencies.
These values are expressed in KHz. Note that there are
- several steppings of the rated to run at different
+ several steppings of the rate to run at different
maximum frequencies. Check the specs to make sure that your
particular processor can run at the rate you select here."
}
interface allows a platform to indicate that the specified
serial port can be used as a diagnostic and/or debug channel."
}
-
- cdl_interface CYGINT_DEVS_ETH_FEC_REQUIRED {
- display "FEC ethernet driver required"
- }
-
- implements CYGINT_DEVS_ETH_FEC_REQUIRED
}
#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
-#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
- cacheable, bufferable, perm) \
- CYG_MACRO_START \
- register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
- \
- desc.word = 0; \
- desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
- desc.section.domain = 0; \
- desc.section.c = (cacheable); \
- desc.section.b = (bufferable); \
- desc.section.ap = (perm); \
- desc.section.base_address = (actual_base); \
- *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
- = desc.word; \
+#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
+ cacheable, bufferable, perm) \
+ CYG_MACRO_START \
+ register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
+ \
+ desc.word = 0; \
+ desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
+ desc.section.domain = 0; \
+ desc.section.c = cacheable; \
+ desc.section.b = bufferable; \
+ desc.section.ap = perm; \
+ desc.section.base_address = actual_base; \
+ *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, virtual_base) \
+ = desc.word; \
CYG_MACRO_END
-#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \
- { \
- int i; int j = abase; int k = vbase; \
- for (i = size; i > 0 ; i--,j++,k++) { \
- ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
- } \
- }
+#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) { \
+ int i; int j = abase; int k = vbase; \
+ for (i = size; i > 0 ; i--, j++, k++) { \
+ ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
+ } \
+}
union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
unsigned long word;
ARM_ACCESS_TYPE_NO_ACCESS(13) | \
ARM_ACCESS_TYPE_NO_ACCESS(14) | \
ARM_ACCESS_TYPE_NO_ACCESS(15) )
+/*
+ * translate the virtual address of ram space to physical address
+ * It is dependent on the implementation of hal_mmu_init
+ */
+#ifndef RAM_BANK0_SIZE
+#warning using SDRAM_SIZE for RAM_BANK0_SIZE
+#define RAM_BANK0_SIZE SDRAM_SIZE
+#endif
+
+static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
+{
+ /* SDRAM mappings:
+ 80000000 -> 80000000
+ 90000000 -> 80000000 + (SDRAM_SIZE / 2)
+ */
+ if (virt < 0x08000000) {
+ return virt | (virt < RAM_BANK0_SIZE ? CSD0_BASE_ADDR : CSD1_BASE_ADDR);
+ }
+ if ((virt & 0xF0000000) == CSD0_BASE_ADDR) {
+ virt &= ~0x08000000;
+ if (virt >= CSD0_BASE_ADDR + RAM_BANK0_SIZE) {
+ virt = virt - CSD0_BASE_ADDR + CSD1_BASE_ADDR - RAM_BANK0_SIZE;
+ }
+ }
+ return virt;
+}
+
+/*
+ * remap the physical address of ram space to uncacheable virtual address space
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
+{
+ /* 0x88000000~0x88FFFFFF is uncacheable memory space which is mapped to SDRAM */
+ if ((phy & 0xF0000000) == CSD0_BASE_ADDR) {
+ phy |= 0x08000000;
+ }
+ if ((phy & 0xF0000000) == CSD1_BASE_ADDR) {
+ phy = (phy - CSD1_BASE_ADDR + CSD0_BASE_ADDR + RAM_BANK0_SIZE) | 0x08000000;
+ }
+ return phy;
+}
// ------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_MM_H
//==========================================================================
//
-// hal_soc.h
+// hal_soc.h
//
-// SoC chip definitions
+// SoC chip definitions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
#define __HAL_SOC_H__
#ifdef __ASSEMBLER__
+#define UL(a) (a)
-#define REG8_VAL(a) (a)
-#define REG16_VAL(a) (a)
-#define REG32_VAL(a) (a)
+#define REG8_VAL(a) (a)
+#define REG16_VAL(a) (a)
+#define REG32_VAL(a) (a)
-#define REG8_PTR(a) (a)
-#define REG16_PTR(a) (a)
-#define REG32_PTR(a) (a)
+#define REG8_PTR(a) (a)
+#define REG16_PTR(a) (a)
+#define REG32_PTR(a) (a)
#else /* __ASSEMBLER__ */
+#define UL(a) (a##UL)
extern char HAL_PLATFORM_EXTRA[];
-#define REG8_VAL(a) ((unsigned char)(a))
-#define REG16_VAL(a) ((unsigned short)(a))
-#define REG32_VAL(a) ((unsigned int)(a))
-
-#define REG8_PTR(a) ((volatile unsigned char *)(a))
-#define REG16_PTR(a) ((volatile unsigned short *)(a))
-#define REG32_PTR(a) ((volatile unsigned int *)(a))
-#define readb(a) (*(volatile unsigned char *)(a))
-#define readw(a) (*(volatile unsigned short *)(a))
-#define readl(a) (*(volatile unsigned int *)(a))
-#define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
-#define writew(v,a) (*(volatile unsigned short *)(a) = (v))
-#define writel(v,a) (*(volatile unsigned int *)(a) = (v))
+#define REG8_VAL(a) ((unsigned char)(a))
+#define REG16_VAL(a) ((unsigned short)(a))
+#define REG32_VAL(a) ((unsigned int)(a))
+
+#define REG8_PTR(a) ((volatile unsigned char *)(a))
+#define REG16_PTR(a) ((volatile unsigned short *)(a))
+#define REG32_PTR(a) ((volatile unsigned int *)(a))
+#define readb(a) (*(volatile unsigned char *)(a))
+#define readw(a) (*(volatile unsigned short *)(a))
+#define readl(a) (*(volatile unsigned int *)(a))
+#define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
+#define writew(v,a) (*(volatile unsigned short *)(a) = (v))
+#define writel(v,a) (*(volatile unsigned int *)(a) = (v))
#endif /* __ASSEMBLER__ */
/*
* AIPS 1
*/
-#define AIPS1_BASE_ADDR 0x43F00000
-#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
-#define MAX_BASE_ADDR 0x43F04000
-#define CLKCTL_BASE_ADDR 0x43F08000
-#define ETB_SLOT4_BASE_ADDR 0x43F0C000
-#define ETB_SLOT5_BASE_ADDR 0x43F1000l
-#define ECT_CTIO_BASE_ADDR 0x43F18000
-#define I2C_BASE_ADDR 0x43F80000
-#define I2C3_BASE_ADDR 0x43F84000
-#define CAN1_BASE_ADDR 0x43F88000
-#define CAN2_BASE_ADDR 0x43F8C000
-#define UART1_BASE_ADDR 0x43F90000
-#define UART2_BASE_ADDR 0x43F94000
-#define I2C2_BASE_ADDR 0x43F98000
-#define OWIRE_BASE_ADDR 0x43F9C000
-#define CSPI1_BASE_ADDR 0x43FA4000
-#define KPP_BASE_ADDR 0x43FA8000
-#define IOMUXC_BASE_ADDR 0x43FAC000
-#define AUDMUX_BASE_ADDR 0x43FB0000
-#define ECT_IP1_BASE_ADDR 0x43FB8000
-#define ECT_IP2_BASE_ADDR 0x43FBC000
+#define AIPS1_BASE_ADDR UL(0x43F00000)
+#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
+#define MAX_BASE_ADDR UL(0x43F04000)
+#define CLKCTL_BASE_ADDR UL(0x43F08000)
+#define ETB_SLOT4_BASE_ADDR UL(0x43F0C000)
+#define ETB_SLOT5_BASE_ADDR UL(0x43F10000)
+#define ECT_CTIO_BASE_ADDR UL(0x43F18000)
+#define I2C_BASE_ADDR UL(0x43F80000)
+#define I2C3_BASE_ADDR UL(0x43F84000)
+#define CAN1_BASE_ADDR UL(0x43F88000)
+#define CAN2_BASE_ADDR UL(0x43F8C000)
+#define UART1_BASE_ADDR UL(0x43F90000)
+#define UART2_BASE_ADDR UL(0x43F94000)
+#define I2C2_BASE_ADDR UL(0x43F98000)
+#define OWIRE_BASE_ADDR UL(0x43F9C000)
+#define CSPI1_BASE_ADDR UL(0x43FA4000)
+#define KPP_BASE_ADDR UL(0x43FA8000)
+#define IOMUXC_BASE_ADDR UL(0x43FAC000)
+#define AUDMUX_BASE_ADDR UL(0x43FB0000)
+#define ECT_IP1_BASE_ADDR UL(0x43FB8000)
+#define ECT_IP2_BASE_ADDR UL(0x43FBC000)
/*
* SPBA
*/
-#define SPBA_BASE_ADDR 0x50000000
-#define CSPI3_BASE_ADDR 0x50040000
-#define UART4_BASE_ADDR 0x50008000
-#define UART3_BASE_ADDR 0x5000C000
-#define CSPI2_BASE_ADDR 0x50010000
-#define SSI2_BASE_ADDR 0x50014000
-#define ESAI_BASE_ADDR 0x50018000
-#define ATA_DMA_BASE_ADDR 0x50020000
-#define SIM1_BASE_ADDR 0x50024000
-#define SIM2_BASE_ADDR 0x50028000
-#define UART5_BASE_ADDR 0x5002C000
-#define TSC_BASE_ADDR 0x50030000
-#define SSI1_BASE_ADDR 0x50034000
-#define FEC_BASE_ADDR 0x50038000
-#define SOC_FEC_BASE FEC_BASE_ADDR
-#define SPBA_CTRL_BASE_ADDR 0x5003C000
+#define SPBA_BASE_ADDR UL(0x50000000)
+#define CSPI3_BASE_ADDR UL(0x50040000)
+#define UART4_BASE_ADDR UL(0x50008000)
+#define UART3_BASE_ADDR UL(0x5000C000)
+#define CSPI2_BASE_ADDR UL(0x50010000)
+#define SSI2_BASE_ADDR UL(0x50014000)
+#define ESAI_BASE_ADDR UL(0x50018000)
+#define ATA_DMA_BASE_ADDR UL(0x50020000)
+#define SIM1_BASE_ADDR UL(0x50024000)
+#define SIM2_BASE_ADDR UL(0x50028000)
+#define UART5_BASE_ADDR UL(0x5002C000)
+#define TSC_BASE_ADDR UL(0x50030000)
+#define SSI1_BASE_ADDR UL(0x50034000)
+#define FEC_BASE_ADDR UL(0x50038000)
+#define SOC_FEC_BASE FEC_BASE_ADDR
+#define SPBA_CTRL_BASE_ADDR UL(0x5003C000)
/*
* AIPS 2
*/
-#define AIPS2_BASE_ADDR 0x53F00000
-#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
-#define CCM_BASE_ADDR 0x53F80000
-#define GPT4_BASE_ADDR 0x53F84000
-#define GPT3_BASE_ADDR 0x53F88000
-#define GPT2_BASE_ADDR 0x53F8C000
-#define GPT1_BASE_ADDR 0x53F90000
-#define EPIT1_BASE_ADDR 0x53F94000
-#define EPIT2_BASE_ADDR 0x53F98000
-#define GPIO4_BASE_ADDR 0x53F9C000
-#define PWM2_BASE_ADDR 0x53FA0000
-#define GPIO3_BASE_ADDR 0x53FA4000
-#define PWM3_BASE_ADDR 0x53FA8000
-#define SCC_BASE_ADDR 0x53FAC000
-#define SCM_BASE_ADDR 0x53FAE000
-#define SMN_BASE_ADDR 0x53FAF000
-#define RNGD_BASE_ADDR 0x53FB0000
-#define MMC_SDHC1_BASE_ADDR 0x53FB4000
-#define MMC_SDHC2_BASE_ADDR 0x53FB8000
-#define ESDHC1_REG_BASE MMC_SDHC1_BASE_ADDR
-#define LCDC_BASE_ADDR 0x53FBC000
-#define SLCDC_BASE_ADDR 0x53FC0000
-#define PWM4_BASE_ADDR 0x53FC8000
-#define GPIO1_BASE_ADDR 0x53FCC000
-#define GPIO2_BASE_ADDR 0x53FD0000
-#define SDMA_BASE_ADDR 0x53FD4000
-#define WDOG_BASE_ADDR 0x53FDC000
-#define PWM1_BASE_ADDR 0x53FE0000
-#define RTIC_BASE_ADDR 0x53FEC000
-#define IIM_BASE_ADDR 0x53FF0000
-#define USB_BASE_ADDR 0x53FF4000
-#define CSI_BASE_ADDR 0x53FF8000
-#define DRYICE_BASE_ADDR 0x53FFC000
+#define AIPS2_BASE_ADDR UL(0x53F00000)
+#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
+#define CCM_BASE_ADDR UL(0x53F80000)
+#define GPT4_BASE_ADDR UL(0x53F84000)
+#define GPT3_BASE_ADDR UL(0x53F88000)
+#define GPT2_BASE_ADDR UL(0x53F8C000)
+#define GPT1_BASE_ADDR UL(0x53F90000)
+#define EPIT1_BASE_ADDR UL(0x53F94000)
+#define EPIT2_BASE_ADDR UL(0x53F98000)
+#define GPIO4_BASE_ADDR UL(0x53F9C000)
+#define PWM2_BASE_ADDR UL(0x53FA0000)
+#define GPIO3_BASE_ADDR UL(0x53FA4000)
+#define PWM3_BASE_ADDR UL(0x53FA8000)
+#define SCC_BASE_ADDR UL(0x53FAC000)
+#define SCM_BASE_ADDR UL(0x53FAE000)
+#define SMN_BASE_ADDR UL(0x53FAF000)
+#define RNGD_BASE_ADDR UL(0x53FB0000)
+#define MMC_SDHC1_BASE_ADDR UL(0x53FB4000)
+#define MMC_SDHC2_BASE_ADDR UL(0x53FB8000)
+#define ESDHC1_REG_BASE MMC_SDHC1_BASE_ADDR
+#define LCDC_BASE_ADDR UL(0x53FBC000)
+#define SLCDC_BASE_ADDR UL(0x53FC0000)
+#define PWM4_BASE_ADDR UL(0x53FC8000)
+#define GPIO1_BASE_ADDR UL(0x53FCC000)
+#define GPIO2_BASE_ADDR UL(0x53FD0000)
+#define SDMA_BASE_ADDR UL(0x53FD4000)
+#define WDOG_BASE_ADDR UL(0x53FDC000)
+#define PWM1_BASE_ADDR UL(0x53FE0000)
+#define RTIC_BASE_ADDR UL(0x53FEC000)
+#define IIM_BASE_ADDR UL(0x53FF0000)
+#define USB_BASE_ADDR UL(0x53FF4000)
+#define CSI_BASE_ADDR UL(0x53FF8000)
+#define DRYICE_BASE_ADDR UL(0x53FFC000)
/*
* ROMPATCH and AVIC
*/
-#define ROMPATCH_BASE_ADDR 0x60000000
-#define ASIC_BASE_ADDR 0x68000000
+#define ROMPATCH_BASE_ADDR UL(0x60000000)
+#define ASIC_BASE_ADDR UL(0x68000000)
-#define RAM_BASE_ADDR 0x78000000
+#define RAM_BASE_ADDR UL(0x78000000)
/*
* NAND, SDRAM, WEIM, M3IF, EMI controllers
*/
-#define EXT_MEM_CTRL_BASE 0xB8000000
-#define ESDCTL_BASE_ADDR 0xB8001000
-#define WEIM_BASE_ADDR 0xB8002000
-#define WEIM_CTRL_CS0 WEIM_BASE_ADDR
-#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10)
-#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20)
-#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30)
-#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40)
-#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50)
-#define M3IF_BASE 0xB8003000
-#define EMI_BASE 0xB8004000
-
-#define NFC_BASE 0xBB000000
+#define EXT_MEM_CTRL_BASE UL(0xB8000000)
+#define ESDCTL_BASE_ADDR UL(0xB8001000)
+#define WEIM_BASE_ADDR UL(0xB8002000)
+#define WEIM_CTRL_CS0 WEIM_BASE_ADDR
+#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10)
+#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20)
+#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30)
+#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40)
+#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50)
+#define M3IF_BASE UL(0xB8003000)
+#define EMI_BASE UL(0xB8004000)
+
+#define NFC_BASE UL(0xBB000000)
/*
* Memory regions and CS
*/
-#define CSD0_BASE_ADDR 0x80000000
-#define CSD1_BASE_ADDR 0x90000000
-#define CS0_BASE_ADDR 0xA0000000
-#define CS1_BASE_ADDR 0xA8000000
-#define CS2_BASE_ADDR 0xB0000000
-#define CS3_BASE_ADDR 0xB2000000
-#define CS4_BASE_ADDR 0xB4000000
-#define CS5_BASE_ADDR 0xB6000000
+#define CSD0_BASE_ADDR UL(0x80000000)
+#define CSD1_BASE_ADDR UL(0x90000000)
+#define CS0_BASE_ADDR UL(0xA0000000)
+#define CS1_BASE_ADDR UL(0xA8000000)
+#define CS2_BASE_ADDR UL(0xB0000000)
+#define CS3_BASE_ADDR UL(0xB2000000)
+#define CS4_BASE_ADDR UL(0xB4000000)
+#define CS5_BASE_ADDR UL(0xB6000000)
/*
* IRQ Controller Register Definitions.
*/
-#define ASIC_NIMASK REG32_PTR(ASIC_BASE_ADDR + (0x04))
-#define ASIC_INTTYPEH REG32_PTR(ASIC_BASE_ADDR + (0x18))
-#define ASIC_INTTYPEL REG32_PTR(ASIC_BASE_ADDR + (0x1C))
+#define ASIC_NIMASK REG32_PTR(ASIC_BASE_ADDR + 0x04)
+#define ASIC_INTTYPEH REG32_PTR(ASIC_BASE_ADDR + 0x18)
+#define ASIC_INTTYPEL REG32_PTR(ASIC_BASE_ADDR + 0x1C)
/* CCM */
-#define CLKCTL_MPCTL 0x00
-#define CLKCTL_UPCTL 0x04
-#define CLKCTL_CCTL 0x08
-#define CLKCTL_CGR0 0x0C
-#define CLKCTL_CGR1 0x10
-#define CLKCTL_CGR2 0x14
-#define CLKCTL_PCDR0 0x18
-#define CLKCTL_PCDR1 0x1C
-#define CLKCTL_PCDR2 0x20
-#define CLKCTL_PCDR3 0x24
-#define CLKCTL_RCSR 0x28
-#define CLKCTL_CRDR 0x2C
-#define CLKCTL_DCVR0 0x30
-#define CLKCTL_DCVR1 0x34
-#define CLKCTL_DCVR2 0x38
-#define CLKCTL_DCVR3 0x3C
-#define CLKCTL_LTR0 0x40
-#define CLKCTL_LTR1 0x44
-#define CLKCTL_LTR2 0x48
-#define CLKCTL_LTR3 0x4C
-#define CLKCTL_LTBR0 0x50
-#define CLKCTL_LTBR1 0x54
-#define CLKCTL_PCMR0 0x58
-#define CLKCTL_PCMR1 0x5C
-#define CLKCTL_PCMR2 0x60
-#define CLKCTL_MCR 0x64
-#define CLKCTL_LPIMR0 0x68
-#define CLKCTL_LPIMR1 0x6C
+#define CLKCTL_MPCTL 0x00
+#define CLKCTL_UPCTL 0x04
+#define CLKCTL_CCTL 0x08
+#define CLKCTL_CGR0 0x0C
+#define CLKCTL_CGR1 0x10
+#define CLKCTL_CGR2 0x14
+#define CLKCTL_PCDR0 0x18
+#define CLKCTL_PCDR1 0x1C
+#define CLKCTL_PCDR2 0x20
+#define CLKCTL_PCDR3 0x24
+#define CLKCTL_RCSR 0x28
+#define CLKCTL_CRDR 0x2C
+#define CLKCTL_DCVR0 0x30
+#define CLKCTL_DCVR1 0x34
+#define CLKCTL_DCVR2 0x38
+#define CLKCTL_DCVR3 0x3C
+#define CLKCTL_LTR0 0x40
+#define CLKCTL_LTR1 0x44
+#define CLKCTL_LTR2 0x48
+#define CLKCTL_LTR3 0x4C
+#define CLKCTL_LTBR0 0x50
+#define CLKCTL_LTBR1 0x54
+#define CLKCTL_PCMR0 0x58
+#define CLKCTL_PCMR1 0x5C
+#define CLKCTL_PCMR2 0x60
+#define CLKCTL_MCR 0x64
+#define CLKCTL_LPIMR0 0x68
+#define CLKCTL_LPIMR1 0x6C
#define CRM_CCTL_ARM_SRC (1 << 14)
-#define CRM_CCTL_AHB_OFFSET 28
+#define CRM_CCTL_ARM_OFFSET 30
+#define CRM_CCTL_AHB_OFFSET 28
+#define SOC_MAC_ADDR_BASE (IIM_BASE_ADDR + 0x868)
-#define FREQ_24MHZ 24000000
-#define PLL_REF_CLK FREQ_24MHZ
+#define FREQ_24MHZ 24000000
+#define PLL_REF_CLK FREQ_24MHZ
/*
* FIXME-DALE - Constants verified up to this point.
- * Offsets and derived constants below should be confirmed.
+ * Offsets and derived constants below should be confirmed.
*/
-#define CLKMODE_AUTO 0
-#define CLKMODE_CONSUMER 1
+#define CLKMODE_AUTO 0
+#define CLKMODE_CONSUMER 1
/* WEIM - CS0 */
-#define CSCRU 0x00
-#define CSCRL 0x04
-#define CSCRA 0x08
-
-#define CHIP_REV_1_0 0x0 /* PASS 1.0 */
-#define CHIP_REV_1_1 0x1 /* PASS 1.1 */
-#define CHIP_REV_2_0 0x2 /* PASS 2.0 */
-#define CHIP_LATEST CHIP_REV_1_1
-
-#define IIM_STAT_OFF 0x00
-#define IIM_STAT_BUSY (1 << 7)
-#define IIM_STAT_PRGD (1 << 1)
-#define IIM_STAT_SNSD (1 << 0)
-#define IIM_STATM_OFF 0x04
-#define IIM_ERR_OFF 0x08
-#define IIM_ERR_PRGE (1 << 7)
-#define IIM_ERR_WPE (1 << 6)
-#define IIM_ERR_OPE (1 << 5)
-#define IIM_ERR_RPE (1 << 4)
-#define IIM_ERR_WLRE (1 << 3)
-#define IIM_ERR_SNSE (1 << 2)
-#define IIM_ERR_PARITYE (1 << 1)
-#define IIM_EMASK_OFF 0x0C
-#define IIM_FCTL_OFF 0x10
-#define IIM_UA_OFF 0x14
-#define IIM_LA_OFF 0x18
-#define IIM_SDAT_OFF 0x1C
-#define IIM_PREV_OFF 0x20
-#define IIM_SREV_OFF 0x24
-#define IIM_PREG_P_OFF 0x28
-#define IIM_SCS0_OFF 0x2C
-#define IIM_SCS1_OFF 0x30
-#define IIM_SCS2_OFF 0x34
-#define IIM_SCS3_OFF 0x38
-
-#define EPIT_BASE_ADDR EPIT1_BASE_ADDR
-#define EPITCR 0x00
-#define EPITSR 0x04
-#define EPITLR 0x08
-#define EPITCMPR 0x0C
-#define EPITCNR 0x10
-
-#define GPT_BASE_ADDR GPT1_BASE_ADDR
-#define GPTCR 0x00
-#define GPTPR 0x04
-#define GPTSR 0x08
-#define GPTIR 0x0C
-#define GPTOCR1 0x10
-#define GPTOCR2 0x14
-#define GPTOCR3 0x18
-#define GPTICR1 0x1C
-#define GPTICR2 0x20
-#define GPTCNT 0x24
+#define CSCRU 0x00
+#define CSCRL 0x04
+#define CSCRA 0x08
+
+#define CHIP_REV_1_0 0x0 /* PASS 1.0 */
+#define CHIP_REV_1_1 0x1 /* PASS 1.1 */
+#define CHIP_REV_2_0 0x2 /* PASS 2.0 */
+#define CHIP_LATEST CHIP_REV_1_1
+
+#define IIM_STAT_OFF 0x00
+#define IIM_STAT_BUSY (1 << 7)
+#define IIM_STAT_PRGD (1 << 1)
+#define IIM_STAT_SNSD (1 << 0)
+#define IIM_STATM_OFF 0x04
+#define IIM_ERR_OFF 0x08
+#define IIM_ERR_PRGE (1 << 7)
+#define IIM_ERR_WPE (1 << 6)
+#define IIM_ERR_OPE (1 << 5)
+#define IIM_ERR_RPE (1 << 4)
+#define IIM_ERR_WLRE (1 << 3)
+#define IIM_ERR_SNSE (1 << 2)
+#define IIM_ERR_PARITYE (1 << 1)
+#define IIM_EMASK_OFF 0x0C
+#define IIM_FCTL_OFF 0x10
+#define IIM_UA_OFF 0x14
+#define IIM_LA_OFF 0x18
+#define IIM_SDAT_OFF 0x1C
+#define IIM_PREV_OFF 0x20
+#define IIM_SREV_OFF 0x24
+#define IIM_PREG_P_OFF 0x28
+#define IIM_SCS0_OFF 0x2C
+#define IIM_SCS1_OFF 0x30
+#define IIM_SCS2_OFF 0x34
+#define IIM_SCS3_OFF 0x38
+
+#define EPIT_BASE_ADDR EPIT1_BASE_ADDR
+#define EPITCR 0x00
+#define EPITSR 0x04
+#define EPITLR 0x08
+#define EPITCMPR 0x0C
+#define EPITCNR 0x10
+
+#define GPT_BASE_ADDR GPT1_BASE_ADDR
+#define GPTCR 0x00
+#define GPTPR 0x04
+#define GPTSR 0x08
+#define GPTIR 0x0C
+#define GPTOCR1 0x10
+#define GPTOCR2 0x14
+#define GPTOCR3 0x18
+#define GPTICR1 0x1C
+#define GPTICR2 0x20
+#define GPTCNT 0x24
/* ESDCTL */
-#define ESDCTL_ESDCTL0 0x00
-#define ESDCTL_ESDCFG0 0x04
-#define ESDCTL_ESDCTL1 0x08
-#define ESDCTL_ESDCFG1 0x0C
-#define ESDCTL_ESDMISC 0x10
+#define ESDCTL_ESDCTL0 0x00
+#define ESDCTL_ESDCFG0 0x04
+#define ESDCTL_ESDCTL1 0x08
+#define ESDCTL_ESDCFG1 0x0C
+#define ESDCTL_ESDMISC 0x10
/* DRYICE */
-#define DRYICE_DTCMR 0x00
-#define DRYICE_DTCLR 0x04
-#define DRYICE_DCAMR 0x08
-#define DRYICE_DCALR 0x0C
-#define DRYICE_DCR 0x10
-#define DRYICE_DSR 0x14
-#define DRYICE_DIER 0x18
-#define DRYICE_DMCR 0x1C
-#define DRYICE_DKSR 0x20
-#define DRYICE_DKCR 0x24
-#define DRYICE_DTCR 0x28
-#define DRYICE_DACR 0x2C
-#define DRYICE_DGPR 0x3C
-#define DRYICE_DPKR0 0x40
-#define DRYICE_DPKR1 0x44
-#define DRYICE_DPKR2 0x48
-#define DRYICE_DPKR3 0x4C
-#define DRYICE_DPKR4 0x50
-#define DRYICE_DPKR5 0x54
-#define DRYICE_DPKR6 0x58
-#define DRYICE_DPKR7 0x5C
-#define DRYICE_DRKR0 0x60
-#define DRYICE_DRKR1 0x64
-#define DRYICE_DRKR2 0x68
-#define DRYICE_DRKR3 0x6C
-#define DRYICE_DRKR4 0x70
-#define DRYICE_DRKR5 0x74
-#define DRYICE_DRKR6 0x78
-#define DRYICE_DRKR7 0x7C
+#define DRYICE_DTCMR 0x00
+#define DRYICE_DTCLR 0x04
+#define DRYICE_DCAMR 0x08
+#define DRYICE_DCALR 0x0C
+#define DRYICE_DCR 0x10
+#define DRYICE_DSR 0x14
+#define DRYICE_DIER 0x18
+#define DRYICE_DMCR 0x1C
+#define DRYICE_DKSR 0x20
+#define DRYICE_DKCR 0x24
+#define DRYICE_DTCR 0x28
+#define DRYICE_DACR 0x2C
+#define DRYICE_DGPR 0x3C
+#define DRYICE_DPKR0 0x40
+#define DRYICE_DPKR1 0x44
+#define DRYICE_DPKR2 0x48
+#define DRYICE_DPKR3 0x4C
+#define DRYICE_DPKR4 0x50
+#define DRYICE_DPKR5 0x54
+#define DRYICE_DPKR6 0x58
+#define DRYICE_DPKR7 0x5C
+#define DRYICE_DRKR0 0x60
+#define DRYICE_DRKR1 0x64
+#define DRYICE_DRKR2 0x68
+#define DRYICE_DRKR3 0x6C
+#define DRYICE_DRKR4 0x70
+#define DRYICE_DRKR5 0x74
+#define DRYICE_DRKR6 0x78
+#define DRYICE_DRKR7 0x7C
/* GPIO */
-#define GPIO_DR 0x00
-#define GPIO_GDIR 0x04
-#define GPIO_PSR0 0x08
-#define GPIO_ICR1 0x0C
-#define GPIO_ICR2 0x10
-#define GPIO_IMR 0x14
-#define GPIO_ISR 0x18
-#define GPIO_EDGE_SEL 0x1C
+#define GPIO_DR 0x00
+#define GPIO_GDIR 0x04
+#define GPIO_PSR0 0x08
+#define GPIO_ICR1 0x0C
+#define GPIO_ICR2 0x10
+#define GPIO_IMR 0x14
+#define GPIO_ISR 0x18
+#define GPIO_EDGE_SEL 0x1C
#if (PLL_REF_CLK != 24000000)
#endif
/* Assuming 24MHz input clock */
-/* PD MFD MFI MFN */
-#define MPCTL_PARAM_399 (((1-1) << 26) + ((16-1) << 16) + (8 << 10) + (5 << 0))
-#define MPCTL_PARAM_532 ((1 << 31) + ((1-1) << 26) + ((12-1) << 16) + (11 << 10) + (1 << 0))
-#define MPCTL_PARAM_665 (((1-1) << 26) + ((48-1) << 16) + (13 << 10) + (41 << 0))
+/* PD MFD MFI MFN */
+#define MPCTL_PARAM_399 (((1-1) << 26) + ((16-1) << 16) + (8 << 10) + (5 << 0))
+#define MPCTL_PARAM_532 ((1 << 31) + ((1-1) << 26) + ((12-1) << 16) + (11 << 10) + (1 << 0))
+#define MPCTL_PARAM_665 (((1-1) << 26) + ((48-1) << 16) + (13 << 10) + (41 << 0))
-/* UPCTL PD MFD MFI MFN */
-#define UPCTL_PARAM_300 (((1-1) << 26) + ((4-1) << 16) + (6 << 10) + (1 << 0))
+/* UPCTL PD MFD MFI MFN */
+#define UPCTL_PARAM_300 (((1-1) << 26) + ((4-1) << 16) + (6 << 10) + (1 << 0))
#define NFC_V1_1
-#define NAND_REG_BASE (NFC_BASE + 0x1E00)
-#define NFC_BUFSIZE_REG_OFF (0 + 0x00)
-#define RAM_BUFFER_ADDRESS_REG_OFF (0 + 0x04)
-#define NAND_FLASH_ADD_REG_OFF (0 + 0x06)
-#define NAND_FLASH_CMD_REG_OFF (0 + 0x08)
-#define NFC_CONFIGURATION_REG_OFF (0 + 0x0A)
-#define ECC_STATUS_RESULT_REG_OFF (0 + 0x0C)
-#define ECC_RSLT_MAIN_AREA_REG_OFF (0 + 0x0E)
-#define ECC_RSLT_SPARE_AREA_REG_OFF (0 + 0x10)
-#define NF_WR_PROT_REG_OFF (0 + 0x12)
-#define NAND_FLASH_WR_PR_ST_REG_OFF (0 + 0x18)
-#define NAND_FLASH_CONFIG1_REG_OFF (0 + 0x1A)
-#define NAND_FLASH_CONFIG2_REG_OFF (0 + 0x1C)
-#define UNLOCK_START_BLK_ADD_REG_OFF (0 + 0x20)
-#define UNLOCK_END_BLK_ADD_REG_OFF (0 + 0x22)
-#define RAM_BUFFER_ADDRESS_RBA_3 0x3
-#define NFC_BUFSIZE_1KB 0x0
-#define NFC_BUFSIZE_2KB 0x1
-#define NFC_CONFIGURATION_UNLOCKED 0x2
-#define ECC_STATUS_RESULT_NO_ERR 0x0
-#define ECC_STATUS_RESULT_1BIT_ERR 0x1
-#define ECC_STATUS_RESULT_2BIT_ERR 0x2
-#define NF_WR_PROT_UNLOCK 0x4
-#define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7)
-#define NAND_FLASH_CONFIG1_RST (1 << 6)
-#define NAND_FLASH_CONFIG1_BIG (1 << 5)
-#define NAND_FLASH_CONFIG1_INT_MSK (1 << 4)
-#define NAND_FLASH_CONFIG1_ECC_EN (1 << 3)
-#define NAND_FLASH_CONFIG1_SP_EN (1 << 2)
-#define NAND_FLASH_CONFIG2_INT_DONE (1 << 15)
-#define NAND_FLASH_CONFIG2_FDO_PAGE (0 << 3)
-#define NAND_FLASH_CONFIG2_FDO_ID (2 << 3)
-#define NAND_FLASH_CONFIG2_FDO_STATUS (4 << 3)
-#define NAND_FLASH_CONFIG2_FDI_EN (1 << 2)
-#define NAND_FLASH_CONFIG2_FADD_EN (1 << 1)
-#define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0)
-#define FDO_PAGE_SPARE_VAL 0x8
-#define NAND_BUF_NUM 8
-
-#define MXC_NAND_BASE_DUMMY 0x00000000
-#define MXC_MMC_BASE_DUMMY 0x00000000
-#define NOR_FLASH_BOOT 0
-#define NAND_FLASH_BOOT 0x10000000
-#define SDRAM_NON_FLASH_BOOT 0x20000000
-#define MMC_FLASH_BOOT 0x40000000
-#define MXCBOOT_FLAG_REG (CSI_BASE_ADDR + 0x28) // use CSIDMASA-FB1
-#define MXCFIS_NOTHING 0x00000000
-#define MXCFIS_NAND 0x10000000
-#define MXCFIS_NOR 0x20000000
-#define MXCFIS_MMC 0x40000000
-#define MXCFIS_FLAG_REG (CSI_BASE_ADDR + 0x2C) // use CSIDMASA-FB2
-
-#define IS_BOOTING_FROM_NAND() (readl(MXCBOOT_FLAG_REG) == NAND_FLASH_BOOT)
-#define IS_BOOTING_FROM_NOR() (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
-#define IS_BOOTING_FROM_SDRAM() (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
-#define IS_BOOTING_FROM_MMC() (readl(MXCBOOT_FLAG_REG) == MMC_FLASH_BOOT)
+#define NAND_REG_BASE (NFC_BASE + 0x1E00)
+#define NFC_BUFSIZE_REG_OFF 0x00
+#define RAM_BUFFER_ADDRESS_REG_OFF 0x04
+#define NAND_FLASH_ADD_REG_OFF 0x06
+#define NAND_FLASH_CMD_REG_OFF 0x08
+#define NFC_CONFIGURATION_REG_OFF 0x0A
+#define ECC_STATUS_RESULT_REG_OFF 0x0C
+#define ECC_RSLT_MAIN_AREA_REG_OFF 0x0E
+#define ECC_RSLT_SPARE_AREA_REG_OFF 0x10
+#define NF_WR_PROT_REG_OFF 0x12
+#define NAND_FLASH_WR_PR_ST_REG_OFF 0x18
+#define NAND_FLASH_CONFIG1_REG_OFF 0x1A
+#define NAND_FLASH_CONFIG2_REG_OFF 0x1C
+#define UNLOCK_START_BLK_ADD_REG_OFF 0x20
+#define UNLOCK_END_BLK_ADD_REG_OFF 0x22
+#define RAM_BUFFER_ADDRESS_RBA_3 0x3
+#define NFC_BUFSIZE_1KB 0x0
+#define NFC_BUFSIZE_2KB 0x1
+#define NFC_CONFIGURATION_UNLOCKED 0x2
+#define ECC_STATUS_RESULT_NO_ERR 0x0
+#define ECC_STATUS_RESULT_1BIT_ERR 0x1
+#define ECC_STATUS_RESULT_2BIT_ERR 0x2
+#define NF_WR_PROT_UNLOCK 0x4
+#define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7)
+#define NAND_FLASH_CONFIG1_RST (1 << 6)
+#define NAND_FLASH_CONFIG1_BIG (1 << 5)
+#define NAND_FLASH_CONFIG1_INT_MSK (1 << 4)
+#define NAND_FLASH_CONFIG1_ECC_EN (1 << 3)
+#define NAND_FLASH_CONFIG1_SP_EN (1 << 2)
+#define NAND_FLASH_CONFIG2_INT_DONE (1 << 15)
+#define NAND_FLASH_CONFIG2_FDO_PAGE (0 << 3)
+#define NAND_FLASH_CONFIG2_FDO_ID (2 << 3)
+#define NAND_FLASH_CONFIG2_FDO_STATUS (4 << 3)
+#define NAND_FLASH_CONFIG2_FDI_EN (1 << 2)
+#define NAND_FLASH_CONFIG2_FADD_EN (1 << 1)
+#define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0)
+#define FDO_PAGE_SPARE_VAL 0x8
+#define NAND_BUF_NUM 8
+
+#define MXC_NAND_BASE_DUMMY 0x00000000
+#define MXC_MMC_BASE_DUMMY 0x00000000
+#define NOR_FLASH_BOOT 0
+#define NAND_FLASH_BOOT 0x10000000
+#define SDRAM_NON_FLASH_BOOT 0x20000000
+#define MMC_FLASH_BOOT 0x40000000
+#define MXCBOOT_FLAG_REG (CSI_BASE_ADDR + 0x28) // use CSIDMASA-FB1
+#define MXCFIS_NOTHING 0x00000000
+#define MXCFIS_NAND 0x10000000
+#define MXCFIS_NOR 0x20000000
+#define MXCFIS_MMC 0x40000000
+#define MXCFIS_FLAG_REG (CSI_BASE_ADDR + 0x2C) // use CSIDMASA-FB2
+
+#define IS_BOOTING_FROM_NAND() (readl(MXCBOOT_FLAG_REG) == NAND_FLASH_BOOT)
+#define IS_BOOTING_FROM_NOR() (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
+#define IS_BOOTING_FROM_SDRAM() (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
+#define IS_BOOTING_FROM_MMC() (readl(MXCBOOT_FLAG_REG) == MMC_FLASH_BOOT)
#ifndef MXCFLASH_SELECT_NAND
-#define IS_FIS_FROM_NAND() 0
+#define IS_FIS_FROM_NAND() 0
#else
-#define IS_FIS_FROM_NAND() (readl(MXCFIS_FLAG_REG) == MXCFIS_NAND)
+#define IS_FIS_FROM_NAND() (readl(MXCFIS_FLAG_REG) == MXCFIS_NAND)
#endif
#ifndef MXCFLASH_SELECT_MMC
-#define IS_FIS_FROM_MMC() 0
+#define IS_FIS_FROM_MMC() 0
#else
-#define IS_FIS_FROM_MMC() (readl(MXCFIS_FLAG_REG) == MXCFIS_MMC)
+#define IS_FIS_FROM_MMC() (readl(MXCFIS_FLAG_REG) == MXCFIS_MMC)
#endif
#ifndef MXCFLASH_SELECT_NOR
-#define IS_FIS_FROM_NOR() 0
+#define IS_FIS_FROM_NOR() 0
#else
-#define IS_FIS_FROM_NOR() (readl(MXCFIS_FLAG_REG) == MXCFIS_NOR)
+#define IS_FIS_FROM_NOR() (readl(MXCFIS_FLAG_REG) == MXCFIS_NOR)
#endif
-#define MXC_ASSERT_NOR_BOOT() writel(MXCFIS_NOR, MXCFIS_FLAG_REG)
-#define MXC_ASSERT_NAND_BOOT() writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
-#define MXC_ASSERT_MMC_BOOT() writel(MXCFIS_MMC, MXCFIS_FLAG_REG)
+#define MXC_ASSERT_NOR_BOOT() writel(MXCFIS_NOR, MXCFIS_FLAG_REG)
+#define MXC_ASSERT_NAND_BOOT() writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
+#define MXC_ASSERT_MMC_BOOT() writel(MXCFIS_MMC, MXCFIS_FLAG_REG)
/*
* This macro is used to get certain bit field from a number
*/
-#define MXC_GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1))
+#define MXC_GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1))
/*
* This macro is used to set certain bit field inside a number
*/
-#define MXC_SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
+#define MXC_SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
-#define UART_WIDTH_32 /* internal UART is 32bit access only */
+#define UART_WIDTH_32 /* internal UART is 32bit access only */
#if !defined(__ASSEMBLER__)
void cyg_hal_plf_serial_init(void);
void cyg_hal_plf_serial_stop(void);
void hal_delay_us(unsigned int usecs);
-#define HAL_DELAY_US(n) hal_delay_us(n)
+#define HAL_DELAY_US(n) hal_delay_us(n)
enum plls {
- MCU_PLL = CCM_BASE_ADDR + CLKCTL_MPCTL,
- USB_PLL = CCM_BASE_ADDR + CLKCTL_UPCTL,
+ MCU_PLL = CCM_BASE_ADDR + CLKCTL_MPCTL,
+ USB_PLL = CCM_BASE_ADDR + CLKCTL_UPCTL,
};
enum main_clocks {
- CPU_CLK,
- AHB_CLK,
- IPG_CLK,
- IPG_PER_CLK, // not there on MX25 but simulated for compatibility
+ CPU_CLK,
+ AHB_CLK,
+ IPG_CLK,
+ IPG_PER_CLK, // not there on MX25 but simulated for compatibility
};
enum peri_clocks {
- PER_UART_CLK,
- SPI1_CLK = CSPI1_BASE_ADDR,
- SPI2_CLK = CSPI2_BASE_ADDR,
+ PER_UART_CLK,
+ SPI1_CLK = CSPI1_BASE_ADDR,
+ SPI2_CLK = CSPI2_BASE_ADDR,
};
unsigned int pll_clock(enum plls pll);
#endif //#if !defined(__ASSEMBLER__)
-#define HAL_MMU_OFF() \
-CYG_MACRO_START \
- asm volatile ( \
- "1: " \
- "mrc p15, 0, r15, c7, c14, 3;" /*test clean and inval*/ \
- "bne 1b;" \
- "mov r0, #0;" \
- "mcr p15,0,r0,c7,c10,4;" /*drain write buffer*/ \
- "mcr p15,0,r0,c7,c5,0;" /* invalidate I cache */ \
- "mrc p15,0,r0,c1,c0,0;" /* read c1 */ \
- "bic r0,r0,#0x7;" /* disable DCache and MMU */ \
- "bic r0,r0,#0x1000;" /* disable ICache */ \
- "mcr p15,0,r0,c1,c0,0;" /* */ \
- "nop;" /* flush i+d-TLBs */ \
- "nop;" /* flush i+d-TLBs */ \
- "nop;" /* flush i+d-TLBs */ \
- : \
- : \
- : "r0","memory" /* clobber list */); \
+#define HAL_MMU_OFF() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "1: " \
+ "mrc p15, 0, r15, c7, c14, 3;" /*test clean and inval*/ \
+ "bne 1b;" \
+ "mov r0, #0;" \
+ "mcr p15,0,r0,c7,c10,4;" /*drain write buffer*/ \
+ "mcr p15,0,r0,c7,c5,0;" /* invalidate I cache */ \
+ "mrc p15,0,r0,c1,c0,0;" /* read c1 */ \
+ "bic r0,r0,#0x7;" /* disable DCache and MMU */ \
+ "bic r0,r0,#0x1000;" /* disable ICache */ \
+ "mcr p15,0,r0,c1,c0,0;" /* */ \
+ "nop;" /* flush i+d-TLBs */ \
+ "nop;" /* flush i+d-TLBs */ \
+ "nop;" /* flush i+d-TLBs */ \
+ : \
+ : \
+ : "r0","memory" /* clobber list */); \
CYG_MACRO_END
#endif /* __HAL_SOC_H__ */
//----------------------------------------------------------------------------
// Reset.
-#define HAL_PLATFORM_RESET() \
- CYG_MACRO_START \
- *(volatile unsigned short *)WDOG_BASE_ADDR |= 0x4; \
- /* hang here forever if reset fails */ \
- while (1){} \
+#define HAL_PLATFORM_RESET() \
+ CYG_MACRO_START \
+ *(volatile unsigned short *)WDOG_BASE_ADDR &= ~(1 << 4); \
+ /* hang here forever if reset fails */ \
+ while (1){} \
CYG_MACRO_END
// Fallback (never really used)
//==========================================================================
//
-// cmds.c
+// cmds.c
//
-// SoC [platform] specific RedBoot commands
+// SoC [platform] specific RedBoot commands
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
#include <redboot.h>
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/plf_mmap.h>
-#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
#include <cyg/hal/hal_cache.h>
#define IIM_FUSE_DEBUG
-typedef unsigned long long u64;
-typedef unsigned int u32;
-typedef unsigned short u16;
-typedef unsigned char u8;
+typedef unsigned long long u64;
+typedef unsigned int u32;
+typedef unsigned short u16;
+typedef unsigned char u8;
u32 pll_clock(enum plls pll);
u32 get_main_clock(enum main_clocks clk);
static void clock_setup(int argc, char *argv[]);
RedBoot_cmd("clock",
- "Setup/Display clock\nSyntax:",
- "[<ARM core clock in MHz> [:<ARM-AHB clock divider>]\n\
+ "Setup/Display clock\nSyntax:",
+
"[<ARM core clock in MHz> [:<ARM-AHB clock divider>]\n\
If a selection is zero or no divider is specified, the optimal divider values\n\
will be chosen. Examples:\n\
[clock] -> Show various clocks\n\
[clock 199:3] -> Core=199.5 AHB=66.5(Core/3) IPG=33.25(AHB/2)\n\
[clock 133:2] -> Core=133 AHB=66.5(Core/2) IPG=33.25(AHB/2)\n\
Core range: 532-133, AHB range: 133-66.5, IPG is always AHB/2\n",
- clock_setup
- );
+ clock_setup
+ );
void clock_spi_enable(unsigned int spi_clk)
{
- diag_printf("%s: stubbed\n", __func__);
+ diag_printf("%s: stubbed\n", __func__);
}
static void clock_setup(int argc,char *argv[])
{
- u32 i, data[2], temp, core_clk, ahb_div, cctl, arm_src, arm_div;
-
- if (argc == 1)
- goto print_clock;
-
- for (i = 0; i < 2; i++) {
- if (!parse_num(*(&argv[1]), (unsigned long *)&temp, &argv[1], ":")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
- data[i] = temp;
- }
-
- core_clk = data[0];
- ahb_div = data[1] - 1;
-
- if (core_clk / (ahb_div + 1) > 133 ||
- core_clk / (ahb_div + 1) < 66) {
- diag_printf("Illegal AHB divider value specified\n");
- return;
- }
-
- switch (core_clk) {
- case 532:
- arm_src = 0;
- arm_div = 1 - 1;
- break;
- case 399:
- arm_src = 1;
- arm_div = 1 - 1;
- break;
- case 199:
- case 200:
- arm_src = 1;
- arm_div = 2 - 1;
- break;
- case 133:
- arm_src = 1;
- arm_div = 3 - 1;
- break;
- default:
- diag_printf("Illegal core clock value specified\n");
- return;
- }
-
- cctl = readl(CCM_BASE_ADDR + CLKCTL_CCTL);
- cctl &= ~0xF0004000;
- cctl |= arm_div << 30;
- cctl |= ahb_div << 28;
- cctl |= arm_src << 14;
- writel(cctl, CCM_BASE_ADDR + CLKCTL_CCTL);
-
- diag_printf("\n<<<New clock settings>>>\n");
-
- // Now printing clocks
+ u32 i, data[2], core_clk, ahb_div, cctl, arm_src, arm_div;
+ unsigned long temp;
+
+ if (argc == 1)
+ goto print_clock;
+
+ for (i = 0; i < 2; i++) {
+ if (!parse_num(argv[1], &temp, &argv[1], ":")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ data[i] = temp;
+ }
+
+ core_clk = data[0];
+ ahb_div = data[1] - 1;
+
+ if (core_clk / (ahb_div + 1) > 133 ||
+ core_clk / (ahb_div + 1) < 66) {
+ diag_printf("Illegal AHB divider value specified\n");
+ return;
+ }
+
+ switch (core_clk) {
+ case 532:
+ arm_src = 0;
+ arm_div = 1 - 1;
+ break;
+ case 399:
+ arm_src = 1;
+ arm_div = 1 - 1;
+ break;
+ case 199:
+ case 200:
+ arm_src = 1;
+ arm_div = 2 - 1;
+ break;
+ case 133:
+ arm_src = 1;
+ arm_div = 3 - 1;
+ break;
+ default:
+ diag_printf("Illegal core clock value specified\n");
+ return;
+ }
+
+ cyg_hal_plf_serial_stop();
+
+ cctl = readl(CCM_BASE_ADDR + CLKCTL_CCTL);
+ cctl &= ~0xF0004000;
+ cctl |= arm_div << 30;
+ cctl |= ahb_div << 28;
+ cctl |= arm_src << 14;
+ writel(cctl, CCM_BASE_ADDR + CLKCTL_CCTL);
+
+ hal_delay_us(10000);
+ cyg_hal_plf_serial_init();
+
+ diag_printf("\n<<<New clock settings>>>\n");
+
+ // Now printing clocks
print_clock:
- diag_printf("\nMPLL\t\tUPLL\n");
- diag_printf("=========================\n");
- diag_printf("%-16d%-16d\n\n", pll_clock(MCU_PLL), pll_clock(USB_PLL));
- diag_printf("CPU\t\tAHB\t\tIPG\n");
- diag_printf("========================================\n");
- diag_printf("%-16d%-16d%-16d\n\n",
- get_main_clock(CPU_CLK),
- get_main_clock(AHB_CLK),
- get_main_clock(IPG_CLK));
-
- diag_printf("UART\n");
- diag_printf("========\n");
- diag_printf("%-16d\n\n",
- get_peri_clock(PER_UART_CLK));
-
- diag_printf("SPI\n");
- diag_printf("========\n");
- diag_printf("%-16d\n\n",
- get_peri_clock(SPI1_CLK));
+ diag_printf("\nMPLL\t\tUPLL\n");
+ diag_printf("=========================\n");
+ diag_printf("%-16d%-16d\n\n", pll_clock(MCU_PLL), pll_clock(USB_PLL));
+ diag_printf("CPU\t\tAHB\t\tIPG\n");
+ diag_printf("========================================\n");
+ diag_printf("%-16d%-16d%-16d\n\n",
+ get_main_clock(CPU_CLK),
+ get_main_clock(AHB_CLK),
+ get_main_clock(IPG_CLK));
+
+ diag_printf("UART\n");
+ diag_printf("========\n");
+ diag_printf("%-16d\n\n",
+ get_peri_clock(PER_UART_CLK));
+
+ diag_printf("SPI\n");
+ diag_printf("========\n");
+ diag_printf("%-16d\n\n",
+ get_peri_clock(SPI1_CLK));
}
/*!
*/
u32 pll_clock(enum plls pll)
{
- u64 mfi, mfn, mfd, pdf, ref_clk, pll_out;
- u64 reg = readl(pll);
-
- pdf = (reg >> 26) & 0xF;
- mfd = (reg >> 16) & 0x3FF;
- mfi = (reg >> 10) & 0xF;
- mfi = (mfi <= 5) ? 5: mfi;
- mfn = reg & 0x3FF;
-
- ref_clk = PLL_REF_CLK;
-
- pll_out = (2 * ref_clk * mfi + ((2 * ref_clk * mfn) / (mfd + 1))) /
- (pdf + 1);
-
- return (u32)pll_out;
+ int mfi, mfn, mfd, pdf;
+ u32 pll_out;
+ u32 reg = readl(pll);
+ u64 ref_clk;
+
+ pdf = (reg >> 26) & 0xF;
+ mfd = (reg >> 16) & 0x3FF;
+ mfi = (reg >> 10) & 0xF;
+ if (mfi < 5) {
+ mfi = 5;
+ }
+ mfn = reg & 0x3FF;
+ if (mfn >= 512) {
+ mfn = 1024 - mfn;
+ }
+ ref_clk = PLL_REF_CLK;
+
+ pll_out = (2 * ref_clk * mfi + ((2 * ref_clk * mfn) / (mfd + 1))) /
+ (pdf + 1);
+ return pll_out;
}
/*!
*/
u32 get_main_clock(enum main_clocks clk)
{
- u32 cctl = readl(CCM_BASE_ADDR + CLKCTL_CCTL);
- u32 ahb_div;
- u32 ret_val = 0;
-
- switch (clk) {
- case CPU_CLK:
- ret_val = pll_clock(MCU_PLL);
- if (cctl & CRM_CCTL_ARM_SRC) {
- ret_val *= 3;
- ret_val /= 4;
- }
- break;
- case AHB_CLK:
- ahb_div = ((cctl >> CRM_CCTL_AHB_OFFSET) & 3) + 1;
- ret_val = get_main_clock(CPU_CLK) / ahb_div;
- break;
- case IPG_CLK:
- case IPG_PER_CLK:
- ret_val = get_main_clock(AHB_CLK) / 2;
- break;
- default:
- diag_printf("Unknown clock: %d\n", clk);
- break;
- }
-
- return ret_val;
+ u32 cctl = readl(CCM_BASE_ADDR + CLKCTL_CCTL);
+ u32 div;
+ u32 ret_val = 0;
+
+ switch (clk) {
+ case CPU_CLK:
+ ret_val = pll_clock(MCU_PLL);
+ if (cctl & CRM_CCTL_ARM_SRC) {
+ ret_val = (ret_val * 3) / 4;
+ }
+ div = ((cctl >> CRM_CCTL_ARM_OFFSET) & 3) + 1;
+ ret_val /= div;
+ break;
+ case AHB_CLK:
+ div = ((cctl >> CRM_CCTL_AHB_OFFSET) & 3) + 1;
+ ret_val = get_main_clock(CPU_CLK) / div;
+ break;
+ case IPG_CLK:
+ case IPG_PER_CLK:
+ ret_val = get_main_clock(AHB_CLK) / 2;
+ break;
+ default:
+ diag_printf("Unknown clock: %d\n", clk);
+ }
+
+ return ret_val;
}
/*!
*/
u32 get_peri_clock(enum peri_clocks clk)
{
- u32 ret_val = 0;
- u32 pcdr, div;
-
- switch (clk) {
- case PER_UART_CLK:
- pcdr = readl(CCM_BASE_ADDR + CLKCTL_PCDR3);
- div = (pcdr >> 24) + 1;
- ret_val = get_main_clock(AHB_CLK) / div;
- break;
- case SPI1_CLK:
- case SPI2_CLK:
- ret_val = get_main_clock(IPG_CLK);
- break;
- default:
- diag_printf("%s(): This clock: %d not supported yet \n",
- __FUNCTION__, clk);
- break;
- }
- return ret_val;
+ u32 ret_val = 0;
+ u32 pcdr, div;
+
+ switch (clk) {
+ case PER_UART_CLK:
+ pcdr = readl(CCM_BASE_ADDR + CLKCTL_PCDR3);
+ div = (pcdr >> 24) + 1;
+ ret_val = get_main_clock(AHB_CLK) / div;
+ break;
+ case SPI1_CLK:
+ case SPI2_CLK:
+ ret_val = get_main_clock(IPG_CLK);
+ break;
+ default:
+ diag_printf("%s(): This clock: %d not supported yet\n",
+ __FUNCTION__, clk);
+ }
+ return ret_val;
}
-#define IIM_ERR_SHIFT 8
-#define POLL_FUSE_PRGD (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT))
-#define POLL_FUSE_SNSD (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT))
+#define IIM_ERR_SHIFT 8
+#define POLL_FUSE_PRGD (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT))
+#define POLL_FUSE_SNSD (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT))
static void fuse_op_start(void)
{
- /* Do not generate interrupt */
- writel(0, IIM_BASE_ADDR + IIM_STATM_OFF);
- // clear the status bits and error bits
- writel(0x3, IIM_BASE_ADDR + IIM_STAT_OFF);
- writel(0xFE, IIM_BASE_ADDR + IIM_ERR_OFF);
+ /* Do not generate interrupt */
+ writel(0, IIM_BASE_ADDR + IIM_STATM_OFF);
+ // clear the status bits and error bits
+ writel(0x3, IIM_BASE_ADDR + IIM_STAT_OFF);
+ writel(0xFE, IIM_BASE_ADDR + IIM_ERR_OFF);
}
/*
* The action should be either:
- * POLL_FUSE_PRGD
+ * POLL_FUSE_PRGD
* or:
- * POLL_FUSE_SNSD
+ * POLL_FUSE_SNSD
*/
static int poll_fuse_op_done(int action)
{
- u32 status, error;
-
- if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) {
- diag_printf("%s(%d) invalid operation\n", __FUNCTION__, action);
- return -1;
- }
-
- /* Poll busy bit till it is NOT set */
- while ((readl(IIM_BASE_ADDR + IIM_STAT_OFF) & IIM_STAT_BUSY) != 0 ) {
- }
-
- /* Test for successful write */
- status = readl(IIM_BASE_ADDR + IIM_STAT_OFF);
- error = readl(IIM_BASE_ADDR + IIM_ERR_OFF);
-
- if ((status & action) != 0 && (error & (action >> IIM_ERR_SHIFT)) == 0) {
- if (error) {
- diag_printf("Even though the operation seems successful...\n");
- diag_printf("There are some error(s) at addr=0x%x: 0x%x\n",
- (IIM_BASE_ADDR + IIM_ERR_OFF), error);
- }
- return 0;
- }
- diag_printf("%s(%d) failed\n", __FUNCTION__, action);
- diag_printf("status address=0x%x, value=0x%x\n",
- (IIM_BASE_ADDR + IIM_STAT_OFF), status);
- diag_printf("There are some error(s) at addr=0x%x: 0x%x\n",
- (IIM_BASE_ADDR + IIM_ERR_OFF), error);
- return -1;
+ u32 status, error;
+
+ if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) {
+ diag_printf("%s(%d) invalid operation\n", __FUNCTION__, action);
+ return -1;
+ }
+
+ /* Poll busy bit till it is NOT set */
+ while ((readl(IIM_BASE_ADDR + IIM_STAT_OFF) & IIM_STAT_BUSY) != 0 ) {
+ }
+
+ /* Test for successful write */
+ status = readl(IIM_BASE_ADDR + IIM_STAT_OFF);
+ error = readl(IIM_BASE_ADDR + IIM_ERR_OFF);
+
+ if ((status & action) != 0 && (error & (action >> IIM_ERR_SHIFT)) == 0) {
+ if (error) {
+ diag_printf("Even though the operation seems successful...\n");
+ diag_printf("There are some error(s) at addr=0x%02lx: 0x%02x\n",
+ (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+ }
+ return 0;
+ }
+ diag_printf("%s(%d) failed\n", __FUNCTION__, action);
+ diag_printf("status address=0x%02lx, value=0x%02x\n",
+ (IIM_BASE_ADDR + IIM_STAT_OFF), status);
+ diag_printf("There are some error(s) at addr=0x%02lx: 0x%02x\n",
+ (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+ return -1;
}
static void sense_fuse(int bank, int row, int bit)
{
+ int ret;
int addr, addr_l, addr_h, reg_addr;
- fuse_op_start();
+ fuse_op_start();
- addr = ((bank << 11) | (row << 3) | (bit & 0x7));
- /* Set IIM Program Upper Address */
- addr_h = (addr >> 8) & 0x000000FF;
- /* Set IIM Program Lower Address */
- addr_l = (addr & 0x000000FF);
+ addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+ /* Set IIM Program Upper Address */
+ addr_h = (addr >> 8) & 0x000000FF;
+ /* Set IIM Program Lower Address */
+ addr_l = (addr & 0x000000FF);
#ifdef IIM_FUSE_DEBUG
- diag_printf("%s: addr_h=0x%x, addr_l=0x%x\n",
- __FUNCTION__, addr_h, addr_l);
+ diag_printf("%s: addr_h=0x%02x, addr_l=0x%02x\n",
+ __FUNCTION__, addr_h, addr_l);
#endif
- writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
- writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
- /* Start sensing */
- writel(0x8, IIM_BASE_ADDR + IIM_FCTL_OFF);
- if (poll_fuse_op_done(POLL_FUSE_SNSD) != 0) {
- diag_printf("%s(bank: %d, row: %d, bit: %d failed\n",
- __FUNCTION__, bank, row, bit);
- }
- reg_addr = IIM_BASE_ADDR + IIM_SDAT_OFF;
- diag_printf("fuses at (bank:%d, row:%d) = 0x%x\n", bank, row, readl(reg_addr));
+ writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
+ writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
+ /* Start sensing */
+ writel(0x8, IIM_BASE_ADDR + IIM_FCTL_OFF);
+ if ((ret = poll_fuse_op_done(POLL_FUSE_SNSD)) != 0) {
+ diag_printf("%s(bank: %d, row: %d, bit: %d failed\n",
+ __FUNCTION__, bank, row, bit);
+ }
+ reg_addr = IIM_BASE_ADDR + IIM_SDAT_OFF;
+ if (ret == 0)
+ diag_printf("fuses at (bank:%d, row:%d) = 0x%02x\n", bank, row, readl(reg_addr));
}
void do_fuse_read(int argc, char *argv[])
{
- int bank, row;
-
- if (argc == 1) {
- diag_printf("Useage: fuse_read <bank> <row>\n");
- return;
- } else if (argc == 3) {
- if (!parse_num(*(&argv[1]), (unsigned long *)&bank, &argv[1], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
- if (!parse_num(*(&argv[2]), (unsigned long *)&row, &argv[2], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
-
- diag_printf("Read fuse at bank:%d row:%d\n", bank, row);
- sense_fuse(bank, row, 0);
-
- } else {
- diag_printf("Passing in wrong arguments: %d\n", argc);
- diag_printf("Useage: fuse_read <bank> <row>\n");
- }
+ unsigned long bank, row;
+
+ if (argc == 1) {
+ diag_printf("Useage: fuse_read <bank> <row>\n");
+ return;
+ } else if (argc == 3) {
+ if (!parse_num(argv[1], &bank, &argv[1], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(argv[2], &row, &argv[2], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+
+ diag_printf("Read fuse at bank:%ld row:%ld\n", bank, row);
+ sense_fuse(bank, row, 0);
+
+ } else {
+ diag_printf("Passing in wrong arguments: %d\n", argc);
+ diag_printf("Useage: fuse_read <bank> <row>\n");
+ }
}
/* Blow fuses based on the bank, row and bit positions (all 0-based)
*/
-static int fuse_blow(int bank,int row,int bit)
+int fuse_blow(int bank,int row,int bit)
{
- int addr, addr_l, addr_h, ret = -1;
+ int addr, addr_l, addr_h, ret = -1;
- fuse_op_start();
+ fuse_op_start();
- /* Disable IIM Program Protect */
- writel(0xAA, IIM_BASE_ADDR + IIM_PREG_P_OFF);
+ /* Disable IIM Program Protect */
+ writel(0xAA, IIM_BASE_ADDR + IIM_PREG_P_OFF);
- addr = ((bank << 11) | (row << 3) | (bit & 0x7));
- /* Set IIM Program Upper Address */
- addr_h = (addr >> 8) & 0x000000FF;
- /* Set IIM Program Lower Address */
- addr_l = (addr & 0x000000FF);
+ addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+ /* Set IIM Program Upper Address */
+ addr_h = (addr >> 8) & 0x000000FF;
+ /* Set IIM Program Lower Address */
+ addr_l = (addr & 0x000000FF);
#ifdef IIM_FUSE_DEBUG
- diag_printf("blowing addr_h=0x%x, addr_l=0x%x\n", addr_h, addr_l);
+ diag_printf("blowing addr_h=0x%02x, addr_l=0x%02x\n", addr_h, addr_l);
#endif
- writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
- writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
- /* Start Programming */
- writel(0x71, IIM_BASE_ADDR + IIM_FCTL_OFF);
- if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) {
- ret = 0;
- }
-
- /* Enable IIM Program Protect */
- writel(0x0, IIM_BASE_ADDR + IIM_PREG_P_OFF);
- return ret;
+ writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
+ writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
+ /* Start Programming */
+ writel(0x71, IIM_BASE_ADDR + IIM_FCTL_OFF);
+ if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) {
+ ret = 0;
+ }
+
+ /* Enable IIM Program Protect */
+ writel(0x0, IIM_BASE_ADDR + IIM_PREG_P_OFF);
+ return ret;
}
/*
* This command is added for burning IIM fuses
*/
RedBoot_cmd("fuse_read",
- "read some fuses",
- "<bank> <row>",
- do_fuse_read
- );
+ "read some fuses",
+ "<bank> <row>",
+ do_fuse_read
+ );
RedBoot_cmd("fuse_blow",
- "blow some fuses",
- "<bank> <row> <value>",
- do_fuse_blow
- );
+ "blow some fuses",
+ "<bank> <row> <value>",
+ do_fuse_blow
+ );
-#define INIT_STRING "12345678"
+#define INIT_STRING "12345678"
static char ready_to_blow[] = INIT_STRING;
void quick_itoa(u32 num, char *a)
{
- int i, j, k;
- for (i = 0; i <= 7; i++) {
- j = (num >> (4 * i)) & 0xF;
- k = (j < 10) ? '0' : ('a' - 0xa);
- a[i] = j + k;
- }
+ int i, j, k;
+ for (i = 0; i <= 7; i++) {
+ j = (num >> (4 * i)) & 0xF;
+ k = (j < 10) ? '0' : ('a' - 0xa);
+ a[i] = j + k;
+ }
}
void do_fuse_blow(int argc, char *argv[])
{
- int bank, row, value, i;
-
- if (argc == 1) {
- diag_printf("It is too dangeous for you to use this command.\n");
- return;
- } else if (argc == 2) {
- if (strcasecmp(argv[1], "nandboot") == 0) {
- quick_itoa(readl(EPIT_BASE_ADDR + EPITCNR), ready_to_blow);
- diag_printf("%s\n", ready_to_blow);
- }
- return;
- } else if (argc == 3) {
- if (strcasecmp(argv[1], "nandboot") == 0 &&
- strcasecmp(argv[2], ready_to_blow) == 0) {
+ unsigned long bank, row, value;
+ int i;
+
+ if (argc == 1) {
+ diag_printf("It is too dangeous for you to use this command.\n");
+ return;
+ } else if (argc == 2) {
+ if (strcasecmp(argv[1], "nandboot") == 0) {
+ quick_itoa(readl(EPIT_BASE_ADDR + EPITCNR), ready_to_blow);
+ diag_printf("%s\n", ready_to_blow);
+ }
+ return;
+ } else if (argc == 3) {
+ if (strcasecmp(argv[1], "nandboot") == 0 &&
+ strcasecmp(argv[2], ready_to_blow) == 0) {
#if defined(CYGPKG_HAL_ARM_MXC91131) || defined(CYGPKG_HAL_ARM_MX21) || defined(CYGPKG_HAL_ARM_MX27) || defined(CYGPKG_HAL_ARM_MX31) ||defined(CYGPKG_HAL_ARM_MX35) || defined(CYGPKG_HAL_ARM_MX25)
- diag_printf("No need to blow any fuses for NAND boot on this platform\n\n");
+ diag_printf("No need to blow any fuses for NAND boot on this platform\n\n");
#else
#error "Are you sure you want this?"
- diag_printf("Ready to burn NAND boot fuses\n");
- if (fuse_blow(0, 16, 1) != 0 || fuse_blow(0, 16, 7) != 0) {
- diag_printf("NAND BOOT fuse blown failed miserably ...\n");
- } else {
- diag_printf("NAND BOOT fuse blown successfully ...\n");
- }
- } else {
- diag_printf("Not ready: %s, %s\n", argv[1], argv[2]);
+ diag_printf("Ready to burn NAND boot fuses\n");
+ if (fuse_blow(0, 16, 1) != 0 || fuse_blow(0, 16, 7) != 0) {
+ diag_printf("NAND BOOT fuse blown failed miserably ...\n");
+ } else {
+ diag_printf("NAND BOOT fuse blown successfully ...\n");
+ }
+ } else {
+ diag_printf("Not ready: %s, %s\n", argv[1], argv[2]);
#endif
- }
- } else if (argc == 4) {
- if (!parse_num(*(&argv[1]), (unsigned long *)&bank, &argv[1], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
- if (!parse_num(*(&argv[2]), (unsigned long *)&row, &argv[2], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
- if (!parse_num(*(&argv[3]), (unsigned long *)&value, &argv[3], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
-
- diag_printf("Blowing fuse at bank:%d row:%d value:%d\n",
- bank, row, value);
- for (i = 0; i < 8; i++) {
- if (((value >> i) & 0x1) == 0) {
- continue;
- }
- if (fuse_blow(bank, row, i) != 0) {
- diag_printf("fuse_blow(bank: %d, row: %d, bit: %d failed\n",
- bank, row, i);
- } else {
- diag_printf("fuse_blow(bank: %d, row: %d, bit: %d successful\n",
- bank, row, i);
- }
- }
- sense_fuse(bank, row, 0);
-
- } else {
- diag_printf("Passing in wrong arguments: %d\n", argc);
- }
- /* Reset to default string */
- strcpy(ready_to_blow, INIT_STRING);;
+ }
+ } else if (argc == 4) {
+ if (!parse_num(argv[1], &bank, &argv[1], " ")) {
+ diag_printf("Error: Invalid fuse bank\n");
+ return;
+ }
+ if (!parse_num(argv[2], &row, &argv[2], " ")) {
+ diag_printf("Error: Invalid fuse row\n");
+ return;
+ }
+ if (!parse_num(argv[3], &value, &argv[3], " ")) {
+ diag_printf("Error: Invalid value\n");
+ return;
+ }
+ if (!verify_action("Confirm to blow fuse at bank:%ld row:%ld value:0x%02lx (%ld)",
+ bank, row, value)) {
+ diag_printf("fuse_blow canceled\n");
+ return;
+ }
+
+ diag_printf("Blowing fuse at bank:%ld row:%ld value:%ld\n",
+ bank, row, value);
+ for (i = 0; i < 8; i++) {
+ if (((value >> i) & 0x1) == 0) {
+ continue;
+ }
+ if (fuse_blow(bank, row, i) != 0) {
+ diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d failed\n",
+ bank, row, i);
+ } else {
+ diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d successful\n",
+ bank, row, i);
+ }
+ }
+ sense_fuse(bank, row, 0);
+ } else {
+ diag_printf("Passing in wrong arguments: %d\n", argc);
+ }
+ /* Reset to default string */
+ strcpy(ready_to_blow, INIT_STRING);
}
/* precondition: m>0 and n>0. Let g=gcd(m,n). */
int gcd(int m, int n)
{
- int t;
- while(m > 0) {
- if(n > m) {t = m; m = n; n = t;} /* swap */
- m -= n;
- }
- return n;
+ int t;
+ while (m > 0) {
+ if (n > m) {t = m; m = n; n = t;} /* swap */
+ m -= n;
+ }
+ return n;
}
-
/*=============================================================================
//
-// hal_diag.c
+// hal_diag.c
//
-// HAL diagnostic output code
+// HAL diagnostic output code
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
#include <pkgconf/system.h>
#include CYGBLD_HAL_PLATFORM_H
-#include <cyg/infra/cyg_type.h> // base types
-#include <cyg/infra/cyg_trac.h> // tracing macros
-#include <cyg/infra/cyg_ass.h> // assertion macros
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
-#include <cyg/hal/hal_arch.h> // basic machine info
-#include <cyg/hal/hal_intr.h> // interrupt macros
-#include <cyg/hal/hal_io.h> // IO macros
-#include <cyg/hal/hal_if.h> // Calling interface definitions
+#include <cyg/hal/hal_arch.h> // basic machine info
+#include <cyg/hal/hal_intr.h> // interrupt macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_if.h> // Calling interface definitions
#include <cyg/hal/hal_diag.h>
-#include <cyg/hal/drv_api.h> // cyg_drv_interrupt_acknowledge
-#include <cyg/hal/hal_misc.h> // Helper functions
-#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/drv_api.h> // cyg_drv_interrupt_acknowledge
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
/*
* UART Control Register 0 Bit Fields.
*/
-#define EUartUCR1_ADEN (1 << 15) // Auto dectect interrupt
-#define EUartUCR1_ADBR (1 << 14) // Auto detect baud rate
-#define EUartUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable
-#define EUartUCR1_IDEN (1 << 12) // Idle condition interrupt
-#define EUartUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable
-#define EUartUCR1_RDMAEN (1 << 8) // Recv ready DMA enable
-#define EUartUCR1_IREN (1 << 7) // Infrared interface enable
-#define EUartUCR1_TXMPTYEN (1 << 6) // Transimitter empty interrupt enable
-#define EUartUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable
-#define EUartUCR1_SNDBRK (1 << 4) // Send break
-#define EUartUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable
-#define EUartUCR1_DOZE (1 << 1) // Doze
-#define EUartUCR1_UARTEN (1 << 0) // UART enabled
-#define EUartUCR2_ESCI (1 << 15) // Escape seq interrupt enable
-#define EUartUCR2_IRTS (1 << 14) // Ignore RTS pin
-#define EUartUCR2_CTSC (1 << 13) // CTS pin control
-#define EUartUCR2_CTS (1 << 12) // Clear to send
-#define EUartUCR2_ESCEN (1 << 11) // Escape enable
-#define EUartUCR2_PREN (1 << 8) // Parity enable
-#define EUartUCR2_PROE (1 << 7) // Parity odd/even
-#define EUartUCR2_STPB (1 << 6) // Stop
-#define EUartUCR2_WS (1 << 5) // Word size
-#define EUartUCR2_RTSEN (1 << 4) // Request to send interrupt enable
-#define EUartUCR2_ATEN (1 << 3) // Aging timer enable
-#define EUartUCR2_TXEN (1 << 2) // Transmitter enabled
-#define EUartUCR2_RXEN (1 << 1) // Receiver enabled
-#define EUartUCR2_SRST_ (1 << 0) // SW reset
-#define EUartUCR3_PARERREN (1 << 12) // Parity enable
-#define EUartUCR3_FRAERREN (1 << 11) // Frame error interrupt enable
-#define EUartUCR3_ADNIMP (1 << 7) // Autobaud detection not improved
-#define EUartUCR3_RXDSEN (1 << 6) // Receive status interrupt enable
-#define EUartUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable
-#define EUartUCR3_AWAKEN (1 << 4) // Async wake interrupt enable
-#define EUartUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected
-#define EUartUCR3_INVT (1 << 1) // Inverted Infrared transmission
-#define EUartUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable
-#define EUartUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars)
-#define EUartUCR4_INVR (1 << 9) // Inverted infrared reception
-#define EUartUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable
-#define EUartUCR4_WKEN (1 << 7) // Wake interrupt enable
-#define EUartUCR4_IRSC (1 << 5) // IR special case
-#define EUartUCR4_LPBYP (1 << 4) // Low power bypass
-#define EUartUCR4_TCEN (1 << 3) // Transmit complete interrupt enable
-#define EUartUCR4_BKEN (1 << 2) // Break condition interrupt enable
-#define EUartUCR4_OREN (1 << 1) // Receiver overrun interrupt enable
-#define EUartUCR4_DREN (1 << 0) // Recv data ready interrupt enable
-#define EUartUFCR_RXTL_SHF 0 // Receiver trigger level shift
-#define EUartUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div 1)
-#define EUartUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div 2)
-#define EUartUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3)
-#define EUartUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4)
-#define EUartUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5)
-#define EUartUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6)
-#define EUartUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7)
-#define EUartUFCR_TXTL_SHF 10 // Transmitter trigger level shift
-#define EUartUSR1_PARITYERR (1 << 15) // Parity error interrupt flag
-#define EUartUSR1_RTSS (1 << 14) // RTS pin status
-#define EUartUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag
-#define EUartUSR1_RTSD (1 << 12) // RTS delta
-#define EUartUSR1_ESCF (1 << 11) // Escape seq interrupt flag
-#define EUartUSR1_FRAMERR (1 << 10) // Frame error interrupt flag
-#define EUartUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag
-#define EUartUSR1_AGTIM (1 << 8) // Aging timeout interrupt status
-#define EUartUSR1_RXDS (1 << 6) // Receiver idle interrupt flag
-#define EUartUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag
-#define EUartUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag
-#define EUartUSR2_ADET (1 << 15) // Auto baud rate detect complete
-#define EUartUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty
-#define EUartUSR2_IDLE (1 << 12) // Idle condition
-#define EUartUSR2_ACST (1 << 11) // Autobaud counter stopped
-#define EUartUSR2_IRINT (1 << 8) // Serial infrared interrupt flag
-#define EUartUSR2_WAKE (1 << 7) // Wake
-#define EUartUSR2_RTSF (1 << 4) // RTS edge interrupt flag
-#define EUartUSR2_TXDC (1 << 3) // Transmitter complete
-#define EUartUSR2_BRCD (1 << 2) // Break condition
-#define EUartUSR2_ORE (1 << 1) // Overrun error
-#define EUartUSR2_RDR (1 << 0) // Recv data ready
-#define EUartUTS_FRCPERR (1 << 13) // Force parity error
-#define EUartUTS_LOOP (1 << 12) // Loop tx and rx
-#define EUartUTS_TXEMPTY (1 << 6) // TxFIFO empty
-#define EUartUTS_RXEMPTY (1 << 5) // RxFIFO empty
-#define EUartUTS_TXFULL (1 << 4) // TxFIFO full
-#define EUartUTS_RXFULL (1 << 3) // RxFIFO full
-#define EUartUTS_SOFTRST (1 << 0) // Software reset
-
-#define EUartUFCR_RFDIV EUartUFCR_RFDIV_1
+#define EUartUCR1_ADEN (1 << 15) // Auto dectect interrupt
+#define EUartUCR1_ADBR (1 << 14) // Auto detect baud rate
+#define EUartUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable
+#define EUartUCR1_IDEN (1 << 12) // Idle condition interrupt
+#define EUartUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable
+#define EUartUCR1_RDMAEN (1 << 8) // Recv ready DMA enable
+#define EUartUCR1_IREN (1 << 7) // Infrared interface enable
+#define EUartUCR1_TXMPTYEN (1 << 6) // Transimitter empty interrupt enable
+#define EUartUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable
+#define EUartUCR1_SNDBRK (1 << 4) // Send break
+#define EUartUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable
+#define EUartUCR1_DOZE (1 << 1) // Doze
+#define EUartUCR1_UARTEN (1 << 0) // UART enabled
+#define EUartUCR2_ESCI (1 << 15) // Escape seq interrupt enable
+#define EUartUCR2_IRTS (1 << 14) // Ignore RTS pin
+#define EUartUCR2_CTSC (1 << 13) // CTS pin control
+#define EUartUCR2_CTS (1 << 12) // Clear to send
+#define EUartUCR2_ESCEN (1 << 11) // Escape enable
+#define EUartUCR2_PREN (1 << 8) // Parity enable
+#define EUartUCR2_PROE (1 << 7) // Parity odd/even
+#define EUartUCR2_STPB (1 << 6) // Stop
+#define EUartUCR2_WS (1 << 5) // Word size
+#define EUartUCR2_RTSEN (1 << 4) // Request to send interrupt enable
+#define EUartUCR2_ATEN (1 << 3) // Aging timer enable
+#define EUartUCR2_TXEN (1 << 2) // Transmitter enabled
+#define EUartUCR2_RXEN (1 << 1) // Receiver enabled
+#define EUartUCR2_SRST_ (1 << 0) // SW reset
+#define EUartUCR3_PARERREN (1 << 12) // Parity enable
+#define EUartUCR3_FRAERREN (1 << 11) // Frame error interrupt enable
+#define EUartUCR3_ADNIMP (1 << 7) // Autobaud detection not improved
+#define EUartUCR3_RXDSEN (1 << 6) // Receive status interrupt enable
+#define EUartUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable
+#define EUartUCR3_AWAKEN (1 << 4) // Async wake interrupt enable
+#define EUartUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected
+#define EUartUCR3_INVT (1 << 1) // Inverted Infrared transmission
+#define EUartUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable
+#define EUartUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars)
+#define EUartUCR4_INVR (1 << 9) // Inverted infrared reception
+#define EUartUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable
+#define EUartUCR4_WKEN (1 << 7) // Wake interrupt enable
+#define EUartUCR4_IRSC (1 << 5) // IR special case
+#define EUartUCR4_LPBYP (1 << 4) // Low power bypass
+#define EUartUCR4_TCEN (1 << 3) // Transmit complete interrupt enable
+#define EUartUCR4_BKEN (1 << 2) // Break condition interrupt enable
+#define EUartUCR4_OREN (1 << 1) // Receiver overrun interrupt enable
+#define EUartUCR4_DREN (1 << 0) // Recv data ready interrupt enable
+#define EUartUFCR_RXTL_SHF 0 // Receiver trigger level shift
+#define EUartUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div 1)
+#define EUartUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div 2)
+#define EUartUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3)
+#define EUartUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4)
+#define EUartUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5)
+#define EUartUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6)
+#define EUartUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7)
+#define EUartUFCR_TXTL_SHF 10 // Transmitter trigger level shift
+#define EUartUSR1_PARITYERR (1 << 15) // Parity error interrupt flag
+#define EUartUSR1_RTSS (1 << 14) // RTS pin status
+#define EUartUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag
+#define EUartUSR1_RTSD (1 << 12) // RTS delta
+#define EUartUSR1_ESCF (1 << 11) // Escape seq interrupt flag
+#define EUartUSR1_FRAMERR (1 << 10) // Frame error interrupt flag
+#define EUartUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag
+#define EUartUSR1_AGTIM (1 << 8) // Aging timeout interrupt status
+#define EUartUSR1_RXDS (1 << 6) // Receiver idle interrupt flag
+#define EUartUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag
+#define EUartUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag
+#define EUartUSR2_ADET (1 << 15) // Auto baud rate detect complete
+#define EUartUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty
+#define EUartUSR2_IDLE (1 << 12) // Idle condition
+#define EUartUSR2_ACST (1 << 11) // Autobaud counter stopped
+#define EUartUSR2_IRINT (1 << 8) // Serial infrared interrupt flag
+#define EUartUSR2_WAKE (1 << 7) // Wake
+#define EUartUSR2_RTSF (1 << 4) // RTS edge interrupt flag
+#define EUartUSR2_TXDC (1 << 3) // Transmitter complete
+#define EUartUSR2_BRCD (1 << 2) // Break condition
+#define EUartUSR2_ORE (1 << 1) // Overrun error
+#define EUartUSR2_RDR (1 << 0) // Recv data ready
+#define EUartUTS_FRCPERR (1 << 13) // Force parity error
+#define EUartUTS_LOOP (1 << 12) // Loop tx and rx
+#define EUartUTS_TXEMPTY (1 << 6) // TxFIFO empty
+#define EUartUTS_RXEMPTY (1 << 5) // RxFIFO empty
+#define EUartUTS_TXFULL (1 << 4) // TxFIFO full
+#define EUartUTS_RXFULL (1 << 3) // RxFIFO full
+#define EUartUTS_SOFTRST (1 << 0) // Software reset
+
+#define EUartUFCR_RFDIV EUartUFCR_RFDIV_1
#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_1)
-#define MXC_UART_REFFREQ (get_peri_clock(PER_UART_CLK) / 1)
+#define MXC_UART_REFFREQ (get_peri_clock(PER_UART_CLK) / 1)
#endif
#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_2)
-#define MXC_UART_REFFREQ (get_peri_clock(PER_UART_CLK) / 2)
+#define MXC_UART_REFFREQ (get_peri_clock(PER_UART_CLK) / 2)
#endif
#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_4)
-#define MXC_UART_REFFREQ (get_peri_clock(PER_UART_CLK) / 4)
+#define MXC_UART_REFFREQ (get_peri_clock(PER_UART_CLK) / 4)
+#endif
+
+/* The Freescale 3Stack board has two external UART ports which are mapped first
+ * for whatever strange reason.
+ * Other manufacturers may not have these UARTS on their boards but would
+ * as well like to have their serial ports start at '0'!
+ */
+#ifdef CYGPKG_HAL_ARM_MX25_3STACK
+#define MXC_UART_CHAN_OFFSET 2
+#else
+#define MXC_UART_CHAN_OFFSET 0
#endif
#if 0
void
cyg_hal_plf_comms_init(void)
{
- static int initialized = 0;
+ static int initialized = 0;
- if (initialized)
- return;
+ if (initialized)
+ return;
- initialized = 1;
+ initialized = 1;
- cyg_hal_plf_serial_init();
+ cyg_hal_plf_serial_init();
}
#endif
//=============================================================================
#ifdef UART_WIDTH_32
struct mxc_serial {
- volatile cyg_uint32 urxd[16];
- volatile cyg_uint32 utxd[16];
- volatile cyg_uint32 ucr1;
- volatile cyg_uint32 ucr2;
- volatile cyg_uint32 ucr3;
- volatile cyg_uint32 ucr4;
- volatile cyg_uint32 ufcr;
- volatile cyg_uint32 usr1;
- volatile cyg_uint32 usr2;
- volatile cyg_uint32 uesc;
- volatile cyg_uint32 utim;
- volatile cyg_uint32 ubir;
- volatile cyg_uint32 ubmr;
- volatile cyg_uint32 ubrc;
- volatile cyg_uint32 onems;
- volatile cyg_uint32 uts;
+ volatile cyg_uint32 urxd[16];
+ volatile cyg_uint32 utxd[16];
+ volatile cyg_uint32 ucr1;
+ volatile cyg_uint32 ucr2;
+ volatile cyg_uint32 ucr3;
+ volatile cyg_uint32 ucr4;
+ volatile cyg_uint32 ufcr;
+ volatile cyg_uint32 usr1;
+ volatile cyg_uint32 usr2;
+ volatile cyg_uint32 uesc;
+ volatile cyg_uint32 utim;
+ volatile cyg_uint32 ubir;
+ volatile cyg_uint32 ubmr;
+ volatile cyg_uint32 ubrc;
+ volatile cyg_uint32 onems;
+ volatile cyg_uint32 uts;
};
#else
struct mxc_serial {
- volatile cyg_uint16 urxd[1];
- volatile cyg_uint16 resv0[31];
-
- volatile cyg_uint16 utxd[1];
- volatile cyg_uint16 resv1[31];
- volatile cyg_uint16 ucr1;
- volatile cyg_uint16 resv2;
- volatile cyg_uint16 ucr2;
- volatile cyg_uint16 resv3;
- volatile cyg_uint16 ucr3;
- volatile cyg_uint16 resv4;
- volatile cyg_uint16 ucr4;
- volatile cyg_uint16 resv5;
- volatile cyg_uint16 ufcr;
- volatile cyg_uint16 resv6;
- volatile cyg_uint16 usr1;
- volatile cyg_uint16 resv7;
- volatile cyg_uint16 usr2;
- volatile cyg_uint16 resv8;
- volatile cyg_uint16 uesc;
- volatile cyg_uint16 resv9;
- volatile cyg_uint16 utim;
- volatile cyg_uint16 resv10;
- volatile cyg_uint16 ubir;
- volatile cyg_uint16 resv11;
- volatile cyg_uint16 ubmr;
- volatile cyg_uint16 resv12;
- volatile cyg_uint16 ubrc;
- volatile cyg_uint16 resv13;
- volatile cyg_uint16 onems;
- volatile cyg_uint16 resv14;
- volatile cyg_uint16 uts;
- volatile cyg_uint16 resv15;
+ volatile cyg_uint16 urxd[1];
+ volatile cyg_uint16 resv0[31];
+
+ volatile cyg_uint16 utxd[1];
+ volatile cyg_uint16 resv1[31];
+ volatile cyg_uint16 ucr1;
+ volatile cyg_uint16 resv2;
+ volatile cyg_uint16 ucr2;
+ volatile cyg_uint16 resv3;
+ volatile cyg_uint16 ucr3;
+ volatile cyg_uint16 resv4;
+ volatile cyg_uint16 ucr4;
+ volatile cyg_uint16 resv5;
+ volatile cyg_uint16 ufcr;
+ volatile cyg_uint16 resv6;
+ volatile cyg_uint16 usr1;
+ volatile cyg_uint16 resv7;
+ volatile cyg_uint16 usr2;
+ volatile cyg_uint16 resv8;
+ volatile cyg_uint16 uesc;
+ volatile cyg_uint16 resv9;
+ volatile cyg_uint16 utim;
+ volatile cyg_uint16 resv10;
+ volatile cyg_uint16 ubir;
+ volatile cyg_uint16 resv11;
+ volatile cyg_uint16 ubmr;
+ volatile cyg_uint16 resv12;
+ volatile cyg_uint16 ubrc;
+ volatile cyg_uint16 resv13;
+ volatile cyg_uint16 onems;
+ volatile cyg_uint16 resv14;
+ volatile cyg_uint16 uts;
+ volatile cyg_uint16 resv15;
};
#endif
typedef struct {
- volatile struct mxc_serial* base;
- cyg_int32 msec_timeout;
- int isr_vector;
- int baud_rate;
+ volatile struct mxc_serial *base;
+ cyg_int32 msec_timeout;
+ int isr_vector;
+ int baud_rate;
} channel_data_t;
static channel_data_t channels[] = {
#if CYGHWR_HAL_ARM_SOC_UART1 != 0
- {(volatile struct mxc_serial*)UART1_BASE_ADDR, 1000,
- CYGNUM_HAL_INTERRUPT_UART1, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+ {(volatile struct mxc_serial*)UART1_BASE_ADDR, 1000,
+ CYGNUM_HAL_INTERRUPT_UART1, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
#endif
#if CYGHWR_HAL_ARM_SOC_UART2 != 0
- {(volatile struct mxc_serial*)UART2_BASE_ADDR, 1000,
- CYGNUM_HAL_INTERRUPT_UART2, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+ {(volatile struct mxc_serial*)UART2_BASE_ADDR, 1000,
+ CYGNUM_HAL_INTERRUPT_UART2, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
#endif
#if CYGHWR_HAL_ARM_SOC_UART3 != 0
- {(volatile struct mxc_serial*)UART3_BASE_ADDR, 1000,
- CYGNUM_HAL_INTERRUPT_UART3, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+ {(volatile struct mxc_serial*)UART3_BASE_ADDR, 1000,
+ CYGNUM_HAL_INTERRUPT_UART3, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
#endif
};
/*---------------------------------------------------------------------------*/
-static void init_serial_channel(channel_data_t* __ch_data)
+static void init_serial_channel(channel_data_t *__ch_data)
{
- volatile struct mxc_serial* base = __ch_data->base;
-
- /* Wait for UART to finish transmitting */
- while (!(base->uts & EUartUTS_TXEMPTY));
-
- /* Disable UART */
- base->ucr1 &= ~EUartUCR1_UARTEN;
-
- /* Set to default POR state */
- base->ucr1 = 0x00000000;
- base->ucr2 = 0x00000000;
-
- while (!(base->ucr2 & EUartUCR2_SRST_));
-
- base->ucr3 = 0x00000704;
- base->ucr4 = 0x00008000;
- base->ufcr = 0x00000801;
- base->uesc = 0x0000002B;
- base->utim = 0x00000000;
- base->ubir = 0x00000000;
- base->ubmr = 0x00000000;
- base->onems = 0x00000000;
- base->uts = 0x00000000;
-
- /* Configure FIFOs */
- base->ufcr = (1 << EUartUFCR_RXTL_SHF) | EUartUFCR_RFDIV
- | (2 << EUartUFCR_TXTL_SHF);
-
- /* Setup One MS timer */
- base->onems = (MXC_UART_REFFREQ / 1000);
-
- /* Set to 8N1 */
- base->ucr2 &= ~EUartUCR2_PREN;
- base->ucr2 |= EUartUCR2_WS;
- base->ucr2 &= ~EUartUCR2_STPB;
-
- /* Ignore RTS */
- base->ucr2 |= EUartUCR2_IRTS;
-
- /* Enable UART */
- base->ucr1 |= EUartUCR1_UARTEN;
-
- /* Enable FIFOs */
- base->ucr2 |= EUartUCR2_SRST_ | EUartUCR2_RXEN | EUartUCR2_TXEN;
-
- /* Clear status flags */
- base->usr2 |= EUartUSR2_ADET |
- EUartUSR2_IDLE |
- EUartUSR2_IRINT |
- EUartUSR2_WAKE |
- EUartUSR2_RTSF |
- EUartUSR2_BRCD |
- EUartUSR2_ORE |
- EUartUSR2_RDR;
-
- /* Clear status flags */
- base->usr1 |= EUartUSR1_PARITYERR |
- EUartUSR1_RTSD |
- EUartUSR1_ESCF |
- EUartUSR1_FRAMERR |
- EUartUSR1_AIRINT |
- EUartUSR1_AWAKE;
-
- /* Set the numerator value minus one of the BRM ratio */
- base->ubir = (__ch_data->baud_rate / 100) - 1;
-
- /* Set the denominator value minus one of the BRM ratio */
- base->ubmr = ((MXC_UART_REFFREQ / 1600) - 1);
-
+ volatile struct mxc_serial *base = __ch_data->base;
+
+ /* Wait for UART to finish transmitting */
+ while (!(base->uts & EUartUTS_TXEMPTY));
+
+ /* Disable UART */
+ base->ucr1 &= ~EUartUCR1_UARTEN;
+
+ /* Set to default POR state */
+ base->ucr1 = 0x00000000;
+ base->ucr2 = 0x00000000;
+
+ while (!(base->ucr2 & EUartUCR2_SRST_));
+
+ base->ucr3 = 0x00000704;
+ base->ucr4 = 0x00008000;
+ base->ufcr = 0x00000801;
+ base->uesc = 0x0000002B;
+ base->utim = 0x00000000;
+ base->ubir = 0x00000000;
+ base->ubmr = 0x00000000;
+ base->onems = 0x00000000;
+ base->uts = 0x00000000;
+
+ /* Configure FIFOs */
+ base->ufcr = (1 << EUartUFCR_RXTL_SHF) | EUartUFCR_RFDIV |
+ (2 << EUartUFCR_TXTL_SHF);
+
+ /* Setup One MS timer */
+ base->onems = MXC_UART_REFFREQ / 1000;
+
+ /* Set to 8N1 */
+ base->ucr2 &= ~EUartUCR2_PREN;
+ base->ucr2 |= EUartUCR2_WS;
+ base->ucr2 &= ~EUartUCR2_STPB;
+
+ /* Ignore RTS */
+ base->ucr2 |= EUartUCR2_IRTS;
+
+ /* Enable UART */
+ base->ucr1 |= EUartUCR1_UARTEN;
+
+ /* Enable FIFOs */
+ base->ucr2 |= EUartUCR2_SRST_ | EUartUCR2_RXEN | EUartUCR2_TXEN;
+
+ /* Clear status flags */
+ base->usr2 |= EUartUSR2_ADET |
+ EUartUSR2_IDLE |
+ EUartUSR2_IRINT |
+ EUartUSR2_WAKE |
+ EUartUSR2_RTSF |
+ EUartUSR2_BRCD |
+ EUartUSR2_ORE |
+ EUartUSR2_RDR;
+
+ /* Clear status flags */
+ base->usr1 |= EUartUSR1_PARITYERR |
+ EUartUSR1_RTSD |
+ EUartUSR1_ESCF |
+ EUartUSR1_FRAMERR |
+ EUartUSR1_AIRINT |
+ EUartUSR1_AWAKE;
+
+ /* Set the numerator value minus one of the BRM ratio */
+ base->ubir = (__ch_data->baud_rate / 100) - 1;
+
+ /* Set the denominator value minus one of the BRM ratio */
+ base->ubmr = (MXC_UART_REFFREQ / 1600) - 1;
}
-static void stop_serial_channel(channel_data_t* __ch_data)
+static void stop_serial_channel(channel_data_t *__ch_data)
{
- volatile struct mxc_serial* base = __ch_data->base;
+ volatile struct mxc_serial *base = __ch_data->base;
- /* Wait for UART to finish transmitting */
- while (!(base->uts & EUartUTS_TXEMPTY));
+ /* Wait for UART to finish transmitting */
+ while (!(base->uts & EUartUTS_TXEMPTY));
- /* Disable UART */
- base->ucr1 &= ~EUartUCR1_UARTEN;
+ /* Disable UART */
+ base->ucr1 &= ~EUartUCR1_UARTEN;
}
//#define debug_uart_log_buf
void cyg_hal_plf_serial_putc(void *__ch_data, char c)
{
- volatile struct mxc_serial* base = ((channel_data_t*)__ch_data)->base;
-
+ channel_data_t *chan = __ch_data;
+ volatile struct mxc_serial *base = chan->base;
#ifdef debug_uart_log_buf
- __log_buf[diag_bp++] = c;
+ __log_buf[diag_bp++] = c;
#endif
- CYGARC_HAL_SAVE_GP();
+ CYGARC_HAL_SAVE_GP();
- // Wait for Tx FIFO not full
- while (base->uts & EUartUTS_TXFULL)
- ;
- base->utxd[0] = c;
+ // Wait for Tx FIFO not full
+ while (base->uts & EUartUTS_TXFULL)
+ ;
+ base->utxd[0] = c;
- CYGARC_HAL_RESTORE_GP();
+ CYGARC_HAL_RESTORE_GP();
}
-static cyg_bool cyg_hal_plf_serial_getc_nonblock(void* __ch_data,
- cyg_uint8* ch)
+static cyg_bool cyg_hal_plf_serial_getc_nonblock(void *__ch_data,
+ cyg_uint8 *ch)
{
- volatile struct mxc_serial* base = ((channel_data_t*)__ch_data)->base;
+ channel_data_t *chan = __ch_data;
+ volatile struct mxc_serial *base = chan->base;
- // If receive fifo is empty, return false
- if (base->uts & EUartUTS_RXEMPTY)
- return false;
+ // If receive fifo is empty, return false
+ if (base->uts & EUartUTS_RXEMPTY)
+ return false;
- *ch = (char)base->urxd[0];
+ *ch = (char)base->urxd[0];
- return true;
+ return true;
}
-cyg_uint8 cyg_hal_plf_serial_getc(void* __ch_data)
+cyg_uint8 cyg_hal_plf_serial_getc(void *__ch_data)
{
- cyg_uint8 ch;
- CYGARC_HAL_SAVE_GP();
+ cyg_uint8 ch;
+ CYGARC_HAL_SAVE_GP();
- while (!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
+ while (!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
- CYGARC_HAL_RESTORE_GP();
- return ch;
+ CYGARC_HAL_RESTORE_GP();
+ return ch;
}
-static void cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
- cyg_uint32 __len)
+static void cyg_hal_plf_serial_write(void *__ch_data, const cyg_uint8 *__buf,
+ cyg_uint32 __len)
{
- CYGARC_HAL_SAVE_GP();
+ CYGARC_HAL_SAVE_GP();
- while(__len-- > 0)
- cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+ while (__len-- > 0)
+ cyg_hal_plf_serial_putc(__ch_data, *__buf++);
- CYGARC_HAL_RESTORE_GP();
+ CYGARC_HAL_RESTORE_GP();
}
-static void cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf,
- cyg_uint32 __len)
+static void cyg_hal_plf_serial_read(void *__ch_data, cyg_uint8 *__buf,
+ cyg_uint32 __len)
{
- CYGARC_HAL_SAVE_GP();
+ CYGARC_HAL_SAVE_GP();
- while (__len-- > 0)
- *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+ while (__len-- > 0)
+ *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
- CYGARC_HAL_RESTORE_GP();
+ CYGARC_HAL_RESTORE_GP();
}
-cyg_bool cyg_hal_plf_serial_getc_timeout(void* __ch_data,
- cyg_uint8* ch)
+cyg_bool cyg_hal_plf_serial_getc_timeout(void *__ch_data,
+ cyg_uint8 *ch)
{
- int delay_count;
- channel_data_t* chan = (channel_data_t*)__ch_data;
- cyg_bool res;
- CYGARC_HAL_SAVE_GP();
+ int delay_count;
+ channel_data_t *chan = __ch_data;
+ cyg_bool res;
+ CYGARC_HAL_SAVE_GP();
- delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+ delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
- for(;;) {
- res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
- if (res || 0 == delay_count--)
- break;
+ for (;;) {
+ res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
+ if (res || 0 == delay_count--)
+ break;
- CYGACC_CALL_IF_DELAY_US(100);
- }
+ CYGACC_CALL_IF_DELAY_US(100);
+ }
- CYGARC_HAL_RESTORE_GP();
- return res;
+ CYGARC_HAL_RESTORE_GP();
+ return res;
}
static int cyg_hal_plf_serial_control(void *__ch_data,
- __comm_control_cmd_t __func, ...)
+ __comm_control_cmd_t __func, ...)
{
- static int irq_state = 0;
- channel_data_t* chan = (channel_data_t*)__ch_data;
- int ret = -1;
- va_list ap;
-
- CYGARC_HAL_SAVE_GP();
- va_start(ap, __func);
-
- switch (__func) {
- case __COMMCTL_GETBAUD:
- ret = chan->baud_rate;
- break;
- case __COMMCTL_SETBAUD:
- chan->baud_rate = va_arg(ap, cyg_int32);
- // Should we verify this value here?
- init_serial_channel(chan);
- ret = 0;
- break;
- case __COMMCTL_IRQ_ENABLE:
- irq_state = 1;
-
- chan->base->ucr1 |= EUartUCR1_RRDYEN;
-
- HAL_INTERRUPT_UNMASK(chan->isr_vector);
- break;
- case __COMMCTL_IRQ_DISABLE:
- ret = irq_state;
- irq_state = 0;
-
- chan->base->ucr1 &= ~EUartUCR1_RRDYEN;
-
- HAL_INTERRUPT_MASK(chan->isr_vector);
- break;
- case __COMMCTL_DBG_ISR_VECTOR:
- ret = chan->isr_vector;
- break;
- case __COMMCTL_SET_TIMEOUT:
- ret = chan->msec_timeout;
- chan->msec_timeout = va_arg(ap, cyg_uint32);
- break;
- default:
- break;
- }
- va_end(ap);
- CYGARC_HAL_RESTORE_GP();
- return ret;
+ static int irq_state = 0;
+ channel_data_t *chan = __ch_data;
+ int ret = -1;
+ va_list ap;
+
+ CYGARC_HAL_SAVE_GP();
+ va_start(ap, __func);
+
+ switch (__func) {
+ case __COMMCTL_GETBAUD:
+ ret = chan->baud_rate;
+ break;
+ case __COMMCTL_SETBAUD:
+ chan->baud_rate = va_arg(ap, cyg_int32);
+ // Should we verify this value here?
+ init_serial_channel(chan);
+ ret = 0;
+ break;
+ case __COMMCTL_IRQ_ENABLE:
+ irq_state = 1;
+
+ chan->base->ucr1 |= EUartUCR1_RRDYEN;
+
+ HAL_INTERRUPT_UNMASK(chan->isr_vector);
+ break;
+ case __COMMCTL_IRQ_DISABLE:
+ ret = irq_state;
+ irq_state = 0;
+
+ chan->base->ucr1 &= ~EUartUCR1_RRDYEN;
+
+ HAL_INTERRUPT_MASK(chan->isr_vector);
+ break;
+ case __COMMCTL_DBG_ISR_VECTOR:
+ ret = chan->isr_vector;
+ break;
+ case __COMMCTL_SET_TIMEOUT:
+ ret = chan->msec_timeout;
+ chan->msec_timeout = va_arg(ap, cyg_uint32);
+ break;
+ default:
+ break;
+ }
+ va_end(ap);
+ CYGARC_HAL_RESTORE_GP();
+ return ret;
}
-static int cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
- CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+static int cyg_hal_plf_serial_isr(void *__ch_data, int *__ctrlc,
+ CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
- int res = 0;
- channel_data_t* chan = (channel_data_t*)__ch_data;
- char c;
+ int res = 0;
+ channel_data_t *chan = __ch_data;
+ char c;
- CYGARC_HAL_SAVE_GP();
+ CYGARC_HAL_SAVE_GP();
- cyg_drv_interrupt_acknowledge(chan->isr_vector);
+ cyg_drv_interrupt_acknowledge(chan->isr_vector);
- *__ctrlc = 0;
- if (!(chan->base->uts & EUartUTS_RXEMPTY)) {
- c = (char)chan->base->urxd[0];
+ *__ctrlc = 0;
+ if (!(chan->base->uts & EUartUTS_RXEMPTY)) {
+ c = (char)chan->base->urxd[0];
- if (cyg_hal_is_break( &c , 1 ))
- *__ctrlc = 1;
+ if (cyg_hal_is_break(&c, 1))
+ *__ctrlc = 1;
- res = CYG_ISR_HANDLED;
- }
+ res = CYG_ISR_HANDLED;
+ }
- CYGARC_HAL_RESTORE_GP();
- return res;
+ CYGARC_HAL_RESTORE_GP();
+ return res;
}
+#define NUMOF(x) (sizeof(x) / sizeof(x[0]))
+
void cyg_hal_plf_serial_init(void)
{
- hal_virtual_comm_table_t* comm;
- int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
- int i;
- static int jjj = 0;
-
- // Init channels
-#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
- for (i = 0; i < NUMOF(channels); i++) {
- init_serial_channel(&channels[i]);
- CYGACC_CALL_IF_SET_CONSOLE_COMM(i+2);
- comm = CYGACC_CALL_IF_CONSOLE_PROCS();
- CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
- CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
- CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
- CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
- CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
- CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
- CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
- CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
- if (jjj == 0) {
- cyg_hal_plf_serial_putc(&channels[i], '+');
- jjj++;
- }
- cyg_hal_plf_serial_putc(&channels[i], '+');
- }
-
- // Restore original console
- CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+ hal_virtual_comm_table_t *comm;
+ int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ int i;
+ static int jjj = 0;
+
+ // Init channels
+ for (i = 0; i < NUMOF(channels); i++) {
+ init_serial_channel(&channels[i]);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(i + MXC_UART_CHAN_OFFSET);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+ if (jjj == 0) {
+ cyg_hal_plf_serial_putc(&channels[i], '+');
+ jjj++;
+ }
+ }
+
+ // Restore original console
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
void cyg_hal_plf_serial_stop(void)
{
- int i;
+ int i;
- // Init channels
-#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
- for (i = 0; i < NUMOF(channels); i++) {
- stop_serial_channel(&channels[i]);
- }
+ // Init channels
+ for (i = 0; i < NUMOF(channels); i++) {
+ stop_serial_channel(&channels[i]);
+ }
}
//=============================================================================
#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
-#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
+#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
+
+#define MXC_UART1_CHAN (0 + MXC_UART_CHAN_OFFSET)
+#define MXC_UART2_CHAN (1 + MXC_UART_CHAN_OFFSET)
+#define MXC_UART3_CHAN (2 + MXC_UART_CHAN_OFFSET)
+#define MXC_UART4_CHAN (3 + MXC_UART_CHAN_OFFSET)
+#define MXC_UART5_CHAN (4 + MXC_UART_CHAN_OFFSET)
+#define MXC_UART6_CHAN (5 + MXC_UART_CHAN_OFFSET)
+
+#undef __BASE
-#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 2)
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART1_CHAN)
#define __BASE ((void*)UART1_BASE_ADDR)
#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART1
-#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 3)
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART2_CHAN)
#define __BASE ((void*)UART2_BASE_ADDR)
#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART2
-#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 4)
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART3_CHAN)
#define __BASE ((void*)UART3_BASE_ADDR)
#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART3
-#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 5)
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART4_CHAN)
#define __BASE ((void*)UART4_BASE_ADDR)
#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART4
-#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 6)
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART5_CHAN)
#define __BASE ((void*)UART5_BASE_ADDR)
#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART5
#endif
#endif
static channel_data_t channel = {
- (volatile struct mxc_serial*)__BASE, 0, CYGHWR_HAL_GDB_PORT_VECTOR
+ __BASE, 0, CYGHWR_HAL_GDB_PORT_VECTOR
};
#ifdef HAL_DIAG_USES_HARDWARE
void hal_diag_init(void)
{
- static int init = 0;
- char *msg = "\n\rARM eCos\n\r";
- cyg_uint8 lcr;
+ static int init = 0;
+ char *msg = "\n\rARM eCos\n\r";
- if (init++) return;
+ if (init++) return;
- init_serial_channel(&channel);
+ init_serial_channel(&channel);
- while (*msg) hal_diag_write_char(*msg++);
+ while (*msg) hal_diag_write_char(*msg++);
}
#ifdef DEBUG_DIAG
{
#ifdef DEBUG_DIAG
#ifndef CYG_HAL_STARTUP_ROM
- diag_buffer[diag_bp++] = c;
- if (diag_bp == sizeof(diag_buffer)) diag_bp = 0;
+ diag_buffer[diag_bp++] = c;
+ if (diag_bp == sizeof(diag_buffer)) diag_bp = 0;
#endif
#endif
- cyg_hal_plf_serial_putc(&channel, c);
+ cyg_hal_plf_serial_putc(&channel, c);
}
void hal_diag_read_char(char *c)
{
- *c = cyg_hal_plf_serial_getc(&channel);
+ *c = cyg_hal_plf_serial_getc(&channel);
}
#else // not HAL_DIAG_USES_HARDWARE - it uses GDB protocol
void hal_diag_read_char(char *c)
{
- *c = cyg_hal_plf_serial_getc(&channel);
+ *c = cyg_hal_plf_serial_getc(&channel);
}
void hal_diag_write_char(char c)
{
- static char line[100];
- static int pos = 0;
+ static char line[100];
+ static int pos = 0;
- // FIXME: Some LED blinking might be nice right here.
+ // FIXME: Some LED blinking might be nice right here.
- // No need to send CRs
- if( c == '\r' ) return;
+ // No need to send CRs
+ if (c == '\r') return;
- line[pos++] = c;
+ line[pos++] = c;
- if (c == '\n' || pos == sizeof(line)) {
- CYG_INTERRUPT_STATE old;
-
- // Disable interrupts. This prevents GDB trying to interrupt us
- // while we are in the middle of sending a packet. The serial
- // receive interrupt will be seen when we re-enable interrupts
- // later.
+ if (c == '\n' || pos == sizeof(line)) {
+ CYG_INTERRUPT_STATE old;
+ // Disable interrupts. This prevents GDB trying to interrupt us
+ // while we are in the middle of sending a packet. The serial
+ // receive interrupt will be seen when we re-enable interrupts
+ // later.
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
- CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+ CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
#else
- HAL_DISABLE_INTERRUPTS(old);
+ HAL_DISABLE_INTERRUPTS(old);
#endif
-
- while (1) {
- static char hex[] = "0123456789ABCDEF";
- cyg_uint8 csum = 0;
- int i;
+ while (1) {
+ static char hex[] = "0123456789ABCDEF";
+ cyg_uint8 csum = 0;
+ int i;
#ifndef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
- char c1;
+ char c1;
#endif
- cyg_hal_plf_serial_putc(&channel, '$');
- cyg_hal_plf_serial_putc(&channel, 'O');
- csum += 'O';
- for(i = 0; i < pos; i++) {
- char ch = line[i];
- char h = hex[(ch>>4)&0xF];
- char l = hex[ch&0xF];
- cyg_hal_plf_serial_putc(&channel, h);
- cyg_hal_plf_serial_putc(&channel, l);
- csum += h;
- csum += l;
- }
- cyg_hal_plf_serial_putc(&channel, '#');
- cyg_hal_plf_serial_putc(&channel, hex[(csum>>4)&0xF]);
- cyg_hal_plf_serial_putc(&channel, hex[csum&0xF]);
+ cyg_hal_plf_serial_putc(&channel, '$');
+ cyg_hal_plf_serial_putc(&channel, 'O');
+ csum += 'O';
+ for (i = 0; i < pos; i++) {
+ char ch = line[i];
+ char h = hex[(ch >> 4) & 0xF];
+ char l = hex[ch & 0xF];
+ cyg_hal_plf_serial_putc(&channel, h);
+ cyg_hal_plf_serial_putc(&channel, l);
+ csum += h;
+ csum += l;
+ }
+ cyg_hal_plf_serial_putc(&channel, '#');
+ cyg_hal_plf_serial_putc(&channel, hex[(csum >> 4) & 0xF]);
+ cyg_hal_plf_serial_putc(&channel, hex[csum & 0xF]);
#ifdef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
- break; // regardless
+ break; // regardless
#else // not CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT Ie. usually...
- // Wait for the ACK character '+' from GDB here and handle
- // receiving a ^C instead. This is the reason for this clause
- // being a loop.
- c1 = cyg_hal_plf_serial_getc(&channel);
+ // Wait for the ACK character '+' from GDB here and handle
+ // receiving a ^C instead. This is the reason for this clause
+ // being a loop.
+ c1 = cyg_hal_plf_serial_getc(&channel);
- if( c1 == '+' )
- break; // a good acknowledge
+ if (c1 == '+')
+ break; // a good acknowledge
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
- cyg_drv_interrupt_acknowledge(CYGHWR_HAL_GDB_PORT_VECTOR);
- if( c1 == 3 ) {
- // Ctrl-C: breakpoint.
- cyg_hal_gdb_interrupt(
- (target_register_t)__builtin_return_address(0) );
- break;
- }
+ cyg_drv_interrupt_acknowledge(CYGHWR_HAL_GDB_PORT_VECTOR);
+ if (c1 == '\003') {
+ // Ctrl-C: breakpoint.
+ cyg_hal_gdb_interrupt((target_register_t)__builtin_return_address(0));
+ break;
+ }
#endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
#endif // ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
- // otherwise, loop round again
- }
+ // otherwise, loop round again
+ }
- pos = 0;
+ pos = 0;
- // And re-enable interrupts
+ // And re-enable interrupts
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
- CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+ CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
#else
- HAL_RESTORE_INTERRUPTS(old);
+ HAL_RESTORE_INTERRUPTS(old);
#endif
-
- }
+ }
}
#endif
#include <cyg/hal/hal_mm.h> // MMap table definitions
#include <cyg/infra/diag.h> // diag_printf
+#include <cyg/io/imx_nfc.h>
// Most initialization has already been done before we get here.
// All we do here is set up the interrupt environment.
#define IIM_SREV_REV_SH 4
#define IIM_SREV_REV_LEN 4
-#define PROD_SIGNATURE_MX25 0x1
+#define PROD_SIGNATURE_MX25 0x1F
#define PROD_SIGNATURE_SUPPORTED_1 PROD_SIGNATURE_MX25
#define CHIP_VERSION_NONE 0xFFFFFFFF // invalid product ID
#define CHIP_VERSION_UNKNOWN 0xDEADBEEF // invalid chip rev
-#define PART_NUMBER_OFFSET (12)
-#define MAJOR_NUMBER_OFFSET (4)
-#define MINOR_NUMBER_OFFSET (0)
+#define PART_NUMBER_OFFSET 12
+#define MAJOR_NUMBER_OFFSET 4
+#define MINOR_NUMBER_OFFSET 0
/*
* System_rev will have the following format
*/
unsigned int system_rev = CHIP_REV_1_0;
static int find_correct_chip;
-extern char HAL_PLATFORM_EXTRA[55];
/*
* This functions reads the IIM module and returns the system revision number.
val = readl(IIM_BASE_ADDR + IIM_PREV_OFF);
system_rev = 0x25 << PART_NUMBER_OFFSET; /* For MX25 Platform*/
- /* If the IIM doesn't contain valid product signature, return
+ /* If the IIM doesn't contain a valid product signature, return
* the lowest revision number */
if ((MXC_GET_FIELD(val, IIM_PROD_REV_LEN, IIM_PROD_REV_SH) !=
PROD_SIGNATURE_SUPPORTED_1)) {
+#if 0
return CHIP_VERSION_NONE;
+#endif
}
/* Now trying to retrieve the silicon rev from IIM's SREV register */
ver = read_system_rev();
find_correct_chip = ver;
+ if (ver != CHIP_VERSION_NONE) {
+ /* Valid product revision found. Check actual silicon rev from the ROM code. */
+ if (ver == 0x0) {
+ HAL_PLATFORM_EXTRA[5] = '1';
+ HAL_PLATFORM_EXTRA[7] = '0';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ } else if (ver == 0x1) {
+ HAL_PLATFORM_EXTRA[5] = '1';
+ HAL_PLATFORM_EXTRA[7] = '1';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 1 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ } else {
+ HAL_PLATFORM_EXTRA[5] = 'z';
+ HAL_PLATFORM_EXTRA[7] = 'z';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ find_correct_chip = CHIP_VERSION_UNKNOWN;
+ }
+ }
+
// Mask all interrupts
writel(0xFFFFFFFF, ASIC_NIMASK);
unsigned int hal_timer_count(void)
{
- return (0xFFFFFFFF - readl(EPIT_BASE_ADDR + EPITCNR));
+ return 0 - readl(EPIT_BASE_ADDR + EPITCNR);
}
#define WDT_MAGIC_1 0x5555
static unsigned int led_on = 0;
//
-// Delay for some number of micro-seconds
+// Delay for some number of microseconds
//
void hal_delay_us(unsigned int usecs)
{
* unsigned int delayCount = (usecs * 32000) / 1000000;
* So use the following one instead
*/
- unsigned int delayCount = (usecs*4 + 124) / 125;
+ unsigned int delayCount = (usecs * 512) / 16000;
if (delayCount == 0) {
return;
// Interrupt priorities are not configurable.
}
-unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz, unsigned int is_mlc, unsigned int num_of_chips)
+unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz, unsigned int is_mlc,
+ unsigned int num_of_chips)
{
unsigned int tmp ;
if (is_mlc) {
tmp = readw(NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF) | (1 << 8);
} else {
- tmp = readw(NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF) & (~(1 << 8));
+ tmp = readw(NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF) & ~(1 << 8);
}
writew(tmp, NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF);
if (io_sz == 16) {
tmp |= (1 << 14);
} else {
- tmp &= (~(1 << 14));
+ tmp &= ~(1 << 14);
}
tmp &= ~(3<<8);
- switch(pg_sz = 2048){
+ switch (pg_sz) {
case 2048:
- tmp |= (1<<8);
- break;
+ tmp |= (1<<8);
+ break;
case 4096:
- tmp |= (1<<9);
- break;
+ tmp |= (1<<9);
+ break;
}
writel(tmp, CCM_BASE_ADDR + CLKCTL_RCSR);
- diag_printf("NAND: RCSR=%x\n", tmp);
- return 0x10;
+ return MXC_NFC_V1_1;
}
+#define WDOG_WRSR ((CYG_WORD16 *)(WDOG_BASE_ADDR + 0x4))
+#define CRM_RCSR ((CYG_WORD32 *)(CCM_BASE_ADDR + 0x28))
+
static void check_reset_source(void)
{
+#if 1
+ char *reset_cause = "UNKNOWN";
+ CYG_WORD16 wrsr;
+ CYG_WORD32 rcsr;
+
+ HAL_READ_UINT32(CRM_RCSR, rcsr);
+ HAL_READ_UINT16(WDOG_WRSR, wrsr);
+ rcsr &= 0x0f;
+ if (rcsr == 0) {
+ reset_cause = "POWER_ON RESET";
+ } else if (rcsr == 1) {
+ reset_cause = "EXTERNAL RESET";
+ } else if (rcsr & (1 << 3)) {
+ reset_cause = "JTAG RESET";
+ } else if (rcsr & (1 << 2)) {
+ reset_cause = "SOFT RESET";
+ } else if (rcsr & (1 << 1)) {
+ if (wrsr & (1 << 0)) {
+ reset_cause = "SOFTWARE RESET";
+ } else if (wrsr & (1 << 1)) {
+ reset_cause = "WATCHDOG TIMEOUT";
+ }
+ } else {
+ diag_printf("Unknown RESET cause: RCSR=0x%08x WRSR=0x%04x\n", rcsr, wrsr);
+ return;
+ }
+ diag_printf("Last RESET cause: %s\n", reset_cause);
+#else
unsigned int rest = readl(CCM_BASE_ADDR + CLKCTL_RCSR) & 0xF;
if (rest == 0)
diag_printf("hardware reset by POR\n");
else if (rest == 1)
diag_printf("hardware reset by Board reset signal\n");
- else if ((rest & 2) == 2)
+ else if (rest & 2)
diag_printf("hardware reset by WDOG\n");
- else if ((rest & 4) == 4)
+ else if (rest & 4)
diag_printf("hardware reset by SOFT RESET\n");
- else if ((rest & 8) == 8)
+ else if (rest & 8)
diag_printf("hardware reset by JTAG SW RESET\n");
else
diag_printf("hardware reset by unknown source (REST=%x)\n", rest);
+#endif
}
RedBoot_init(check_reset_source, RedBoot_INIT_LAST);
display "Global command prefix"
flavor data
no_define
- default_value { "arm-elf" }
+ default_value { "arm-none-eabi" }
description "
This option specifies the command prefix used when
invoking the build tools."
display "Global compiler flags"
flavor data
no_define
- default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
description "
This option controls the global compiler flags which are used to
compile all packages by default. Individual packages may define
#include <cyg/hal/hal_soc.h> // Hardware definitions
#define PMIC_SPI_BASE CSPI1_BASE_ADDR
+#define PMIC_SPI_CHIP_SELECT_NO SPI_CTRL_CS0
#define PBC_REG_SHIFT 1
#define PBC_BASE SOC_CS4_BASE /* Peripheral Bus Controller */
#define CYGHWR_HAL_ROM_VADDR 0x0
+//#define NFC_2K_BI_SWAP
+
// This macro represents the initial startup code for the platform
// r11 is reserved to contain chip rev info in this file
.macro _platform_setup1
mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
+ mov r0, #NFC_BASE
+ add r1, r0, #0x400
+ cmp pc, r0
+ blo init_aipi_start
+ cmp pc, r1
+ bhi init_aipi_start
+#ifdef NFC_2K_BI_SWAP
+ ldr r3, [r0, #0x7D0] // load word at addr 464 of last 512 RAM buffer
+ and r3, r3, #0xFFFFFF00 // mask off the LSB
+ ldr r4, [r0, #0x834] // load word at addr 4 of the 3rd spare area buffer
+ mov r4, r4, lsr #8 // shift it to get the byte at addr 5
+ and r4, r4, #0xFF // throw away upper 3 bytes
+ add r3, r4, r3 // construct the word
+ str r3, [r0, #0x7D0] // write back
+#endif
+
init_aipi_start:
init_aipi
ldr r0, SOC_SYSCTRL_BASE_W
mov r1, #0x03
str r1, [r0, #(SOC_SYSCTRL_PCSR - SOC_SYSCTRL_BASE)]
- mov r1, #0xFFFFFFC9
+ ldr r1, [r0, #(SOC_SYSCTRL_FMCR - SOC_SYSCTRL_BASE)]
+ and r1, r1, #0xFFFFFFF0
+ orr r1, r1, #9
str r1, [r0, #(SOC_SYSCTRL_FMCR - SOC_SYSCTRL_BASE)]
init_max_start:
blo Normal_Boot_Continue
cmp pc, r2
bhi Normal_Boot_Continue
+
NAND_Boot_Start:
/* Copy image from flash to SDRAM first */
ldr r1, MXC_REDBOOT_ROM_START
nop
nop
+NAND_Copy_Main:
+ // Check if x16/2kb page
+ ldr r7, SOC_SYSCTRL_BASE_W
+ ldr r7, [r7, #0x14]
+ ands r7, r7, #(1 << 5)
+
mov r0, #NAND_FLASH_BOOT
ldr r1, AVIC_VECTOR0_ADDR_W
str r0, [r1]
mov r0, #MXCFIS_NAND
ldr r1, AVIC_VECTOR1_ADDR_W
str r0, [r1]
-NAND_Copy_Main:
+
ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
mov r1, #0x800 //r1: starting flash addr to be copied. Updated constantly
- add r2, r0, #0x200 //r2: end of 1st RAM buf. Doesn't change
+ add r2, r0, #0x800 //2K Page:: r2: end of 1st RAM buf. Doesn't change
+ addeq r2, r0, #0x200 //512 Page:: r2: end of 1st RAM buf. Doesn't change
add r12, r0, #0xE00 //r12: NFC register base. Doesn't change
- ldr r14, MXC_REDBOOT_ROM_START
- add r13, r14, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
- add r14, r14, r1 //r14: starting SDRAM address for copying. Updated constantly
+ ldr r11, MXC_REDBOOT_ROM_START
+ add r13, r11, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
+ add r11, r11, r1 //r11: starting SDRAM address for copying. Updated constantly
//unlock internal buffer
mov r3, #0x2
strh r3, [r12, #0xA]
Nfc_Read_Page:
-// writew(FLASH_Read_Mode1, NAND_FLASH_CMD_REG);
- mov r3, #0x0;
- strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
- mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
- strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
- do_wait_op_done
-
+// NFC_CMD_INPUT(FLASH_Read_Mode1);
+ mov r3, #0x0
+ nfc_cmd_input
+
+ // Check if x16/2kb page
+ ldr r7, SOC_SYSCTRL_BASE_W
+ ldr r7, [r7, #0x14]
+ ands r7, r7, #(1 << 5)
+ bne nfc_addr_ops_2kb
// start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
mov r3, r1
do_addr_input //1st addr cycle
do_addr_input //2nd addr cycle
mov r3, r1, lsr #17
do_addr_input //3rd addr cycle
-
mov r3, r1, lsr #25
do_addr_input //4th addr cycle
+ b end_of_nfc_addr_ops
+
+nfc_addr_ops_2kb:
+// start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
+ mov r3, #0
+ do_addr_input //1st addr cycle
+ mov r3, #0
+ do_addr_input //2nd addr cycle
+ mov r3, r1, lsr #11
+ do_addr_input //3rd addr cycle
+ mov r3, r1, lsr #19
+ do_addr_input //4th addr cycle
+ mov r3, r1, lsr #27
+ do_addr_input //4th addr cycle
+// NFC_CMD_INPUT(FLASH_Read_Mode1_2K);
+ mov r3, #0x30
+ nfc_cmd_input
+end_of_nfc_addr_ops:
// NFC_DATA_OUTPUT(buf, FDO_PAGE_SPARE_VAL);
-// writew(NAND_FLASH_CONFIG1_ECC_EN, NAND_FLASH_CONFIG1_REG);
- mov r3, #(NAND_FLASH_CONFIG1_ECC_EN)
- strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
-
-// writew(buf_no, RAM_BUFFER_ADDRESS_REG);
- mov r3, #0
- strh r3, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
-// writew(FDO_PAGE_SPARE_VAL & 0xFF, NAND_FLASH_CONFIG2_REG);
- mov r3, #FDO_PAGE_SPARE_VAL
- strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
-// wait_op_done();
- do_wait_op_done
+// writew(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN,
+// NAND_FLASH_CONFIG1_REG);
+ mov r8, #0
+ bl nfc_data_output
+ bl do_wait_op_done
+ // Check if x16/2kb page
+ ldr r7, SOC_SYSCTRL_BASE_W
+ ldr r7, [r7, #0x14]
+ ands r7, r7, #(1 << 5)
+ beq nfc_addr_data_output_done_512
+
+// For 2K page - 2nd 512
+ mov r8, #1
+ bl nfc_data_output
+ bl do_wait_op_done
+
+// 3rd 512
+ mov r8, #2
+ bl nfc_data_output
+ bl do_wait_op_done
+
+// 4th 512
+ mov r8, #3
+ bl nfc_data_output
+ bl do_wait_op_done
+// end of 4th
+#ifdef NFC_2K_BI_SWAP
+ ldr r3, [r0, #0x7D0] // load word at addr 464 of last 512 RAM buffer
+ and r3, r3, #0xFFFFFF00 // mask off the LSB
+ ldr r4, [r0, #0x834] // load word at addr 4 of the 3rd spare area buffer
+ mov r4, r4, lsr #8 // shift it to get the byte at addr 5
+ and r4, r4, #0xFF // throw away upper 3 bytes
+ add r3, r4, r3 // construct the word
+ str r3, [r0, #0x7D0] // write back
+#endif
+ // check for bad block
+ mov r3, r1, lsl #(32-17) // get rid of block number
+ cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
+ b nfc_addr_data_output_done
+nfc_addr_data_output_done_512:
// check for bad block
- mov r3, r1, lsl #(32-5-9)
- cmp r3, #(512 << (32-5-9))
- bhi Copy_Good_Blk
+ mov r3, r1, lsl #(32-5-9) // get rid of block number
+ cmp r3, #(512 << (32-5-9)) // check if not page 0 or 1
+
+nfc_addr_data_output_done:
+ b Copy_Good_Blk // workaround for now. See ENGR00067497
+// bhi Copy_Good_Blk
add r4, r0, #0x800 //r3 -> spare area buf 0
ldrh r4, [r4, #0x4]
and r4, r4, #0xFF00
cmp r3, #0x0
beq Skip_bad_block
// even suckier since we already read the first page!
- sub r14, r14, #512 //rewind 1 page for the sdram pointer
- sub r1, r1, #512 //rewind 1 page for the flash pointer
+
+ // Check if x16/2kb page
+ ldr r7, SOC_SYSCTRL_BASE_W
+ ldr r7, [r7, #0x14]
+ ands r7, r7, #(1 << 5)
+
+ subeq r11, r11, #512 //rewind 1 page for the sdram pointer
+ subeq r1, r1, #512 //rewind 1 page for the flash pointer
+
+ // for 2k page
+ subne r11, r11, #0x800 //rewind 1 page for the sdram pointer
+ subne r1, r1, #0x800 //rewind 1 page for the flash pointer
+
Skip_bad_block:
- add r1, r1, #(32*512)
+ // Check if x16/2kb page
+ ldr r7, SOC_SYSCTRL_BASE_W
+ ldr r7, [r7, #0x14]
+ ands r7, r7, #(1 << 5)
+
+ addeq r1, r1, #(32*512)
+ addne r1, r1, #(64*2048)
+
b Nfc_Read_Page
Copy_Good_Blk:
//copying page
1: ldmia r0!, {r3-r10}
- stmia r14!, {r3-r10}
+ stmia r11!, {r3-r10}
cmp r0, r2
blo 1b
- cmp r14, r13
+ cmp r11, r13
bge NAND_Copy_Main_done
- add r1, r1, #0x200
- ldr r0, NFC_BASE_W
+ // Check if x16/2kb page
+ ldr r7, SOC_SYSCTRL_BASE_W
+ ldr r7, [r7, #0x14]
+ ands r7, r7, #(1 << 5)
+
+ addeq r1, r1, #0x200
+ addne r1, r1, #0x800
+ mov r0, #NFC_BASE
b Nfc_Read_Page
NAND_Copy_Main_done:
.endm // _platform_setup1
+do_wait_op_done:
+ 1:
+ ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
+ beq 1b
+ bx lr // do_wait_op_done
+
+nfc_data_output:
+ mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
+ strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+
+ // writew(buf_no, RAM_BUFFER_ADDRESS_REG);
+ strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
+ // writew(FDO_PAGE_SPARE_VAL & 0xFF, NAND_FLASH_CONFIG2_REG);
+ mov r3, #FDO_PAGE_SPARE_VAL
+ strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ bx lr
+
#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
#define PLATFORM_SETUP1
#endif
str r1, [r0, #CSCRA_OFFSET]
.endm /* init_cs0_sync */
- .macro init_cs4: /* ADS board expanded IOs */
+ .macro init_cs4 /* ADS board expanded IOs */
ldr r1, SOC_CS4_CTL_BASE_W
ldr r2, CS4_CSCRU_0x0000DCF6
str r2, [r1, #CSCRU_OFFSET]
ldr r1, [r1]
ands r1, r1, #0xF0000000
// add Latency on CAS only for TO2
- ldreq r1, SDRAM_0x00795729
- ldrne r1, SDRAM_0x00795429
-
+ // TO 1.0's ID = 0x0 ==>> CAS = 3
+ bne 2f
+ ldr r1, SDRAM_0x00795729
+ b 3f
+ // now handles TO 2.x
+ 2:
+ ands r1, r1, #0xE0000000
+ // TO 2.0's ID = 0x1 => CAS = 4 due to the MPEG4 issue
+ ldreq r1, SDRAM_0x00795429
+ // subesquent TO's are OK w/ CAS = 3
+ ldrne r1, SDRAM_0x00795729
+ 3:
str r1, [r0, #0x4]
ldr r1, SDRAM_0x92200000
str r1, [r0, #0x0]
str r1, [r0, #0x0]
.endm // setup_sdram_ddr
- .macro do_wait_op_done
- 1:
- ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
- ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
- beq 1b
- mov r3, #0x0
+ .macro nfc_cmd_input
+ strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
+ mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
- .endm // do_wait_op_done
+ bl do_wait_op_done
+ .endm // nfc_cmd_input
.macro do_addr_input
and r3, r3, #0xFF
strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
mov r3, #NAND_FLASH_CONFIG2_FADD_EN
strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
- do_wait_op_done
+ bl do_wait_op_done
.endm // do_addr_input
#define PLATFORM_VECTORS _platform_vectors
SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
};
cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
- user_value 1 "FSL 200740"
+ user_value 1 "FSL 200904"
};
#include <cyg/hal/hal_mm.h>
externC void* memset(void *, int, size_t);
+#define REG_REGULATOR_MODE_1 33
void hal_mmu_init(void)
{
static void board_raise_voltage(void)
{
+ unsigned int val = 0, temp = 0;
#if defined (CLOCK_399_133_66)
/* Increase core voltage to 1.45 */
setCoreVoltage(0x16);
#endif
+
+ temp = 0x9240;
+ val = (1 << 31) | (REG_REGULATOR_MODE_1 << 25) | (temp & 0x00FFFFFF);
+ /* Enable VCAM */
+ spi_xchg_single(val, PMIC_SPI_BASE);
}
RedBoot_init(board_raise_voltage, RedBoot_INIT_PRIO(101));
int stat;
if (IS_FIS_FROM_NAND()) {
- base_addr = (void*)MXC_NAND_BASE_DUMMY;
+ base_addr = (void*)0;
diag_printf("Updating ROM in NAND flash\n");
} else if (IS_FIS_FROM_NOR()) {
base_addr = (void*)BOARD_FLASH_START;
implements CYGHWR_HAL_ARM_SOC_UART3
implements CYGHWR_HAL_ARM_SOC_UART4
+ requires {CYGBLD_BUILD_REDBOOT == 1}
+
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_soc.h>"
cdl_component CYG_HAL_STARTUP {
display "Startup type"
flavor data
- default_value {"ROMRAM"}
- legal_values {"ROMRAM"}
+ default_value { "ROMRAM" }
+ legal_values { "ROMRAM" }
no_define
define -file system.h CYG_HAL_STARTUP
description "
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
display "Debug serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
- flavor data
+ flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value 0
description "
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
- display "Default console channel."
- flavor data
- legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
- calculated 0
+ display "Default console channel."
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ calculated 0
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
- display "Console serial port"
- active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ display "Console serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
flavor data
- legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
- default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
- description "
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ description "
The TX27 provides access to three serial ports. This option
chooses which port will be used for console output."
}
cdl_component CYGBLD_GLOBAL_OPTIONS {
- display "Global build options"
- flavor none
+ display "Global build options"
+ flavor none
no_define
description "
Global build options including control over
parent CYGPKG_NONE
cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
- display "Global command prefix"
- flavor data
+ display "Global command prefix"
+ flavor data
no_define
- default_value { "arm-linux" }
- description "
+ default_value { "arm-926ejs-linux-gnu" }
+ description "
This option specifies the command prefix used when
invoking the build tools."
}
cdl_option CYGBLD_GLOBAL_CFLAGS {
- display "Global compiler flags"
- flavor data
+ display "Global compiler flags"
+ flavor data
no_define
- default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ requires CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS
+ default_value { "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe" }
description "
This option controls the global compiler flags which are used to
compile all packages by default. Individual packages may define
}
cdl_option CYGBLD_GLOBAL_LDFLAGS {
- display "Global linker flags"
- flavor data
+ display "Global linker flags"
+ flavor data
no_define
default_value { "-Wl,--gc-sections -Wl,-static -O2 -nostdlib" }
description "
packages may define options which override these global flags."
}
}
+
cdl_component CYGPKG_HAL_ARM_TX27_OPTIONS {
display "Ka-Ro electronics TX27 module build options"
- flavor none
+ flavor none
no_define
+ requires { CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0 }
description "
Package specific build options including control over
compiler flags used only in building this package,
and details of which tests are built."
+ cdl_option CYGNUM_HAL_ARM_TX27_SDRAM_SIZE {
+ display "SDRAM size"
+ flavor data
+ legal_values { 0x04000000 0x08000000 }
+ default_value { 0x04000000 }
+# This is what I would like to do, but define_proc currently does not allow for
+# accessing variables
+# display "SDRAM size in MiB"
+# legal_values { 64 128 }
+# default_value { 64 }
+# define_proc {
+# puts $::cdl_header "#define CYGNUM_HAL_ARM_TX27_SDRAM_SIZE \
+# [format "0x%08x" [expr $CYGNUM_HAL_ARM_TX27_SDRAM_SIZE * 1048576]]"
+# }
+ description "
+ This option specifies the SDRAM size of the TX27 module."
+ }
+
+ cdl_option CYGOPT_HAL_ARM_TX27_DEBUG {
+ display "Enable low level debugging with LED"
+ flavor bool
+ default_value { false }
+ description "
+ This option enables low level debugging by blink codes
+ of the LED on STK5."
+ }
+
cdl_option CYGPKG_HAL_ARM_TX27_CFLAGS_ADD {
- display "Additional compiler flags"
- flavor data
+ display "Additional compiler flags"
+ flavor data
no_define
default_value { "" }
description "
}
cdl_option CYGPKG_HAL_ARM_TX27_CFLAGS_REMOVE {
- display "Suppressed compiler flags"
- flavor data
+ display "Suppressed compiler flags"
+ flavor data
no_define
default_value { "" }
description "
display "Memory layout"
flavor data
no_define
- calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_tx27_ram" :
- (CYG_HAL_STARTUP == "ROMRAM") ? "arm_tx27_romram" :
- "arm_tx27_rom" }
+ calculated { "arm_tx27_romram" }
cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
display "Memory layout linker script fragment"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
- calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_tx27_ram.ldi>" :
- (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_tx27_romram.ldi>" :
- "<pkgconf/mlt_arm_tx27_rom.ldi>" }
+ calculated { "<pkgconf/mlt_arm_tx27_romram.ldi>" }
}
cdl_option CYGHWR_MEMORY_LAYOUT_H {
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_H
- calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_tx27_ram.h>" :
- (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_tx27_romram.h>" :
- "<pkgconf/mlt_arm_tx27_rom.h>" }
+ calculated { "<pkgconf/mlt_arm_tx27_romram.h>" }
}
}
requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
description "
Enable this option if this program is to be used as a ROM monitor,
- i.e. applications will be loaded into RAM on the TX27, and this
+ i.e. applications will be loaded into RAM on the TX27 module, and this
ROM monitor may process exceptions or interrupts generated from the
application. This enables features such as utilizing a separate
interrupt stack when exceptions are generated."
description "
This option lists the target's requirements for a valid Redboot
configuration."
-
+
compile -library=libextras.a redboot_cmds.c
cdl_option CYGBLD_BUILD_REDBOOT_BIN {
$(OBJCOPY) --strip-debug $< $(@:.bin=.img)
$(OBJCOPY) -O srec $< $(@:.bin=.srec)
$(OBJCOPY) -O binary $< $@
+ $(COMMAND_PREFIX)nm $< | awk 'NF == 3 {print}' | sort > $(<:.elf=.map)
}
}
}
#define CYGHWR_HAL_ROM_VADDR 0x0
-//#define TX27_DEBUG
-
-#ifndef TX27_DEBUG
+#ifndef CYGOPT_HAL_ARM_TX27_DEBUG
#define LED_ON
#define LED_OFF
.macro LED_CTRL,val
.macro DELAY,val
.endm
#else
-#define CYGHWR_LED_MACRO LED_BLINK \x
+#define CYGHWR_LED_MACRO LED_BLINK #\x
#define LED_ON bl led_on
#define LED_OFF bl led_off
.macro DELAY,ms
.endm
.macro LED_BLINK,val
- mov r2, #\val
+ mov r3, \val
211:
- subs r2, r2, #1
+ subs r3, r3, #1
bmi 212f
LED_CTRL #1
DELAY 200
// This macro represents the initial startup code for the platform
// r11 is reserved to contain chip rev info in this file
.macro _platform_setup1
- b KARO_TX27_SETUP_START
-#ifdef TX27_DEBUG
-led_on:
- ldr r10, GPIOF_BASE
- // PTF_DR
- mov r9, #(1 << 13) // LED ON
- str r9, [r10, #GPIO_DR]
- mov pc, lr
-
-led_off:
- ldr r10, GPIOF_BASE
- // PTF_DR
- mov r9, #0 // LED OFF
- str r9, [r10, #GPIO_DR]
- mov pc, lr
-#endif
-
-nfc_cmd_input:
- strh r3, [r4, #NAND_FLASH_CMD_REG_OFF]
- mov r3, #NAND_FLASH_CONFIG2_FCMD_EN
- strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
- b nfc_wait_op_done
-
-nfc_addr_input:
- and r3, r3, #0xFF
- strh r3, [r4, #NAND_FLASH_ADD_REG_OFF]
- mov r3, #NAND_FLASH_CONFIG2_FADD_EN
- strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
- b nfc_wait_op_done
-
-nfc_data_output:
- mov r3, #FDO_PAGE_SPARE_VAL
- strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
- add r8, r8, #1
- b nfc_wait_op_done
-
-nfc_wait_op_done:
-311:
- ldrh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
- ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
- movne r3, #0x0
- strneh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
- movne pc, lr
- b 311b
-
KARO_TX27_SETUP_START:
// invalidate I/D cache/TLB
mov r0, #0
init_aipi_start:
init_aipi
-#if 1
- mov r0, #SDRAM_NON_FLASH_BOOT
- ldr r1, AVIC_VECTOR0_ADDR_W
- str r0, [r1] // for checking boot source from nand or sdram
-#endif
+
+ LED_INIT
+
// setup System Controls
ldr r0, SOC_SYSCTRL_BASE_W
mov r1, #0x03
init_clock_start:
init_clock
init_sdram_start:
+ LED_BLINK #1
setup_sdram_ddr
-
+ LED_BLINK #2
HWInitialise_skip_SDRAM_setup:
ldr r0, NFC_BASE_W
add r2, r0, #0x800 // 2K window
NAND_Boot_Start:
/* Copy image from flash to SDRAM first */
- ldr r1, MXC_REDBOOT_ROM_START
+ ldr r1, MXC_REDBOOT_RAM_START
1:
ldmia r0!, {r3-r10}
stmia r1!, {r3-r10}
blo 1b
LED_ON
- ldr r1, MXC_REDBOOT_ROM_START
+ ldr r1, MXC_REDBOOT_RAM_START
ldr r0, NFC_BASE_W
2:
ldr r3, [r1], #4
LED_OFF
b 4f
3:
- LED_BLINK 3
+ LED_BLINK #3
b 3b
4:
LED_ON
/* Jump to SDRAM */
- jump_to_sdram
+ bl jump_to_sdram
LED_OFF
-#if 1
- mov r0, #NAND_FLASH_BOOT
- ldr r1, AVIC_VECTOR0_ADDR_W
- str r0, [r1]
- mov r0, #MXCFIS_NAND
- ldr r1, AVIC_VECTOR1_ADDR_W
- str r0, [r1]
-#endif
NAND_Copy_Main:
ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
mov r1, #TX27_NAND_PAGE_SIZE //r1: starting flash addr to be copied. Updated constantly
- add r2, r0, #TX27_NAND_PAGE_SIZE //r2: end of 3st RAM buf. Doesn't change
+ add r2, r0, #TX27_NAND_PAGE_SIZE //r2: end of 1st RAM buf. Doesn't change
add r4, r0, #0xE00 //r4: NFC register base. Doesn't change
- ldr r5, MXC_REDBOOT_ROM_START
+ ldr r5, MXC_REDBOOT_RAM_START
add r6, r5, #REDBOOT_IMAGE_SIZE //r6: end of SDRAM address for copying. Doesn't change
add r5, r5, r1 //r5: starting SDRAM address for copying. Updated constantly
sub r5, r5, #TX27_NAND_PAGE_SIZE //rewind 1 page for the sdram pointer
sub r1, r1, #TX27_NAND_PAGE_SIZE //rewind 1 page for the flash pointer
Skip_bad_block:
-#ifdef TX27_DEBUG
- LED_BLINK 1
+#ifdef CYGOPT_HAL_ARM_TX27_DEBUG
+ LED_BLINK #1
b Skip_bad_block
#endif
add r1, r1, #(TX27_NAND_BLKS_PER_PAGE*TX27_NAND_PAGE_SIZE)
NAND_Copy_Main_done:
Normal_Boot_Continue:
- jump_to_sdram
+ bl jump_to_sdram
// Code and all data used up to here must fit within the first 2KiB of FLASH ROM!
Now_in_SDRAM:
- ///LED_BLINK 3
+ LED_BLINK #3
#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
/* Copy image from flash to SDRAM first */
ldr r0, =0xFFFFF000
and r0, r0, pc
- ldr r1, MXC_REDBOOT_ROM_START
+ ldr r1, MXC_REDBOOT_RAM_START
cmp r0, r1
beq HWInitialise_skip_SDRAM_copy
cmp r0, r2
ble 1b
- jump_to_sdram
+ bl jump_to_sdram
#endif /* CYG_HAL_STARTUP_ROMRAM */
HWInitialise_skip_SDRAM_copy:
- ///LED_BLINK 2
+ LED_BLINK #2
init_cs0_sync_start:
init_cs0_sync
bic r2, r2, #0x0000FC00
str r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
- /* Configure PCDR */
/* Configure PCDR1 */
ldr r1, SOC_CRM_PCDR1_W
str r1, [r0, #(SOC_CRM_PCDR1 - SOC_CRM_BASE)]
// base address of SDRAM for SET MODE commands written to SDRAM via address lines
mov r2, #SOC_CSD0_BASE
- mov r1, #(1 << 3) // delay line soft reset
+ mov r1, #(1 << 1) // SDRAM controller reset
str r1, [r0, #ESDCTL_ESDMISC]
1:
// wait until SDRAMRDY bit is set indicating SDRAM is usable
tst r1, #(1 << 31)
beq 1b
- mov r1, #(1 << 2) // enable DDR pipeline
+ mov r1, #(1 << 3) @ delay line soft reset
+ str r1, [r0, #ESDCTL_ESDMISC]
+1:
+ // wait until SDRAMRDY bit is set indicating SDRAM is usable
+ ldr r1, [r0, #ESDCTL_ESDMISC]
+ tst r1, #(1 << 31)
+ beq 1b
+
+ mov r1, #(1 << 2) @ enable DDR pipeline
str r1, [r0, #ESDCTL_ESDMISC]
ldr r1, SDRAM_ESDCFG0_VAL
ldr r1, SDRAM_PRE_ALL_CMD
str r1, [r0, #ESDCTL_ESDCTL0]
- str r1, [r2, #(1 << 10)] // contents of r1 irrelevant, data written via A0-A12
+ str r1, [r2, #(1 << 10)] @ contents of r1 irrelevant, data written via A0-A11
+
ldr r1, SDRAM_AUTO_REF_CMD
str r1, [r0, #ESDCTL_ESDCTL0]
-
- // initiate 8 auto refresh cycles
- mov r3, #7
-1:
- str r1, [r2, #(1 << 10)] // contents of r1 irrelevant, data written via A0-A12
- subs r3, r3, #1
- bpl 1b
+ @ initiate 2 auto refresh cycles
+ .rept 2
+ str r1, [r2]
+ .endr
ldr r1, SDRAM_SET_MODE_REG_CMD
str r1, [r0, #ESDCTL_ESDCTL0]
- strb r1, [r2, #0x0033] // actually a write to SDRAM MODE register
+ @ address offset for extended mode register
+ add r3, r2, #(2 << 24)
+ @ select drive strength via extended mode register:
+ @ 0=full 1=half 2=quarter 3=3-quarter
+ ldrb r1, [r2, #(0 << 5)]
+
+ ldrb r1, [r2, #0x033] @ write to SDRAM MODE register (via A0-A12)
ldr r1, SDRAM_NORMAL_MODE
str r1, [r0, #ESDCTL_ESDCTL0]
str r1, [r2]
- mov r1, #((1 << 3) | (1 << 2))
+ mov r1, #((1 << 3) | (1 << 2) | (1 << 5))
str r1, [r0, #ESDCTL_ESDMISC]
.endm // setup_sdram_ddr
- .macro jump_to_sdram
- mov r0, #0
+#ifdef CYGOPT_HAL_ARM_TX27_DEBUG
+led_on:
+ ldr r10, GPIOF_BASE
+ // PTF_DR
+ mov r9, #(1 << 13) // LED ON
+ str r9, [r10, #GPIO_DR]
+ mov pc, lr
+
+led_off:
+ ldr r10, GPIOF_BASE
+ // PTF_DR
+ mov r9, #0 // LED OFF
+ str r9, [r10, #GPIO_DR]
+ mov pc, lr
+#endif
+
+nfc_cmd_input:
+ strh r3, [r4, #NAND_FLASH_CMD_REG_OFF]
+ mov r3, #NAND_FLASH_CONFIG2_FCMD_EN
+ strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
+ b nfc_wait_op_done
+
+nfc_addr_input:
+ and r3, r3, #0xFF
+ strh r3, [r4, #NAND_FLASH_ADD_REG_OFF]
+ mov r3, #NAND_FLASH_CONFIG2_FADD_EN
+ strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
+ b nfc_wait_op_done
+
+nfc_data_output:
+ mov r3, #FDO_PAGE_SPARE_VAL
+ strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
+ add r8, r8, #1
+ b nfc_wait_op_done
+
+nfc_wait_op_done:
+311:
+ ldrh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
+ ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
+ movne r3, #0x0
+ strneh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
+ movne pc, lr
+ b 311b
+
+jump_to_sdram:
+ b 1f
+ .align 5
+1:
mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
mcr 15, 0, r0, c7, c10, 4 /* Data Write Barrier */
ldr r0, SDRAM_ADDR_MASK
- ldr r1, MXC_REDBOOT_ROM_START
- and r0, pc, r0
+ ldr r1, MXC_REDBOOT_RAM_START
+ and r0, lr, r0
sub r0, r1, r0
- add pc, pc, r0
- nop
- .endm
+ add lr, lr, r0
+ mov pc, lr
.align 5
.ascii "KARO TX27 " __DATE__ " " __TIME__
.align
// All these constants need to be in the first 2KiB of FLASH
GPIOF_BASE: .word 0x10015500
-CONST_0xFFF: .word 0xfff
-SDRAM_ADDR_MASK: .word 0xfff00000
-MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x00100000
-AVIC_VECTOR0_ADDR_W: .word MXCBOOT_FLAG_REG
-AVIC_VECTOR1_ADDR_W: .word MXCFIS_FLAG_REG
+SDRAM_ADDR_MASK: .word 0xffff0000
+MXC_REDBOOT_RAM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
SOC_SYSCTRL_BASE_W: .word SOC_SYSCTRL_BASE
SOC_MAX_BASE_W: .word SOC_MAX_BASE
SOC_MAX_MPR_VAL: .word 0x00302145
SOC_CRM_BASE_W: .word SOC_CRM_BASE
-CRM_MPCTL0_VAL_W: .word CRM_MPCTL0_VAL
-CRM_SPCTL0_VAL_W: .word CRM_SPCTL0_VAL
-CRM_MPCTL0_VAL_27MHZ_W: .word CRM_MPCTL0_VAL_27MHZ
-CRM_SPCTL0_VAL_27MHZ_W: .word CRM_SPCTL0_VAL_27MHZ
-SOC_CRM_CSCR_W: .word CRM_CSCR_VAL
CRM_MPCTL0_VAL2_W: .word CRM_MPCTL0_VAL2
CRM_SPCTL0_VAL2_W: .word CRM_SPCTL0_VAL2
-CRM_MPCTL0_VAL2_27MHZ_W: .word CRM_MPCTL0_VAL2_27MHZ
-CRM_SPCTL0_VAL2_27MHZ_W: .word CRM_SPCTL0_VAL2_27MHZ
SOC_CRM_CSCR2_W: .word CRM_CSCR_VAL2
SOC_CRM_PCDR1_W: .word 0x09030913 // p1=20 p2=10 p3=4 p4=10
SOC_CRM_PCCR0_W: .word 0x3108480F
CS4_CSCRA_VAL: .word 0x44443302
NFC_BASE_W: .word NFC_BASE
SOC_ESDCTL_BASE_W: .word SOC_ESDCTL_BASE
-SDRAM_ESDCFG0_VAL: .word 0x00395728
-SDRAM_PRE_ALL_CMD: .word 0x92200000
-SDRAM_AUTO_REF_CMD: .word 0xA2200000
-SDRAM_SET_MODE_REG_CMD: .word 0xB2200000
-SDRAM_NORMAL_MODE: .word 0x82124485
+SDRAM_ESDCFG0_VAL: .word 0x00395729
+SDRAM_PRE_ALL_CMD: .word 0x92120000
+SDRAM_AUTO_REF_CMD: .word 0xA2120000
+SDRAM_SET_MODE_REG_CMD: .word 0xB2120000
+#if SDRAM_SIZE > SZ_64M
+SDRAM_NORMAL_MODE: .word 0x82226485
+#else
+SDRAM_NORMAL_MODE: .word 0x82126485
+#endif
CS0_CSCRU_VAL: .word 0x0000CC03
CS0_CSCRL_VAL: .word 0xA0330D01
CS0_CSCRA_VAL: .word 0x00220800
#define SZ_1G 0x40000000
#define RAM_BANK0_BASE SOC_CSD0_BASE
-
-#define SDRAM_BASE_ADDR SOC_CSD0_BASE
-#define SDRAM_SIZE TX27_SDRAM_SIZE
+#define TX27_SDRAM_SIZE SDRAM_SIZE
#define TX27_LED_MASK (1 << 13)
#define TX27_LED_REG_ADDR (SOC_GPIOF_BASE + GPIO_DR)
#define LED_MAX_NUM 1
-#define LED_IS_ON(n) ({ \
- CYG_WORD32 __val; \
+#define LED_IS_ON(n) ({ \
+ CYG_WORD32 __val; \
HAL_READ_UINT32(SOC_GPIOF_BASE + GPIO_DR, __val); \
- __val & TX27_LED_MASK; \
-})
+ __val & TX27_LED_MASK; \
+}) \
-#define TURN_LED_ON(n) \
- CYG_MACRO_START \
- CYG_WORD32 __val; \
+#define TURN_LED_ON(n) \
+ CYG_MACRO_START \
+ CYG_WORD32 __val; \
HAL_READ_UINT32(TX27_LED_REG_ADDR, __val); \
- __val |= TX27_LED_MASK; \
+ __val |= TX27_LED_MASK; \
HAL_WRITE_UINT32(TX27_LED_REG_ADDR, __val); \
- CYG_MACRO_END
+ CYG_MACRO_END \
-#define TURN_LED_OFF(n) \
- CYG_MACRO_START \
- CYG_WORD32 __val; \
+#define TURN_LED_OFF(n) \
+ CYG_MACRO_START \
+ CYG_WORD32 __val; \
HAL_READ_UINT32(TX27_LED_REG_ADDR, __val); \
- __val &= ~TX27_LED_MASK; \
+ __val &= ~TX27_LED_MASK; \
HAL_WRITE_UINT32(TX27_LED_REG_ADDR, __val); \
- CYG_MACRO_END
-
-#define BOARD_DEBUG_LED(n) \
- CYG_MACRO_START \
- if (n >= 0 && n < LED_MAX_NUM) { \
- if (LED_IS_ON(n)) \
- TURN_LED_OFF(n); \
- else \
- TURN_LED_ON(n); \
- } \
- CYG_MACRO_END
+ CYG_MACRO_END
+
+#define BOARD_DEBUG_LED(n) \
+ CYG_MACRO_START \
+ if (n >= 0 && n < LED_MAX_NUM) { \
+ if (LED_IS_ON(n)) \
+ TURN_LED_OFF(n); \
+ else \
+ TURN_LED_ON(n); \
+ } \
+ CYG_MACRO_END
+
+#define BLINK_LED(l, n) \
+ CYG_MACRO_START \
+ int _i; \
+ for (_i = 0; _i < (n); _i++) { \
+ BOARD_DEBUG_LED(l); \
+ HAL_DELAY_US(200000); \
+ BOARD_DEBUG_LED(l); \
+ HAL_DELAY_US(300000); \
+ } \
+ HAL_DELAY_US(1000000); \
+ CYG_MACRO_END
#if !defined(__ASSEMBLER__)
enum {
writel(val & ~(1 << gpio), SOC_GPIOA_BASE + (grp << 8) + GPIO_DR);
}
-unsigned int setCoreVoltage(unsigned int coreVol);
#endif
// eCos memory layout - Fri Oct 20 05:56:55 2000
+//#define REDBOOT_BOTTOM
+
// This is a generated file - do not edit
-#if !defined(__LINKER_SCRIPT__) && !defined(__ASSEMBLER__)
-#include <cyg/infra/cyg_type.h>
-#include <stddef.h>
-#endif
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_VARIANT_H
+#include CYGBLD_HAL_PLATFORM_H
+#include <cyg/hal/hal_soc.h> // Hardware definitions
-//#define REDBOOT_BOTTOM
+#define SDRAM_BASE_ADDR SOC_CSD0_BASE
+#define SDRAM_SIZE CYGNUM_HAL_ARM_TX27_SDRAM_SIZE
#define REDBOOT_IMAGE_SIZE 0x00040000
-#define REDBOOT_OFFSET 0x00100000
-#define TX27_SDRAM_SIZE 0x04000000
-#ifdef REDBOOT_BOTTOM
-#define CYGMEM_REGION_ram (0xA0000000 + REDBOOT_OFFSET)
-#define CYGMEM_REGION_rom (0xA0000000)
+#ifndef REDBOOT_BOTTOM
+#define REDBOOT_OFFSET REDBOOT_IMAGE_SIZE
+#define CYGMEM_REGION_ram SDRAM_BASE_ADDR
+#define CYGMEM_REGION_rom (CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE)
#else
-#define CYGMEM_REGION_ram (0xA0000000)
-#define CYGMEM_REGION_rom (CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - REDBOOT_OFFSET)
+#define REDBOOT_OFFSET 0x00100000
+#define CYGMEM_REGION_ram (SDRAM_BASE_ADDR + REDBOOT_OFFSET)
+#define CYGMEM_REGION_rom SDRAM_BASE_ADDR
#endif
-//#define CYGMEM_REGION_ram (0xA0000000)
-#define CYGMEM_REGION_ram_SIZE (TX27_SDRAM_SIZE)
+#define CYGMEM_REGION_ram_SIZE (SDRAM_SIZE - REDBOOT_OFFSET)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
-//#define CYGMEM_REGION_rom (0xA1F00000)
+
#define CYGMEM_REGION_rom_SIZE REDBOOT_OFFSET
-#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
-#if !defined(__LINKER_SCRIPT__) && !defined(__ASSEMBLER__)
-extern char CYG_LABEL_NAME (__heap1) [];
+#define CYGMEM_REGION_rom_ATTR CYGMEM_REGION_ATTR_R
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME(__heap1)[];
#endif
-#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
-#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_rom - (size_t) CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME(__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_rom - (size_t)CYG_LABEL_NAME(__heap1))
// This is a generated file - do not edit
#include <cyg/infra/cyg_type.inc>
-#define __LINKER_SCRIPT__
-#include <pkgconf/mlt_arm_tx27_romram.h>
+#define __ASSEMBLER__
+#include CYGHWR_MEMORY_LAYOUT_H
MEMORY
{
{
SECTIONS_BEGIN
SECTION_rom_vectors (rom, CYGMEM_REGION_rom, LMA_EQ_VMA)
+ SECTION_RELOCS(rom, ALIGN (0x1), LMA_EQ_VMA)
SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
template redboot ;
package -hardware CYGPKG_HAL_ARM current ;
package -hardware CYGPKG_HAL_ARM_MX27 current ;
- package -hardware CYGPKG_HAL_ARM_TX27KARO v1_0 ;
+ package -hardware CYGPKG_HAL_ARM_TX27KARO current ;
package -template CYGPKG_HAL current ;
package -template CYGPKG_INFRA current ;
package -template CYGPKG_REDBOOT current ;
package -template CYGPKG_LIBC_STRING current ;
package -template CYGPKG_CRC current ;
package -hardware CYGPKG_IO_ETH_DRIVERS current ;
- package -hardware CYGPKG_DEVS_ETH_ARM_TX27 v1_0 ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_TX27 current ;
package -hardware CYGPKG_DEVS_ETH_FEC current ;
package -hardware CYGPKG_COMPRESS_ZLIB current ;
package -hardware CYGPKG_IO_FLASH current ;
package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
- package -hardware CYGPKG_IO_I2C current ;
- package -hardware CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS1307 current ;
- package CYGPKG_MEMALLOC current ;
- package CYGPKG_DEVS_ETH_PHY current ;
- package CYGPKG_LIBC_I18N current ;
+ package -template CYGPKG_MEMALLOC current ;
+ package -template CYGPKG_DEVS_ETH_PHY current ;
+ package -template CYGPKG_LIBC_I18N current ;
+ package -template CYGPKG_LIBC_STDLIB current ;
+ package -template CYGPKG_ERROR current ;
};
cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
inferred_value 0
};
-cdl_component CYGDBG_IO_ETH_DRIVERS_DEBUG {
- user_value 1
+cdl_option CYGHWR_DEVS_ETH_PHY_LAN8700 {
+ inferred_value 1
};
-cdl_option CYGDBG_IO_ETH_DRIVERS_DEBUG_VERBOSITY {
+cdl_option CYGIMP_LIBC_RAND_SIMPLE1 {
user_value 0
};
-cdl_component CYGPKG_IO_ETH_DRIVERS_STAND_ALONE {
+cdl_option CYGIMP_LIBC_RAND_KNUTH1 {
user_value 1
};
-cdl_option CYGHWR_DEVS_ETH_PHY_LAN8700 {
- user_value 1
-};
-
-cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+cdl_option CYGFUN_LIBC_STDLIB_CONV_LONGLONG {
user_value 0
- inferred_value 1
};
-cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
- user_value 4096
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
};
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
- user_value 0
+ inferred_value 0
};
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
};
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
- inferred_value 1
+ inferred_value 0
};
cdl_option CYGSEM_HAL_ROM_MONITOR {
- user_value 1
- inferred_value 1
-};
-
-cdl_option CYGBLD_ARM_ENABLE_THUMB_INTERWORK {
- user_value 1
inferred_value 1
};
user_value 33554432
};
-cdl_option CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK {
- user_value 399
-};
-
-cdl_component CYG_HAL_STARTUP {
- user_value ROMRAM
-};
-
-cdl_component CYGSEM_REDBOOT_ELF {
- user_value 1
-};
-
cdl_component CYGBLD_BUILD_REDBOOT {
- user_value 1
+ inferred_value 1
};
cdl_option CYGBLD_BUILD_REDBOOT_WITH_GDB {
- user_value 0
+ inferred_value 0
};
cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
- user_value 1 "Ka-Ro [exec date -I]"
+ inferred_value 1 "Ka-Ro [exec date -I]"
};
cdl_option CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
inferred_value 1
};
-cdl_option CYGBLD_BUILD_REDBOOT_WITH_MXCUSB {
- user_value 0
-};
-
-cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_WINCE_SUPPORT {
user_value 1
};
-cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
- user_value 10
-};
-
-cdl_option CYGDBG_REDBOOT_NET_DEBUG {
+cdl_option CYGSEM_REDBOOT_NET_HTTP_DOWNLOAD {
user_value 0
};
cdl_option CYGPKG_REDBOOT_ANY_CONSOLE {
- user_value 1
+ inferred_value 0
+};
+
+cdl_option CYGSEM_REDBOOT_PLF_ESA_VALIDATE {
+ inferred_value 1
};
cdl_option CYGPKG_REDBOOT_MAX_CMD_LINE {
- user_value 1024
+ inferred_value 1024
};
cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
inferred_value 0x00040000
};
-cdl_component CYGSEM_REDBOOT_FLASH_CONFIG {
- user_value 1
-};
-
-cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
- user_value 0
-};
-
cdl_option CYGNUM_REDBOOT_FLASH_SCRIPT_SIZE {
- user_value 2048
+ inferred_value 2048
};
-cdl_option CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT {
- user_value 0 0
+cdl_component CYGPKG_REDBOOT_DISK {
+ user_value 0
};
cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_TIMEOUT_RESOLUTION {
- user_value 10
+ inferred_value 10
};
cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_DEFAULT_TIMEOUT {
- user_value 100
+ inferred_value 1
};
-cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS {
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
inferred_value 0xA0108000
};
-cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
- inferred_value 0xA0108000
+cdl_option CYGBLD_ISO_CTYPE_HEADER {
+ inferred_value 1 <cyg/libc/i18n/ctype.inl>
};
-cdl_option CYGHWR_REDBOOT_ARM_LINUX_TAGS_ADDRESS {
- user_value 0xA0001000
+cdl_option CYGBLD_ISO_ERRNO_CODES_HEADER {
+ inferred_value 1 <cyg/error/codes.h>
};
-cdl_option CYGBLD_ISO_CTYPE_HEADER {
- user_value 1 <cyg/libc/i18n/ctype.inl>
+cdl_option CYGBLD_ISO_ERRNO_HEADER {
+ inferred_value 1 <cyg/error/errno.h>
};
cdl_option CYGBLD_ISO_STDLIB_STRCONV_HEADER {
- user_value 1 <cyg/libc/stdlib/atox.inl>
+ inferred_value 1 <cyg/libc/stdlib/atox.inl>
};
cdl_option CYGBLD_ISO_STDLIB_ABS_HEADER {
- user_value 1 <cyg/libc/stdlib/abs.inl>
+ inferred_value 1 <cyg/libc/stdlib/abs.inl>
};
cdl_option CYGBLD_ISO_STDLIB_DIV_HEADER {
- user_value 1 <cyg/libc/stdlib/div.inl>
+ inferred_value 1 <cyg/libc/stdlib/div.inl>
+};
+
+cdl_option CYGBLD_ISO_STRERROR_HEADER {
+ inferred_value 1 <cyg/error/strerror.h>
};
cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
-cdl_option CYGBLD_ISO_C_TIME_TYPES_HEADER {
- user_value 1 <cyg/libc/time/time.h>
-};
-
-cdl_option CYGBLD_ISO_C_CLOCK_FUNCS_HEADER {
- user_value 1 <cyg/libc/time/time.h>
-};
-
-cdl_option CYGBLD_ISO_BSDTYPES_HEADER {
- user_value 0 0
-};
-
cdl_option CYGSEM_IO_FLASH_READ_INDIRECT {
inferred_value 1
};
inferred_value 1
};
+cdl_component CYGHWR_FLASH_NAND_BBT_HEADER {
+ inferred_value 1 <cyg/io/tx27_nand_bbt.h>
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_MULTI {
+ inferred_value 0
+};
+
+cdl_option CYGSEM_ERROR_PER_THREAD_ERRNO {
+ inferred_value 0
+};
#endif //CYGSEM_REDBOOT_FLASH_CONFIG
+#ifdef CYGPKG_IO_FLASH
+#include <cyg/io/flash.h>
+#endif
+
static void runImg(int argc, char *argv[]);
static void do_mem(int argc, char *argv[]);
);
}
-extern unsigned long entry_address;
-
static void runImg(int argc,char *argv[])
{
unsigned int virt_addr, phys_addr;
romupdate
);
-extern int flash_program(void *_addr, void *_data, int len, void **err_addr);
-extern int flash_erase(void *addr, int len, void **err_addr);
-extern char *flash_errmsg(int err);
-
#ifdef CYGPKG_IO_FLASH
void romupdate(int argc, char *argv[])
{
void *err_addr, *base_addr;
int stat;
- base_addr = (void*)MXC_NAND_BASE_DUMMY;
+ base_addr = (void*)(MXC_NAND_BASE_DUMMY + CYGBLD_REDBOOT_FLASH_BOOT_OFFSET);
diag_printf("Updating RedBoot in NAND flash\n");
// Erase area to be programmed
return;
}
// Now program it
- if ((stat = flash_program(base_addr, ram_end - CYGMEM_REGION_rom_SIZE,
+ if ((stat = flash_program(base_addr, ram_end,
CYGBLD_REDBOOT_MIN_IMAGE_SIZE, &err_addr)) != 0) {
diag_printf("Can't program region at %p: %s\n",
err_addr, flash_errmsg(stat));
}
#endif //CYGPKG_IO_FLASH
#endif /* CYG_HAL_STARTUP_ROMRAM */
-
-static void setcorevol(int argc, char *argv[]);
-
-RedBoot_cmd("setcorevol",
- "Set the core voltage. Setting is not checked against current core frequency.",
- "[1.2 | 1.25 | 1.3 | 1.35 | 1.4 | 1.45 | 1.5 | 1.55 | 1.6]",
- setcorevol
- );
-
-/*
- * This function communicates with LP3972 to set the core voltage according to
- * the argument
- */
-// LW: revisit use I2C routines for LP3972
-unsigned int setCoreVoltage(unsigned int coreVol)
-{
- /* Set the core voltage */
- diag_printf("%s: Not yet implemented\n", __FUNCTION__);
- return 0;
-}
-
-static void setcorevol(int argc, char *argv[])
-{
- unsigned int coreVol;
-
- /* check if the number of args is OK. 1 arg expected. argc = 2 */
- if (argc != 2) {
- diag_printf("Invalid argument. Need to specify a voltage\n");
- return;
- }
-
- /* check if the argument is valid. */
- if (strcasecmp(argv[1], "1.2") == 0) {
- coreVol = 0xC;
- } else if (strcasecmp(argv[1], "1.25") == 0) {
- coreVol = 0xE;
- } else if (strcasecmp(argv[1], "1.3") == 0) {
- coreVol = 0x10;
- } else if (strcasecmp(argv[1], "1.35") == 0) {
- coreVol = 0x12;
- } else if (strcasecmp(argv[1], "1.4") == 0) {
- coreVol = 0x14;
- } else if (strcasecmp(argv[1], "1.45") == 0) {
- coreVol = 0x16;
- } else if (strcasecmp(argv[1], "1.5") == 0) {
- coreVol = 0x18;
- } else if (strcasecmp(argv[1], "1.55") == 0) {
- coreVol = 0x1A;
- } else if (strcasecmp(argv[1], "1.6") == 0) {
- coreVol = 0x1C;
- } else {
- diag_printf("Invalid argument. Type help setcorevol for valid values\n");
- return ;
- }
-
- setCoreVoltage(coreVol);
- return;
-}
hal_diag_write_char_serial('O');
csum += 'O';
for (i = 0; i < pos; i++) {
- char ch = line[i];
- char h = hex[(ch>>4)&0xF];
- char l = hex[ch&0xF];
- hal_diag_write_char_serial(h);
- hal_diag_write_char_serial(l);
- csum += h;
- csum += l;
+ char ch = line[i];
+ char h = hex[(ch >> 4) & 0xF];
+ char l = hex[ch & 0xF];
+ hal_diag_write_char_serial(h);
+ hal_diag_write_char_serial(l);
+ csum += h;
+ csum += l;
}
hal_diag_write_char_serial('#');
- hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
- hal_diag_write_char_serial(hex[csum&0xF]);
+ hal_diag_write_char_serial(hex[(csum >> 4) & 0xF]);
+ hal_diag_write_char_serial(hex[csum & 0xF]);
// Wait for the ACK character '+' from GDB here and handle
// receiving a ^C instead. This is the reason for this clause
if (!hal_diag_read_serial(&c1))
continue; // No response - try sending packet again
- if ( c1 == '+' )
+ if (c1 == '+')
break; // a good acknowledge
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
- if ( c1 == 3 ) {
- // Ctrl-C: breakpoint.
- cyg_hal_gdb_interrupt (__builtin_return_address(0));
- break;
+ if (c1 == 3) {
+ // Ctrl-C: breakpoint.
+ cyg_hal_gdb_interrupt (__builtin_return_address(0));
+ break;
}
#endif
// otherwise, loop round again
//####ECOSGPLCOPYRIGHTEND####
//========================================================================*/
+#include <stdlib.h>
#include <redboot.h>
#include <string.h>
#include <pkgconf/hal.h>
*/
memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
- /* Actual Virtual Size Attributes Function */
+ /* Physical Virtual Size Attributes Function */
/* Base Base MB cached? buffered? access permissions */
/* xxx00000 xxx00000 */
X_ARM_MMU_SECTION(0x000, 0xF00, 0x001, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Boot Rom */
fec_gpio_init();
}
-static void tx27_raise_voltage(void)
+#define SOC_FBAC0_REG 0x10028800UL
+
+extern int fuse_blow(int bank, int row, int bit);
+
+#define SOC_I2C2_BASE UL(0x1001D000)
+
+/* Address offsets of the I2C registers */
+#define MXC_IADR 0x00 /* Address Register */
+#define MXC_IFDR 0x04 /* Freq div register */
+#define MXC_I2CR 0x08 /* Control regsiter */
+#define MXC_I2SR 0x0C /* Status register */
+#define MXC_I2DR 0x10 /* Data I/O register */
+
+/* Bit definitions of I2CR */
+#define MXC_I2CR_IEN 0x0080
+#define MXC_I2CR_IIEN 0x0040
+#define MXC_I2CR_MSTA 0x0020
+#define MXC_I2CR_MTX 0x0010
+#define MXC_I2CR_TXAK 0x0008
+#define MXC_I2CR_RSTA 0x0004
+
+/* Bit definitions of I2SR */
+#define MXC_I2SR_ICF 0x0080
+#define MXC_I2SR_IAAS 0x0040
+#define MXC_I2SR_IBB 0x0020
+#define MXC_I2SR_IAL 0x0010
+#define MXC_I2SR_SRW 0x0004
+#define MXC_I2SR_IIF 0x0002
+#define MXC_I2SR_RXAK 0x0001
+
+#define LP3972_SLAVE_ADDR 0x34
+
+static inline cyg_uint8 i2c_addr(cyg_uint8 addr, int rw)
+{
+ return (addr << 1) | !!rw;
+}
+
+static inline cyg_uint8 mx27_i2c_read(cyg_uint8 reg)
+{
+ cyg_uint16 val;
+ HAL_READ_UINT16(SOC_I2C2_BASE + reg, val);
+ return val;
+}
+
+static inline void mx27_i2c_write(cyg_uint8 reg, cyg_uint8 val)
+{
+ HAL_WRITE_UINT16(SOC_I2C2_BASE + reg, val);
+}
+
+static inline void mx27_i2c_set_reg(cyg_uint8 reg, cyg_uint8 set, cyg_uint8 clr)
+{
+ cyg_uint8 val = mx27_i2c_read(reg);
+ val = (val & ~clr) | set;
+ mx27_i2c_write(reg, val);
+}
+
+static void mx27_i2c_disable(void)
+{
+ /* disable I2C controller */
+ mx27_i2c_set_reg(MXC_I2CR, 0, MXC_I2CR_IEN);
+ /* disable I2C clock */
+ set_reg(SOC_CRM_PCCR0, 0, (1 << 17));
+}
+
+static int mx27_i2c_init(void)
+{
+ int ret;
+
+ /* configure PC5,PC6 as Primary Function */
+ set_reg(SOC_GPIOC_BASE + GPIO_GPR, 0, GPR_MASK(5) | GPR_MASK(6));
+ set_reg(SOC_GPIOC_BASE + GPIO_GIUS, 0, GPR_MASK(5) | GPR_MASK(6));
+
+ /* enable I2C clock */
+ set_reg(SOC_CRM_PCCR0, (1 << 17), 0);
+
+ /* setup I2C clock divider */
+ mx27_i2c_write(MXC_IFDR, 0x2c);
+ mx27_i2c_write(MXC_I2SR, 0);
+
+ /* enable I2C controller in master mode */
+ mx27_i2c_write(MXC_I2CR, MXC_I2CR_IEN);
+
+ ret = mx27_i2c_read(MXC_I2SR);
+ if (ret & MXC_I2SR_IBB) {
+ diag_printf("I2C bus busy\n");
+ mx27_i2c_disable();
+ return -EIO;
+ }
+ return 0;
+}
+
+static int mx27_i2c_wait_busy(int set)
+{
+ int ret;
+ const int max_loops = 100;
+ int retries = max_loops;
+
+ cyg_uint8 mask = set ? MXC_I2SR_IBB : 0;
+
+ while ((ret = mask ^ (mx27_i2c_read(MXC_I2SR) & MXC_I2SR_IBB)) && --retries > 0) {
+ HAL_DELAY_US(3);
+ }
+ if (ret != 0) {
+ diag_printf("i2c: Waiting for IBB to %s timed out\n", set ? "set" : "clear");
+ return -ETIMEDOUT;
+ }
+ return ret;
+}
+
+static int mx27_i2c_wait_tc(void)
+{
+ int ret;
+ const int max_loops = 1000;
+ int retries = max_loops;
+
+ while (!((ret = mx27_i2c_read(MXC_I2SR)) & MXC_I2SR_IIF) && --retries > 0) {
+ HAL_DELAY_US(3);
+ }
+ mx27_i2c_write(MXC_I2SR, 0);
+ if (!(ret & MXC_I2SR_IIF)) {
+ diag_printf("i2c: Wait for transfer completion timed out\n");
+ return -ETIMEDOUT;
+ }
+ if (ret & MXC_I2SR_ICF) {
+ if (mx27_i2c_read(MXC_I2CR) & MXC_I2CR_MTX) {
+ if (!(ret & MXC_I2SR_RXAK)) {
+ ret = 0;
+ } else {
+ diag_printf("i2c: No ACK received after writing data\n");
+ return -ENXIO;
+ }
+ }
+ }
+ return ret;
+}
+
+static int mx27_i2c_stop(void)
+{
+ int ret;
+
+ mx27_i2c_set_reg(MXC_I2CR, 0, MXC_I2CR_MSTA | MXC_I2CR_MTX);
+ ret = mx27_i2c_wait_busy(0);
+ return ret;
+}
+
+static int mx27_i2c_start(cyg_uint8 addr, int rw)
+{
+ int ret;
+
+ ret = mx27_i2c_init();
+ if (ret < 0) {
+ diag_printf("I2C bus init failed; cannot switch fuse programming voltage\n");
+ return ret;
+ }
+ mx27_i2c_set_reg(MXC_I2CR, MXC_I2CR_MSTA, 0);
+ ret = mx27_i2c_wait_busy(1);
+ if (ret == 0) {
+ mx27_i2c_set_reg(MXC_I2CR, MXC_I2CR_MTX, 0);
+ mx27_i2c_write(MXC_I2DR, i2c_addr(addr, rw));
+ ret = mx27_i2c_wait_tc();
+ if (ret < 0) {
+ mx27_i2c_stop();
+ }
+ }
+ return ret;
+}
+
+static int mx27_i2c_repeat_start(cyg_uint8 addr, int rw)
+{
+ int ret;
+
+ mx27_i2c_set_reg(MXC_I2CR, MXC_I2CR_RSTA, 0);
+ HAL_DELAY_US(3);
+ mx27_i2c_write(MXC_I2DR, i2c_addr(addr, rw));
+ ret = mx27_i2c_wait_tc();
+ if (ret < 0) {
+ mx27_i2c_stop();
+ }
+ return ret;
+}
+
+static int mx27_i2c_read_byte(void)
+{
+ int ret;
+
+ mx27_i2c_set_reg(MXC_I2CR, MXC_I2CR_TXAK, MXC_I2CR_MTX);
+ (void)mx27_i2c_read(MXC_I2DR); /* dummy read after address cycle */
+ ret = mx27_i2c_wait_tc();
+ mx27_i2c_stop();
+ if (ret < 0) {
+ return ret;
+ }
+ ret = mx27_i2c_read(MXC_I2DR);
+ return ret;
+}
+
+static int mx27_i2c_write_byte(cyg_uint8 data, int last)
+{
+ int ret;
+
+ mx27_i2c_set_reg(MXC_I2CR, MXC_I2CR_MTX, 0);
+ mx27_i2c_write(MXC_I2DR, data);
+ if ((ret = mx27_i2c_wait_tc()) < 0 || last) {
+ mx27_i2c_stop();
+ }
+ return ret;
+}
+
+static int lp3972_reg_read(cyg_uint8 reg)
+{
+ int ret;
+
+ ret = mx27_i2c_start(LP3972_SLAVE_ADDR, 0);
+ if (ret < 0) {
+ return ret;
+ }
+ ret = mx27_i2c_write_byte(reg, 0);
+ if (ret < 0) {
+ return ret;
+ }
+ ret = mx27_i2c_repeat_start(LP3972_SLAVE_ADDR, 1);
+ if (ret < 0) {
+ return ret;
+ }
+ ret = mx27_i2c_read_byte();
+ mx27_i2c_disable();
+ return ret;
+}
+
+static int lp3972_reg_write(cyg_uint8 reg, cyg_uint8 val)
{
-#if defined (CLOCK_399_133_66)
- /* Increase core voltage to 1.45 */
- setCoreVoltage(0x16);
-#endif
+ int ret;
+
+ ret = mx27_i2c_start(LP3972_SLAVE_ADDR, 0);
+ if (ret < 0) {
+ return ret;
+ }
+ ret = mx27_i2c_write_byte(reg, 0);
+ if (ret < 0) {
+ return ret;
+ }
+ ret = mx27_i2c_write_byte(val, 1);
+ mx27_i2c_disable();
+ return ret;
}
-RedBoot_init(tx27_raise_voltage, RedBoot_INIT_PRIO(101));
+int tx27_mac_addr_program(unsigned char mac_addr[ETHER_ADDR_LEN])
+{
+ int ret = 0;
+ int i;
+
+ for (i = 0; i < ETHER_ADDR_LEN; i++) {
+ unsigned char fuse = readl(SOC_FEC_MAC_BASE2 + (i << 2));
+
+ if ((fuse | mac_addr[i]) != mac_addr[i]) {
+ diag_printf("MAC address fuse cannot be programmed: fuse[%d]=0x%02x -> 0x%02x\n",
+ i, fuse, mac_addr[i]);
+ return -1;
+ }
+ if (fuse != mac_addr[i]) {
+ ret = 1;
+ }
+ }
+ if (ret == 0) {
+ return ret;
+ }
+ ret = lp3972_reg_write(0x39, 0xf0);
+ if (ret < 0) {
+ diag_printf("Failed to switch fuse programming voltage\n");
+ return ret;
+ }
+ ret = lp3972_reg_read(0x39);
+ if (ret != 0xf0) {
+ diag_printf("Failed to switch fuse programming voltage\n");
+ return ret;
+ }
+ for (i = 0; i < ETHER_ADDR_LEN; i++) {
+ int bit;
+ unsigned char fuse = readl(SOC_FEC_MAC_BASE2 + (i << 2));
+
+ for (bit = 0; bit < 8; bit++) {
+ if (((mac_addr[i] >> bit) & 0x1) == 0)
+ continue;
+ if (((mac_addr[i] >> bit) & 1) == ((fuse >> bit) & 1)) {
+ continue;
+ }
+ if (fuse_blow(0, i + 5, bit)) {
+ diag_printf("Failed to blow fuse bank 0 row %d bit %d\n",
+ i, bit);
+ ret = -1;
+ goto out;
+ }
+ }
+ }
+ /* would like to blow the MAC_ADDR_LOCK fuse, but that's not available on MX27 */
+ //fuse_blow(0, 0, SOC_MAC_ADDR_LOCK_BIT);
+out:
+ lp3972_reg_write(0x39, 0);
+ return ret;
+}
#include CYGHWR_MEMORY_LAYOUT_H
}
}
+static unsigned long random;
+extern unsigned int hal_timer_count(void);
+/* provide at least _some_ sort of randomness */
+static void random_init(void)
+{
+ do {
+ srand(random + hal_timer_count());
+ random = rand();
+ } while ((hal_timer_count() < 5) || (hal_timer_count() & 0x47110815));
+}
+RedBoot_init(random_init, RedBoot_INIT_FIRST);
+
+#define WDOG_WRSR ((CYG_WORD16 *)0x10002004)
static void display_board_type(void)
{
+ char *reset_cause;
+ CYG_WORD16 wrsr;
+
diag_printf("\nBoard Type: Ka-Ro TX27\n");
+ HAL_READ_UINT16(WDOG_WRSR, wrsr);
+ switch (wrsr) {
+ case (1 << 4):
+ reset_cause = "POWER_ON RESET";
+ break;
+ case (1 << 3):
+ reset_cause = "EXTERNAL RESET";
+ break;
+ case (1 << 1):
+ reset_cause = "WATCHDOG RESET";
+ break;
+ case (1 << 0):
+ reset_cause = "SOFT RESET";
+ break;
+ default:
+ reset_cause = "UNKNOWN";
+ }
+ diag_printf("Last RESET cause: %s\n", reset_cause);
}
static void display_board_info(void)
}
RedBoot_init(display_board_info, RedBoot_INIT_LAST);
-// ------------------------------------------------------------------------
-//==-*- c-basic-offset: 4; tab-width: 4; -*-================================
+//==========================================================================
//
// hal_soc.h
//
#include <cyg/hal/mx27_pins.h>
#ifdef __ASSEMBLER__
-
+#define UL(a) (a)
#define REG8_VAL(a) (a)
#define REG16_VAL(a) (a)
#define REG32_VAL(a) (a)
#else /* __ASSEMBLER__ */
+#define UL(a) (a##UL)
+
extern char HAL_PLATFORM_EXTRA[];
#define REG8_VAL(a) ((unsigned char)(a))
#define REG16_VAL(a) ((unsigned short)(a))
#endif /* __ASSEMBLER__ */
-// Default Memory Layout Definitions
+/*
+ * Default Memory Layout Definitions
+ */
-#define SOC_AIPI1_BASE 0x10000000
-#define SOC_AIPI2_BASE 0x10020000
+#define SOC_AIPI1_BASE UL(0x10000000)
+#define SOC_AIPI2_BASE UL(0x10020000)
#define SOC_AIPI_PAR_OFF 8
#define CSPI2_BASE_ADDR (SOC_AIPI1_BASE + 0x0F000)
#define CSPI3_BASE_ADDR (SOC_AIPI1_BASE + 0x17000)
-#define SOC_CRM_BASE 0x10027000
+#define SOC_CRM_BASE UL(0x10027000)
#define SOC_CRM_CSCR (SOC_CRM_BASE + 0x0)
#define SOC_CRM_MPCTL0 (SOC_CRM_BASE + 0x4)
#define SOC_CRM_MPCTL1 (SOC_CRM_BASE + 0x8)
#endif
#endif
-// PD MFD MFI MFN
-#define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn) (((pd-1)<<26) + ((fd-1)<<16) + (fi<<10) + (fn<<0))
+// PD MFD MFI MFN
+#define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn) ((((pd)-1)<<26) + (((fd)-1)<<16) + ((fi)<<10) + (((fn) & 0x3ff) << 0))
#if (PLL_REF_CLK == FREQ_32768HZ)
#define PLL_REF_CLK_32768HZ
// SPCTL0 for 240 MHz
#define CRM_SPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 124, 7, 19)
#define CRM_SPCTL0_VAL_27MHZ CRM_SPCTL0_VAL
- #define CRM_SPCTL0_VAL2 CRM_PLL_PCTL_PARAM(2, 59, 7, 9)
+ #define CRM_SPCTL0_VAL2 CRM_PLL_PCTL_PARAM(2, 755, 11, -205)
#define CRM_SPCTL0_VAL2_27MHZ CRM_SPCTL0_VAL2
#if defined (CLOCK_266_133_66)
#define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 400, 7, 371)
#endif // PLL_REF_CLK == FREQ_26MHZ
// system control
-#define SOC_SYSCTRL_BASE 0x10027800
+#define SOC_SYSCTRL_BASE UL(0x10027800)
#define SOC_SYSCTRL_CID (SOC_SYSCTRL_BASE + 0x00)
#define SOC_SYSCTRL_FMCR (SOC_SYSCTRL_BASE + 0x14)
#define FMCR_FMS (1 << 5)
#define SOC_SYSCTRL_DCVR3 (SOC_SYSCTRL_BASE + 0x70)
// Interrupt Controller Register Definitions.
-#define SOC_AITC_BASE 0x10040000
+#define SOC_AITC_BASE UL(0x10040000)
#define SOC_AITC_INTCNTL (SOC_AITC_BASE + 0x00)
#define SOC_AITC_NIMASK (SOC_AITC_BASE + 0x04)
#define SOC_AITC_INTENNUM (SOC_AITC_BASE + 0x08)
#define UART_WIDTH_32
// UART Base Addresses
-#define SOC_UART1_BASE 0x1000A000
-#define SOC_UART2_BASE 0x1000B000
-#define SOC_UART3_BASE 0x1000C000
-#define SOC_UART4_BASE 0x1000D000
-#define SOC_UART5_BASE 0x1001B000
-#define SOC_UART6_BASE 0x1001C000
-
-#define SOC_MAX_BASE 0x1003F000
+#define SOC_UART1_BASE UL(0x1000A000)
+#define SOC_UART2_BASE UL(0x1000B000)
+#define SOC_UART3_BASE UL(0x1000C000)
+#define SOC_UART4_BASE UL(0x1000D000)
+#define SOC_UART5_BASE UL(0x1001B000)
+#define SOC_UART6_BASE UL(0x1001C000)
+
+#define SOC_MAX_BASE UL(0x1003F000)
// Slave port base offset
#define MAX_SLAVE_PORT0_OFFSET 0x0
#define MAX_SLAVE_PORT1_OFFSET 0x100
/*
* MX27 GPIO Register Definitions
*/
-#define SOC_GPIOA_BASE 0x10015000
-#define SOC_GPIOB_BASE 0x10015100
-#define SOC_GPIOC_BASE 0x10015200
-#define SOC_GPIOD_BASE 0x10015300
-#define SOC_GPIOE_BASE 0x10015400
-#define SOC_GPIOF_BASE 0x10015500
-#define SOC_GPIO_PMASK 0x10015600
+#define SOC_GPIOA_BASE UL(0x10015000)
+#define SOC_GPIOB_BASE UL(0x10015100)
+#define SOC_GPIOC_BASE UL(0x10015200)
+#define SOC_GPIOD_BASE UL(0x10015300)
+#define SOC_GPIOE_BASE UL(0x10015400)
+#define SOC_GPIOF_BASE UL(0x10015500)
+#define SOC_GPIO_PMASK UL(0x10015600)
#define GPIO_DDIR 0x0 /* Data direction reg */
#define GPIO_OCR1 0x4 /* Output config reg 1 */
#define GPIO_OCR2 0x8 /* Output config reg 2 */
*/
#define HAL_DELAY_TIMER SOC_GPT2_BASE // use timer2 for hal_delay_us()
-#define SOC_GPT1_BASE 0x10003000
-#define SOC_GPT2_BASE 0x10004000
-#define SOC_GPT3_BASE 0x10005000
-#define SOC_GPT4_BASE 0x10019000
-#define SOC_GPT5_BASE 0x1001A000
-#define SOC_GPT6_BASE 0x1001F000
+#define SOC_GPT1_BASE UL(0x10003000)
+#define SOC_GPT2_BASE UL(0x10004000)
+#define SOC_GPT3_BASE UL(0x10005000)
+#define SOC_GPT4_BASE UL(0x10019000)
+#define SOC_GPT5_BASE UL(0x1001A000)
+#define SOC_GPT6_BASE UL(0x1001F000)
#define GPT_TCTL_OFFSET 0x0
#define GPT_TPRER_OFFSET 0x4
#define GPT_TCMP_OFFSET 0x8
#define MX_STARTUP_DELAY (1000000 / 10) // 0.1s delay to get around the ethernet reset failure problem
#define TIMER_PRESCALER 3
-#define SOC_SI_ID_REG 0x10027800
+#define SOC_SI_ID_REG UL(0x10027800)
#define SOC_SILICONID_Rev1_0 0x0
#define SOC_SILICONID_Rev2_0 0x1
#define SOC_SILICONID_Rev2_1 0x2
#define CHIP_REV_3_1 4
#define CHIP_REV_unknown 0x100
-#define SOC_WDOG_BASE 0x10002000
+#define SOC_WDOG_BASE UL(0x10002000)
#define WDOG_BASE_ADDR SOC_WDOG_BASE
-#define NFC_BASE 0xD8000000
-#define SOC_ESDCTL_BASE 0xD8001000
-#define SOC_EIM_BASE 0xD8002000
-#define SOC_M3IF_BASE 0xD8003000
-#define SOC_PCMCIA_BASE 0xD8004000
+#define NFC_BASE UL(0xD8000000)
+#define SOC_ESDCTL_BASE UL(0xD8001000)
+#define SOC_EIM_BASE UL(0xD8002000)
+#define SOC_M3IF_BASE UL(0xD8003000)
+#define SOC_PCMCIA_BASE UL(0xD8004000)
#define SOC_CS0_CTL_BASE SOC_EIM_BASE
#define SOC_CS1_CTL_BASE (SOC_EIM_BASE + 0x10)
#define CSWCR_OFFSET 0x60
// Memories
-#define SOC_CSD0_BASE 0xA0000000
-#define SOC_CSD1_BASE 0xB0000000
-#define SOC_CS0_BASE 0xC0000000
+#define SOC_CSD0_BASE UL(0xA0000000)
+#define SOC_CSD1_BASE UL(0xB0000000)
+#define SOC_CS0_BASE UL(0xC0000000)
#define CS0_BASE_ADDR SOC_CS0_BASE
-#define SOC_CS1_BASE 0xC8000000
-#define SOC_CS2_BASE 0xD0000000
-#define SOC_CS3_BASE 0xD2000000
-#define SOC_CS4_BASE 0xD4000000
-#define SOC_CS5_BASE 0xD6000000
+#define SOC_CS1_BASE UL(0xC8000000)
+#define SOC_CS2_BASE UL(0xD0000000)
+#define SOC_CS3_BASE UL(0xD2000000)
+#define SOC_CS4_BASE UL(0xD4000000)
+#define SOC_CS5_BASE UL(0xD6000000)
#define NAND_REG_BASE (NFC_BASE + 0xE00)
-#define SOC_IIM_BASE 0x10028000
-#define SOC_FEC_MAC_BASE 0x10028C04
-#define SOC_FEC_MAC_BASE2 0x10028814
-#define SOC_FEC_BASE 0x1002B000
+#define SOC_IIM_BASE UL(0x10028000)
+#define SOC_FEC_MAC_BASE UL(0x10028C04)
+#define SOC_FEC_MAC_BASE2 UL(0x10028814)
+#define SOC_FEC_BASE UL(0x1002B000)
#define IIM_BASE_ADDR SOC_IIM_BASE
/* IIM */
#define CHIP_REV_1_0 0x0 /* PASS 1.0 */
#define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0)
#define FDO_PAGE_SPARE_VAL 0x8
-#define MXC_NAND_BASE_DUMMY 0xE0000000
+#define MXC_NAND_BASE_DUMMY UL(0xE0000000)
#define NOR_FLASH_BOOT 0
#define NAND_FLASH_BOOT 0x10
#define SDRAM_NON_FLASH_BOOT 0x20
int gpio_request_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode);
void clock_spi_enable(unsigned int spi_clk);
-enum {
- MXC_NFC_V1,
- MXC_NFC_V2,
-};
-
-typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int);
+typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
#endif //#if !defined(__ASSEMBLER__)
//----------------------------------------------------------------------------
// Reset.
-#define HAL_PLATFORM_RESET() \
- CYG_MACRO_START \
- *(volatile unsigned long *)SOC_CRM_PCCR1 |= 0x01000000; \
- *(volatile unsigned short *)SOC_WDOG_BASE |= 0x4; \
- /* hang here forever if reset fails */ \
- while (1){} \
+#define HAL_PLATFORM_RESET() \
+ CYG_MACRO_START \
+ *(volatile unsigned long *)SOC_CRM_PCCR1 |= 0x01000000; \
+ *(volatile unsigned short *)SOC_WDOG_BASE = \
+ (*(volatile unsigned short *)SOC_WDOG_BASE & ~(1 << 4)) | (1 << 2); \
+ /* hang here forever if reset fails */ \
+ while (1) { } \
CYG_MACRO_END
// Fallback (never really used)
#define MXC_PERCLK_NUM 4
RedBoot_cmd("clock",
- "Setup/Display clock (max AHB=133MHz, max IPG=66.5MHz)\nSyntax:",
-
"[<core clock in MHz> [:<AHB-to-core divider>[:<IPG-to-AHB divider>]]] \n\n\
+ "Setup/Display clock (max AHB=133MHz, max IPG=66.5MHz)\nSyntax:",
+ "[<core clock in MHz> [:<AHB-to-core divider>[:<IPG-to-AHB divider>]]] \n\n\
If a divider is zero or no divider is specified, the optimal divider values \n\
will be chosen. Examples:\n\
[clock] -> Show various clocks\n\
[clock 350] -> Core=350 AHB=117 IPG=58.5\n\
[clock 266:4] -> Core=266 AHB=66.5(Core/4) IPG=66.5\n\
[clock 266:4:2] -> Core=266 AHB=66.5(Core/4) IPG=33.25(AHB/2)\n",
- clock_setup
- );
+ clock_setup
+ );
/*!
* This is to calculate various parameters based on reference clock and
*
* @return 0 if successful; non-zero otherwise.
*/
-int calc_pll_params(u32 ref, u32 target, u32 *p_pd,
- u32 *p_mfi, u32 *p_mfn, u32 *p_mfd)
+int calc_pll_params(u32 ref, u32 target, int *p_pd,
+ int *p_mfi, int *p_mfn, int *p_mfd)
{
- u64 pd, mfi, mfn, n_target = (u64)target, n_ref = (u64)ref;
+ int pd, mfi, mfn;
+ u64 n_target = target, n_ref = ref;
if (g_clock_src == FREQ_26MHZ) {
- pll_mfd_fixed = 26 * 16;
+ pll_mfd_fixed = 26 * 16;
} else if (g_clock_src == FREQ_27MHZ) {
- pll_mfd_fixed = 27 * 16;
+ pll_mfd_fixed = 27 * 16;
} else {
- pll_mfd_fixed = 512;
+ pll_mfd_fixed = 512;
}
// Make sure targeted freq is in the valid range. Otherwise the
// following calculation might be wrong!!!
if (target < PLL_FREQ_MIN || target > PLL_FREQ_MAX) {
- return ERR_WRONG_CLK;
+ return ERR_WRONG_CLK;
}
// Use n_target and n_ref to avoid overflow
for (pd = 1; pd <= PLL_PD_MAX; pd++) {
- mfi = (n_target * pd) / (2 * n_ref);
- if (mfi > PLL_MFI_MAX) {
- return ERR_NO_MFI;
- } else if (mfi < PLL_MFI_MIN) {
- continue;
- }
- break;
+ mfi = (n_target * pd) / (2 * n_ref);
+ if (mfi > PLL_MFI_MAX) {
+ return ERR_NO_MFI;
+ } else if (mfi < PLL_MFI_MIN) {
+ continue;
+ }
+ break;
}
// Now got pd and mfi already
mfn = (((n_target * pd) / 2 - n_ref * mfi) * pll_mfd_fixed) / n_ref;
// Check mfn within limit and mfn < denominator
if (sys_ver == SOC_SILICONID_Rev1_0) {
- if (mfn > PLL_MFN_MAX || mfn >= pll_mfd_fixed) {
- return ERR_NO_MFN;
- }
+ if (mfn < 0 || mfn > PLL_MFN_MAX || mfn >= pll_mfd_fixed) {
+ return ERR_NO_MFN;
+ }
} else {
- if (mfn > PLL_MFN_MAX_2 || mfn >= pll_mfd_fixed) {
- return ERR_NO_MFN;
- }
+ if (mfn < -PLL_MFN_MAX_2 || mfn > PLL_MFN_MAX_2 || mfn >= pll_mfd_fixed) {
+ return ERR_NO_MFN;
+ }
}
if (pd > PLL_PD_MAX) {
- return ERR_NO_PD;
+ return ERR_NO_PD;
}
- *p_pd = (u32)pd;
- *p_mfi = (u32)mfi;
- *p_mfn = (u32)mfn;
+ *p_pd = pd;
+ *p_mfi = mfi;
+ *p_mfn = mfn;
*p_mfd = pll_mfd_fixed;
return 0;
}
* (ipg_div - 1) needs to be set in the register
# @return 0 if successful; non-zero otherwise
*/
+#define CMD_CLOCK_DEBUG
int configure_clock(u32 ref, u32 core_clk, u32 ahb_div, u32 ipg_div)
{
- u32 pll, presc = 1, pd, mfi, mfn, mfd, brmo = 1, cscr, mpctl0;
+ u32 pll, presc = 1;
+ int pd, mfi, mfn, mfd;
+ u32 cscr, mpctl0;
u32 pcdr0, nfc_div, hdiv, nfc_div_factor;
u32 per_div[MXC_PERCLK_NUM];
int ret, i, arm_src = 0;
per_clk_old[1] = get_peri_clock(PER_CLK2);
per_clk_old[2] = get_peri_clock(PER_CLK3);
per_clk_old[3] = get_peri_clock(PER_CLK4);
-
+diag_printf("per1=%9u\n", per_clk_old[0]);
+diag_printf("per2=%9u\n", per_clk_old[1]);
+diag_printf("per3=%9u\n", per_clk_old[2]);
+diag_printf("per4=%9u\n", per_clk_old[3]);
// assume pll default to core clock first
if (sys_ver == SOC_SILICONID_Rev1_0) {
- pll = core_clk;
- nfc_div_factor = 1;
+ pll = core_clk;
+ nfc_div_factor = 1;
} else {
- if (core_clk > (266 * SZ_DEC_1M)) {
- pll = core_clk;
- arm_src = 1;
- } else {
- pll = core_clk * 3 / 2;
- }
- nfc_div_factor = ahb_div;
+ if (core_clk > 266 * SZ_DEC_1M) {
+ pll = core_clk;
+ arm_src = 1;
+ } else {
+ pll = core_clk * 3 / 2;
+ }
+ nfc_div_factor = ahb_div;
}
// when core_clk >= PLL_FREQ_MIN, the presc can be 1.
// Otherwise, need to calculate presc value below and adjust the targeted pll
if (pll < PLL_FREQ_MIN) {
- int presc_max;
- if(sys_ver == SOC_SILICONID_Rev1_0) {
- presc_max = PRESC_MAX;
- } else {
- presc_max = ARM_DIV_MAX;
- }
-
- for (presc = 1; presc <= presc_max; presc++) {
- if ((pll * presc) > PLL_FREQ_MIN) {
- break;
- }
- }
- if (presc == (presc_max + 1)) {
- diag_printf("can't make presc=%d\n", presc);
- return ERR_NO_PRESC;
- }
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- pll = core_clk * presc;
- } else {
- pll = 3 * core_clk * presc / 2;
- }
+ int presc_max;
+
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ presc_max = PRESC_MAX;
+ } else {
+ presc_max = ARM_DIV_MAX;
+ }
+
+ for (presc = 1; presc <= presc_max; presc++) {
+ if (pll * presc > PLL_FREQ_MIN) {
+ break;
+ }
+ }
+ if (presc == presc_max + 1) {
+ diag_printf("can't make presc=%d\n", presc);
+ return ERR_NO_PRESC;
+ }
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ pll = core_clk * presc;
+ } else {
+ pll = 3 * core_clk * presc / 2;
+ }
}
// pll is now the targeted pll output. Use it along with ref input clock
// to get pd, mfi, mfn, mfd
if ((ret = calc_pll_params(ref, pll, &pd, &mfi, &mfn, &mfd)) != 0) {
#ifdef CMD_CLOCK_DEBUG
- diag_printf("can't find pll parameters: %d\n", ret);
+ diag_printf("can't find pll parameters: %d\n", ret);
#endif
- return ret;
+ return ret;
}
#ifdef CMD_CLOCK_DEBUG
diag_printf("ref=%d, pll=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
- ref, pll, pd, mfi, mfn, mfd);
+ ref, pll, pd, mfi, mfn, mfd);
#endif
// blindly increase divider first to avoid too fast ahbclk and ipgclk
// in case the core clock increases too much
cscr = readl(SOC_CRM_CSCR);
if (sys_ver == SOC_SILICONID_Rev1_0) {
- hdiv = (pll + AHB_CLK_MAX -1) / AHB_CLK_MAX;
- cscr = (cscr & ~(0x0000FF00)) | ((hdiv - 1) << 9) | (1 << 8);
+ hdiv = (pll + AHB_CLK_MAX - 1) / AHB_CLK_MAX;
+ cscr = (cscr & ~0x0000FF00) | ((hdiv - 1) << 9) | (1 << 8);
} else {
- if (core_clk > (266 * SZ_DEC_1M)) {
- hdiv = (pll + AHB_CLK_MAX - 1) / AHB_CLK_MAX;
- } else {
- hdiv = (2 * pll + 3 * AHB_CLK_MAX - 1) / (3 * AHB_CLK_MAX);
- }
- cscr = (cscr & ~(0x0000FF00)) | ((hdiv - 1) << 8);
+ if (core_clk > 266 * SZ_DEC_1M) {
+ hdiv = (pll + AHB_CLK_MAX - 1) / AHB_CLK_MAX;
+ } else {
+ hdiv = (2 * pll + 3 * AHB_CLK_MAX - 1) / (3 * AHB_CLK_MAX);
+ }
+ cscr = (cscr & ~0x0000FF00) | ((hdiv - 1) << 8);
}
writel(cscr, SOC_CRM_CSCR);
// update PLL register
- if ((mfd < (10 * mfn)) && ((10 * mfn) < (9 * mfd)))
- brmo = 0;
- if (brmo != 0)
- writel(1 << 6, SOC_CRM_MPCTL1);
+ if (!((mfd < 10 * mfn) && (10 * mfn < 9 * mfd)))
+ writel(1 << 6, SOC_CRM_MPCTL1);
mpctl0 = readl(SOC_CRM_MPCTL0);
mpctl0 = (mpctl0 & 0xC000C000) |
- CPLM_SETUP |
- ((pd - 1) << 26) |
- ((mfd - 1) << 16) |
- (mfi << 10) |
- mfn;
+ CPLM_SETUP |
+ ((pd - 1) << 26) |
+ ((mfd - 1) << 16) |
+ (mfi << 10) |
+ mfn;
writel(mpctl0, SOC_CRM_MPCTL0);
// restart mpll
cscr &= ~0x0000FF00;
if (sys_ver == SOC_SILICONID_Rev1_0) {
- cscr |= ((presc - 1) << 13) | ((ahb_div - 1) << 9) | ((ipg_div - 1) << 8);
+ cscr |= ((presc - 1) << 13) | ((ahb_div - 1) << 9) | ((ipg_div - 1) << 8);
} else {
- cscr |= (arm_src << 15) | ((presc - 1) << 12) | ((ahb_div - 1) << 8);
+ cscr |= (arm_src << 15) | ((presc - 1) << 12) | ((ahb_div - 1) << 8);
}
writel(cscr, SOC_CRM_CSCR);
// Make sure optimal NFC clock but less than NFC_CLK_MAX
for (nfc_div = 1; nfc_div <= 16; nfc_div++) {
- if ((core_clk / (nfc_div_factor * nfc_div)) <= NFC_CLK_MAX) {
- break;
- }
+ if ((core_clk / (nfc_div_factor * nfc_div)) <= NFC_CLK_MAX) {
+ break;
+ }
}
pcdr0 = readl(SOC_CRM_PCDR0);
- if(sys_ver == SOC_SILICONID_Rev1_0) {
- writel(((pcdr0 & 0xFFFF0FFF) | ((nfc_div - 1) << 12)),
- SOC_CRM_PCDR0);
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ writel(((pcdr0 & 0xFFFF0FFF) | ((nfc_div - 1) << 12)),
+ SOC_CRM_PCDR0);
} else {
- writel(((pcdr0 & 0xFFFFF3CF) | ((nfc_div - 1) << 6)),
- SOC_CRM_PCDR0);
+ writel(((pcdr0 & 0xFFFFF3CF) | ((nfc_div - 1) << 6)),
+ SOC_CRM_PCDR0);
}
- if(sys_ver == SOC_SILICONID_Rev1_0) {
- pll = pll_clock(MCU_PLL) + 500000;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ pll = pll_clock(MCU_PLL) + 500000;
} else {
- if (core_clk > (266 * SZ_DEC_1M)) {
- pll = pll_clock(MCU_PLL) + 500000;
- } else {
- pll = 2 * pll_clock(MCU_PLL) / 3 + 500000;
- }
+ if (core_clk > (266 * SZ_DEC_1M)) {
+ pll = pll_clock(MCU_PLL) + 500000;
+ } else {
+ pll = 2 * pll_clock(MCU_PLL) / 3 + 500000;
+ }
}
for (i = 0; i < MXC_PERCLK_NUM; i++) {
- per_div[i] = (pll / per_clk_old[i]) - 1;
+ per_div[i] = (pll / per_clk_old[i]) - 1;
}
writel((per_div[3] << 24) | (per_div[2] << 16) | (per_div[1] << 8) |
- (per_div[0]), SOC_CRM_PCDR1);
+ (per_div[0]), SOC_CRM_PCDR1);
return 0;
}
int ret;
if (argc == 1)
- goto print_clock;
+ goto print_clock;
if (g_clock_src == FREQ_27MHZ) {
- diag_printf("Error: clock setup is not supported for 27MHz source\n\n");
- return;
+ diag_printf("Error: clock setup is not supported for 27MHz source\n\n");
+ return;
}
for (i = 0; i < 3; i++) {
- if (!parse_num(argv[1], &temp, &argv[1], ":")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
- data[i] = temp;
+ if (!parse_num(argv[1], &temp, &argv[1], ":")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ data[i] = temp;
}
core_clk = data[0] * SZ_DEC_1M;
ahb_div = data[1]; // actual register field + 1
ipg_div = data[2]; // actual register field + 1
- if(sys_ver == SOC_SILICONID_Rev1_0) {
- presc_max = PRESC_MAX;
- ahb_div_max = AHB_DIV_MAX;
- pll = core_clk;
- ahb_clk_in = core_clk;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ presc_max = PRESC_MAX;
+ ahb_div_max = AHB_DIV_MAX;
+ pll = core_clk;
+ ahb_clk_in = core_clk;
} else {
- presc_max = ARM_DIV_MAX;
- ahb_div_max = AHB_DIV_MAX / ARM_DIV_MAX;
- if (core_clk > (266 * SZ_DEC_1M)) {
- pll = core_clk;
- ahb_clk_in = core_clk * 2 / 3;
- } else {
- pll = 3 * core_clk / 2;
- ahb_clk_in = core_clk;
- }
- ipg_div = 2;
+ presc_max = ARM_DIV_MAX;
+ ahb_div_max = AHB_DIV_MAX / ARM_DIV_MAX;
+ if (core_clk > (266 * SZ_DEC_1M)) {
+ pll = core_clk;
+ ahb_clk_in = core_clk * 2 / 3;
+ } else {
+ pll = 3 * core_clk / 2;
+ ahb_clk_in = core_clk;
+ }
+ ipg_div = 2;
}
if (pll < (PLL_FREQ_MIN / presc_max) || pll > PLL_FREQ_MAX) {
- diag_printf("Targeted core clock should be within [%d - %d]\n",
- PLL_FREQ_MIN / presc_max, PLL_FREQ_MAX);
- return;
+ diag_printf("Targeted core clock should be within [%d - %d]\n",
+ PLL_FREQ_MIN / presc_max, PLL_FREQ_MAX);
+ return;
}
// find the ahb divider
if (ahb_div > ahb_div_max) {
- diag_printf("Invalid AHB divider: %d. Maximum value is %d\n",
- ahb_div, ahb_div_max);
- return;
+ diag_printf("Invalid AHB divider: %d. Maximum value is %d\n",
+ ahb_div, ahb_div_max);
+ return;
}
if (ahb_div == 0) {
- // no AHBCLK divider specified
- for (ahb_div = 1; ; ahb_div++) {
- if ((ahb_clk_in / ahb_div) <= AHB_CLK_MAX) {
- break;
- }
- }
+ // no AHBCLK divider specified
+ for (ahb_div = 1; ; ahb_div++) {
+ if ((ahb_clk_in / ahb_div) <= AHB_CLK_MAX) {
+ break;
+ }
+ }
}
if (ahb_div > ahb_div_max || (ahb_clk_in / ahb_div) > AHB_CLK_MAX) {
- diag_printf("Can't make AHB=%d since max=%d\n",
- core_clk / ahb_div, AHB_CLK_MAX);
- return;
+ diag_printf("Can't make AHB=%d since max=%d\n",
+ core_clk / ahb_div, AHB_CLK_MAX);
+ return;
}
// find the ipg divider
ahb_clk = ahb_clk_in / ahb_div;
if (ipg_div > IPG_DIV_MAX) {
- diag_printf("Invalid IPG divider: %d. Maximum value is %d\n",
- ipg_div, IPG_DIV_MAX);
- return;
+ diag_printf("Invalid IPG divider: %d. Maximum value is %d\n",
+ ipg_div, IPG_DIV_MAX);
+ return;
}
if (ipg_div == 0) {
- ipg_div++; // At least =1
- if (ahb_clk > IPG_CLK_MAX)
- ipg_div++; // Make it =2
+ ipg_div++; // At least =1
+ if (ahb_clk > IPG_CLK_MAX)
+ ipg_div++; // Make it =2
}
if (ipg_div > IPG_DIV_MAX || (ahb_clk / ipg_div) > IPG_CLK_MAX) {
- diag_printf("Can't make IPG=%d since max=%d\n",
- (ahb_clk / ipg_div), IPG_CLK_MAX);
- return;
+ diag_printf("Can't make IPG=%d since max=%d\n",
+ (ahb_clk / ipg_div), IPG_CLK_MAX);
+ return;
}
ipg_clk = ahb_clk / ipg_div;
diag_printf("Trying to set core=%d ahb=%d ipg=%d...\n",
- core_clk, ahb_clk, ipg_clk);
+ core_clk, ahb_clk, ipg_clk);
// stop the serial to be ready to adjust the clock
hal_delay_us(100000);
hal_delay_us(100000);
if (ret != 0) {
- diag_printf("Failed to setup clock: %d\n", ret);
- return;
+ diag_printf("Failed to setup clock: %d\n", ret);
+ return;
}
// check for new per clock settings and warn user if there is a change.
if (per_clk_old[0] != get_peri_clock(PER_CLK1)) {
- diag_printf("New per_clk1 changed! Old freq is %d\n", per_clk_old[0]);
+ diag_printf("per_clk1 changed; old clock was: %u\n", per_clk_old[0]);
}
if (per_clk_old[1] != get_peri_clock(PER_CLK2)) {
- diag_printf("New per_clk2 changed! Old freq is %d\n", per_clk_old[1]);
+ diag_printf("per_clk2 changed; old clock was: %u\n", per_clk_old[1]);
}
if (per_clk_old[2] != get_peri_clock(PER_CLK3)) {
- diag_printf("New per_clk3 changed! Old freq is %d\n", per_clk_old[2]);
+ diag_printf("per_clk3 changed; old clock was: %u\n", per_clk_old[2]);
}
if (per_clk_old[3] != get_peri_clock(PER_CLK4)) {
- diag_printf("New per_clk4 changed! Old freq is %d\n", per_clk_old[3]);
+ diag_printf("per_clk4 changed; old clock was: %u\n", per_clk_old[3]);
}
diag_printf("\n<<<New clock setting>>>\n");
diag_printf("CPU\t\tAHB\t\tIPG\t\tNFC\t\tUSB\n");
diag_printf("========================================================================\n");
diag_printf("%-16d%-16d%-16d%-16d%-16d\n\n",
- get_main_clock(CPU_CLK),
- get_main_clock(AHB_CLK),
- get_main_clock(IPG_CLK),
- get_main_clock(NFC_CLK),
- get_main_clock(USB_CLK));
+ get_main_clock(CPU_CLK),
+ get_main_clock(AHB_CLK),
+ get_main_clock(IPG_CLK),
+ get_main_clock(NFC_CLK),
+ get_main_clock(USB_CLK));
diag_printf("PER1\t\tPER2\t\tPER3\t\tPER4\n");
diag_printf("===========================================");
diag_printf("=============\n");
diag_printf("%-16d%-16d%-16d%-16d\n\n",
- get_peri_clock(PER_CLK1),
- get_peri_clock(PER_CLK2),
- get_peri_clock(PER_CLK3),
- get_peri_clock(PER_CLK4));
+ get_peri_clock(PER_CLK1),
+ get_peri_clock(PER_CLK2),
+ get_peri_clock(PER_CLK3),
+ get_peri_clock(PER_CLK4));
diag_printf("H264\t\tMSHC\t\tSSI1\t\tSSI2\n");
diag_printf("========================================================\n");
diag_printf("%-16d%-16d%-16d%-16d\n\n",
- get_peri_clock(H264_BAUD),
- get_peri_clock(MSHC_BAUD),
- get_peri_clock(SSI1_BAUD),
- get_peri_clock(SSI2_BAUD));
+ get_peri_clock(H264_BAUD),
+ get_peri_clock(MSHC_BAUD),
+ get_peri_clock(SSI1_BAUD),
+ get_peri_clock(SSI2_BAUD));
diag_printf("PERCLK: 1-<UART|GPT|PWM> 2-<SDHC|CSPI> 3-<LCDC> 4-<CSI>\n");
}
*/
u32 pll_clock(enum plls pll)
{
- u64 mfi, mfn, mfd, pdf, ref_clk, pll_out;
- u64 reg = readl(pll);
+ int mfi, mfn, mfd, pdf;
+ u32 pll_out;
+ u32 reg = readl(pll);
+ u64 ref_clk;
if ((pll == SER_PLL) && (sys_ver == SOC_SILICONID_Rev2_0)) {
- writel(reg, pll);
+ writel(reg, pll);
}
pdf = (reg >> 26) & 0xF;
mfd = (reg >> 16) & 0x3FF;
mfi = (reg >> 10) & 0xF;
- mfi = (mfi <= 5) ? 5: mfi;
+ if (mfi < 5) {
+ mfi = 5;
+ }
mfn = reg & 0x3FF;
-
+ if (mfn >= 512) {
+ mfn = 1024 - mfn;
+ }
ref_clk = g_clock_src;
pll_out = (2 * ref_clk * mfi + ((2 * ref_clk * mfn) / (mfd + 1))) /
- (pdf + 1);
+ (pdf + 1);
- return (u32)pll_out;
+ return pll_out;
}
/*!
u32 pcdr0 = readl(SOC_CRM_PCDR0);
if (sys_ver == SOC_SILICONID_Rev1_0) {
- presc = ((cscr >> CRM_CSCR_PRESC_OFFSET) & 0x7) + 1;
+ presc = ((cscr >> CRM_CSCR_PRESC_OFFSET) & 0x7) + 1;
} else {
- presc = ((cscr >> CRM_CSCR_ARM_OFFSET) & 0x3) + 1;
+ presc = ((cscr >> CRM_CSCR_ARM_OFFSET) & 0x3) + 1;
}
switch (clk) {
case CPU_CLK:
- if ((sys_ver == SOC_SILICONID_Rev1_0) || (cscr & CRM_CSCR_ARM_SRC)) {
- ret_val = pll_clock(MCU_PLL) / presc;
- } else {
- ret_val = 2 * pll_clock(MCU_PLL) / (3 * presc);
- }
- break;
+ if ((sys_ver == SOC_SILICONID_Rev1_0) || (cscr & CRM_CSCR_ARM_SRC)) {
+ ret_val = pll_clock(MCU_PLL) / presc;
+ } else {
+ ret_val = 2 * pll_clock(MCU_PLL) / (3 * presc);
+ }
+ break;
case AHB_CLK:
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ahb_div = ((cscr >> CRM_CSCR_BCLKDIV_OFFSET) & 0xF) + 1;
- ret_val = pll_clock(MCU_PLL) / (presc * ahb_div);
- } else {
- ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
- ret_val = 2*pll_clock(MCU_PLL) / (3*ahb_div);
- }
- break;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ahb_div = ((cscr >> CRM_CSCR_BCLKDIV_OFFSET) & 0xF) + 1;
+ ret_val = pll_clock(MCU_PLL) / (presc * ahb_div);
+ } else {
+ ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
+ ret_val = 2 * pll_clock(MCU_PLL) / (3 * ahb_div);
+ }
+ break;
case IPG_CLK:
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ahb_div = ((cscr >> CRM_CSCR_BCLKDIV_OFFSET) & 0xF) + 1;
- ipg_pdf = ((cscr >> CRM_CSCR_IPDIV_OFFSET) & 0x1) + 1;
- ret_val = pll_clock(MCU_PLL) / (presc * ahb_div * ipg_pdf);
- } else {
- ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
- ret_val = pll_clock(MCU_PLL) / (3*ahb_div);
- }
- break;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ahb_div = ((cscr >> CRM_CSCR_BCLKDIV_OFFSET) & 0xF) + 1;
+ ipg_pdf = ((cscr >> CRM_CSCR_IPDIV_OFFSET) & 0x1) + 1;
+ ret_val = pll_clock(MCU_PLL) / (presc * ahb_div * ipg_pdf);
+ } else {
+ ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
+ ret_val = pll_clock(MCU_PLL) / (3*ahb_div);
+ }
+ break;
case NFC_CLK:
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- nfc_div = ((pcdr0 >> 12) & 0xF) + 1;
- /* AHB/nfc_div */
- ret_val = pll_clock(MCU_PLL) / (presc * nfc_div);
- } else {
- nfc_div = ((pcdr0 >> 6) & 0xF) + 1;
- ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
- ret_val = 2*pll_clock(MCU_PLL) / (3*ahb_div*nfc_div);
- }
- break;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ nfc_div = ((pcdr0 >> 12) & 0xF) + 1;
+ /* AHB/nfc_div */
+ ret_val = pll_clock(MCU_PLL) / (presc * nfc_div);
+ } else {
+ nfc_div = ((pcdr0 >> 6) & 0xF) + 1;
+ ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
+ ret_val = 2*pll_clock(MCU_PLL) / (3 * ahb_div * nfc_div);
+ }
+ break;
case USB_CLK:
- usb_div = ((cscr >> CRM_CSCR_USB_DIV_OFFSET) & 0x7) + 1;
- ret_val = pll_clock(SER_PLL) / usb_div;
- break;
+ usb_div = ((cscr >> CRM_CSCR_USB_DIV_OFFSET) & 0x7) + 1;
+ ret_val = pll_clock(SER_PLL) / usb_div;
+ break;
default:
- diag_printf("Unknown clock: %d\n", clk);
- break;
+ diag_printf("Unknown clock: %d\n", clk);
+ break;
}
return ret_val;
}
switch (clk) {
case PER_CLK1:
- div = (pcdr1 & 0x3F) + 1;
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = pll_clock(MCU_PLL) / div;
- } else {
- ret_val = 2*pll_clock(MCU_PLL) / (3*div);
- }
- break;
+ div = (pcdr1 & 0x3F) + 1;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = pll_clock(MCU_PLL) / div;
+ } else {
+ ret_val = 2*pll_clock(MCU_PLL) / (3*div);
+ }
+ break;
case PER_CLK2:
case SPI1_CLK:
case SPI2_CLK:
- div = ((pcdr1 >> 8) & 0x3F) + 1;
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = pll_clock(MCU_PLL) / div;
- } else {
- ret_val = 2*pll_clock(MCU_PLL) / (3*div);
- }
- break;
+ div = ((pcdr1 >> 8) & 0x3F) + 1;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = pll_clock(MCU_PLL) / div;
+ } else {
+ ret_val = 2*pll_clock(MCU_PLL) / (3*div);
+ }
+ break;
case PER_CLK3:
- div = ((pcdr1 >> 16) & 0x3F) + 1;
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = pll_clock(MCU_PLL) / div;
- } else {
- ret_val = 2*pll_clock(MCU_PLL) / (3*div);
- }
- break;
+ div = ((pcdr1 >> 16) & 0x3F) + 1;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = pll_clock(MCU_PLL) / div;
+ } else {
+ ret_val = 2*pll_clock(MCU_PLL) / (3*div);
+ }
+ break;
case PER_CLK4:
- div = ((pcdr1 >> 24) & 0x3F) + 1;
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = pll_clock(MCU_PLL) / div;
- } else {
- ret_val = 2*pll_clock(MCU_PLL) / (3*div);
- }
- break;
+ div = ((pcdr1 >> 24) & 0x3F) + 1;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = pll_clock(MCU_PLL) / div;
+ } else {
+ ret_val = 2*pll_clock(MCU_PLL) / (3*div);
+ }
+ break;
case SSI1_BAUD:
- div = (pcdr0 >> 16) & 0x3F;
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- if (div < 2) {
- div = 62 * 2;
- }
- } else {
- div += 4;
- }
- if ((cscr & (1 << 22)) != 0) {
- // This takes care of 0.5*SSIDIV[0] by x2
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = (2 * pll_clock(MCU_PLL)) / div;
- } else {
- ret_val = (4 * pll_clock(MCU_PLL)) / (3*div);
- }
- } else {
- ret_val = (2 * pll_clock(SER_PLL)) / div;
- }
- break;
+ div = (pcdr0 >> 16) & 0x3F;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ if (div < 2) {
+ div = 62 * 2;
+ }
+ } else {
+ div += 4;
+ }
+ if ((cscr & (1 << 22)) != 0) {
+ // This takes care of 0.5*SSIDIV[0] by x2
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = (2 * pll_clock(MCU_PLL)) / div;
+ } else {
+ ret_val = (4 * pll_clock(MCU_PLL)) / (3*div);
+ }
+ } else {
+ ret_val = (2 * pll_clock(SER_PLL)) / div;
+ }
+ break;
case SSI2_BAUD:
- div = (pcdr0 >> 26) & 0x3F;
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- if (div < 2) {
- div = 62 * 2;
- }
- } else {
- div += 4;
- }
- if ((cscr & (1 << 23)) != 0) {
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = (2 * pll_clock(MCU_PLL)) / div;
- } else {
- ret_val = (4 * pll_clock(MCU_PLL)) / (3*div);
- }
- } else {
- ret_val = (2 * pll_clock(SER_PLL)) / div;
- }
- break;
+ div = (pcdr0 >> 26) & 0x3F;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ if (div < 2) {
+ div = 62 * 2;
+ }
+ } else {
+ div += 4;
+ }
+ if ((cscr & (1 << 23)) != 0) {
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = (2 * pll_clock(MCU_PLL)) / div;
+ } else {
+ ret_val = (4 * pll_clock(MCU_PLL)) / (3*div);
+ }
+ } else {
+ ret_val = (2 * pll_clock(SER_PLL)) / div;
+ }
+ break;
case H264_BAUD:
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- div = (pcdr0 >> 8) & 0xF;
- if (div < 2) {
- div = 62 * 2;
- }
- } else {
- div = (pcdr0 >> 10) & 0x3F;
- div += 4;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ div = (pcdr0 >> 8) & 0xF;
+ if (div < 2) {
+ div = 62 * 2;
+ }
+ } else {
+ div = (pcdr0 >> 10) & 0x3F;
+ div += 4;
+ }
+ if ((cscr & (1 << 21)) != 0) {
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = (2 * pll_clock(MCU_PLL)) / div;
+ } else {
+ ret_val = (4 * pll_clock(MCU_PLL)) / (3*div);
+ }
+ } else {
+ ret_val = (2 * pll_clock(SER_PLL)) / div;
}
- if ((cscr & (1 << 21)) != 0) {
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = (2 * pll_clock(MCU_PLL)) / div;
- } else {
- ret_val = (4 * pll_clock(MCU_PLL)) / (3*div);
- }
- } else {
- ret_val = (2 * pll_clock(SER_PLL)) / div;
- }
- break;
+ break;
case MSHC_BAUD:
- if ((cscr & (1 << 20)) != 0) {
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- div = (pcdr0 & 0x1F) + 1;
- ret_val = pll_clock(MCU_PLL) / div;
- } else {
- div = (pcdr0 & 0x3F) + 1;
- ret_val = 2*pll_clock(MCU_PLL) / (3*div);
- }
- } else {
- div = (pcdr0 & 0x1F) + 1;
- ret_val = (2 * pll_clock(SER_PLL)) / div;
- }
- break;
+ if ((cscr & (1 << 20)) != 0) {
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ div = (pcdr0 & 0x1F) + 1;
+ ret_val = pll_clock(MCU_PLL) / div;
+ } else {
+ div = (pcdr0 & 0x3F) + 1;
+ ret_val = 2*pll_clock(MCU_PLL) / (3*div);
+ }
+ } else {
+ div = (pcdr0 & 0x1F) + 1;
+ ret_val = (2 * pll_clock(SER_PLL)) / div;
+ }
+ break;
default:
- diag_printf("%s(): This clock: %d not supported yet \n",
- __FUNCTION__, clk);
- break;
+ diag_printf("%s(): This clock: %d not supported yet \n",
+ __FUNCTION__, clk);
+ break;
}
return ret_val;
}
RedBoot_cmd("clko",
- "Select clock source for CLKO (TP1 on EVB or S3 Pin 1)",
- " The output clock is the actual clock source freq divided by 8. Default is FCLK\n\
- Note that the module clock will be turned on for reading!\n\
- <0> - display current clko selection \n\
- <1> - CLK32 \n\
- <2> - PREMCLK \n\
- <3> - CLK26M (may see nothing if 26MHz Crystal is not connected) \n\
- <4> - MPLL Reference CLK \n\
- <5> - SPLL Reference CLK \n\
- <6> - MPLL CLK \n\
- <7> - SPLL CLK \n\
- <8> - FCLK \n\
- <9> - AHBCLK \n\
- <10> - IPG_CLK (PERCLK) \n\
- <11> - PERCLK1 \n\
- <12> - PERCLK2 \n\
- <13> - PERCLK3 \n\
- <14> - PERCLK4 \n\
- <15> - SSI 1 Baud \n\
- <16> - SSI 2 Baud \n\
- <17> - NFC \n\
- <18> - MSHC Baud \n\
- <19> - H264 Baud \n\
- <20> - CLK60M Always \n\
- <21> - CLK32K Always \n\
- <22> - CLK60M \n\
- <23> - DPTC Ref",
- clko
- );
+ "Select clock source for CLKO (TP1 on EVB or S3 Pin 1)",
+ " The output clock is the actual clock source freq divided by 8. Default is FCLK\n\
+ Note that the module clock will be turned on for reading!\n\
+ <0> - display current clko selection \n\
+ <1> - CLK32 \n\
+ <2> - PREMCLK \n\
+ <3> - CLK26M (may see nothing if 26MHz Crystal is not connected) \n\
+ <4> - MPLL Reference CLK \n\
+ <5> - SPLL Reference CLK \n\
+ <6> - MPLL CLK \n\
+ <7> - SPLL CLK \n\
+ <8> - FCLK \n\
+ <9> - AHBCLK \n\
+ <10> - IPG_CLK (PERCLK) \n\
+ <11> - PERCLK1 \n\
+ <12> - PERCLK2 \n\
+ <13> - PERCLK3 \n\
+ <14> - PERCLK4 \n\
+ <15> - SSI 1 Baud \n\
+ <16> - SSI 2 Baud \n\
+ <17> - NFC \n\
+ <18> - MSHC Baud \n\
+ <19> - H264 Baud \n\
+ <20> - CLK60M Always \n\
+ <21> - CLK32K Always \n\
+ <22> - CLK60M \n\
+ <23> - DPTC Ref",
+ clko
+ );
static u8* clko_name[] ={
"NULL",
u32 action = 0, ccsr;
if (!scan_opts(argc, argv, 1, 0, 0, &action,
- OPTION_ARG_TYPE_NUM, "action"))
- return;
+ OPTION_ARG_TYPE_NUM, "action"))
+ return;
if (action >= CLKO_MAX_INDEX) {
- diag_printf("%d is not supported\n\n", action);
- return;
+ diag_printf("%d is not supported\n\n", action);
+ return;
}
ccsr = readl(SOC_CRM_CCSR);
if (action != 0) {
- ccsr = (ccsr & (~0x1F)) + action - 1;
- writel(ccsr, SOC_CRM_CCSR);
- diag_printf("Set clko to ");
+ ccsr = (ccsr & (~0x1F)) + action - 1;
+ writel(ccsr, SOC_CRM_CCSR);
+ diag_printf("Set clko to ");
}
ccsr = readl(SOC_CRM_CCSR);
diag_printf("%s\n", clko_name[(ccsr & 0x1F) + 1]);
- diag_printf("CCSR register[0x%x] = 0x%x\n", SOC_CRM_CCSR, ccsr);
+ diag_printf("CCSR register[0x%08lx] = 0x%08x\n", SOC_CRM_CCSR, ccsr);
}
extern int flash_program(void *_addr, void *_data, int len, void **err_addr);
u32 sz = readl(SERIAL_DOWNLOAD_SZ_REG);
if (readl(SERIAL_DOWNLOAD_MAGIC_REG) != SERIAL_DOWNLOAD_MAGIC) {
- return;
+ return;
}
if (nor_update) {
- // Erase area to be programmed
- if ((stat = flash_erase((void *)dst, sz, &err_addr)) != 0) {
- diag_printf("BEADDEAD\n");
- return;
- }
- diag_printf("BEADBEEF\n");
- // Now program it
- if ((stat = flash_program((void *)dst, (void *)src, sz,
- &err_addr)) != 0) {
- diag_printf("BEADFEEF\n");
- }
+ // Erase area to be programmed
+ if ((stat = flash_erase((void *)dst, sz, &err_addr)) != 0) {
+ diag_printf("BEADDEAD\n");
+ return;
+ }
+ diag_printf("BEADBEEF\n");
+ // Now program it
+ if ((stat = flash_program((void *)dst, (void *)src, sz,
+ &err_addr)) != 0) {
+ diag_printf("BEADFEEF\n");
+ }
}
diag_printf("BEADCEEF\n");
}
u32 status, error;
if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) {
- diag_printf("%s(%d) invalid operation\n", __FUNCTION__, action);
- return -1;
+ diag_printf("%s(%d) invalid operation\n", __FUNCTION__, action);
+ return -1;
}
/* Poll busy bit till it is NOT set */
error = readl(IIM_BASE_ADDR + IIM_ERR_OFF);
if ((status & action) != 0 && (error & (action >> IIM_ERR_SHIFT)) == 0) {
- if (error) {
- diag_printf("Even though the operation seems successful...\n");
- diag_printf("There are some error(s) at addr=0x%x: 0x%x\n",
- (IIM_BASE_ADDR + IIM_ERR_OFF), error);
- }
- return 0;
+ if (error) {
+ diag_printf("Even though the operation seems successful...\n");
+ diag_printf("There are some error(s) at addr=0x%08lx: 0x%08x\n",
+ (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+ }
+ return 0;
}
diag_printf("%s(%d) failed\n", __FUNCTION__, action);
- diag_printf("status address=0x%x, value=0x%x\n",
- (IIM_BASE_ADDR + IIM_STAT_OFF), status);
- diag_printf("There are some error(s) at addr=0x%x: 0x%x\n",
- (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+ diag_printf("status address=0x%08lx, value=0x%08x\n",
+ (IIM_BASE_ADDR + IIM_STAT_OFF), status);
+ diag_printf("There are some error(s) at addr=0x%08lx: 0x%08x\n",
+ (IIM_BASE_ADDR + IIM_ERR_OFF), error);
return -1;
}
addr_l = (addr & 0x000000FF);
#ifdef IIM_FUSE_DEBUG
- diag_printf("%s: addr_h=0x%x, addr_l=0x%x\n",
- __FUNCTION__, addr_h, addr_l);
+ diag_printf("%s: addr_h=0x%02x, addr_l=0x%02x\n",
+ __FUNCTION__, addr_h, addr_l);
#endif
writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
/* Start sensing */
writel(0x8, IIM_BASE_ADDR + IIM_FCTL_OFF);
if ((ret = poll_fuse_op_done(POLL_FUSE_SNSD)) != 0) {
- diag_printf("%s(bank: %d, row: %d, bit: %d failed\n",
- __FUNCTION__, bank, row, bit);
+ diag_printf("%s(bank: %d, row: %d, bit: %d failed\n",
+ __FUNCTION__, bank, row, bit);
}
reg_addr = IIM_BASE_ADDR + IIM_SDAT_OFF;
if (ret == 0)
- diag_printf("fuses at (bank:%d, row:%d) = 0x%x\n", bank, row, readl(reg_addr));
+ diag_printf("fuses at (bank:%d, row:%d) = 0x%02x\n", bank, row, readl(reg_addr));
}
void do_fuse_read(int argc, char *argv[])
unsigned long bank, row;
if (argc == 1) {
- diag_printf("Useage: fuse_read <bank> <row>\n");
- return;
+ diag_printf("Useage: fuse_read <bank> <row>\n");
+ return;
} else if (argc == 3) {
- if (!parse_num(argv[1], &bank, &argv[1], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
- if (!parse_num(*(&argv[2]), &row, &argv[2], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
-
- diag_printf("Read fuse at bank:%ld row:%ld\n", bank, row);
- sense_fuse(bank, row, 0);
+ if (!parse_num(argv[1], &bank, &argv[1], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(argv[2], &row, &argv[2], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+
+ diag_printf("Read fuse at bank:%ld row:%ld\n", bank, row);
+ sense_fuse(bank, row, 0);
} else {
- diag_printf("Passing in wrong arguments: %d\n", argc);
- diag_printf("Useage: fuse_read <bank> <row>\n");
+ diag_printf("Passing in wrong arguments: %d\n", argc);
+ diag_printf("Useage: fuse_read <bank> <row>\n");
}
}
/* Blow fuses based on the bank, row and bit positions (all 0-based)
*/
-static int fuse_blow(int bank,int row,int bit)
+int fuse_blow(int bank, int row, int bit)
{
int addr, addr_l, addr_h, ret = -1;
/* Set IIM Program Lower Address */
addr_l = (addr & 0x000000FF);
+ diag_printf("blowing fuse bank %d row %d bit %d\n", bank, row, bit & 7);
#ifdef IIM_FUSE_DEBUG
- diag_printf("blowing addr_h=0x%x, addr_l=0x%x\n", addr_h, addr_l);
+ diag_printf("blowing addr_h=0x%02x, addr_l=0x%02x\n", addr_h, addr_l);
#endif
writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
/* Start Programming */
- writel(0x31, IIM_BASE_ADDR + IIM_FCTL_OFF);
+ writel(0x71, IIM_BASE_ADDR + IIM_FCTL_OFF);
if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) {
- ret = 0;
+ ret = 0;
}
/* Enable IIM Program Protect */
* This command is added for burning IIM fuses
*/
RedBoot_cmd("fuse_read",
- "read some fuses",
- "<bank> <row>",
- do_fuse_read
- );
+ "read some fuses",
+ "<bank> <row>",
+ do_fuse_read
+ );
RedBoot_cmd("fuse_blow",
- "blow some fuses",
- "<bank> <row> <value>",
- do_fuse_blow
- );
+ "blow some fuses",
+ "<bank> <row> <value>",
+ do_fuse_blow
+ );
#define INIT_STRING "12345678"
static char ready_to_blow[] = INIT_STRING;
-void quick_itoa(u32 num, char *a)
-{
- int i, j, k;
- for (i = 0; i <= 7; i++) {
- j = (num >> (4 * i)) & 0xF;
- k = (j < 10) ? '0' : ('a' - 0xa);
- a[i] = j + k;
- }
-}
-
void do_fuse_blow(int argc, char *argv[])
{
unsigned long bank, row, value;
int i;
if (argc == 1) {
- diag_printf("It is too dangeous for you to use this command.\n");
- return;
+ diag_printf("It is too dangeous for you to use this command.\n");
+ return;
} else if (argc == 2) {
- if (strcasecmp(argv[1], "nandboot") == 0) {
- diag_printf("%s\n", "fuse blown not needed");
- }
- return;
+ if (strcasecmp(argv[1], "nandboot") == 0) {
+ diag_printf("%s\n", "fuse blown not needed");
+ }
+ return;
} else if (argc == 3) {
- if (strcasecmp(argv[1], "nandboot") == 0) {
+ if (strcasecmp(argv[1], "nandboot") == 0) {
#if defined(CYGPKG_HAL_ARM_MXC91131) || defined(CYGPKG_HAL_ARM_MX21) || defined(CYGPKG_HAL_ARM_MX27) || defined(CYGPKG_HAL_ARM_MX31)
- diag_printf("No need to blow any fuses for NAND boot on this platform\n\n");
+ diag_printf("No need to blow any fuses for NAND boot on this platform\n\n");
#else
- diag_printf("Ready to burn NAND boot fuses\n");
- if (fuse_blow(0, 16, 1) != 0 || fuse_blow(0, 16, 7) != 0) {
- diag_printf("NAND BOOT fuse blown failed miserably ...\n");
- } else {
- diag_printf("NAND BOOT fuse blown successfully ...\n");
- }
- } else {
- diag_printf("Not ready: %s, %s\n", argv[1], argv[2]);
+ diag_printf("Ready to burn NAND boot fuses\n");
+ if (fuse_blow(0, 16, 1) != 0 || fuse_blow(0, 16, 7) != 0) {
+ diag_printf("NAND BOOT fuse blown failed miserably ...\n");
+ } else {
+ diag_printf("NAND BOOT fuse blown successfully ...\n");
+ }
+ } else {
+ diag_printf("Not ready: %s, %s\n", argv[1], argv[2]);
#endif
- }
+ }
} else if (argc == 4) {
- if (!parse_num(argv[1], &bank, &argv[1], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
- if (!parse_num(argv[2], &row, &argv[2], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
- if (!parse_num(argv[3], &value, &argv[3], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
-
- diag_printf("Blowing fuse at bank:%ld row:%ld value:%ld\n",
- bank, row, value);
- for (i = 0; i < 8; i++) {
- if (((value >> i) & 0x1) == 0) {
- continue;
- }
- if (fuse_blow(bank, row, i) != 0) {
- diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d failed\n",
- bank, row, i);
- } else {
- diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d successful\n",
- bank, row, i);
- }
- }
- sense_fuse(bank, row, 0);
+ if (!parse_num(argv[1], &bank, &argv[1], " ")) {
+ diag_printf("Error: Invalid fuse bank\n");
+ return;
+ }
+ if (!parse_num(argv[2], &row, &argv[2], " ")) {
+ diag_printf("Error: Invalid fuse row\n");
+ return;
+ }
+ if (!parse_num(argv[3], &value, &argv[3], " ")) {
+ diag_printf("Error: Invalid value\n");
+ return;
+ }
+ if (!verify_action("Confirm to blow fuse at bank:%ld row:%ld value:0x%02lx (%ld)",
+ bank, row, value)) {
+ diag_printf("fuse_blow canceled\n");
+ return;
+ }
+
+ for (i = 0; i < 8; i++) {
+ if (((value >> i) & 0x1) == 0) {
+ continue;
+ }
+ if (fuse_blow(bank, row, i) != 0) {
+ diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d failed\n",
+ bank, row, i);
+ } else {
+ diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d successful\n",
+ bank, row, i);
+ }
+ }
+ sense_fuse(bank, row, 0);
} else {
- diag_printf("Passing in wrong arguments: %d\n", argc);
+ diag_printf("Passing in wrong arguments: %d\n", argc);
}
/* Reset to default string */
strcpy(ready_to_blow, INIT_STRING);
int gcd(int m, int n)
{
int t;
- while(m > 0) {
- if(n > m) {t = m; m = n; n = t;} /* swap */
- m -= n;
+ while (m > 0) {
+ if (n > m) {t = m; m = n; n = t;} /* swap */
+ m -= n;
}
return n;
}
switch (prcs) {
case 0x01:
- diag_printf("FPM enabled --> 32KHz input source\n");
- return;
+ diag_printf("FPM enabled --> 32KHz input source\n");
+ return;
case 0x02:
- break;
+ break;
default:
- diag_printf("Error %d: unknown clock source %d\n", __LINE__, prcs);
- return;
+ diag_printf("Error %d: unknown clock source %d\n", __LINE__, prcs);
+ return;
}
// enable GPT with IPG clock input
ipg_real = diff * (1000 / CLOCK_SRC_DETECT_MS);
if (ipg_real > (CLOCK_IPG_DEFAULT + CLOCK_SRC_DETECT_MARGIN)) {
- if (g_clock_src != FREQ_27MHZ)
- num = 27;
+ if (g_clock_src != FREQ_27MHZ)
+ num = 27;
} else if (ipg_real < (CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN)) {
- if (g_clock_src != FREQ_26MHZ)
- num = 26;
+ if (g_clock_src != FREQ_26MHZ)
+ num = 26;
}
if (num != 0) {
- diag_printf("Error: Actural clock input is %d MHz\n", num);
- diag_printf(" ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n\n",
- ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
- diag_printf(" But clock source defined to be %d\n\n", g_clock_src);
- hal_delay_us(2000000);
+ diag_printf("Error: Actual clock input is %d MHz\n", num);
+ diag_printf(" ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n\n",
+ ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
+ diag_printf(" But clock source defined to be %d\n\n", g_clock_src);
+ hal_delay_us(2000000);
} else {
- diag_printf("ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n\n",
- ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
- diag_printf("clock source defined to be %d\n\n", g_clock_src);
+ diag_printf("ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n\n",
+ ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
+ diag_printf("clock source defined to be %d\n\n", g_clock_src);
}
#endif
}
reg = readl(SOC_CRM_PCCR0);
if (spi_clk == SPI1_CLK) {
- writel(reg | (1 << 31), SOC_CRM_PCCR0);
- gpio_request_mux(MX27_PIN_CSPI1_MOSI, GPIO_MUX_PRIMARY);
- gpio_request_mux(MX27_PIN_CSPI1_MISO, GPIO_MUX_PRIMARY);
- gpio_request_mux(MX27_PIN_CSPI1_SCLK, GPIO_MUX_PRIMARY);
- gpio_request_mux(MX27_PIN_CSPI1_RDY, GPIO_MUX_PRIMARY);
- gpio_request_mux(MX27_PIN_CSPI1_SS0, GPIO_MUX_PRIMARY);
- gpio_request_mux(MX27_PIN_CSPI1_SS1, GPIO_MUX_PRIMARY);
- gpio_request_mux(MX27_PIN_CSPI1_SS2, GPIO_MUX_PRIMARY);
+ writel(reg | (1 << 31), SOC_CRM_PCCR0);
+ gpio_request_mux(MX27_PIN_CSPI1_MOSI, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSPI1_MISO, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSPI1_SCLK, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSPI1_RDY, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSPI1_SS0, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSPI1_SS1, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSPI1_SS2, GPIO_MUX_PRIMARY);
} else if (spi_clk == SPI2_CLK) {
- writel(reg | (1 << 30), SOC_CRM_PCCR0);
+ writel(reg | (1 << 30), SOC_CRM_PCCR0);
}
}
#define MXC_UART_REFFREQ (get_peri_clock(PER_CLK1) / 4)
#endif
+/* The Freescale MX27ADS board has two external UART ports which are mapped first
+ * for whatever strange reason.
+ * Other manufacturers may not have these UARTS on their boards but would
+ * as well like to have their serial ports start at '0'!
+ */
+#ifdef CYGPKG_HAL_ARM_MX27ADS
+#define MXC_UART_CHAN_OFFSET 2
+#else
+#define MXC_UART_CHAN_OFFSET 0
+#endif
+
+#ifndef REMOVE_ME
+#include <cyg/infra/diag.h>
+#endif
+
#if 0
void
cyg_hal_plf_comms_init(void)
#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
for (i = 0; i < NUMOF(channels); i++) {
init_serial_channel(&channels[i]);
- CYGACC_CALL_IF_SET_CONSOLE_COMM(i+2);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(i + MXC_UART_CHAN_OFFSET);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
cyg_hal_plf_serial_putc(&channels[i], '+');
jjj++;
}
- cyg_hal_plf_serial_putc(&channels[i], '+');
}
// Restore original console
#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+#define MXC_UART1_CHAN (0 + MXC_UART_CHAN_OFFSET)
+#define MXC_UART2_CHAN (1 + MXC_UART_CHAN_OFFSET)
+#define MXC_UART3_CHAN (2 + MXC_UART_CHAN_OFFSET)
+#define MXC_UART4_CHAN (3 + MXC_UART_CHAN_OFFSET)
+#define MXC_UART5_CHAN (4 + MXC_UART_CHAN_OFFSET)
+#define MXC_UART6_CHAN (5 + MXC_UART_CHAN_OFFSET)
+
#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
-#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 2)
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART1_CHAN)
#define __BASE ((void*)SOC_UART1_BASE)
#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART1
-#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 3)
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART2_CHAN)
#define __BASE ((void*)SOC_UART2_BASE)
#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART2
-#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 4)
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART3_CHAN)
#define __BASE ((void*)SOC_UART3_BASE)
#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART3
-#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 5)
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART4_CHAN)
#define __BASE ((void*)SOC_UART4_BASE)
#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART4
-#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 6)
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART5_CHAN)
#define __BASE ((void*)SOC_UART5_BASE)
#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART5
-#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 7)
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART6_CHAN)
#define __BASE ((void*)SOC_UART6_BASE)
#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART6
#endif
#define IIM_PROD_REV_LEN 5
#define IIM_SREV_REV_SH 4
#define IIM_SREV_REV_LEN 4
-#define PART_NUMBER_OFFSET (12)
-#define MAJOR_NUMBER_OFFSET (4)
-#define MINOR_NUMBER_OFFSET (0)
+#define PART_NUMBER_OFFSET 12
+#define MAJOR_NUMBER_OFFSET 4
+#define MINOR_NUMBER_OFFSET 0
// Most initialization has already been done before we get here.
// All we do here is set up the interrupt environment.
void hal_hardware_init(void)
{
- volatile unsigned int temp;
- volatile unsigned int esdctl0 = readl(SOC_ESDCTL_BASE);
- volatile unsigned int v;
-
- sys_ver = readl(SOC_SI_ID_REG) >> 28 ;
-
- system_rev = 0x27 << PART_NUMBER_OFFSET;
-
- switch (sys_ver) {
- case SOC_SILICONID_Rev1_0:
- HAL_PLATFORM_EXTRA[5] = '1';
- HAL_PLATFORM_EXTRA[7] = '0';
- system_rev |= 1 << MAJOR_NUMBER_OFFSET;
- system_rev |= 0 << MINOR_NUMBER_OFFSET;
- break;
- case SOC_SILICONID_Rev2_0:
- HAL_PLATFORM_EXTRA[5] = '2';
- HAL_PLATFORM_EXTRA[7] = '0';
- system_rev |= 2 << MAJOR_NUMBER_OFFSET;
- system_rev |= 0 << MINOR_NUMBER_OFFSET;
- break;
- case SOC_SILICONID_Rev2_1:
- HAL_PLATFORM_EXTRA[5] = '2';
- HAL_PLATFORM_EXTRA[7] = '1';
- system_rev |= 2 << MAJOR_NUMBER_OFFSET;
- system_rev |= 1 << MINOR_NUMBER_OFFSET;
- break;
- }
-
- if ((esdctl0 & 0x20000) == 0x0) {
- HAL_PLATFORM_EXTRA[11] = '1';
- HAL_PLATFORM_EXTRA[12] = '6';
- }
-
- // enable user mode SOC register accesses
- writel(1, SOC_AIPI1_BASE + SOC_AIPI_PAR_OFF);
- writel(1, SOC_AIPI2_BASE + SOC_AIPI_PAR_OFF);
-
- // Enable clko and divide it by 8
- v = readl(SOC_CRM_PCDR0);
- v |= 0xF << 22;
- writel(v, SOC_CRM_PCDR0);
- // Default for core clock
- writel(0x7, SOC_CRM_CCSR);
- // Enable clocks for FEC, GPIO, GPT2, IIM
- writel(0x06810000, SOC_CRM_PCCR0);
- // Enable clocks for UARTs, BROM, EMI, HCLK_FEC, PERCLK1, NFC
- writel(0xFC4A0408, SOC_CRM_PCCR1);
-
- // Mask all interrupts
- writel(0xFFFFFFFF, SOC_AITC_NIMASK);
-
- // Make all interrupts do IRQ and not FIQ
- writel(0, SOC_AITC_INTTYPEH);
- writel(0, SOC_AITC_INTTYPEL);
-
- // Disable all GPIO interrupt sources
-
- // Enable caches
- HAL_ICACHE_ENABLE();
- HAL_DCACHE_ENABLE();
-
- if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
- // increase the WDOG timeout value to the max
- writew(readw(WDOG_BASE_ADDR) | 0xFF00, WDOG_BASE_ADDR);
- }
-
- // Perform any platform specific initializations
- plf_hardware_init();
-
- // Set up eCos/ROM interfaces
- hal_if_init();
-
- // init timer2 and start it -- use 32KHz clock
-
- writel(0x4, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // counter reset when timer is disabled
- writel(0x0, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // disable timer
-
- writel(0x00008000, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // reset timer
- while((readl(SOC_GPT2_BASE + GPT_TCTL_OFFSET) & 0x8000) != 0); // make sure reset complete
-
- writel(0x0, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // disable timer
- writel(0, SOC_GPT2_BASE + GPT_TPRER_OFFSET);
- temp = readl(SOC_GPT2_BASE + GPT_TCTL_OFFSET);
- writel(temp | 0x00000100, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // free-run mode
- temp = readl(SOC_GPT2_BASE + GPT_TCTL_OFFSET);
- writel(temp | 0x00000008, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // 32KHz to prescaler
- temp = readl(SOC_GPT2_BASE + GPT_TCTL_OFFSET);
- writel(temp | 0x00000001, SOC_GPT2_BASE + GPT_TCTL_OFFSET); //enable timer
-
- hal_delay_us(MX_STARTUP_DELAY);
+ unsigned int temp;
+ unsigned int esdctl0 = readl(SOC_ESDCTL_BASE);
+ unsigned int v;
+
+ sys_ver = readl(SOC_SI_ID_REG) >> 28 ;
+
+ system_rev = 0x27 << PART_NUMBER_OFFSET;
+
+ switch (sys_ver) {
+ case SOC_SILICONID_Rev1_0:
+ HAL_PLATFORM_EXTRA[5] = '1';
+ HAL_PLATFORM_EXTRA[7] = '0';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET;
+ system_rev |= 0 << MINOR_NUMBER_OFFSET;
+ break;
+ case SOC_SILICONID_Rev2_0:
+ HAL_PLATFORM_EXTRA[5] = '2';
+ HAL_PLATFORM_EXTRA[7] = '0';
+ system_rev |= 2 << MAJOR_NUMBER_OFFSET;
+ system_rev |= 0 << MINOR_NUMBER_OFFSET;
+ break;
+ case SOC_SILICONID_Rev2_1:
+ HAL_PLATFORM_EXTRA[5] = '2';
+ HAL_PLATFORM_EXTRA[7] = '1';
+ system_rev |= 2 << MAJOR_NUMBER_OFFSET;
+ system_rev |= 1 << MINOR_NUMBER_OFFSET;
+ break;
+ }
+
+ if ((esdctl0 & 0x20000) == 0x0) {
+ HAL_PLATFORM_EXTRA[11] = '1';
+ HAL_PLATFORM_EXTRA[12] = '6';
+ }
+
+ // enable user mode SOC register accesses
+ writel(1, SOC_AIPI1_BASE + SOC_AIPI_PAR_OFF);
+ writel(1, SOC_AIPI2_BASE + SOC_AIPI_PAR_OFF);
+
+ // Enable clko and divide it by 8
+ v = readl(SOC_CRM_PCDR0);
+ v |= 0xF << 22;
+ writel(v, SOC_CRM_PCDR0);
+ // Default for core clock
+ writel(0x7, SOC_CRM_CCSR);
+ // Enable clocks for FEC, GPIO, GPT2, IIM
+ writel(0x06810000, SOC_CRM_PCCR0);
+ // Enable clocks for UARTs, BROM, EMI, HCLK_FEC, PERCLK1, NFC
+ writel(0xFC4A0408, SOC_CRM_PCCR1);
+
+ // Mask all interrupts
+ writel(0xFFFFFFFF, SOC_AITC_NIMASK);
+
+ // Make all interrupts do IRQ and not FIQ
+ writel(0, SOC_AITC_INTTYPEH);
+ writel(0, SOC_AITC_INTTYPEL);
+
+ // Disable all GPIO interrupt sources
+
+ // Enable caches
+ HAL_ICACHE_ENABLE();
+ HAL_DCACHE_ENABLE();
+
+ if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
+ // increase the WDOG timeout value to the max
+ writew(readw(WDOG_BASE_ADDR) | 0xFF00, WDOG_BASE_ADDR);
+ }
+
+ // init timer2 and start it -- use 32KHz clock
+
+ writel(0x4, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // counter reset when timer is disabled
+ writel(0x0, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // disable timer
+
+ writel(0x00008000, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // reset timer
+ while((readl(SOC_GPT2_BASE + GPT_TCTL_OFFSET) & 0x8000) != 0); // make sure reset complete
+
+ writel(0x0, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // disable timer
+ writel(0, SOC_GPT2_BASE + GPT_TPRER_OFFSET);
+ temp = readl(SOC_GPT2_BASE + GPT_TCTL_OFFSET);
+ writel(temp | 0x00000100, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // free-run mode
+ temp = readl(SOC_GPT2_BASE + GPT_TCTL_OFFSET);
+ writel(temp | 0x00000008, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // 32KHz to prescaler
+ temp = readl(SOC_GPT2_BASE + GPT_TCTL_OFFSET);
+ writel(temp | 0x00000001, SOC_GPT2_BASE + GPT_TCTL_OFFSET); //enable timer
+
+ // Perform any platform specific initializations
+ plf_hardware_init();
+
+ // Set up eCos/ROM interfaces
+ hal_if_init();
+
+ hal_delay_us(MX_STARTUP_DELAY);
}
// -------------------------------------------------------------------------
unsigned int hal_timer_count(void)
{
- return readl(HAL_DELAY_TIMER + GPT_TCN_OFFSET);
+ return readl(HAL_DELAY_TIMER + GPT_TCN_OFFSET);
}
#define WDT_MAGIC_1 0x5555
//
void hal_delay_us(unsigned int usecs)
{
- unsigned long timerCount, timerCompare;
- unsigned int delayCount = (usecs * 512) / 15625;
- //diag_printf("entering mx2 hal_delay_us: %d, delaycount = %d, system_rev = %d\n\n", usecs, delayCount, system_rev);
+ unsigned long timerCount, timerCompare;
+ unsigned int delayCount = (usecs * 512) / 15625;
+ //diag_printf("entering mx2 hal_delay_us: %d, delaycount = %d, system_rev = %d\n\n", usecs, delayCount, system_rev);
- if (delayCount == 0) {
- return;
- }
+ if (delayCount == 0) {
+ return;
+ }
- // issue the service sequence instructions
- if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
- writew(WDT_MAGIC_1, WDOG_BASE_ADDR + MXC_WDT_WSR);
- writew(WDT_MAGIC_2, WDOG_BASE_ADDR + MXC_WDT_WSR);
- }
+ // issue the service sequence instructions
+ if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
+ writew(WDT_MAGIC_1, WDOG_BASE_ADDR + MXC_WDT_WSR);
+ writew(WDT_MAGIC_2, WDOG_BASE_ADDR + MXC_WDT_WSR);
+ }
- writel(0x03, HAL_DELAY_TIMER + GPT_TSTAT_OFFSET); // clear the compare status bit
- timerCount = readl(HAL_DELAY_TIMER + GPT_TCN_OFFSET);
-
- timerCompare = timerCount + delayCount;
+ writel(0x03, HAL_DELAY_TIMER + GPT_TSTAT_OFFSET); // clear the compare status bit
+ timerCount = readl(HAL_DELAY_TIMER + GPT_TCN_OFFSET);
- writel(timerCompare, HAL_DELAY_TIMER + GPT_TCMP_OFFSET); // setup compare reg
+ timerCompare = timerCount + delayCount;
- while ((0x1 & readl(HAL_DELAY_TIMER + GPT_TSTAT_OFFSET)) == 0); // return until compare bit is set
- writel(0x03, HAL_DELAY_TIMER + GPT_TSTAT_OFFSET); // clear the compare status bit
+ writel(timerCompare, HAL_DELAY_TIMER + GPT_TCMP_OFFSET); // setup compare reg
- if ((++led_on % 3000) == 0)
- BOARD_DEBUG_LED(0);
+ while ((0x1 & readl(HAL_DELAY_TIMER + GPT_TSTAT_OFFSET)) == 0); // return until compare bit is set
+ writel(0x03, HAL_DELAY_TIMER + GPT_TSTAT_OFFSET); // clear the compare status bit
+
+ if ((++led_on % 3000) == 0)
+ BOARD_DEBUG_LED(0);
}
// -------------------------------------------------------------------------
int hal_IRQ_handler(void)
{
#ifdef HAL_EXTENDED_IRQ_HANDLER
- cyg_uint32 index;
+ cyg_uint32 index;
- // Use platform specific IRQ handler, if defined
- // Note: this macro should do a 'return' with the appropriate
- // interrupt number if such an extended interrupt exists. The
- // assumption is that the line after the macro starts 'normal' processing.
- HAL_EXTENDED_IRQ_HANDLER(index);
+ // Use platform specific IRQ handler, if defined
+ // Note: this macro should do a 'return' with the appropriate
+ // interrupt number if such an extended interrupt exists. The
+ // assumption is that the line after the macro starts 'normal' processing.
+ HAL_EXTENDED_IRQ_HANDLER(index);
#endif
- return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
+ return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
}
//
void hal_interrupt_mask(int vector)
{
-// diag_printf("6hal_interrupt_mask(vector=%d) \n", vector);
+ // diag_printf("6hal_interrupt_mask(vector=%d) \n", vector);
#ifdef HAL_EXTENDED_INTERRUPT_MASK
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_MASK(vector);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_MASK(vector);
#endif
}
void hal_interrupt_unmask(int vector)
{
-// diag_printf("7hal_interrupt_unmask(vector=%d) \n", vector);
+ // diag_printf("7hal_interrupt_unmask(vector=%d) \n", vector);
#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_UNMASK(vector);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_UNMASK(vector);
#endif
}
void hal_interrupt_acknowledge(int vector)
{
-// diag_printf("8hal_interrupt_acknowledge(vector=%d) \n", vector);
+ // diag_printf("8hal_interrupt_acknowledge(vector=%d) \n", vector);
#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector);
#endif
}
{
#ifdef HAL_EXTENDED_INTERRUPT_SET_LEVEL
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_SET_LEVEL(vector, level);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_SET_LEVEL(vector, level);
#endif
- // Interrupt priorities are not configurable.
+ // Interrupt priorities are not configurable.
}
/*------------------------------------------------------------------------*/
display "Global command prefix"
flavor data
no_define
- default_value { "arm-elf" }
+ default_value { "arm-none-eabi" }
description "
This option specifies the command prefix used when
invoking the build tools."
display "Global compiler flags"
flavor data
no_define
- default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
description "
This option controls the global compiler flags which are used to
compile all packages by default. Individual packages may define
#include <cyg/hal/hal_soc.h> // Hardware definitions
#define PMIC_SPI_BASE CSPI2_BASE_ADDR
+#define PMIC_SPI_CHIP_SELECT_NO SPI_CTRL_CS0
#define PBC_BASE CS4_BASE_ADDR /* Peripheral Bus Controller */
#define PBC_VERSION 0x0
#include <cyg/hal/hal_mmu.h> // MMU definitions
#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+//#define BOOT_FROM_MMC
+
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
#define PLATFORM_SETUP1 _platform_setup1
+#if defined(BOOT_FROM_MMC)
+#define PLATFORM_PREAMBLE flash_header
+#endif
#define CYGHWR_HAL_ARM_HAS_MMU
#ifdef CYG_HAL_STARTUP_ROMRAM
#define CYGSEM_HAL_ROM_RESET_USES_JUMP
#endif
-#define SDRAM_FULL_PAGE_BIT 0x100
-#define SDRAM_FULL_PAGE_MODE 0x37
-#define SDRAM_BURST_MODE 0x33
+//#define ARM_399MHZ
+#define ARM_532MHZ
+
+#define SDRAM_FULL_PAGE_BIT 0x100
+#define SDRAM_FULL_PAGE_MODE 0x37
+#define SDRAM_BURST_MODE 0x33
+#define MMC_BLK_LEN 0x200
+#define MMC_START_ADDR 0x0
+#define MMC_LOAD_SIZE 0x30000
#define CYGHWR_HAL_ROM_VADDR 0x0
#if 0
//#define TURN_OFF_IMPRECISE_ABORT
+ .macro flash_header
+ b 1f
+ //0x400
+ .org 0x400
+ .long 0x0
+ .long 0x0
+ MMC_SDHC1_BASE_ADDR_W: .word MMC_SDHC1_BASE_ADDR
+ ESDHC_INTERRUPT_ENABLE_W: .word ESDHC_INTERRUPT_ENABLE
+ ESDHC_CLEAR_INTERRUPT_W: .word ESDHC_CLEAR_INTERRUPT
+ MXC_REDBOOT_ROM_ST_ADDR: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
+ REDBOOT_RESET_VECTOR: .word reset_vector
+1:
+ /* Check if booting from IRAM for MMC boot */
+ mov r0, #SDRAM_BASE_ADDR
+ cmp pc, r0
+ bhs 100f
+ setup_sdram ddr X32 DDR 0
+ mmcsd_read
+ mov r12, #MMC_BOOT
+100:
+ ldr r0, REDBOOT_RESET_VECTOR
+ mov pc, r0
+ .endm
+
+ .macro mmcsd_read
+ //Configure interface block and number of blocks 1 block and size is 512 Bytes
+ mov r2, #MMC_BLK_LEN
+ ldr r3, MMC_SDHC1_BASE_ADDR_W
+ str r2, [r3, #ESDHC_REG_BLK_LEN]
+ mov r2, #1
+ str r2, [r3, #ESDHC_REG_NOB]
+ //set block size and number of blocks of card
+ mov r1, #MMC_START_ADDR
+ mov r2, #MMC_BLK_LEN
+ sub r10, r1, r2
+ ldr r11, MXC_REDBOOT_ROM_ST_ADDR
+ mov r12, #MMC_LOAD_SIZE
+ add r12, r11, r12
+
+ //set read data length, Comfigure command CMD16 for single block read
+ mov r0, #MMC_BLK_LEN
+ mov r1, #0x10
+ mov r2, #0x1
+ send_cmd_wait_resp
+
+read_a_blk:
+ //set read data address
+ //CMD17 data_present Y
+ mov r2, #MMC_BLK_LEN
+ add r10, r10, r2
+ mov r0, r10
+ mov r1, #0x11
+ mov r2, #0x9
+ send_cmd_wait_resp
+ mov r5, #MMC_BLK_LEN
+ add r5, r11, r5
+
+ //enable interrupt
+ ldr r4, ESDHC_INTERRUPT_ENABLE_W
+ str r4, [r3, #ESDHC_REG_INT_STATUS_ENABLE]
+read_from_buffer:
+ ldr r4, [r3, #ESDHC_REG_INT_STATUS]
+ mov r2, #0x80 //ESDHC_STATUS_BUF_READ_RDY_MSK
+ ands r4, r4, r2
+ beq read_from_buffer
+
+four_times: //transfer data from SDHC buffer to ddr(4 words once)
+ ldr r4, [r3, #ESDHC_REG_BUFFER_DATA]
+ str r4, [r11]
+ add r11, r11, #0x4
+ ldr r4, [r3, #ESDHC_REG_BUFFER_DATA]
+ str r4, [r11]
+ add r11, r11, #0x4
+ ldr r4, [r3, #ESDHC_REG_BUFFER_DATA]
+ str r4, [r11]
+ add r11, r11, #0x4
+ ldr r4, [r3, #ESDHC_REG_BUFFER_DATA]
+ str r4, [r11]
+ add r11, r11, #0x4
+ cmp r11, r5
+ blo read_from_buffer
+
+check_tran_done: //check if the transfer is over
+ ldr r4, [r3, #ESDHC_REG_INT_STATUS]
+ mov r2, #0x800 //ESDHC_STATUS_TRANSFER_COMPLETE_MSK
+ ands r2, r4, r2
+ beq check_tran_done
+ ands r2, r2, #0x8
+ bne check_tran_done
+ cmp r11, r12
+ blo read_a_blk
+ .endm
+
+ //r0~r2 are reserved
+ .macro send_cmd_wait_resp
+ //start clk
+ ldr r3, MMC_SDHC1_BASE_ADDR_W
+ mov r4, #0x2
+ str r4, [r3, #ESDHC_REG_CLK]
+
+ //wait until the clk has started
+1:
+ ldr r4, [r3, #ESDHC_REG_INT_STATUS]
+ mov r5, #0x100
+ ands r4, r4, r5
+ beq 1b
+
+ //Clear Interrupt status register
+ ldr r4, ESDHC_CLEAR_INTERRUPT_W
+ str r4, [r3, #ESDHC_REG_INT_STATUS]
+ /* Enable Interrupt */
+ ldr r4, [r3, #ESDHC_REG_INT_STATUS_ENABLE]
+ ldr r5, ESDHC_INTERRUPT_ENABLE_W
+ orr r4, r4, r5
+ str r4, [r3, #ESDHC_REG_INT_STATUS_ENABLE]
+
+ /* Write Command Argument in Command Argument Register */
+ str r1, [r3, #ESDHC_REG_COMMAND]
+ str r0, [r3, #ESDHC_REG_COMMAND_TRANS_TYPE]
+ str r2, [r3, #ESDHC_REG_COMMAND_DAT_CONT]
+
+2: //wait for responds
+ mov r0, #0
+ mov r1, #0x1000
+3:
+ add r0,r0,#1
+ cmp r0,r1
+ bne 3b
+
+ ldr r0, [r3, #ESDHC_REG_INT_STATUS]
+ mov r1, #0x2000
+ ands r1, r0, r1
+ beq 2b
+
+ //mask all int
+ mov r4, #0
+ str r4, [r3, #ESDHC_REG_INT_STATUS_ENABLE]
+ .endm
+
// This macro represents the initial startup code for the platform
// r11 is reserved to contain chip rev info in this file
.macro _platform_setup1
bic r0, r0, #0x100
msr cpsr, r0
#endif
-
mov r0, #0
mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
ldr r0, ARM_PPMRR /* start from AIPS 2GB region */
mcr p15, 0, r0, c15, c2, 4
+ /* Reload data from spare area to 0x400 of main area if booting from NAND */
+ mov r0, #NFC_BASE
+ add r1, r0, #0x400
+ cmp pc, r0
+ blo 1f
+ cmp pc, r1
+ bhi 1f
+
+1:
/*** L2 Cache setup/invalidation/disable ***/
/* Disable L2 cache first */
mov r0, #L2CC_BASE_ADDR
init_cs0_async_start:
// init_cs0_async
+
/* If SDRAM has been setup, bypass clock/WEIM setup */
+ cmp r12, #MMC_BOOT
+ ldreq r1, AVIC_VECTOR0_ADDR_W
+ streq r12, [r1]
+ beq init_cs4_start
+
cmp pc, #SDRAM_BASE_ADDR
blo init_clock_start
cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
init_clock_start:
init_clock
+ cmp r12, #MMC_BOOT
+ beq HWInitialise_skip_SDRAM_setup
+
/* Based on chip rev, setup params for SDRAM controller */
ldr r10, =0
mov r4, #SDRAM_BURST_MODE
init_sdram_start:
-
+#ifndef BOOT_FROM_MMC
/* Assuming DDR memory first */
setup_sdram ddr X32 DDR 0
-#if 0
- beq HWInitialise_skip_SDRAM_setup
- setup_sdram ddr X16 DDR 0
- beq HWInitialise_skip_SDRAM_setup
- setup_sdram sdr X32 SDR 0
- beq HWInitialise_skip_SDRAM_setup
- setup_sdram sdr X16 SDR 0
- beq HWInitialise_skip_SDRAM_setup
-
- /* Reach hear means memory setup problem. Try to
- * increase the HCLK divider */
- ldr r0, CCM_BASE_ADDR_W
- ldr r1, [r0, #CLKCTL_PDR0]
- and r2, r1, #0x38
- cmp r2, #0x38
- beq loop_forever
- add r1, r1, #0x8
- str r1, [r0, #CLKCTL_PDR0]
- b init_sdram_start
-
-loop_forever:
- b loop_forever /* shouldn't get here */
#endif
HWInitialise_skip_SDRAM_setup:
bl nfc_data_output
bl do_wait_op_done
// end of 4th
-
// check for bad block
mov r3, r1, lsl #(32-17) // get rid of block number
cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
Normal_Boot_Continue:
-#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
+#if defined(CYG_HAL_STARTUP_ROMRAM) || defined(BOOT_FROM_MMC) /* enable running from RAM */
/* Copy image from flash to SDRAM first */
ldr r0, =0xFFFFF000
and r0, r0, pc
ldr r2, =10f
mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
orr r1, r1, #7 // enable MMU bit
+ orr r1, r1, #0x800 // enable z bit
mcr MMU_CP, 0, r1, MMU_Control, c0
mov pc,r2 /* Change address spaces */
nop
ands r1, r1, #CLK_INPUT_27MHZ_SET
// 532-133-66.5
- ldr r1, CCM_PDR0_532_133_66_W
+ ldr r1, CCM_PDR0_W
str r1, [r0, #CLKCTL_PDR0]
- ldr r1, MPCTL_PARAM_532_W
+ ldr r1, MPCTL_PARAM_W
ldrne r1, MPCTL_PARAM_532_27_W
str r1, [r0, #CLKCTL_MPCTL]
.macro setup_sdram, name, bus_width, mode, full_page
/* It sets the "Z" flag in the CPSR at the end of the macro */
+ b 1f
+ ESDCTL_BASE_W: .word ESDCTL_BASE
+ SDRAM_0x0075E73A: .word 0x0075E73A
+ SDRAM_PARAM1_DDR: .word 0x4
+ SDRAM_PARAM1_SDR: .word 0x0
+ SDRAM_PARAM2_DDR: .word 0x80000F00
+ SDRAM_PARAM2_SDR: .word 0x80000400
+ SDRAM_PARAM3_DDR: .word 0x00100000
+ SDRAM_PARAM3_SDR: .word 0x0
+ SDRAM_PARAM4_X32: .word 0x00010000
+ SDRAM_PARAM4_X16: .word 0x0
+ SDRAM_0x55555555: .word 0x55555555
+ SDRAM_0xAAAAAAAA: .word 0xAAAAAAAA
+ SDRAM_0x92100000: .word 0x92100000
+ SDRAM_0xA2100000: .word 0xA2100000
+ SDRAM_0xB2100000: .word 0xB2100000
+ SDRAM_0x82116080: .word 0x82116080
+1:
ldr r0, ESDCTL_BASE_W
mov r2, #SDRAM_BASE_ADDR
ldr r1, SDRAM_0x0075E73A
.else
strb r1, [r2, #SDRAM_BURST_MODE]
.endif
-
+
ldr r1, =0xFF
ldr r12, =0x81000000
strb r1, [r12]
ldr r0, [r1, #0x6C]
bic r0, r0, #(1 << 12)
str r0, [r1, #0x6C]
-
+
// CAS
ldr r0, [r1, #0x70]
bic r0, r0, #(1 << 22)
str r0, [r1, #0x70]
-
+
// RAS
ldr r0, [r1, #0x74]
bic r0, r0, #(1 << 2)
str r0, [r1, #0x74]
-
+
// CS2 (CSD0)
ldr r0, [r1, #0x7C]
bic r0, r0, #(1 << 22)
str r0, [r1, #0x7C]
-
+
// DQM3
ldr r0, [r1, #0x84]
bic r0, r0, #(1 << 22)
str r0, [r1, #0x84]
-
+
// DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
ldr r2, =22 // (0x2E0 - 0x288) / 4 = 22
pad_loop:
MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
MAX_PARAM1: .word 0x00302154
CLKCTL_BASE_ADDR_W: .word CLKCTL_BASE_ADDR
-ESDCTL_BASE_W: .word ESDCTL_BASE
M3IF_BASE_W: .word M3IF_BASE
-SDRAM_PARAM1_DDR: .word 0x4
-SDRAM_PARAM1_SDR: .word 0x0
-SDRAM_PARAM2_DDR: .word 0x80000F00
-SDRAM_PARAM2_SDR: .word 0x80000400
-SDRAM_PARAM3_DDR: .word 0x00100000
-SDRAM_PARAM3_SDR: .word 0x0
-SDRAM_PARAM4_X32: .word 0x00010000
-SDRAM_PARAM4_X16: .word 0x0
-SDRAM_0x55555555: .word 0x55555555
-SDRAM_0xAAAAAAAA: .word 0xAAAAAAAA
-SDRAM_0x92100000: .word 0x92100000
-SDRAM_0xA2100000: .word 0xA2100000
-SDRAM_0xB2100000: .word 0xB2100000
-SDRAM_0x82116080: .word 0x82116080
-SDRAM_0x0075E73A: .word 0x0075E73A
WEIM_CTRL_CS0_W: .word WEIM_CTRL_CS0
CS0_CSCRU_0x11414C80: .word 0x11414C80
CS0_CSCRL_0x30000D03: .word 0x30000D03
CS0_CSCRA_0x00310800: .word 0x00310800
IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
-CCM_PDR0_532_133_66_W: .word PDR0_532_133_66
-MPCTL_PARAM_532_W: .word MPCTL_PARAM_532
+#ifdef ARM_399MHZ
+CCM_PDR0_W: .word PDR0_399_133_66
+MPCTL_PARAM_W: .word MPCTL_PARAM_399
+#endif
+#ifdef ARM_532MHZ
+CCM_PDR0_W: .word PDR0_532_133_66
+MPCTL_PARAM_W: .word MPCTL_PARAM_532
+#endif
+
MPCTL_PARAM_532_27_W: .word MPCTL_PARAM_532_27
CCM_PDR1_0x49FCFE7F: .word 0x49FCFE7F
CCM_UPCTL_PARAM_240: .word UPCTL_PARAM_240
SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START \
cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
if ( _v_ < 128 * SZ_1M ) /* SDRAM */ \
- _v_ += 0x800u * SZ_1M; \
+ _v_ += SDRAM_BASE_ADDR; \
else /* Rest of it */ \
/* no change */ ; \
(paddr) = _v_; \
package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
package -hardware CYGPKG_DEVS_FLASH_MX31ADS_SPANSION current ;
package -hardware CYGPKG_DEVS_MXC_SPI current ;
+ package -hardware CYGPKG_DEVS_MXC_I2C current ;
package -template CYGPKG_HAL current ;
package -template CYGPKG_INFRA current ;
package -template CYGPKG_REDBOOT current ;
inferred_value 1
};
+cdl_option CYGHWR_DEVS_FLASH_MMC {
+ inferred_value 1
+};
+
cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
inferred_value 0
};
};
cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
- user_value 1 "FSL 200740"
+ user_value 1 "FSL 200904"
};
//
unsigned int g_clock_src;
+extern int g_board_type;
void plf_hardware_init(void)
{
volatile unsigned short dummy, temp;
volatile int i = 0;
unsigned long val = readl(CCM_BASE_ADDR + CLKCTL_CCMR);
-
+
if ((val & 0x6) == 0x4) {
if ((readw(PBC_BASE + PBC_BSTAT2) & CLK_INPUT_27MHZ_SET) != 0) {
g_clock_src = FREQ_27MHZ;
writel(0x00001313, IOMUXC_BASE_ADDR + 0x74);
writel(0x00000040, IOMUXC_BASE_ADDR + 0x7C);
writel(0x40400000, IOMUXC_BASE_ADDR + 0x78);
+
+ g_board_type = BOARD_TYPE_ADS;
}
#include CYGHWR_MEMORY_LAYOUT_H
#if (REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE)
#error REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE
-#endif
+#endif
RedBoot_config_option("Board specifics",
brd_specs,
- ALWAYS_ENABLED,
+ ALWAYS_ENABLED,
true,
CONFIG_INT,
0
);
#endif //CYGSEM_REDBOOT_FLASH_CONFIG
+char HAL_PLATFORM_EXTRA[60] = "MX31 ADS (Freescale i.MX31 based) PASS 1.0 [x32 DDR]";
+
static void runImg(int argc, char *argv[]);
RedBoot_cmd("run",
#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYG_HAL_STARTUP_ROMRAM)
-RedBoot_cmd("romupdate",
- "Update Redboot with currently running image",
+RedBoot_cmd("romupdate",
+ "Update Redboot with currently running image",
"",
- romupdate
+ romupdate
);
extern int flash_program(void *_addr, void *_data, int len, void **err_addr);
{
void *err_addr, *base_addr;
int stat;
-
- if (IS_FIS_FROM_NAND()) {
- base_addr = (void*)MXC_NAND_BASE_DUMMY;
+ if (IS_FIS_FROM_MMC()) {
+ diag_printf("Updating ROM in MMC/SD flash\n");
+ base_addr = (void*)MXC_MMC_BASE_DUMMY;
+ /* Read the MBR from the card to RAM */
+ mmc_data_read((cyg_uint32*)(ram_end + 0x4), 0x3FC, base_addr);
+ diag_printf("Programming Redboot to MMC/SD flash\n");
+ mmc_data_write((cyg_uint32*)ram_end, CYGBLD_REDBOOT_MIN_IMAGE_SIZE, (cyg_uint32)base_addr);
+ return;
+ } else if (IS_FIS_FROM_NAND()) {
+ base_addr = (void*)0;
diag_printf("Updating ROM in NAND flash\n");
} else if (IS_FIS_FROM_NOR()) {
base_addr = (void*)BOARD_FLASH_START;
diag_printf("Updating ROM in NOR flash\n");
} else {
diag_printf("romupdate not supported\n");
- diag_printf("Use \"factive [NOR|NAND]\" to select either NOR or NAND flash\n");
+ diag_printf("Use \"factive [NOR|NAND|MMC]\" to select either MMC, NOR, NAND flash\n");
return;
}
// Erase area to be programmed
if ((stat = flash_erase((void *)base_addr,
CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
(void **)&err_addr)) != 0) {
- diag_printf("Can't erase region at %p: %s\n",
+ diag_printf("Can't erase region at %p: %s\n",
err_addr, flash_errmsg(stat));
return;
}
// Now program it
if ((stat = flash_program((void *)base_addr, (void *)ram_end,
- CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
(void **)&err_addr)) != 0) {
- diag_printf("Can't program region at %p: %s\n",
+ diag_printf("Can't program region at %p: %s\n",
err_addr, flash_errmsg(stat));
}
}
-RedBoot_cmd("factive",
- "Enable one flash media for Redboot",
- "[NOR | NAND]",
- factive
+
+RedBoot_cmd("factive",
+ "Enable one flash media for Redboot",
+ "[NOR | NAND | MMC]",
+ factive
);
void factive(int argc, char *argv[])
return;
#else
MXC_ASSERT_NAND_BOOT();
+#endif
+ } else if (strcasecmp(argv[1], "MMC") == 0) {
+#ifndef MXCFLASH_SELECT_MMC
+ diag_printf("Not supported\n");
+ return;
+#else
+ MXC_ASSERT_MMC_BOOT();
#endif
} else {
diag_printf("Invalid command: %s\n", argv[1]);
description "
The processor can run at various frequencies.
These values are expressed in KHz. Note that there are
- several steppings of the rated to run at different
+ several steppings of the rate to run at different
maximum frequencies. Check the specs to make sure that your
particular processor can run at the rate you select here."
}
// Query the state of the L2 cache
#define HAL_L2CACHE_IS_ENABLED(_state_) \
-CYG_MACRO_START \
- _state_ = (*(unsigned long *)(0x30000100)) & 0x1; \
-CYG_MACRO_END
+ (_state_ = readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1)
#ifdef L2CC_ENABLED
-#define HAL_ENABLE_L2() \
-CYG_MACRO_START \
- asm volatile ( \
- "ldr r0, =0x30000100;" \
- "ldr r1, [r0];" \
- "orr r1, r1, #0x1;" \
- "str r1, [r0];" \
- : \
- : \
- : "r0", "r1" /* Clobber list */ \
- ); \
-CYG_MACRO_END
-
-#define HAL_DISABLE_L2() \
-CYG_MACRO_START \
- asm volatile ( \
- "ldr r0, =0x30000000;" \
- "ldr r1, [r0, #0x100];" \
- "bic r1, r1, #0x1;" \
- "str r1, [r0, #0x100];" \
- : \
- : \
- : "r0", "r1" /* Clobber list */ \
- ); \
-CYG_MACRO_END
+#define HAL_ENABLE_L2() \
+{ \
+ writel(1, L2CC_BASE_ADDR + L2_CACHE_CTL_REG); \
+}
-#define HAL_SYNC_L2() \
-CYG_MACRO_START \
- asm volatile ( \
- "ldr r0, =0x30000000;" \
- "ldr r1, [r0, #0x100];" \
- "mov r2, r1;" \
- "tst r1, #0x1;" \
- "beq 1f;" \
- "bic r1, r1, #0x1;" \
- "str r1, [r0, #0x100];" \
- "1: " \
- "ldr r2, =0x0;" \
- "str r2, [r0, #0x730];" \
- "str r2, [r0, #0x100];" \
- : \
- : \
- : "r0", "r1", "r2" /* Clobber list */ \
- ); \
-CYG_MACRO_END
+#define HAL_DISABLE_L2() \
+{ \
+ writel(0, L2CC_BASE_ADDR + L2_CACHE_CTL_REG); \
+}
-#define HAL_INVALIDATE_L2() \
-CYG_MACRO_START \
- asm volatile ( \
- "ldr r0, =0x30000000;" \
- "ldr r1, [r0, #0x100];" \
- "mov r2, r1;" \
- "tst r1, #0x1;" \
- "beq 1f;" \
- "bic r1, r1, #0x1;" \
- "str r1, [r0, #0x100];" \
- "1: " \
- "ldr r1, =0x0;" \
- "str r1, [r0, #0x730];" \
- "ldr r1, =0xFF;" \
- "str r1, [r0, #0x77C];" \
- "2: " \
- "ldr r1, [r0, #0x77C];" \
- "cmp r1, #0x0;" \
- "bne 2b;" \
- "str r2, [r0, #0x100];" \
- : \
- : \
- : "r0", "r1" /* Clobber list */ \
- ); \
-CYG_MACRO_END
+#define HAL_SYNC_L2() \
+{ \
+ if ((readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1) != 0) { \
+ writel(0, L2CC_BASE_ADDR + L2_CACHE_SYNC_REG); \
+ while ((readl(L2CC_BASE_ADDR + L2_CACHE_SYNC_REG) & 1) == 1); \
+ } \
+}
-#define HAL_CLEAN_INVALIDATE_L2() \
-CYG_MACRO_START \
- asm volatile ( \
- "ldr r0, =0x30000000;" \
- "ldr r1, [r0, #0x100];" \
- "mov r2, r1;" \
- "tst r1, #0x1;" \
- "beq 1f;" \
- "bic r1, r1, #0x1;" \
- "str r1, [r0, #0x100];" \
- "1: " \
- "ldr r2, =0x0;" \
- "str r2, [r0, #0x730];" \
- "ldr r2, =0xFF;" \
- "str r2, [r0, #0x7FC];" \
- "2: " \
- "ldr r2, [r0, #0x7FC];" \
- "cmp r2, #0x0;" \
- "bne 2b;" \
- "str r2, [r0, #0x100];" \
- : \
- : \
- : "r0", "r1" /* Clobber list */ \
- ); \
-CYG_MACRO_END
+#define HAL_INVALIDATE_L2() \
+{ \
+ if ((readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1) != 0) { \
+ writel(0xFF, L2CC_BASE_ADDR + L2_CACHE_INV_WAY_REG); \
+ while ((readl(L2CC_BASE_ADDR + L2_CACHE_INV_WAY_REG) & 0xFF) != 0); \
+ HAL_SYNC_L2(); \
+ } \
+}
+ \
+#define HAL_CLEAN_INVALIDATE_L2() \
+{ \
+ if ((readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1) != 0) { \
+ writel(0xFF, L2CC_BASE_ADDR + L2_CACHE_CLEAN_INV_WAY_REG); \
+ while ((readl(L2CC_BASE_ADDR + L2_CACHE_CLEAN_INV_WAY_REG) & 0xFF) != 0);\
+ HAL_SYNC_L2(); \
+ } \
+}
#else //L2CC_ENABLED
#define HAL_DCACHE_SYNC() { \
HAL_DCACHE_SYNC_L1(); \
- HAL_SYNC_L2(); \
+ /* don't just call HAL_SYNC_L2() */ \
+ HAL_CLEAN_INVALIDATE_L2(); \
}
#define HAL_ICACHE_INVALIDATE_ALL() { \
#endif /* __ASSEMBLER__ */
+#define IRAM_BASE_ADDR 0x1FFC0000
/*
* Default Memory Layout Definitions
*/
#define SPBA_BASE_ADDR 0x50000000
#define MMC_SDHC1_BASE_ADDR 0x50004000
#define MMC_SDHC2_BASE_ADDR 0x50008000
+#define ESDHC1_REG_BASE MMC_SDHC1_BASE_ADDR
#define UART3_BASE_ADDR 0x5000C000
#define CSPI2_BASE_ADDR 0x50010000
#define SSI2_BASE_ADDR 0x50014000
#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20)
#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30)
#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40)
+#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50)
#define M3IF_BASE 0xB8003000
#define PCMCIA_CTL_BASE 0xB8004000
#define AVIC_INTTYPEL REG32_PTR(AVIC_BASE_ADDR + (0x1C))
/* L210 */
-#define L2CC_BASE_ADDR 0x30000000
#define L2_CACHE_LINE_SIZE 32
#define L2_CACHE_CTL_REG 0x100
#define L2_CACHE_AUX_CTL_REG 0x104
#define L2_CACHE_SYNC_REG 0x730
#define L2_CACHE_INV_LINE_REG 0x770
#define L2_CACHE_INV_WAY_REG 0x77C
-#define L2_CACHE_CLEAN_LINE_REG 0x7B0
-#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
+#define L2_CACHE_CLEAN_LINE_PA_REG 0x7B0
+#define L2_CACHE_CLEAN_LINE_WAY_REG 0x7B8
+#define L2_CACHE_CLEAN_WAY_REG 0x7BC
+#define L2_CACHE_CLEAN_INV_LINE_PA_REG 0x7F0
+#define L2_CACHE_CLEAN_INV_LINE_WAY_REG 0x7F8
+#define L2_CACHE_CLEAN_INV_WAY_REG 0x7FC
/* CCM */
#define CLKCTL_CCMR 0x00
//#define PLL_REF_CLK FREQ_32768HZ
//#define PLL_REF_CLK FREQ_32000HZ
+/* MMC */
+#define ESDHC_REG_CLK 0x0
+#define ESDHC_REG_INT_STATUS 0x4
+#define ESDHC_REG_CLK_RATE 0x8
+#define ESDHC_REG_BLK_LEN 0x18
+#define ESDHC_REG_NOB 0x1C
+#define ESDHC_REG_INT_STATUS_ENABLE 0x24
+#define ESDHC_REG_COMMAND 0x28
+#define ESDHC_REG_COMMAND_TRANS_TYPE 0x2C
+#define ESDHC_REG_COMMAND_DAT_CONT 0xC
+#define ESDHC_REG_RESFIFO 0x34
+#define ESDHC_REG_BUFFER_DATA 0x38
+
+#define ESDHC_CLEAR_INTERRUPT 0xffffffff
+#define ESDHC_INTERRUPT_ENABLE 0x0000c015
+
/* WEIM - CS0 */
#define CSCRU 0x00
#define CSCRL 0x04
#define UPCTL_PARAM_240 (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
#define UPCTL_PARAM_240_27 (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0))
+/* SPCTL PD MFD MFI MFN */
+#define SPCTL_PARAM_399 (((1-1) << 26) + ((52-1) << 16) + (7 << 10) + (35 << 0))
+#define SPCTL_PARAM_399_27 (((1-1) << 26) + ((5-1) << 16) + (7 << 10) + (2 << 0))
+
/* PDR0 */
#define PDR0_208_104_52 0xFF870D48 /* ARM=208MHz, HCLK=104MHz, IPG=52MHz */
#define PDR0_399_66_66 0xFF872B28 /* ARM=399MHz, HCLK=IPG=66.5MHz */
#define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0)
#define FDO_PAGE_SPARE_VAL 0x8
-#define MXC_NAND_BASE_DUMMY 0x00000000
-#define NOR_FLASH_BOOT 0
+#define MXC_MMC_BASE_DUMMY 0x00000000
+
+#define NOR_FLASH_BOOT 0
#define NAND_FLASH_BOOT 0x10000000
-#define SDRAM_NON_FLASH_BOOT 0x20000000
+#define SDRAM_NON_FLASH_BOOT 0x20000000
+#define MMC_BOOT 0x40000000
#define MXCBOOT_FLAG_REG (AVIC_BASE_ADDR + 0x100)
-#define MXCFIS_NOTHING 0x00000000
-#define MXCFIS_NAND 0x10000000
-#define MXCFIS_NOR 0x20000000
-#define MXCFIS_FLAG_REG (AVIC_BASE_ADDR + 0x104)
+
+#define MXCFIS_NOTHING 0x00000000
+#define MXCFIS_NAND 0x10000000
+#define MXCFIS_NOR 0x20000000
+#define MXCFIS_MMC 0x40000000
+#define MXCFIS_FLAG_REG (AVIC_BASE_ADDR + 0x104)
#define IS_BOOTING_FROM_NAND() (readl(MXCBOOT_FLAG_REG) == NAND_FLASH_BOOT)
-#define IS_BOOTING_FROM_NOR() (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
-#define IS_BOOTING_FROM_SDRAM() (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
+#define IS_BOOTING_FROM_NOR() (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
+#define IS_BOOTING_FROM_SDRAM() (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
+#define IS_BOOTING_FROM_MMC() (readl(MXCBOOT_FLAG_REG) == MMC_BOOT)
#ifndef MXCFLASH_SELECT_NAND
-#define IS_FIS_FROM_NAND() 0
+#define IS_FIS_FROM_NAND() 0
#else
-#define IS_FIS_FROM_NAND() (readl(MXCFIS_FLAG_REG) == MXCFIS_NAND)
+#define IS_FIS_FROM_NAND() (readl(MXCFIS_FLAG_REG) == MXCFIS_NAND)
#endif
#ifndef MXCFLASH_SELECT_NOR
#define IS_FIS_FROM_NOR() 0
#else
-#define IS_FIS_FROM_NOR() (!IS_FIS_FROM_NAND())
+#define IS_FIS_FROM_NOR() (readl(MXCFIS_FLAG_REG) == MXCFIS_NOR)
+#endif
+
+#ifndef MXCFLASH_SELECT_MMC
+#define IS_FIS_FROM_MMC() 0
+#else
+#define IS_FIS_FROM_MMC() (readl(MXCFIS_FLAG_REG) == MXCFIS_MMC)
#endif
#define MXC_ASSERT_NOR_BOOT() writel(MXCFIS_NOR, MXCFIS_FLAG_REG)
-#define MXC_ASSERT_NAND_BOOT() writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
+#define MXC_ASSERT_NAND_BOOT() writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
+#define MXC_ASSERT_MMC_BOOT() writel(MXCFIS_MMC, MXCFIS_FLAG_REG)
/*
* This macro is used to get certain bit field from a number
unsigned int get_peri_clock(enum peri_clocks clk);
enum {
- MXC_NFC_V1,
- MXC_NFC_V2,
+ BOARD_TYPE_UNKNOWN,
+ BOARD_TYPE_ADS,
+ BOARD_TYPE_3STACK,
};
-typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int);
+typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
#endif //#if !defined(__ASSEMBLER__)
);
/*!
- * This is to calculate various parameters based on reference clock and
+ * This is to calculate various parameters based on reference clock and
* targeted clock based on the equation:
* t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
* This calculation is based on a fixed MFD value for simplicity.
*
* @return 0 if successful; non-zero otherwise.
*/
-int calc_pll_params(u32 ref, u32 target, u32 *p_pd,
+int calc_pll_params(u32 ref, u32 target, u32 *p_pd,
u32 *p_mfi, u32 *p_mfn, u32 *p_mfd)
{
u64 pd, mfi, mfn, n_target = (u64)target, n_ref = (u64)ref;
pll_mfd_fixed = 1024;
}
- // Make sure targeted freq is in the valid range. Otherwise the
+ // Make sure targeted freq is in the valid range. Otherwise the
// following calculation might be wrong!!!
if (target < PLL_FREQ_MIN || target > PLL_FREQ_MAX) {
return ERR_WRONG_CLK;
/*!
* This function assumes the expected core clock has to be changed by
* modifying the PLL. This is NOT true always but for most of the times,
- * it is. So it assumes the PLL output freq is the same as the expected
+ * it is. So it assumes the PLL output freq is the same as the expected
* core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
- * In the latter case, it will try to increase the presc value until
+ * In the latter case, it will try to increase the presc value until
* (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
* calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
- * on the targeted PLL and reference input clock to the PLL. Lastly,
+ * on the targeted PLL and reference input clock to the PLL. Lastly,
* it sets the register based on these values along with the dividers.
* Note 1) There is no value checking for the passed-in divider values
* so the caller has to make sure those values are sensible.
* 4) This function should not have allowed diag_printf() calls since
* the serial driver has been stoped. But leave then here to allow
* easy debugging by NOT calling the cyg_hal_plf_serial_stop().
- *
+ *
* @param ref pll input reference clock (32KHz or 26MHz)
* @param core_clk core clock in Hz
- * @param ahb_div ahb divider to divide the core clock to get ahb clock
+ * @param ahb_div ahb divider to divide the core clock to get ahb clock
* (ahb_div - 1) needs to be set in the register
* @param ipg_div ipg divider to divide the ahb clock to get ipg clock
* (ipg_div - 1) needs to be set in the register
diag_printf("can't make hsp_div=%d\n", hsp_div);
return ERR_NO_PRESC;
}
-
+
// get nfc_div - make sure optimal NFC clock but less than NFC_CLK_MAX
for (nfc_div = 1; nfc_div <= NFC_PODF_MAX; nfc_div++) {
if ((pll / (ahb_div * nfc_div)) <= NFC_CLK_MAX) {
return ret;
}
#ifdef CMD_CLOCK_DEBUG
- diag_printf("ref=%d, pll=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
+ diag_printf("ref=%d, pll=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
ref, pll, pd, mfi, mfn, mfd);
#endif
writel(pdr0, CCM_BASE_ADDR + CLKCTL_PDR0);
// calculate new pdr0
pdr0 &= ~0x00003FFF;
- pdr0 |= ((hsp_div - 1) << 11) | ((nfc_div - 1) << 8) | ((ipg_div - 1) << 6) |
+ pdr0 |= ((hsp_div - 1) << 11) | ((nfc_div - 1) << 8) | ((ipg_div - 1) << 6) |
((ahb_div - 1) << 3) | ((presc - 1) << 0);
// update PLL register
ipg_div = data[2]; // actual register field + 1
if (core_clk < (PLL_FREQ_MIN / PRESC_MAX) || core_clk > PLL_FREQ_MAX) {
- diag_printf("Targeted core clock should be within [%d - %d]\n",
+ diag_printf("Targeted core clock should be within [%d - %d]\n",
PLL_FREQ_MIN / PRESC_MAX, PLL_FREQ_MAX);
return;
}
- // find the ahb divider
+ // find the ahb divider
if (ahb_div > AHB_DIV_MAX) {
diag_printf("Invalid AHB divider: %d. Maximum value is %d\n",
ahb_div, AHB_DIV_MAX);
}
}
if (ahb_div > AHB_DIV_MAX || (core_clk / ahb_div) > AHB_CLK_MAX) {
- diag_printf("Can't make AHB=%d since max=%d\n",
+ diag_printf("Can't make AHB=%d since max=%d\n",
core_clk / ahb_div, AHB_CLK_MAX);
return;
}
// find the ipg divider
ahb_clk = core_clk / ahb_div;
if (ipg_div > IPG_DIV_MAX) {
- diag_printf("Invalid IPG divider: %d. Maximum value is %d\n",
+ diag_printf("Invalid IPG divider: %d. Maximum value is %d\n",
ipg_div, IPG_DIV_MAX);
return;
}
ipg_div++; // Make it =2
}
if (ipg_div > IPG_DIV_MAX || (ahb_clk / ipg_div) > IPG_CLK_MAX) {
- diag_printf("Can't make IPG=%d since max=%d\n",
+ diag_printf("Can't make IPG=%d since max=%d\n",
(ahb_clk / ipg_div), IPG_CLK_MAX);
return;
}
ipg_clk = ahb_clk / ipg_div;
- diag_printf("Trying to set core=%d ahb=%d ipg=%d...\n",
+ diag_printf("Trying to set core=%d ahb=%d ipg=%d...\n",
core_clk, ahb_clk, ipg_clk);
// stop the serial to be ready to adjust the clock
diag_printf("===========================================");
diag_printf("=============\n");
- diag_printf("%-16d%-16d%-16d%-16d\n\n",
+ diag_printf("%-16d%-16d%-16d%-16d\n\n",
get_peri_clock(UART1_BAUD),
get_peri_clock(SSI1_BAUD),
get_peri_clock(SSI2_BAUD),
diag_printf("===========================================");
diag_printf("=============\n");
- diag_printf("%-16d%-16d%-16d%-16d\n\n",
+ diag_printf("%-16d%-16d%-16d%-16d\n\n",
get_peri_clock(FIRI_BAUD),
get_peri_clock(SIM_BAUD),
get_peri_clock(MSTICK1_CLK),
val = readl(IOMUXC_BASE_ADDR + 0x80);
writel((val & 0xFFFF) | 0x12120000, IOMUXC_BASE_ADDR + 0x80);
- writel(0x12121212, IOMUXC_BASE_ADDR + 0x84);
- writel(0x12121212, IOMUXC_BASE_ADDR + 0x88);
+ writel(0x12123812, IOMUXC_BASE_ADDR + 0x84);
+
+ val = readl(IOMUXC_BASE_ADDR + 0x88);
+ writel((val & 0xFFFFFF00) | 0x12, IOMUXC_BASE_ADDR + 0x88);
+
+ /* Select CSPI 1 signals */
+ val = readl(IOMUXC_BASE_ADDR + 0x8);
+ writel((val | 0x4), IOMUXC_BASE_ADDR + 0x8);
+
+ val = readl(IOMUXC_BASE_ADDR + 0x78);
+ writel((val & 0xFFFFFF) | 0x24000000, IOMUXC_BASE_ADDR + 0x78);
+
+ val = readl(IOMUXC_BASE_ADDR + 0x7C);
+ writel((val & 0xFFFFFF00) | 0x24, IOMUXC_BASE_ADDR + 0x7C);
+
writel(0x12121212, IOMUXC_BASE_ADDR + 0x8C);
+
+ val = readl(IOMUXC_BASE_ADDR + 0x88);
+ writel((val & 0xFF) | 0x12121200, IOMUXC_BASE_ADDR + 0x88);
+}
+
+// The clocks are on by default. But need to setup the IOMUX
+void mxc_i2c_init(unsigned int module_base)
+{
+ unsigned int val, reg;
+
+ switch (module_base) {
+ case I2C_BASE_ADDR:
+ reg = IOMUXC_BASE_ADDR + 0xA0;
+ val = (readl(reg) & 0xFFFF0000) | 0x1212; // func mode
+ writel(val, reg);
+ break;
+ case I2C2_BASE_ADDR:
+ reg = IOMUXC_BASE_ADDR + 0x88;
+ val = (readl(reg) & 0xFFFFFF00) | 0x24; // alt mode 1
+ writel(val, reg);
+ reg = IOMUXC_BASE_ADDR + 0x84;
+ val = (readl(reg) & 0x00FFFFFF) | 0x24000000; // alt mode 1
+ writel(val, reg);
+ break;
+ case I2C3_BASE_ADDR:
+ reg = IOMUXC_BASE_ADDR + 0x84;
+ val = (readl(reg) & 0xFFFFFF00) | 0x24; // alt mode 1
+ writel(val, reg);
+ reg = IOMUXC_BASE_ADDR + 0x80;
+ val = (readl(reg) & 0x00FFFFFF) | 0x24000000; // alt mode 1
+ writel(val, reg);
+ break;
+ default:
+ diag_printf("Invalide I2C base: 0x%x\n", module_base);
+ return;
+ }
}
/*!
case SIM_BAUD:
clk_sel = ccmr & (1 << 24);
pdf = (mpdr0 >> 16) & 0x1F;
- ret_val = (clk_sel != 0) ? get_main_clock(IPG_CLK) :
+ ret_val = (clk_sel != 0) ? get_main_clock(IPG_CLK) :
pll_clock(USB_PLL) / (pdf + 1);
break;
case SSI1_BAUD:
case CSI_BAUD:
clk_sel = ccmr & (1 << 25);
pdf = (mpdr0 >> 23) & 0x1FF;
- ret_val = (clk_sel != 0) ? (pll_clock(SER_PLL) / (pdf + 1)) :
+ ret_val = (clk_sel != 0) ? (pll_clock(SER_PLL) / (pdf + 1)) :
(pll_clock(USB_PLL) / (pdf + 1));
break;
case FIRI_BAUD:
cosr = readl(CCM_BASE_ADDR + CLKCTL_COSR);
diag_printf("%s\n", clko_name[(cosr & 0xF) + 1]);
- diag_printf("COSR register[0x%x] = 0x%x\n",
+ diag_printf("COSR register[0x%x] = 0x%x\n",
(CCM_BASE_ADDR + CLKCTL_COSR), cosr);
}
/*
* The action should be either:
- * POLL_FUSE_PRGD
+ * POLL_FUSE_PRGD
* or:
* POLL_FUSE_SNSD
*/
int addr, addr_l, addr_h, reg_addr;
fuse_op_start();
-
+
addr = ((bank << 11) | (row << 3) | (bit & 0x7));
/* Set IIM Program Upper Address */
addr_h = (addr >> 8) & 0x000000FF;
#define INIT_STRING "12345678"
static char ready_to_blow[] = INIT_STRING;
-void quick_itoa(u32 num, char *a)
+void quick_itoa(u32 num, char *a)
{
- int i, j, k;
+ int i, j, k;
for (i = 0; i <= 7; i++) {
j = (num >> (4 * i)) & 0xF;
k = (j < 10) ? '0' : ('a' - 0xa);
}
return;
} else if (argc == 3) {
- if (strcasecmp(argv[1], "nandboot") == 0 &&
+ if (strcasecmp(argv[1], "nandboot") == 0 &&
strcasecmp(argv[2], ready_to_blow) == 0) {
#if defined(CYGPKG_HAL_ARM_MXC91131) || defined(CYGPKG_HAL_ARM_MX21) || defined(CYGPKG_HAL_ARM_MX27) || defined(CYGPKG_HAL_ARM_MX31)
diag_printf("No need to blow any fuses for NAND boot on this platform\n\n");
#ifdef debug_uart_log_buf
__log_buf[diag_bp++] = c;
-#endif
-
+#endif
+
CYGARC_HAL_SAVE_GP();
// Wait for Tx FIFO not full
CYGARC_HAL_RESTORE_GP();
}
-static cyg_bool cyg_hal_plf_serial_getc_nonblock(void* __ch_data,
+static cyg_bool cyg_hal_plf_serial_getc_nonblock(void* __ch_data,
cyg_uint8* ch)
{
volatile struct mxc_serial* base = ((channel_data_t*)__ch_data)->base;
CYGARC_HAL_RESTORE_GP();
}
-static void cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf,
+static void cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf,
cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
CYGARC_HAL_RESTORE_GP();
}
-cyg_bool cyg_hal_plf_serial_getc_timeout(void* __ch_data,
- cyg_uint8* ch)
+cyg_bool cyg_hal_plf_serial_getc_timeout(void* __ch_data,
+ cyg_uint8* ch)
{
int delay_count;
channel_data_t* chan = (channel_data_t*)__ch_data;
return res;
}
-static int cyg_hal_plf_serial_control(void *__ch_data,
- __comm_control_cmd_t __func, ...)
+static int cyg_hal_plf_serial_control(void *__ch_data,
+ __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
#define MAJOR_NUMBER_OFFSET (4)
#define MINOR_NUMBER_OFFSET (0)
-/*
+/*
* System_rev will have the following format
* 31-12 = part # (0x31, 0x32, 0x27, 0x91131, 0x91321, etc)
* 11-8 = unused
*/
unsigned int system_rev = CHIP_REV_1_0;
static int find_correct_chip;
-
-char HAL_PLATFORM_EXTRA[55] = "MX31 ADS (Freescale i.MX31 based) PASS 1.0 [x32 DDR]";
+int g_board_type = BOARD_TYPE_UNKNOWN;
+extern char HAL_PLATFORM_EXTRA[60];
/*
* This functions reads the IIM module and returns the system revision number.
if (MXC_GET_FIELD(val, IIM_PROD_REV_LEN, IIM_PROD_REV_SH) ==
PROD_SIGNATURE_MX32) {
system_rev = 0x32 << PART_NUMBER_OFFSET; /* For MX32 Platform*/
- HAL_PLATFORM_EXTRA[3] = '2';
- HAL_PLATFORM_EXTRA[25] = '2';
+ if (g_board_type == BOARD_TYPE_ADS) {
+ HAL_PLATFORM_EXTRA[3] = '2';
+ HAL_PLATFORM_EXTRA[25] = '2';
+ } else if (g_board_type == BOARD_TYPE_3STACK) {
+ HAL_PLATFORM_EXTRA[3] = '2';
+ HAL_PLATFORM_EXTRA[29] = '2';
+ }
} else {
system_rev = 0x31 << PART_NUMBER_OFFSET; /* For MX31 Platform*/
}
extern nfc_setup_func_t *nfc_setup;
unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz,
- unsigned int is_mlc);
+ unsigned int is_mlc, unsigned int num_of_chips);
void hal_hardware_init(void)
{
volatile unsigned int esdmisc = readl(ESDCTL_BASE + 0x10);
volatile unsigned int esdctl0 = readl(ESDCTL_BASE);
- int ver = read_system_rev();
+ int ver;
+ char chip_ver[2];
+
+ // Perform any platform specific initializations
+ plf_hardware_init();
+
+ ver = read_system_rev();
find_correct_chip = ver;
/* Valid product revision found. Check actual silicon rev and
* NOT use the version from the ROM code. */
if (((ver >> 4) & 0xF) == 0x0) {
- HAL_PLATFORM_EXTRA[39] = '1';
- HAL_PLATFORM_EXTRA[41] = '0';
+ chip_ver[0] = '1';
+ chip_ver[1] = '0';
system_rev |= 1 << MAJOR_NUMBER_OFFSET ;/*Major Number*/
system_rev |= 0 << MINOR_NUMBER_OFFSET ;/*Minor Number*/
} else if (((ver >> 4) & 0xF) == 0x1) {
- HAL_PLATFORM_EXTRA[39] = '1';
- HAL_PLATFORM_EXTRA[41] = '1';
- system_rev |= 1 << MAJOR_NUMBER_OFFSET ;/*Major Number*/
+ chip_ver[0] = '1';
+ chip_ver[1] = '1';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET ;/*Major Number*/
system_rev |= 1 << MINOR_NUMBER_OFFSET ;/*Minor Number*/
} else if (((ver >> 4) & 0xF) == 0x2) {
- HAL_PLATFORM_EXTRA[39] = '2';
- HAL_PLATFORM_EXTRA[41] = '0';
+ chip_ver[0] = '2';
+ chip_ver[1] = '0';
system_rev |= 2 << MAJOR_NUMBER_OFFSET ;/*Major Number*/
system_rev |= 0 << MINOR_NUMBER_OFFSET ;/*Minor Number*/
} else {
- HAL_PLATFORM_EXTRA[39] = 'x';
- HAL_PLATFORM_EXTRA[41] = 'x';
+ chip_ver[0] = 'x';
+ chip_ver[1] = 'x';
system_rev |= 1 << MAJOR_NUMBER_OFFSET ;/*Major Number*/
system_rev |= 0 << MINOR_NUMBER_OFFSET ;/*Minor Number*/
find_correct_chip = CHIP_VERSION_UNKNOWN;
}
}
- if ((esdmisc & 0x4) == 0) {
- HAL_PLATFORM_EXTRA[48] = 'S';
- }
- if ((esdctl0 & 0x30000) != 0x20000) {
- HAL_PLATFORM_EXTRA[45] = '1';
- HAL_PLATFORM_EXTRA[46] = '6';
+ if (g_board_type == BOARD_TYPE_ADS) {
+ HAL_PLATFORM_EXTRA[39] = chip_ver[0];
+ HAL_PLATFORM_EXTRA[41] = chip_ver[1];
+ if ((esdmisc & 0x4) == 0) {
+ HAL_PLATFORM_EXTRA[48] = 'S';
+ }
+ if ((esdctl0 & 0x30000) != 0x20000) {
+ HAL_PLATFORM_EXTRA[45] = '1';
+ HAL_PLATFORM_EXTRA[46] = '6';
+ }
+ } else if (g_board_type == BOARD_TYPE_3STACK) {
+ HAL_PLATFORM_EXTRA[43] = chip_ver[0];
+ HAL_PLATFORM_EXTRA[45] = chip_ver[1];
+ if ((esdmisc & 0x4) == 0) {
+ HAL_PLATFORM_EXTRA[52] = 'S';
+ }
+ if ((esdctl0 & 0x30000) != 0x20000) {
+ HAL_PLATFORM_EXTRA[49] = '1';
+ HAL_PLATFORM_EXTRA[50] = '6';
+ }
}
// Mask all interrupts
writew(readw(WDOG_BASE_ADDR) | 0xFF00, WDOG_BASE_ADDR);
}
- // Perform any platform specific initializations
- plf_hardware_init();
-
// Set up eCos/ROM interfaces
hal_if_init();
#define WDT_MAGIC_2 0xAAAA
#define MXC_WDT_WSR 0x2
+unsigned int i2c_base_addr[] = {
+ I2C_BASE_ADDR,
+ I2C2_BASE_ADDR,
+ I2C3_BASE_ADDR
+};
+unsigned int i2c_num = 3;
+
static unsigned int led_on = 0;
//
// Delay for some number of micro-seconds
// Interrupt priorities are not configurable.
}
-unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz, unsigned int is_mlc)
+unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz, unsigned int is_mlc, unsigned int num_of_chips)
{
unsigned int tmp, res = -1;
tmp = readw(NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF) & (~(1 << 9));
}
writew(tmp, NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF);
-
+
if (pg_sz == 2048) {
tmp = readl(CCM_BASE_ADDR + CLKCTL_RCSR) | (1 << 30);
} else {
tmp = readl(CCM_BASE_ADDR + CLKCTL_RCSR) & (~(1 << 30));
}
writel(tmp, CCM_BASE_ADDR + CLKCTL_RCSR);
-
+
if (io_sz == 16) {
tmp = readl(CCM_BASE_ADDR + CLKCTL_RCSR) | (1 << 31);
} else {
break;
default:
diag_printf("Unknown chip version: 0x%x\n", tmp);
- break;
}
return res;
}
description "
The processor can run at various frequencies.
These values are expressed in KHz. Note that there are
- several steppings of the rated to run at different
+ several steppings of the rate to run at different
maximum frequencies. Check the specs to make sure that your
particular processor can run at the rate you select here."
}
writel(tmp, CCM_BASE_ADDR + CLKCTL_RCSR);
diag_printf("NAND: RCSR=%x\n", tmp);
- return 0x10;
+ return MXC_NFC_V1;
}
static void check_reset_source(void)
--- /dev/null
+# ====================================================================
+#
+# hal_arm_tx37.cdl
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+
+cdl_package CYGPKG_HAL_ARM_TX37KARO {
+ display "Ka-Ro TX37 module"
+ parent CYGPKG_HAL_ARM_MX37
+ requires CYGINT_ISO_CTYPE
+ hardware
+ include_dir cyg/hal
+ define_header hal_arm_tx37.h
+ description "
+ This HAL platform package provides generic
+ support for the Ka-Ro electronics TX37 module."
+
+ compile tx37_misc.c tx37_diag.c
+ implements CYGINT_HAL_DEBUG_GDB_STUBS
+ implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+ implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+
+ implements CYGHWR_HAL_ARM_SOC_UART1
+ implements CYGHWR_HAL_ARM_SOC_UART2
+
+ requires {CYGBLD_BUILD_REDBOOT == 1}
+
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_soc.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_tx37.h>"
+ puts $::cdl_header "#define HAL_PLATFORM_CPU \"Freescale i.MX37 based\""
+ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Ka-Ro TX37 processor module\""
+ puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 1575"
+ puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK tx37_program_new_stack"
+ }
+
+ cdl_component CYG_HAL_STARTUP {
+ display "Startup type"
+ flavor data
+ default_value { "ROMRAM" }
+ legal_values { "ROMRAM" }
+ no_define
+ define -file system.h CYG_HAL_STARTUP
+ description "
+ The only startup type allowed is ROMRAM, since this will allow
+ the program to exist in ROM, but be copied to RAM during startup
+ which is required to boot from NAND flash."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ display "Diagnostic serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the console port.
+ Note: this should match the value chosen for the GDB port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ display "GDB serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the GDB port.
+ Note: this should match the value chosen for the console port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the TX37"
+ flavor data
+ calculated 2
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ The TX37 provides access to two serial ports. This option
+ chooses which port will be used to connect to a host
+ running GDB."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+ display "Default console channel."
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ calculated 0
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Console serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ description "
+ The TX37 provides access to two serial ports. This option
+ chooses which port will be used for console output."
+ }
+
+ cdl_component CYGBLD_GLOBAL_OPTIONS {
+ display "Global build options"
+ flavor none
+ no_define
+ description "
+ Global build options including control over
+ compiler flags, linker flags and choice of toolchain."
+
+
+ parent CYGPKG_NONE
+
+ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ display "Global command prefix"
+ flavor data
+ no_define
+ default_value { "arm-1136jfs-linux-gnu" }
+ description "
+ This option specifies the command prefix used when
+ invoking the build tools."
+ }
+
+ cdl_option CYGBLD_GLOBAL_CFLAGS {
+ display "Global compiler flags"
+ flavor data
+ no_define
+ requires CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS
+ default_value { "-mcpu=arm9 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe" }
+ description "
+ This option controls the global compiler flags which are used to
+ compile all packages by default. Individual packages may define
+ options which override these global flags."
+ }
+
+ cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ display "Global linker flags"
+ flavor data
+ no_define
+ default_value { "-Wl,--gc-sections -Wl,-static -O2 -nostdlib" }
+ description "
+ This option controls the global linker flags. Individual
+ packages may define options which override these global flags."
+ }
+ }
+
+ cdl_component CYGPKG_HAL_ARM_TX37_OPTIONS {
+ display "Ka-Ro electronics TX37 module build options"
+ flavor none
+ no_define
+ requires { CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0 }
+ description "
+ Package specific build options including control over
+ compiler flags used only in building this package,
+ and details of which tests are built."
+
+ cdl_option CYGNUM_HAL_ARM_TX37_SDRAM_SIZE {
+ display "SDRAM size"
+ flavor data
+ legal_values { 0x08000000 0x04000000 }
+ default_value { 0x08000000 }
+# This is what I would like to do, but define_proc currently does not allow for
+# accessing variables
+# display "SDRAM size in MiB"
+# legal_values { 128 }
+# default_value { 128 }
+# define_proc {
+# puts $::cdl_header "#define CYGNUM_HAL_ARM_TX37_SDRAM_SIZE \
+# [format "0x%08x" [expr $CYGNUM_HAL_ARM_TX37_SDRAM_SIZE * 1048576]]"
+# }
+ description "
+ This option specifies the SDRAM size of the TX37 module."
+ }
+
+ cdl_option CYGOPT_HAL_ARM_TX37_DEBUG {
+ display "Enable low level debugging with LED"
+ flavor bool
+ default_value { false }
+ description "
+ This option enables low level debugging by blink codes
+ of the LED on STK5."
+ }
+
+ cdl_option CYGPKG_HAL_ARM_TX37_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the TX37 HAL. These flags are used in addition
+ to the set of global flags."
+ }
+
+ cdl_option CYGPKG_HAL_ARM_TX37_CFLAGS_REMOVE {
+ display "Suppressed compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the TX37 HAL. These flags are removed from
+ the set of global flags if present."
+ }
+
+ }
+
+ cdl_component CYGHWR_MEMORY_LAYOUT {
+ display "Memory layout"
+ flavor data
+ no_define
+ calculated { "arm_tx37_romram" }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ display "Memory layout linker script fragment"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+ calculated { "<pkgconf/mlt_arm_tx37_romram.ldi>" }
+ }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ display "Memory layout header file"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_H
+ calculated { "<pkgconf/mlt_arm_tx37_romram.h>" }
+ }
+ }
+
+ cdl_option CYGSEM_HAL_ROM_MONITOR {
+ display "Behave as a ROM monitor"
+ flavor bool
+ default_value 0
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+ description "
+ Enable this option if this program is to be used as a ROM monitor,
+ i.e. applications will be loaded into RAM on the TX37 module, and this
+ ROM monitor may process exceptions or interrupts generated from the
+ application. This enables features such as utilizing a separate
+ interrupt stack when exceptions are generated."
+ }
+
+ cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ display "Work with a ROM monitor"
+ flavor booldata
+ legal_values { "Generic" "GDB_stubs" }
+ default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "RAM" }
+ description "
+ Support can be enabled for different varieties of ROM monitor.
+ This support changes various eCos semantics such as the encoding
+ of diagnostic output, or the overriding of hardware interrupt
+ vectors.
+ Firstly there is \"Generic\" support which prevents the HAL
+ from overriding the hardware vectors that it does not use, to
+ instead allow an installed ROM monitor to handle them. This is
+ the most basic support which is likely to be common to most
+ implementations of ROM monitor.
+ \"GDB_stubs\" provides support when GDB stubs are included in
+ the ROM monitor or boot ROM."
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ display "Redboot HAL options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+ description "
+ This option lists the target's requirements for a valid Redboot
+ configuration."
+
+ compile -library=libextras.a redboot_cmds.c
+
+ cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ display "Build Redboot ROM binary image"
+ active_if CYGBLD_BUILD_REDBOOT
+ default_value 1
+ no_define
+ description "This option enables the conversion of the Redboot ELF
+ image to a binary image suitable for ROM programming."
+
+ make -priority 325 {
+ <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+ $(OBJCOPY) -O binary $< $@
+ $(COMMAND_PREFIX)nm $< | awk 'NF == 3 {print}' | sort > $(<:.elf=.map)
+ }
+ }
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_TX37_OPTIONS {
+ display "Redboot HAL variant options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+
+ # RedBoot details
+ requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x40108000 }
+ define_proc {
+ puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00"
+ }
+ }
+}
--- /dev/null
+#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
+#define CYGONCE_HAL_PLATFORM_SETUP_H
+
+//=============================================================================
+//
+// hal_platform_setup.h
+//
+// Platform specific support for HAL (assembly code)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <pkgconf/system.h> // System-wide configuration info
+#include CYGBLD_HAL_VARIANT_H // Variant specific configuration
+#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
+#include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
+#include <cyg/hal/hal_mmu.h> // MMU definitions
+#include <cyg/hal/karo_tx37.h> // Platform specific hardware definitions
+
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1 _platform_setup1
+#define CYGHWR_HAL_ARM_HAS_MMU
+
+#ifdef CYG_HAL_STARTUP_ROMRAM
+#define CYGSEM_HAL_ROM_RESET_USES_JUMP
+#endif
+
+//#define NFC_2K_BI_SWAP
+#define SDRAM_FULL_PAGE_BIT 0x100
+#define SDRAM_FULL_PAGE_MODE 0x37
+#define SDRAM_BURST_MODE 0x33
+
+#define CYGHWR_HAL_ROM_VADDR 0x0
+
+#if 0
+#define UNALIGNED_ACCESS_ENABLE
+#define SET_T_BIT_DISABLE
+#define BRANCH_PREDICTION_ENABLE
+#endif
+
+
+#define TX37_NAND_PAGE_SIZE 2048
+#define TX37_NAND_BLKS_PER_PAGE 64
+
+#ifndef CYGOPT_HAL_ARM_TX37_DEBUG
+ .macro LED_CTRL,val
+ .endm
+ .macro LED_BLINK,val
+ .endm
+#define DELAY
+#else
+#define CYGHWR_LED_MACRO LED_BLINK #\x
+ .macro DELAY,ms
+ ldr r10, =\ms
+111:
+ subs r10, r10, #1
+ bmi 113f
+ ldr r9, =3000
+112:
+ subs r9, r9, #1
+ bne 112b
+ b 111b
+ .ltorg
+113:
+ .endm
+
+ .macro LED_CTRL,val
+ // switch user LED (GPIO2_19) on STK5
+ ldr r10, GPIO2_BASE_ADDR_W
+ mov r9, #\val
+ cmp r9, #0
+ movne r9, #(1 << 19) // LED ON
+ moveq r9, #0 // LED OFF
+ str r9, [r10, #0x00] @ GPIO_DR
+ .endm
+
+ .macro LED_BLINK,val
+ mov r2, \val
+211:
+ subs r2, r2, #1
+ bmi 212f
+ LED_CTRL 1
+ DELAY 200
+ LED_CTRL 0
+ DELAY 300
+ b 211b
+212:
+ DELAY 1000
+ .endm
+#endif
+
+ .macro LED_INIT
+ // initialize GPIO2[19] for LED on STK5
+ ldr r10, IOMUXC_BASE_ADDR_W
+ @ AUD5_RXC = ALT4 (GPIO2[19])
+ mov r9, #4
+ str r9, [r10, #0x120]
+ ldr r10, GPIO2_BASE_ADDR_W
+
+ mov r9, #(1 << 19)
+ str r9, [r10, #0x00] @ GPIO_DR
+
+ mov r9, #(1 << 19)
+ str r9, [r10, #0x04] @ GPIO_GDIR
+ .endm
+
+//#define ENABLE_IMPRECISE_ABORT
+
+/*
+#define PLATFORM_PREAMBLE flash_header
+
+//flash header & DCD @ 0x400
+.macro flash_header
+ b reset_vector
+.org 0x400
+app_code_jump_v: .long reset_vector
+app_code_barker: .long 0xB1
+app_code_csf: .long 0
+dcd_ptr_ptr: .long dcd_ptr
+super_root_key: .long 0
+dcd_ptr: .long dcd_data
+app_dest_ptr: .long CYGMEM_REGION_rom - REDBOOT_OFFSET
+
+dcd_data: .long 0xB17219E9
+dcd_len: .long (49 * 12)
+
+//DCD
+//iomux 1
+// KEY_ROW0 -> EMI_DRAM_D[16]
+.long 4
+.long 0xc3fa8008
+.long 0x1
+// 2
+// KEY_ROW1 -> EMI_DRAM_D[17]
+.long 4
+.long 0xc3fa800c
+.long 0x1
+// 3
+// KEY_ROW2 -> EMI_DRAM_D[18]
+.long 4
+.long 0xc3fa8010
+.long 0x1
+// 4
+// KEY_ROW3 -> EMI_DRAM_D[19]
+.long 4
+.long 0xc3fa8014
+.long 0x1
+//5
+// KEY_ROW4 -> EMI_DRAM_D[20]
+.long 4
+.long 0xc3fa8018
+.long 0x1
+//6
+// KEY_ROW5 -> EMI_DRAM_D[21]
+.long 4
+.long 0xc3fa801c
+.long 0x1
+// 7
+// KEY_ROW6 -> EMI_DRAM_D[22]
+.long 4
+.long 0xc3fa8020
+.long 0x1
+// 8
+// KEY_ROW7 -> EMI_DRAM_D[23]
+.long 4
+.long 0xc3fa8024
+.long 0x1
+// 9
+// KEY_ROW7
+// IETM_D0 -> EMI_DRAM_D[24]
+.long 4
+.long 0xc3fa8028
+.long 0x1
+
+//10
+// IETM_D1 -> EMI_DRAM_D[25]
+.long 4
+.long 0xc3fa802c
+.long 0x1
+
+// 11
+// IETM_D2 -> EMI_DRAM_D[26]
+.long 4
+.long 0xc3fa8030
+.long 0x1
+
+// 12
+// IETM_D3 -> EMI_DRAM_D[27]
+.long 4
+.long 0xc3fa8034
+.long 0x1
+
+// 13
+// IETM_D4 -> EMI_DRAM_D[28]
+.long 4
+.long 0xc3fa8038
+.long 0x1
+
+// 14
+// IETM_D5 -> EMI_DRAM_D[29]
+.long 4
+.long 0xc3fa803c
+.long 0x1
+
+// 15
+// IETM_D6 -> EMI_DRAM_D[30]
+.long 4
+.long 0xc3fa8040
+.long 0x1
+
+// 16
+// IETM_D7 -> EMI_DRAM_D[31]
+.long 4
+.long 0xc3fa8044
+.long 0x1
+
+// 17
+// EIM_EB0 -> DRAM_DQM[2]
+.long 4
+.long 0xc3fa8048
+.long 0x1
+
+// 18
+// EIM_EB1 -> DRAM_DQM[3]
+.long 4
+.long 0xc3fa804c
+.long 0x1
+
+// 19
+// EIM_ECB -> DRAM_SDQS[2]
+.long 4
+.long 0xc3fa805c
+.long 0x1
+
+// 20
+// SW_PAD_CTL_PAD_EIM_ECB -> DDR input type / Pull/Keeper Enabled / Pull / 100KOhm Pull Down / High Drive Strength
+.long 4
+.long 0xc3fa82bc
+.long 0x02c4
+
+// 21
+// EIM_LBA -> DRAM_SDQS[3]
+.long 4
+.long 0xc3fa8060
+.long 0x1
+
+// 22
+// SW_PAD_CTL_PAD_EIM_LBA -> DDR input type / Pull/Keeper Enabled / Pull / 100KOhm Pull Down / High Drive Strength
+.long 4
+.long 0xc3fa82c0
+.long 0x02c4
+
+// 23
+// SW_PAD_CTL_GRP_S7 -> Medium Drive Strength
+.long 4
+.long 0xc3fa84a8
+.long 0x2
+
+// 24
+// SW_PAD_CTL_GRP_S8 -> Medium Drive Strength
+.long 4
+.long 0xc3fa84b0
+.long 0x2
+
+// 25
+// SW_PAD_CTL_GRP_S9 -> Medium Drive Strength
+.long 4
+.long 0xc3fa84b4
+.long 0x2
+
+// 26
+// SW_PAD_CTL_GRP_S10 -> Medium Drive Strength
+.long 4
+.long 0xc3fa84e0
+.long 0x2
+
+// 27
+// SW_PAD_CTL_PAD_DRAM_DQM0 -> Medium Drive Strength
+.long 4
+.long 0xc3fa8278
+.long 0x2
+
+// 28
+// SW_PAD_CTL_PAD_DRAM_DQM1 -> Medium Drive Strength
+.long 4
+.long 0xc3fa827c
+.long 0x2
+
+// 29
+// DRAM_SDQS0 -> Medium Drive Strength
+.long 4
+.long 0xc3fa8298
+.long 0x2
+
+// 30
+// DRAM_SDQS1 -> Medium Drive Strength
+.long 4
+.long 0xc3fa829c
+.long 0x2
+
+// 31
+// SW_PAD_CTL_GRP_S3 -> Medium Drive Strength
+.long 4
+.long 0xc3fa84fc
+.long 0x2
+
+// 32
+// SW_PAD_CTL_GRP_S4 -> Medium Drive Strength
+.long 4
+.long 0xc3fa8504
+.long 0x2
+
+// 33
+// SW_PAD_CTL_GRP_S5 -> Medium Drive Strength
+.long 4
+.long 0xc3fa848c
+.long 0x2
+
+// 34
+// SW_PAD_CTL_GRP_S6 -> Medium Drive Strength
+.long 4
+.long 0xc3fa849c
+.long 0x2
+
+// 35
+// DRAM_SDCLK -> Medium Drive Strength
+.long 4
+.long 0xc3fa8294
+.long 0x2
+
+// 36
+// SW_PAD_CTL_PAD_DRAM_RAS -> Medium Drive Strength
+.long 4
+.long 0xc3fa8280
+.long 0x2
+
+// 37
+// SW_PAD_CTL_PAD_DRAM_CAS -> Medium Drive Strength
+.long 4
+.long 0xc3fa8284
+.long 0x2
+
+// 38
+// SW_PAD_CTL_PAD_DRAM_SDWE -> Medium Drive Strength
+.long 4
+.long 0xc3fa8288
+.long 0x2
+
+// 39
+// SW_PAD_CTL_PAD_DRAM_SDCKE0 -> Medium Drive Strength
+.long 4
+.long 0xc3fa828c
+.long 0x2
+
+// 40
+// SW_PAD_CTL_PAD_DRAM_SDCKE1 -> Medium Drive Strength
+.long 4
+.long 0xc3fa8290
+.long 0x2
+
+// set CSD0 1
+// 41
+.long 4
+.long 0xe3fd9000
+.long 0x80000000
+
+// Precharge command 2
+// 42
+.long 4
+.long 0xe3fd9014
+.long 0x04008008
+// refresh commands 3
+// 43
+.long 4
+.long 0xe3fd9014
+.long 0x00008010
+
+// 44
+.long 4
+.long 0xe3fd9014
+.long 0x00008010
+// LMR with CAS=3 BL=3 5
+// 45
+.long 4
+.long 0xe3fd9014
+.long 0x00338018
+
+// 13row 9 col 32 bit sref=4 micro model 6
+// 46
+.long 4
+.long 0xe3fd9000
+.long 0xB2120000
+
+// timing parameter 7
+// 47
+.long 4
+.long 0xe3fd9004
+.long 0x70395729
+
+// mddr enable RLAT=2 8
+// 48
+.long 4
+.long 0xe3fd9010
+.long 0x000A0084
+
+// Normal mode 9
+// 49
+.long 4
+.long 0xe3fd9014
+.long 0x00000000
+
+image_len: .long REDBOOT_IMAGE_SIZE
+.endm
+*/
+
+// This macro represents the initial startup code for the platform
+ .macro _platform_setup1
+KARO_TX37_SETUP_START:
+/*
+ * ARM1136 init
+ * - invalidate I/D cache/TLB and drain write buffer;
+ * - invalidate L2 cache
+ * - unaligned access
+ * - branch predictions
+ */
+ // mrc p15, 0, r0, c1, c1, 0 // Read Secure Configuration Register data. Why doesn't work???
+ // mcr p15, 0, <Rd>, c1, c1, 0 ; Write Secure Configuration Register data
+#ifdef ENABLE_IMPRECISE_ABORT
+ mrs r1, spsr // save old spsr
+ mrs r0, cpsr // read out the cpsr
+ bic r0, r0, #0x100 // clear the A bit
+ msr spsr, r0 // update spsr
+ add lr, pc, #0x8 // update lr
+ movs pc, lr // update cpsr
+ nop
+ nop
+ nop
+ nop
+ msr spsr, r1 // restore old spsr
+#endif
+ mov r0, #0
+ mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
+ mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+ mcr 15, 0, r0, c7, c10, 4 /* Data write barrier */
+
+ /* Also setup the Peripheral Port Remap register inside the core */
+ ldr r0, ARM_PPMRR /* start from AIPS 2GB region */
+ mcr p15, 0, r0, c15, c2, 4
+#ifdef L2CC_ENABLED
+ cmp pc, #SDRAM_BASE_ADDR
+ blo 1f
+ cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
+ blo skip_l2
+
+ /*** L2 Cache setup/invalidation/disable ***/
+ /* Disable L2 cache first */
+ mov r0, #L2CC_BASE_ADDR
+ mov r2, #0
+ str r2, [r0, #L2_CACHE_CTL_REG]
+ /*
+ * Configure L2 Cache:
+ * - 128k size(16k way)
+ * - 8-way associativity
+ * - 0 ws TAG/VALID/DIRTY
+ * - 4 ws DATA R/W
+ */
+ mov r2, #0xFF000000
+ add r2, r2, #0x00F00000
+ ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
+ and r1, r1, r2
+ ldr r2, L2CACHE_PARAM
+ orr r1, r1, r2
+ str r1, [r0, #L2_CACHE_AUX_CTL_REG]
+
+ /* Invalidate L2 */
+ mov r1, #0xFF
+ str r1, [r0, #L2_CACHE_INV_WAY_REG]
+L2_loop:
+ /* Poll Invalidate By Way register */
+ ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
+ ands r2, r2, #0xFF
+ bne L2_loop
+ /*** End of L2 operations ***/
+skip_l2:
+#endif
+
+/*
+ * End of ARM1136 init
+ */
+init_spba_start:
+ init_spba
+init_aips_start:
+ init_aips
+init_max_start:
+ init_max
+init_m4if_start:
+ init_m4if
+init_iomux_start:
+ init_iomux
+
+ LED_INIT
+ LED_CTRL 0
+
+ // disable wdog
+ mov r0, #0x30
+ ldr r1, WDOG1_BASE_W
+ strh r0, [r1]
+
+ /* If SDRAM has been setup, bypass clock/WEIM setup */
+ cmp pc, #SDRAM_BASE_ADDR
+ blo external_boot_cont
+ cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
+ blo internal_boot_cont
+
+external_boot_cont:
+init_sdram_start:
+ setup_sdram
+
+internal_boot_cont:
+init_clock_start:
+ init_clock
+
+HWInitialise_skip_SDRAM_setup:
+ ldr r0, NFC_BASE_W
+ add r2, r0, #0x1000 // 4K window
+ cmp pc, r0
+ blo Normal_Boot_Continue
+ cmp pc, r2
+ bhs Normal_Boot_Continue
+
+NAND_Boot_Start:
+ /* Copy image from flash to SDRAM first */
+ ldr r1, MXC_REDBOOT_RAM_START
+1:
+ ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ blo 1b
+
+ /* Jump to SDRAM */
+ ldr r1, CONST_0x0FFF
+ and r0, pc, r1 /* offset of pc */
+ ldr r1, MXC_REDBOOT_RAM_START
+ add r1, r1, #0x8
+ add pc, r0, r1
+ nop
+
+Now_in_SDRAM:
+NAND_Copy_Main:
+ // Check if x16/2kb page
+ // ldr r7, CCM_BASE_ADDR_W
+ // ldr r7, [r7, #0xC]
+ // ands r7, r7, #(1 << 30)
+ ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
+ mov r1, #TX37_NAND_PAGE_SIZE //r1: starting flash addr to be copied. Updated constantly
+ // ???? should be dynamic based on the page size kevin todo
+ add r2, r0, #TX37_NAND_PAGE_SIZE //r2: end of 3rd RAM buf. Doesn't change ?? dynamic
+
+ ldr r11, NFC_IP_BASE_W //r11: NFC IP register base. Doesn't change
+ add r12, r0, #0x1E00 //r12: NFC AXI register base. Doesn't change
+ ldr r14, MXC_REDBOOT_RAM_START
+ add r13, r14, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
+ add r14, r14, r1 //r14: starting SDRAM address for copying. Updated constantly
+
+ //unlock internal buffer
+ mov r3, #0xFF000000
+ add r3, r3, #0x00FF0000
+ str r3, [r11, #0x4]
+ str r3, [r11, #0x8]
+ str r3, [r11, #0xC]
+ str r3, [r11, #0x10]
+ mov r3, #0x20000 // BLS = 2 -> Buffer Lock Set = unlocked
+ add r3, r3, #0x4 // WPC = 4 -> write protection command = unlock blocks
+ str r3, [r11, #0x0] // kevin - revist for multiple CS ??
+ mov r3, #0
+ str r3, [r11, #0x18]
+
+Nfc_Read_Page:
+ mov r3, #0x0
+ str r3, [r12, #0x0]
+ mov r3, #NAND_LAUNCH_FCMD
+ str r3, [r12, #0xC]
+ do_wait_op_done
+
+// start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
+ mov r4, r1
+ mov r3, #0
+ do_addr_input //1st addr cycle
+
+ mov r3, #0
+ do_addr_input //2nd addr cycle
+
+ mov r3, r4, lsr #11
+ and r3, r3, #0xFF
+ mov r3, r3, lsl #16
+ do_addr_input //3rd addr cycle
+
+ mov r3, r4, lsr #19
+ and r3, r3, #0xFF
+ mov r3, r3, lsl #16
+ do_addr_input //4th addr cycle
+
+ mov r3, #0x30
+ str r3, [r12, #0x0]
+ mov r3, #NAND_LAUNCH_FCMD
+ str r3, [r12, #0xC]
+ do_wait_op_done
+
+// write RBA=0 to NFC_CONFIGURATION1
+ mov r3, #0
+ str r3, [r12, #0x4]
+
+// writel(mode & 0xFF, NAND_LAUNCH_REG)
+ mov r3, #0x8
+ str r3, [r12, #0xC]
+ do_wait_op_done
+
+Copy_Good_Blk:
+ @ copy page
+1:
+ ldmia r0!, {r3-r10}
+ stmia r14!, {r3-r10}
+ cmp r0, r2
+ blo 1b
+ cmp r14, r13
+ bge NAND_Copy_Main_done
+ add r1, r1, #TX37_NAND_PAGE_SIZE
+ ldr r0, NFC_BASE_W
+ b Nfc_Read_Page
+
+NAND_Copy_Main_done:
+
+Normal_Boot_Continue:
+#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
+ /* Copy image from flash to SDRAM first */
+ ldr r0, SDRAM_ADDR_MASK
+ and r0, r0, pc
+ ldr r1, MXC_REDBOOT_RAM_START
+ cmp r0, r1
+ beq HWInitialise_skip_SDRAM_copy
+
+ add r2, r0, #REDBOOT_IMAGE_SIZE
+1:
+ ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ ble 1b
+
+ bl jump_to_sdram
+#endif /* CYG_HAL_STARTUP_ROMRAM */
+
+HWInitialise_skip_SDRAM_copy:
+/*
+ * Note:
+ * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
+ */
+STACK_Setup:
+ // Set up a stack [for calling C code]
+ ldr r1, =__startup_stack
+ ldr r2, =RAM_BANK0_BASE
+ orr sp, r1, r2
+
+ // Create MMU tables
+ bl hal_mmu_init
+
+ // Enable MMU
+ ldr r2, =10f
+ mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
+ orr r1, r1, #7 // enable MMU bit
+ orr r1, r1, #0x800 // enable z bit
+ b 9f
+ .align 5
+9:
+ mcr MMU_CP, 0, r1, MMU_Control, c0
+ mov pc,r2 /* Change address spaces */
+ nop
+10:
+ .endm // _platform_setup1
+
+jump_to_sdram:
+ ldr r0, SDRAM_ADDR_MASK
+ ldr r1, MXC_REDBOOT_RAM_START
+ and r0, lr, r0
+ sub r0, r1, r0
+ add lr, lr, r0
+ mov pc, lr
+
+#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1
+#endif
+ /* Do nothing */
+ .macro init_spba
+ .endm /* init_spba */
+
+ /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
+ .macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, AIPS1_CTRL_BASE_ADDR_W
+ ldr r1, AIPS1_PARAM_W
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ ldr r0, AIPS2_CTRL_BASE_ADDR_W
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ .endm /* init_aips */
+
+ /* MAX (Multi-Layer AHB Crossbar Switch) setup */
+ .macro init_max
+ ldr r0, MAX_BASE_ADDR_W
+#if 0
+ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+ ldr r1, MAX_PARAM1
+ str r1, [r0, #0x000] /* for S0 */
+ str r1, [r0, #0x100] /* for S1 */
+ str r1, [r0, #0x200] /* for S2 */
+ str r1, [r0, #0x300] /* for S3 */
+ str r1, [r0, #0x400] /* for S4 */
+ /* SGPCR - always park on last master */
+ ldr r1, =0x10
+ str r1, [r0, #0x010] /* for S0 */
+ str r1, [r0, #0x110] /* for S1 */
+ str r1, [r0, #0x210] /* for S2 */
+ str r1, [r0, #0x310] /* for S3 */
+ str r1, [r0, #0x410] /* for S4 */
+ /* MGPCR - restore default values */
+ ldr r1, =0x0
+ str r1, [r0, #0x800] /* for M0 */
+ str r1, [r0, #0x900] /* for M1 */
+ str r1, [r0, #0xA00] /* for M2 */
+ str r1, [r0, #0xB00] /* for M3 */
+ str r1, [r0, #0xC00] /* for M4 */
+ str r1, [r0, #0xD00] /* for M5 */
+#endif
+ .endm /* init_max */
+
+ .macro init_clock
+ /*
+ * Clock setup
+ * After this step,
+
+ Module Freq (MHz)
+ ===========================
+ ARM core 532 ap_clk
+ AHB 133 ahb_clk
+ IP 66.5 ipg_clk
+ EMI 133 ddr_clk
+
+ * All other clocks can be figured out based on this.
+ */
+ /*
+ * Step 1: Switch to step clock
+ */
+ ldr r0, CCM_BASE_ADDR_W
+ mov r1, #0x00000104
+ str r1, [r0, #CLKCTL_CCSR]
+
+ /* Step 2: Setup PLL's */
+ /* Set PLL1 to be 532MHz */
+ ldr r0, PLL1_BASE_ADDR_W
+
+ ldr r2, PLL_1_2_VAL
+ str r2, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
+ mov r1, #0x2
+ str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+
+ mov r1, #0x50
+ str r1, [r0, #PLL_DP_OP]
+ mov r1, #23
+ str r1, [r0, #PLL_DP_MFD]
+ mov r1, #13
+ str r1, [r0, #PLL_DP_MFN]
+
+ mov r1, #0x50
+ str r1, [r0, #PLL_DP_HFS_OP]
+ mov r1, #23
+ str r1, [r0, #PLL_DP_HFS_MFD]
+ mov r1, #13
+ str r1, [r0, #PLL_DP_HFS_MFN]
+
+ /* Now restart PLL 1 */
+ orr r1, r2, #0x10
+ str r1, [r0, #PLL_DP_CTL]
+1:
+ ldr r1, [r0, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+ beq 1b
+
+ /*
+ * Step 2: Setup PLL2 to 665 MHz.
+ */
+ ldr r0, PLL2_BASE_ADDR_W
+
+ ldr r2, PLL_1_2_VAL
+ str r2, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
+ mov r1, #0x2
+ str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+
+ mov r1, #0x60
+ str r1, [r0, #PLL_DP_OP]
+ mov r1, #95
+ str r1, [r0, #PLL_DP_MFD]
+ mov r1, #89
+ str r1, [r0, #PLL_DP_MFN]
+
+ mov r1, #0x60
+ str r1, [r0, #PLL_DP_HFS_OP]
+ mov r1, #95
+ str r1, [r0, #PLL_DP_HFS_MFD]
+ mov r1, #89
+ str r1, [r0, #PLL_DP_HFS_MFN]
+
+ /* Now restart PLL 2 */
+ orr r1, r2, #0x10
+ str r1, [r0, #PLL_DP_CTL]
+1:
+ ldr r1, [r0, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+ beq 1b
+
+ /*
+ * Set PLL 3 to 216MHz
+ */
+ ldr r0, PLL3_BASE_ADDR_W
+
+ ldr r2, PLL_3_VAL
+ str r2, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
+ mov r1, #0x2
+ str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+
+ mov r1, #0x92
+ str r1, [r0, #PLL_DP_OP]
+ mov r1, #0x0
+ str r1, [r0, #PLL_DP_MFD]
+ mov r1, #0x0
+ str r1, [r0, #PLL_DP_MFN]
+
+ mov r1, #0x91
+ str r1, [r0, #PLL_DP_HFS_OP]
+ mov r1, #0x0
+ str r1, [r0, #PLL_DP_HFS_MFD]
+ mov r1, #0x0
+ str r1, [r0, #PLL_DP_HFS_MFN]
+
+ /* Now restart PLL 3 */
+ orr r1, r2, #0x10
+ str r1, [r0, #PLL_DP_CTL]
+1:
+ ldr r1, [r0, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+ beq 1b
+ /* End of PLL 3 setup */
+
+ /* Setup the ARM platform clock dividers */
+ ldr r0, PLATFORM_BASE_ADDR_W
+ ldr r1, PLATFORM_CLOCK_DIV_W
+ str r1, [r0, #0x18]
+
+ /*
+ * Step 3: switching to PLL 1 and restore default register values.
+ */
+ ldr r0, CCM_BASE_ADDR_W
+ mov r1, #0x00000100
+ str r1, [r0, #CLKCTL_CCSR]
+
+ mov r1, #0x000A0000
+ add r1, r1, #0x00000F0
+ str r1, [r0, #CLKCTL_CCOSR]
+ /* Use 133MHz for DDR clock */
+ mov r1, #0x1C00
+ str r1, [r0, #CLKCTL_CAMR]
+ /* Use PLL 2 for UART's, get 66.5MHz from it */
+ ldr r1, CCM_CSCMR1_VAL
+ str r1, [r0, #CLKCTL_CSCMR1]
+ ldr r1, CCM_CSCDR1_VAL
+ str r1, [r0, #CLKCTL_CSCDR1]
+
+ mov r1, #0x1C
+ str r1, [r0, #CLKCTL_CBCDR7]
+ mov r1, #1
+ str r1, [r0, #4]
+ .endm /* init_clock */
+
+ /* M4IF setup */
+ .macro init_m4if
+ /* Configure M4IF registers, VPU and IPU given higher priority (=0x4)
+ IPU accesses with ID=0x1 given highest priority (=0xA) */
+ ldr r1, M4IF_BASE_W
+ ldr r0, M4IF_0x00000a01
+ str r0, [r1, #M4IF_FIDBP]
+
+ ldr r0, M4IF_0x00000404
+ str r0, [r1, #M4IF_FBPM0]
+ .endm /* init_m4if */
+
+ .macro setup_sdram
+ ldr r0, ESDCTL_BASE_W
+ /* Set CSD0 */
+ mov r1, #0x80000000
+ str r1, [r0, #ESDCTL_ESDCTL0]
+1:
+ @ wait for SDRAM ready
+ ldr r2, [r0, #ESDCTL_ESDMISC]
+ and r2, r2, r1
+ beq 1b
+
+ /* Precharge command */
+ ldr r1, SDRAM_CMD_PRECHG
+ str r1, [r0, #ESDCTL_ESDSCR]
+
+ /* 2 refresh commands */
+ ldr r1, SDRAM_CMD_SLFRFSH
+ .rept 2
+ str r1, [r0, #ESDCTL_ESDSCR]
+ .endr
+
+ /* LMR with CAS Latency=3 and BurstLength=3->8words */
+ ldr r1, SDRAM_CMD_MODEREG
+ str r1, [r0, #ESDCTL_ESDSCR]
+
+ /* 13 ROW, 9 COL, 32Bit, SREF=4 */
+ ldr r1, SDRAM_ESDCTL0_VAL
+ str r1, [r0, #ESDCTL_ESDCTL0]
+
+ /* Timing parameters */
+ ldr r1, SDRAM_ESDCFG0_VAL
+ str r1, [r0, #ESDCTL_ESDCFG0]
+
+ /* MDDR enable, RALAT=1 */
+ ldr r1, SDRAM_ESDMISC_VAL
+ str r1, [r0, #ESDCTL_ESDMISC]
+
+ /* Normal mode */
+ mov r1, #0x00000000
+ str r1, [r0, #ESDCTL_ESDSCR]
+ .endm
+
+ .macro do_wait_op_done
+1:
+ ldr r3, [r11, #0x18]
+ ands r3, r3, #NFC_IPC_INT
+ beq 1b
+ mov r3, #0x0
+ str r3, [r11, #0x18]
+ .endm // do_wait_op_done
+
+ .macro do_addr_input
+ str r3, [r12, #0x0]
+ mov r3, #NAND_LAUNCH_FADD
+ str r3, [r12, #0xC]
+ do_wait_op_done
+ .endm // do_addr_input
+
+ /* To support 133MHz DDR */
+ .macro init_iomux
+ ldr r0, IOMUXC_BASE_ADDR_W
+
+ // DDR signal setup for D16-D31 and drive strength
+ mov r8, #0x1
+ add r1, r0, #8
+ add r2, r0, #0x4C
+1:
+ stmia r1!, {r8}
+ cmp r1, r2
+ bls 1b
+
+ str r8, [r0, #0x5C]
+ str r8, [r0, #0x60]
+
+ add r2, r0, #0x200
+ mov r8, #0x2C4
+ str r8, [r2, #0xBC]
+ str r8, [r2, #0xC0]
+
+ mov r8, #0x2
+ str r8, [r0, #0x4A8]
+ str r8, [r0, #0x4B0]
+ str r8, [r0, #0x4B4]
+ str r8, [r0, #0x4E0]
+ str r8, [r0, #0x4FC]
+ str r8, [r0, #0x504]
+ str r8, [r0, #0x48C]
+ str r8, [r0, #0x49C]
+
+ add r1, r0, #0x278
+ add r2, r0, #0x29C
+2:
+ stmia r1!, {r8}
+ cmp r1, r2
+ bls 2b
+ .endm /* init_iomux */
+
+#define PLATFORM_VECTORS _platform_vectors
+ .macro _platform_vectors
+ .globl _KARO_MAGIC
+_KARO_MAGIC:
+ .ascii "KARO_CE6"
+ .globl _KARO_STRUCT_SIZE
+_KARO_STRUCT_SIZE:
+ .word 0 // reserve space structure length
+
+ .globl _KARO_CECFG_START
+_KARO_CECFG_START:
+ .rept 1024/4
+ .word 0 // reserve space for CE configuration
+ .endr
+
+ .globl _KARO_CECFG_END
+_KARO_CECFG_END:
+ .endm
+
+KaRo_MSG: .asciz "KARO TX37 " __DATE__ " " __TIME__ "\n"
+ARM_PPMRR: .word 0x80000016
+L2CACHE_PARAM: .word 0x0003001B
+WDOG1_BASE_W: .word WDOG1_BASE_ADDR
+IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
+AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
+AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
+AIPS1_PARAM_W: .word 0x77777777
+MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
+MAX_PARAM1: .word 0x00302154
+ESDCTL_BASE_W: .word ESDCTL_BASE
+M4IF_BASE_W: .word M4IF_BASE
+M4IF_0x00000a01: .word 0x00000a01
+M4IF_0x00000404: .word 0x00000404
+NFC_BASE_W: .word NFC_BASE
+NFC_IP_BASE_W: .word NFC_IP_BASE
+SDRAM_CMD_PRECHG: .word 0x04008008
+SDRAM_CMD_SLFRFSH: .word 0x00008010
+SDRAM_CMD_MODEREG: .word 0x00338018
+#if SDRAM_SIZE > SZ_64M
+SDRAM_ESDCTL0_VAL: .word 0xB2220000
+#else
+SDRAM_ESDCTL0_VAL: .word 0xB2120000
+#endif
+SDRAM_ESDCFG0_VAL: .word 0x70395729
+SDRAM_ESDMISC_VAL: .word 0x000A0084
+IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
+GPIO2_BASE_ADDR_W: .word GPIO2_BASE_ADDR
+MXC_REDBOOT_RAM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
+SDRAM_ADDR_MASK: .word 0xFFFFF000
+CONST_0x0FFF: .word 0x0FFF
+CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
+PLATFORM_BASE_ADDR_W: .word PLATFORM_BASE_ADDR
+PLATFORM_CLOCK_DIV_W: .word 0x00077713
+CCM_CSCDR1_VAL: .word 0x01450B21
+CCM_CSCMR1_VAL: .word 0xA5A6A020
+PLL1_BASE_ADDR_W: .word PLL1_BASE_ADDR
+PLL2_BASE_ADDR_W: .word PLL2_BASE_ADDR
+PLL3_BASE_ADDR_W: .word PLL3_BASE_ADDR
+PLL_1_2_VAL: .word 0x1222
+PLL_3_VAL: .word 0x222
+
+/*--------------------------------------------------------------------------*/
+/* end of hal_platform_setup.h */
+#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
--- /dev/null
+#ifndef CYGONCE_KARO_TX37_H
+#define CYGONCE_KARO_TX37_H
+
+//=============================================================================
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+#define SZ_1K 0x00000400
+#define SZ_2K 0x00000800
+#define SZ_4K 0x00001000
+#define SZ_8K 0x00002000
+#define SZ_16K 0x00004000
+#define SZ_32K 0x00008000
+#define SZ_64K 0x00010000
+#define SZ_128K 0x00020000
+#define SZ_256K 0x00040000
+#define SZ_512K 0x00080000
+#define SZ_1M 0x00100000
+#define SZ_2M 0x00200000
+#define SZ_4M 0x00400000
+#define SZ_8M 0x00800000
+#define SZ_16M 0x01000000
+#define SZ_32M 0x02000000
+#define SZ_64M 0x04000000
+#define SZ_128M 0x08000000
+#define SZ_256M 0x10000000
+#define SZ_512M 0x20000000
+#define SZ_1G 0x40000000
+
+
+#define RAM_BANK0_BASE SDRAM_BASE_ADDR
+#define TX37_SDRAM_SIZE SDRAM_SIZE
+
+#define GPIO_DR 0x00
+#define GPIO_GDIR 0x04
+#define GPIO_PSR 0x08
+
+#define STK5_LED_MASK (1 << 19)
+#define STK5_LED_REG_ADDR (GPIO2_BASE_ADDR + GPIO_DR)
+
+#define LED_MAX_NUM 1
+
+#define LED_IS_ON(n) ({ \
+ CYG_WORD32 __val; \
+ HAL_READ_UINT32(STK5_LED_REG_ADDR, __val); \
+ __val & STK5_LED_MASK; \
+})
+
+#define TURN_LED_ON(n) \
+ CYG_MACRO_START \
+ CYG_WORD32 __val; \
+ HAL_READ_UINT32(STK5_LED_REG_ADDR, __val); \
+ __val |= STK5_LED_MASK; \
+ HAL_WRITE_UINT32(STK5_LED_REG_ADDR, __val); \
+ CYG_MACRO_END
+
+#define TURN_LED_OFF(n) \
+ CYG_MACRO_START \
+ CYG_WORD32 __val; \
+ HAL_READ_UINT32(STK5_LED_REG_ADDR, __val); \
+ __val &= ~STK5_LED_MASK; \
+ HAL_WRITE_UINT32(STK5_LED_REG_ADDR, __val); \
+ CYG_MACRO_END
+
+#define BOARD_DEBUG_LED(n) \
+ CYG_MACRO_START \
+ if (n >= 0 && n < LED_MAX_NUM) { \
+ if (LED_IS_ON(n)) \
+ TURN_LED_OFF(n); \
+ else \
+ TURN_LED_ON(n); \
+ } \
+ CYG_MACRO_END
+
+#define BLINK_LED(l, n) \
+ CYG_MACRO_START \
+ int _i; \
+ for (_i = 0; _i < (n); _i++) { \
+ BOARD_DEBUG_LED(l); \
+ HAL_DELAY_US(200000); \
+ BOARD_DEBUG_LED(l); \
+ HAL_DELAY_US(300000); \
+ } \
+ HAL_DELAY_US(1000000); \
+ CYG_MACRO_END
+
+#if !defined(__ASSEMBLER__)
+#ifdef CYGOPT_HAL_ARM_TX37_DEBUG // REMOVE ME
+extern void plf_dumpmem(unsigned long addr, int len);
+#else
+static inline void plf_dumpmem(unsigned long addr, int len)
+{
+}
+#endif // CYGOPT_HAL_ARM_TX37_DEBUG
+
+enum {
+ BOARD_TYPE_TX37KARO,
+};
+
+#define gpio_tst_bit(grp, gpio) _gpio_tst_bit(grp, gpio, __FUNCTION__, __LINE__)
+static inline int _gpio_tst_bit(int grp, int gpio, const char *func, int line)
+{
+ if (grp < 1 || grp > 3) {
+ return 0;
+ }
+ if (gpio < 0 || gpio > 31) {
+ return 0;
+ }
+ unsigned long val = readl(GPIO1_BASE_ADDR + ((grp - 1) << 14) + GPIO_PSR);
+ return !!(val & (1 << gpio));
+}
+
+#include <cyg/infra/diag.h>
+static inline void gpio_set_bit(int grp, int gpio)
+{
+ if (grp < 1 || grp > 3) {
+ return;
+ }
+ if (gpio < 0 || gpio > 31) {
+ return;
+ }
+ unsigned long val = readl(GPIO1_BASE_ADDR + ((grp - 1) << 14) + GPIO_DR);
+ writel(val | (1 << gpio), GPIO1_BASE_ADDR + ((grp - 1) << 14) + GPIO_DR);
+#if 0
+ diag_printf("%s: Changing GPIO_DR[%d]@%08lx from %08lx to %08lx\n", __FUNCTION__,
+ grp, GPIO1_BASE_ADDR + ((grp - 1) << 14), val, val | (1 << gpio));
+#endif
+}
+
+static inline void gpio_clr_bit(int grp, int gpio)
+{
+ if (grp < 1 || grp > 3) {
+ return;
+ }
+ if (gpio < 0 || gpio > 31) {
+ return;
+ }
+ unsigned long val = readl(GPIO1_BASE_ADDR + ((grp - 1) << 14) + GPIO_DR);
+ writel(val & ~(1 << gpio), GPIO1_BASE_ADDR + ((grp - 1) << 14) + GPIO_DR);
+#if 0
+ diag_printf("%s: Changing GPIO_DR[%d]@%08lx from %08lx to %08lx\n", __FUNCTION__,
+ grp, GPIO1_BASE_ADDR + ((grp - 1) << 14), val, val & ~(1 << gpio));
+#endif
+}
+#endif /* __ASSEMBLER__ */
+
+#endif /* CYGONCE_KARO_TX37_H */
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_VARIANT_H
+#include CYGBLD_HAL_PLATFORM_H
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+
+#define SDRAM_BASE_ADDR CSD0_BASE_ADDR
+#define SDRAM_SIZE CYGNUM_HAL_ARM_TX37_SDRAM_SIZE
+
+#define REDBOOT_IMAGE_SIZE 0x00040000
+
+#ifndef REDBOOT_BOTTOM
+#define REDBOOT_OFFSET REDBOOT_IMAGE_SIZE
+#define CYGMEM_REGION_ram SDRAM_BASE_ADDR
+#define CYGMEM_REGION_rom (CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE)
+#else
+#define REDBOOT_OFFSET 0x00100000
+#define CYGMEM_REGION_ram (SDRAM_BASE_ADDR + REDBOOT_OFFSET)
+#define CYGMEM_REGION_rom SDRAM_BASE_ADDR
+#endif
+
+#define CYGMEM_REGION_ram_SIZE (SDRAM_SIZE - REDBOOT_OFFSET)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_rom_SIZE REDBOOT_OFFSET
+#define CYGMEM_REGION_rom_ATTR CYGMEM_REGION_ATTR_R
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME(__heap1)[];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME(__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_rom - (size_t)CYG_LABEL_NAME(__heap1))
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+#define __ASSEMBLER__
+#include <pkgconf/mlt_arm_tx37_romram.h>
+
+MEMORY
+{
+ ram : ORIGIN = CYGMEM_REGION_ram, LENGTH = CYGMEM_REGION_ram_SIZE
+ rom : ORIGIN = CYGMEM_REGION_rom, LENGTH = CYGMEM_REGION_rom_SIZE
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_rom_vectors (rom, CYGMEM_REGION_rom, LMA_EQ_VMA)
+ SECTION_RELOCS(rom, ALIGN (0x1), LMA_EQ_VMA)
+ SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixed_vectors (ram, CYGMEM_REGION_ram + 0x20, LMA_EQ_VMA)
+ SECTION_data (ram, CYGMEM_REGION_ram + 0x8000, FOLLOWING (.gcc_except_table))
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
--- /dev/null
+#ifndef CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+#define CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+
+//=============================================================================
+//
+// plf_io.h
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/hal/karo_tx37.h>
+#include <cyg/hal/hal_soc.h>
+
+#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \
+ CYG_MACRO_START \
+ { \
+ extern unsigned int system_rev; \
+ /* Next ATAG_MEM. */ \
+ _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_MEM; \
+ /* Round up so there's only one bit set in the memory size. \
+ * Don't double it if it's already a power of two, though. \
+ */ \
+ _p_->u.mem.size = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE); \
+ if (_p_->u.mem.size < CYGMEM_REGION_ram_SIZE) \
+ _p_->u.mem.size <<= 1; \
+ _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram); \
+ _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size); \
+ _p_->hdr.size = ((sizeof(struct tag_revision)) + sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_REVISION; \
+ _p_->u.revision.rev = system_rev; \
+ } \
+ CYG_MACRO_END
+
+#endif // CYGONCE_HAL_ARM_BOARD_PLF_IO_H
--- /dev/null
+#ifndef CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+#define CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+//=============================================================================
+//
+// plf_mmap.h
+//
+// Platform specific memory map support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_misc.h>
+
+// Get the pagesize for a particular virtual address:
+
+// This does not depend on the vaddr.
+#define HAL_MM_PAGESIZE(vaddr, pagesize) CYG_MACRO_START \
+ (pagesize) = SZ_1M; \
+CYG_MACRO_END
+
+// Get the physical address from a virtual address:
+
+#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START \
+ cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
+ if ( _v_ < 128 * SZ_1M ) /* SDRAM */ \
+ _v_ += SDRAM_BASE_ADDR; \
+ else /* Rest of it */ \
+ /* no change */ ; \
+ (paddr) = _v_; \
+CYG_MACRO_END
+
+//---------------------------------------------------------------------------
+#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
--- /dev/null
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "RedBoot configuration for Ka-Ro TX37 processor module" ;
+
+ # These fields should not be modified.
+ hardware tx37karo ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM current ;
+ package -hardware CYGPKG_HAL_ARM_MX37 current ;
+ package -hardware CYGPKG_HAL_ARM_TX37KARO current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_TX37 current ;
+ package -hardware CYGPKG_DEVS_ETH_FEC current ;
+ package -hardware CYGPKG_COMPRESS_ZLIB current ;
+ package -hardware CYGPKG_IO_FLASH current ;
+ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+ package -template CYGPKG_MEMALLOC current ;
+ package -template CYGPKG_DEVS_ETH_PHY current ;
+ package -template CYGPKG_LIBC_I18N current ;
+ package -template CYGPKG_LIBC_STDLIB current ;
+ package -template CYGPKG_ERROR current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_ETH_PHY_LAN8700 {
+ inferred_value 1
+};
+
+cdl_option CYGIMP_LIBC_RAND_SIMPLE1 {
+ user_value 0
+};
+
+cdl_option CYGIMP_LIBC_RAND_KNUTH1 {
+ user_value 1
+};
+
+cdl_option CYGFUN_LIBC_STDLIB_CONV_LONGLONG {
+ user_value 0
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 0
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ inferred_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_GDB {
+ inferred_value 0
+};
+
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+ inferred_value 1 "Ka-Ro [exec date -I]"
+};
+
+cdl_option CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+ inferred_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_WINCE_SUPPORT {
+ user_value 1
+};
+
+cdl_option CYGSEM_REDBOOT_NET_HTTP_DOWNLOAD {
+ user_value 0
+};
+
+cdl_option CYGPKG_REDBOOT_ANY_CONSOLE {
+ inferred_value 0
+};
+
+cdl_option CYGSEM_REDBOOT_PLF_ESA_VALIDATE {
+ inferred_value 1
+};
+
+cdl_option CYGPKG_REDBOOT_MAX_CMD_LINE {
+ inferred_value 1024
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ inferred_value 0x00040000
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_SCRIPT_SIZE {
+ inferred_value 2048
+};
+
+cdl_component CYGPKG_REDBOOT_DISK {
+ user_value 0
+};
+
+cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_TIMEOUT_RESOLUTION {
+ inferred_value 10
+};
+
+cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_DEFAULT_TIMEOUT {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS {
+ inferred_value 0x40108000
+};
+
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+ inferred_value 0x40108000
+};
+
+cdl_option CYGBLD_ISO_CTYPE_HEADER {
+ inferred_value 1 <cyg/libc/i18n/ctype.inl>
+};
+
+cdl_option CYGBLD_ISO_ERRNO_CODES_HEADER {
+ inferred_value 1 <cyg/error/codes.h>
+};
+
+cdl_option CYGBLD_ISO_ERRNO_HEADER {
+ inferred_value 1 <cyg/error/errno.h>
+};
+
+cdl_option CYGBLD_ISO_STDLIB_STRCONV_HEADER {
+ inferred_value 1 <cyg/libc/stdlib/atox.inl>
+};
+
+cdl_option CYGBLD_ISO_STDLIB_ABS_HEADER {
+ inferred_value 1 <cyg/libc/stdlib/abs.inl>
+};
+
+cdl_option CYGBLD_ISO_STDLIB_DIV_HEADER {
+ inferred_value 1 <cyg/libc/stdlib/div.inl>
+};
+
+cdl_option CYGBLD_ISO_STRERROR_HEADER {
+ inferred_value 1 <cyg/error/strerror.h>
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGSEM_IO_FLASH_READ_INDIRECT {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_IO_FLASH_VERIFY_PROGRAM {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+ inferred_value 1
+};
+
+cdl_component CYGHWR_FLASH_NAND_BBT_HEADER {
+ inferred_value 1 <cyg/io/tx37_nand_bbt.h>
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_MULTI {
+ inferred_value 0
+};
+
+cdl_option CYGSEM_ERROR_PER_THREAD_ERRNO {
+ inferred_value 0
+};
+
--- /dev/null
+//==========================================================================
+//
+// redboot_cmds.c
+//
+// Board [platform] specific RedBoot commands
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+#include <redboot.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/plf_mmap.h>
+#include <cyg/hal/karo_tx37.h> // Platform specific hardware definitions
+
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <flash_config.h>
+
+#if (REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE)
+#error REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE
+#endif
+
+#endif //CYGSEM_REDBOOT_FLASH_CONFIG
+
+#ifdef CYGPKG_IO_FLASH
+#include <cyg/io/flash.h>
+#endif
+
+char HAL_PLATFORM_EXTRA[20] = "PASS x.x [x32 DDR]";
+static void runImg(int argc, char *argv[]);
+static void do_mem(int argc, char *argv[]);
+
+RedBoot_cmd("mem",
+ "Set a memory location",
+ "[-h|-b] [-n] [-a <address>] <data>",
+ do_mem
+ );
+
+RedBoot_cmd("run",
+ "Run an image at a location with MMU off",
+ "[<virtual addr>]",
+ runImg
+ );
+
+static void do_mem(int argc, char *argv[])
+{
+ struct option_info opts[4];
+ bool mem_half_word, mem_byte;
+ bool no_verify;
+ bool addr_set;
+ unsigned long address;
+ unsigned int value;
+ int ret;
+ init_opts(&opts[0], 'b', false, OPTION_ARG_TYPE_FLG,
+ &mem_byte, NULL, "write a byte");
+ init_opts(&opts[1], 'h', false, OPTION_ARG_TYPE_FLG,
+ &mem_half_word, NULL, "write a half-word");
+ init_opts(&opts[2], 'a', true, OPTION_ARG_TYPE_NUM,
+ &address, &addr_set, "address to write to");
+ init_opts(&opts[3], 'n', false, OPTION_ARG_TYPE_FLG,
+ &no_verify, NULL, "noverify");
+
+ ret = scan_opts(argc, argv, 1, opts, sizeof(opts) / sizeof(opts[0]),
+ &value, OPTION_ARG_TYPE_NUM, "value to be written");
+ if (ret == 0) {
+ return;
+ }
+ if (!addr_set) {
+ diag_printf("** Error: '-a <address>' must be specified\n");
+ return;
+ }
+ if (ret == argc + 1) {
+ diag_printf("** Error: non-option argument '<value>' must be specified\n");
+ return;
+ }
+ if (mem_byte && mem_half_word) {
+ diag_printf("** Error: Should not specify both byte and half-word access\n");
+ } else if (mem_byte) {
+ value &= 0xff;
+ *(volatile cyg_uint8*)address = (cyg_uint8)value;
+ if (no_verify) {
+ diag_printf(" Set 0x%08lX to 0x%02X\n", address, value);
+ } else {
+ diag_printf(" Set 0x%08lX to 0x%02X (result 0x%02X)\n",
+ address, value, (int)*(cyg_uint8*)address );
+ }
+ } else if (mem_half_word) {
+ if (address & 1) {
+ diag_printf("** Error: address for half-word access must be half-word aligned\n");
+ } else {
+ value &= 0xffff;
+ *(volatile cyg_uint16*)address = (cyg_uint16)value;
+ if (no_verify) {
+ diag_printf(" Set 0x%08lX to 0x%04X\n", address, value);
+ } else {
+ diag_printf(" Set 0x%08lX to 0x%04X (result 0x%04X)\n",
+ address, value, (int)*(cyg_uint16*)address);
+ }
+ }
+ } else {
+ if (address & 3) {
+ diag_printf("** Error: address for word access must be word aligned\n");
+ } else {
+ *(volatile cyg_uint32*)address = (cyg_uint32)value;
+ if (no_verify) {
+ diag_printf(" Set 0x%08lX to 0x%08X\n", address, value);
+ } else {
+ diag_printf(" Set 0x%08lX to 0x%08X (result 0x%08X)\n",
+ address, value, (int)*(cyg_uint32*)address);
+ }
+ }
+ }
+}
+
+void launchRunImg(unsigned long addr)
+{
+ asm volatile ("mov r12, r0;");
+ HAL_CLEAN_INVALIDATE_L2();
+ HAL_DISABLE_L2();
+ HAL_MMU_OFF();
+ asm volatile (
+ "mov r0, #0;"
+ "mov r1, r12;"
+ "mov r11, #0;"
+ "mov r12, #0;"
+ "mrs r10, cpsr;"
+ "bic r10, r10, #0xF0000000;"
+ "msr cpsr_f, r10;"
+ "mov pc, r1"
+ );
+}
+
+static void runImg(int argc,char *argv[])
+{
+ unsigned int virt_addr, phys_addr;
+
+ // Default physical entry point for Symbian
+ if (entry_address == 0xFFFFFFFF)
+ virt_addr = 0x800000;
+ else
+ virt_addr = entry_address;
+
+ if (!scan_opts(argc, argv, 1, 0, 0, &virt_addr,
+ OPTION_ARG_TYPE_NUM, "virtual address"))
+ return;
+
+ if (entry_address != 0xFFFFFFFF)
+ diag_printf("load entry_address=0x%lx\n", entry_address);
+ HAL_VIRT_TO_PHYS_ADDRESS(virt_addr, phys_addr);
+
+ diag_printf("virt_addr=0x%x\n",virt_addr);
+ diag_printf("phys_addr=0x%x\n",phys_addr);
+
+ launchRunImg(phys_addr);
+}
+
+#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYG_HAL_STARTUP_ROMRAM)
+
+RedBoot_cmd("romupdate",
+ "Update Redboot with currently running image",
+ "",
+ romupdate
+ );
+
+#ifdef CYGPKG_IO_FLASH
+void romupdate(int argc, char *argv[])
+{
+ void *err_addr, *base_addr;
+ int stat;
+
+ base_addr = (void*)(MXC_NAND_BASE_DUMMY + CYGBLD_REDBOOT_FLASH_BOOT_OFFSET);
+ diag_printf("Updating RedBoot in NAND flash\n");
+
+ // Erase area to be programmed
+ if ((stat = flash_erase(base_addr, CYGBLD_REDBOOT_MIN_IMAGE_SIZE, &err_addr)) != 0) {
+ diag_printf("Can't erase region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ return;
+ }
+ // Now program it
+ if ((stat = flash_program(base_addr, ram_end,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE, &err_addr)) != 0) {
+ diag_printf("Can't program region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ }
+}
+#endif //CYGPKG_IO_FLASH
+#endif /* CYG_HAL_STARTUP_ROMRAM */
--- /dev/null
+/*=============================================================================
+//
+// board_diag.c
+//
+// HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_arch.h> // basic machine info
+#include <cyg/hal/hal_intr.h> // interrupt macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_if.h> // Calling-if API
+#include <cyg/hal/drv_api.h> // driver API
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/karo_tx37.h> // Platform specifics
+
+extern void cyg_hal_plf_serial_init(void);
+
+void cyg_hal_plf_comms_init(void)
+{
+ static int initialized = 0;
+
+ if (initialized) {
+ return;
+ }
+ initialized = 1;
+ cyg_hal_plf_serial_init();
+}
+
+//-----------------------------------------------------------------------------
+// Based on 3.6864 MHz xtal
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x18
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x0C
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x06
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x04
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
+#define CYG_DEV_SERIAL_BAUD_MSB 0x00
+#define CYG_DEV_SERIAL_BAUD_LSB 0x02
+#endif
+
+#ifndef CYG_DEV_SERIAL_BAUD_MSB
+#error Missing/incorrect serial baud rate defined - CDL error?
+#endif
+
+//-----------------------------------------------------------------------------
+// Define the serial registers. The board is equipped with a 16552
+// serial chip.
+
+#if defined (EXT_UART_x16)
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT16
+#define HAL_READ_UINT_UART HAL_READ_UINT16
+typedef cyg_uint16 uart_width;
+#elif defined (EXT_UART_x32)
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT32
+#define HAL_READ_UINT_UART HAL_READ_UINT32
+typedef cyg_uint32 uart_width;
+#else //_x8
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT8
+#define HAL_READ_UINT_UART HAL_READ_UINT8
+typedef cyg_uint8 uart_width;
+#endif
+
+#define CYG_DEV_SERIAL_RHR 0x00 // receiver buffer register, read, dlab = 0
+#define CYG_DEV_SERIAL_THR 0x00 // transmitter holding register, write, dlab = 0
+#define CYG_DEV_SERIAL_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IER 0x01 // interrupt enable register, read/write, dlab = 0
+#define CYG_DEV_SERIAL_DLM 0x01 // divisor latch (MS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IIR 0x02 // interrupt identification register, read, dlab = 0
+#define CYG_DEV_SERIAL_FCR 0x02 // fifo control register, write, dlab = 0
+#define CYG_DEV_SERIAL_AFR 0x02 // alternate function register, read/write, dlab = 1
+#define CYG_DEV_SERIAL_LCR 0x03 // line control register, read/write
+#define CYG_DEV_SERIAL_MCR 0x04
+#define CYG_DEV_SERIAL_MCR_A 0x04
+#define CYG_DEV_SERIAL_MCR_B 0x04
+#define CYG_DEV_SERIAL_LSR 0x05 // line status register, read
+#define CYG_DEV_SERIAL_MSR 0x06 // modem status register, read
+#define CYG_DEV_SERIAL_SCR 0x07 // scratch pad register
+
+// The interrupt enable register bits.
+#define SIO_IER_ERDAI 0x01 // enable received data available irq
+#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
+#define SIO_IER_ELSI 0x04 // enable receiver line status irq
+#define SIO_IER_EMSI 0x08 // enable modem status interrupt
+
+// The interrupt identification register bits.
+#define SIO_IIR_IP 0x01 // 0 if interrupt pending
+#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
+#define ISR_Tx 0x02
+#define ISR_Rx 0x04
+
+// The line status register bits.
+#define SIO_LSR_DR 0x01 // data ready
+#define SIO_LSR_OE 0x02 // overrun error
+#define SIO_LSR_PE 0x04 // parity error
+#define SIO_LSR_FE 0x08 // framing error
+#define SIO_LSR_BI 0x10 // break interrupt
+#define SIO_LSR_THRE 0x20 // transmitter holding register empty
+#define SIO_LSR_TEMT 0x40 // transmitter register empty
+#define SIO_LSR_ERR 0x80 // any error condition
+
+// The modem status register bits.
+#define SIO_MSR_DCTS 0x01 // delta clear to send
+#define SIO_MSR_DDSR 0x02 // delta data set ready
+#define SIO_MSR_TERI 0x04 // trailing edge ring indicator
+#define SIO_MSR_DDCD 0x08 // delta data carrier detect
+#define SIO_MSR_CTS 0x10 // clear to send
+#define SIO_MSR_DSR 0x20 // data set ready
+#define SIO_MSR_RI 0x40 // ring indicator
+#define SIO_MSR_DCD 0x80 // data carrier detect
+
+// The line control register bits.
+#define SIO_LCR_WLS0 0x01 // word length select bit 0
+#define SIO_LCR_WLS1 0x02 // word length select bit 1
+#define SIO_LCR_STB 0x04 // number of stop bits
+#define SIO_LCR_PEN 0x08 // parity enable
+#define SIO_LCR_EPS 0x10 // even parity select
+#define SIO_LCR_SP 0x20 // stick parity
+#define SIO_LCR_SB 0x40 // set break
+#define SIO_LCR_DLAB 0x80 // divisor latch access bit
+
+// The FIFO control register
+#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
+#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
+#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
+
+//-----------------------------------------------------------------------------
+
+
+//#define x_debug_uart_log_buf
+#ifdef x_debug_uart_log_buf
+#define x_DIAG_BUFSIZE 2048
+static char __x_log_buf[x_DIAG_BUFSIZE];
+static int x_diag_bp = 0;
+#endif
+
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
+
+
+#ifdef __BASE
+
+#ifdef CYGSEM_HAL_ROM_MONITOR
+#define CYG_HAL_STARTUP_ROM
+#define CYG_HAL_STARTUP_ROMRAM
+#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#endif
+
+#if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define HAL_DIAG_USES_HARDWARE
+#elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
+#define HAL_DIAG_USES_HARDWARE
+#elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+#define HAL_DIAG_USES_HARDWARE
+#endif
+
+static channel_data_t channel = {
+ (uart_width*) _BASE, 0, 0
+};
+
+#ifdef HAL_DIAG_USES_HARDWARE
+
+void hal_diag_init(void)
+{
+ static int init = 0;
+ char *msg = "\n\rARM eCos\n\r";
+ uart_width lcr;
+
+ if (init++) return;
+
+ init_duart_channel(&channel);
+
+ while (*msg) hal_diag_write_char(*msg++);
+}
+
+#ifdef DEBUG_DIAG
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define DIAG_BUFSIZE 32
+#else
+#define DIAG_BUFSIZE 2048
+#endif
+static char diag_buffer[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+
+void hal_diag_write_char(char c)
+{
+ uart_width lsr;
+
+ hal_diag_init();
+
+ cyg_hal_plf_duart_putc(&channel, c)
+
+#ifdef DEBUG_DIAG
+ diag_buffer[diag_bp++] = c;
+ if (diag_bp == DIAG_BUFSIZE) {
+ while (1) ;
+ diag_bp = 0;
+ }
+#endif
+}
+
+void hal_diag_read_char(char *c)
+{
+ *c = cyg_hal_plf_duart_getc(&channel);
+}
+
+#else // HAL_DIAG relies on GDB
+
+// Initialize diag port - assume GDB channel is already set up
+void hal_diag_init(void)
+{
+ if (0) init_duart_channel(&channel); // avoid warning
+}
+
+// Actually send character down the wire
+static void hal_diag_write_char_serial(char c)
+{
+ cyg_hal_plf_duart_putc(&channel, c);
+}
+
+static bool hal_diag_read_serial(char *c)
+{
+ long timeout = 1000000000; // A long time...
+
+ while (!cyg_hal_plf_duart_getc_nonblock(&channel, c))
+ if (0 == --timeout) return false;
+
+ return true;
+}
+
+void hal_diag_read_char(char *c)
+{
+ while (!hal_diag_read_serial(c)) ;
+}
+
+void hal_diag_write_char(char c)
+{
+ static char line[100];
+ static int pos = 0;
+
+ // No need to send CRs
+ if (c == '\r') return;
+
+ line[pos++] = c;
+
+ if (c == '\n' || pos == sizeof(line)) {
+ CYG_INTERRUPT_STATE old;
+
+ // Disable interrupts. This prevents GDB trying to interrupt us
+ // while we are in the middle of sending a packet. The serial
+ // receive interrupt will be seen when we re-enable interrupts
+ // later.
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+#else
+ HAL_DISABLE_INTERRUPTS(old);
+#endif
+
+ while (1) {
+ static char hex[] = "0123456789ABCDEF";
+ cyg_uint8 csum = 0;
+ int i;
+ char c1;
+
+ hal_diag_write_char_serial('$');
+ hal_diag_write_char_serial('O');
+ csum += 'O';
+ for (i = 0; i < pos; i++) {
+ char ch = line[i];
+ char h = hex[(ch>>4)&0xF];
+ char l = hex[ch&0xF];
+ hal_diag_write_char_serial(h);
+ hal_diag_write_char_serial(l);
+ csum += h;
+ csum += l;
+ }
+ hal_diag_write_char_serial('#');
+ hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
+ hal_diag_write_char_serial(hex[csum&0xF]);
+
+ // Wait for the ACK character '+' from GDB here and handle
+ // receiving a ^C instead. This is the reason for this clause
+ // being a loop.
+ if (!hal_diag_read_serial(&c1))
+ continue; // No response - try sending packet again
+
+ if ( c1 == '+' )
+ break; // a good acknowledge
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
+ if ( c1 == 3 ) {
+ // Ctrl-C: breakpoint.
+ cyg_hal_gdb_interrupt (__builtin_return_address(0));
+ break;
+ }
+#endif
+ // otherwise, loop round again
+ }
+
+ pos = 0;
+
+ // And re-enable interrupts
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+#else
+ HAL_RESTORE_INTERRUPTS(old);
+#endif
+
+ }
+}
+#endif
+
+#endif // __BASE
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
--- /dev/null
+//==========================================================================
+//
+// tx37_misc.c
+//
+// HAL misc board support code for the TX37 board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#include <string.h>
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include <redboot.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h> // Interrupt names
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/karo_tx37.h> // Platform specifics
+#include <cyg/infra/diag.h> // diag_printf
+
+// All the MM table layout is here:
+#include <cyg/hal/hal_mm.h>
+
+void hal_mmu_init(void)
+{
+ unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
+ unsigned long i;
+
+ /*
+ * Set the TTB register
+ */
+ asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(ttb_base) /*:*/);
+
+ /*
+ * Set the Domain Access Control Register
+ */
+ i = ARM_ACCESS_DACR_DEFAULT;
+ asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(i) /*:*/);
+
+ /*
+ * First clear all TT entries - ie Set them to Faulting
+ */
+ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+
+ /* Physical Virtual Size Attributes Function */
+ /* Base Base MB cached? buffered? access permissions */
+ /* xxx00000 xxx00000 */
+ X_ARM_MMU_SECTION(0x000, 0x200, 0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */
+ X_ARM_MMU_SECTION(0x100, 0x100, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IRAM */
+ X_ARM_MMU_SECTION(0x400, 0x000, TX37_SDRAM_SIZE >> 20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0x400, 0x400, TX37_SDRAM_SIZE >> 20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0x400, 0x480, TX37_SDRAM_SIZE >> 20, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0x7ff, 0x7ff, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* NAND Flash buffer */
+ X_ARM_MMU_SECTION(0x800, 0x800, 0x020, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IPUv3D */
+ X_ARM_MMU_SECTION(0xB00, 0xB00, 0x400, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* periperals */
+}
+
+//
+// Platform specific initialization
+//
+
+static inline void set_reg(unsigned long addr, CYG_WORD32 set, CYG_WORD32 clr)
+{
+ CYG_WORD32 val;
+ HAL_READ_UINT32(addr, val);
+ val = (val & ~clr) | set;
+ HAL_WRITE_UINT32(addr, val);
+}
+
+#define GPIO_BASE(grp) (GPIO1_BASE_ADDR + (((grp) - 1) << 14))
+static inline void setup_gpio(int grp, int bit)
+{
+ set_reg(GPIO_BASE(grp) + GPIO_DR, 0, 1 << bit);
+ set_reg(GPIO_BASE(grp) + GPIO_GDIR, 1 << bit, 0);
+}
+
+/* GPIOs to set up for TX27/Starterkit-5:
+ Function FCT GPIO Pad IOMUXC SW_PAD SW_PAD mode
+ OFFSET CTRL MUX
+FEC_MDC 4 GPIO3_1 CSPI1_MISO 0x138 0x398
+FEC_MDIO 4 GPIO2_23 AUD5_WB_FS 0x130 0x390 0x5a8 0
+FEC_RX_CLK 1 GPIO2_1 EIM_CS1 0x058 0x2b8 0x5b0 0
+FEC_RX_DV 3 GPIO1_10 EIM_BCLK 0x064 0x2c4 0x5b4 0
+FEC_RXD0 4 GPIO2_30 UART1_RI 0x174 0x3d4 0x5ac 1
+FEC_RXD1 4 GPIO3_3 CSPI1_SS1 0x140 0x3a0
+FEC_RXD2 4 GPIO3_5 CSPI2_MOSI 0x148 0x3a8
+FEC_RXD3 4 GPIO3_6 CSPI2_MISO 0x14c 0x3ac
+FEC_RX_ER 4 GPIO3_0 CSPI1_MOSI 0x134 0x394 0x5b8 1
+FEC_TX_CLK 3 GPIO1_9 EIM_RW 0x068 0x2c8 0x5bc 0
+FEC_TX_EN 3 GPIO1_13 EIM_OE 0x050 0x2b0
+FEC_TXD0 4 GPIO2_31 UART1_DCD 0x178 0x3d8
+FEC_TXD1 4 GPIO3_7 CSPI2_SS0 0x150 0x3b0
+FEC_TXD2 4 GPIO3_8 CSPI2_SS1 0x154 0x3b4 :( reference Manual says: 0xBASE_
+FEC_TXD3 4 GPIO3_9 CSPI2_SCLK 0x158 0x3b8
+FEC_COL 1 GPIO2_0 EIM_CS0 0x054 0x2b4 0x5a0 0
+FEC_CRS 4 GPIO3_2 CSPI1_SS0 0x13c 0x39c 0x5a4 1
+FEC_TX_ER 4 GPIO3_4 CSPI1_SCLK 0x144 0x3a4
+
+FEC_RESET# 1 GPIO1_7 GPIO1_7 0x22c 0x484
+FEC_ENABLE 4 GPIO2_9 NANDF_CS1 0x088 0x2e8
+---
+OSC26M_ENABLE LP3972 GPIO2
+*/
+static void fec_gpio_init(void)
+{
+ /* setup GPIO data register to 0 and DDIR output for FEC PHY pins */
+ setup_gpio(3, 1);
+ setup_gpio(2, 23);
+ setup_gpio(2, 1);
+ setup_gpio(1, 10);
+ setup_gpio(2, 30);
+ setup_gpio(3, 3);
+ setup_gpio(3, 5);
+ setup_gpio(3, 6);
+ setup_gpio(3, 0);
+ setup_gpio(1, 9);
+ setup_gpio(1, 13);
+ setup_gpio(2, 31);
+ setup_gpio(3, 7);
+ setup_gpio(3, 8);
+ setup_gpio(3, 9);
+ setup_gpio(2, 0);
+ setup_gpio(3, 2);
+ setup_gpio(3, 4);
+
+ setup_gpio(1, 7);
+ setup_gpio(2, 9);
+
+ /* setup input mux for FEC pins */
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x5a8, 0);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x5b0, 0);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x5b4, 0);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x5ac, 1);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x5b8, 1);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x5bc, 0);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x5a0, 0);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x5a4, 1);
+
+ /* setup FEC PHY pins for GPIO function (with SION set) */
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x138, 4 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x130, 4 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x058, 1 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x064, 3 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x174, 4 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x140, 4 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x148, 4 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x14c, 4 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x134, 4 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x068, 3 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x050, 3 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x178, 4 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x150, 4 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x154, 4 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x158, 4 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x054, 1 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x13c, 4 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x144, 4 | 0x10);
+
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x22c, 1 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x088, 4 | 0x10);
+}
+
+void plf_hardware_init(void)
+{
+ unsigned int v;
+
+ fec_gpio_init();
+
+ v = (32 << 16) | /* spare area size: 32 half words */
+ (1 << 12) | /* 8bit bus */
+ (3 << 9) | /* extra dead cycles [0..7] */
+ (1 << 7) | /* PPB: 0: 32 1: 64 2: 128 3: 256 */
+ (1 << 6) | /* ECC mode: 0: 8bit 1: 4bit */
+ (0 << 5) | /* little endian */
+ (1 << 4) | /* disable interrupt */
+ (1 << 3) | /* enable ECC */
+ (0 << 2) | /* SYM: 0: asymmetric 1: symmetric */
+ (1 << 0); /* PS: 0: 512 1: 2K 2: 4K 3: 4K */
+ writel(v, NFC_FLASH_CONFIG2_REG);
+
+ writel(0xFFFF0000, UNLOCK_BLK_ADD0_REG);
+ writel(0xFFFF0000, UNLOCK_BLK_ADD1_REG);
+ writel(0xFFFF0000, UNLOCK_BLK_ADD2_REG);
+ writel(0xFFFF0000, UNLOCK_BLK_ADD3_REG);
+
+ v = NFC_WR_PROT_CS0 | NFC_WR_PROT_BLS_UNLOCK | NFC_WR_PROT_WPC;
+ writel(v, NFC_WR_PROT_REG);
+
+ writel(0, NFC_IPC_REG);
+
+ // UART1
+ //RXD
+ writel(0x0, IOMUXC_BASE_ADDR + 0x15C);
+ writel(0x4, IOMUXC_BASE_ADDR + 0x604);
+ writel(0x1C5, IOMUXC_BASE_ADDR + 0x3BC);
+
+ //TXD
+ writel(0x0, IOMUXC_BASE_ADDR + 0x160);
+ writel(0x1C5, IOMUXC_BASE_ADDR + 0x3C0);
+
+ //RTS
+ writel(0x0, IOMUXC_BASE_ADDR + 0x164);
+ writel(0x4, IOMUXC_BASE_ADDR + 0x600);
+ writel(0x1C4, IOMUXC_BASE_ADDR + 0x3C4);
+
+ //CTS
+ writel(0x0, IOMUXC_BASE_ADDR + 0x168);
+ writel(0x1C4, IOMUXC_BASE_ADDR + 0x3C8);
+}
+
+typedef void code_fun(void);
+
+void tx37_program_new_stack(void *func)
+{
+ register CYG_ADDRESS stack_ptr asm("sp");
+ register CYG_ADDRESS old_stack asm("r4");
+ register code_fun *new_func asm("r0");
+ old_stack = stack_ptr;
+ stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
+ new_func = (code_fun*)func;
+ new_func();
+ stack_ptr = old_stack;
+}
+
+static void display_board_info(void)
+{
+ const char *dlm = "";
+ CYG_WORD32 srsr;
+ CYG_WORD16 wrsr;
+
+ diag_printf("\nBoard Type: Ka-Ro TX37\n");
+
+ HAL_READ_UINT32(SRC_SRSR_REG, srsr);
+ diag_printf("Last RESET cause: ");
+
+ if (srsr & (1 << 16)) {
+ diag_printf("%s%s", dlm, "WARM BOOT");
+ dlm = " | ";
+ }
+ if (srsr & (1 << 0)) {
+ diag_printf("%s%s", dlm, "POWER_ON");
+ dlm = " | ";
+ }
+ if (srsr & (1 << 2)) {
+ diag_printf("%s%s", dlm, "EXTERNAL");
+ dlm = " | ";
+ }
+ if (srsr & (1 << 3)) {
+ diag_printf("%s%s", dlm, "COLD");
+ dlm = " | ";
+ }
+ if (srsr & (1 << 4)) {
+ HAL_READ_UINT16(WDOG_WRSR_REG, wrsr);
+ if (wrsr & (1 << 0)) {
+ diag_printf("%s%s", dlm, "SOFTWARE");
+ dlm = " | ";
+ }
+ if (wrsr & (1 << 1)) {
+ diag_printf("%s%s", dlm, "WATCHDOG");
+ dlm = " | ";
+ }
+ }
+ if (srsr & (1 << 5)) {
+ diag_printf("%s%s", dlm, "JTAG");
+ dlm = " | ";
+ }
+ if (*dlm == '\0') {
+ diag_printf("Last RESET cause: UNKNOWN: 0x%08x\n", srsr);
+ } else {
+ diag_printf(" RESET\n");
+ }
+ return;
+}
+RedBoot_init(display_board_info, RedBoot_INIT_LAST);
description "
The processor can run at various frequencies.
These values are expressed in KHz. Note that there are
- several steppings of the rated to run at different
+ several steppings of the rate to run at different
maximum frequencies. Check the specs to make sure that your
particular processor can run at the rate you select here."
}
ARM_ACCESS_TYPE_NO_ACCESS(14) | \
ARM_ACCESS_TYPE_NO_ACCESS(15) )
+/*
+ * translate the virtual address of ram space to physical address
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
+{
+ if (virt < 0x08000000) {
+ return virt | 0x40000000;
+ }
+ if ((virt & 0xF0000000) == 0x40000000) {
+ return virt & ~0x08000000;
+ }
+ return virt;
+}
+
+/*
+ * remap the physical address of ram space to uncacheable virtual address space
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
+{
+ /* 0x48000000~0x48FFFFFF is uncacheable meory space which is mapped to SDRAM*/
+ if ((phy & 0xF0000000) == 0x40000000) {
+ phy |= 0x08000000;
+ }
+ return phy;
+}
+
// ------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_MM_H
// End of hal_mm.h
//==========================================================================
//
-// hal_soc.h
+// hal_soc.h
//
-// SoC chip definitions
+// SoC chip definitions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
#define __HAL_SOC_H__
#ifdef __ASSEMBLER__
+#define UL(a) (a)
+#define REG8_VAL(a) (a)
+#define REG16_VAL(a) (a)
+#define REG32_VAL(a) (a)
-#define REG8_VAL(a) (a)
-#define REG16_VAL(a) (a)
-#define REG32_VAL(a) (a)
-
-#define REG8_PTR(a) (a)
-#define REG16_PTR(a) (a)
-#define REG32_PTR(a) (a)
+#define REG8_PTR(a) (a)
+#define REG16_PTR(a) (a)
+#define REG32_PTR(a) (a)
#else /* __ASSEMBLER__ */
+#define UL(a) (a##UL)
+
extern char HAL_PLATFORM_EXTRA[];
-#define REG8_VAL(a) ((unsigned char)(a))
-#define REG16_VAL(a) ((unsigned short)(a))
-#define REG32_VAL(a) ((unsigned int)(a))
-
-#define REG8_PTR(a) ((volatile unsigned char *)(a))
-#define REG16_PTR(a) ((volatile unsigned short *)(a))
-#define REG32_PTR(a) ((volatile unsigned int *)(a))
-#define readb(a) (*(volatile unsigned char *)(a))
-#define readw(a) (*(volatile unsigned short *)(a))
-#define readl(a) (*(volatile unsigned int *)(a))
-#define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
-#define writew(v,a) (*(volatile unsigned short *)(a) = (v))
-#define writel(v,a) (*(volatile unsigned int *)(a) = (v))
+#define REG8_VAL(a) ((unsigned char)(a))
+#define REG16_VAL(a) ((unsigned short)(a))
+#define REG32_VAL(a) ((unsigned int)(a))
+
+#define REG8_PTR(a) ((volatile unsigned char *)(a))
+#define REG16_PTR(a) ((volatile unsigned short *)(a))
+#define REG32_PTR(a) ((volatile unsigned int *)(a))
+#define readb(a) (*(volatile unsigned char *)(a))
+#define readw(a) (*(volatile unsigned short *)(a))
+#define readl(a) (*(volatile unsigned int *)(a))
+#define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
+#define writew(v,a) (*(volatile unsigned short *)(a) = (v))
+#define writel(v,a) (*(volatile unsigned int *)(a) = (v))
#endif /* __ASSEMBLER__ */
* Default Memory Layout Definitions
*/
-#define L2CC_BASE_ADDR 0xB0000000
+#define L2CC_BASE_ADDR UL(0xB0000000)
-#define IRAM_BASE_ADDR 0x10000000
+#define IRAM_BASE_ADDR UL(0x10000000)
/*
* AIPS 1
*/
-#define AIPS1_BASE_ADDR 0xC3F00000
-#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
-#define MAX_BASE_ADDR 0xC3F80000
-#define GPIO1_BASE_ADDR 0xC3F84000
-#define GPIO2_BASE_ADDR 0xC3F88000
-#define GPIO3_BASE_ADDR 0xC3F8C000
-#define KPP_BASE_ADDR 0xC3F94000
-#define WDOG1_BASE_ADDR 0xC3F98000
-#define WDOG_BASE_ADDR WDOG1_BASE_ADDR
-#define WDOG2_BASE_ADDR 0xC3F9C000
-#define GPT1_BASE_ADDR 0xC3FA0000
-#define RTC_BASE_ADDR 0xC3FA4000
-#define IOMUXC_BASE_ADDR 0xC3FA8000
-#define IIM_BASE_ADDR 0xC3FAC000
-#define FEC_BASE_ADDR 0xC3FE8000
-
+#define AIPS1_BASE_ADDR UL(0xC3F00000)
+#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
+#define MAX_BASE_ADDR UL(0xC3F80000)
+#define GPIO1_BASE_ADDR UL(0xC3F84000)
+#define GPIO2_BASE_ADDR UL(0xC3F88000)
+#define GPIO3_BASE_ADDR UL(0xC3F8C000)
+#define KPP_BASE_ADDR UL(0xC3F94000)
+#define WDOG1_BASE_ADDR UL(0xC3F98000)
+#define WDOG_BASE_ADDR WDOG1_BASE_ADDR
+
+#define WDOG_WCR_REG (WDOG_BASE_ADDR + 0x00)
+#define WDOG_WRSR_REG (WDOG_BASE_ADDR + 0x04)
+
+#define WDOG2_BASE_ADDR UL(0xC3F9C000)
+#define GPT1_BASE_ADDR UL(0xC3FA0000)
+#define RTC_BASE_ADDR UL(0xC3FA4000)
+#define IOMUXC_BASE_ADDR UL(0xC3FA8000)
+#define IIM_BASE_ADDR UL(0xC3FAC000)
+#define FEC_BASE_ADDR UL(0xC3FE8000)
+#define SOC_FEC_BASE FEC_BASE_ADDR
/*
* SPBA
*/
-#define MMC_SDHC1_BASE_ADDR 0xC0004000
-#define ESDHC1_REG_BASE MMC_SDHC1_BASE_ADDR
-#define MMC_SDHC2_BASE_ADDR 0xC0008000
-#define UART3_BASE_ADDR 0xC000C000
-#define CSPI2_BASE_ADDR 0xC0010000
-#define SSI2_BASE_ADDR 0xC0014000
-#define ATA_DMA_BASE_ADDR 0xC0034000
-#define SPBA_CTRL_BASE_ADDR 0xC003C000
+#define MMC_SDHC1_BASE_ADDR UL(0xC0004000)
+#define ESDHC1_REG_BASE MMC_SDHC1_BASE_ADDR
+#define MMC_SDHC2_BASE_ADDR UL(0xC0008000)
+#define UART3_BASE_ADDR UL(0xC000C000)
+#define CSPI2_BASE_ADDR UL(0xC0010000)
+#define SSI2_BASE_ADDR UL(0xC0014000)
+#define ATA_DMA_BASE_ADDR UL(0xC0034000)
+#define SPBA_CTRL_BASE_ADDR UL(0xC003C000)
/*
* AIPS 2
*/
-#define AIPS2_BASE_ADDR 0xE3F00000
-#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
-#define PLL1_BASE_ADDR 0xE3F80000
-#define PLL2_BASE_ADDR 0xE3F84000
-#define PLL3_BASE_ADDR 0xE3F88000
-#define CCM_BASE_ADDR 0xE3F8C000
-#define SRC_BASE_ADDR 0xE3F94000
-#define EPIT1_BASE_ADDR 0xE3F98000
-#define EPIT2_BASE_ADDR 0xE3F9C000
-#define CSPI3_BASE_ADDR 0xE3FA8000
-#define CSPI1_BASE_ADDR 0xE3FAC000
-#define UART1_BASE_ADDR 0xE3FB0000
-#define UART2_BASE_ADDR 0xE3FBC000
-#define I2C3_BASE_ADDR 0xE3FC0000
-#define I2C2_BASE_ADDR 0xE3FC4000
-#define I2C_BASE_ADDR 0xE3FC8000
-#define SSI1_BASE_ADDR 0xE3FCC000
-#define AUDMUX_BASE 0xE3FD0000
-
-#define GPC_BASE_ADDR 0xE3F90000
-#define GPC_CNTR_REG (GPC_BASE_ADDR + 0)
-#define GPC_PGR_REG (GPC_BASE_ADDR + 4)
-#define GPC_VCR_REG (GPC_BASE_ADDR + 8)
-
-#define PGC_BASE_VPU (GPC_BASE_ADDR + 0x0240)
-#define PGC_BASE_IPU (GPC_BASE_ADDR + 0x0220)
-#define GPC_PGR (GPC_BASE_ADDR + 0x000)
-#define SRPGCR_ARM (GPC_BASE_ADDR + 0x02A0 + 0x0000)
-#define SRPGCR_EMI (GPC_BASE_ADDR + 0x0280 + 0x0000)
-#define PGC_PGCR_VPU (PGC_BASE_VPU + 0x0000)
-#define PGC_PGCR_IPU (PGC_BASE_IPU + 0x0000)
-
-#define PLATFORM_BASE_ADDR 0xB0404000
-#define PLATFORM_LPC_REG (PLATFORM_BASE_ADDR + 0x14)
+#define AIPS2_BASE_ADDR UL(0xE3F00000)
+#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
+#define PLL1_BASE_ADDR UL(0xE3F80000)
+#define PLL2_BASE_ADDR UL(0xE3F84000)
+#define PLL3_BASE_ADDR UL(0xE3F88000)
+#define CCM_BASE_ADDR UL(0xE3F8C000)
+#define SRC_BASE_ADDR UL(0xE3F94000)
+
+#define SRC_SRSR_REG (SRC_BASE_ADDR + 0x08)
+
+#define EPIT1_BASE_ADDR UL(0xE3F98000)
+#define EPIT2_BASE_ADDR UL(0xE3F9C000)
+#define CSPI3_BASE_ADDR UL(0xE3FA8000)
+#define CSPI1_BASE_ADDR UL(0xE3FAC000)
+#define UART1_BASE_ADDR UL(0xE3FB0000)
+#define UART2_BASE_ADDR UL(0xE3FBC000)
+#define I2C3_BASE_ADDR UL(0xE3FC0000)
+#define I2C2_BASE_ADDR UL(0xE3FC4000)
+#define I2C_BASE_ADDR UL(0xE3FC8000)
+#define SSI1_BASE_ADDR UL(0xE3FCC000)
+#define AUDMUX_BASE UL(0xE3FD0000)
+
+#define GPC_BASE_ADDR UL(0xE3F90000)
+#define GPC_CNTR_REG (GPC_BASE_ADDR + 0x0)
+#define GPC_PGR_REG (GPC_BASE_ADDR + 0x4)
+#define GPC_VCR_REG (GPC_BASE_ADDR + 0x8)
+
+#define PGC_BASE_VPU (GPC_BASE_ADDR + 0x0240)
+#define PGC_BASE_IPU (GPC_BASE_ADDR + 0x0220)
+#define GPC_PGR (GPC_BASE_ADDR + 0x000)
+#define SRPGCR_ARM (GPC_BASE_ADDR + 0x02A0 + 0x0000)
+#define SRPGCR_EMI (GPC_BASE_ADDR + 0x0280 + 0x0000)
+#define PGC_PGCR_VPU (PGC_BASE_VPU + 0x0000)
+#define PGC_PGCR_IPU (PGC_BASE_IPU + 0x0000)
+
+#define PLATFORM_BASE_ADDR UL(0xB0404000)
+#define PLATFORM_LPC_REG (PLATFORM_BASE_ADDR + 0x14)
/*
* Interrupt controller
*/
-#define INTC_BASE_ADDR 0xB0800000
+#define INTC_BASE_ADDR UL(0xB0800000)
/*
* NAND, SDRAM, WEIM, M4IF, EMI controllers
*/
-#define NFC_IP_BASE 0xE3FDB000
-#define ESDCTL_BASE 0xE3FD9000
-#define WEIM_BASE_ADDR 0xE3FDA000
-
-#define WEIM_CTRL_CS0 WEIM_BASE_ADDR
-#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x18)
-#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x30)
-#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x48)
-#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x60)
-#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x78)
-#define M4IF_BASE 0xE3FD8000
+#define NFC_IP_BASE UL(0xE3FDB000)
+#define ESDCTL_BASE UL(0xE3FD9000)
+#define WEIM_BASE_ADDR UL(0xE3FDA000)
+
+#define WEIM_CTRL_CS0 WEIM_BASE_ADDR
+#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x18)
+#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x30)
+#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x48)
+#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x60)
+#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x78)
+#define M4IF_BASE UL(0xE3FD8000)
/*
* Memory regions and CS
*/
-#define CSD0_BASE_ADDR 0x40000000
-#define CSD1_BASE_ADDR 0x50000000
-#define CS0_BASE_ADDR 0x60000000
-#define CS1_BASE_ADDR 0x68000000
-#define CS2_BASE_ADDR 0x70000000
+#define CSD0_BASE_ADDR UL(0x40000000)
+#define CSD1_BASE_ADDR UL(0x50000000)
+#define CS0_BASE_ADDR UL(0x60000000)
+#define CS1_BASE_ADDR UL(0x68000000)
+#define CS2_BASE_ADDR UL(0x70000000)
/*
* IRQ Controller Register Definitions.
*/
-#define INTC_NIMASK REG32_PTR(INTC_BASE_ADDR + (0x04))
-#define INTC_INTTYPEH REG32_PTR(INTC_BASE_ADDR + (0x18))
-#define INTC_INTTYPEL REG32_PTR(INTC_BASE_ADDR + (0x1C))
+#define INTC_NIMASK REG32_PTR(INTC_BASE_ADDR + (0x04))
+#define INTC_INTTYPEH REG32_PTR(INTC_BASE_ADDR + (0x18))
+#define INTC_INTTYPEL REG32_PTR(INTC_BASE_ADDR + (0x1C))
/* M4IF */
-#define M4IF_FBPM0 0x40
-#define M4IF_FIDBP 0x48
+#define M4IF_FBPM0 0x40
+#define M4IF_FIDBP 0x48
/* L210 */
-#define L2_CACHE_LINE_SIZE 32
-#define L2_CACHE_CTL_REG 0x100
-#define L2_CACHE_AUX_CTL_REG 0x104
-#define L2_CACHE_SYNC_REG 0x730
-#define L2_CACHE_INV_LINE_REG 0x770
-#define L2_CACHE_INV_WAY_REG 0x77C
-#define L2_CACHE_CLEAN_LINE_PA_REG 0x7B0
-#define L2_CACHE_CLEAN_LINE_WAY_REG 0x7B8
-#define L2_CACHE_CLEAN_WAY_REG 0x7BC
-#define L2_CACHE_CLEAN_INV_LINE_PA_REG 0x7F0
+#define L2_CACHE_LINE_SIZE 32
+#define L2_CACHE_CTL_REG 0x100
+#define L2_CACHE_AUX_CTL_REG 0x104
+#define L2_CACHE_SYNC_REG 0x730
+#define L2_CACHE_INV_LINE_REG 0x770
+#define L2_CACHE_INV_WAY_REG 0x77C
+#define L2_CACHE_CLEAN_LINE_PA_REG 0x7B0
+#define L2_CACHE_CLEAN_LINE_WAY_REG 0x7B8
+#define L2_CACHE_CLEAN_WAY_REG 0x7BC
+#define L2_CACHE_CLEAN_INV_LINE_PA_REG 0x7F0
#define L2_CACHE_CLEAN_INV_LINE_WAY_REG 0x7F8
-#define L2_CACHE_CLEAN_INV_WAY_REG 0x7FC
+#define L2_CACHE_CLEAN_INV_WAY_REG 0x7FC
/* CCM */
-#define CLKCTL_CCMR 0x00
-#define CLKCTL_PDR0 0x04
-#define CLKCTL_PDR1 0x08
-
-#define CLKCTL_CCSR 0x0C
-#define CLKCTL_CACRR 0x10
-#define CLKCTL_CBCDR2 0x18
-#define CLKCTL_CBCDR3 0x1C
-#define CLKCTL_CBCDR4 0x20
-#define CLKCTL_CBCDR5 0x24
-#define CLKCTL_CBCDR6 0x28
-#define CLKCTL_CBCDR7 0x2C
-#define CLKCTL_CAMR 0x30
-#define CLKCTL_PDR2 0x64
-#define CLKCTL_RCSR 0x0C
-#define CLKCTL_MPCTL 0x10
-#define CLKCTL_UPCTL 0x14
-#define CLKCTL_SPCTL 0x18
-#define CLKCTL_COSR 0x1C
-#define CLKCTL_CSCMR1 0x34
-#define CLKCTL_CSCDR1 0x3C
-#define CLKCTL_CS1CDR 0x40
-#define CLKCTL_CS2CDR 0x44
-#define CLKCTL_CSCDR2 0x60
-#define CLKCTL_CDCR 0x6C
-#define CLKCTL_CCOSR 0x80
-
-#define FREQ_24MHZ 24000000
-#define FREQ_32768HZ (32768 * 1024)
-#define FREQ_38400HZ (38400 * 1024)
-#define FREQ_32000HZ (32000 * 1024)
-#define PLL_REF_CLK FREQ_24MHZ
+#define CLKCTL_CCMR 0x00
+#define CLKCTL_PDR0 0x04
+#define CLKCTL_PDR1 0x08
+
+#define CLKCTL_CCSR 0x0C
+#define CLKCTL_CACRR 0x10
+#define CLKCTL_CBCDR2 0x18
+#define CLKCTL_CBCDR3 0x1C
+#define CLKCTL_CBCDR4 0x20
+#define CLKCTL_CBCDR5 0x24
+#define CLKCTL_CBCDR6 0x28
+#define CLKCTL_CBCDR7 0x2C
+#define CLKCTL_CAMR 0x30
+#define CLKCTL_PDR2 0x64
+#define CLKCTL_RCSR 0x0C
+#define CLKCTL_MPCTL 0x10
+#define CLKCTL_UPCTL 0x14
+#define CLKCTL_SPCTL 0x18
+#define CLKCTL_COSR 0x1C
+#define CLKCTL_CSCMR1 0x34
+#define CLKCTL_CSCDR1 0x3C
+#define CLKCTL_CS1CDR 0x40
+#define CLKCTL_CS2CDR 0x44
+#define CLKCTL_CSCDR2 0x60
+#define CLKCTL_CDCR 0x6C
+#define CLKCTL_CCOSR 0x80
+
+#define FREQ_24MHZ 24000000
+#define FREQ_32768HZ (32768 * 1024)
+#define FREQ_38400HZ (38400 * 1024)
+#define FREQ_32000HZ (32000 * 1024)
+#define PLL_REF_CLK FREQ_24MHZ
//#define PLL_REF_CLK FREQ_32768HZ
//#define PLL_REF_CLK FREQ_32000HZ
/* WEIM registers */
-#define CSGCR1 0x00
-#define CSGCR2 0x04
-#define CSRCR1 0x08
-#define CSRCR2 0x0C
-#define CSWCR1 0x10
+#define CSGCR1 0x00
+#define CSGCR2 0x04
+#define CSRCR1 0x08
+#define CSRCR2 0x0C
+#define CSWCR1 0x10
/* ESDCTL */
-#define ESDCTL_ESDCTL0 0x00
-#define ESDCTL_ESDCFG0 0x04
-#define ESDCTL_ESDCTL1 0x08
-#define ESDCTL_ESDCFG1 0x0C
-#define ESDCTL_ESDMISC 0x10
-#define ESDCTL_ESDSCR 0x14
-#define ESDCTL_ESDCDLY1 0x20
-#define ESDCTL_ESDCDLY2 0x24
-#define ESDCTL_ESDCDLY3 0x28
-#define ESDCTL_ESDCDLY4 0x2C
-#define ESDCTL_ESDCDLY5 0x30
-#define ESDCTL_ESDCDLYGD 0x34
+#define ESDCTL_ESDCTL0 0x00
+#define ESDCTL_ESDCFG0 0x04
+#define ESDCTL_ESDCTL1 0x08
+#define ESDCTL_ESDCFG1 0x0C
+#define ESDCTL_ESDMISC 0x10
+#define ESDCTL_ESDSCR 0x14
+#define ESDCTL_ESDCDLY1 0x20
+#define ESDCTL_ESDCDLY2 0x24
+#define ESDCTL_ESDCDLY3 0x28
+#define ESDCTL_ESDCDLY4 0x2C
+#define ESDCTL_ESDCDLY5 0x30
+#define ESDCTL_ESDCDLYGD 0x34
/* DPLL */
-#define PLL_DP_CTL 0x00
-#define PLL_DP_CONFIG 0x04
-#define PLL_DP_OP 0x08
-#define PLL_DP_MFD 0x0C
-#define PLL_DP_MFN 0x10
-#define PLL_DP_MFNMINUS 0x14
-#define PLL_DP_MFNPLUS 0x18
-#define PLL_DP_HFS_OP 0x1C
-#define PLL_DP_HFS_MFD 0x20
-#define PLL_DP_HFS_MFN 0x24
-#define PLL_DP_TOGC 0x28
-#define PLL_DP_DESTAT 0x2C
-
-#define CHIP_REV_1_0 0x0 /* PASS 1.0 */
-#define CHIP_REV_1_1 0x1 /* PASS 1.1 */
-#define CHIP_REV_2_0 0x2 /* PASS 2.0 */
-#define CHIP_LATEST CHIP_REV_1_1
-
-#define IIM_STAT_OFF 0x00
-#define IIM_STAT_BUSY (1 << 7)
-#define IIM_STAT_PRGD (1 << 1)
-#define IIM_STAT_SNSD (1 << 0)
-#define IIM_STATM_OFF 0x04
-#define IIM_ERR_OFF 0x08
-#define IIM_ERR_PRGE (1 << 7)
-#define IIM_ERR_WPE (1 << 6)
-#define IIM_ERR_OPE (1 << 5)
-#define IIM_ERR_RPE (1 << 4)
-#define IIM_ERR_WLRE (1 << 3)
-#define IIM_ERR_SNSE (1 << 2)
-#define IIM_ERR_PARITYE (1 << 1)
-#define IIM_EMASK_OFF 0x0C
-#define IIM_FCTL_OFF 0x10
-#define IIM_UA_OFF 0x14
-#define IIM_LA_OFF 0x18
-#define IIM_SDAT_OFF 0x1C
-#define IIM_PREV_OFF 0x20
-#define IIM_SREV_OFF 0x24
-#define IIM_PREG_P_OFF 0x28
-#define IIM_SCS0_OFF 0x2C
-#define IIM_SCS1_P_OFF 0x30
-#define IIM_SCS2_OFF 0x34
-#define IIM_SCS3_P_OFF 0x38
-
-#define EPIT_BASE_ADDR EPIT1_BASE_ADDR
-#define EPITCR 0x00
-#define EPITSR 0x04
-#define EPITLR 0x08
-#define EPITCMPR 0x0C
-#define EPITCNR 0x10
+#define PLL_DP_CTL 0x00
+#define PLL_DP_CONFIG 0x04
+#define PLL_DP_OP 0x08
+#define PLL_DP_MFD 0x0C
+#define PLL_DP_MFN 0x10
+#define PLL_DP_MFNMINUS 0x14
+#define PLL_DP_MFNPLUS 0x18
+#define PLL_DP_HFS_OP 0x1C
+#define PLL_DP_HFS_MFD 0x20
+#define PLL_DP_HFS_MFN 0x24
+#define PLL_DP_TOGC 0x28
+#define PLL_DP_DESTAT 0x2C
+
+#define CHIP_REV_1_0 0x0 /* PASS 1.0 */
+#define CHIP_REV_1_1 0x1 /* PASS 1.1 */
+#define CHIP_REV_2_0 0x2 /* PASS 2.0 */
+#define CHIP_LATEST CHIP_REV_1_1
+
+#define IIM_STAT_OFF 0x00
+#define IIM_STAT_BUSY (1 << 7)
+#define IIM_STAT_PRGD (1 << 1)
+#define IIM_STAT_SNSD (1 << 0)
+#define IIM_STATM_OFF 0x04
+#define IIM_ERR_OFF 0x08
+#define IIM_ERR_PRGE (1 << 7)
+#define IIM_ERR_WPE (1 << 6)
+#define IIM_ERR_OPE (1 << 5)
+#define IIM_ERR_RPE (1 << 4)
+#define IIM_ERR_WLRE (1 << 3)
+#define IIM_ERR_SNSE (1 << 2)
+#define IIM_ERR_PARITYE (1 << 1)
+#define IIM_EMASK_OFF 0x0C
+#define IIM_FCTL_OFF 0x10
+#define IIM_UA_OFF 0x14
+#define IIM_LA_OFF 0x18
+#define IIM_SDAT_OFF 0x1C
+#define IIM_PREV_OFF 0x20
+#define IIM_SREV_OFF 0x24
+#define IIM_PREG_P_OFF 0x28
+#define IIM_SCS0_OFF 0x2C
+#define IIM_SCS1_P_OFF 0x30
+#define IIM_SCS2_OFF 0x34
+#define IIM_SCS3_P_OFF 0x38
+
+#define EPIT_BASE_ADDR EPIT1_BASE_ADDR
+#define EPITCR 0x00
+#define EPITSR 0x04
+#define EPITLR 0x08
+#define EPITCMPR 0x0C
+#define EPITCNR 0x10
/*defines iomux for mx37*/
-#define IOMUX_SD1_CMD_PORT 0
-#define IOMUX_SD1_CMD_PIN 32
-#define IOMUX_SD1_CMD_SEL (0x200 | 0x10 | (51<<12))
-#define IOMUX_SD1_CMD_DIR (0xFF)
-
-#define IOMUX_SD1_CLK_PORT 0
-#define IOMUX_SD1_CLK_PIN 32
-#define IOMUX_SD1_CLK_SEL (0x200 |(52<<12))
-#define IOMUX_SD1_CLK_DIR (0xFF)
-
-#define IOMUX_SD1_DATA0_PORT 0
-#define IOMUX_SD1_DATA0_PIN 32
-#define IOMUX_SD1_DATA0_SEL (0x200 | (53<<12))
-#define IOMUX_SD1_DATA0_DIR (0xFF)
-
-#define IOMUX_SD1_DATA1_PORT 0
-#define IOMUX_SD1_DATA1_PIN 32
-#define IOMUX_SD1_DATA1_SEL (0x200 | (54<<12))
-#define IOMUX_SD1_DATA1_DIR (0xFF)
-
-#define IOMUX_SD1_DATA2_PORT 0
-#define IOMUX_SD1_DATA2_PIN 32
-#define IOMUX_SD1_DATA2_SEL (0x200 | (55<<12))
-#define IOMUX_SD1_DATA2_DIR (0xFF)
-
-#define IOMUX_SD1_DATA3_PORT 0
-#define IOMUX_SD1_DATA3_PIN 32
-#define IOMUX_SD1_DATA3_SEL (0x200 | (56<<12))
-#define IOMUX_SD1_DATA3_DIR (0xFF)
-
-#define IOMUX_SD2_DATA0_PORT 0
-#define IOMUX_SD2_DATA0_PIN 32
-#define IOMUX_SD2_DATA0_SEL (0x200 | 0x4 | (59<<12))
-#define IOMUX_SD2_DATA0_DIR (0xFF)
-#define IOMUX_SD2_DATA1_PORT 0
-#define IOMUX_SD2_DATA1_PIN 32
-#define IOMUX_SD2_DATA1_SEL (0x200 | 0x4 | (60<<12))
-#define IOMUX_SD2_DATA1_DIR (0xFF)
-#define IOMUX_SD2_DATA2_PORT 0
-#define IOMUX_SD2_DATA2_PIN 32
-#define IOMUX_SD2_DATA2_SEL (0x200 | 0x4 | (61<<12))
-#define IOMUX_SD2_DATA2_DIR (0xFF)
-#define IOMUX_SD2_DATA3_PORT 0
-#define IOMUX_SD2_DATA3_PIN 32
-#define IOMUX_SD2_DATA3_SEL (0x200 | 0x4 | (62<<12))
-#define IOMUX_SD2_DATA3_DIR (0xFF)
-
-#define IOMUX_PAD_GPIO1_4_PORT 0
-#define IOMUX_PAD_GPIO1_4_PIN 32
-#define IOMUX_PAD_GPIO1_4_SEL (0x200 | 0x6 | (134<<12))
-#define IOMUX_PAD_GPIO1_4_SEL_1 (0x200 | 0x0 | (134<<12))
-#define IOMUX_PAD_GPIO1_4_DIR (0xFF)
-
-#define IOMUX_PAD_GPIO1_5_PORT 0
-#define IOMUX_PAD_GPIO1_5_PIN 32
-#define IOMUX_PAD_GPIO1_5_SEL (0x200 | 0x6 | (135<<12))
-#define IOMUX_PAD_GPIO1_5_DIR (0xFF)
-
-#define IOMUX_PAD_GPIO1_6_PORT 0
-#define IOMUX_PAD_GPIO1_6_PIN 32
-#define IOMUX_PAD_GPIO1_6_SEL (0x200 | 0x6 | (136<<12))
-#define IOMUX_PAD_GPIO1_6_DIR (0xFF)
-
-#define GPT_BASE_ADDR GPT1_BASE_ADDR
-#define GPTCR 0x00
-#define GPTPR 0x04
-#define GPTSR 0x08
-#define GPTIR 0x0C
-#define GPTOCR1 0x10
-#define GPTOCR2 0x14
-#define GPTOCR3 0x18
-#define GPTICR1 0x1C
-#define GPTICR2 0x20
-#define GPTCNT 0x24
+#define IOMUX_SD1_CMD_PORT 0
+#define IOMUX_SD1_CMD_PIN 32
+#define IOMUX_SD1_CMD_SEL (0x200 | 0x10 | (51 << 12))
+#define IOMUX_SD1_CMD_DIR 0xFF
+
+#define IOMUX_SD1_CLK_PORT 0
+#define IOMUX_SD1_CLK_PIN 32
+#define IOMUX_SD1_CLK_SEL (0x200 | (52 << 12))
+#define IOMUX_SD1_CLK_DIR 0xFF
+
+#define IOMUX_SD1_DATA0_PORT 0
+#define IOMUX_SD1_DATA0_PIN 32
+#define IOMUX_SD1_DATA0_SEL (0x200 | (53 << 12))
+#define IOMUX_SD1_DATA0_DIR 0xFF
+
+#define IOMUX_SD1_DATA1_PORT 0
+#define IOMUX_SD1_DATA1_PIN 32
+#define IOMUX_SD1_DATA1_SEL (0x200 | (54 << 12))
+#define IOMUX_SD1_DATA1_DIR 0xFF
+
+#define IOMUX_SD1_DATA2_PORT 0
+#define IOMUX_SD1_DATA2_PIN 32
+#define IOMUX_SD1_DATA2_SEL (0x200 | (55 << 12))
+#define IOMUX_SD1_DATA2_DIR 0xFF
+
+#define IOMUX_SD1_DATA3_PORT 0
+#define IOMUX_SD1_DATA3_PIN 32
+#define IOMUX_SD1_DATA3_SEL (0x200 | (56 << 12))
+#define IOMUX_SD1_DATA3_DIR 0xFF
+
+#define IOMUX_SD2_DATA0_PORT 0
+#define IOMUX_SD2_DATA0_PIN 32
+#define IOMUX_SD2_DATA0_SEL (0x200 | 0x4 | (59 << 12))
+#define IOMUX_SD2_DATA0_DIR 0xFF
+#define IOMUX_SD2_DATA1_PORT 0
+#define IOMUX_SD2_DATA1_PIN 32
+#define IOMUX_SD2_DATA1_SEL (0x200 | 0x4 | (60 << 12))
+#define IOMUX_SD2_DATA1_DIR 0xFF
+#define IOMUX_SD2_DATA2_PORT 0
+#define IOMUX_SD2_DATA2_PIN 32
+#define IOMUX_SD2_DATA2_SEL (0x200 | 0x4 | (61 << 12))
+#define IOMUX_SD2_DATA2_DIR 0xFF
+#define IOMUX_SD2_DATA3_PORT 0
+#define IOMUX_SD2_DATA3_PIN 32
+#define IOMUX_SD2_DATA3_SEL (0x200 | 0x4 | (62 << 12))
+#define IOMUX_SD2_DATA3_DIR 0xFF
+
+#define IOMUX_PAD_GPIO1_4_PORT 0
+#define IOMUX_PAD_GPIO1_4_PIN 32
+#define IOMUX_PAD_GPIO1_4_SEL (0x200 | 0x6 | (134 << 12))
+#define IOMUX_PAD_GPIO1_4_SEL_1 (0x200 | 0x0 | (134 << 12))
+#define IOMUX_PAD_GPIO1_4_DIR 0xFF
+
+#define IOMUX_PAD_GPIO1_5_PORT 0
+#define IOMUX_PAD_GPIO1_5_PIN 32
+#define IOMUX_PAD_GPIO1_5_SEL (0x200 | 0x6 | (135 << 12))
+#define IOMUX_PAD_GPIO1_5_DIR 0xFF
+
+#define IOMUX_PAD_GPIO1_6_PORT 0
+#define IOMUX_PAD_GPIO1_6_PIN 32
+#define IOMUX_PAD_GPIO1_6_SEL (0x200 | 0x6 | (136 << 12))
+#define IOMUX_PAD_GPIO1_6_DIR 0xFF
+
+#define GPT_BASE_ADDR GPT1_BASE_ADDR
+#define GPTCR 0x00
+#define GPTPR 0x04
+#define GPTSR 0x08
+#define GPTIR 0x0C
+#define GPTOCR1 0x10
+#define GPTOCR2 0x14
+#define GPTOCR3 0x18
+#define GPTICR1 0x1C
+#define GPTICR2 0x20
+#define GPTCNT 0x24
/* Assuming 26MHz input clock */
-/* PD MFD MFI MFN */
-#define MPCTL_PARAM_208 (((2-1) << 26) + ((1 -1) << 16) + (8 << 10) + (0 << 0))
-#define MPCTL_PARAM_399 (((1-1) << 26) + ((52-1) << 16) + (7 << 10) + (35 << 0))
-#define MPCTL_PARAM_532 (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
-#define MPCTL_PARAM_665 (((1-1) << 26) + ((52-1) << 16) + (12 << 10) + (41 << 0))
-#define MPCTL_PARAM_532_27 (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0))
-
-/* UPCTL PD MFD MFI MFN */
-#define UPCTL_PARAM_288 (((1-1) << 26) + ((13-1) << 16) + (5 << 10) + (7 << 0))
-#define UPCTL_PARAM_240 (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
-#define UPCTL_PARAM_240_27 (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0))
+/* PD MFD MFI MFN */
+#define MPCTL_PARAM_208 (((2-1) << 26) + ((1 -1) << 16) + (8 << 10) + (0 << 0))
+#define MPCTL_PARAM_399 (((1-1) << 26) + ((52-1) << 16) + (7 << 10) + (35 << 0))
+#define MPCTL_PARAM_532 (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
+#define MPCTL_PARAM_665 (((1-1) << 26) + ((52-1) << 16) + (12 << 10) + (41 << 0))
+#define MPCTL_PARAM_532_27 (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0))
+
+/* UPCTL PD MFD MFI MFN */
+#define UPCTL_PARAM_288 (((1-1) << 26) + ((13-1) << 16) + (5 << 10) + (7 << 0))
+#define UPCTL_PARAM_240 (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
+#define UPCTL_PARAM_240_27 (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0))
/* PDR0 */
-#define PDR0_208_104_52 0xFF870D48 /* ARM=208MHz, HCLK=104MHz, IPG=52MHz */
-#define PDR0_399_66_66 0xFF872B28 /* ARM=399MHz, HCLK=IPG=66.5MHz */
-#define PDR0_399_133_66 0xFF871650 /* ARM=399MHz, HCLK=133MHz, IPG=66.5MHz */
-#define PDR0_532_133_66 0xFF871D58 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
-#define PDR0_665_83_42 0xFF873B78 /* ARM=665MHz, HCLK=83MHz, IPG=42MHz */
-#define PDR0_665_133_66 0xFF872560 /* ARM=665MHz, HCLK=133MHz, IPG=66MHz */
-
-//#define BARKER_CODE_SWAP_LOC 0x404
-#define BARKER_CODE_VAL 0xB1
+#define PDR0_208_104_52 0xFF870D48 /* ARM=208MHz, HCLK=104MHz, IPG=52MHz */
+#define PDR0_399_66_66 0xFF872B28 /* ARM=399MHz, HCLK=IPG=66.5MHz */
+#define PDR0_399_133_66 0xFF871650 /* ARM=399MHz, HCLK=133MHz, IPG=66.5MHz */
+#define PDR0_532_133_66 0xFF871D58 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
+#define PDR0_665_83_42 0xFF873B78 /* ARM=665MHz, HCLK=83MHz, IPG=42MHz */
+#define PDR0_665_133_66 0xFF872560 /* ARM=665MHz, HCLK=133MHz, IPG=66MHz */
+
+//#define BARKER_CODE_SWAP_LOC 0x404
+#define BARKER_CODE_VAL 0xB1
#define NFC_V2_1
-#define NFC_BASE 0x7FFF0000
-#define NAND_REG_BASE (NFC_BASE + 0x1E00)
-
-#define NAND_ADD_CMD_REG (NAND_REG_BASE + 0x00)
-
-#define NAND_CONFIGURATION1_REG (NAND_REG_BASE + 0x04)
- #define NAND_CONFIGURATION1_NFC_RST (1 << 2)
- #define NAND_CONFIGURATION1_NF_CE (1 << 1)
- #define NAND_CONFIGURATION1_SP_EN (1 << 0)
-
-#define NAND_ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x08)
-
-#define NAND_LAUNCH_REG (NAND_REG_BASE + 0x0C)
- #define NAND_LAUNCH_FCMD (1 << 0)
- #define NAND_LAUNCH_FADD (1 << 1)
- #define NAND_LAUNCH_FDI (1 << 2)
-
-
-#define NFC_WR_PROT_REG (NFC_IP_BASE + 0x00)
- #define NFC_WR_PROT_CS0 (0 << 20)
- #define NFC_WR_PROT_BLS_UNLOCK (2 << 16)
- #define NFC_WR_PROT_WPC (4 << 0)
-
-#define UNLOCK_BLK_ADD0_REG (NFC_IP_BASE + 0x04)
-
-#define UNLOCK_BLK_ADD1_REG (NFC_IP_BASE + 0x08)
-
-#define UNLOCK_BLK_ADD2_REG (NFC_IP_BASE + 0x0C)
-
-#define UNLOCK_BLK_ADD3_REG (NFC_IP_BASE + 0x10)
-
-#define NFC_FLASH_CONFIG2_REG (NFC_IP_BASE + 0x14)
- #define NFC_FLASH_CONFIG2_EDC0 (0 << 9)
- #define NFC_FLASH_CONFIG2_EDC1 (1 << 9)
- #define NFC_FLASH_CONFIG2_EDC2 (2 << 9)
- #define NFC_FLASH_CONFIG2_EDC3 (3 << 9)
- #define NFC_FLASH_CONFIG2_EDC4 (4 << 9)
- #define NFC_FLASH_CONFIG2_EDC5 (5 << 9)
- #define NFC_FLASH_CONFIG2_EDC6 (6 << 9)
- #define NFC_FLASH_CONFIG2_EDC7 (7 << 9)
- #define NFC_FLASH_CONFIG2_PPB_32 (0 << 7)
- #define NFC_FLASH_CONFIG2_PPB_64 (1 << 7)
- #define NFC_FLASH_CONFIG2_PPB_128 (2 << 7)
- #define NFC_FLASH_CONFIG2_PPB_256 (3 << 7)
- #define NFC_FLASH_CONFIG2_INT_MSK (1 << 4)
- #define NFC_FLASH_CONFIG2_ECC_EN (1 << 3)
- #define NFC_FLASH_CONFIG2_SYM (1 << 2)
-
-#define NFC_IPC_REG (NFC_IP_BASE + 0x18)
- #define NFC_IPC_INT (1 << 31)
- #define NFC_IPC_LPS (1 << 30)
- #define NFC_IPC_RB_B (1 << 29)
- #define NFC_IPC_CACK (1 << 1)
- #define NFC_IPC_CREQ (1 << 0)
-#define NFC_AXI_ERR_ADD_REG (NFC_IP_BASE + 0x1C)
-
-#define MXC_NAND_BASE_DUMMY 0x00000000
-#define MXC_MMC_BASE_DUMMY 0x00000000
-
-#define FROM_SDRAM 0x00000000
-#define FROM_NAND_FLASH 0x10000000
-#define FROM_NOR_FLASH 0x20000000
-#define FROM_MMC_FLASH 0x40000000
-#define FROM_SPI_NOR_FLASH 0x80000000
-
-#define IS_BOOTING_FROM_NAND() (_mxc_boot == FROM_NAND_FLASH)
+#define NFC_BASE UL(0x7FFF0000)
+#define NAND_REG_BASE (NFC_BASE + 0x1E00)
+
+#define NAND_ADD_CMD_REG (NAND_REG_BASE + 0x00)
+
+#define NAND_CONFIGURATION1_REG (NAND_REG_BASE + 0x04)
+ #define NAND_CONFIGURATION1_NFC_RST (1 << 2)
+ #define NAND_CONFIGURATION1_NF_CE (1 << 1)
+ #define NAND_CONFIGURATION1_SP_EN (1 << 0)
+
+#define NAND_ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x08)
+
+#define NAND_LAUNCH_REG (NAND_REG_BASE + 0x0C)
+ #define NAND_LAUNCH_FCMD (1 << 0)
+ #define NAND_LAUNCH_FADD (1 << 1)
+ #define NAND_LAUNCH_FDI (1 << 2)
+
+
+#define NFC_WR_PROT_REG (NFC_IP_BASE + 0x00)
+ #define NFC_WR_PROT_CS0 (0 << 20)
+ #define NFC_WR_PROT_BLS_UNLOCK (2 << 16)
+ #define NFC_WR_PROT_WPC (4 << 0)
+
+#define UNLOCK_BLK_ADD0_REG (NFC_IP_BASE + 0x04)
+
+#define UNLOCK_BLK_ADD1_REG (NFC_IP_BASE + 0x08)
+
+#define UNLOCK_BLK_ADD2_REG (NFC_IP_BASE + 0x0C)
+
+#define UNLOCK_BLK_ADD3_REG (NFC_IP_BASE + 0x10)
+
+#define NFC_FLASH_CONFIG2_REG (NFC_IP_BASE + 0x14)
+ #define NFC_FLASH_CONFIG2_EDC0 (0 << 9)
+ #define NFC_FLASH_CONFIG2_EDC1 (1 << 9)
+ #define NFC_FLASH_CONFIG2_EDC2 (2 << 9)
+ #define NFC_FLASH_CONFIG2_EDC3 (3 << 9)
+ #define NFC_FLASH_CONFIG2_EDC4 (4 << 9)
+ #define NFC_FLASH_CONFIG2_EDC5 (5 << 9)
+ #define NFC_FLASH_CONFIG2_EDC6 (6 << 9)
+ #define NFC_FLASH_CONFIG2_EDC7 (7 << 9)
+ #define NFC_FLASH_CONFIG2_PPB_32 (0 << 7)
+ #define NFC_FLASH_CONFIG2_PPB_64 (1 << 7)
+ #define NFC_FLASH_CONFIG2_PPB_128 (2 << 7)
+ #define NFC_FLASH_CONFIG2_PPB_256 (3 << 7)
+ #define NFC_FLASH_CONFIG2_INT_MSK (1 << 4)
+ #define NFC_FLASH_CONFIG2_ECC_EN (1 << 3)
+ #define NFC_FLASH_CONFIG2_SYM (1 << 2)
+
+#define NFC_IPC_REG (NFC_IP_BASE + 0x18)
+ #define NFC_IPC_INT (1 << 31)
+ #define NFC_IPC_LPS (1 << 30)
+ #define NFC_IPC_RB_B (1 << 29)
+ #define NFC_IPC_CACK (1 << 1)
+ #define NFC_IPC_CREQ (1 << 0)
+#define NFC_AXI_ERR_ADD_REG (NFC_IP_BASE + 0x1C)
+
+#define MXC_NAND_BASE_DUMMY 0x00000000
+#define MXC_MMC_BASE_DUMMY 0x00000000
+
+#define FROM_SDRAM 0x00000000
+#define FROM_NAND_FLASH 0x10000000
+#define FROM_NOR_FLASH 0x20000000
+#define FROM_MMC_FLASH 0x40000000
+#define FROM_SPI_NOR_FLASH 0x80000000
+
+#define IS_BOOTING_FROM_NAND() (_mxc_boot == FROM_NAND_FLASH)
// No NOR flash is supported under MX37 for booting
-#define IS_BOOTING_FROM_NOR() (0)
-#define IS_BOOTING_FROM_SPI_NOR() (0)
-#define IS_BOOTING_FROM_SDRAM() (_mxc_boot == FROM_SDRAM)
-#define IS_BOOTING_FROM_MMC() (_mxc_boot == FROM_MMC_FLASH)
+#define IS_BOOTING_FROM_NOR() 0
+#define IS_BOOTING_FROM_SPI_NOR() 0
+#define IS_BOOTING_FROM_SDRAM() (_mxc_boot == FROM_SDRAM)
+#define IS_BOOTING_FROM_MMC() (_mxc_boot == FROM_MMC_FLASH)
#ifndef MXCFLASH_SELECT_NAND
-#define IS_FIS_FROM_NAND() 0
+#define IS_FIS_FROM_NAND() 0
#else
-#define IS_FIS_FROM_NAND() (_mxc_fis == FROM_NAND_FLASH)
+#define IS_FIS_FROM_NAND() (_mxc_fis == FROM_NAND_FLASH)
#endif
#ifndef MXCFLASH_SELECT_MMC
-#define IS_FIS_FROM_MMC() 0
+#define IS_FIS_FROM_MMC() 0
#else
-#define IS_FIS_FROM_MMC() (_mxc_fis == FROM_MMC_FLASH)
+#define IS_FIS_FROM_MMC() (_mxc_fis == FROM_MMC_FLASH)
#endif
-#define IS_FIS_FROM_NOR() 0
+#define IS_FIS_FROM_NOR() 0
/*
* This macro is used to get certain bit field from a number
*/
-#define MXC_GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1))
+#define MXC_GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1))
/*
* This macro is used to set certain bit field inside a number
*/
-#define MXC_SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
+#define MXC_SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
#define L2CC_ENABLED
-#define UART_WIDTH_32 /* internal UART is 32bit access only */
+#define UART_WIDTH_32 /* internal UART is 32bit access only */
/* Offsets for system_rev */
-#define PART_NUMBER_OFFSET (12)
-#define PMIC_ID_OFFSET (8)
-#define MAJOR_NUMBER_OFFSET (4)
-#define MINOR_NUMBER_OFFSET (0)
+#define PART_NUMBER_OFFSET 12
+#define PMIC_ID_OFFSET 8
+#define MAJOR_NUMBER_OFFSET 4
+#define MINOR_NUMBER_OFFSET 0
#if !defined(__ASSEMBLER__)
void cyg_hal_plf_serial_init(void);
void cyg_hal_plf_serial_stop(void);
void hal_delay_us(unsigned int usecs);
-#define HAL_DELAY_US(n) hal_delay_us(n)
+#define HAL_DELAY_US(n) hal_delay_us(n)
extern int _mxc_fis;
extern int _mxc_boot;
extern unsigned int system_rev;
enum plls {
- PLL1,
- PLL2,
- PLL3,
+ PLL1,
+ PLL2,
+ PLL3,
};
enum main_clocks {
- CPU_CLK,
- AHB_CLK,
- IPG_CLK,
- IPG_PER_CLK,
- DDR_CLK,
- NFC_CLK,
- USB_CLK,
+ CPU_CLK,
+ AHB_CLK,
+ IPG_CLK,
+ IPG_PER_CLK,
+ DDR_CLK,
+ NFC_CLK,
+ USB_CLK,
};
enum peri_clocks {
- UART1_BAUD,
- UART2_BAUD,
- UART3_BAUD,
- SSI1_BAUD,
- SSI2_BAUD,
- CSI_BAUD,
- MSTICK1_CLK,
- MSTICK2_CLK,
- SPI1_CLK = CSPI1_BASE_ADDR,
- SPI2_CLK = CSPI2_BASE_ADDR,
+ UART1_BAUD,
+ UART2_BAUD,
+ UART3_BAUD,
+ SSI1_BAUD,
+ SSI2_BAUD,
+ CSI_BAUD,
+ MSTICK1_CLK,
+ MSTICK2_CLK,
+ SPI1_CLK = CSPI1_BASE_ADDR,
+ SPI2_CLK = CSPI2_BASE_ADDR,
};
unsigned int pll_clock(enum plls pll);
#endif //#if !defined(__ASSEMBLER__)
-#define HAL_MMU_OFF() \
-CYG_MACRO_START \
- asm volatile ( \
- "mcr p15, 0, r0, c7, c14, 0;" \
- "mcr p15, 0, r0, c7, c10, 4;" /* drain the write buffer */ \
- "mcr p15, 0, r0, c7, c5, 0;" /* invalidate I cache */ \
- "mrc p15, 0, r0, c1, c0, 0;" /* read c1 */ \
- "bic r0, r0, #0x7;" /* disable DCache and MMU */ \
- "bic r0, r0, #0x1000;" /* disable ICache */ \
- "mcr p15, 0, r0, c1, c0, 0;" /* */ \
- "nop;" /* flush i+d-TLBs */ \
- "nop;" /* flush i+d-TLBs */ \
- "nop;" /* flush i+d-TLBs */ \
- : \
- : \
- : "r0","memory" /* clobber list */); \
+#define HAL_MMU_OFF() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mcr p15, 0, r0, c7, c14, 0;" \
+ "mcr p15, 0, r0, c7, c10, 4;" /* drain the write buffer */ \
+ "mcr p15, 0, r0, c7, c5, 0;" /* invalidate I cache */ \
+ "mrc p15, 0, r0, c1, c0, 0;" /* read c1 */ \
+ "bic r0, r0, #0x7;" /* disable DCache and MMU */ \
+ "bic r0, r0, #0x1000;" /* disable ICache */ \
+ "mcr p15, 0, r0, c1, c0, 0;" \
+ "nop;" /* flush i+d-TLBs */ \
+ "nop;" /* flush i+d-TLBs */ \
+ "nop;" /* flush i+d-TLBs */ \
+ : \
+ : \
+ : "r0","memory" /* clobber list */); \
CYG_MACRO_END
#endif /* __HAL_SOC_H__ */
// end up clumped into interrupt signal #11. Using the symbols
// below allow for detection of these separately.
-#define CYGNUM_HAL_INTERRUPT_GPIO11 (32+11)
-#define CYGNUM_HAL_INTERRUPT_GPIO12 (32+12)
-#define CYGNUM_HAL_INTERRUPT_GPIO13 (32+13)
-#define CYGNUM_HAL_INTERRUPT_GPIO14 (32+14)
-#define CYGNUM_HAL_INTERRUPT_GPIO15 (32+15)
-#define CYGNUM_HAL_INTERRUPT_GPIO16 (32+16)
-#define CYGNUM_HAL_INTERRUPT_GPIO17 (32+17)
-#define CYGNUM_HAL_INTERRUPT_GPIO18 (32+18)
-#define CYGNUM_HAL_INTERRUPT_GPIO19 (32+19)
-#define CYGNUM_HAL_INTERRUPT_GPIO20 (32+20)
-#define CYGNUM_HAL_INTERRUPT_GPIO21 (32+21)
-#define CYGNUM_HAL_INTERRUPT_GPIO22 (32+22)
-#define CYGNUM_HAL_INTERRUPT_GPIO23 (32+23)
-#define CYGNUM_HAL_INTERRUPT_GPIO24 (32+24)
-#define CYGNUM_HAL_INTERRUPT_GPIO25 (32+25)
-#define CYGNUM_HAL_INTERRUPT_GPIO26 (32+26)
-#define CYGNUM_HAL_INTERRUPT_GPIO27 (32+27)
+#define CYGNUM_HAL_INTERRUPT_GPIO11 (32 + 11)
+#define CYGNUM_HAL_INTERRUPT_GPIO12 (32 + 12)
+#define CYGNUM_HAL_INTERRUPT_GPIO13 (32 + 13)
+#define CYGNUM_HAL_INTERRUPT_GPIO14 (32 + 14)
+#define CYGNUM_HAL_INTERRUPT_GPIO15 (32 + 15)
+#define CYGNUM_HAL_INTERRUPT_GPIO16 (32 + 16)
+#define CYGNUM_HAL_INTERRUPT_GPIO17 (32 + 17)
+#define CYGNUM_HAL_INTERRUPT_GPIO18 (32 + 18)
+#define CYGNUM_HAL_INTERRUPT_GPIO19 (32 + 19)
+#define CYGNUM_HAL_INTERRUPT_GPIO20 (32 + 20)
+#define CYGNUM_HAL_INTERRUPT_GPIO21 (32 + 21)
+#define CYGNUM_HAL_INTERRUPT_GPIO22 (32 + 22)
+#define CYGNUM_HAL_INTERRUPT_GPIO23 (32 + 23)
+#define CYGNUM_HAL_INTERRUPT_GPIO24 (32 + 24)
+#define CYGNUM_HAL_INTERRUPT_GPIO25 (32 + 25)
+#define CYGNUM_HAL_INTERRUPT_GPIO26 (32 + 26)
+#define CYGNUM_HAL_INTERRUPT_GPIO27 (32 + 27)
#define CYGNUM_HAL_INTERRUPT_NONE -1
#define CYGNUM_HAL_ISR_MIN 0
-#define CYGNUM_HAL_ISR_MAX (27+32)
+#define CYGNUM_HAL_ISR_MAX (27 + 32)
-#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1)
+#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1)
// The vector used by the Real time clock
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0
// method for reading clock interrupt latency
#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
externC void hal_clock_latency(cyg_uint32 *);
-# define HAL_CLOCK_LATENCY( _pvalue_ ) \
- hal_clock_latency( (cyg_uint32 *)(_pvalue_) )
+#define HAL_CLOCK_LATENCY(_pvalue_) \
+ hal_clock_latency((cyg_uint32 *)(_pvalue_))
#endif
//----------------------------------------------------------------------------
// Reset.
-#define HAL_PLATFORM_RESET() \
- CYG_MACRO_START \
- *(volatile unsigned short *)WDOG_BASE_ADDR |= 0x4; \
- /* hang here forever if reset fails */ \
- while (1){} \
- CYG_MACRO_END
+#define HAL_PLATFORM_RESET() \
+ CYG_MACRO_START \
+ cyg_uint32 srsr; \
+ cyg_uint16 wcr; \
+ /* clear all reset flags */ \
+ HAL_READ_UINT32(SRC_SRSR_REG, srsr); \
+ HAL_WRITE_UINT32(SRC_SRSR_REG, srsr); \
+ HAL_READ_UINT16(WDOG_WCR_REG, wcr); \
+ wcr &= ~(1 << 4); \
+ HAL_WRITE_UINT16(WDOG_WCR_REG, wcr); \
+ /* hang here forever if reset fails */ \
+ while (1) {} \
+ CYG_MACRO_END
// Fallback (never really used)
#define HAL_PLATFORM_RESET_ENTRY 0x00000000
//==========================================================================
//
-// cmds.c
+// cmds.c
//
-// SoC [platform] specific RedBoot commands
+// SoC [platform] specific RedBoot commands
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
#include <redboot.h>
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/plf_mmap.h>
-#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
#include <cyg/hal/hal_cache.h>
int gcd(int m, int n);
-typedef unsigned long long u64;
-typedef unsigned int u32;
-typedef unsigned short u16;
-typedef unsigned char u8;
-
-#define SZ_DEC_1M 1000000
-#define PLL_PD_MAX 16 //actual pd+1
-#define PLL_MFI_MAX 15
-#define PLL_MFI_MIN 5
-#define ARM_DIV_MAX 8
-#define IPG_DIV_MAX 4
-#define AHB_DIV_MAX 8
-#define EMI_DIV_MAX 8
-#define NFC_DIV_MAX 8
-
-#define REF_IN_CLK_NUM 4
+typedef unsigned long long u64;
+typedef unsigned int u32;
+typedef unsigned short u16;
+typedef unsigned char u8;
+
+#define SZ_DEC_1M 1000000
+#define PLL_PD_MAX 16 //actual pd+1
+#define PLL_MFI_MAX 15
+#define PLL_MFI_MIN 5
+#define ARM_DIV_MAX 8
+#define IPG_DIV_MAX 4
+#define AHB_DIV_MAX 8
+#define EMI_DIV_MAX 8
+#define NFC_DIV_MAX 8
+
+#define REF_IN_CLK_NUM 4
struct fixed_pll_mfd {
- u32 ref_clk_hz;
- u32 mfd;
+ u32 ref_clk_hz;
+ u32 mfd;
};
const struct fixed_pll_mfd fixed_mfd[REF_IN_CLK_NUM] = {
- {0, 0}, // reserved
- {0, 0}, // reserved
- {FREQ_24MHZ, 24 * 16}, // 384
- {0, 0}, // reserved
+ {0, 0}, // reserved
+ {0, 0}, // reserved
+ {FREQ_24MHZ, 24 * 16}, // 384
+ {0, 0}, // reserved
};
struct pll_param {
- u32 pd;
- u32 mfi;
- u32 mfn;
- u32 mfd;
+ u32 pd;
+ u32 mfi;
+ u32 mfn;
+ u32 mfd;
};
-#define PLL_FREQ_MAX(_ref_clk_) (2 * _ref_clk_ * PLL_MFI_MAX)
-#define PLL_FREQ_MIN(_ref_clk_) ((2 * _ref_clk_ * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
-#define AHB_CLK_MAX 133333333
-#define IPG_CLK_MAX (AHB_CLK_MAX / 2)
-#define NFC_CLK_MAX 25000000
+#define PLL_FREQ_MAX(_ref_clk_) (2 * _ref_clk_ * PLL_MFI_MAX)
+#define PLL_FREQ_MIN(_ref_clk_) ((2 * _ref_clk_ * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
+#define AHB_CLK_MAX 133333333
+#define IPG_CLK_MAX (AHB_CLK_MAX / 2)
+#define NFC_CLK_MAX 25000000
// IPU-HSP clock is independent of the HCLK and can go up to 177MHz but requires
// higher voltage support. For simplicity, limit it to 133MHz
-#define HSP_CLK_MAX 133333333
+#define HSP_CLK_MAX 133333333
-#define ERR_WRONG_CLK -1
-#define ERR_NO_MFI -2
-#define ERR_NO_MFN -3
-#define ERR_NO_PD -4
-#define ERR_NO_PRESC -5
-#define ERR_NO_AHB_DIV -6
+#define ERR_WRONG_CLK -1
+#define ERR_NO_MFI -2
+#define ERR_NO_MFN -3
+#define ERR_NO_PD -4
+#define ERR_NO_PRESC -5
+#define ERR_NO_AHB_DIV -6
u32 pll_clock(enum plls pll);
u32 get_main_clock(enum main_clocks clk);
static volatile u32 *pll_base[] =
{
- REG32_PTR(PLL1_BASE_ADDR),
- REG32_PTR(PLL2_BASE_ADDR),
- REG32_PTR(PLL3_BASE_ADDR),
+ REG32_PTR(PLL1_BASE_ADDR),
+ REG32_PTR(PLL2_BASE_ADDR),
+ REG32_PTR(PLL3_BASE_ADDR),
};
-#define NOT_ON_VAL 0xDEADBEEF
+#define NOT_ON_VAL 0xDEADBEEF
static void clock_setup(int argc, char *argv[]);
static void clko(int argc, char *argv[]);
RedBoot_cmd("clock",
- "Setup/Display clock (max AHB=133MHz, max IPG=66.5MHz)\nSyntax:",
- "[<core clock in MHz> [:<AHB-to-core divider>[:<IPG-to-AHB divider>]]] \n\n\
+ "Setup/Display clock (max AHB=133MHz, max IPG=66.5MHz)\nSyntax:",
+
"[<core clock in MHz> [:<AHB-to-core divider>[:<IPG-to-AHB divider>]]] \n\n\
If a divider is zero or no divider is specified, the optimal divider values \n\
will be chosen. Examples:\n\
- [clock] -> Show various clocks\n\
- [clock 532] -> Core=532 AHB=133 IPG=66.5\n\
- [clock 399] -> Core=399 AHB=133 IPG=66.5\n\
- [clock 532:8] -> Core=532 AHB=66.5(Core/8) IPG=66.5\n\
- [clock 532:8:2] -> Core=532 AHB=66.5(Core/8) IPG=33.25(AHB/2)\n",
- clock_setup
- );
+ [clock] -> Show various clocks\n\
+ [clock 532] -> Core=532 AHB=133 IPG=66.5\n\
+ [clock 399] -> Core=399 AHB=133 IPG=66.5\n\
+ [clock 532:8] -> Core=532 AHB=66.5(Core/8) IPG=66.5\n\
+ [clock 532:8:2] -> Core=532 AHB=66.5(Core/8) IPG=33.25(AHB/2)\n",
+ clock_setup
+ );
/*!
* This is to calculate various parameters based on reference clock and
* targeted clock based on the equation:
- * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
+ * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
* This calculation is based on a fixed MFD value for simplicity.
*
- * @param ref reference clock freq in Hz
- * @param target targeted clock in Hz
- * @param p_pd calculated pd value (pd value from register + 1) upon return
- * @param p_mfi calculated actual mfi value upon return
- * @param p_mfn calculated actual mfn value upon return
- * @param p_mfd fixed mfd value (mfd value from register + 1) upon return
+ * @param ref reference clock freq in Hz
+ * @param target targeted clock in Hz
+ * @param p_pd calculated pd value (pd value from register + 1) upon return
+ * @param p_mfi calculated actual mfi value upon return
+ * @param p_mfn calculated actual mfn value upon return
+ * @param p_mfd fixed mfd value (mfd value from register + 1) upon return
*
- * @return 0 if successful; non-zero otherwise.
+ * @return 0 if successful; non-zero otherwise.
*/
int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
{
- u64 pd, mfi = 1, mfn, mfd, n_target = target, n_ref = ref, i;
-
- // make sure targeted freq is in the valid range. Otherwise the
- // following calculation might be wrong!!!
- if (n_target < PLL_FREQ_MIN(ref) || n_target > PLL_FREQ_MAX(ref))
- return ERR_WRONG_CLK;
- for (i = 0; ; i++) {
- if (i == REF_IN_CLK_NUM)
- return ERR_WRONG_CLK;
- if (fixed_mfd[i].ref_clk_hz == ref) {
- mfd = fixed_mfd[i].mfd;
- break;
- }
- }
- // Use n_target and n_ref to avoid overflow
- for (pd = 1; pd <= PLL_PD_MAX; pd++) {
- mfi = (n_target * pd) / (2 * n_ref);
- if (mfi > PLL_MFI_MAX) {
- return ERR_NO_MFI;
- } else if (mfi < 5) {
- continue;
- }
- break;
- }
- // Now got pd and mfi already
- mfn = (((n_target * pd) / 2 - n_ref * mfi) * mfd) / n_ref;
+ u64 pd, mfi = 1, mfn, mfd, n_target = target, n_ref = ref, i;
+
+ // make sure targeted freq is in the valid range. Otherwise the
+ // following calculation might be wrong!!!
+ if (n_target < PLL_FREQ_MIN(ref) || n_target > PLL_FREQ_MAX(ref))
+ return ERR_WRONG_CLK;
+ for (i = 0; ; i++) {
+ if (i == REF_IN_CLK_NUM)
+ return ERR_WRONG_CLK;
+ if (fixed_mfd[i].ref_clk_hz == ref) {
+ mfd = fixed_mfd[i].mfd;
+ break;
+ }
+ }
+ // Use n_target and n_ref to avoid overflow
+ for (pd = 1; pd <= PLL_PD_MAX; pd++) {
+ mfi = (n_target * pd) / (2 * n_ref);
+ if (mfi > PLL_MFI_MAX) {
+ return ERR_NO_MFI;
+ } else if (mfi < 5) {
+ continue;
+ }
+ break;
+ }
+ // Now got pd and mfi already
+ mfn = (((n_target * pd) / 2 - n_ref * mfi) * mfd) / n_ref;
#ifdef CMD_CLOCK_DEBUG
- diag_printf("%d: ref=%d, target=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
- __LINE__, ref, (u32)n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
+ diag_printf("%d: ref=%d, target=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
+ __LINE__, ref, (u32)n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
#endif
- i = 1;
- if (mfn != 0)
- i = gcd(mfd, mfn);
- pll->pd = (u32)pd;
- pll->mfi = (u32)mfi;
- pll->mfn = (u32)(mfn / i);
- pll->mfd = (u32)(mfd / i);
- return 0;
+ i = 1;
+ if (mfn != 0)
+ i = gcd(mfd, mfn);
+ pll->pd = (u32)pd;
+ pll->mfi = (u32)mfi;
+ pll->mfn = (u32)(mfn / i);
+ pll->mfd = (u32)(mfd / i);
+ return 0;
}
/*!
* on the targeted PLL and reference input clock to the PLL. Lastly,
* it sets the register based on these values along with the dividers.
* Note 1) There is no value checking for the passed-in divider values
- * so the caller has to make sure those values are sensible.
- * 2) Also adjust the NFC divider such that the NFC clock doesn't
- * exceed NFC_CLK_MAX.
- * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
- * 177MHz for higher voltage, this function fixes the max to 133MHz.
- * 4) This function should not have allowed diag_printf() calls since
- * the serial driver has been stoped. But leave then here to allow
- * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
+ * so the caller has to make sure those values are sensible.
+ * 2) Also adjust the NFC divider such that the NFC clock doesn't
+ * exceed NFC_CLK_MAX.
+ * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
+ * 177MHz for higher voltage, this function fixes the max to 133MHz.
+ * 4) This function should not have allowed diag_printf() calls since
+ * the serial driver has been stoped. But leave then here to allow
+ * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
*
- * @param ref pll input reference clock (32KHz or 26MHz)
- * @param core_clk core clock in Hz
- * @param emi_clk emi clock in Hz
- * @param ahb_div ahb divider to divide the core clock to get ahb clock
- * (ahb_div - 1) needs to be set in the register
- * @param ipg_div ipg divider to divide the core clock to get ipg clock
- * (ipg_div - 1) needs to be set in the register
- # @return 0 if successful; non-zero otherwise
+ * @param ref pll input reference clock (32KHz or 26MHz)
+ * @param core_clk core clock in Hz
+ * @param emi_clk emi clock in Hz
+ * @param ahb_div ahb divider to divide the core clock to get ahb clock
+ * (ahb_div - 1) needs to be set in the register
+ * @param ipg_div ipg divider to divide the core clock to get ipg clock
+ * (ipg_div - 1) needs to be set in the register
+ # @return 0 if successful; non-zero otherwise
*/
int configure_clock(u32 ref, u32 core_clk, u32 emi_clk, u32 ahb_div, u32 ipg_div)
{
#if 0
- u32 pll, arm_div = 1, emi_div = 0, nfc_div, ascsr, acdr, acder2;
- struct pll_param pll_param;
- int ret;
-
- // assume pll default to core clock first
- pll = core_clk;
- // when core_clk >= PLL_FREQ_MIN, the presc can be 1.
- // Otherwise, need to calculate presc value below and adjust the targeted pll
- if (core_clk < PLL_FREQ_MIN) {
- for (presc = 1; presc <= PRESC_MAX; presc++) {
- if ((core_clk * presc) > PLL_FREQ_MIN) {
- break;
- }
- }
- if (presc == (PRESC_MAX + 1)) {
- diag_printf("can't make presc=%d\n", presc);
- return ERR_NO_PRESC;
- }
- pll = core_clk * presc;
- }
- // get hsp_div
- for (hsp_div = 1; hsp_div <= HSP_PODF_MAX; hsp_div++) {
- if ((pll / hsp_div) <= HSP_CLK_MAX) {
- break;
- }
- }
- if (hsp_div == (HSP_PODF_MAX + 1)) {
- diag_printf("can't make hsp_div=%d\n", hsp_div);
- return ERR_NO_PRESC;
- }
-
- // get nfc_div - make sure optimal NFC clock but less than NFC_CLK_MAX
- for (nfc_div = 1; nfc_div <= NFC_PODF_MAX; nfc_div++) {
- if ((pll / (ahb_div * nfc_div)) <= NFC_CLK_MAX) {
- break;
- }
- }
-
- // pll is now the targeted pll output. Use it along with ref input clock
- // to get pd, mfi, mfn, mfd
- if ((ret = calc_pll_params(ref, pll, &pd, &mfi, &mfn, &mfd)) != 0) {
- diag_printf("can't find pll parameters: %d\n", ret);
- return ret;
- }
+ u32 pll, arm_div = 1, emi_div = 0, nfc_div, ascsr, acdr, acder2;
+ struct pll_param pll_param;
+ int ret;
+
+ // assume pll default to core clock first
+ pll = core_clk;
+ // when core_clk >= PLL_FREQ_MIN, the presc can be 1.
+ // Otherwise, need to calculate presc value below and adjust the targeted pll
+ if (core_clk < PLL_FREQ_MIN) {
+ for (presc = 1; presc <= PRESC_MAX; presc++) {
+ if ((core_clk * presc) > PLL_FREQ_MIN) {
+ break;
+ }
+ }
+ if (presc == (PRESC_MAX + 1)) {
+ diag_printf("can't make presc=%d\n", presc);
+ return ERR_NO_PRESC;
+ }
+ pll = core_clk * presc;
+ }
+ // get hsp_div
+ for (hsp_div = 1; hsp_div <= HSP_PODF_MAX; hsp_div++) {
+ if ((pll / hsp_div) <= HSP_CLK_MAX) {
+ break;
+ }
+ }
+ if (hsp_div == (HSP_PODF_MAX + 1)) {
+ diag_printf("can't make hsp_div=%d\n", hsp_div);
+ return ERR_NO_PRESC;
+ }
+
+ // get nfc_div - make sure optimal NFC clock but less than NFC_CLK_MAX
+ for (nfc_div = 1; nfc_div <= NFC_PODF_MAX; nfc_div++) {
+ if ((pll / (ahb_div * nfc_div)) <= NFC_CLK_MAX) {
+ break;
+ }
+ }
+
+ // pll is now the targeted pll output. Use it along with ref input clock
+ // to get pd, mfi, mfn, mfd
+ if ((ret = calc_pll_params(ref, pll, &pd, &mfi, &mfn, &mfd)) != 0) {
+ diag_printf("can't find pll parameters: %d\n", ret);
+ return ret;
+ }
#ifdef CMD_CLOCK_DEBUG
- diag_printf("ref=%d, pll=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
- ref, pll, pd, mfi, mfn, mfd);
+ diag_printf("ref=%d, pll=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
+ ref, pll, pd, mfi, mfn, mfd);
#endif
- // blindly increase divider first to avoid too fast ahbclk and ipgclk
- // in case the core clock increases too much
- pdr0 = readl(CCM_BASE_ADDR + CLKCTL_PDR0);
- pdr0 &= ~0x000000FF;
- // increase the dividers. should work even when core clock is 832 (26*2*16)MHz
- // which is unlikely true.
- pdr0 |= (1 << 6) | (6 << 3) | (0 << 0);
- writel(pdr0, CCM_BASE_ADDR + CLKCTL_PDR0);
- // calculate new pdr0
- pdr0 &= ~0x00003FFF;
- pdr0 |= ((hsp_div - 1) << 11) | ((nfc_div - 1) << 8) | ((ipg_div - 1) << 6) |
- ((ahb_div - 1) << 3) | ((presc - 1) << 0);
-
- // update PLL register
- if ((mfd >= (10 * mfn)) || ((10 * mfn) >= (9 * mfd)))
- brmo = 1;
-
- mpctl0 = readl(CCM_BASE_ADDR + CLKCTL_MPCTL);
- mpctl0 = (mpctl0 & 0x4000C000) |
- (brmo << 31) |
- ((pd - 1) << 26) |
- ((mfd - 1) << 16) |
- (mfi << 10) |
- mfn;
- writel(mpctl0, CCM_BASE_ADDR + CLKCTL_MPCTL);
- writel(pdr0, CCM_BASE_ADDR + CLKCTL_PDR0);
- // add some delay for new values to take effect
- for (i = 0; i < 10000; i++);
+ // blindly increase divider first to avoid too fast ahbclk and ipgclk
+ // in case the core clock increases too much
+ pdr0 = readl(CCM_BASE_ADDR + CLKCTL_PDR0);
+ pdr0 &= ~0x000000FF;
+ // increase the dividers. should work even when core clock is 832 (26*2*16)MHz
+ // which is unlikely true.
+ pdr0 |= (1 << 6) | (6 << 3) | (0 << 0);
+ writel(pdr0, CCM_BASE_ADDR + CLKCTL_PDR0);
+ // calculate new pdr0
+ pdr0 &= ~0x00003FFF;
+ pdr0 |= ((hsp_div - 1) << 11) | ((nfc_div - 1) << 8) | ((ipg_div - 1) << 6) |
+ ((ahb_div - 1) << 3) | ((presc - 1) << 0);
+
+ // update PLL register
+ if ((mfd >= (10 * mfn)) || ((10 * mfn) >= (9 * mfd)))
+ brmo = 1;
+
+ mpctl0 = readl(CCM_BASE_ADDR + CLKCTL_MPCTL);
+ mpctl0 = (mpctl0 & 0x4000C000) |
+ (brmo << 31) |
+ ((pd - 1) << 26) |
+ ((mfd - 1) << 16) |
+ (mfi << 10) |
+ mfn;
+ writel(mpctl0, CCM_BASE_ADDR + CLKCTL_MPCTL);
+ writel(pdr0, CCM_BASE_ADDR + CLKCTL_PDR0);
+ // add some delay for new values to take effect
+ for (i = 0; i < 10000; i++);
#endif
- return 0;
+ return 0;
}
static void clock_setup(int argc,char *argv[])
{
#if 0
- u32 i, core_clk, ipg_div, data[3], temp, ahb_div, ahb_clk, ipg_clk;
- int ret;
-
- if (argc == 1)
- goto print_clock;
-
- for (i = 0; i < 3; i++) {
- if (!parse_num(*(&argv[1]), (unsigned long *)&temp, &argv[1], ":")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
- data[i] = temp;
- }
-
- core_clk = data[0] * SZ_DEC_1M;
- ahb_div = data[1]; // actual register field + 1
- ipg_div = data[2]; // actual register field + 1
-
- if (core_clk < (PLL_FREQ_MIN / PRESC_MAX) || core_clk > PLL_FREQ_MAX) {
- diag_printf("Targeted core clock should be within [%d - %d]\n",
- PLL_FREQ_MIN / PRESC_MAX, PLL_FREQ_MAX);
- return;
- }
-
- // find the ahb divider
- if (ahb_div > AHB_DIV_MAX) {
- diag_printf("Invalid AHB divider: %d. Maximum value is %d\n",
- ahb_div, AHB_DIV_MAX);
- return;
- }
- if (ahb_div == 0) {
- // no HCLK divider specified
- for (ahb_div = 1; ; ahb_div++) {
- if ((core_clk / ahb_div) <= AHB_CLK_MAX) {
- break;
- }
- }
- }
- if (ahb_div > AHB_DIV_MAX || (core_clk / ahb_div) > AHB_CLK_MAX) {
- diag_printf("Can't make AHB=%d since max=%d\n",
- core_clk / ahb_div, AHB_CLK_MAX);
- return;
- }
-
- // find the ipg divider
- ahb_clk = core_clk / ahb_div;
- if (ipg_div > IPG_DIV_MAX) {
- diag_printf("Invalid IPG divider: %d. Maximum value is %d\n",
- ipg_div, IPG_DIV_MAX);
- return;
- }
- if (ipg_div == 0) {
- ipg_div++; // At least =1
- if (ahb_clk > IPG_CLK_MAX)
- ipg_div++; // Make it =2
- }
- if (ipg_div > IPG_DIV_MAX || (ahb_clk / ipg_div) > IPG_CLK_MAX) {
- diag_printf("Can't make IPG=%d since max=%d\n",
- (ahb_clk / ipg_div), IPG_CLK_MAX);
- return;
- }
- ipg_clk = ahb_clk / ipg_div;
-
- diag_printf("Trying to set core=%d ahb=%d ipg=%d...\n",
- core_clk, ahb_clk, ipg_clk);
-
- // stop the serial to be ready to adjust the clock
- hal_delay_us(100000);
- cyg_hal_plf_serial_stop();
- // adjust the clock
- ret = configure_clock(PLL_REF_CLK, core_clk, ahb_div, ipg_div);
- // restart the serial driver
- cyg_hal_plf_serial_init();
- hal_delay_us(100000);
-
- if (ret != 0) {
- diag_printf("Failed to setup clock: %d\n", ret);
- return;
- }
- diag_printf("\n<<<New clock setting>>>\n");
-
- // Now printing clocks
+ u32 i, core_clk, ipg_div, data[3], temp, ahb_div, ahb_clk, ipg_clk;
+ int ret;
+
+ if (argc == 1)
+ goto print_clock;
+
+ for (i = 0; i < 3; i++) {
+ if (!parse_num(argv[1], &temp, &argv[1], ":")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ data[i] = temp;
+ }
+
+ core_clk = data[0] * SZ_DEC_1M;
+ ahb_div = data[1]; // actual register field + 1
+ ipg_div = data[2]; // actual register field + 1
+
+ if (core_clk < (PLL_FREQ_MIN / PRESC_MAX) || core_clk > PLL_FREQ_MAX) {
+ diag_printf("Targeted core clock should be within [%d - %d]\n",
+ PLL_FREQ_MIN / PRESC_MAX, PLL_FREQ_MAX);
+ return;
+ }
+
+ // find the ahb divider
+ if (ahb_div > AHB_DIV_MAX) {
+ diag_printf("Invalid AHB divider: %d. Maximum value is %d\n",
+ ahb_div, AHB_DIV_MAX);
+ return;
+ }
+ if (ahb_div == 0) {
+ // no HCLK divider specified
+ for (ahb_div = 1; ; ahb_div++) {
+ if ((core_clk / ahb_div) <= AHB_CLK_MAX) {
+ break;
+ }
+ }
+ }
+ if (ahb_div > AHB_DIV_MAX || (core_clk / ahb_div) > AHB_CLK_MAX) {
+ diag_printf("Can't make AHB=%d since max=%d\n",
+ core_clk / ahb_div, AHB_CLK_MAX);
+ return;
+ }
+
+ // find the ipg divider
+ ahb_clk = core_clk / ahb_div;
+ if (ipg_div > IPG_DIV_MAX) {
+ diag_printf("Invalid IPG divider: %d. Maximum value is %d\n",
+ ipg_div, IPG_DIV_MAX);
+ return;
+ }
+ if (ipg_div == 0) {
+ ipg_div++; // At least =1
+ if (ahb_clk > IPG_CLK_MAX)
+ ipg_div++; // Make it =2
+ }
+ if (ipg_div > IPG_DIV_MAX || (ahb_clk / ipg_div) > IPG_CLK_MAX) {
+ diag_printf("Can't make IPG=%d since max=%d\n",
+ (ahb_clk / ipg_div), IPG_CLK_MAX);
+ return;
+ }
+ ipg_clk = ahb_clk / ipg_div;
+
+ diag_printf("Trying to set core=%d ahb=%d ipg=%d...\n",
+ core_clk, ahb_clk, ipg_clk);
+
+ // stop the serial to be ready to adjust the clock
+ hal_delay_us(100000);
+ cyg_hal_plf_serial_stop();
+ // adjust the clock
+ ret = configure_clock(PLL_REF_CLK, core_clk, ahb_div, ipg_div);
+ // restart the serial driver
+ cyg_hal_plf_serial_init();
+ hal_delay_us(100000);
+
+ if (ret != 0) {
+ diag_printf("Failed to setup clock: %d\n", ret);
+ return;
+ }
+ diag_printf("\n<<<New clock setting>>>\n");
+
+ // Now printing clocks
print_clock:
#endif
- diag_printf("\nPLL1\t\tPLL2\t\tPLL3\n");
- diag_printf("========================================\n");
- diag_printf("%-16d%-16d%-16d\n\n", pll_clock(PLL1), pll_clock(PLL2),
- pll_clock(PLL3));
- diag_printf("CPU\t\tAHB\t\tIPG\t\tEMI_CLK\n");
- diag_printf("========================================================\n");
- diag_printf("%-16d%-16d%-16d%-16d\n\n",
- get_main_clock(CPU_CLK),
- get_main_clock(AHB_CLK),
- get_main_clock(IPG_CLK),
- get_main_clock(DDR_CLK));
-
- diag_printf("NFC\t\tUSB\n");
- diag_printf("========================================\n");
- diag_printf("%-16d%-16d\n\n",
- get_main_clock(NFC_CLK),
- get_main_clock(USB_CLK));
-
- diag_printf("UART1-3\t\tSSI1\t\tSSI2\t\tCSI\n");
- diag_printf("===========================================");
- diag_printf("=============\n");
-
- diag_printf("%-16d%-16d%-16d%-16d\n\n",
- get_peri_clock(UART1_BAUD),
- get_peri_clock(SSI1_BAUD),
- get_peri_clock(SSI2_BAUD),
- get_peri_clock(CSI_BAUD));
-
- diag_printf("MSTICK1\t\tMSTICK2\t\tSPI\n");
- diag_printf("===========================================");
- diag_printf("=============\n");
-
- diag_printf("%-16d%-16d%-16d\n\n",
- get_peri_clock(MSTICK1_CLK),
- get_peri_clock(MSTICK2_CLK),
- get_peri_clock(SPI1_CLK));
+ diag_printf("\nPLL1\t\tPLL2\t\tPLL3\n");
+ diag_printf("========================================\n");
+ diag_printf("%-16d%-16d%-16d\n\n", pll_clock(PLL1), pll_clock(PLL2),
+ pll_clock(PLL3));
+ diag_printf("CPU\t\tAHB\t\tIPG\t\tEMI_CLK\n");
+ diag_printf("========================================================\n");
+ diag_printf("%-16d%-16d%-16d%-16d\n\n",
+ get_main_clock(CPU_CLK),
+ get_main_clock(AHB_CLK),
+ get_main_clock(IPG_CLK),
+ get_main_clock(DDR_CLK));
+
+ diag_printf("NFC\t\tUSB\n");
+ diag_printf("========================================\n");
+ diag_printf("%-16d%-16d\n\n",
+ get_main_clock(NFC_CLK),
+ get_main_clock(USB_CLK));
+
+ diag_printf("UART1-3\t\tSSI1\t\tSSI2\t\tCSI\n");
+ diag_printf("===========================================");
+ diag_printf("=============\n");
+
+ diag_printf("%-16d%-16d%-16d%-16d\n\n",
+ get_peri_clock(UART1_BAUD),
+ get_peri_clock(SSI1_BAUD),
+ get_peri_clock(SSI2_BAUD),
+ get_peri_clock(CSI_BAUD));
+
+ diag_printf("MSTICK1\t\tMSTICK2\t\tSPI\n");
+ diag_printf("===========================================");
+ diag_printf("=============\n");
+
+ diag_printf("%-16d%-16d%-16d\n\n",
+ get_peri_clock(MSTICK1_CLK),
+ get_peri_clock(MSTICK2_CLK),
+ get_peri_clock(SPI1_CLK));
#if 0
- diag_printf("IPG_PERCLK as baud clock for: UART1-5, I2C, OWIRE, SDHC");
- if (((readl(EPIT1_BASE_ADDR) >> 24) & 0x3) == 0x2) {
- diag_printf(", EPIT");
- }
- if (((readl(GPT1_BASE_ADDR) >> 6) & 0x7) == 0x2) {
- diag_printf("GPT,");
- }
+ diag_printf("IPG_PERCLK as baud clock for: UART1-5, I2C, OWIRE, SDHC");
+ if (((readl(EPIT1_BASE_ADDR) >> 24) & 0x3) == 0x2) {
+ diag_printf(", EPIT");
+ }
+ if (((readl(GPT1_BASE_ADDR) >> 6) & 0x7) == 0x2) {
+ diag_printf("GPT,");
+ }
#endif
- diag_printf("\n");
+ diag_printf("\n");
}
*/
u32 pll_clock(enum plls pll)
{
- u64 mfi, mfn, mfd, pdf, ref_clk, pll_out, sign;
- u64 dp_ctrl, dp_op, dp_mfd, dp_mfn, clk_sel;
- u8 dbl = 0;
-
- dp_ctrl = pll_base[pll][PLL_DP_CTL >> 2];
- clk_sel = MXC_GET_FIELD(dp_ctrl, 2, 8);
- ref_clk = fixed_mfd[clk_sel].ref_clk_hz;
-
- if ((pll_base[pll][PLL_DP_CTL >> 2] & 0x80) == 0) {
- dp_op = pll_base[pll][PLL_DP_OP >> 2];
- dp_mfd = pll_base[pll][PLL_DP_MFD >> 2];
- dp_mfn = pll_base[pll][PLL_DP_MFN >> 2];
- } else {
- dp_op = pll_base[pll][PLL_DP_HFS_OP >> 2];
- dp_mfd = pll_base[pll][PLL_DP_HFS_MFD >> 2];
- dp_mfn = pll_base[pll][PLL_DP_HFS_MFN >> 2];
- }
- pdf = dp_op & 0xF;
- mfi = (dp_op >> 4) & 0xF;
- mfi = (mfi <= 5) ? 5: mfi;
- mfd = dp_mfd & 0x07FFFFFF;
- mfn = dp_mfn & 0x07FFFFFF;
-
- sign = (mfn < 0x4000000) ? 0: 1;
- mfn = (mfn <= 0x4000000) ? mfn: (0x8000000 - mfn);
-
- dbl = ((dp_ctrl >> 12) & 0x1) + 1;
-
- dbl = dbl * 2;
- if (sign == 0) {
- pll_out = (dbl * ref_clk * mfi + ((dbl * ref_clk * mfn) / (mfd + 1))) /
- (pdf + 1);
- } else {
- pll_out = (dbl * ref_clk * mfi - ((dbl * ref_clk * mfn) / (mfd + 1))) /
- (pdf + 1);
- }
-
- return (u32)pll_out;
+ u64 mfi, mfn, mfd, pdf, ref_clk, pll_out, sign;
+ u64 dp_ctrl, dp_op, dp_mfd, dp_mfn, clk_sel;
+ u8 dbl = 0;
+
+ dp_ctrl = pll_base[pll][PLL_DP_CTL >> 2];
+ clk_sel = MXC_GET_FIELD(dp_ctrl, 2, 8);
+ ref_clk = fixed_mfd[clk_sel].ref_clk_hz;
+
+ if ((pll_base[pll][PLL_DP_CTL >> 2] & 0x80) == 0) {
+ dp_op = pll_base[pll][PLL_DP_OP >> 2];
+ dp_mfd = pll_base[pll][PLL_DP_MFD >> 2];
+ dp_mfn = pll_base[pll][PLL_DP_MFN >> 2];
+ } else {
+ dp_op = pll_base[pll][PLL_DP_HFS_OP >> 2];
+ dp_mfd = pll_base[pll][PLL_DP_HFS_MFD >> 2];
+ dp_mfn = pll_base[pll][PLL_DP_HFS_MFN >> 2];
+ }
+ pdf = dp_op & 0xF;
+ mfi = (dp_op >> 4) & 0xF;
+ mfi = (mfi <= 5) ? 5: mfi;
+ mfd = dp_mfd & 0x07FFFFFF;
+ mfn = dp_mfn & 0x07FFFFFF;
+
+ sign = (mfn < 0x4000000) ? 0: 1;
+ mfn = (mfn <= 0x4000000) ? mfn: (0x8000000 - mfn);
+
+ dbl = ((dp_ctrl >> 12) & 0x1) + 1;
+
+ dbl = dbl * 2;
+ if (sign == 0) {
+ pll_out = (dbl * ref_clk * mfi + ((dbl * ref_clk * mfn) / (mfd + 1))) /
+ (pdf + 1);
+ } else {
+ pll_out = (dbl * ref_clk * mfi - ((dbl * ref_clk * mfn) / (mfd + 1))) /
+ (pdf + 1);
+ }
+
+ return (u32)pll_out;
}
// The clocks are on by default. But need to setup the IOMUX
void clock_spi_enable(unsigned int spi_clk)
{
- // Take care of SPI2
- writel(0x0, IOMUXC_BASE_ADDR + 0x14C);
- writel(0x1, IOMUXC_BASE_ADDR + 0x3AC);
- writel(0x100, IOMUXC_BASE_ADDR + 0x494);
- writel(0x0, IOMUXC_BASE_ADDR + 0x148);
- writel(0x1, IOMUXC_BASE_ADDR + 0x3A8);
- writel(0x3, IOMUXC_BASE_ADDR + 0x168);
- writel(0x180, IOMUXC_BASE_ADDR + 0x3C8);
- writel(0x0, IOMUXC_BASE_ADDR + 0x158);
- writel(0x101, IOMUXC_BASE_ADDR + 0x3B8);
- writel(0x0, IOMUXC_BASE_ADDR + 0x150);
- writel(0x1, IOMUXC_BASE_ADDR + 0x3B0);
- writel(0x100, IOMUXC_BASE_ADDR + 0x490);
+ // Take care of SPI2
+ writel(0x0, IOMUXC_BASE_ADDR + 0x14C);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x3AC);
+ writel(0x100, IOMUXC_BASE_ADDR + 0x494);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x148);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x3A8);
+ writel(0x3, IOMUXC_BASE_ADDR + 0x168);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x3C8);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x158);
+ writel(0x101, IOMUXC_BASE_ADDR + 0x3B8);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x150);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x3B0);
+ writel(0x100, IOMUXC_BASE_ADDR + 0x490);
}
/*!
*/
u32 get_lp_apm(void)
{
- u32 ret_val = 0;
- u32 ccsr = readl(CCM_BASE_ADDR + CLKCTL_CCSR);
-
- if (((ccsr >> 9) & 1) == 0) {
- ret_val = FREQ_24MHZ;
- } else {
- ret_val = FREQ_32000HZ;
- }
- return ret_val;
+ u32 ret_val = 0;
+ u32 ccsr = readl(CCM_BASE_ADDR + CLKCTL_CCSR);
+
+ if (((ccsr >> 9) & 1) == 0) {
+ ret_val = FREQ_24MHZ;
+ } else {
+ ret_val = FREQ_32000HZ;
+ }
+ return ret_val;
}
/*!
*/
u32 get_periph_clk(void)
{
- u32 cbcdr6 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR6);
- u32 camr = readl(CCM_BASE_ADDR + CLKCTL_CAMR);
- u32 ret_val = 0, clk_sel;
-
- if (((cbcdr6 >> 4) & 1) == 0) {
- ret_val = pll_clock(PLL2);
- } else {
- clk_sel = (camr >> 12) & 3;
- if (clk_sel == 0) {
- ret_val = pll_clock(PLL1);
- } else if (clk_sel == 1) {
- ret_val = pll_clock(PLL3);
- } else if (clk_sel == 2) {
- ret_val = get_lp_apm();
- }
- }
-
- return ret_val;
+ u32 cbcdr6 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR6);
+ u32 camr = readl(CCM_BASE_ADDR + CLKCTL_CAMR);
+ u32 ret_val = 0, clk_sel;
+
+ if (((cbcdr6 >> 4) & 1) == 0) {
+ ret_val = pll_clock(PLL2);
+ } else {
+ clk_sel = (camr >> 12) & 3;
+ if (clk_sel == 0) {
+ ret_val = pll_clock(PLL1);
+ } else if (clk_sel == 1) {
+ ret_val = pll_clock(PLL3);
+ } else if (clk_sel == 2) {
+ ret_val = get_lp_apm();
+ }
+ }
+
+ return ret_val;
}
/*!
*/
u32 get_emi_core_clk(void)
{
- u32 cbcdr6 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR6);
- u32 cbcdr2 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR2);
- u32 clk_sel = 0, pdf = 0, max_pdf = 0, peri_clk = 0, ahb_clk = 0;
- u32 ret_val = 0;
-
- max_pdf = (cbcdr2 >> 10) & 0x7;
- peri_clk = get_periph_clk();
- ahb_clk = peri_clk / (max_pdf + 1);
-
- pdf = cbcdr6 & 0x7;
- clk_sel = (cbcdr6 >> 3) & 1;
- if (clk_sel == 0) {
- ret_val = peri_clk / (pdf + 1);
- } else {
- ret_val = ahb_clk / (pdf + 1);
- }
- return ret_val;
+ u32 cbcdr6 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR6);
+ u32 cbcdr2 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR2);
+ u32 clk_sel = 0, pdf = 0, max_pdf = 0, peri_clk = 0, ahb_clk = 0;
+ u32 ret_val = 0;
+
+ max_pdf = (cbcdr2 >> 10) & 0x7;
+ peri_clk = get_periph_clk();
+ ahb_clk = peri_clk / (max_pdf + 1);
+
+ pdf = cbcdr6 & 0x7;
+ clk_sel = (cbcdr6 >> 3) & 1;
+ if (clk_sel == 0) {
+ ret_val = peri_clk / (pdf + 1);
+ } else {
+ ret_val = ahb_clk / (pdf + 1);
+ }
+ return ret_val;
}
// The clocks are on by default. But need to setup the IOMUX
void mxc_i2c_init(unsigned int module_base)
{
- unsigned int val, reg;
-
- switch (module_base) {
- case I2C_BASE_ADDR:
- writel(0x0, IOMUXC_BASE_ADDR + 0x104);
- writel(0x1, IOMUXC_BASE_ADDR + 0x5C0);
- writel(0xA8, IOMUXC_BASE_ADDR + 0x364);
-
- writel(0x0, IOMUXC_BASE_ADDR + 0x108);
- writel(0x1, IOMUXC_BASE_ADDR + 0x5C4);
- writel(0xA8, IOMUXC_BASE_ADDR + 0x368);
-
- writel(0x100, IOMUXC_BASE_ADDR + 0x4D0);
- break;
- case I2C2_BASE_ADDR:
- // i2c SCL
- writel(0x2, IOMUXC_BASE_ADDR + 0x210);
- writel(0x1EC, IOMUXC_BASE_ADDR + 0x468);
- writel(0x1, IOMUXC_BASE_ADDR + 0x5C8);
- // i2c SDA
- writel(0x2, IOMUXC_BASE_ADDR + 0x214);
- writel(0x1EC, IOMUXC_BASE_ADDR + 0x46C);
- writel(0x1, IOMUXC_BASE_ADDR + 0x5CC);
- break;
- case I2C3_BASE_ADDR:
- reg = IOMUXC_BASE_ADDR + 0x84;
- val = (readl(reg) & 0xFFFFFF00) | 0x24; // alt mode 1
- writel(val, reg);
- reg = IOMUXC_BASE_ADDR + 0x80;
- val = (readl(reg) & 0x00FFFFFF) | 0x24000000; // alt mode 1
- writel(val, reg);
- break;
- default:
- diag_printf("Invalid I2C base: 0x%x\n", module_base);
- return;
- }
+ unsigned int val, reg;
+
+ switch (module_base) {
+ case I2C_BASE_ADDR:
+ writel(0x0, IOMUXC_BASE_ADDR + 0x104);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x5C0);
+ writel(0xA8, IOMUXC_BASE_ADDR + 0x364);
+
+ writel(0x0, IOMUXC_BASE_ADDR + 0x108);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x5C4);
+ writel(0xA8, IOMUXC_BASE_ADDR + 0x368);
+
+ writel(0x100, IOMUXC_BASE_ADDR + 0x4D0);
+ break;
+ case I2C2_BASE_ADDR:
+ // i2c SCL
+ writel(0x2, IOMUXC_BASE_ADDR + 0x210);
+ writel(0x1EC, IOMUXC_BASE_ADDR + 0x468);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x5C8);
+ // i2c SDA
+ writel(0x2, IOMUXC_BASE_ADDR + 0x214);
+ writel(0x1EC, IOMUXC_BASE_ADDR + 0x46C);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x5CC);
+ break;
+ case I2C3_BASE_ADDR:
+ reg = IOMUXC_BASE_ADDR + 0x84;
+ val = (readl(reg) & 0xFFFFFF00) | 0x24; // alt mode 1
+ writel(val, reg);
+ reg = IOMUXC_BASE_ADDR + 0x80;
+ val = (readl(reg) & 0x00FFFFFF) | 0x24000000; // alt mode 1
+ writel(val, reg);
+ break;
+ default:
+ diag_printf("Invalid I2C base: 0x%x\n", module_base);
+ return;
+ }
}
/*!
*/
u32 get_main_clock(enum main_clocks clk)
{
- u32 mcu_podf, max_pdf, ipg_pdf, nfc_pdf, clk_sel;
- u32 pll, ret_val = 0;
- u32 cacrr = readl(CCM_BASE_ADDR + CLKCTL_CACRR);
- u32 cbcdr2 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR2);
- u32 cbcdr3 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR3);
- u32 cbcdr4 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR4);
- u32 cbcdr5 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR5);
- u32 cbcdr7 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR7);
- u32 camr = readl(CCM_BASE_ADDR + CLKCTL_CAMR);
-
- switch (clk) {
- case CPU_CLK:
- mcu_podf = cacrr & 0x7;
- pll = pll_clock(PLL1);
- ret_val = pll / (mcu_podf + 1);
- break;
- case AHB_CLK:
- max_pdf = (cbcdr2 >> 10) & 0x7;
- pll = get_periph_clk();
- ret_val = pll / (max_pdf + 1);
- break;
- case IPG_CLK:
- max_pdf = (cbcdr2 >> 10) & 0x7;
- ipg_pdf = (cbcdr2 >> 8) & 0x3;
- pll = get_periph_clk();
- ret_val = pll / ((max_pdf + 1) * (ipg_pdf + 1));
- break;
- case IPG_PER_CLK:
+ u32 mcu_podf, max_pdf, ipg_pdf, nfc_pdf, clk_sel;
+ u32 pll, ret_val = 0;
+ u32 cacrr = readl(CCM_BASE_ADDR + CLKCTL_CACRR);
+ u32 cbcdr2 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR2);
+ u32 cbcdr3 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR3);
+ u32 cbcdr4 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR4);
+ u32 cbcdr5 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR5);
+ u32 cbcdr7 = readl(CCM_BASE_ADDR + CLKCTL_CBCDR7);
+ u32 camr = readl(CCM_BASE_ADDR + CLKCTL_CAMR);
+
+ switch (clk) {
+ case CPU_CLK:
+ mcu_podf = cacrr & 0x7;
+ pll = pll_clock(PLL1);
+ ret_val = pll / (mcu_podf + 1);
+ break;
+ case AHB_CLK:
+ max_pdf = (cbcdr2 >> 10) & 0x7;
+ pll = get_periph_clk();
+ ret_val = pll / (max_pdf + 1);
+ break;
+ case IPG_CLK:
+ max_pdf = (cbcdr2 >> 10) & 0x7;
+ ipg_pdf = (cbcdr2 >> 8) & 0x3;
+ pll = get_periph_clk();
+ ret_val = pll / ((max_pdf + 1) * (ipg_pdf + 1));
+ break;
+ case IPG_PER_CLK:
#if 0
- clk_sel = ccmr & (1 << 24);
- pdf = (mpdr0 >> 16) & 0x1F;
- if (clk_sel != 0) {
- // get the ipg_clk
- max_pdf = (reg >> 3) & 0x7;
- ipg_pdf = (reg >> 6) & 0x3;
- pll = pll_clock(PLL1);
- ret_val = pll / ((max_pdf + 1) * (ipg_pdf + 1));
- } else {
- ret_val = pll_clock(PLL2) / (pdf + 1);
- }
+ clk_sel = ccmr & (1 << 24);
+ pdf = (mpdr0 >> 16) & 0x1F;
+ if (clk_sel != 0) {
+ // get the ipg_clk
+ max_pdf = (reg >> 3) & 0x7;
+ ipg_pdf = (reg >> 6) & 0x3;
+ pll = pll_clock(PLL1);
+ ret_val = pll / ((max_pdf + 1) * (ipg_pdf + 1));
+ } else {
+ ret_val = pll_clock(PLL2) / (pdf + 1);
+ }
#endif
- break;
- case DDR_CLK:
- clk_sel = (camr >> 10) & 3;
- if (clk_sel == 0) {
- ret_val = get_periph_clk() / ((cbcdr3 & 7) + 1);
- } else if (clk_sel == 1) {
- ret_val = get_periph_clk() / ((cbcdr4 & 7) + 1);
- } else if (clk_sel == 2) {
- ret_val = get_periph_clk() / ((cbcdr5 & 7) + 1);
- } else if (clk_sel == 3) {
- ret_val = get_emi_core_clk();
- }
- break;
- case NFC_CLK:
- nfc_pdf = cbcdr7 & 0x7;
- pll = get_emi_core_clk();
- /* AHB/nfc_pdf */
- ret_val = pll / (nfc_pdf + 1);
- break;
- case USB_CLK:
+ break;
+ case DDR_CLK:
+ clk_sel = (camr >> 10) & 3;
+ if (clk_sel == 0) {
+ ret_val = get_periph_clk() / ((cbcdr3 & 7) + 1);
+ } else if (clk_sel == 1) {
+ ret_val = get_periph_clk() / ((cbcdr4 & 7) + 1);
+ } else if (clk_sel == 2) {
+ ret_val = get_periph_clk() / ((cbcdr5 & 7) + 1);
+ } else if (clk_sel == 3) {
+ ret_val = get_emi_core_clk();
+ }
+ break;
+ case NFC_CLK:
+ nfc_pdf = cbcdr7 & 0x7;
+ pll = get_emi_core_clk();
+ /* AHB/nfc_pdf */
+ ret_val = pll / (nfc_pdf + 1);
+ break;
+ case USB_CLK:
#if 0
- usb_prdf = reg1 >> 30;
- usb_podf = (reg1 >> 27) & 0x7;
- pll = pll_clock(PLL2);
- ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1));
+ usb_prdf = reg1 >> 30;
+ usb_podf = (reg1 >> 27) & 0x7;
+ pll = pll_clock(PLL2);
+ ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1));
#endif
- break;
- default:
- diag_printf("Unknown clock: %d\n", clk);
- break;
- }
+ break;
+ default:
+ diag_printf("Unknown clock: %d\n", clk);
+ break;
+ }
- return ret_val;
+ return ret_val;
}
/*!
*/
u32 get_peri_clock(enum peri_clocks clk)
{
- u32 ret_val = 0, pdf, pre_pdf, clk_sel;
- u32 cscmr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCMR1);
- u32 cscdr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCDR1);
- u32 cscdr2 = readl(CCM_BASE_ADDR + CLKCTL_CSCDR2);
- u32 cs1cdr = readl(CCM_BASE_ADDR + CLKCTL_CS1CDR);
- u32 cs2cdr = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);
-
- switch (clk) {
- case UART1_BAUD:
- case UART2_BAUD:
- case UART3_BAUD:
- pre_pdf = (cscdr1 >> 3) & 0x7;
- pdf = cscdr1 & 0x7;
- clk_sel = (cscmr1 >> 24) & 3;
- if (clk_sel == 0) {
- ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
- } else if (clk_sel == 1) {
- ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
- } else if (clk_sel == 2) {
- ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
- }
- break;
- case SSI1_BAUD:
- pre_pdf = (cs1cdr >> 6) & 0x7;
- pdf = cs1cdr & 0x3F;
- clk_sel = (cscmr1 >> 14) & 3;
- if (clk_sel == 0) {
- ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
- } else if (clk_sel == 0x1) {
- ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
- } else if (clk_sel == 0x2) {
- ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
- } else {
- diag_printf("Error: Use reserved value for SSI1!\n");
- ret_val = 0;
- }
- break;
- case SSI2_BAUD:
- pre_pdf = (cs2cdr >> 6) & 0x7;
- pdf = cs2cdr & 0x3F;
- clk_sel = (cscmr1 >> 12) & 3;
- if (clk_sel == 0) {
- ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
- } else if (clk_sel == 0x1) {
- ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
- } else if (clk_sel == 0x2) {
- ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
- } else {
- diag_printf("Error: Use reserved value for SSI2!\n");
- ret_val = 0;
- }
- break;
- case CSI_BAUD:
+ u32 ret_val = 0, pdf, pre_pdf, clk_sel;
+ u32 cscmr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCMR1);
+ u32 cscdr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCDR1);
+ u32 cscdr2 = readl(CCM_BASE_ADDR + CLKCTL_CSCDR2);
+ u32 cs1cdr = readl(CCM_BASE_ADDR + CLKCTL_CS1CDR);
+ u32 cs2cdr = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);
+
+ switch (clk) {
+ case UART1_BAUD:
+ case UART2_BAUD:
+ case UART3_BAUD:
+ pre_pdf = (cscdr1 >> 3) & 0x7;
+ pdf = cscdr1 & 0x7;
+ clk_sel = (cscmr1 >> 24) & 3;
+ if (clk_sel == 0) {
+ ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 1) {
+ ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 2) {
+ ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
+ }
+ break;
+ case SSI1_BAUD:
+ pre_pdf = (cs1cdr >> 6) & 0x7;
+ pdf = cs1cdr & 0x3F;
+ clk_sel = (cscmr1 >> 14) & 3;
+ if (clk_sel == 0) {
+ ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 0x1) {
+ ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 0x2) {
+ ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
+ } else {
+ diag_printf("Error: Use reserved value for SSI1!\n");
+ ret_val = 0;
+ }
+ break;
+ case SSI2_BAUD:
+ pre_pdf = (cs2cdr >> 6) & 0x7;
+ pdf = cs2cdr & 0x3F;
+ clk_sel = (cscmr1 >> 12) & 3;
+ if (clk_sel == 0) {
+ ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 0x1) {
+ ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 0x2) {
+ ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
+ } else {
+ diag_printf("Error: Use reserved value for SSI2!\n");
+ ret_val = 0;
+ }
+ break;
+ case CSI_BAUD:
#if 0
- clk_sel = ccmr & (1 << 25);
- pdf = (mpdr0 >> 23) & 0x1FF;
- ret_val = (clk_sel != 0) ? (pll_clock(PLL3) / (pdf + 1)) :
- (pll_clock(PLL2) / (pdf + 1));
+ clk_sel = ccmr & (1 << 25);
+ pdf = (mpdr0 >> 23) & 0x1FF;
+ ret_val = (clk_sel != 0) ? (pll_clock(PLL3) / (pdf + 1)) :
+ (pll_clock(PLL2) / (pdf + 1));
#endif
- break;
- case MSTICK1_CLK:
+ break;
+ case MSTICK1_CLK:
#if 0
- pdf = mpdr2 & 0x3F;
- ret_val = pll_clock(PLL2) / (pdf + 1);
+ pdf = mpdr2 & 0x3F;
+ ret_val = pll_clock(PLL2) / (pdf + 1);
#endif
- break;
- case MSTICK2_CLK:
+ break;
+ case MSTICK2_CLK:
#if 0
- pdf = (mpdr2 >> 7) & 0x3F;
- ret_val = pll_clock(PLL2) / (pdf + 1);
+ pdf = (mpdr2 >> 7) & 0x3F;
+ ret_val = pll_clock(PLL2) / (pdf + 1);
#endif
- break;
- case SPI1_CLK:
- case SPI2_CLK:
- pre_pdf = (cscdr2 >> 25) & 0x7;
- pdf = (cscdr2 >> 19) & 0x3F;
- clk_sel = (cscmr1 >> 4) & 3;
- if (clk_sel == 0) {
- ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
- } else if (clk_sel == 1) {
- ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
- } else if (clk_sel == 2) {
- ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
- }
- break;
- default:
- diag_printf("%s(): This clock: %d not supported yet \n",
- __FUNCTION__, clk);
- break;
- }
-
- return ret_val;
+ break;
+ case SPI1_CLK:
+ case SPI2_CLK:
+ pre_pdf = (cscdr2 >> 25) & 0x7;
+ pdf = (cscdr2 >> 19) & 0x3F;
+ clk_sel = (cscmr1 >> 4) & 3;
+ if (clk_sel == 0) {
+ ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 1) {
+ ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 2) {
+ ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
+ }
+ break;
+ default:
+ diag_printf("%s(): This clock: %d not supported yet \n",
+ __FUNCTION__, clk);
+ break;
+ }
+
+ return ret_val;
}
RedBoot_cmd("clko",
- "Select clock source for CLKO (J11 on the CPU daughter card)",
- " Default is 1/8 of ARM core\n\
- <0> - display current clko selection \n\
- <1> - mpl_dpdgck_clk (MPLL) \n\
- <2> - ipg_clk_ccm (IPG) \n\
- <3> - upl_dpdgck_clk (UPLL) \n\
- <4> - pll_ref_clk \n\
- <5> - fpm_ckil512_clk \n\
- <6> - ipg_clk_ahb_arm (AHB) \n\
- <7> - ipg_clk_arm (ARM) \n\
- <8> - spl_dpdgck_clk (SPLL) \n\
- <9> - ckih \n\
- <10> - ipg_clk_ahb_emi_clk \n\
- <11> - ipg_clk_ipu_hsp \n\
- <12> - ipg_clk_nfc_20m \n\
- <13> - ipg_clk_perclk_uart1 (IPG_PER)",
- clko
- );
-
-static u8* clko_name[] ={
- "NULL",
- "1/8 of mpl_dpdgck_clk (MPLL)",
- "ipg_clk_ccm (IPG)",
- "1/8 of upl_dpdgck_clk (UPLL)",
- "pll_ref_clk",
- "fpm_ckil512_clk",
- "ipg_clk_ahb_arm (AHB)",
- "1/8 of ipg_clk_arm (ARM)",
- "1/8 of spl_dpdgck_clk (SPLL)",
- "ckih",
- "ipg_clk_ahb_emi_clk",
- "ipg_clk_ipu_hsp",
- "ipg_clk_nfc_20m",
- "ipg_clk_perclk_uart1 (IPG_PER)",
+ "Select clock source for CLKO (J11 on the CPU daughter card)",
+ " Default is 1/8 of ARM core\n\
+ <0> - display current clko selection \n\
+ <1> - mpl_dpdgck_clk (MPLL) \n\
+ <2> - ipg_clk_ccm (IPG) \n\
+ <3> - upl_dpdgck_clk (UPLL) \n\
+ <4> - pll_ref_clk \n\
+ <5> - fpm_ckil512_clk \n\
+ <6> - ipg_clk_ahb_arm (AHB) \n\
+ <7> - ipg_clk_arm (ARM) \n\
+ <8> - spl_dpdgck_clk (SPLL) \n\
+ <9> - ckih \n\
+ <10> - ipg_clk_ahb_emi_clk \n\
+ <11> - ipg_clk_ipu_hsp \n\
+ <12> - ipg_clk_nfc_20m \n\
+ <13> - ipg_clk_perclk_uart1 (IPG_PER)",
+ clko
+ );
+
+static char *clko_name[] ={
+ "NULL",
+ "1/8 of mpl_dpdgck_clk (MPLL)",
+ "ipg_clk_ccm (IPG)",
+ "1/8 of upl_dpdgck_clk (UPLL)",
+ "pll_ref_clk",
+ "fpm_ckil512_clk",
+ "ipg_clk_ahb_arm (AHB)",
+ "1/8 of ipg_clk_arm (ARM)",
+ "1/8 of spl_dpdgck_clk (SPLL)",
+ "ckih",
+ "ipg_clk_ahb_emi_clk",
+ "ipg_clk_ipu_hsp",
+ "ipg_clk_nfc_20m",
+ "ipg_clk_perclk_uart1 (IPG_PER)",
};
-#define CLKO_MAX_INDEX (sizeof(clko_name) / sizeof(u8*))
+#define CLKO_MAX_INDEX NUM_ELEMS(clko_name)
-static void clko(int argc,char *argv[])
+static void clko(int argc, char *argv[])
{
- u32 action = 0, cosr;
-
- if (!scan_opts(argc, argv, 1, 0, 0, (void*) &action,
- OPTION_ARG_TYPE_NUM, "action"))
- return;
-
- if (action >= CLKO_MAX_INDEX) {
- diag_printf("%d is not supported\n\n", action);
- return;
- }
-
- cosr = readl(CCM_BASE_ADDR + CLKCTL_COSR);
-
- if (action != 0) {
- cosr = (cosr & (~0x1FF)) + action - 1;
- if (action == 1 || action == 3 || action == 7 || action == 8) {
- cosr |= (0x3 << 6); // make it divided by 8
- }
- writel(cosr, CCM_BASE_ADDR + CLKCTL_COSR);
- diag_printf("Set clko to ");
- }
-
- cosr = readl(CCM_BASE_ADDR + CLKCTL_COSR);
- diag_printf("%s\n", clko_name[(cosr & 0xF) + 1]);
- diag_printf("COSR register[0x%x] = 0x%x\n",
- (CCM_BASE_ADDR + CLKCTL_COSR), cosr);
+ u32 action = 0, cosr;
+
+ if (!scan_opts(argc, argv, 1, 0, 0, &action,
+ OPTION_ARG_TYPE_NUM, "action"))
+ return;
+
+ if (action >= CLKO_MAX_INDEX) {
+ diag_printf("%d is not supported\n\n", action);
+ return;
+ }
+
+ cosr = readl(CCM_BASE_ADDR + CLKCTL_COSR);
+
+ if (action != 0) {
+ cosr = (cosr & (~0x1FF)) + action - 1;
+ if (action == 1 || action == 3 || action == 7 || action == 8) {
+ cosr |= (0x3 << 6); // make it divided by 8
+ }
+ writel(cosr, CCM_BASE_ADDR + CLKCTL_COSR);
+ diag_printf("Set clko to ");
+ }
+
+ cosr = readl(CCM_BASE_ADDR + CLKCTL_COSR);
+ diag_printf("%s\n", clko_name[(cosr & 0xF) + 1]);
+ diag_printf("COSR register[0x%08lx] = 0x%08x\n",
+ (CCM_BASE_ADDR + CLKCTL_COSR), cosr);
}
#ifdef L2CC_ENABLED
* by using this command.
*/
RedBoot_cmd("L2",
- "L2 cache",
- "[ON | OFF]",
- do_L2_caches
- );
+ "L2 cache",
+ "[ON | OFF]",
+ do_L2_caches
+ );
void do_L2_caches(int argc, char *argv[])
{
- u32 oldints;
- int L2cache_on=0;
-
- if (argc == 2) {
- if (strcasecmp(argv[1], "on") == 0) {
- HAL_DISABLE_INTERRUPTS(oldints);
- HAL_ENABLE_L2();
- HAL_RESTORE_INTERRUPTS(oldints);
- } else if (strcasecmp(argv[1], "off") == 0) {
- HAL_DISABLE_INTERRUPTS(oldints);
- HAL_CLEAN_INVALIDATE_L2();
- HAL_DISABLE_L2();
- HAL_RESTORE_INTERRUPTS(oldints);
- } else {
- diag_printf("Invalid L2 cache mode: %s\n", argv[1]);
- }
- } else {
- HAL_L2CACHE_IS_ENABLED(L2cache_on);
- diag_printf("L2 cache: %s\n", L2cache_on?"On":"Off");
- }
+ u32 oldints;
+ int L2cache_on=0;
+
+ if (argc == 2) {
+ if (strcasecmp(argv[1], "on") == 0) {
+ HAL_DISABLE_INTERRUPTS(oldints);
+ HAL_ENABLE_L2();
+ HAL_RESTORE_INTERRUPTS(oldints);
+ } else if (strcasecmp(argv[1], "off") == 0) {
+ HAL_DISABLE_INTERRUPTS(oldints);
+ HAL_CLEAN_INVALIDATE_L2();
+ HAL_DISABLE_L2();
+ HAL_RESTORE_INTERRUPTS(oldints);
+ } else {
+ diag_printf("Invalid L2 cache mode: %s\n", argv[1]);
+ }
+ } else {
+ HAL_L2CACHE_IS_ENABLED(L2cache_on);
+ diag_printf("L2 cache: %s\n", L2cache_on?"On":"Off");
+ }
}
#endif //L2CC_ENABLED
-#define IIM_ERR_SHIFT 8
-#define POLL_FUSE_PRGD (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT))
-#define POLL_FUSE_SNSD (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT))
+#define IIM_ERR_SHIFT 8
+#define POLL_FUSE_PRGD (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT))
+#define POLL_FUSE_SNSD (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT))
static void fuse_op_start(void)
{
- /* Do not generate interrupt */
- writel(0, IIM_BASE_ADDR + IIM_STATM_OFF);
- // clear the status bits and error bits
- writel(0x3, IIM_BASE_ADDR + IIM_STAT_OFF);
- writel(0xFE, IIM_BASE_ADDR + IIM_ERR_OFF);
+ /* Do not generate interrupt */
+ writel(0, IIM_BASE_ADDR + IIM_STATM_OFF);
+ // clear the status bits and error bits
+ writel(0x3, IIM_BASE_ADDR + IIM_STAT_OFF);
+ writel(0xFE, IIM_BASE_ADDR + IIM_ERR_OFF);
}
/*
* The action should be either:
- * POLL_FUSE_PRGD
+ * POLL_FUSE_PRGD
* or:
- * POLL_FUSE_SNSD
+ * POLL_FUSE_SNSD
*/
static int poll_fuse_op_done(int action)
{
- u32 status, error;
-
- if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) {
- diag_printf("%s(%d) invalid operation\n", __FUNCTION__, action);
- return -1;
- }
-
- /* Poll busy bit till it is NOT set */
- while ((readl(IIM_BASE_ADDR + IIM_STAT_OFF) & IIM_STAT_BUSY) != 0 ) {
- }
-
- /* Test for successful write */
- status = readl(IIM_BASE_ADDR + IIM_STAT_OFF);
- error = readl(IIM_BASE_ADDR + IIM_ERR_OFF);
-
- if ((status & action) != 0 && (error & (action >> IIM_ERR_SHIFT)) == 0) {
- if (error) {
- diag_printf("Even though the operation seems successful...\n");
- diag_printf("There are some error(s) at addr=0x%x: 0x%x\n",
- (IIM_BASE_ADDR + IIM_ERR_OFF), error);
- }
- return 0;
- }
- diag_printf("%s(%d) failed\n", __FUNCTION__, action);
- diag_printf("status address=0x%x, value=0x%x\n",
- (IIM_BASE_ADDR + IIM_STAT_OFF), status);
- diag_printf("There are some error(s) at addr=0x%x: 0x%x\n",
- (IIM_BASE_ADDR + IIM_ERR_OFF), error);
- return -1;
+ u32 status, error;
+
+ if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) {
+ diag_printf("%s(%d) invalid operation\n", __FUNCTION__, action);
+ return -1;
+ }
+
+ /* Poll busy bit till it is NOT set */
+ while ((readl(IIM_BASE_ADDR + IIM_STAT_OFF) & IIM_STAT_BUSY) != 0 ) {
+ }
+
+ /* Test for successful write */
+ status = readl(IIM_BASE_ADDR + IIM_STAT_OFF);
+ error = readl(IIM_BASE_ADDR + IIM_ERR_OFF);
+
+ if ((status & action) != 0 && (error & (action >> IIM_ERR_SHIFT)) == 0) {
+ if (error) {
+ diag_printf("Even though the operation seems successful...\n");
+ diag_printf("There are some error(s) at addr=0x%08lx: 0x%08x\n",
+ IIM_BASE_ADDR + IIM_ERR_OFF, error);
+ }
+ return 0;
+ }
+ diag_printf("%s(%d) failed\n", __FUNCTION__, action);
+ diag_printf("status address=0x%08lx, value=0x%08x\n",
+ (IIM_BASE_ADDR + IIM_STAT_OFF), status);
+ diag_printf("There are some error(s) at addr=0x%08lx: 0x%08x\n",
+ (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+ return -1;
}
static void sense_fuse(int bank, int row, int bit)
{
- int addr, addr_l, addr_h, reg_addr;
+ int addr, addr_l, addr_h, reg_addr;
- fuse_op_start();
+ fuse_op_start();
- addr = ((bank << 11) | (row << 3) | (bit & 0x7));
- /* Set IIM Program Upper Address */
- addr_h = (addr >> 8) & 0x000000FF;
- /* Set IIM Program Lower Address */
- addr_l = (addr & 0x000000FF);
+ addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+ /* Set IIM Program Upper Address */
+ addr_h = (addr >> 8) & 0x000000FF;
+ /* Set IIM Program Lower Address */
+ addr_l = (addr & 0x000000FF);
#ifdef IIM_FUSE_DEBUG
- diag_printf("%s: addr_h=0x%x, addr_l=0x%x\n",
- __FUNCTION__, addr_h, addr_l);
+ diag_printf("%s: addr_h=0x%x, addr_l=0x%x\n",
+ __FUNCTION__, addr_h, addr_l);
#endif
- writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
- writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
- /* Start sensing */
- writel(0x8, IIM_BASE_ADDR + IIM_FCTL_OFF);
- if (poll_fuse_op_done(POLL_FUSE_SNSD) != 0) {
- diag_printf("%s(bank: %d, row: %d, bit: %d failed\n",
- __FUNCTION__, bank, row, bit);
- }
- reg_addr = IIM_BASE_ADDR + IIM_SDAT_OFF;
- diag_printf("fuses at (bank:%d, row:%d) = 0x%x\n", bank, row, readl(reg_addr));
+ writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
+ writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
+ /* Start sensing */
+ writel(0x8, IIM_BASE_ADDR + IIM_FCTL_OFF);
+ if (poll_fuse_op_done(POLL_FUSE_SNSD) != 0) {
+ diag_printf("%s(bank: %d, row: %d, bit: %d failed\n",
+ __FUNCTION__, bank, row, bit);
+ }
+ reg_addr = IIM_BASE_ADDR + IIM_SDAT_OFF;
+ diag_printf("fuses at (bank:%d, row:%d) = 0x%x\n", bank, row, readl(reg_addr));
}
void do_fuse_read(int argc, char *argv[])
{
- int bank, row;
-
- if (argc == 1) {
- diag_printf("Useage: fuse_read <bank> <row>\n");
- return;
- } else if (argc == 3) {
- if (!parse_num(*(&argv[1]), (unsigned long *)&bank, &argv[1], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
- if (!parse_num(*(&argv[2]), (unsigned long *)&row, &argv[2], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
-
- diag_printf("Read fuse at bank:%d row:%d\n", bank, row);
- sense_fuse(bank, row, 0);
-
- } else {
- diag_printf("Passing in wrong arguments: %d\n", argc);
- diag_printf("Useage: fuse_read <bank> <row>\n");
- }
+ unsigned long bank, row;
+
+ if (argc == 1) {
+ diag_printf("Useage: fuse_read <bank> <row>\n");
+ return;
+ } else if (argc == 3) {
+ if (!parse_num(argv[1], &bank, &argv[1], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(argv[2], &row, &argv[2], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+
+ diag_printf("Read fuse at bank:%ld row:%ld\n", bank, row);
+ sense_fuse(bank, row, 0);
+
+ } else {
+ diag_printf("Passing in wrong arguments: %d\n", argc);
+ diag_printf("Useage: fuse_read <bank> <row>\n");
+ }
}
/* Blow fuses based on the bank, row and bit positions (all 0-based)
*/
static int fuse_blow(int bank,int row,int bit)
{
- int addr, addr_l, addr_h, ret = -1;
+ int addr, addr_l, addr_h, ret = -1;
- fuse_op_start();
+ fuse_op_start();
- /* Disable IIM Program Protect */
- writel(0xAA, IIM_BASE_ADDR + IIM_PREG_P_OFF);
+ /* Disable IIM Program Protect */
+ writel(0xAA, IIM_BASE_ADDR + IIM_PREG_P_OFF);
- addr = ((bank << 11) | (row << 3) | (bit & 0x7));
- /* Set IIM Program Upper Address */
- addr_h = (addr >> 8) & 0x000000FF;
- /* Set IIM Program Lower Address */
- addr_l = (addr & 0x000000FF);
+ addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+ /* Set IIM Program Upper Address */
+ addr_h = (addr >> 8) & 0x000000FF;
+ /* Set IIM Program Lower Address */
+ addr_l = (addr & 0x000000FF);
#ifdef IIM_FUSE_DEBUG
- diag_printf("blowing addr_h=0x%x, addr_l=0x%x\n", addr_h, addr_l);
+ diag_printf("blowing addr_h=0x%x, addr_l=0x%x\n", addr_h, addr_l);
#endif
- writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
- writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
- /* Start Programming */
- writel(0x31, IIM_BASE_ADDR + IIM_FCTL_OFF);
- if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) {
- ret = 0;
- }
-
- /* Enable IIM Program Protect */
- writel(0x0, IIM_BASE_ADDR + IIM_PREG_P_OFF);
- return ret;
+ writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
+ writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
+ /* Start Programming */
+ writel(0x71, IIM_BASE_ADDR + IIM_FCTL_OFF);
+ if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) {
+ ret = 0;
+ }
+
+ /* Enable IIM Program Protect */
+ writel(0x0, IIM_BASE_ADDR + IIM_PREG_P_OFF);
+ return ret;
}
/*
* This command is added for burning IIM fuses
*/
RedBoot_cmd("fuse_read",
- "read some fuses",
- "<bank> <row>",
- do_fuse_read
- );
+ "read some fuses",
+ "<bank> <row>",
+ do_fuse_read
+ );
RedBoot_cmd("fuse_blow",
- "blow some fuses",
- "<bank> <row> <value>",
- do_fuse_blow
- );
+ "blow some fuses",
+ "<bank> <row> <value>",
+ do_fuse_blow
+ );
-#define INIT_STRING "12345678"
+#define INIT_STRING "12345678"
static char ready_to_blow[] = INIT_STRING;
void quick_itoa(u32 num, char *a)
{
- int i, j, k;
- for (i = 0; i <= 7; i++) {
- j = (num >> (4 * i)) & 0xF;
- k = (j < 10) ? '0' : ('a' - 0xa);
- a[i] = j + k;
- }
+ int i, j, k;
+ for (i = 0; i <= 7; i++) {
+ j = (num >> (4 * i)) & 0xF;
+ k = (j < 10) ? '0' : ('a' - 0xa);
+ a[i] = j + k;
+ }
}
void do_fuse_blow(int argc, char *argv[])
{
- int bank, row, value, i;
-
- if (argc == 1) {
- diag_printf("It is too dangeous for you to use this command.\n");
- return;
- } else if (argc == 2) {
- if (strcasecmp(argv[1], "nandboot") == 0) {
- quick_itoa(readl(EPIT_BASE_ADDR + EPITCNR), ready_to_blow);
- diag_printf("%s\n", ready_to_blow);
- }
- return;
- } else if (argc == 3) {
- if (strcasecmp(argv[1], "nandboot") == 0 &&
- strcasecmp(argv[2], ready_to_blow) == 0) {
+ unsigned long bank, row, value;
+ int i;
+
+ if (argc == 1) {
+ diag_printf("It is too dangeous for you to use this command.\n");
+ return;
+ } else if (argc == 2) {
+ if (strcasecmp(argv[1], "nandboot") == 0) {
+ quick_itoa(readl(EPIT_BASE_ADDR + EPITCNR), ready_to_blow);
+ diag_printf("%s\n", ready_to_blow);
+ }
+ return;
+ } else if (argc == 3) {
+ if (strcasecmp(argv[1], "nandboot") == 0 &&
+ strcasecmp(argv[2], ready_to_blow) == 0) {
#if defined(CYGPKG_HAL_ARM_MXC91131) || defined(CYGPKG_HAL_ARM_MX21) || defined(CYGPKG_HAL_ARM_MX27) || defined(CYGPKG_HAL_ARM_MX31)
- diag_printf("No need to blow any fuses for NAND boot on this platform\n\n");
+ diag_printf("No need to blow any fuses for NAND boot on this platform\n\n");
#else
- diag_printf("Ready to burn NAND boot fuses\n");
- if (fuse_blow(0, 16, 1) != 0 || fuse_blow(0, 16, 7) != 0) {
- diag_printf("NAND BOOT fuse blown failed miserably ...\n");
- } else {
- diag_printf("NAND BOOT fuse blown successfully ...\n");
- }
- } else {
- diag_printf("Not ready: %s, %s\n", argv[1], argv[2]);
+ diag_printf("Ready to burn NAND boot fuses\n");
+ if (fuse_blow(0, 16, 1) != 0 || fuse_blow(0, 16, 7) != 0) {
+ diag_printf("NAND BOOT fuse blown failed miserably ...\n");
+ } else {
+ diag_printf("NAND BOOT fuse blown successfully ...\n");
+ }
+ } else {
+ diag_printf("Not ready: %s, %s\n", argv[1], argv[2]);
#endif
- }
- } else if (argc == 4) {
- if (!parse_num(*(&argv[1]), (unsigned long *)&bank, &argv[1], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
- if (!parse_num(*(&argv[2]), (unsigned long *)&row, &argv[2], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
- if (!parse_num(*(&argv[3]), (unsigned long *)&value, &argv[3], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
-
- diag_printf("Blowing fuse at bank:%d row:%d value:%d\n",
- bank, row, value);
- for (i = 0; i < 8; i++) {
- if (((value >> i) & 0x1) == 0) {
- continue;
- }
- if (fuse_blow(bank, row, i) != 0) {
- diag_printf("fuse_blow(bank: %d, row: %d, bit: %d failed\n",
- bank, row, i);
- } else {
- diag_printf("fuse_blow(bank: %d, row: %d, bit: %d successful\n",
- bank, row, i);
- }
- }
- sense_fuse(bank, row, 0);
-
- } else {
- diag_printf("Passing in wrong arguments: %d\n", argc);
- }
- /* Reset to default string */
- strcpy(ready_to_blow, INIT_STRING);;
+ }
+ } else if (argc == 4) {
+ if (!parse_num(argv[1], &bank, &argv[1], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(argv[2], &row, &argv[2], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(argv[3], &value, &argv[3], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+
+ diag_printf("Blowing fuse at bank: %ld row: %ld value: %ld\n",
+ bank, row, value);
+ for (i = 0; i < 8; i++) {
+ if (((value >> i) & 0x1) == 0) {
+ continue;
+ }
+ if (fuse_blow(bank, row, i) != 0) {
+ diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d failed\n",
+ bank, row, i);
+ } else {
+ diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d successful\n",
+ bank, row, i);
+ }
+ }
+ sense_fuse(bank, row, 0);
+
+ } else {
+ diag_printf("Wrong number of arguments: %d\n", argc);
+ }
+ /* Reset to default string */
+ strcpy(ready_to_blow, INIT_STRING);;
}
/* precondition: m>0 and n>0. Let g=gcd(m,n). */
int gcd(int m, int n)
{
- int t;
- while(m > 0) {
- if(n > m) {t = m; m = n; n = t;} /* swap */
- m -= n;
- }
- return n;
+ int t;
+ while(m > 0) {
+ if(n > m) {t = m; m = n; n = t;} /* swap */
+ m -= n;
+ }
+ return n;
}
-#define CLOCK_SRC_DETECT_MS 100
-#define CLOCK_IPG_DEFAULT 66500000
-#define CLOCK_SRC_DETECT_MARGIN 500000
+#define CLOCK_SRC_DETECT_MS 100
+#define CLOCK_IPG_DEFAULT 66500000
+#define CLOCK_SRC_DETECT_MARGIN 500000
void mxc_show_clk_input(void)
{
-// u32 c1, c2, diff, ipg_real, num = 0;
+// u32 c1, c2, diff, ipg_real, num = 0;
- return; // FIXME
+ return; // FIXME
#if 0
- switch (prcs) {
- case 0x01:
- diag_printf("FPM enabled --> 32KHz input source\n");
- return;
- case 0x02:
- break;
- default:
- diag_printf("Error %d: unknown clock source %d\n", __LINE__, prcs);
- return;
- }
-
- // enable GPT with IPG clock input
- writel(0x241, GPT_BASE_ADDR + GPTCR);
- // prescaler = 1
- writel(0, GPT_BASE_ADDR + GPTPR);
-
- c1 = readl(GPT_BASE_ADDR + GPTCNT);
- // use 32KHz input clock to get the delay
- hal_delay_us(CLOCK_SRC_DETECT_MS * 1000);
- c2 = readl(GPT_BASE_ADDR + GPTCNT);
- diff = (c2 > c1) ? (c2 - c1) : (0xFFFFFFFF - c1 + c2);
-
- ipg_real = diff * (1000 / CLOCK_SRC_DETECT_MS);
-
- if (num != 0) {
- diag_printf("Error: Actural clock input is %d MHz\n", num);
- diag_printf(" ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n\n",
- ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
- hal_delay_us(2000000);
- } else {
- diag_printf("ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n\n",
- ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
- }
+ switch (prcs) {
+ case 0x01:
+ diag_printf("FPM enabled --> 32KHz input source\n");
+ return;
+ case 0x02:
+ break;
+ default:
+ diag_printf("Error %d: unknown clock source %d\n", __LINE__, prcs);
+ return;
+ }
+
+ // enable GPT with IPG clock input
+ writel(0x241, GPT_BASE_ADDR + GPTCR);
+ // prescaler = 1
+ writel(0, GPT_BASE_ADDR + GPTPR);
+
+ c1 = readl(GPT_BASE_ADDR + GPTCNT);
+ // use 32KHz input clock to get the delay
+ hal_delay_us(CLOCK_SRC_DETECT_MS * 1000);
+ c2 = readl(GPT_BASE_ADDR + GPTCNT);
+ diff = (c2 > c1) ? (c2 - c1) : (0xFFFFFFFF - c1 + c2);
+
+ ipg_real = diff * (1000 / CLOCK_SRC_DETECT_MS);
+
+ if (num != 0) {
+ diag_printf("Error: Actural clock input is %d MHz\n", num);
+ diag_printf(" ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n\n",
+ ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
+ hal_delay_us(2000000);
+ } else {
+ diag_printf("ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n\n",
+ ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
+ }
#endif
}
void imx_power_mode(int mode)
{
- volatile unsigned int val;
- switch (mode) {
- case 0:
- diag_printf("WFI only\n");
- break;
- case 1:
- diag_printf("Entering WAIT mode\n");
- // wait mode - from validation code
- // Set DSM_INT_HOLDOFF bit in TZIC
- // If the TZIC didn't write the bit then there was interrupt pending
- // It will be serviced while we're in the loop
- // So we write to this bit again
- while (readl(INTC_BASE_ADDR + 0x14) == 0) {
- writel(1, INTC_BASE_ADDR + 0x14);
- // Wait few cycles
- __asm("nop");
- __asm("nop");
- __asm("nop");
- __asm("nop");
- __asm("nop");
- __asm("nop");
- __asm("nop");
- }
- val = readl(CCM_BASE_ADDR + 0x74);
- val = (val & 0xfffffffc) | 0x1; // set WAIT mode
- writel(val, CCM_BASE_ADDR + 0x74);
- val = readl(PLATFORM_LPC_REG);
- writel(val | (1 << 16), PLATFORM_LPC_REG);// ENABLE DSM in ELBOW submodule of ARM platform
- val = readl(PLATFORM_LPC_REG);
- writel(val | (1 << 17), PLATFORM_LPC_REG);// ENABLE DSM in ELBOW submodule of ARM platform
- break;
- case 2:
- diag_printf("Entering stop mode\n");
- hal_delay_us(100);
- // stop mode - from validation code
- // Set DSM_INT_HOLDOFF bit in TZIC
- // If the TZIC didn't write the bit then there was interrupt pending
- // It will be serviced while we're in the loop
- // So we write to this bit again
- while (readl(INTC_BASE_ADDR + 0x14) == 0) {
- writel(1, INTC_BASE_ADDR + 0x14);
- // Wait few cycles
- __asm("nop");
- __asm("nop");
- __asm("nop");
- __asm("nop");
- __asm("nop");
- __asm("nop");
- __asm("nop");
- }
- val = readl(CCM_BASE_ADDR + 0x74);
- val = (val & 0xfffffffc) | 0x2; // set STOP mode
- writel(val, CCM_BASE_ADDR + 0x74);
- val = readl(PLATFORM_LPC_REG);
- writel(val | (3 << 16), PLATFORM_LPC_REG);// ENABLE DSM in ELBOW submodule of ARM platform
-
- // power gating these peripherals
- writel(0x0000030f, GPC_PGR);
- writel(0x1, SRPGCR_EMI);
- writel(0x1, SRPGCR_ARM);
- writel(0x1, PGC_PGCR_VPU);
- writel(0x1, PGC_PGCR_IPU);
- break;
- default:
- diag_printf("Unknown low power mode: %d\n", mode);
- return;
- }
-
- asm("mov r1, #0");
- asm("mcr p15, 0, r1, c7, c0, 4");
+ volatile unsigned int val;
+ switch (mode) {
+ case 0:
+ diag_printf("WFI only\n");
+ break;
+ case 1:
+ diag_printf("Entering WAIT mode\n");
+ // wait mode - from validation code
+ // Set DSM_INT_HOLDOFF bit in TZIC
+ // If the TZIC didn't write the bit then there was interrupt pending
+ // It will be serviced while we're in the loop
+ // So we write to this bit again
+ while (readl(INTC_BASE_ADDR + 0x14) == 0) {
+ writel(1, INTC_BASE_ADDR + 0x14);
+ // Wait few cycles
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ }
+ val = readl(CCM_BASE_ADDR + 0x74);
+ val = (val & 0xfffffffc) | 0x1; // set WAIT mode
+ writel(val, CCM_BASE_ADDR + 0x74);
+ val = readl(PLATFORM_LPC_REG);
+ writel(val | (1 << 16), PLATFORM_LPC_REG);// ENABLE DSM in ELBOW submodule of ARM platform
+ val = readl(PLATFORM_LPC_REG);
+ writel(val | (1 << 17), PLATFORM_LPC_REG);// ENABLE DSM in ELBOW submodule of ARM platform
+ break;
+ case 2:
+ diag_printf("Entering stop mode\n");
+ hal_delay_us(100);
+ // stop mode - from validation code
+ // Set DSM_INT_HOLDOFF bit in TZIC
+ // If the TZIC didn't write the bit then there was interrupt pending
+ // It will be serviced while we're in the loop
+ // So we write to this bit again
+ while (readl(INTC_BASE_ADDR + 0x14) == 0) {
+ writel(1, INTC_BASE_ADDR + 0x14);
+ // Wait few cycles
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ }
+ val = readl(CCM_BASE_ADDR + 0x74);
+ val = (val & 0xfffffffc) | 0x2; // set STOP mode
+ writel(val, CCM_BASE_ADDR + 0x74);
+ val = readl(PLATFORM_LPC_REG);
+ writel(val | (3 << 16), PLATFORM_LPC_REG);// ENABLE DSM in ELBOW submodule of ARM platform
+
+ // power gating these peripherals
+ writel(0x0000030f, GPC_PGR);
+ writel(0x1, SRPGCR_EMI);
+ writel(0x1, SRPGCR_ARM);
+ writel(0x1, PGC_PGCR_VPU);
+ writel(0x1, PGC_PGCR_IPU);
+ break;
+ default:
+ diag_printf("Unknown low power mode: %d\n", mode);
+ return;
+ }
+
+ asm("mov r1, #0");
+ asm("mcr p15, 0, r1, c7, c0, 4");
}
void do_power_mode(int argc, char *argv[])
{
- int mode;
-
- if (argc == 1) {
- diag_printf("Useage: power_mode <mode>\n");
- return;
- } else if (argc == 2) {
- if (!parse_num(*(&argv[1]), (unsigned long *)&mode, &argv[1], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
- imx_power_mode(mode);
-
- } else {
- diag_printf("Passing in wrong arguments: %d\n", argc);
- diag_printf("Useage: power_mode <mode>\n");
- }
+ unsigned long mode;
+
+ if (argc == 1) {
+ diag_printf("Usage: power_mode <mode>\n");
+ return;
+ } else if (argc == 2) {
+ if (!parse_num(argv[1], &mode, &argv[1], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ imx_power_mode(mode);
+
+ } else {
+ diag_printf("Passing in wrong arguments: %d\n", argc);
+ diag_printf("Usage: power_mode <mode>\n");
+ }
}
/*
*/
RedBoot_cmd("power_mode",
"Enter various power modes:",
- "\n\
- <0> - WAIT\n\
- <1> - SRPG\n\
- <2> - STOP\n\
- <3> - STOP with Power-Gating\n\
- -- need reset after issuing the command",
+ "\n"
+ " <0> - WAIT\n"
+ " <1> - SRPG\n"
+ " <2> - STOP\n"
+ " <3> - STOP with Power-Gating\n"
+ " -- need reset after issuing the command",
do_power_mode
- );
+ );
cyg_hal_plf_serial_putc(&channels[i], '+');
jjj++;
}
- cyg_hal_plf_serial_putc(&channels[i], '+');
}
// Restore original console
//==========================================================================
//
-// soc_misc.c
+// soc_misc.c
//
-// HAL misc board support code
+// HAL misc board support code
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
#include <pkgconf/system.h>
#include CYGBLD_HAL_PLATFORM_H
-#include <cyg/infra/cyg_type.h> // base types
-#include <cyg/infra/cyg_trac.h> // tracing macros
-#include <cyg/infra/cyg_ass.h> // assertion macros
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
-#include <cyg/hal/hal_misc.h> // Size constants
-#include <cyg/hal/hal_io.h> // IO macros
-#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_misc.h> // Size constants
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
#include <cyg/hal/hal_diag.h>
-#include <cyg/hal/hal_intr.h> // Interrupt names
-#include <cyg/hal/hal_cache.h> // Cache control
-#include <cyg/hal/hal_soc.h> // Hardware definitions
-#include <cyg/hal/hal_mm.h> // MMap table definitions
+#include <cyg/hal/hal_intr.h> // Interrupt names
+#include <cyg/hal/hal_cache.h> // Cache control
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/hal_mm.h> // MMap table definitions
-#include <cyg/infra/diag.h> // diag_printf
+#include <cyg/infra/diag.h> // diag_printf
+#include <cyg/io/imx_nfc.h>
// Most initialization has already been done before we get here.
// All we do here is set up the interrupt environment.
externC void plf_hardware_init(void);
int _mxc_boot, _mxc_fis;
-#define IIM_PROD_REV_SH 3
-#define IIM_PROD_REV_LEN 5
-#define IIM_SREV_REV_SH 4
-#define IIM_SREV_REV_LEN 4
-#define PROD_SIGNATURE_MX37 0x1
+#define IIM_PROD_REV_SH 3
+#define IIM_PROD_REV_LEN 5
+#define IIM_SREV_REV_SH 4
+#define IIM_SREV_REV_LEN 4
+#define PROD_SIGNATURE_MX37 0x1
#define PROD_SIGNATURE_SUPPORTED PROD_SIGNATURE_MX37
-#define CHIP_VERSION_NONE 0xFFFFFFFF // invalid product ID
-#define CHIP_VERSION_UNKNOWN 0xDEADBEEF // invalid chip rev
+#define CHIP_VERSION_NONE 0xFFFFFFFF // invalid product ID
+#define CHIP_VERSION_UNKNOWN 0xDEADBEEF // invalid chip rev
/*
* System_rev will have the following format
*/
static int read_system_rev(void)
{
- int val;
+ int val;
- val = readl(IIM_BASE_ADDR + IIM_PREV_OFF);
+ val = readl(IIM_BASE_ADDR + IIM_PREV_OFF);
- system_rev = 0x37 << PART_NUMBER_OFFSET; /* For MX37 Platform*/
+ system_rev = 0x37 << PART_NUMBER_OFFSET; /* For MX37 Platform*/
- /* Now trying to retrieve the silicon rev from IIM's SREV register */
- return readl(IIM_BASE_ADDR + IIM_SREV_OFF);
+ /* Now trying to retrieve the silicon rev from IIM's SREV register */
+ return readl(IIM_BASE_ADDR + IIM_SREV_OFF);
}
extern nfc_setup_func_t *nfc_setup;
unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz,
- unsigned int is_mlc, unsigned int num_of_chips);
+ unsigned int is_mlc, unsigned int num_of_chips);
void hal_hardware_init(void)
{
- volatile unsigned int esdmisc = readl(ESDCTL_BASE + 0x10);
- volatile unsigned int esdctl0 = readl(ESDCTL_BASE);
- volatile unsigned int sbmr;
- int bt_mem_type = 0, bt_mem_control = 0;
- int ver = read_system_rev();
- unsigned int *fis_addr = (unsigned int *)IRAM_BASE_ADDR;
-
- switch (*fis_addr) {
- case FROM_MMC_FLASH:
- _mxc_fis = FROM_MMC_FLASH;
- break;
- case FROM_NAND_FLASH:
- _mxc_fis = FROM_NAND_FLASH;
- break;
- default:
- sbmr = readl(SRC_BASE_ADDR + 0x4);
- bt_mem_control = sbmr & 0x3;
- bt_mem_type = (sbmr & 0x180) >> 7;
- if (bt_mem_control == 0x3) {
- if (bt_mem_type == 0) {
- _mxc_fis = FROM_MMC_FLASH;
- _mxc_boot = FROM_MMC_FLASH;
- } else if (bt_mem_type == 3) {
- _mxc_fis = FROM_SPI_NOR_FLASH;
- _mxc_boot = FROM_SPI_NOR_FLASH;
- }
- } else if (bt_mem_control == 0x1) {
- _mxc_fis = FROM_NAND_FLASH;
- _mxc_boot = FROM_NAND_FLASH;
- }
- }
-
- find_correct_chip = ver;
-
- if (ver != CHIP_VERSION_NONE) {
- /* Valid product revision found. Check actual silicon rev and
- * NOT use the version from the ROM code. */
- if (((ver >> 4) & 0xF) == 0x0) {
- HAL_PLATFORM_EXTRA[5] = '1';
- HAL_PLATFORM_EXTRA[7] = '0';
- system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
- system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/
- } else if (((ver >> 4) & 0xF) == 0x1) {
- HAL_PLATFORM_EXTRA[5] = '1';
- HAL_PLATFORM_EXTRA[7] = '1';
- system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
- system_rev |= 1 << MINOR_NUMBER_OFFSET; /*Minor Number*/
- } else {
- HAL_PLATFORM_EXTRA[5] = 'x';
- HAL_PLATFORM_EXTRA[7] = 'x';
- system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
- system_rev |= 1 << MINOR_NUMBER_OFFSET; /*Minor Number*/
- find_correct_chip = CHIP_VERSION_UNKNOWN;
- }
- }
-
- if ((esdmisc & 0x4) == 0) {
- HAL_PLATFORM_EXTRA[14] = 'S';
- }
- if ((esdctl0 & 0x30000) != 0x20000) {
- HAL_PLATFORM_EXTRA[11] = '1';
- HAL_PLATFORM_EXTRA[12] = '6';
- }
-
- // Enable caches
- HAL_ICACHE_ENABLE();
- HAL_DCACHE_ENABLE();
-
- // enable EPIT and start it with 32KHz input clock
- writel(0x00010000, EPIT_BASE_ADDR + EPITCR);
-
- // make sure reset is complete
- while ((readl(EPIT_BASE_ADDR + EPITCR) & 0x10000) != 0) {
- }
-
- writel(0x030E0002, EPIT_BASE_ADDR + EPITCR);
- writel(0x030E0003, EPIT_BASE_ADDR + EPITCR);
-
- writel(0, EPIT_BASE_ADDR + EPITCMPR); // always compare with 0
-
- if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
- // increase the WDOG timeout value to the max
- writew(readw(WDOG_BASE_ADDR) | 0xFF00, WDOG_BASE_ADDR);
- }
-
- // Perform any platform specific initializations
- plf_hardware_init();
-
- // Set up eCos/ROM interfaces
- hal_if_init();
-
- nfc_setup = (nfc_setup_func_t*)mxc_nfc_soc_setup;
+ volatile unsigned int esdmisc = readl(ESDCTL_BASE + 0x10);
+ volatile unsigned int esdctl0 = readl(ESDCTL_BASE);
+ volatile unsigned int sbmr;
+ int bt_mem_type = 0, bt_mem_control = 0;
+ int ver = read_system_rev();
+ unsigned int *fis_addr = (unsigned int *)IRAM_BASE_ADDR;
+
+ switch (*fis_addr) {
+ case FROM_MMC_FLASH:
+ _mxc_fis = FROM_MMC_FLASH;
+ break;
+ case FROM_NAND_FLASH:
+ _mxc_fis = FROM_NAND_FLASH;
+ break;
+ default:
+ sbmr = readl(SRC_BASE_ADDR + 0x4);
+ bt_mem_control = sbmr & 0x3;
+ bt_mem_type = (sbmr & 0x180) >> 7;
+ if (bt_mem_control == 0x3) {
+ if (bt_mem_type == 0) {
+ _mxc_fis = FROM_MMC_FLASH;
+ _mxc_boot = FROM_MMC_FLASH;
+ } else if (bt_mem_type == 3) {
+ _mxc_fis = FROM_SPI_NOR_FLASH;
+ _mxc_boot = FROM_SPI_NOR_FLASH;
+ }
+ } else if (bt_mem_control == 0x1) {
+ _mxc_fis = FROM_NAND_FLASH;
+ _mxc_boot = FROM_NAND_FLASH;
+ }
+ }
+
+ find_correct_chip = ver;
+
+ if (ver != CHIP_VERSION_NONE) {
+ /* Valid product revision found. Check actual silicon rev and
+ * NOT use the version from the ROM code. */
+ if (((ver >> 4) & 0xF) == 0x0) {
+ HAL_PLATFORM_EXTRA[5] = '1';
+ HAL_PLATFORM_EXTRA[7] = '0';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ } else if (((ver >> 4) & 0xF) == 0x1) {
+ HAL_PLATFORM_EXTRA[5] = '1';
+ HAL_PLATFORM_EXTRA[7] = '1';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 1 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ } else {
+ HAL_PLATFORM_EXTRA[5] = 'x';
+ HAL_PLATFORM_EXTRA[7] = 'x';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 1 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ find_correct_chip = CHIP_VERSION_UNKNOWN;
+ }
+ }
+
+ if ((esdmisc & 0x4) == 0) {
+ HAL_PLATFORM_EXTRA[14] = 'S';
+ }
+ if ((esdctl0 & 0x30000) != 0x20000) {
+ HAL_PLATFORM_EXTRA[11] = '1';
+ HAL_PLATFORM_EXTRA[12] = '6';
+ }
+
+ // Enable caches
+ HAL_ICACHE_ENABLE();
+ HAL_DCACHE_ENABLE();
+
+ // enable EPIT and start it with 32KHz input clock
+ writel(0x00010000, EPIT_BASE_ADDR + EPITCR);
+
+ // make sure reset is complete
+ while ((readl(EPIT_BASE_ADDR + EPITCR) & 0x10000) != 0) {
+ }
+
+ writel(0x030E0002, EPIT_BASE_ADDR + EPITCR);
+ writel(0x030E0003, EPIT_BASE_ADDR + EPITCR);
+
+ writel(0, EPIT_BASE_ADDR + EPITCMPR); // always compare with 0
+
+ if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
+ // increase the WDOG timeout value to the max
+ writew(readw(WDOG_BASE_ADDR) | 0xFF00, WDOG_BASE_ADDR);
+ }
+
+ // Perform any platform specific initializations
+ plf_hardware_init();
+
+ // Set up eCos/ROM interfaces
+ hal_if_init();
+
+ nfc_setup = (nfc_setup_func_t*)mxc_nfc_soc_setup;
}
// -------------------------------------------------------------------------
// This routine is called during a clock interrupt.
// Define this if you want to ensure that the clock is perfect (i.e. does
-// not drift). One reason to leave it turned off is that it costs some
+// not drift). One reason to leave it turned off is that it costs some
// us per system clock interrupt for this maintenance.
#undef COMPENSATE_FOR_CLOCK_DRIFT
// Note: The "contract" for this function is that the value is the number
// of hardware clocks that have happened since the last interrupt (i.e.
-// when it was reset). This value is used to measure interrupt latencies.
+// when it was reset). This value is used to measure interrupt latencies.
// However, since the hardware counter runs freely, this routine computes
// the difference between the current clock period and the number of hardware
// ticks left before the next timer interrupt.
unsigned int hal_timer_count(void)
{
- return (0xFFFFFFFF - readl(EPIT_BASE_ADDR + EPITCNR));
+ return (0xFFFFFFFF - readl(EPIT_BASE_ADDR + EPITCNR));
}
-#define WDT_MAGIC_1 0x5555
-#define WDT_MAGIC_2 0xAAAA
-#define MXC_WDT_WSR 0x2
+#define WDT_MAGIC_1 0x5555
+#define WDT_MAGIC_2 0xAAAA
+#define MXC_WDT_WSR 0x2
unsigned int i2c_base_addr[] = {
- I2C_BASE_ADDR,
- I2C2_BASE_ADDR,
- I2C3_BASE_ADDR
+ I2C_BASE_ADDR,
+ I2C2_BASE_ADDR,
+ I2C3_BASE_ADDR
};
unsigned int i2c_num = 3;
//
void hal_delay_us(unsigned int usecs)
{
- /*
- * This causes overflow.
- * unsigned int delayCount = (usecs * 32768) / 1000000;
- * So use the following one instead
- */
- unsigned int delayCount = (usecs * 512) / 15625;
+ /*
+ * This causes overflow.
+ * unsigned int delayCount = (usecs * 32768) / 1000000;
+ * So use the following one instead
+ */
+ unsigned int delayCount = (usecs * 512) / 15625;
+ static unsigned int led_on;
- if (delayCount == 0) {
- return;
- }
+ if (delayCount == 0) {
+ return;
+ }
- // issue the service sequence instructions
- if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
- writew(WDT_MAGIC_1, WDOG_BASE_ADDR + MXC_WDT_WSR);
- writew(WDT_MAGIC_2, WDOG_BASE_ADDR + MXC_WDT_WSR);
- }
+ // issue the service sequence instructions
+ if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
+ writew(WDT_MAGIC_1, WDOG_BASE_ADDR + MXC_WDT_WSR);
+ writew(WDT_MAGIC_2, WDOG_BASE_ADDR + MXC_WDT_WSR);
+ }
- writel(0x01, EPIT_BASE_ADDR + EPITSR); // clear the compare status bit
+ writel(0x01, EPIT_BASE_ADDR + EPITSR); // clear the compare status bit
- writel(delayCount, EPIT_BASE_ADDR + EPITLR);
+ writel(delayCount, EPIT_BASE_ADDR + EPITLR);
- while ((0x1 & readl(EPIT_BASE_ADDR + EPITSR)) == 0); // return until compare bit is set
+ while ((0x1 & readl(EPIT_BASE_ADDR + EPITSR)) == 0); // return until compare bit is set
+
+ if ((++led_on % 3000) == 0)
+ BOARD_DEBUG_LED(0);
}
// -------------------------------------------------------------------------
-// This routine is called to respond to a hardware interrupt (IRQ). It
+// This routine is called to respond to a hardware interrupt (IRQ). It
// should interrogate the hardware and return the IRQ vector number.
int hal_IRQ_handler(void)
{
#ifdef HAL_EXTENDED_IRQ_HANDLER
- cyg_uint32 index;
+ cyg_uint32 index;
- // Use platform specific IRQ handler, if defined
- // Note: this macro should do a 'return' with the appropriate
- // interrupt number if such an extended interrupt exists. The
- // assumption is that the line after the macro starts 'normal' processing.
- HAL_EXTENDED_IRQ_HANDLER(index);
+ // Use platform specific IRQ handler, if defined
+ // Note: this macro should do a 'return' with the appropriate
+ // interrupt number if such an extended interrupt exists. The
+ // assumption is that the line after the macro starts 'normal' processing.
+ HAL_EXTENDED_IRQ_HANDLER(index);
#endif
- return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
+ return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
}
//
void hal_interrupt_mask(int vector)
{
-// diag_printf("6hal_interrupt_mask(vector=%d) \n", vector);
+// diag_printf("6hal_interrupt_mask(vector=%d) \n", vector);
#ifdef HAL_EXTENDED_INTERRUPT_MASK
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_MASK(vector);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_MASK(vector);
#endif
}
void hal_interrupt_unmask(int vector)
{
-// diag_printf("7hal_interrupt_unmask(vector=%d) \n", vector);
+// diag_printf("7hal_interrupt_unmask(vector=%d) \n", vector);
#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_UNMASK(vector);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_UNMASK(vector);
#endif
}
void hal_interrupt_acknowledge(int vector)
{
-// diag_printf("8hal_interrupt_acknowledge(vector=%d) \n", vector);
+// diag_printf("8hal_interrupt_acknowledge(vector=%d) \n", vector);
#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector);
#endif
}
{
#ifdef HAL_EXTENDED_INTERRUPT_CONFIGURE
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_CONFIGURE(vector, level, up);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_CONFIGURE(vector, level, up);
#endif
}
{
#ifdef HAL_EXTENDED_INTERRUPT_SET_LEVEL
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_SET_LEVEL(vector, level);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_SET_LEVEL(vector, level);
#endif
- // Interrupt priorities are not configurable.
+ // Interrupt priorities are not configurable.
}
-unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz, unsigned int is_mlc, unsigned int num_of_chips)
+unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz,
+ unsigned int is_mlc, unsigned int num_of_chips)
{
- return 0x20; // NFC version 2
+ return MXC_NFC_V2; // NFC version 2
}
static void check_correct_chip(void)
{
- if (find_correct_chip == CHIP_VERSION_UNKNOWN) {
- diag_printf("Unrecognized chip version: 0x%x!!!\n", read_system_rev());
- diag_printf("Assuming chip version=0x%x\n", system_rev);
- } else if (find_correct_chip == CHIP_VERSION_NONE) {
- diag_printf("Unrecognized chip: 0x%x!!!\n", readl(IIM_BASE_ADDR + IIM_PREV_OFF));
- }
+ if (find_correct_chip == CHIP_VERSION_UNKNOWN) {
+ diag_printf("Unrecognized chip version: 0x%x!!!\n", read_system_rev());
+ diag_printf("Assuming chip version=0x%x\n", system_rev);
+ } else if (find_correct_chip == CHIP_VERSION_NONE) {
+ diag_printf("Unrecognized chip: 0x%x!!!\n", readl(IIM_BASE_ADDR + IIM_PREV_OFF));
+ }
}
RedBoot_init(check_correct_chip, RedBoot_INIT_LAST);
description "
The processor can run at various frequencies.
These values are expressed in KHz. Note that there are
- several steppings of the rated to run at different
+ several steppings of the rate to run at different
maximum frequencies. Check the specs to make sure that your
particular processor can run at the rate you select here."
}
while (1) {
}
}
- return 0x30;
+ return MXC_NFC_V3;
}
static void show_sys_info(void)
unsigned int get_peri_clock(enum peri_clocks clk);
-enum {
- MXC_NFC_V1,
- MXC_NFC_V2,
-};
-
typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int);
#endif //#if !defined(__ASSEMBLER__)
unsigned int get_peri_clock(enum peri_clocks clk);
-enum {
- MXC_NFC_V1,
- MXC_NFC_V2,
-};
-
typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int);
#endif //#if !defined(__ASSEMBLER__)
unsigned int get_peri_clock(enum peri_clocks clk);
-enum {
- MXC_NFC_V1,
- MXC_NFC_V2,
-};
-
typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int);
#endif //#if !defined(__ASSEMBLER__)
unsigned int get_peri_clock(enum peri_clocks clk);
-enum {
- MXC_NFC_V1,
- MXC_NFC_V2,
-};
-
typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int);
#endif //#if !defined(__ASSEMBLER__)
'ram' when building programs to load into RAM using eCos GDB
stubs. Select 'rom' when building a stand-alone application
which will be put into ROM, or for the special case of
- building the eCos GDB stubs themselves. Using ROMRAM will allow
+ building the eCos GDB stubs themselves. Using ROMRAM will allow
the program to exist in ROM, but be copied to RAM during startup."
}
flavor data
calculated 6
}
-
+
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
display "Debug serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
calculated 0
}
-
+
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
display "Console serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
The board has only three serial ports. This option
chooses which port will be used for console output."
}
-
+
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
flavor none
display "Global command prefix"
flavor data
no_define
- default_value { "arm-elf" }
+ default_value { "arm-none-eabi" }
description "
This option specifies the command prefix used when
invoking the build tools."
display "Global compiler flags"
flavor data
no_define
- default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
description "
This option controls the global compiler flags which are used to
compile all packages by default. Individual packages may define
display "Memory layout"
flavor data
no_define
- calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_board_ram" :
- (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" :
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_board_ram" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" :
"arm_board_rom" }
cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.ldi>" :
- (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.ldi>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.ldi>" :
"<pkgconf/mlt_arm_board_rom.ldi>" }
}
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_H
- calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.h>" :
- (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.h>" :
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.h>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.h>" :
"<pkgconf/mlt_arm_board_rom.h>" }
}
}
make -priority 325 {
<PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
- $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
$(OBJCOPY) -O srec $< $(@:.bin=.srec)
$(OBJCOPY) -O binary $< $@
}
'ram' when building programs to load into RAM using eCos GDB
stubs. Select 'rom' when building a stand-alone application
which will be put into ROM, or for the special case of
- building the eCos GDB stubs themselves. Using ROMRAM will allow
+ building the eCos GDB stubs themselves. Using ROMRAM will allow
the program to exist in ROM, but be copied to RAM during startup."
}
flavor data
calculated 6
}
-
+
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
display "Debug serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
calculated 0
}
-
+
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
display "Console serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
The board has only three serial ports. This option
chooses which port will be used for console output."
}
-
+
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
flavor none
display "Global compiler flags"
flavor data
no_define
- default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
description "
This option controls the global compiler flags which are used to
compile all packages by default. Individual packages may define
display "Memory layout"
flavor data
no_define
- calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_board_ram" :
- (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" :
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_board_ram" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" :
"arm_board_rom" }
cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.ldi>" :
- (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.ldi>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.ldi>" :
"<pkgconf/mlt_arm_board_rom.ldi>" }
}
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_H
- calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.h>" :
- (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.h>" :
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.h>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.h>" :
"<pkgconf/mlt_arm_board_rom.h>" }
}
}
description "
This option lists the target's requirements for a valid Redboot
configuration."
-
+
compile -library=libextras.a redboot_cmds.c
cdl_option CYGBLD_BUILD_REDBOOT_BIN {
make -priority 325 {
<PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
- $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
$(OBJCOPY) -O srec $< $(@:.bin=.srec)
$(OBJCOPY) -O binary $< $@
}
#include <cyg/hal/hal_soc.h> // Hardware definitions
#define PMIC_SPI_BASE CSPI2_BASE_ADDR
+#define PMIC_SPI_CHIP_SELECT_NO SPI_CTRL_CS0
#define PBC_BASE CS4_BASE_ADDR /* Peripheral Bus Controller */
#define PBC_VERSION PBC_BASE
TURN_LED_ON(n); \
} \
CYG_MACRO_END
-
+
#endif /* CYGONCE_FSL_BOARD_H */
ldr r2, =10f
mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
orr r1, r1, #7 // enable MMU bit
+ orr r1, r1, #0x800 // enable z bit
mcr MMU_CP, 0, r1, MMU_Control, c0
mov pc,r2 /* Change address spaces */
nop
/* CS0 sync mode setup */
.macro init_cs0_sync
/*
- * Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz):
+ * Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz)
*/
/* Flash reset command */
- mov r0, #CS0_BASE_ADDR
+ mov r0, #CS0_BASE_ADDR
ldr r1, =0xF0F0
strh r1, [r0]
/* 1st command */
ldr r2, =0xAAA
- add r2, r2, r0
+ add r2, r2, r0
ldr r1, =0xAAAA
- strh r1, [r2]
+ strh r1, [r2]
/* 2nd command */
ldr r2, =0x554
add r2, r2, r0
.endm /* init_cs4 */
// DDR SDRAM setup
- * r4 = burst mode vs full-page mode */
+ /* r4 = burst mode vs full-page mode */
.macro init_ddr_sdram
ldr r3, SDRAM_0x82216080 /* 16 bit memory */
ldr r0, ESDCTL_BASE_W
SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
};
cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
- user_value 1 "FSL 200740"
+ user_value 1 "FSL 200904"
};
};
cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
- user_value 1 "FSL 200740"
+ user_value 1 "FSL 200904"
};
int stat;
if (IS_FIS_FROM_NAND()) {
- base_addr = (void*)MXC_NAND_BASE_DUMMY;
+ base_addr = (void*)0;
diag_printf("Updating ROM in NAND flash\n");
} else if (IS_FIS_FROM_NOR()) {
base_addr = (void*)BOARD_FLASH_START;
'ram' when building programs to load into RAM using eCos GDB
stubs. Select 'rom' when building a stand-alone application
which will be put into ROM, or for the special case of
- building the eCos GDB stubs themselves. Using ROMRAM will allow
+ building the eCos GDB stubs themselves. Using ROMRAM will allow
the program to exist in ROM, but be copied to RAM during startup."
}
flavor data
calculated 6
}
-
+
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
display "Debug serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
calculated 0
}
-
+
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
display "Console serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
The board has only three serial ports. This option
chooses which port will be used for console output."
}
-
+
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
flavor none
display "Global command prefix"
flavor data
no_define
- default_value { "arm-elf" }
+ default_value { "arm-none-eabi" }
description "
This option specifies the command prefix used when
invoking the build tools."
display "Global compiler flags"
flavor data
no_define
- default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
description "
This option controls the global compiler flags which are used to
compile all packages by default. Individual packages may define
display "Memory layout"
flavor data
no_define
- calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_board_ram" :
- (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" :
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_board_ram" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" :
"arm_board_rom" }
cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.ldi>" :
- (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.ldi>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.ldi>" :
"<pkgconf/mlt_arm_board_rom.ldi>" }
}
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_H
- calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.h>" :
- (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.h>" :
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.h>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.h>" :
"<pkgconf/mlt_arm_board_rom.h>" }
}
}
make -priority 325 {
<PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
- $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
$(OBJCOPY) -O srec $< $(@:.bin=.srec)
$(OBJCOPY) -O binary $< $@
}
#include <cyg/hal/hal_soc.h> // Hardware definitions
#define PMIC_SPI_BASE CSPI2_BASE_ADDR
+#define PMIC_SPI_CHIP_SELECT_NO SPI_CTRL_CS0
#define BOARD_CS_LAN_BASE (CS2_BASE_ADDR + 0x300)
ldr r2, =10f
mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
orr r1, r1, #7 // enable MMU bit
+ orr r1, r1, #0x800 // enable z bit
mcr MMU_CP, 0, r1, MMU_Control, c0
mov pc,r2 /* Change address spaces */
nop
SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
};
cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
- user_value 1 "FSL 200740"
+ user_value 1 "FSL 200904"
};
cdl_option CYGBLD_BUILD_REDBOOT_WITH_MXCUSB {
int stat;
if (IS_FIS_FROM_NAND()) {
- base_addr = (void*)MXC_NAND_BASE_DUMMY;
+ base_addr = (void*)0;
diag_printf("Updating ROM in NAND flash\n");
} else if (IS_FIS_FROM_NOR()) {
base_addr = (void*)BOARD_FLASH_START;
'ram' when building programs to load into RAM using eCos GDB
stubs. Select 'rom' when building a stand-alone application
which will be put into ROM, or for the special case of
- building the eCos GDB stubs themselves. Using ROMRAM will allow
+ building the eCos GDB stubs themselves. Using ROMRAM will allow
the program to exist in ROM, but be copied to RAM during startup."
}
flavor data
calculated 6
}
-
+
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
display "Debug serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
calculated 0
}
-
+
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
display "Console serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
The board has only three serial ports. This option
chooses which port will be used for console output."
}
-
+
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
flavor none
display "Global command prefix"
flavor data
no_define
- default_value { "arm-elf" }
+ default_value { "arm-none-eabi" }
description "
This option specifies the command prefix used when
invoking the build tools."
display "Global compiler flags"
flavor data
no_define
- default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
description "
This option controls the global compiler flags which are used to
compile all packages by default. Individual packages may define
display "Memory layout"
flavor data
no_define
- calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_board_ram" :
- (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" :
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_board_ram" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" :
"arm_board_rom" }
cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.ldi>" :
- (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.ldi>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.ldi>" :
"<pkgconf/mlt_arm_board_rom.ldi>" }
}
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_H
- calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.h>" :
- (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.h>" :
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_board_ram.h>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.h>" :
"<pkgconf/mlt_arm_board_rom.h>" }
}
}
make -priority 325 {
<PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
- $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
$(OBJCOPY) -O srec $< $(@:.bin=.srec)
$(OBJCOPY) -O binary $< $@
}
#include <cyg/hal/hal_soc.h> // Hardware definitions
#define PMIC_SPI_BASE CSPI2_BASE_ADDR
+#define PMIC_SPI_CHIP_SELECT_NO SPI_CTRL_CS0
#define BOARD_CS_LAN_BASE (CS2_BASE_ADDR + 0x300)
ldr r2, =10f
mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
orr r1, r1, #7 // enable MMU bit
+ orr r1, r1, #0x800 // enable z bit
mcr MMU_CP, 0, r1, MMU_Control, c0
mov pc,r2 /* Change address spaces */
nop
SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
};
cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
- user_value 1 "FSL 200740"
+ user_value 1 "FSL 200904"
};
cdl_option CYGBLD_BUILD_REDBOOT_WITH_MXCUSB {
user_value 1
int stat;
if (IS_FIS_FROM_NAND()) {
- base_addr = (void*)MXC_NAND_BASE_DUMMY;
+ base_addr = (void*)0;
diag_printf("Updating ROM in NAND flash\n");
} else if (IS_FIS_FROM_NOR()) {
base_addr = (void*)BOARD_FLASH_START;
description "
The processor can run at various frequencies.
These values are expressed in KHz. Note that there are
- several steppings of the rated to run at different
+ several steppings of the rate to run at different
maximum frequencies. Check the specs to make sure that your
particular processor can run at the rate you select here."
}
// Query the state of the L2 cache
#define HAL_L2CACHE_IS_ENABLED(_state_) \
-CYG_MACRO_START \
- _state_ = (*(unsigned long *)(0x30000100)) & 0x1; \
-CYG_MACRO_END
+ (_state_ = readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1)
#ifdef L2CC_ENABLED
-#define HAL_ENABLE_L2() \
-CYG_MACRO_START \
- asm volatile ( \
- "ldr r0, =0x30000100;" \
- "ldr r1, [r0];" \
- "orr r1, r1, #0x1;" \
- "str r1, [r0];" \
- : \
- : \
- : "r0", "r1" /* Clobber list */ \
- ); \
-CYG_MACRO_END
-
-#define HAL_DISABLE_L2() \
-CYG_MACRO_START \
- asm volatile ( \
- "ldr r0, =0x30000000;" \
- "ldr r1, [r0, #0x100];" \
- "bic r1, r1, #0x1;" \
- "str r1, [r0, #0x100];" \
- : \
- : \
- : "r0", "r1" /* Clobber list */ \
- ); \
-CYG_MACRO_END
+#define HAL_ENABLE_L2() \
+{ \
+ writel(1, L2CC_BASE_ADDR + L2_CACHE_CTL_REG); \
+}
-#define HAL_SYNC_L2() \
-CYG_MACRO_START \
- asm volatile ( \
- "ldr r0, =0x30000000;" \
- "ldr r1, [r0, #0x100];" \
- "mov r2, r1;" \
- "tst r1, #0x1;" \
- "beq 1f;" \
- "bic r1, r1, #0x1;" \
- "str r1, [r0, #0x100];" \
- "1: " \
- "ldr r2, =0x0;" \
- "str r2, [r0, #0x730];" \
- "str r2, [r0, #0x100];" \
- : \
- : \
- : "r0", "r1", "r2" /* Clobber list */ \
- ); \
-CYG_MACRO_END
+#define HAL_DISABLE_L2() \
+{ \
+ writel(0, L2CC_BASE_ADDR + L2_CACHE_CTL_REG); \
+}
-#define HAL_INVALIDATE_L2() \
-CYG_MACRO_START \
- asm volatile ( \
- "ldr r0, =0x30000000;" \
- "ldr r1, [r0, #0x100];" \
- "mov r2, r1;" \
- "tst r1, #0x1;" \
- "beq 1f;" \
- "bic r1, r1, #0x1;" \
- "str r1, [r0, #0x100];" \
- "1: " \
- "ldr r1, =0x0;" \
- "str r1, [r0, #0x730];" \
- "ldr r1, =0xFF;" \
- "str r1, [r0, #0x77C];" \
- "2: " \
- "ldr r1, [r0, #0x77C];" \
- "cmp r1, #0x0;" \
- "bne 2b;" \
- "str r2, [r0, #0x100];" \
- : \
- : \
- : "r0", "r1" /* Clobber list */ \
- ); \
-CYG_MACRO_END
+#define HAL_SYNC_L2() \
+{ \
+ if ((readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1) != 0) { \
+ writel(0, L2CC_BASE_ADDR + L2_CACHE_SYNC_REG); \
+ while ((readl(L2CC_BASE_ADDR + L2_CACHE_SYNC_REG) & 1) == 1); \
+ } \
+}
-#define HAL_CLEAN_INVALIDATE_L2() \
-CYG_MACRO_START \
- asm volatile ( \
- "ldr r0, =0x30000000;" \
- "ldr r1, [r0, #0x100];" \
- "mov r2, r1;" \
- "tst r1, #0x1;" \
- "beq 1f;" \
- "bic r1, r1, #0x1;" \
- "str r1, [r0, #0x100];" \
- "1: " \
- "ldr r2, =0x0;" \
- "str r2, [r0, #0x730];" \
- "ldr r2, =0xFF;" \
- "str r2, [r0, #0x7FC];" \
- "2: " \
- "ldr r2, [r0, #0x7FC];" \
- "cmp r2, #0x0;" \
- "bne 2b;" \
- "str r2, [r0, #0x100];" \
- : \
- : \
- : "r0", "r1" /* Clobber list */ \
- ); \
-CYG_MACRO_END
+#define HAL_INVALIDATE_L2() \
+{ \
+ if ((readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1) != 0) { \
+ writel(0xFF, L2CC_BASE_ADDR + L2_CACHE_INV_WAY_REG); \
+ while ((readl(L2CC_BASE_ADDR + L2_CACHE_INV_WAY_REG) & 0xFF) != 0); \
+ HAL_SYNC_L2(); \
+ } \
+}
+ \
+#define HAL_CLEAN_INVALIDATE_L2() \
+{ \
+ if ((readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1) != 0) { \
+ writel(0xFF, L2CC_BASE_ADDR + L2_CACHE_CLEAN_INV_WAY_REG); \
+ while ((readl(L2CC_BASE_ADDR + L2_CACHE_CLEAN_INV_WAY_REG) & 0xFF) != 0);\
+ HAL_SYNC_L2(); \
+ } \
+}
#else //L2CC_ENABLED
#define HAL_DCACHE_SYNC() { \
HAL_DCACHE_SYNC_L1(); \
- HAL_SYNC_L2(); \
+ /* don't just call HAL_SYNC_L2() */ \
+ HAL_CLEAN_INVALIDATE_L2(); \
}
#define HAL_ICACHE_INVALIDATE_ALL() { \
#define AVIC_INTTYPEL REG32_PTR(AVIC_BASE_ADDR + (0x1C))
/* L210 */
-#define L2CC_BASE_ADDR 0x30000000
#define L2_CACHE_LINE_SIZE 32
#define L2_CACHE_CTL_REG 0x100
#define L2_CACHE_AUX_CTL_REG 0x104
#define L2_CACHE_SYNC_REG 0x730
#define L2_CACHE_INV_LINE_REG 0x770
#define L2_CACHE_INV_WAY_REG 0x77C
-#define L2_CACHE_CLEAN_LINE_REG 0x7B0
-#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
+#define L2_CACHE_CLEAN_LINE_PA_REG 0x7B0
+#define L2_CACHE_CLEAN_LINE_WAY_REG 0x7B8
+#define L2_CACHE_CLEAN_WAY_REG 0x7BC
+#define L2_CACHE_CLEAN_INV_LINE_PA_REG 0x7F0
+#define L2_CACHE_CLEAN_INV_LINE_WAY_REG 0x7F8
+#define L2_CACHE_CLEAN_INV_WAY_REG 0x7FC
/* SPBA */
#define SPBA_IOMUX 0x30
/* UPCTL PD MFD MFI MFN */
#define UPCTL_PARAM_288 (((1-1) << 26) + ((13-1) << 16) + (5 << 10) + (7 << 0))
-
+
#define PDR0_399_133_66 0xFF800550 /* ARM=399MHz, HCLK=133MHz, IPG=66.5MHz */
#define PDR0_399_100_50 0xFF800458 /* ARM=399MHz, HCLK=100MHz, IPG=50MHz */
#define PDR0_399_66_66 0xFF800328 /* ARM=399MHz, HCLK=IPG=66.5MHz */
#define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0)
#define FDO_PAGE_SPARE_VAL 0x8
-#define MXC_NAND_BASE_DUMMY 0xE0000000
-#define NOR_FLASH_BOOT 0
-#define NAND_FLASH_BOOT 0x10000000
-#define SDRAM_NON_FLASH_BOOT 0x20000000
+#define NOR_FLASH_BOOT 0
+#define NAND_FLASH_BOOT 0x10000000
+#define SDRAM_NON_FLASH_BOOT 0x20000000
+#define MMC_BOOT 0x40000000
#define MXCBOOT_FLAG_REG (AVIC_BASE_ADDR + 0x100)
+
#define MXCFIS_NOTHING 0x00000000
#define MXCFIS_NAND 0x10000000
#define MXCFIS_NOR 0x20000000
+#define MXCFIS_MMC 0x40000000
#define MXCFIS_FLAG_REG (AVIC_BASE_ADDR + 0x104)
#define IS_BOOTING_FROM_NAND() (readl(MXCBOOT_FLAG_REG) == NAND_FLASH_BOOT)
#define IS_BOOTING_FROM_NOR() (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
-#define IS_BOOTING_FROM_SDRAM() (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
+#define IS_BOOTING_FROM_SDRAM() (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
+#define IS_BOOTING_FROM_MMC() (readl(MXCBOOT_FLAG_REG) == MMC_BOOT)
#ifndef MXCFLASH_SELECT_NAND
#define IS_FIS_FROM_NAND() 0
#ifndef MXCFLASH_SELECT_NOR
#define IS_FIS_FROM_NOR() 0
#else
-#define IS_FIS_FROM_NOR() (!IS_FIS_FROM_NAND())
+#define IS_FIS_FROM_NOR() (readl(MXCFIS_FLAG_REG) == MXCFIS_NOR)
#endif
-#define MXC_ASSERT_NOR_BOOT() writel(MXCFIS_NOR, MXCFIS_FLAG_REG)
-#define MXC_ASSERT_NAND_BOOT() writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
+#ifndef MXCFLASH_SELECT_MMC
+#define IS_FIS_FROM_MMC() 0
+#else
+#define IS_FIS_FROM_MMC() (readl(MXCFIS_FLAG_REG) == MXCFIS_MMC)
+#endif
+
+#define MXC_ASSERT_NOR_BOOT() writel(MXCFIS_NOR, MXCFIS_FLAG_REG)
+#define MXC_ASSERT_NAND_BOOT() writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
+#define MXC_ASSERT_MMC_BOOT() writel(MXCFIS_MMC, MXCFIS_FLAG_REG)
/*
* This macro is used to get certain bit field from a number
unsigned int get_peri_clock(enum peri_clocks clk);
-enum {
- MXC_NFC_V1,
- MXC_NFC_V2,
-};
-
-typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int);
+typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
#endif //#if !defined(__ASSEMBLER__)
// Now printing clocks
print_clock:
-#ifdef CYGPKG_HAL_ARM_MXC91331_CHIP
- diag_printf("\nMPLL\t\tUPLL\n");
- diag_printf("=========================\n");
- diag_printf("%-16d%-16d\n\n", pll_clock(MCU_PLL), pll_clock(USB_PLL));
-#endif
#ifdef CYGPKG_HAL_ARM_MXC91321_CHIP
diag_printf("\nMPLL\t\tUPLL\t\tTPLL\n");
diag_printf("================================================\n");
ref_clk = (clk_sel != 0) ? pll_clock(USB_PLL) : pll_clock(MCU_PLL);
ret_val = ref_clk / ((pre_pdf + 1) * (pdf + 1));
break;
- case CSI_BAUD:
-#ifdef CYGPKG_HAL_ARM_MXC91331_CHIP
- pdf = (mpdr0 >> 23) & 0x1FF;
- ret_val = pll_clock(USB_PLL) / (pdf + 1);
-#endif
+
#ifdef CYGPKG_HAL_ARM_MXC91321_CHIP
clk_sel = (mcr >> 25) & 0x3;
pdf = ((mpdr0 >> 23) & 0x1FF) + 1;
} else if (argc == 3) {
if (strcasecmp(argv[1], "nandboot") == 0 &&
strcasecmp(argv[2], ready_to_blow) == 0) {
-#if defined(CYGPKG_HAL_ARM_MXC91131) || defined(CYGPKG_HAL_ARM_MX21) || defined(CYGPKG_HAL_ARM_MX27) || defined(CYGPKG_HAL_ARM_MX31)
+#if defined(CYGPKG_HAL_ARM_MX21) || defined(CYGPKG_HAL_ARM_MX27) || defined(CYGPKG_HAL_ARM_MX31)
diag_printf("No need to blow any fuses for NAND boot on this platform\n\n");
#else
diag_printf("Ready to burn NAND boot fuses\n");
#define IIM_SREV_REV_SH 4
#define IIM_SREV_REV_LEN 4
#define PROD_SIGNATURE_MX31 0x1
-#define PROD_SIGNATURE_MXC91331 0x4
#define PROD_SIGNATURE_MXC91321 0x6
-#define PROD_SIGNATURE_MXC91231 0x8
-#define PROD_SIGNATURE_MXC91131 0x10
-#if defined(CYGPKG_HAL_ARM_MXC91331_CHIP)
-#define PROD_SIGNATURE_SUPPORTED PROD_SIGNATURE_MXC91331
-#elif defined(CYGPKG_HAL_ARM_MXC91321_CHIP)
+#if defined(CYGPKG_HAL_ARM_MXC91321_CHIP)
#define PROD_SIGNATURE_SUPPORTED PROD_SIGNATURE_MXC91321
#else
-#error Neither MXC91331 nor MXC91321 defined. What is it?
+#error MXC91321 not defined. What is it?
#endif
#define CHIP_VERSION_NONE 0xFFFFFFFF // invalid product ID
#define CHIP_VERSION_UNKNOWN 0xDEADBEEF // invalid chip rev
find_correct_chip = ver;
-#if defined(CYGPKG_HAL_ARM_MXC91331_CHIP)
- unsigned char chip_ver = readb(INTERNAL_ROM_VA + 0x60);
-
- if (ver != CHIP_VERSION_NONE) {
- /* Valid product revision found. Check actual silicon rev and
- * NOT use the version from the ROM code. */
- switch (ver & 0xFF) {
- case 0x40:
- HAL_PLATFORM_EXTRA[5] = '2';
- HAL_PLATFORM_EXTRA[7] = '1';
- system_rev |= 2 << MAJOR_NUMBER_OFFSET;
- system_rev |= 1 << MINOR_NUMBER_OFFSET;
- break;
- default:
- HAL_PLATFORM_EXTRA[5] = 'x';
- HAL_PLATFORM_EXTRA[7] = 'x';
- HAL_PLATFORM_EXTRA[9] = 'x';
- system_rev |= 1 << MAJOR_NUMBER_OFFSET;
- system_rev |= 0 << MINOR_NUMBER_OFFSET;
- find_correct_chip = CHIP_VERSION_UNKNOWN;
- break;
- }
- } else {
- if (chip_ver == 2) {
- HAL_PLATFORM_EXTRA[5] = '2';
- system_rev |= 2 << MAJOR_NUMBER_OFFSET;
- system_rev |= 0 << MINOR_NUMBER_OFFSET;
- }
- }
-#else
if (ver != CHIP_VERSION_NONE) {
switch (ver & 0xFF) {
case 0x0:
break;
}
}
-#endif // CYGPKG_HAL_ARM_MXC91331_CHIP
if ((esdmisc & 0x4) == 0) {
HAL_PLATFORM_EXTRA[16] = 'S';
unsigned int get_peri_clock(enum peri_clocks clk);
-enum {
- MXC_NFC_V1,
- MXC_NFC_V2,
-};
-
typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int);
#endif //#if !defined(__ASSEMBLER__)
+2006-03-01 Mark Salter <msalter@sadr.localdomain>
+
+ * include/hal_platform_setup.h: Fix DELAY macro.
+
2004-09-20 Mark Salter <msalter@redhat.com>
* cdl/hal_arm_xscale_grg.cdl: Add -mcpu=xscale to LDFLAGS.
// Delay a bit
.macro DELAY cycles, reg0
-#if 0
ldr \reg0, =\cycles
subs \reg0, \reg0, #1
subne pc, pc, #0xc
-#endif
.endm
// ------------------------------------------------------------------------
+2006-03-01 Mark Salter <msalter@sadr.localdomain>
+
+ * include/hal_platform_setup.h: Fix DELAY macro.
+
2004-09-27 Mark Salter <msalter@redhat.com>
* misc/redboot_ROMRAM.ecm: Remove CYGHWR_HAL_IXP425_PCI_NP_WORKAROUND.
// Delay a bit
.macro DELAY cycles, reg0
-#if 0
ldr \reg0, =\cycles
subs \reg0, \reg0, #1
subne pc, pc, #0xc
-#endif
.endm
// ------------------------------------------------------------------------
+2006-03-01 Mark Salter <msalter@sadr.localdomain>
+
+ * include/hal_platform_setup.h: Fix DELAY macro.
+
2004-09-02 Mark Salter <msalter@redhat.com>
* misc/redboot_RAM.ecm: Remove CYGOPT_DEVS_FLASH_STRATA_NOT_IN_RAM.
// Delay a bit
.macro DELAY cycles, reg0
-#if 0
ldr \reg0, =\cycles
subs \reg0, \reg0, #1
subne pc, pc, #0xc
-#endif
.endm
// ------------------------------------------------------------------------
+2005-12-06 David Vrabel <dvrabel@arcom.com>
+
+ * cdl/hal_arm_xscale_pxa2x0.cdl: New
+ CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT option to select support for
+ the PXA25x series or the PXA27x series. The default is PXA25x so
+ existing packages work as-is.
+
+ * include/hal_pxa2x0.h: Add some extra PXA27x specific registers.
+
+ * src/pxa2x0_misc.c, include/hal_var_ints.h: Add support for the
+ extra interrupts (including the extra GPIO ones) on the PXA27x.
+
+ * src/pxa2x0_misc.c (hal_delay_us): Use correct timer clock
+ frequency for PXA27x. Correctly handle the loop taking longer
+ than 1 timer tick.
+
+2005-09-19 David Vrabel <dvrabel@arcom.com>
+
+ * cdl/hal_arm_xscale_pxa2x0.cdl: Fix the last patch, logical OR
+ not bitwise is needed.
+
+2005-09-15 David Vrabel <dvrabel@arcom.com>
+
+ * cdl/hal_arm_xscale_pxa2x0.cdl: Only build hal_diag.c if one of
+ the three internal UARTs is used.
+
2005-04-22 Ian Campbell <icampbell@arcom.com>
* include/hal_pxa2x0.h: OSCC was incorrectly name CSCC.
puts $::cdl_header "#define CYGBLD_HAL_VAR_H <cyg/hal/hal_pxa2x0.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H"
}
+
+ cdl_option CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT {
+ display "PXA2XX processor model"
+ description "
+ This option selects the variant of the PXA2XX family (PXA25x
+ or PXA27x) to support."
+ flavor data
+ legal_values { "PXA25X" "PXA27X" }
+ default_value { "PXA25X" }
+ }
- compile hal_diag.c pxa2x0_misc.c
+ compile pxa2x0_misc.c
# Real-time clock/counter specifics
cdl_component CYGNUM_HAL_RTC_CONSTANTS {
serial port can be used as a diagnostic and/or debug channel."
}
+ cdl_option CYGBLD_BUILD_HAL_ARM_XSCALE_PXA2X0_SERIAL_DIAG {
+ display "Include support for PXA2X0 serial diagnostic/debug channels"
+ default_value { CYGHWR_HAL_ARM_PXA2X0_FFUART
+ || CYGHWR_HAL_ARM_PXA2X0_BTUART
+ || CYGHWR_HAL_ARM_PXA2X0_STUART }
+
+ compile hal_diag.c
+ }
}
#define PXA2X0_ICFP PXA2X0_REGISTER( PXA2X0_IC_BASE+0x000c )
#define PXA2X0_ICPR PXA2X0_REGISTER( PXA2X0_IC_BASE+0x0010 )
#define PXA2X0_ICCR PXA2X0_REGISTER( PXA2X0_IC_BASE+0x0014 )
+#define PXA2X0_ICMR2 PXA2X0_REGISTER( PXA2X0_IC_BASE+0x00a0 )
+#define PXA2X0_ICLR2 PXA2X0_REGISTER( PXA2X0_IC_BASE+0x00a4 )
// GPIO
#define PXA2X0_GPIO_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0e00000 )
#define PXA2X0_GAFR1_U PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0060 )
#define PXA2X0_GAFR2_L PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0064 )
#define PXA2X0_GAFR2_U PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0068 )
+#define PXA2X0_GAFR3_L PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x006c )
+#define PXA2X0_GAFR3_U PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0070 )
+#define PXA2X0_GPLR3 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0100 )
+#define PXA2X0_GPDR3 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x010c )
+#define PXA2X0_GPSR3 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0118 )
+#define PXA2X0_GPCR3 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0124 )
+#define PXA2X0_GRER3 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0130 )
+#define PXA2X0_GFER3 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x013c )
+#define PXA2X0_GEDR3 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0148 )
#define PXA2X0_GPIO_NORM 0x00
#define PXA2X0_GPIO_AF1 0x01
#define PXA2X0_CCCR PXA2X0_REGISTER( PXA2X0_CLK_BASE+0x0000 )
#define PXA2X0_CKEN PXA2X0_REGISTER( PXA2X0_CLK_BASE+0x0004 )
#define PXA2X0_OSCC PXA2X0_REGISTER( PXA2X0_CLK_BASE+0x0008 )
- // Memory Clock
-#define PXA2X0_CCCR_L09 (0x1f)
-#define PXA2X0_CCCR_L27 (0x01)
-#define PXA2X0_CCCR_L32 (0x02)
-#define PXA2X0_CCCR_L36 (0x03)
-#define PXA2X0_CCCR_L40 (0x04)
-#define PXA2X0_CCCR_L45 (0x05)
- // Memory-to-Run-Mode multiplier
-#define PXA2X0_CCCR_M1 (0x1 << 5)
-#define PXA2X0_CCCR_M2 (0x2 << 5)
-#define PXA2X0_CCCR_M4 (0x3 << 5)
- // Run-Mode-to-Turbo-Mode multiplier
-#define PXA2X0_CCCR_N10 (0x2 << 7) // N=1.0
-#define PXA2X0_CCCR_N15 (0x3 << 7) // N=1.5
-#define PXA2X0_CCCR_N20 (0x4 << 7) // N=2.0
-#define PXA2X0_CCCR_N25 (0x5 << 7) // N=2.5
-#define PXA2X0_CCCR_N30 (0x6 << 7) // N=3.0
+// PXA25x CCCR bits
+#ifdef CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA25X
+// Crystal Frequency to Memory Frequency multiplier
+# define PXA2X0_CCCR_L09 (0x1f)
+# define PXA2X0_CCCR_L27 (0x01)
+# define PXA2X0_CCCR_L32 (0x02)
+# define PXA2X0_CCCR_L36 (0x03)
+# define PXA2X0_CCCR_L40 (0x04)
+# define PXA2X0_CCCR_L45 (0x05)
+// Memory frequency to to run mode frequency multiplier
+# define PXA2X0_CCCR_M1 (0x1 << 5)
+# define PXA2X0_CCCR_M2 (0x2 << 5)
+# define PXA2X0_CCCR_M4 (0x3 << 5)
+// Run mode frequency to turbo mode frequency multiplier
+# define PXA2X0_CCCR_N10 (0x2 << 7) // N=1.0
+# define PXA2X0_CCCR_N15 (0x3 << 7) // N=1.5
+# define PXA2X0_CCCR_N20 (0x4 << 7) // N=2.0
+# define PXA2X0_CCCR_N25 (0x5 << 7) // N=2.5
+# define PXA2X0_CCCR_N30 (0x6 << 7) // N=3.0
+#endif
+
+// PXA27x CCCR bits
+#ifdef CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X
+// Run-mode-to-oscillator ratio
+# define PXA27X_CCCR_L8 (0x08)
+# define PXA27X_CCCR_L16 (0x10)
+// Turbo-mode-to-run-mode ratio
+# define PXA27X_CCCR_N1 (0x02 << 7)
+# define PXA27X_CCCR_N1_5 (0x03 << 7)
+# define PXA27X_CCCR_N2 (0x04 << 7)
+# define PXA27X_CCCR_N2_5 (0x05 << 7)
+# define PXA27X_CCCR_N3 (0x06 << 7)
+
+# define PXA27X_CCCR_A (0x02000000)
+# define PXA27X_CCCR_PLL_EARLY_EN (0x04000000)
+# define PXA27X_CCCR_LCD_26 (0x08000000)
+# define PXA27X_CCCR_PPDIS (0x40000000)
+# define PXA27X_CCCR_CPDIS (0x80000000)
+#endif
// LCD Controller
#define PXA2X0_LCCR0 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0000 )
#include <cyg/hal/hal_pxa2x0.h>
// 1st level
-// 0-7 Reserved
+#define CYGNUM_HAL_INTERRUPT_SSP3 0
+#define CYGNUM_HAL_INTERRUPT_MSL 1
+#define CYGNUM_HAL_INTERRUPT_USBH2 2
+#define CYGNUM_HAL_INTERRUPT_USBH1 3
+#define CYGNUM_HAL_INTERRUPT_KEYPAD 4
+#define CYGNUM_HAL_INTERRUPT_MEMSTK 5
+#define CYGNUM_HAL_INTERRUPT_PWRI2C 6
+#define CYGNUM_HAL_INTERRUPT_OST_4_11 7
#define CYGNUM_HAL_INTERRUPT_GPIO0 8
#define CYGNUM_HAL_INTERRUPT_GPIO1 9
-#define CYGNUM_HAL_INTERRUPT_GPIO 10
+#define CYGNUM_HAL_INTERRUPT_GPIOX 10
#define CYGNUM_HAL_INTERRUPT_USB 11
#define CYGNUM_HAL_INTERRUPT_PMU 12
#define CYGNUM_HAL_INTERRUPT_I2S 13
#define CYGNUM_HAL_INTERRUPT_AC97 14
-// 15,16 Reserved
+#define CYGNUM_HAL_INTERRUPT_ASSP 15 /* PXA25x */
+#define CYGNUM_HAL_INTERRUPT_USIM 15 /* PXA27x */
+#define CYGNUM_HAL_INTERRUT_NSSP 16
#define CYGNUM_HAL_INTERRUPT_LCD 17
#define CYGNUM_HAL_INTERRUPT_I2C 18
#define CYGNUM_HAL_INTERRUPT_ICP 19
#define CYGNUM_HAL_INTERRUPT_HZ 30
#define CYGNUM_HAL_INTERRUPT_ALARM 31
+#if defined (CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X)
+
+#define CYGNUM_HAL_INTERRUPT_TPM 32
+#define CYGNUM_HAL_INTERRUPT_CAMERA 33
+
+#define CYGNUM_HAL_INTERNAL_IRQS 34
+
+#elif defined(CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA25X)
+
+#define CYGNUM_HAL_INTERNAL_IRQS 32
// 2nd level
#define CYGNUM_HAL_INTERRUPT_GPIO2 (32+2)
#define CYGNUM_HAL_INTERRUPT_GPIO84 (96+20)
#define CYGNUM_HAL_INTERRUPT_GPIO85 (96+21)
+#endif
+
+#define CYGNUM_HAL_INTERRUPT_GPIO(i) \
+ (((i) < 2) ? (CYGNUM_HAL_INTERRUPT_GPIO0 + (i)) : (CYGNUM_HAL_INTERNAL_IRQS + (i)))
#define CYGNUM_HAL_INTERRUPT_NONE -1
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0
#define CYGNUM_HAL_ISR_MIN 0
-#define CYGNUM_HAL_ISR_MAX (96+21)
+#if defined CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA25X
+# define CYGNUM_HAL_ISR_MAX (96+21)
+#elif defined CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X
+# define CYGNUM_HAL_ISR_MAX (CYGNUM_HAL_INTERNAL_IRQS + 121)
+#endif
#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX-CYGNUM_HAL_ISR_MIN+1)
#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
*PXA2X0_GFER1 = 0;
*PXA2X0_GFER2 = 0;
+#if defined(CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA25X)
*PXA2X0_GEDR0 = 0xffffffff; // Clear edge detect status
*PXA2X0_GEDR1 = 0xffffffff;
*PXA2X0_GEDR2 = 0x0001ffff;
+#elif defined(CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X)
+ *PXA2X0_ICMR2 = 0;
+ *PXA2X0_ICLR2 = 0;
+
+ *PXA2X0_GRER3 = 0;
+ *PXA2X0_GFER3 = 0;
+
+ *PXA2X0_GEDR0 = 0xfffff71b;
+ *PXA2X0_GEDR1 = 0xffffffff;
+ *PXA2X0_GEDR2 = 0xffffffff;
+ *PXA2X0_GEDR3 = 0x1fffffff;
+#endif
plf_hardware_init(); // Perform any platform specific initializations
// Delay for some number of micro-seconds
void hal_delay_us(cyg_int32 usecs)
{
+#if defined(CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA25X)
+# define NSECS_PER_TICK 271267 /* 3.6865 MHz clock */
+#elif defined(CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X)
+# define NSECS_PER_TICK 307692 /* 3.25 MHz clock */
+#endif
+
cyg_uint32 val = 0;
- cyg_uint32 ctr = *PXA2X0_OSCR;
+ cyg_uint32 prev = *PXA2X0_OSCR;
while (usecs-- > 0) {
- do {
- if (ctr != *PXA2X0_OSCR) {
- val += 271267; // 271267ps (3.6865Mhz -> 271.267ns)
- ++ctr;
- }
- } while (val < 1000000);
+ while (val < 1000000) {
+ cyg_uint32 now = *PXA2X0_OSCR;
+ cyg_uint32 diff = now - prev;
+ val += NSECS_PER_TICK * diff;
+ prev = now;
+ }
val -= 1000000;
}
}
do {
if ( (1 << index) & sources ) {
- if (index == CYGNUM_HAL_INTERRUPT_GPIO) {
+ if (index == CYGNUM_HAL_INTERRUPT_GPIOX) {
// Special case of GPIO cascade. Search for lowest set bit
sources = *PXA2X0_GEDR0;
index = 0;
do {
if (sources & (1 << index)) {
- return index+32;
+ return CYGNUM_HAL_INTERNAL_IRQS + index;
}
index++;
} while (index < 32);
index = 0;
do {
if (sources & (1 << index)) {
- return index+64;
+ return CYGNUM_HAL_INTERNAL_IRQS + 32 + index;
}
index++;
} while (index < 32);
index = 0;
do {
if (sources & (1 << index)) {
- return index+96;
+ return CYGNUM_HAL_INTERNAL_IRQS + 64 + index;
}
index++;
- } while (index < 21);
-
+ } while (index < 32);
+#ifdef CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X
+ sources = *PXA2X0_GEDR3;
+ index = 0;
+ do {
+ if (sources & (1 << index)) {
+ return CYGNUM_HAL_INTERNAL_IRQS + 96 + index;
+ }
+ index++;
+ } while (index < 32);
+#endif
}
return index;
}
// Normal vectors are handled by code subsequent to the macro call.
HAL_EXTENDED_INTERRUPT_MASK(vector);
#endif
-
- if (vector >= CYGNUM_HAL_INTERRUPT_GPIO2) {
- vector = CYGNUM_HAL_INTERRUPT_GPIO;
+#ifdef CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X
+ if (vector >= 32 && vector < CYGNUM_HAL_INTERNAL_IRQS) {
+ *PXA2X0_ICMR2 &= ~(1 << (vector - 32));
+ return;
+ }
+#endif
+ if (vector >= CYGNUM_HAL_INTERRUPT_GPIO(2)) {
+ vector = CYGNUM_HAL_INTERRUPT_GPIOX;
}
*PXA2X0_ICMR &= ~(1 << vector);
}
// Normal vectors are handled by code subsequent to the macro call.
HAL_EXTENDED_INTERRUPT_UNMASK(vector);
#endif
-
- if (vector >= CYGNUM_HAL_INTERRUPT_GPIO2) {
- vector = CYGNUM_HAL_INTERRUPT_GPIO;
+#ifdef CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X
+ if (vector >= 32 && vector < CYGNUM_HAL_INTERNAL_IRQS) {
+ *PXA2X0_ICMR2 |= (1 << (vector - 32));
+ return;
+ }
+#endif
+ if (vector >= CYGNUM_HAL_INTERRUPT_GPIO(2)) {
+ vector = CYGNUM_HAL_INTERRUPT_GPIOX;
}
*PXA2X0_ICMR |= (1 << vector);
}
// Normal vectors are handled by code subsequent to the macro call.
HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector);
#endif
- if (vector == CYGNUM_HAL_INTERRUPT_GPIO0 || vector == CYGNUM_HAL_INTERRUPT_GPIO1)
- {
- *PXA2X0_GEDR0 = (1 << (vector - 8));
- }else{
- if (vector >= CYGNUM_HAL_INTERRUPT_GPIO64) {
- *PXA2X0_GEDR2 = (1 << (vector - 96));
- } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO32) {
- *PXA2X0_GEDR1 = (1 << (vector - 64));
- } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO2) {
- *PXA2X0_GEDR0 = (1 << (vector - 32));
- } else {
- // Not a GPIO interrupt
- return;
- }
- }
+ if (vector == CYGNUM_HAL_INTERRUPT_GPIO0 || vector == CYGNUM_HAL_INTERRUPT_GPIO1) {
+ *PXA2X0_GEDR0 = (1 << (vector - 8));
+ } else {
+#ifdef CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X
+ if (vector >= CYGNUM_HAL_INTERRUPT_GPIO(96)) {
+ *PXA2X0_GEDR3 = (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 96));
+ } else
+#endif
+ if (vector >= CYGNUM_HAL_INTERRUPT_GPIO(64)) {
+ *PXA2X0_GEDR2 = (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 64));
+ } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO(32)) {
+ *PXA2X0_GEDR1 = (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 32));
+ } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO(2)) {
+ *PXA2X0_GEDR0 = (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS));
+ } else {
+ // Not a GPIO interrupt
+ return;
+ }
+ }
}
void hal_interrupt_configure(int vector, int level, int up)
{
+ cyg_bool falling = level || !up;
+ cyg_bool rising = level || up;
#ifdef HAL_EXTENDED_INTERRUPT_CONFIGURE
// Use platform specific handling, if defined
// Normal vectors are handled by code subsequent to the macro call.
HAL_EXTENDED_INTERRUPT_CONFIGURE(vector, level, up);
#endif
- if (vector >= CYGNUM_HAL_INTERRUPT_GPIO64) {
- if (level) {
- if (up) {
- // Enable both edges
- *PXA2X0_GRER2 |= (1 << (vector - 96));
- *PXA2X0_GFER2 |= (1 << (vector - 96));
- } else {
- // Disable both edges
- *PXA2X0_GRER2 &= ~(1 << (vector - 96));
- *PXA2X0_GFER2 &= ~(1 << (vector - 96));
- }
- } else {
- // Only interested in one edge
- if (up) {
- // Set rising edge detect and clear falling edge detect.
- *PXA2X0_GRER2 |= (1 << (vector - 96));
- *PXA2X0_GFER2 &= ~(1 << (vector - 96));
- } else {
- // Set falling edge detect and clear rising edge detect.
- *PXA2X0_GFER2 |= (1 << (vector - 96));
- *PXA2X0_GRER2 &= ~(1 << (vector - 96));
- }
- }
- } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO32) {
- if (level) {
- if (up) {
- // Enable both edges
- *PXA2X0_GRER1 |= (1 << (vector - 64));
- *PXA2X0_GFER1 |= (1 << (vector - 64));
- } else {
- // Disable both edges
- *PXA2X0_GRER1 &= ~(1 << (vector - 64));
- *PXA2X0_GFER1 &= ~(1 << (vector - 64));
- }
- } else {
- // Only interested in one edge
- if (up) {
- // Set rising edge detect and clear falling edge detect.
- *PXA2X0_GRER1 |= (1 << (vector - 64));
- *PXA2X0_GFER1 &= ~(1 << (vector - 64));
- } else {
- // Set falling edge detect and clear rising edge detect.
- *PXA2X0_GFER1 |= (1 << (vector - 64));
- *PXA2X0_GRER1 &= ~(1 << (vector - 64));
- }
- }
- } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO2) {
- if (level) {
- if (up) {
- // Enable both edges
- *PXA2X0_GRER0 |= (1 << (vector - 32));
- *PXA2X0_GFER0 |= (1 << (vector - 32));
- } else {
- // Disable both edges
- *PXA2X0_GRER0 &= ~(1 << (vector - 32));
- *PXA2X0_GFER0 &= ~(1 << (vector - 32));
- }
- } else {
- // Only interested in one edge
- if (up) {
- // Set rising edge detect and clear falling edge detect.
- *PXA2X0_GRER0 |= (1 << (vector - 32));
- *PXA2X0_GFER0 &= ~(1 << (vector - 32));
- } else {
- // Set falling edge detect and clear rising edge detect.
- *PXA2X0_GFER0 |= (1 << (vector - 32));
- *PXA2X0_GRER0 &= ~(1 << (vector - 32));
- }
- }
- } else if (vector == CYGNUM_HAL_INTERRUPT_GPIO0 || vector == CYGNUM_HAL_INTERRUPT_GPIO1)
- {
- if (level) {
- if (up) {
- // Enable both edges
- *PXA2X0_GRER0 |= (1 << (vector - 8));
- *PXA2X0_GFER0 |= (1 << (vector - 8));
- } else {
- // Disable both edges
- *PXA2X0_GRER0 &= ~(1 << (vector - 8));
- *PXA2X0_GFER0 &= ~(1 << (vector - 8));
- }
- } else {
- // Only interested in one edge
- if (up) {
- // Set rising edge detect and clear falling edge detect.
- *PXA2X0_GRER0 |= (1 << (vector - 8));
- *PXA2X0_GFER0 &= ~(1 << (vector - 8));
- } else {
- // Set falling edge detect and clear rising edge detect.
- *PXA2X0_GFER0 |= (1 << (vector - 8));
- *PXA2X0_GRER0 &= ~(1 << (vector - 8));
- }
- }
- }
-
-
+#ifdef CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X
+ if (vector >= CYGNUM_HAL_INTERRUPT_GPIO(96)) {
+ if (falling)
+ *PXA2X0_GFER3 |= (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 96));
+ else
+ *PXA2X0_GFER3 &= ~(1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 96));
+ if (rising)
+ *PXA2X0_GRER3 |= (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 96));
+ else
+ *PXA2X0_GRER3 &= ~(1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 96));
+ } else
+#endif
+ if (vector >= CYGNUM_HAL_INTERRUPT_GPIO(64)) {
+ if (falling)
+ *PXA2X0_GFER2 |= (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 64));
+ else
+ *PXA2X0_GFER2 &= ~(1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 64));
+ if (rising)
+ *PXA2X0_GRER2 |= (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 64));
+ else
+ *PXA2X0_GRER2 &= ~(1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 64));
+ } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO(32)) {
+ if (falling)
+ *PXA2X0_GFER1 |= (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 32));
+ else
+ *PXA2X0_GFER1 &= ~(1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 32));
+ if (rising)
+ *PXA2X0_GRER1 |= (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 32));
+ else
+ *PXA2X0_GRER1 &= ~(1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 32));
+ } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO(2)) {
+ if (falling)
+ *PXA2X0_GFER1 |= (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS));
+ else
+ *PXA2X0_GFER1 &= ~(1 << (vector - CYGNUM_HAL_INTERNAL_IRQS));
+ if (rising)
+ *PXA2X0_GRER1 |= (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS));
+ else
+ *PXA2X0_GRER1 &= ~(1 << (vector - CYGNUM_HAL_INTERNAL_IRQS));
+ } else if (vector == CYGNUM_HAL_INTERRUPT_GPIO0 || vector == CYGNUM_HAL_INTERRUPT_GPIO1) {
+ if (falling)
+ *PXA2X0_GFER0 |= (1 << (vector - 8));
+ else
+ *PXA2X0_GFER0 &= ~(1 << (vector - 8));
+ if (rising)
+ *PXA2X0_GRER0 |= (1 << (vector - 8));
+ else
+ *PXA2X0_GRER0 &= ~(1 << (vector - 8));
+ }
}
void hal_interrupt_set_level(int vector, int level)
+2007-09-27 Grant Edwards <grante@visi.com>
+
+ * include/hal_endian.h (SWAP16): Fix "return value" so
+ that it only returns data in lower 16 bits instead of 24.
+
+2006-05-09 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/hal_if.c (cyg_hal_diag_mangler_gdb_flush): Fix compiler
+ warning about signed/unsigned.
+
+2006-04-19 Alexander Neundorf <alexander.neundorf@jenoptik.com
+
+ * include/hal_if.h, src/hal_if.c: add a VV call for modifying
+ the FIS table from eCos applications
+
2005-06-27 Andrew Lunn <andrew.lunn@ascom.ch>
* include/hal_tables.h (CYG_HAL_TABLE_{QUALIFIED_}ENTRY): added
#ifndef CYG_SWAP16
# define CYG_SWAP16(_x_) \
- ({ cyg_uint16 _x = (_x_); ((_x << 8) | (_x >> 8)); })
+ ({ cyg_uint16 _x = (_x_); (cyg_uint16)((_x << 8) | (_x >> 8)); })
#endif
#ifndef CYG_SWAP32
typedef int (*__comm_if_control_t)(void *__ch_data,
__comm_control_cmd_t __func, ...);
typedef int (*__comm_if_dbg_isr_t)(void *__ch_data,
- int* __ctrlc, CYG_ADDRWORD __vector,
+ int* __ctrlc, CYG_ADDRWORD __vec,
CYG_ADDRWORD __data);
-typedef cyg_bool (*__comm_if_getc_timeout_t)(void* __ch_data, cyg_uint8* __ch);
+typedef cyg_bool (*__comm_if_getc_timeout_t)(void *__ch_data, void *__ch);
#define __call_COMM0(_n_,_rt_,_t_) \
static __inline__ _rt_ \
#define CYGACC_COMM_IF_DBG_ISR_SET(_t_, _x_) \
(_t_)[CYGNUM_COMM_IF_DBG_ISR]=(CYG_ADDRWORD)(_x_)
-__call_COMM1(IF_GETC_TIMEOUT, cyg_bool, __comm_if_getc_timeout_t, cyg_uint8 *)
+__call_COMM1(IF_GETC_TIMEOUT, cyg_bool, __comm_if_getc_timeout_t, void *)
#define CYGACC_COMM_IF_GETC_TIMEOUT(_t_, _c_) \
__call_COMM_IF_GETC_TIMEOUT(_t_, _c_)
#define CYGACC_COMM_IF_GETC_TIMEOUT_SET(_t_, _x_) \
#define CYGNUM_CALL_IF_FLASH_CFG_OP 20
#define CYGNUM_CALL_IF_MONITOR_RETURN 21
#define CYGNUM_CALL_IF_FLASH_FIS_OP 22
+#define CYGNUM_CALL_IF_FLASH_FIS_OP2 23
-#define CYGNUM_CALL_IF_LAST_ENTRY CYGNUM_CALL_IF_FLASH_FIS_OP
+#define CYGNUM_CALL_IF_LAST_ENTRY CYGNUM_CALL_IF_FLASH_FIS_OP2
#define CYGNUM_CALL_IF_INSTALL_BPT_FN 35
typedef char *__call_if_monitor_version_t;
typedef void (__call_if_monitor_return_t)(int status);
typedef cyg_bool (__call_if_flash_fis_op_fn_t)(int __oper, char *__name, void *__val);
+
+//
+// This structure is used to pass parameters to/from the fis routines
+//
+struct fis_table_entry {
+ unsigned char name[16];
+ CYG_ADDRESS flash_base;
+ CYG_ADDRESS mem_base;
+ unsigned long size;
+ CYG_ADDRESS entry_point;
+ unsigned long data_length;
+ unsigned long desc_cksum;
+ unsigned long file_cksum;
+};
+
+typedef int (__call_if_flash_fis_op2_fn_t)(int __oper, unsigned int index, struct fis_table_entry *__fis_entry);
//
// This structure is used to pass parameters to/from the fconfig routines.
// This allows a single virtual vector interface, with widely varying functionality
#define CYGNUM_CALL_IF_FLASH_FIS_GET_DESC_CKSUM (5)
#define CYGNUM_CALL_IF_FLASH_FIS_GET_FILE_CKSUM (6)
+#define CYGACC_CALL_IF_FLASH_FIS_OP2(_o_,_k_,_d_) \
+ CYGACC_CALL_VV3(__call_if_flash_fis_op2_fn_t*, CYGNUM_CALL_IF_FLASH_FIS_OP2, (_o_),(_k_),(_d_))
+__call_VV3(CYGNUM_CALL_IF_FLASH_FIS_OP2, __call_if_flash_fis_op2_fn_t, int, int, unsigned int, struct fis_table_entry *)
+#define CYGACC_CALL_IF_FLASH_FIS_OP2_SET(_x_) \
+ hal_virtual_vector_table[CYGNUM_CALL_IF_FLASH_FIS_OP2]=(CYG_ADDRWORD)(_x_)
+#define CYGNUM_CALL_IF_FLASH_FIS_GET_VERSION (0)
+#define CYGNUM_CALL_IF_FLASH_FIS_INIT (1)
+#define CYGNUM_CALL_IF_FLASH_FIS_GET_ENTRY_COUNT (2)
+#define CYGNUM_CALL_IF_FLASH_FIS_GET_ENTRY (3)
+#define CYGNUM_CALL_IF_FLASH_FIS_START_UPDATE (4)
+#define CYGNUM_CALL_IF_FLASH_FIS_FINISH_UPDATE (5)
+#define CYGNUM_CALL_IF_FLASH_FIS_MODIFY_ENTRY (6)
+
+
// These need to be kept uptodate with the (unadorned) masters
// in RedBoot's flash_config.h:
//=============================================================================
//
-// hal_if.c
+// hal_if.c
//
-// ROM/RAM interfacing functions
+// ROM/RAM interfacing functions
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
-// Author(s): jskov
+// Author(s): jskov
// Contributors:jskov, woehler
-// Date: 2000-06-07
+// Date: 2000-06-07
//
//####DESCRIPTIONEND####
//
# include <pkgconf/kernel.h>
#endif
-#include <cyg/infra/cyg_ass.h> // assertions
+#include <cyg/infra/cyg_ass.h> // assertions
-#include <cyg/hal/hal_arch.h> // set/restore GP
+#include <cyg/hal/hal_arch.h> // set/restore GP
-#include <cyg/hal/hal_io.h> // IO macros
-#include <cyg/hal/hal_if.h> // our interface
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_if.h> // our interface
-#include <cyg/hal/hal_diag.h> // Diag IO
-#include <cyg/hal/hal_misc.h> // User break
+#include <cyg/hal/hal_diag.h> // Diag IO
+#include <cyg/hal/hal_misc.h> // User break
-#include <cyg/hal/hal_stub.h> // stub functionality
+#include <cyg/hal/hal_stub.h> // stub functionality
-#include <cyg/hal/hal_intr.h> // hal_vsr_table and others
+#include <cyg/hal/hal_intr.h> // hal_vsr_table and others
#ifdef CYGPKG_REDBOOT
#include <pkgconf/redboot.h>
static cyg_bool
flash_config_op(int op, struct cyg_fconfig *fc)
{
- cyg_bool res = false;
-
- CYGARC_HAL_SAVE_GP();
-
- switch (op) {
- case CYGNUM_CALL_IF_FLASH_CFG_GET:
- res = flash_get_config(fc->key, fc->val, fc->type);
- break;
- case CYGNUM_CALL_IF_FLASH_CFG_NEXT:
- res = flash_next_key(fc->key, fc->keylen, &fc->type, &fc->offset);
- break;
- case CYGNUM_CALL_IF_FLASH_CFG_SET:
- res = flash_set_config(fc->key, fc->val, fc->type);
- break;
- default:
- // nothing else supported yet - though it is expected that "set"
- // will fit the same set of arguments, potentially.
- break;
- }
-
- CYGARC_HAL_RESTORE_GP();
- return res;
+ cyg_bool res = false;
+
+ CYGARC_HAL_SAVE_GP();
+
+ switch (op) {
+ case CYGNUM_CALL_IF_FLASH_CFG_GET:
+ res = flash_get_config(fc->key, fc->val, fc->type);
+ break;
+ case CYGNUM_CALL_IF_FLASH_CFG_NEXT:
+ res = flash_next_key(fc->key, fc->keylen, &fc->type, &fc->offset);
+ break;
+ case CYGNUM_CALL_IF_FLASH_CFG_SET:
+ res = flash_set_config(fc->key, fc->val, fc->type);
+ break;
+ default:
+ // nothing else supported yet - though it is expected that "set"
+ // will fit the same set of arguments, potentially.
+ break;
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
}
#endif
static cyg_bool
flash_fis_op( int op, char *name, void *val)
{
- cyg_bool res = false;
- struct fis_image_desc *fis;
- int num;
-
- CYGARC_HAL_SAVE_GP();
- fis = fis_lookup(name, &num);
- if(fis != NULL)
- {
- switch ( op ) {
- case CYGNUM_CALL_IF_FLASH_FIS_GET_FLASH_BASE:
- *(CYG_ADDRESS *)val = fis->flash_base;
- res = true;
- break;
- case CYGNUM_CALL_IF_FLASH_FIS_GET_SIZE:
- *(unsigned long *)val = fis->size;
- res = true;
- break;
- case CYGNUM_CALL_IF_FLASH_FIS_GET_MEM_BASE:
- *(CYG_ADDRESS *)val = fis->mem_base;
- res = true;
- break;
- case CYGNUM_CALL_IF_FLASH_FIS_GET_ENTRY_POINT:
- *(CYG_ADDRESS *)val = fis->entry_point;
- res = true;
- break;
- case CYGNUM_CALL_IF_FLASH_FIS_GET_DATA_LENGTH:
- *(unsigned long *)val = fis->data_length;
- res = true;
- break;
- case CYGNUM_CALL_IF_FLASH_FIS_GET_DESC_CKSUM:
- *(unsigned long *)val = fis->desc_cksum;
- res = true;
- break;
- case CYGNUM_CALL_IF_FLASH_FIS_GET_FILE_CKSUM:
- *(unsigned long *)val = fis->file_cksum;
- res = true;
- break;
- default:
- break;
- }
- }
- CYGARC_HAL_RESTORE_GP();
- return res;
+ cyg_bool res = false;
+ struct fis_image_desc *fis;
+ int num;
+
+ CYGARC_HAL_SAVE_GP();
+ fis = fis_lookup(name, &num);
+ if (fis != NULL) {
+ switch (op) {
+ case CYGNUM_CALL_IF_FLASH_FIS_GET_FLASH_BASE:
+ *(CYG_ADDRESS *)val = fis->flash_base;
+ res = true;
+ break;
+ case CYGNUM_CALL_IF_FLASH_FIS_GET_SIZE:
+ *(unsigned long *)val = fis->size;
+ res = true;
+ break;
+ case CYGNUM_CALL_IF_FLASH_FIS_GET_MEM_BASE:
+ *(CYG_ADDRESS *)val = fis->mem_base;
+ res = true;
+ break;
+ case CYGNUM_CALL_IF_FLASH_FIS_GET_ENTRY_POINT:
+ *(CYG_ADDRESS *)val = fis->entry_point;
+ res = true;
+ break;
+ case CYGNUM_CALL_IF_FLASH_FIS_GET_DATA_LENGTH:
+ *(unsigned long *)val = fis->data_length;
+ res = true;
+ break;
+ case CYGNUM_CALL_IF_FLASH_FIS_GET_DESC_CKSUM:
+ *(unsigned long *)val = fis->desc_cksum;
+ res = true;
+ break;
+ case CYGNUM_CALL_IF_FLASH_FIS_GET_FILE_CKSUM:
+ *(unsigned long *)val = fis->file_cksum;
+ res = true;
+ break;
+ }
+ }
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+#include <cyg/io/flash.h>
+
+extern int __flash_init;
+extern int fisdir_size;
+extern int flash_block_size;
+extern void* fis_addr;
+#ifdef CYGOPT_REDBOOT_REDUNDANT_FIS
+extern void* redundant_fis_addr;
+#endif
+extern void* fis_work_block;
+extern int do_flash_init(void);
+extern int fis_start_update_directory(int autolock);
+extern int fis_update_directory(int autolock, int error);
+
+static __call_if_flash_fis_op2_fn_t flash_fis_op2;
+
+static int
+flash_fis_op2( int op, unsigned int index, struct fis_table_entry *entry)
+{
+ int res = 0;
+ CYGARC_HAL_SAVE_GP();
+ switch (op) {
+ case CYGNUM_CALL_IF_FLASH_FIS_GET_VERSION:
+ res = CYG_REDBOOT_FIS_VERSION;
+ break;
+ case CYGNUM_CALL_IF_FLASH_FIS_INIT:
+ __flash_init=0; //force reinitialization
+ res = do_flash_init();
+ break;
+ case CYGNUM_CALL_IF_FLASH_FIS_GET_ENTRY_COUNT:
+ res = fisdir_size / sizeof(struct fis_image_desc);
+ break;
+ case CYGNUM_CALL_IF_FLASH_FIS_GET_ENTRY:
+ {
+ struct fis_image_desc* img = (struct fis_image_desc *)fis_work_block;
+ CYG_ASSERT(entry != NULL, "fis_table_entry == NULL!");
+ memcpy(entry->name, img[index].u.name, 16);
+ entry->flash_base=img[index].flash_base;
+ entry->mem_base=img[index].mem_base;
+ entry->size=img[index].size;
+ entry->entry_point=img[index].entry_point;
+ entry->data_length=img[index].data_length;
+ entry->desc_cksum=img[index].desc_cksum;
+ entry->file_cksum=img[index].file_cksum;
+ res = 0;
+ }
+ break;
+ case CYGNUM_CALL_IF_FLASH_FIS_START_UPDATE:
+ fis_start_update_directory(1);
+ break;
+ case CYGNUM_CALL_IF_FLASH_FIS_FINISH_UPDATE:
+ fis_update_directory(1, index);
+ break;
+ case CYGNUM_CALL_IF_FLASH_FIS_MODIFY_ENTRY:
+ res = 0;
+ if (entry->name[0]!=0xff) {
+ if ((entry->size == 0)
+ || ((entry->size % flash_block_size) !=0)
+ || (flash_verify_addr((void*)entry->flash_base)!=0)
+ || (flash_verify_addr((void*)(entry->flash_base+entry->size-1))!=0)
+ || (entry->size < entry->data_length))
+ res = -1;
+ }
+
+ if (res == 0) {
+ struct fis_image_desc* img = (struct fis_image_desc *)fis_work_block;
+ memcpy(img[index].u.name, entry->name, 16);
+ img[index].flash_base=entry->flash_base;
+ img[index].mem_base=entry->mem_base;
+ img[index].size=entry->size;
+ img[index].entry_point=entry->entry_point;
+ img[index].data_length=entry->data_length;
+ img[index].desc_cksum=entry->desc_cksum;
+ img[index].file_cksum=entry->file_cksum;
+ }
+ break;
+ }
+ CYGARC_HAL_RESTORE_GP();
+ return res;
}
#endif
static void
delay_us(cyg_int32 usecs)
{
- CYGARC_HAL_SAVE_GP();
+ CYGARC_HAL_SAVE_GP();
#ifdef CYGPKG_KERNEL
- {
- cyg_int32 start, elapsed, elapsed_usec;
- cyg_int32 slice;
- cyg_int32 usec_per_period = CYGNUM_HAL_RTC_NUMERATOR/CYGNUM_HAL_RTC_DENOMINATOR/1000;
- cyg_int32 ticks_per_usec = CYGNUM_KERNEL_COUNTERS_RTC_PERIOD/usec_per_period;
-
- do {
- // Spin in slices of 1/2 the RTC period. Allows interrupts
- // time to run without messing up the algorithm. If we
- // spun for 1 period (or more) of the RTC, there would also
- // be problems figuring out when the timer wrapped. We
- // may lose a tick or two for each cycle but it shouldn't
- // matter much.
-
- // The tests against CYGNUM_KERNEL_COUNTERS_RTC_PERIOD
- // check for a value that would cause a 32 bit signed
- // multiply to overflow. But this also implies that just
- // multiplying by ticks_per_usec will yield a good
- // approximation. Otherwise we need to do the full
- // multiply+divide to get sufficient accuracy. Note that
- // this test is actually constant, so the compiler will
- // eliminate it and only compile the branch that is
- // selected.
-
- if( usecs > usec_per_period/2 )
- slice = CYGNUM_KERNEL_COUNTERS_RTC_PERIOD/2;
- else if( CYGNUM_KERNEL_COUNTERS_RTC_PERIOD/2 >= 0x7FFFFFFF/usec_per_period )
- slice = usecs * ticks_per_usec;
- else
- {
- slice = usecs*CYGNUM_KERNEL_COUNTERS_RTC_PERIOD;
- slice /= usec_per_period;
- }
-
- HAL_CLOCK_READ(&start);
- do {
- HAL_CLOCK_READ(&elapsed);
- elapsed = (elapsed - start); // counts up!
- if (elapsed < 0)
- elapsed += CYGNUM_KERNEL_COUNTERS_RTC_PERIOD;
- } while (elapsed < slice);
-
- // Adjust by elapsed, not slice, since an interrupt may
- // have been stalling us for some time.
-
- if( CYGNUM_KERNEL_COUNTERS_RTC_PERIOD >= 0x7FFFFFFF/usec_per_period )
- elapsed_usec = elapsed / ticks_per_usec;
- else
- {
- elapsed_usec = elapsed * usec_per_period;
- elapsed_usec = elapsed_usec / CYGNUM_KERNEL_COUNTERS_RTC_PERIOD;
- }
-
- // It is possible for elapsed_usec to end up zero in some
- // circumstances and we could end up looping indefinitely.
- // Avoid that by ensuring that we always decrement usec by
- // at least 1 each time.
-
- usecs -= elapsed_usec ? elapsed_usec : 1;
-
- } while (usecs > 0);
- }
+ {
+ cyg_int32 start, elapsed, elapsed_usec;
+ cyg_int32 slice;
+ cyg_int32 usec_per_period = CYGNUM_HAL_RTC_NUMERATOR/CYGNUM_HAL_RTC_DENOMINATOR/1000;
+ cyg_int32 ticks_per_usec = CYGNUM_KERNEL_COUNTERS_RTC_PERIOD/usec_per_period;
+
+ do {
+ // Spin in slices of 1/2 the RTC period. Allows interrupts
+ // time to run without messing up the algorithm. If we
+ // spun for 1 period (or more) of the RTC, there would also
+ // be problems figuring out when the timer wrapped. We
+ // may lose a tick or two for each cycle but it shouldn't
+ // matter much.
+
+ // The tests against CYGNUM_KERNEL_COUNTERS_RTC_PERIOD
+ // check for a value that would cause a 32 bit signed
+ // multiply to overflow. But this also implies that just
+ // multiplying by ticks_per_usec will yield a good
+ // approximation. Otherwise we need to do the full
+ // multiply+divide to get sufficient accuracy. Note that
+ // this test is actually constant, so the compiler will
+ // eliminate it and only compile the branch that is
+ // selected.
+
+ if( usecs > usec_per_period/2 )
+ slice = CYGNUM_KERNEL_COUNTERS_RTC_PERIOD/2;
+ else if( CYGNUM_KERNEL_COUNTERS_RTC_PERIOD/2 >= 0x7FFFFFFF/usec_per_period )
+ slice = usecs * ticks_per_usec;
+ else
+ {
+ slice = usecs*CYGNUM_KERNEL_COUNTERS_RTC_PERIOD;
+ slice /= usec_per_period;
+ }
+
+ HAL_CLOCK_READ(&start);
+ do {
+ HAL_CLOCK_READ(&elapsed);
+ elapsed = (elapsed - start); // counts up!
+ if (elapsed < 0)
+ elapsed += CYGNUM_KERNEL_COUNTERS_RTC_PERIOD;
+ } while (elapsed < slice);
+
+ // Adjust by elapsed, not slice, since an interrupt may
+ // have been stalling us for some time.
+
+ if( CYGNUM_KERNEL_COUNTERS_RTC_PERIOD >= 0x7FFFFFFF/usec_per_period )
+ elapsed_usec = elapsed / ticks_per_usec;
+ else
+ {
+ elapsed_usec = elapsed * usec_per_period;
+ elapsed_usec = elapsed_usec / CYGNUM_KERNEL_COUNTERS_RTC_PERIOD;
+ }
+
+ // It is possible for elapsed_usec to end up zero in some
+ // circumstances and we could end up looping indefinitely.
+ // Avoid that by ensuring that we always decrement usec by
+ // at least 1 each time.
+
+ usecs -= elapsed_usec ? elapsed_usec : 1;
+
+ } while (usecs > 0);
+ }
#else // CYGPKG_KERNEL
#ifdef HAL_DELAY_US
- // Use a HAL feature if defined
- HAL_DELAY_US(usecs);
+ // Use a HAL feature if defined
+ HAL_DELAY_US(usecs);
#else
- // If no accurate delay mechanism, just spin for a while. Having
- // an inaccurate delay is much better than no delay at all. The
- // count of 10 should mean the loop takes something resembling
- // 1us on most CPUs running between 30-100MHz [depends on how many
- // instructions this compiles to, how many dispatch units can be
- // used for the simple loop, actual CPU frequency, etc]
- while (usecs-- > 0) {
- int i;
- for (i = 0; i < 10; i++);
- }
+ // If no accurate delay mechanism, just spin for a while. Having
+ // an inaccurate delay is much better than no delay at all. The
+ // count of 10 should mean the loop takes something resembling
+ // 1us on most CPUs running between 30-100MHz [depends on how many
+ // instructions this compiles to, how many dispatch units can be
+ // used for the simple loop, actual CPU frequency, etc]
+ while (usecs-- > 0) {
+ int i;
+ for (i = 0; i < 10; i++);
+ }
#endif // HAL_DELAY_US
#endif // CYGPKG_KERNEL
- CYGARC_HAL_RESTORE_GP();
+ CYGARC_HAL_RESTORE_GP();
}
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US
static void
reset(void)
{
- CYGARC_HAL_SAVE_GP();
- // With luck, the platform defines some magic that will cause a hardware
- // reset.
+ CYGARC_HAL_SAVE_GP();
+ // With luck, the platform defines some magic that will cause a hardware
+ // reset.
#ifdef HAL_PLATFORM_RESET
- HAL_PLATFORM_RESET();
+ HAL_PLATFORM_RESET();
#endif
#ifdef HAL_PLATFORM_RESET_ENTRY
- // If that's not the case (above is an empty statement) there may
- // be defined an address we can jump to - and effectively
- // reinitialize the system. Not quite as good as a reset, but it
- // is often enough.
- goto *HAL_PLATFORM_RESET_ENTRY;
+ // If that's not the case (above is an empty statement) there may
+ // be defined an address we can jump to - and effectively
+ // reinitialize the system. Not quite as good as a reset, but it
+ // is often enough.
+ goto *HAL_PLATFORM_RESET_ENTRY;
#else
#error " no RESET_ENTRY"
#endif
- CYG_FAIL("Reset failed");
- CYGARC_HAL_RESTORE_GP();
+ CYG_FAIL("Reset failed");
+ CYGARC_HAL_RESTORE_GP();
}
#endif
//------------------------------------
// NOP service
#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE) || \
- defined(CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS)
+ defined(CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS)
static int
nop_service(void)
{
- // This is the default service. It always returns false (0), and
- // _does not_ trigger any assertions. Clients must either cope
- // with the service failure or assert.
- return 0;
+ // This is the default service. It always returns false (0), and
+ // _does not_ trigger any assertions. Clients must either cope
+ // with the service failure or assert.
+ return 0;
}
#endif
static int
set_debug_comm(int __comm_id)
{
- static int __selected_id = CYGNUM_CALL_IF_SET_COMM_ID_EMPTY;
- hal_virtual_comm_table_t* __chan;
- int interrupt_state = 0;
- int res = 1, update = 0;
- CYGARC_HAL_SAVE_GP();
-
- CYG_ASSERT(__comm_id >= CYGNUM_CALL_IF_SET_COMM_ID_MANGLER
- && __comm_id < CYGNUM_HAL_VIRTUAL_VECTOR_NUM_CHANNELS,
- "Invalid channel");
-
- switch (__comm_id) {
- case CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT:
- if (__selected_id > 0)
- res = __selected_id-1;
- else if (__selected_id == 0)
- res = CYGNUM_CALL_IF_SET_COMM_ID_MANGLER;
- else
- res = __selected_id;
- break;
-
- case CYGNUM_CALL_IF_SET_COMM_ID_EMPTY:
- CYGACC_CALL_IF_DEBUG_PROCS_SET(0);
- __selected_id = __comm_id;
- break;
-
- case CYGNUM_CALL_IF_SET_COMM_ID_MANGLER:
- __comm_id = 0;
- update = 1;
- break;
-
- default:
- __comm_id++; // skip mangler entry
- update = 1;
- break;
- }
-
- if (update) {
- // Find the interrupt state of the channel.
- __chan = CYGACC_CALL_IF_DEBUG_PROCS();
- if (__chan)
- interrupt_state = CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_IRQ_DISABLE);
-
- __selected_id = __comm_id;
- CYGACC_CALL_IF_DEBUG_PROCS_SET(comm_channels[__comm_id]);
-
- // Set interrupt state on the new channel.
- __chan = CYGACC_CALL_IF_DEBUG_PROCS();
- if (interrupt_state)
- CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_IRQ_ENABLE);
- else
- CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_IRQ_DISABLE);
- }
-
- CYGARC_HAL_RESTORE_GP();
- return res;
+ static int __selected_id = CYGNUM_CALL_IF_SET_COMM_ID_EMPTY;
+ hal_virtual_comm_table_t* __chan;
+ int interrupt_state = 0;
+ int res = 1, update = 0;
+ CYGARC_HAL_SAVE_GP();
+
+ CYG_ASSERT(__comm_id >= CYGNUM_CALL_IF_SET_COMM_ID_MANGLER
+ && __comm_id < CYGNUM_HAL_VIRTUAL_VECTOR_NUM_CHANNELS,
+ "Invalid channel");
+
+ switch (__comm_id) {
+ case CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT:
+ if (__selected_id > 0)
+ res = __selected_id-1;
+ else if (__selected_id == 0)
+ res = CYGNUM_CALL_IF_SET_COMM_ID_MANGLER;
+ else
+ res = __selected_id;
+ break;
+
+ case CYGNUM_CALL_IF_SET_COMM_ID_EMPTY:
+ CYGACC_CALL_IF_DEBUG_PROCS_SET(0);
+ __selected_id = __comm_id;
+ break;
+
+ case CYGNUM_CALL_IF_SET_COMM_ID_MANGLER:
+ __comm_id = 0;
+ update = 1;
+ break;
+
+ default:
+ __comm_id++; // skip mangler entry
+ update = 1;
+ break;
+ }
+
+ if (update) {
+ // Find the interrupt state of the channel.
+ __chan = CYGACC_CALL_IF_DEBUG_PROCS();
+ if (__chan)
+ interrupt_state = CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_IRQ_DISABLE);
+
+ __selected_id = __comm_id;
+ CYGACC_CALL_IF_DEBUG_PROCS_SET(comm_channels[__comm_id]);
+
+ // Set interrupt state on the new channel.
+ __chan = CYGACC_CALL_IF_DEBUG_PROCS();
+ if (interrupt_state)
+ CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_IRQ_ENABLE);
+ else
+ CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_IRQ_DISABLE);
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
}
static int
set_console_comm(int __comm_id)
{
- static int __selected_id = CYGNUM_CALL_IF_SET_COMM_ID_EMPTY;
- int res = 1, update = 0;
- CYGARC_HAL_SAVE_GP();
-
- CYG_ASSERT(__comm_id >= CYGNUM_CALL_IF_SET_COMM_ID_MANGLER
- && __comm_id < CYGNUM_HAL_VIRTUAL_VECTOR_NUM_CHANNELS,
- "Invalid channel");
-
- switch (__comm_id) {
- case CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT:
- if (__selected_id > 0)
- res = __selected_id-1;
- else if (__selected_id == 0)
- res = CYGNUM_CALL_IF_SET_COMM_ID_MANGLER;
- else
- res = __selected_id;
- break;
-
- case CYGNUM_CALL_IF_SET_COMM_ID_EMPTY:
- CYGACC_CALL_IF_CONSOLE_PROCS_SET(0);
- __selected_id = __comm_id;
- break;
-
- case CYGNUM_CALL_IF_SET_COMM_ID_MANGLER:
- __comm_id = 0;
- update = 1;
- break;
-
- default:
- __comm_id++; // skip mangler entry
- update = 1;
- break;
- }
-
- if (update) {
- __selected_id = __comm_id;
-
- CYGACC_CALL_IF_CONSOLE_PROCS_SET(comm_channels[__comm_id]);
- }
-
- CYGARC_HAL_RESTORE_GP();
- return res;
+ static int __selected_id = CYGNUM_CALL_IF_SET_COMM_ID_EMPTY;
+ int res = 1, update = 0;
+ CYGARC_HAL_SAVE_GP();
+
+ CYG_ASSERT(__comm_id >= CYGNUM_CALL_IF_SET_COMM_ID_MANGLER
+ && __comm_id < CYGNUM_HAL_VIRTUAL_VECTOR_NUM_CHANNELS,
+ "Invalid channel");
+
+ switch (__comm_id) {
+ case CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT:
+ if (__selected_id > 0)
+ res = __selected_id-1;
+ else if (__selected_id == 0)
+ res = CYGNUM_CALL_IF_SET_COMM_ID_MANGLER;
+ else
+ res = __selected_id;
+ break;
+
+ case CYGNUM_CALL_IF_SET_COMM_ID_EMPTY:
+ CYGACC_CALL_IF_CONSOLE_PROCS_SET(0);
+ __selected_id = __comm_id;
+ break;
+
+ case CYGNUM_CALL_IF_SET_COMM_ID_MANGLER:
+ __comm_id = 0;
+ update = 1;
+ break;
+
+ default:
+ __comm_id++; // skip mangler entry
+ update = 1;
+ break;
+ }
+
+ if (update) {
+ __selected_id = __comm_id;
+
+ CYGACC_CALL_IF_CONSOLE_PROCS_SET(comm_channels[__comm_id]);
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
}
#endif
static void
flush_icache(void *__p, int __nbytes)
{
- CYGARC_HAL_SAVE_GP();
+ CYGARC_HAL_SAVE_GP();
#ifdef HAL_ICACHE_FLUSH
- HAL_ICACHE_FLUSH( __p , __nbytes );
+ HAL_ICACHE_FLUSH( __p , __nbytes );
#elif defined(HAL_ICACHE_INVALIDATE)
- HAL_ICACHE_INVALIDATE();
+ HAL_ICACHE_INVALIDATE();
#endif
- CYGARC_HAL_RESTORE_GP();
+ CYGARC_HAL_RESTORE_GP();
}
static void
flush_dcache(void *__p, int __nbytes)
{
- CYGARC_HAL_SAVE_GP();
+ CYGARC_HAL_SAVE_GP();
#ifdef HAL_DCACHE_FLUSH
- HAL_DCACHE_FLUSH( __p , __nbytes );
+ HAL_DCACHE_FLUSH( __p , __nbytes );
#elif defined(HAL_DCACHE_INVALIDATE)
- HAL_DCACHE_INVALIDATE();
+ HAL_DCACHE_INVALIDATE();
#endif
- CYGARC_HAL_RESTORE_GP();
+ CYGARC_HAL_RESTORE_GP();
}
#endif
static cyg_uint8
cyg_hal_diag_mangler_gdb_getc(void* __ch_data)
{
- cyg_uint8 __ch;
- hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_DEBUG_PROCS();
- CYGARC_HAL_SAVE_GP();
+ cyg_uint8 __ch;
+ hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_DEBUG_PROCS();
+ CYGARC_HAL_SAVE_GP();
- __ch = CYGACC_COMM_IF_GETC(*__chan);
+ __ch = CYGACC_COMM_IF_GETC(*__chan);
- CYGARC_HAL_RESTORE_GP();
+ CYGARC_HAL_RESTORE_GP();
- return __ch;
+ return __ch;
}
static char __mangler_line[100];
-static int __mangler_pos = 0;
+static int __mangler_pos = 0;
static void
cyg_hal_diag_mangler_gdb_flush(void* __ch_data)
{
- CYG_INTERRUPT_STATE old;
- hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_DEBUG_PROCS();
+ CYG_INTERRUPT_STATE old;
+ hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_DEBUG_PROCS();
#if CYGNUM_HAL_DEBUG_GDB_PROTOCOL_RETRIES != 0
- int tries = CYGNUM_HAL_DEBUG_GDB_PROTOCOL_RETRIES;
+ int tries = CYGNUM_HAL_DEBUG_GDB_PROTOCOL_RETRIES;
#endif
- // Nothing to do if mangler buffer is empty.
- if (__mangler_pos == 0)
- return;
+ // Nothing to do if mangler buffer is empty.
+ if (__mangler_pos == 0)
+ return;
- // Disable interrupts. This prevents GDB trying to interrupt us
- // while we are in the middle of sending a packet. The serial
- // receive interrupt will be seen when we re-enable interrupts
- // later.
+ // Disable interrupts. This prevents GDB trying to interrupt us
+ // while we are in the middle of sending a packet. The serial
+ // receive interrupt will be seen when we re-enable interrupts
+ // later.
#if defined(CYG_HAL_STARTUP_ROM) \
- || !defined(CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION)
- HAL_DISABLE_INTERRUPTS(old);
+ || !defined(CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION)
+ HAL_DISABLE_INTERRUPTS(old);
#else
- CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+ CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
#endif
-
+
#if CYGNUM_HAL_DEBUG_GDB_PROTOCOL_RETRIES != 0
- // Only wait 500ms for data to arrive - avoid "stuck" connections
- CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_SET_TIMEOUT, CYGNUM_HAL_DEBUG_GDB_PROTOCOL_TIMEOUT);
+ // Only wait 500ms for data to arrive - avoid "stuck" connections
+ CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_SET_TIMEOUT, CYGNUM_HAL_DEBUG_GDB_PROTOCOL_TIMEOUT);
#endif
- while(1)
- {
+ while(1)
+ {
static const char hex[] = "0123456789ABCDEF";
- cyg_uint8 csum = 0, c1;
+ cyg_uint8 csum = 0;
+ char c1;
int i;
-
+
CYGACC_COMM_IF_PUTC(*__chan, '$');
CYGACC_COMM_IF_PUTC(*__chan, 'O');
csum += 'O';
for( i = 0; i < __mangler_pos; i++ )
- {
- char ch = __mangler_line[i];
- char h = hex[(ch>>4)&0xF];
- char l = hex[ch&0xF];
- CYGACC_COMM_IF_PUTC(*__chan, h);
- CYGACC_COMM_IF_PUTC(*__chan, l);
- csum += h;
- csum += l;
+ {
+ char ch = __mangler_line[i];
+ char h = hex[(ch>>4)&0xF];
+ char l = hex[ch&0xF];
+ CYGACC_COMM_IF_PUTC(*__chan, h);
+ CYGACC_COMM_IF_PUTC(*__chan, l);
+ csum += h;
+ csum += l;
}
CYGACC_COMM_IF_PUTC(*__chan, '#');
CYGACC_COMM_IF_PUTC(*__chan, hex[(csum>>4)&0xF]);
CYGACC_COMM_IF_PUTC(*__chan, hex[csum&0xF]);
- nak:
+ nak:
#if CYGNUM_HAL_DEBUG_GDB_PROTOCOL_RETRIES != 0
if (CYGACC_COMM_IF_GETC_TIMEOUT(*__chan, &c1) == 0) {
- c1 = '-';
- if (tries && (--tries == 0)) c1 = '+';
+ c1 = '-';
+ if (tries && (--tries == 0)) c1 = '+';
}
#else
c1 = CYGACC_COMM_IF_GETC(*__chan);
if( c1 == '+' ) break;
if( cyg_hal_is_break( &c1 , 1 ) ) {
- // Caller's responsibility to react on this.
- CYGACC_CALL_IF_CONSOLE_INTERRUPT_FLAG_SET(1);
- break;
+ // Caller's responsibility to react on this.
+ CYGACC_CALL_IF_CONSOLE_INTERRUPT_FLAG_SET(1);
+ break;
}
if( c1 != '-' ) goto nak;
- }
+ }
- __mangler_pos = 0;
- // And re-enable interrupts
+ __mangler_pos = 0;
+ // And re-enable interrupts
#if defined(CYG_HAL_STARTUP_ROM) \
- || !defined(CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION)
- HAL_RESTORE_INTERRUPTS(old);
+ || !defined(CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION)
+ HAL_RESTORE_INTERRUPTS(old);
#else
- CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+ CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
#endif
}
static void
cyg_hal_diag_mangler_gdb_putc(void* __ch_data, cyg_uint8 c)
{
- // No need to send CRs
- if( c == '\r' ) return;
+ // No need to send CRs
+ if( c == '\r' ) return;
- CYGARC_HAL_SAVE_GP();
+ CYGARC_HAL_SAVE_GP();
- __mangler_line[__mangler_pos++] = c;
+ __mangler_line[__mangler_pos++] = c;
- if( c == '\n' || __mangler_pos == sizeof(__mangler_line) )
+ if( c == '\n' || __mangler_pos == sizeof(__mangler_line) )
cyg_hal_diag_mangler_gdb_flush(__ch_data);
- CYGARC_HAL_RESTORE_GP();
+ CYGARC_HAL_RESTORE_GP();
}
static void
cyg_hal_diag_mangler_gdb_write(void* __ch_data,
- const cyg_uint8* __buf, cyg_uint32 __len)
+ const cyg_uint8* __buf, cyg_uint32 __len)
{
- CYGARC_HAL_SAVE_GP();
+ CYGARC_HAL_SAVE_GP();
- while(__len-- > 0)
- cyg_hal_diag_mangler_gdb_putc(__ch_data, *__buf++);
+ while(__len-- > 0)
+ cyg_hal_diag_mangler_gdb_putc(__ch_data, *__buf++);
- CYGARC_HAL_RESTORE_GP();
+ CYGARC_HAL_RESTORE_GP();
}
static void
-cyg_hal_diag_mangler_gdb_read(void* __ch_data,
- cyg_uint8* __buf, cyg_uint32 __len)
+cyg_hal_diag_mangler_gdb_read(void* __ch_data,
+ cyg_uint8* __buf, cyg_uint32 __len)
{
- CYGARC_HAL_SAVE_GP();
+ CYGARC_HAL_SAVE_GP();
- while(__len-- > 0)
- *__buf++ = cyg_hal_diag_mangler_gdb_getc(__ch_data);
+ while(__len-- > 0)
+ *__buf++ = cyg_hal_diag_mangler_gdb_getc(__ch_data);
- CYGARC_HAL_RESTORE_GP();
+ CYGARC_HAL_RESTORE_GP();
}
static int
-cyg_hal_diag_mangler_gdb_control(void *__ch_data,
- __comm_control_cmd_t __func, ...)
+cyg_hal_diag_mangler_gdb_control(void *__ch_data,
+ __comm_control_cmd_t __func, ...)
{
- CYGARC_HAL_SAVE_GP();
+ CYGARC_HAL_SAVE_GP();
- if (__func == __COMMCTL_FLUSH_OUTPUT)
+ if (__func == __COMMCTL_FLUSH_OUTPUT)
cyg_hal_diag_mangler_gdb_flush(__ch_data);
- CYGARC_HAL_RESTORE_GP();
- return 0;
+ CYGARC_HAL_RESTORE_GP();
+ return 0;
}
// This is the COMMS init function. It gets called both by the stubs
void
cyg_hal_diag_mangler_gdb_init(void)
{
- hal_virtual_comm_table_t* comm;
- int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
-
- // Initialize mangler procs
- CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_MANGLER);
- comm = CYGACC_CALL_IF_CONSOLE_PROCS();
- CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_diag_mangler_gdb_write);
- CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_diag_mangler_gdb_read);
- CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_diag_mangler_gdb_putc);
- CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_diag_mangler_gdb_getc);
- CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_diag_mangler_gdb_control);
-
- // Restore the original console channel.
- CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+ hal_virtual_comm_table_t* comm;
+ int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+ // Initialize mangler procs
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_MANGLER);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_diag_mangler_gdb_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_diag_mangler_gdb_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_diag_mangler_gdb_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_diag_mangler_gdb_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_diag_mangler_gdb_control);
+
+ // Restore the original console channel.
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
//-----------------------------------------------------------------------------
static cyg_uint8
cyg_hal_diag_mangler_null_getc(void* __ch_data)
{
- cyg_uint8 __ch;
- hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_DEBUG_PROCS();
- CYGARC_HAL_SAVE_GP();
+ cyg_uint8 __ch;
+ hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_DEBUG_PROCS();
+ CYGARC_HAL_SAVE_GP();
- __ch = CYGACC_COMM_IF_GETC(*__chan);
+ __ch = CYGACC_COMM_IF_GETC(*__chan);
- CYGARC_HAL_RESTORE_GP();
+ CYGARC_HAL_RESTORE_GP();
- return __ch;
+ return __ch;
}
static void
cyg_hal_diag_mangler_null_putc(void* __ch_data, cyg_uint8 c)
{
- hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_DEBUG_PROCS();
+ hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_DEBUG_PROCS();
- CYGARC_HAL_SAVE_GP();
+ CYGARC_HAL_SAVE_GP();
- CYGACC_COMM_IF_PUTC(*__chan, c);
+ CYGACC_COMM_IF_PUTC(*__chan, c);
- CYGARC_HAL_RESTORE_GP();
+ CYGARC_HAL_RESTORE_GP();
}
static void
cyg_hal_diag_mangler_null_write(void* __ch_data,
- const cyg_uint8* __buf, cyg_uint32 __len)
+ const cyg_uint8* __buf, cyg_uint32 __len)
{
- CYGARC_HAL_SAVE_GP();
+ CYGARC_HAL_SAVE_GP();
- while(__len-- > 0)
- cyg_hal_diag_mangler_null_putc(__ch_data, *__buf++);
+ while(__len-- > 0)
+ cyg_hal_diag_mangler_null_putc(__ch_data, *__buf++);
- CYGARC_HAL_RESTORE_GP();
+ CYGARC_HAL_RESTORE_GP();
}
static void
-cyg_hal_diag_mangler_null_read(void* __ch_data,
- cyg_uint8* __buf, cyg_uint32 __len)
+cyg_hal_diag_mangler_null_read(void* __ch_data,
+ cyg_uint8* __buf, cyg_uint32 __len)
{
- CYGARC_HAL_SAVE_GP();
+ CYGARC_HAL_SAVE_GP();
- while(__len-- > 0)
- *__buf++ = cyg_hal_diag_mangler_null_getc(__ch_data);
+ while(__len-- > 0)
+ *__buf++ = cyg_hal_diag_mangler_null_getc(__ch_data);
- CYGARC_HAL_RESTORE_GP();
+ CYGARC_HAL_RESTORE_GP();
}
static int
-cyg_hal_diag_mangler_null_control(void *__ch_data,
- __comm_control_cmd_t __func, ...)
+cyg_hal_diag_mangler_null_control(void *__ch_data,
+ __comm_control_cmd_t __func, ...)
{
- // Do nothing (yet).
- return 0;
+ // Do nothing (yet).
+ return 0;
}
// This is the COMMS init function. It gets called both by the stubs
void
cyg_hal_diag_mangler_null_init(void)
{
- hal_virtual_comm_table_t* comm;
- int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
-
- // Initialize mangler procs
- CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_MANGLER);
- comm = CYGACC_CALL_IF_CONSOLE_PROCS();
- CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_diag_mangler_null_write);
- CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_diag_mangler_null_read);
- CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_diag_mangler_null_putc);
- CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_diag_mangler_null_getc);
- CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_diag_mangler_null_control);
-
- // Restore the original console channel.
- CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+ hal_virtual_comm_table_t* comm;
+ int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+ // Initialize mangler procs
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_MANGLER);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_diag_mangler_null_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_diag_mangler_null_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_diag_mangler_null_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_diag_mangler_null_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_diag_mangler_null_control);
+
+ // Restore the original console channel.
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
//-----------------------------------------------------------------------------
void
hal_if_diag_init(void)
{
- // This function may be called from various places and the code
- // should only run once.
- static cyg_uint8 called = 0;
- if (called) return;
- called = 1;
+ // This function may be called from various places and the code
+ // should only run once.
+ static cyg_uint8 called = 0;
+ if (called) return;
+ called = 1;
#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE
#if defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
- // Use the mangler channel, which in turn uses the debug channel.
- CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_MANGLER);
+ // Use the mangler channel, which in turn uses the debug channel.
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_MANGLER);
- // Initialize the mangler channel.
+ // Initialize the mangler channel.
#if defined(CYGSEM_HAL_DIAG_MANGLER_GDB)
- cyg_hal_diag_mangler_gdb_init();
+ cyg_hal_diag_mangler_gdb_init();
#elif defined(CYGSEM_HAL_DIAG_MANGLER_None)
- cyg_hal_diag_mangler_null_init();
+ cyg_hal_diag_mangler_null_init();
#endif
#else // CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
- // Use an actual (raw) IO channel
- CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL);
+ // Use an actual (raw) IO channel
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL);
#endif // CYGDBG_HAL_DIAG_TO_DEBUG_CHAN
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE
}
-void
+void
hal_if_diag_write_char(char c)
{
- hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_CONSOLE_PROCS();
-
- if (__chan)
- CYGACC_COMM_IF_PUTC(*__chan, c);
- else {
- __chan = CYGACC_CALL_IF_DEBUG_PROCS();
-
- // FIXME: What should be done if assertions are not enabled?
- // This is a bad bad situation - we have no means for diag
- // output; we want to hit a breakpoint to alert the developer
- // or something like that.
- CYG_ASSERT(__chan, "No valid channel set");
-
- CYGACC_COMM_IF_PUTC(*__chan, c);
- }
-
- // Check interrupt flag
- if (CYGACC_CALL_IF_CONSOLE_INTERRUPT_FLAG()) {
- CYGACC_CALL_IF_CONSOLE_INTERRUPT_FLAG_SET(0);
- cyg_hal_user_break(0);
- }
+ hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_CONSOLE_PROCS();
+
+ if (__chan)
+ CYGACC_COMM_IF_PUTC(*__chan, c);
+ else {
+ __chan = CYGACC_CALL_IF_DEBUG_PROCS();
+
+ // FIXME: What should be done if assertions are not enabled?
+ // This is a bad bad situation - we have no means for diag
+ // output; we want to hit a breakpoint to alert the developer
+ // or something like that.
+ CYG_ASSERT(__chan, "No valid channel set");
+
+ CYGACC_COMM_IF_PUTC(*__chan, c);
+ }
+
+ // Check interrupt flag
+ if (CYGACC_CALL_IF_CONSOLE_INTERRUPT_FLAG()) {
+ CYGACC_CALL_IF_CONSOLE_INTERRUPT_FLAG_SET(0);
+ cyg_hal_user_break(0);
+ }
}
-void
+void
hal_if_diag_read_char(char *c)
{
- hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_CONSOLE_PROCS();
-
- if (__chan)
- *c = CYGACC_COMM_IF_GETC(*__chan);
- else {
- __chan = CYGACC_CALL_IF_DEBUG_PROCS();
-
- // FIXME: What should be done if assertions are not enabled?
- // This is a bad bad situation - we have no means for diag
- // output; we want to hit a breakpoint to alert the developer
- // or something like that.
- CYG_ASSERT(__chan, "No valid channel set");
-
- *c = CYGACC_COMM_IF_GETC(*__chan);
- }
+ hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_CONSOLE_PROCS();
+
+ if (__chan)
+ *c = CYGACC_COMM_IF_GETC(*__chan);
+ else {
+ __chan = CYGACC_CALL_IF_DEBUG_PROCS();
+
+ // FIXME: What should be done if assertions are not enabled?
+ // This is a bad bad situation - we have no means for diag
+ // output; we want to hit a breakpoint to alert the developer
+ // or something like that.
+ CYG_ASSERT(__chan, "No valid channel set");
+
+ *c = CYGACC_COMM_IF_GETC(*__chan);
+ }
}
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
//=============================================================================
#if defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) \
- || defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT)
+ || defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT)
struct Hal_SavedRegisters *hal_saved_interrupt_state;
void
hal_ctrlc_isr_init(void)
{
- // A ROM monitor never enables the interrupt itself. This is left
- // to the (RAM) application.
+ // A ROM monitor never enables the interrupt itself. This is left
+ // to the (RAM) application.
#ifndef CYGSEM_HAL_ROM_MONITOR
- hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_DEBUG_PROCS();
+ hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_DEBUG_PROCS();
#if 1 // Prevents crash on older stubs
- int v_m;
- // Allow only ctrl-c interrupt enabling when version in table is
- // below legal max and above the necessary service, and _not_
- // the value we set it to below.
- v_m = CYGACC_CALL_IF_VERSION() & CYGNUM_CALL_IF_TABLE_VERSION_CALL_MASK;
- if (v_m >= CYGNUM_CALL_IF_TABLE_VERSION_CALL_MAX
- || v_m < CYGNUM_CALL_IF_SET_DEBUG_COMM
- || v_m == CYGNUM_CALL_IF_TABLE_VERSION_CALL_HACK)
- return;
-
- // Now trash that value - otherwise downloading an image with
- // builtin stubs on a board with older stubs (which will cause the
- // version to be set to VERSION_CALL) may cause all subsequent
- // runs to (wrongly) fall through to the below code. If there is
- // a new stub on the board, it will reinitialize the version field
- // on reset. Yes, this is a gross hack!
- CYGACC_CALL_IF_VERSION_SET(CYGNUM_CALL_IF_TABLE_VERSION_CALL_HACK);
+ int v_m;
+ // Allow only ctrl-c interrupt enabling when version in table is
+ // below legal max and above the necessary service, and _not_
+ // the value we set it to below.
+ v_m = CYGACC_CALL_IF_VERSION() & CYGNUM_CALL_IF_TABLE_VERSION_CALL_MASK;
+ if (v_m >= CYGNUM_CALL_IF_TABLE_VERSION_CALL_MAX
+ || v_m < CYGNUM_CALL_IF_SET_DEBUG_COMM
+ || v_m == CYGNUM_CALL_IF_TABLE_VERSION_CALL_HACK)
+ return;
+
+ // Now trash that value - otherwise downloading an image with
+ // builtin stubs on a board with older stubs (which will cause the
+ // version to be set to VERSION_CALL) may cause all subsequent
+ // runs to (wrongly) fall through to the below code. If there is
+ // a new stub on the board, it will reinitialize the version field
+ // on reset. Yes, this is a gross hack!
+ CYGACC_CALL_IF_VERSION_SET(CYGNUM_CALL_IF_TABLE_VERSION_CALL_HACK);
#endif
- // We can only enable interrupts on a valid debug channel.
- if (__chan)
- CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_IRQ_ENABLE);
+ // We can only enable interrupts on a valid debug channel.
+ if (__chan)
+ CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_IRQ_ENABLE);
#endif
}
cyg_uint32
hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
- hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_DEBUG_PROCS();
- int isr_ret = 0, ctrlc = 0;
-
- if (__chan) {
- isr_ret = CYGACC_COMM_IF_DBG_ISR(*__chan, &ctrlc, vector, data);
- if (ctrlc)
- cyg_hal_user_break( (CYG_ADDRWORD *)hal_saved_interrupt_state );
- }
- return isr_ret;
+ hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_DEBUG_PROCS();
+ int isr_ret = 0, ctrlc = 0;
+
+ if (__chan) {
+ isr_ret = CYGACC_COMM_IF_DBG_ISR(*__chan, &ctrlc, vector, data);
+ if (ctrlc)
+ cyg_hal_user_break( (CYG_ADDRWORD *)hal_saved_interrupt_state );
+ }
+ return isr_ret;
}
cyg_bool
hal_ctrlc_check(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
- hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_DEBUG_PROCS();
- int gdb_vector = vector-1;
- int isr_ret, ctrlc = 0;
-
- // This check only to avoid crash on older stubs in case of unhandled
- // interrupts. It is a bit messy, but required in a transition period.
- if (__chan &&
- (CYGNUM_CALL_IF_TABLE_VERSION_CALL_HACK ==
- (CYGACC_CALL_IF_VERSION() & CYGNUM_CALL_IF_TABLE_VERSION_CALL_MASK))){
- gdb_vector = CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_DBG_ISR_VECTOR);
- }
- if (vector == gdb_vector) {
- isr_ret = CYGACC_COMM_IF_DBG_ISR(*__chan, &ctrlc, vector, data);
- if (ctrlc) {
- cyg_hal_user_break( (CYG_ADDRWORD *)hal_saved_interrupt_state );
- return true;
- }
- }
- return false;
+ hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_DEBUG_PROCS();
+ int gdb_vector = vector-1;
+ int isr_ret, ctrlc = 0;
+
+ // This check only to avoid crash on older stubs in case of unhandled
+ // interrupts. It is a bit messy, but required in a transition period.
+ if (__chan &&
+ (CYGNUM_CALL_IF_TABLE_VERSION_CALL_HACK ==
+ (CYGACC_CALL_IF_VERSION() & CYGNUM_CALL_IF_TABLE_VERSION_CALL_MASK))){
+ gdb_vector = CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_DBG_ISR_VECTOR);
+ }
+ if (vector == gdb_vector) {
+ isr_ret = CYGACC_COMM_IF_DBG_ISR(*__chan, &ctrlc, vector, data);
+ if (ctrlc) {
+ cyg_hal_user_break( (CYG_ADDRWORD *)hal_saved_interrupt_state );
+ return true;
+ }
+ }
+ return false;
}
#endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT || CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
void
hal_if_init(void)
{
- //**********************************************************************
- //
- // Note that if your RAM application is configured to initialize
- // the whole table _or_ the communication channels, you _cannot_
- // step through this function with the debugger. If your channel
- // configurations are set to the default, you should be able to
- // simply step over this function though (or use 'finish' once you
- // have entered this function if that GDB command works).
- //
- // If you really do need to debug this code, the best approach is
- // to have a working RedBoot / GDB stub in ROM and then change the
- // hal_virtual_vector_table to reside at some other address in the
- // RAM configuration than that used by the ROM monitor. Then
- // you'll be able to use the ROM monitor to debug the below code
- // and check that it does the right thing.
- //
- // Note that if you have a ROM monitor in ROM/flash which does
- // support virtual vectors, you should be able to disable the
- // option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE. On some
- // targets (which predate the introduction of virtual vectors)
- // that option is enabled per default and needs to be explicitly
- // disabled when you have an updated ROM monitor.
- //
- //**********************************************************************
+ //**********************************************************************
+ //
+ // Note that if your RAM application is configured to initialize
+ // the whole table _or_ the communication channels, you _cannot_
+ // step through this function with the debugger. If your channel
+ // configurations are set to the default, you should be able to
+ // simply step over this function though (or use 'finish' once you
+ // have entered this function if that GDB command works).
+ //
+ // If you really do need to debug this code, the best approach is
+ // to have a working RedBoot / GDB stub in ROM and then change the
+ // hal_virtual_vector_table to reside at some other address in the
+ // RAM configuration than that used by the ROM monitor. Then
+ // you'll be able to use the ROM monitor to debug the below code
+ // and check that it does the right thing.
+ //
+ // Note that if you have a ROM monitor in ROM/flash which does
+ // support virtual vectors, you should be able to disable the
+ // option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE. On some
+ // targets (which predate the introduction of virtual vectors)
+ // that option is enabled per default and needs to be explicitly
+ // disabled when you have an updated ROM monitor.
+ //
+ //**********************************************************************
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE
- {
- int i;
-
- // Initialize tables with the NOP service.
- // This should only be done for service routine entries - data
- // pointers should be NULLed.
- for (i = 0; i < CYGNUM_CALL_IF_TABLE_SIZE; i++)
- hal_virtual_vector_table[i] = (CYG_ADDRWORD) &nop_service;
-
- // Version number
- CYGACC_CALL_IF_VERSION_SET(CYGNUM_CALL_IF_TABLE_VERSION_CALL
- |((CYG_ADDRWORD)CYGNUM_CALL_IF_TABLE_VERSION_COMM<<CYGNUM_CALL_IF_TABLE_VERSION_COMM_shift));
- }
+ {
+ int i;
+
+ // Initialize tables with the NOP service.
+ // This should only be done for service routine entries - data
+ // pointers should be NULLed.
+ for (i = 0; i < CYGNUM_CALL_IF_TABLE_SIZE; i++)
+ hal_virtual_vector_table[i] = (CYG_ADDRWORD) &nop_service;
+
+ // Version number
+ CYGACC_CALL_IF_VERSION_SET(CYGNUM_CALL_IF_TABLE_VERSION_CALL
+ |((CYG_ADDRWORD)CYGNUM_CALL_IF_TABLE_VERSION_COMM<<CYGNUM_CALL_IF_TABLE_VERSION_COMM_shift));
+ }
#endif
- // Miscellaneous services with wrappers in this file.
+ // Miscellaneous services with wrappers in this file.
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET
- CYGACC_CALL_IF_RESET_SET(reset);
+ CYGACC_CALL_IF_RESET_SET(reset);
#endif
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US
- CYGACC_CALL_IF_DELAY_US_SET(delay_us);
+ CYGACC_CALL_IF_DELAY_US_SET(delay_us);
#endif
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE
- // Cache functions
- CYGACC_CALL_IF_FLUSH_ICACHE_SET(flush_icache);
- CYGACC_CALL_IF_FLUSH_DCACHE_SET(flush_dcache);
+ // Cache functions
+ CYGACC_CALL_IF_FLUSH_ICACHE_SET(flush_icache);
+ CYGACC_CALL_IF_FLUSH_DCACHE_SET(flush_dcache);
#endif
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
- CYGACC_CALL_IF_FLASH_CFG_OP_SET(flash_config_op);
+ CYGACC_CALL_IF_FLASH_CFG_OP_SET(flash_config_op);
#endif
#ifdef CYGOPT_REDBOOT_FIS
- CYGACC_CALL_IF_FLASH_FIS_OP_SET(flash_fis_op);
+ CYGACC_CALL_IF_FLASH_FIS_OP_SET(flash_fis_op);
+ CYGACC_CALL_IF_FLASH_FIS_OP2_SET(flash_fis_op2);
#endif
- // Data entries not currently supported in eCos
+ // Data entries not currently supported in eCos
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA
- CYGACC_CALL_IF_DBG_DATA_SET(0);
+ CYGACC_CALL_IF_DBG_DATA_SET(0);
#endif
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_VERSION
- CYGACC_CALL_IF_MONITOR_VERSION_SET(0);
+ CYGACC_CALL_IF_MONITOR_VERSION_SET(0);
#endif
- // Comm controls
+ // Comm controls
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS
- {
- int i, j;
-
- // Clear out tables with safe dummy function.
- for (j = 0; j < CYGNUM_HAL_VIRTUAL_VECTOR_NUM_CHANNELS+1; j++)
- for (i = 0; i < CYGNUM_COMM_IF_TABLE_SIZE; i++)
- comm_channels[j][i] = (CYG_ADDRWORD) &nop_service;
-
- // Set accessor functions
- CYGACC_CALL_IF_SET_DEBUG_COMM_SET(set_debug_comm);
- CYGACC_CALL_IF_SET_CONSOLE_COMM_SET(set_console_comm);
-
- // Initialize console/debug procs. Note that these _must_
- // be set to empty before the comms init call.
- set_debug_comm(CYGNUM_CALL_IF_SET_COMM_ID_EMPTY);
- set_console_comm(CYGNUM_CALL_IF_SET_COMM_ID_EMPTY);
-
- // Initialize channels. This used to be done in
- // hal_diag_init() and the stub initHardware() functions, but
- // it makes more sense to have here.
- cyg_hal_plf_comms_init();
-
- // Always set the debug channel. If stubs are included, it is
- // necessary. If no stubs are included it does not hurt and is
- // likely to be required by the hal_if_diag_init code anyway
- // as it may rely on it if using a mangler.
- set_debug_comm(CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL);
- // Set console channel to a safe default. hal_if_diag_init
- // will override with console channel or mangler if necessary.
- set_console_comm(CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL);
- }
-
- // Reset console interrupt flag.
- CYGACC_CALL_IF_CONSOLE_INTERRUPT_FLAG_SET(0);
+ {
+ int i, j;
+
+ // Clear out tables with safe dummy function.
+ for (j = 0; j < CYGNUM_HAL_VIRTUAL_VECTOR_NUM_CHANNELS+1; j++)
+ for (i = 0; i < CYGNUM_COMM_IF_TABLE_SIZE; i++)
+ comm_channels[j][i] = (CYG_ADDRWORD) &nop_service;
+
+ // Set accessor functions
+ CYGACC_CALL_IF_SET_DEBUG_COMM_SET(set_debug_comm);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM_SET(set_console_comm);
+
+ // Initialize console/debug procs. Note that these _must_
+ // be set to empty before the comms init call.
+ set_debug_comm(CYGNUM_CALL_IF_SET_COMM_ID_EMPTY);
+ set_console_comm(CYGNUM_CALL_IF_SET_COMM_ID_EMPTY);
+
+ // Initialize channels. This used to be done in
+ // hal_diag_init() and the stub initHardware() functions, but
+ // it makes more sense to have here.
+ cyg_hal_plf_comms_init();
+
+ // Always set the debug channel. If stubs are included, it is
+ // necessary. If no stubs are included it does not hurt and is
+ // likely to be required by the hal_if_diag_init code anyway
+ // as it may rely on it if using a mangler.
+ set_debug_comm(CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL);
+ // Set console channel to a safe default. hal_if_diag_init
+ // will override with console channel or mangler if necessary.
+ set_console_comm(CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL);
+ }
+
+ // Reset console interrupt flag.
+ CYGACC_CALL_IF_CONSOLE_INTERRUPT_FLAG_SET(0);
#endif
- // Set up services provided by clients
-#if defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \
- ( defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs) \
- || defined(CYGSEM_HAL_USE_ROM_MONITOR_CygMon))
+ // Set up services provided by clients
+#if defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \
+ ( defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs) \
+ || defined(CYGSEM_HAL_USE_ROM_MONITOR_CygMon))
- patch_dbg_syscalls( (void *)(hal_virtual_vector_table) );
+ patch_dbg_syscalls( (void *)(hal_virtual_vector_table) );
#endif
- // Init client services
+ // Init client services
#if !defined(CYGPKG_KERNEL) && defined(CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT)
- // Only include this code if we do not have a kernel. Otherwise
- // the kernel supplies the functionality for the app we are linked
- // with.
+ // Only include this code if we do not have a kernel. Otherwise
+ // the kernel supplies the functionality for the app we are linked
+ // with.
- // Prepare for application installation of thread info function in
- // vector table.
- init_thread_syscall( (void *)&hal_virtual_vector_table[CYGNUM_CALL_IF_DBG_SYSCALL] );
+ // Prepare for application installation of thread info function in
+ // vector table.
+ init_thread_syscall( (void *)&hal_virtual_vector_table[CYGNUM_CALL_IF_DBG_SYSCALL] );
#endif
- // Finally, install async breakpoint handler if it is configured in.
- // FIXME: this should probably check for STUBS instead (but code is
- // conditional on BREAK for now)
+ // Finally, install async breakpoint handler if it is configured in.
+ // FIXME: this should probably check for STUBS instead (but code is
+ // conditional on BREAK for now)
#if defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
- // Install async breakpoint handler into vector table.
- CYGACC_CALL_IF_INSTALL_BPT_FN_SET(&cyg_hal_gdb_interrupt);
+ // Install async breakpoint handler into vector table.
+ CYGACC_CALL_IF_INSTALL_BPT_FN_SET(&cyg_hal_gdb_interrupt);
#endif
#if 0 != CYGINT_HAL_PLF_IF_INIT
- // Call platform specific initializations - should only be used
- // to augment what has already been set up, etc.
- plf_if_init();
+ // Call platform specific initializations - should only be used
+ // to augment what has already been set up, etc.
+ plf_if_init();
#endif
}
-
+2005-09-19 David Vrabel <dvrabel@arcom.com>
+
+ * src/redboot_linux_exec.c: No need to include pcmb_serial.h.
+
2005-07-18 David Vrabel <dvrabel@arcom.com>
* include/hal_arch.h: #define CYGARC_VIRTUAL_ADDRESS.
#include CYGHWR_MEMORY_LAYOUT_H
#include <cyg/hal/hal_io.h>
-#include <cyg/hal/pcmb_serial.h>
/*
* Code to launch a Linux image directly in protected mode.
+2007-10-12 Gary Thomas <gary@mlbassoc.com>
+
+ * src/vectors.S: Optimize system initialization of DATA/BSS/etc.
+
+2006-04-18 Gary Thomas <gary@mlbassoc.com>
+
+ * include/hal_arch.h: Adjust stack sizes - they were too small
+ (on machines with FPU) and didn't account for stack checking.
+
2005-07-29 Gary Thomas <gary@mlbassoc.com>
* include/arch.inc: Add one-time-include protection since newer
(38*4 /* offsetof(HAL_SavedRegisters, context_size) */)
// Interrupt + call to ISR, interrupt_end() and the DSR
+#ifdef CYGHWR_HAL_POWERPC_FPU
+#define CYGNUM_HAL_STACK_INTERRUPT_SIZE \
+ (((43*4)+(16*8) /* sizeof(HAL_SavedRegisters) */) + 2 * CYGNUM_HAL_STACK_FRAME_SIZE)
+#else
#define CYGNUM_HAL_STACK_INTERRUPT_SIZE \
((43*4 /* sizeof(HAL_SavedRegisters) */) + 2 * CYGNUM_HAL_STACK_FRAME_SIZE)
+#endif
// We have lots of registers so no particular amount is added in for
// typical local variable usage.
// than this. Allow enough for three interrupt sources - clock, serial and
// one other
+#ifdef CYGFUN_KERNEL_THREADS_STACK_CHECKING
+#define CYGNUM_HAL_STACK_CHECKING_OVERHEAD (2*CYGNUM_KERNEL_THREADS_STACK_CHECK_DATA_SIZE)
+#else
+#define CYGNUM_HAL_STACK_CHECKING_OVERHEAD 0
+#endif
+
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
// An interrupt stack which is large enough for all possible interrupt
// can therefore be much smaller
# define CYGNUM_HAL_STACK_SIZE_MINIMUM \
- (16*CYGNUM_HAL_STACK_FRAME_SIZE + 2*CYGNUM_HAL_STACK_INTERRUPT_SIZE)
+ (16*CYGNUM_HAL_STACK_FRAME_SIZE + \
+ 2*CYGNUM_HAL_STACK_INTERRUPT_SIZE + \
+ CYGNUM_HAL_STACK_CHECKING_OVERHEAD)
#else
// a stack sufficiently large
# define CYGNUM_HAL_STACK_SIZE_MINIMUM \
(((2+3)*CYGNUM_HAL_STACK_INTERRUPT_SIZE) + \
- (16*CYGNUM_HAL_STACK_FRAME_SIZE))
+ (16*CYGNUM_HAL_STACK_FRAME_SIZE) + \
+ CYGNUM_HAL_STACK_CHECKING_OVERHEAD)
#endif
// Now make a reasonable choice for a typical thread size. Pluck figures
// automatic variables per call frame
#define CYGNUM_HAL_STACK_SIZE_TYPICAL \
(CYGNUM_HAL_STACK_SIZE_MINIMUM + \
- 30 * (CYGNUM_HAL_STACK_FRAME_SIZE+(16*4)))
+ (30 * (CYGNUM_HAL_STACK_FRAME_SIZE+(16*4))) + \
+ CYGNUM_HAL_STACK_CHECKING_OVERHEAD)
//--------------------------------------------------------------------------
// Macros for switching context between two eCos instances (jump from
lwi r3,rom_vectors-4
lwi r4,((CYGHWR_HAL_POWERPC_VECTOR_BASE)-4)
lwi r5,rom_vectors_end-4
+ sub r5,r5,r3 # compute number of words to copy
+ srwi r5,r5,2
+ mtctr r5
0: lwzu r0,4(r3)
stwu r0,4(r4)
- cmplw r3,r5
- bne 0b
+ bdnz 0b
#endif
# set up stack
hal_mon_init
#if defined(CYG_HAL_STARTUP_ROM)
-
# Copy data from ROM to ram
lwi r3,__rom_data_start # r3 = rom start
lwi r4,__ram_data_start # r4 = ram start
cmplw r4,r5 # skip if no data
beq 2f
-
-1:
- lwz r0,0(r3) # get word from ROM
- stw r0,0(r4) # store in RAM
- addi r3,r3,4 # increment by 1 word
- addi r4,r4,4 # increment by 1 word
- cmplw r4,r5 # compare
- blt 1b # loop if not yet done
+ sub r5,r5,r4 # compute number of words to copy
+ srwi r5,r5,2
+ mtctr r5
+ subi r3,r3,4
+ subi r4,r4,4
+1: lwzu r0,4(r3) # get word from ROM
+ stwu r0,4(r4) # store in RAM
+ bdnz 1b
2:
#endif
li r0,0 # r0 = 0
cmplw r3,r4 # skip if no bss
beq 2f
+ sub r4,r4,r3 # compute number of words to clear
+ srwi r4,r4,2
+ mtctr r4
+ subi r3,r3,4
-1: stw r0,0(r3) # store zero
- addi r3,r3,4 # increment by 1 word
- cmplw r3,r4 # compare
- blt 1b # loop if not yet done
+1: stwu r0,4(r3) # store zero & increment pointer
+ bdnz 1b
2:
# clear SBSS
lwi r4,__sbss_end # r4 = end
cmplw r3,r4 # skip if no sbss
beq 2f
+ sub r4,r4,r3 # compute number of words to clear
+ srwi r4,r4,2
+ mtctr r4
+ subi r3,r3,4
-1: stw r0,0(r3) # store zero
- addi r3,r3,4 # increment by 1 word
- cmplw r3,r4 # compare
- blt 1b # loop if not yet done
+1: stwu r0,4(r3) # store zero & increment pointer
+ bdnz 1b
2:
# It is now safe to call C functions which may rely on initialized
+2006-11-13 Andreas Fritiofson <andreas.fritiofson@newmad.se>
+
+ * include/var_intr.h: Fixed a set of incorrect asserts.
+
2004-04-22 Jani Monoses <jani@iv.ro>
* cdl/hal_powerpc_mpc5xx.cdl :
#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM31
#define CYGARC_SIU_PRIORITY_HIGH 7 // Maximum interrupt priority on SIU
-#define CYGARC_SIU_PRIORITY_LOW 0 // Minimum interrupt prioeirt on SIU
+#define CYGARC_SIU_PRIORITY_LOW 0 // Minimum interrupt priority on SIU
#define CYGARC_IMB3_PRIORITY_HIGH 31 // Maximum interrupt priority on IMB3
#define CYGARC_IMB3_PRIORITY_LOW 0 // Minimum interrupt priority on IMB3
if(vector < CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1)
{
// Note: highest priority has the lowest numerical value.
- CYG_ASSERT( level >= CYGARC_SIU_PRIORITY_HIGH, "Invalid priority");
- CYG_ASSERT( level <= CYGARC_SIU_PRIORITY_LOW, "Invalid priority");
+ CYG_ASSERT( level >= CYGARC_SIU_PRIORITY_LOW, "Invalid priority");
+ CYG_ASSERT( level <= CYGARC_SIU_PRIORITY_HIGH, "Invalid priority");
}
else
{
- CYG_ASSERT( level >= CYGARC_IMB3_PRIORITY_HIGH, "Invalid priority");
- CYG_ASSERT( level <= CYGARC_IMB3_PRIORITY_LOW, "Invalid priority");
+ CYG_ASSERT( level >= CYGARC_IMB3_PRIORITY_LOW, "Invalid priority");
+ CYG_ASSERT( level <= CYGARC_IMB3_PRIORITY_HIGH, "Invalid priority");
}
switch (vector) {
+2006-01-27 Will Wagner <willw@carallon.com>
+
+ * include/ppc8xx.h: Add definition for frame and parity errors in BD ctrl.
+ Changed macro calculating SMCMR CLEN.
+
2004-04-01 Robert Chenault <robertchenault@yahoo.com>
* include/ppc8xx.h: Add definition for 8 bytes to spi_pram structure
#define QUICC_BD_CTL_Wrap 0x2000 // Last buffer in list
#define QUICC_BD_CTL_Int 0x1000 // Generate interrupt when empty (tx) or full (rx)
#define QUICC_BD_CTL_Last 0x0800 // Last buffer in a sequence
+#define QUICC_BD_CTL_Frame 0x0010 // Framing Error
+#define QUICC_BD_CTL_Parity 0x0008 // Parity Error
#define QUICC_BD_CTL_MASK 0xB000 // User settable bits
// Command register
#define QUICC_SMCE_RX 0x01 // Rx interrupt
// SMC Mode Register
-#define QUICC_SMCMR_CLEN(n) ((n+1)<<11) // Character length
+#define QUICC_SMCMR_CLEN(n) (n<<11) // Character length + parity + stop bits
#define QUICC_SMCMR_SB(n) ((n-1)<<10) // Stop bits (1 or 2)
#define QUICC_SMCMR_PE(n) (n<<9) // Parity enable (0=disable, 1=enable)
#define QUICC_SMCMR_PM(n) (n<<8) // Parity mode (0=odd, 1=even)
-/* Split ROM data Program for CqREEK SH-3 (Thanks Yamanaka-san) */\r
-/* Nihon Cygnus Solutions KASHIWAYA Haruki '00-4-13 */\r
-\r
-/* This program separate ROM data for one ROM socket.\r
- The cq board has two ROM sockets, and those bus size can\r
- switch to 8bit or 16bit with JP6.\r
- If your program is smaller than 32kByte, you can use\r
- a 256k bit ROM with 8bit bus mode.\r
- However, the board curcuit connection is peculiar.\r
- A0 is connected to A14 in 8bit bus mode (See the curcuit diagram),\r
- this mean's all odd data are assigned from 0x4000 offset.\r
- You must use this program and separate ROM data when you use\r
- a 256k bit ROM with 8bit bus mode.\r
-\r
- If your program is bigger than 32kByte, simply, you can use\r
- two 256k bit(or bigger) ROM with 16bit bus mode.\r
- You do *not* need to use this program.\r
- (Details, separate ROM data to odd and even, and write each data to\r
- each ROMs, and attach odd's ROM to IC4, even's ROM to IC8.)\r
-\r
-*/\r
-\r
-#include <stdio.h>\r
-#include <errno.h>\r
-\r
-#define ROMSIZE (32 * 1024)\r
-\r
-main(int argc, char **argv)\r
-{\r
- FILE *fpr, *fpw;\r
- int i, c;\r
- char *s, *p;\r
-\r
- if(argc != 3) {\r
- printf("Usage: mkcqrom <input-filename> <output-filename>\n Please see comments in mkcqrom.c.\n");\r
- exit(1);\r
- }\r
-\r
- p = (char *)malloc(ROMSIZE);\r
- if(p == NULL) {\r
- printf("malloc error\n");\r
- exit(1);\r
- }\r
- fpr = fopen(*++argv, "rb");\r
- if(fpr == NULL) {\r
- printf("open error %s %d\n", *argv, errno);\r
- exit(1);\r
- }\r
- memset(p, 0xff, ROMSIZE);\r
-\r
- /* split even data to 0x4000 offset (A0 is assigned to A14) */\r
- i = 0;\r
- while(1) {\r
- c = getc(fpr);\r
- if(c == EOF) break;\r
- s = p + (i / 2) + (i % 2) * 0x4000;\r
- *s = (char)c;\r
- i++;\r
- }\r
- fclose(fpr);\r
-\r
- fpw = fopen(*++argv, "wb");\r
- if(fpw == NULL) {\r
- printf("open error %s %d\n", *argv, errno);\r
- exit(1);\r
- }\r
- fwrite(p, ROMSIZE, sizeof(char), fpw);\r
- fclose(fpw);\r
-}\r
+/* Split ROM data Program for CqREEK SH-3 (Thanks Yamanaka-san) */
+/* Nihon Cygnus Solutions KASHIWAYA Haruki '00-4-13 */
+
+/* This program separate ROM data for one ROM socket.
+ The cq board has two ROM sockets, and those bus size can
+ switch to 8bit or 16bit with JP6.
+ If your program is smaller than 32kByte, you can use
+ a 256k bit ROM with 8bit bus mode.
+ However, the board curcuit connection is peculiar.
+ A0 is connected to A14 in 8bit bus mode (See the curcuit diagram),
+ this mean's all odd data are assigned from 0x4000 offset.
+ You must use this program and separate ROM data when you use
+ a 256k bit ROM with 8bit bus mode.
+
+ If your program is bigger than 32kByte, simply, you can use
+ two 256k bit(or bigger) ROM with 16bit bus mode.
+ You do *not* need to use this program.
+ (Details, separate ROM data to odd and even, and write each data to
+ each ROMs, and attach odd's ROM to IC4, even's ROM to IC8.)
+
+*/
+
+#include <stdio.h>
+#include <errno.h>
+
+#define ROMSIZE (32 * 1024)
+
+main(int argc, char **argv)
+{
+ FILE *fpr, *fpw;
+ int i, c;
+ char *s, *p;
+
+ if(argc != 3) {
+ printf("Usage: mkcqrom <input-filename> <output-filename>\n Please see comments in mkcqrom.c.\n");
+ exit(1);
+ }
+
+ p = (char *)malloc(ROMSIZE);
+ if(p == NULL) {
+ printf("malloc error\n");
+ exit(1);
+ }
+ fpr = fopen(*++argv, "rb");
+ if(fpr == NULL) {
+ printf("open error %s %d\n", *argv, errno);
+ exit(1);
+ }
+ memset(p, 0xff, ROMSIZE);
+
+ /* split even data to 0x4000 offset (A0 is assigned to A14) */
+ i = 0;
+ while(1) {
+ c = getc(fpr);
+ if(c == EOF) break;
+ s = p + (i / 2) + (i % 2) * 0x4000;
+ *s = (char)c;
+ i++;
+ }
+ fclose(fpr);
+
+ fpw = fopen(*++argv, "wb");
+ if(fpw == NULL) {
+ printf("open error %s %d\n", *argv, errno);
+ exit(1);
+ }
+ fwrite(p, ROMSIZE, sizeof(char), fpw);
+ fclose(fpw);
+}
\1a
\ No newline at end of file
+2005-12-02 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * cdl/hal_sh_sh7750_dreamcast.cdl: Fix the require statements so
+ we can build things other than RedBoot.
+
2004-04-30 Yoshinori Sato <ysato@users.sourceforge.jp>
* cdl/hal_sh_sh7750_dreamcast.cdl: Build boot.S.
The HAL package provides the support needed to run
eCos on SEGA Dreamcast."
- requires { CYGDAT_REDBOOT_SH_LINUX_BOOT_ENTRY == 0x8c210000 }
- requires { CYGDAT_REDBOOT_SH_LINUX_BOOT_BASE_ADDR == 0x8c001000 }
- requires { CYGDAT_REDBOOT_SH_LINUX_BOOT_COMMAND_LINE == "mem=16M" }
+ requires { is_active(CYGSEM_REDBOOT_SH_LINUX_BOOT) implies
+ (CYGDAT_REDBOOT_SH_LINUX_BOOT_ENTRY == 0x8c210000) }
+ requires { is_active(CYGSEM_REDBOOT_SH_LINUX_BOOT) implies
+ (CYGDAT_REDBOOT_SH_LINUX_BOOT_BASE_ADDR == 0x8c001000) }
+ requires { is_active(CYGSEM_REDBOOT_SH_LINUX_BOOT) implies
+ (CYGDAT_REDBOOT_SH_LINUX_BOOT_COMMAND_LINE == "mem=16M") }
compile hal_diag.c plf_misc.c dreamcast_pci.c fb_support.c
compile -library=libextras.a boot.S
+2007-06-12 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/synth_entry.c (__stack_chk_fail): another new function
+ needed when building with gcc 4.1.2
+ * current/src/synth.ld: place eh_frame_hdr into eh_frame.
+
+2006-07-10 Bart Veer <bartv@ecoscentric.com>
+
+ * src/synth_entry.c (__stack_chk_fail_local): new function needed
+ when building with gcc 4.1.1
+
+2005-11-19 Bart Veer <bartv@ecoscentric.com>
+
+ * src/synth_entry.c (_linux_entry): brk() is no longer needed to
+ get heap memory.
+
+ * src/synth.ld: add new section to contain the heap memory rather
+ than rely on brk().
+
+
+2005-11-05 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * include/hal_io.h (struct cyg_hal_sys_old_stat): Make the
+ structure match the kernel version otherwise the stack gets
+ corrupt and we die 'orribly. Added cyg_hal_sys_new_stat for when
+ using the new?stat() calls.
+ * src/synth_syscall.c (cyg_hal_sys_ftok): use the correct structure
+ member names and use the newstat system call so we get
+ values back which are compatible with glibc ftok() function.
+ * tests/ftok.c (new): Test case for the cyg_hal_sys_ftok()
+ function added in the previous patch.
+
+2005-10-19 Alexander Neundorf <neundorf@kde.org>
+
+ * src/synth_syscall.c: add cyg_hal_sys_ftok().
+
2005-07-30 Andrew Lunn <andrew.lunn@ascom.ch>
* src/synth_diag.c (hal_diag_write_char): Compiler warning fix.
calculated { "src/synth.ld" }
}
+ cdl_option CYGSEM_HAL_SYNTH_TESTS {
+ display "Build the Synth HAL tests"
+ default_value 0
+ description "
+ The only test at the moment is disabled by default
+ because it has to be run manually. It should be run both within
+ eCos and natively on Linux and the results compared"
+ }
+
+ cdl_component CYGPKG_HAL_SYNTH_TESTS {
+ display "Synth HAL tests"
+ active_if CYGSEM_HAL_SYNTH_TESTS
+ flavor data
+ no_define
+ calculated { "tests/ftok.c" }
+
+ make {
+ <PREFIX>/tests/ftok: <PACKAGE>/tests/ftok.c
+ @mkdir -p "$(dir $@)"
+ @$(HOST_CC) -DHOST -g -O2 -o $@ $< || cc -DHOST -g -O2 -o $@ $< || -DHOST gcc -g -O2 -o $@ $<
+ }
+ }
}
unsigned int tv_nsec;
};
-struct cyg_hal_sys_stat
+// NOTE: This corresponds to __old_kernel_stat in the kernel sources
+// and should be used with cyg_hal_sys_oldstat etc.
+
+struct cyg_hal_sys_old_stat
+{
+ unsigned short st_dev; /* device */
+ unsigned short st_ino; /* inode */
+ unsigned short st_mode; /* protection */
+ unsigned short st_nlink; /* number of hard links */
+ unsigned short st_uid; /* user ID of owner */
+ unsigned short st_gid; /* group ID of owner */
+ unsigned short st_rdev; /* device type (if inode device) */
+ unsigned long st_size; /* total size, in bytes */
+ unsigned long st_atime; /* time of last access */
+ unsigned long st_mtime; /* time of last modification */
+ unsigned long st_ctime; /* time of last change */
+};
+
+struct cyg_hal_sys_new_stat
{
- unsigned int dev; /* inode */
- unsigned long ino; /* device */
- unsigned short mode; /* protection */
- unsigned short nlink; /* number of hard links */
- unsigned short uid; /* user ID of owner */
- unsigned short gid; /* group ID of owner */
- unsigned long rdev; /* device type (if inode device) */
- unsigned long size; /* total size, in bytes */
- unsigned int blksize; /* blocksize for filesystem I/O */
- unsigned int blocks; /* number of blocks allocated */
- struct cyg_hal_sys_timespec atime; /* time of last access */
- struct cyg_hal_sys_timespec mtime; /* time of last modification */
- struct cyg_hal_sys_timespec ctime; /* time of last change */
+ unsigned long st_dev;
+ unsigned long st_ino;
+ unsigned short st_mode;
+ unsigned short st_nlink;
+ unsigned short st_uid;
+ unsigned short st_gid;
+ unsigned long st_rdev;
+ unsigned long st_size;
+ unsigned long st_blksize;
+ unsigned long st_blocks;
+ unsigned long st_atime;
+ unsigned long st_atime_nsec;
+ unsigned long st_mtime;
+ unsigned long st_mtime_nsec;
+ unsigned long st_ctime;
+ unsigned long st_ctime_nsec;
+ unsigned long __unused4;
+ unsigned long __unused5;
};
// System calls, or rather the subset that is needed internally or by
//detach from it again
externC int cyg_hal_sys_shmdt (const void* shmaddr);
+// Convert a pathname and an identifier into a System V IPC key
+externC int cyg_hal_sys_ftok(const char* path, int id);
+
// The actual implementation appears to return the new brk() value.
externC void* cyg_hal_sys_brk(void*);
externC int cyg_hal_sys_readdir(unsigned int fd,
struct cyg_hal_sys_dirent *dp,
unsigned int count);
-externC int cyg_hal_sys_lstat(const char* name, struct cyg_hal_sys_stat *buf);
-externC int cyg_hal_sys_fstat(int fd, struct cyg_hal_sys_stat *buf);
+// Old syscall versions
+externC int cyg_hal_sys_oldlstat(const char* name,
+ struct cyg_hal_sys_old_stat *buf);
+externC int cyg_hal_sys_oldfstat(int fd, struct cyg_hal_sys_old_stat *buf);
+externC int cyg_hal_sys_oldstat(const char* name,
+ struct cyg_hal_sys_old_stat *buf);
+// New syscall versions
+externC int cyg_hal_sys_newlstat(const char* name,
+ struct cyg_hal_sys_new_stat *buf);
+externC int cyg_hal_sys_newfstat(int fd, struct cyg_hal_sys_new_stat *buf);
+externC int cyg_hal_sys_newstat(const char* name,
+ struct cyg_hal_sys_old_stat *buf);
+
externC int cyg_hal_sys_mkdir(const char* path, int mode);
// Access to environmental data
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2005 Bart Veer
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
.eh_frame _vma_ : _lma_ \
{ \
FORCE_OUTPUT; __EH_FRAME_BEGIN__ = .; \
- KEEP(*(.eh_frame)) \
+ KEEP(*(.eh_frame*)) \
__FRAME_END__ = .; \
. = . + 8; \
} > _region_ = 0
> _region_ \
__bss_end = .;
+#define SECTIONS_HEAP(_region_, _start_, _end_) \
+ .synth_heap _start_ : \
+ { FORCE_OUTPUT; . = _end_ - _start_ ; } \
+ > _region_
+
#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .);
#include <pkgconf/system.h>
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 2002 Bart Veer
+// Copyright (C) 2002, 2005 Bart Veer
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
#include <cyg/infra/cyg_ass.h>
+#include <cyg/infra/diag.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/hal_io.h>
void _linux_entry( void )
{
- void* new_top = (void*) 0;
-
// "Initialize various cpu status registers, including disabling interrupts."
// That is a no-op for the synthetic target, in particular interrupts are
// already disabled.
- // "Set up any CPU memory controller to access ROM, RAM, and I/O devices
- // correctly".
- //
- // This involves using the brk() system call to allocate the RAM used
- // for the heaps. There are no variables mapped there so the system
- // will not have done this for us. Note that the implementation of
- // brk() (mm/mmap.c) differs from the documentation - the return
- // value is the new brk value, not an error code.
- new_top = (void*) (CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE);
- if (new_top != cyg_hal_sys_brk(new_top)) {
- CYG_FAIL("Failed to initialize memory");
- cyg_hal_sys_exit(1);
- }
-
- // Again a no-op for the synthetic target. All memory is readily
- // accessible. Arguably the auxiliary should be started up here, but
- // instead that is left to platform initialization.
+ // "Set up any CPU memory controller to access ROM, RAM, and I/O
+ // devices correctly". The ROM and RAM are set up via the linker
+ // script and taken care of automatically during loading. There
+ // are no memory-mapped devices. Arguably the auxiliary should be
+ // started up here, but instead that is left to platform
+ // initialization.
// "Enable the cache". Effectively the synthetic target has no cache,
// anything provided by the hardware is not readily accessible.
}
#endif
+#if (__GNUC__ >= 4)
+// First noticed with gcc 4.1.1. There is now code to detect stack
+// smashing.
+void __attribute__ ((noreturn))
+__stack_chk_fail_local(void)
+{
+ CYG_FAIL("Stack smashing detected, aborting");
+ diag_printf("Application error: stack smashing detected.\n");
+ cyg_hal_sys_exit(1);
+ for (;;);
+}
+// Another symbol which indicates a similar problem occurred.
+void __stack_chk_fail(void)
+{
+ __stack_chk_fail_local();
+}
+#endif
+
//-----------------------------------------------------------------------------
// End of entry.c
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
// -------------------------------------------
-//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
return (cyg_hal_sys_mmapx(&args));
}
+
+int cyg_hal_sys_ftok(const char* path, int id)
+{
+ struct cyg_hal_sys_old_stat st;
+
+ if (cyg_hal_sys_oldstat(path, &st) != 0)
+ return (cyg_uint32)-1;
+
+ return (cyg_uint32) (id << 24 |
+ (st.st_dev & 0xff) << 16 |
+ (st.st_ino & 0xffff));
+}
+2005-11-19 Bart Veer <bartv@ecoscentric.com>
+
+ * include/pkgconf/mlt_synth_i386_rom.ldi: add new heap section to
+ avoid the use of brk()
+
+2005-11-05 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/syscall-i386-linux-1.0.S: renamed prev_?stat to old?stat to
+ match the kernel. Removed STATCALL2 macro because it caused
+ confusion. Added the new?stat system calls.
+
2005-06-26 Bart Veer <bartv@ecoscentric.com>
* include/var_intr.h (HAL_DELAY_US): new header to supply
MEMORY
{
- rom : ORIGIN = 0x1000000, LENGTH = 0x800000
- ram : ORIGIN = 0x2000000, LENGTH = 0x800000
+ rom : ORIGIN = 0x01000000, LENGTH = 0x800000
+ ram : ORIGIN = 0x02000000, LENGTH = 0x800000
}
SECTIONS
{
SECTIONS_BEGIN
- SECTION_vectors (rom, 0x1000000, LMA_EQ_VMA)
+ SECTION_vectors (rom, 0x01000000, LMA_EQ_VMA)
SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_eh_frame (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rel__got (rom, ALIGN (0x1), LMA_EQ_VMA)
SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA)
- SECTION_data (ram, 0x2000000, LMA_EQ_VMA)
+ SECTION_data (ram, 0x02000000, LMA_EQ_VMA)
SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x10);
+ SECTIONS_HEAP(ram, __heap1, 0x02800000)
SECTIONS_END
}
#define SYS_klog 103
#define SYS_setitimer 104
#define SYS_getitimer 105
-#define SYS_prev_stat 106
-#define SYS_prev_lstat 107
-#define SYS_prev_fstat 108
+#define SYS_newstat 106
+#define SYS_newlstat 107
+#define SYS_newfstat 108
#define SYS_olduname 109
#define SYS_iopl 110
#define SYS_vhangup 111
\
END(x)
-#define STATCALL2(x) \
- .globl NAME(x) ; \
- \
-NAME(x): \
- \
- push %ebx; \
- mov 8(%esp), %ebx; \
- mov 12(%esp), %ecx; \
- lea SYS_prev_##x, %eax; \
- int $0x80; \
- pop %ebx; \
- ret; \
- END(x)
-
#define SYSCALL3(x) \
.globl NAME(x) ; \
\
SYSCALL2(getcwd)
SYSCALL2(access)
SYSCALL3(readdir)
-STATCALL2(lstat)
-STATCALL2(fstat)
+SYSCALL2(oldlstat)
+SYSCALL2(oldfstat)
+SYSCALL2(oldstat)
+SYSCALL2(newlstat)
+SYSCALL2(newfstat)
+SYSCALL2(newstat)
SYSCALL2(mkdir)
SYSCALL5(ipc)
+2008-07-10 Grant Edwards <grant.b.edwards@gmail.com>
+
+ * src/diag.cxx: allow ASCII escape character in printf
+ format strings.
+
+2007-12-28 Oyvind Harboe <oyvind.harboe@zylin.com>
+
+ * src/memcpy.cxx: added assert when memory areas for memcpy()
+ overlaps => result is undefined. It is important to catch *all*
+ cases of this if adding an optimisation for unaligned copy.
+
+2007-06-28 Gary Thomas <gary@mlbassoc.com>
+
+ * src/tcdiag.cxx:
+ * src/diag.cxx: Add (char *) casts to make GCC 4.2.x happy.
+
+2007-05-31 Rutger Hofman <rutger@cs.vu.nl>
+
+ * src/diag.cxx: when printing a long long, should not truncate
+ its value to a long or int size
+
+2006-10-26 Stefan Sommerfeld <sommerfeld@mikrom.com>
+
+ * include/cyg_types.h: fixed typo, __GNU_PATCHLEVEL__ was checked,
+ should be __GNUC_PATCHLEVEL__ (which is already used later)
+ * include/cyg_types.h: fixed comment for CYGBLD_ATTRIB_USED, wrong
+ GCC version was referenced
+
+2006-08-25 Gary Thomas <gary@mlbassoc.com>
+
+ * cdl/infra.cdl:
+ CYGNUM_INFRA_EMPTY_DELETE_THRESHOLD must be 'data', not 'boolean'
+
+2006-05-17 David Vrabel <dvrabel@arcom.com>
+
+ * include/cyg_type.h: #define CYG_NELEM to calculate the
+ number of elements in a (statically allocated) array.
+
+2006-05-08 Sergei Gavrikov <sg@belvok.com>
+
+ * src/buffer.cxx: Fix the compiler warnings.
+
+2005-11-04 Bart Veer <bartv@ecoscentric.com>
+
+ * tests/cxxsupp.cxx: Fix the compiler warnings.
+
+2005-10-16 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/delete.cxx:
+ * cdl/infra.cdl: Count the number of calls to delete when
+ INFRA_DEBUG is enabled. If the threshold is exceeded it probably
+ means the user expects a real delete function, not the empty one.
+
+2005-10-12 Laurent Gonzalez <laurent.gonzalez@trango-systems.com>
+
+ * src/simple.cxx (cyg_check_func_ptr): match the implementation to
+ the prototype. This got forgotten in the last patch.
+
2005-07-29 Andrew Lunn <andrew.lunn@ascom.ch>
* include/cyg_ass.h: Fixed a function prototype so that
so that new and delete can be used, if that is what is required."
}
+ cdl_option CYGNUM_INFRA_EMPTY_DELETE_THRESHOLD {
+ display "Threshold for valid number of delete calls"
+ flavor data
+ default_value 100
+ active_if CYGPKG_INFRA_DEBUG
+ description "
+ Some users don't know about the empty delete function and then
+ wonder why their C++ classes are leaking memory. If
+ INFRA_DEBUG is enabled we keep a counter for the number of
+ times delete is called. If it goes above this threshold we throw
+ an assertion failure. This should point heavy users of
+ delete in the right direction without upsetting those who want
+ an empty delete function. "
+ }
+
# ========================================================================
cdl_option CYGFUN_INFRA_DUMMY_ABORT {
display "Additional compiler flags"
flavor data
no_define
- default_value { "" }
+ default_value { "-fno-rtti -Woverloaded-virtual" }
description "
This option modifies the set of compiler flags for
building the eCos infra package. These flags are used
display "Suppressed compiler flags"
flavor data
no_define
- default_value { "" }
+ default_value { "-Wno-pointer-sign" }
description "
This option modifies the set of compiler flags for
building the eCos infra package. These flags are removed from
const char *file;
cyg_uint32 lnum;
#ifdef CYGDBG_INFRA_DEBUG_TRACE_MESSAGE
- char *exitmsg;
+ const char *exitmsg;
CYG_ADDRWORD exitvalue;
enum { UNSET = 0, SET, VOID } exitset;
#endif
Cyg_TraceFunction_Report_(
int condition, const char *psz_func, const char *psz_file,
- cyg_uint32 linenum, char *psz_exitmsg )
+ cyg_uint32 linenum, const char *psz_exitmsg )
{
cond = condition;
func = psz_func;
if ( cond )
cyg_tracemsg( cyg_trace_enter, func, file, lnum, "enter");
#else
- CYG_UNUSED_PARAM( char *, psz_exitmsg );
+ CYG_UNUSED_PARAM( const char *, psz_exitmsg );
if ( cond )
cyg_tracenomsg( func, file, lnum );
#endif
struct Cyg_TraceFunction_Report_
{
int cond;
- char *func;
- char *file; /* not strictly needed in plain 'C' */
+ const char *func;
+ const char *file; /* not strictly needed in plain 'C' */
cyg_uint32 lnum; /* nor this */
#ifdef CYGDBG_INFRA_DEBUG_TRACE_MESSAGE
- char *exitmsg;
+ const char *exitmsg;
CYG_ADDRWORD exitvalue;
int exitset;
#endif
typedef cyg_haladdress CYG_ADDRESS;
typedef cyg_haladdrword CYG_ADDRWORD;
+// -------------------------------------------------------------------------
+// Number of elements in a (statically allocated) array.
+
+#define CYG_NELEM(a) (sizeof(a) / sizeof((a)[0]))
+
// -------------------------------------------------------------------------
// Constructor ordering macros. These are added as annotations to all
// static objects to order the constuctors appropriately.
// COMPILER-SPECIFIC STUFF
#ifdef __GNUC__
-#if defined(__GNU_PATCHLEVEL__)
+#if defined(__GNUC_PATCHLEVEL__)
# define __GNUC_VERSION__ (__GNUC__ * 10000 \
+ __GNUC_MINOR__ * 100 \
+ __GNUC_PATCHLEVEL__)
# define CYGBLD_ATTRIB_STRFTIME_FORMAT(__format__, __args__) \
__attribute__((format (strftime, __format__, __args__)))
-// Tell the compiler not to throw away a variable or function. Only
-// available on 3.3.4 or above. Old version's didn't throw them away,
+// Tell the compiler not to throw away a variable or function. Only known
+// available on 3.3.2 or above. Old version's didn't throw them away,
// but using the unused attribute should stop warnings.
# if !defined(CYGBLD_ATTRIB_USED)
-# if __GNUC_VERSION__ >= 30404
+# if __GNUC_VERSION__ >= 30302
# define CYGBLD_ATTRIB_USED __attribute__((used))
# else
# define CYGBLD_ATTRIB_USED __attribute__((unused))
// (these are shared between trace and assert functions)
#if 0
-static char * tracepremsgs[] = {
+static const char *tracepremsgs[] = {
" INFO:",
"ENTER :",
"ARGS :",
};
#endif
-static char * tracepremsgs[] = {
+static const char *tracepremsgs[] = {
"'",
"{{",
"((",
"bad code"
};
-static char * tracepostmsgs[] = {
+static const char *tracepostmsgs[] = {
"'",
"",
"))",
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2005 Andrew Lunn
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
#include <pkgconf/infra.h>
#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_ass.h>
// see the description comment in infra.cdl for
// CYGFUN_INFRA_EMPTY_DELETE_FUNCTIONS
#ifdef CYGFUN_INFRA_EMPTY_DELETE_FUNCTIONS
// then define these empty functions:
+#ifdef CYGPKG_INFRA_DEBUG
+static cyg_uint32 counter;
+#endif
+
void operator delete(void *x) throw()
{
+#ifndef CYGPKG_INFRA_DEBUG
CYG_EMPTY_STATEMENT;
+#else
+ counter++;
+ CYG_ASSERT(counter < CYGNUM_INFRA_EMPTY_DELETE_THRESHOLD,
+ "Do you want an empty delete function?");
+#endif
}
void operator delete[](void *x) throw()
{
+#ifndef CYGPKG_INFRA_DEBUG
CYG_EMPTY_STATEMENT;
+#else
+ counter++;
+ CYG_ASSERT(counter < CYGNUM_INFRA_EMPTY_DELETE_THRESHOLD,
+ "Do you want an empty delete function?");
+#endif
}
#endif // CYGFUN_INFRA_EMPTY_DELETE_FUNCTIONS
#include <stdarg.h>
#include <limits.h>
#include <ctype.h>
-
+
#ifdef CYG_HAL_DIAG_LOCK_DATA_DEFN
CYG_HAL_DIAG_LOCK_DATA_DEFN;
#endif
// Mask to unsigned, sized quantity
if (islong) {
val &= ((long long)1 << (sizeof(long) * 8)) - 1;
- } else{
+ } else if (!islonglong) { // no need to mask longlong
val &= ((long long)1 << (sizeof(int) * 8)) - 1;
}
}
c = *cp++;
#if CYGINT_ISO_CTYPE
if (isprint(c) || isspace(c)) {
- (*putc)(c, param);
+ (*putc)(c, param);
} else if (iscntrl(c)) {
(*putc)('\\', param);
(*putc)('C', param);
CYG_REPORT_RETURN();
} // __main()
+#if (__GNUC__ >= 3)
+// Versions of gcc/g++ after 3.0 (approx.), when configured for Linux
+// native development (specifically, --with-__cxa_enable), have
+// additional dependencies related to the destructors for static
+// objects. When compiling C++ code with static objects the compiler
+// inserts a call to __cxa_atexit() with __dso_handle as one of the
+// arguments. __cxa_atexit() would normally be provided by glibc, and
+// __dso_handle is part of crtstuff.c. Synthetic target applications
+// are linked rather differently, so either a differently-configured
+// compiler is needed or dummy versions of these symbols should be
+// provided. If these symbols are not actually used then providing
+// them is still harmless, linker garbage collection will remove them.
+
+externC void
+__cxa_atexit(void (*func)(void *), void *arg2, const void *arg3)
+{
+}
+void *__dso_handle = (void* )&__dso_handle;
+
+// gcc 3.2.2 (approx). The libsupc++ version of the new operator pulls
+// in exception handling code, even when using the nothrow version and
+// building with -fno-exceptions. libgcc_eh.a provides the necessary
+// functions, but requires a dl_iterate_phdr() function. That is related
+// to handling dynamically loaded code so is not applicable to eCos.
+int
+dl_iterate_phdr(void* arg1, void* arg2)
+{
+ return -1;
+}
+
+externC void
+raise(void)
+{
+}
+#endif
// EOF dummyxxmain.cxx
void *
_memcpy( void *s1, const void *s2, size_t n )
{
-#if defined(CYGIMP_INFRA_PREFER_SMALL_TO_FAST_MEMCPY) || defined(__OPTIMIZE_SIZE__)
char *dst = (char *) s1;
const char *src = (const char *) s2;
+
+ CYG_ASSERT((dst >= (src+n)) || ((dst+n) <= src),
+ "memcpy() has undefined result for overlapping copies");
+
+#if defined(CYGIMP_INFRA_PREFER_SMALL_TO_FAST_MEMCPY) || defined(__OPTIMIZE_SIZE__)
#ifdef CYG_TRACING_FIXED
CYG_REPORT_FUNCNAMETYPE( "_memcpy", "returning %08x" );
#endif
return s1;
#else
- char *dst;
- const char *src;
CYG_WORD *aligned_dst;
const CYG_WORD *aligned_src;
CYG_REPORT_FUNCNAMETYPE( "_memcpy", "returning %08x" );
#endif
- dst = (char *)s1;
- src = (const char *)s2;
#ifdef CYG_TRACING_FIXED
CYG_REPORT_FUNCARG3( "dst=%08x, src=%08x, n=%d", dst, src, n );
struct cyg_fconfig fc;
cur_console = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
- fc.key = "info_console_force";
+ fc.key = (char *)"info_console_force";
fc.type = CYGNUM_FLASH_CFG_TYPE_CONFIG_BOOL;
- fc.val = (void *)&i;
+ fc.val = &i;
if (CYGACC_CALL_IF_FLASH_CFG_OP2(CYGNUM_CALL_IF_FLASH_CFG_GET, &fc)) {
if (i) {
- fc.key = "info_console_number";
+ fc.key = (char *)"info_console_number";
fc.type = CYGNUM_FLASH_CFG_TYPE_CONFIG_INT;
if (CYGACC_CALL_IF_FLASH_CFG_OP2(CYGNUM_CALL_IF_FLASH_CFG_GET, &fc)) {
// Then i is the console to force it to:
switch (status) {
case CYGNUM_TEST_FAIL:
- st = "FAIL:";
+ st = (char *)"FAIL:";
break;
case CYGNUM_TEST_PASS:
- st = "PASS:";
+ st = (char *)"PASS:";
break;
case CYGNUM_TEST_EXIT:
- st = "EXIT:";
+ st = (char *)"EXIT:";
break;
case CYGNUM_TEST_INFO:
- st = "INFO:";
+ st = (char *)"INFO:";
break;
case CYGNUM_TEST_GDBCMD:
- st = "GDB:";
+ st = (char *)"GDB:";
break;
case CYGNUM_TEST_NA:
- st = "NOTAPPLICABLE:";
+ st = (char *)"NOTAPPLICABLE:";
break;
default:
- st = "UNKNOWN STATUS:";
+ st = (char *)"UNKNOWN STATUS:";
break;
}
int instance;
public:
Pure(int i);
+ virtual ~Pure() {}
virtual void pure_fun1(void) = 0;
virtual void pure_fun2(void) = 0;
virtual void impure_fun1(void);
{
public:
Derived(int i);
+ virtual ~Derived() {}
void pure_fun1(void);
void pure_fun2(void);
void impure_fun2(void);
+2007-08-23 Alexey Shusharin <mrfinch@mail.ru>
+
+ * doc/can.sgml: Callback on event documentation.
+ * src/can.c: Change one wakeup to callback in a comment.
+ * include/canio.h: changed cyg_addrword_t to CYG_ADDRWORD so
+ can will compile without the kernel.
+
+2007-08-06 Alexey Shusharin <mrfinch@mail.ru>
+ Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * cdl/io_can.cdl: Added option CYGOPT_IO_CAN_SUPPORT_CALLBACK
+
+ * include/canio.h: Added struct cyg_can_callback_cfg for setting
+ callback configurations.
+
+ * include/can.h: Added declaration and initialization of callback
+ configuration in struct can_channel.
+
+ * src/can.c: Added callback configuration changing and
+ application function call.
+
+2007-07-02 Uwe Kindler <uwe_kindler@web.de>
+
+ * cdl/io_can.cdl: Added interface CYGINT_IO_CAN_CHANNELS for
+ counting available CAN channels
+
+ * include/canio.h: Changed type cyg_can_msgbuf_info. The two
+ fields are 16 bit now because device drivers may support more
+ than 256 message buffers (i.e. the LPC2xxx CAN driver)
+
+2007-06-20 Uwe Kindler <uwe_kindler@web.de>
+
+ * test/can_filter: Changed filter loop counter from cyg_uint8 to
+ cyg_uint16 because LPC2xxx CAN driver supports more than 256
+ message buffers.
+
+2007-03-23 Uwe Kindler <uwe_kindler@web.de>
+
+ * cdl/io_can.cdl: Added several interfaces for implementation by
+ device drivers.
+ Moved several configuration options from device drivers to the
+ generic CAN driver. With this design a device driver does not
+ need to provide all configuration options in its CDL file - it
+ simply needs to implement the provided interfaces. The drawback
+ of this decicsion is, that it is not possible to control these
+ options independently for several CAN devices. (But most platforms
+ will have only 1 channel)
+ Added configuration option CYGBLD_IO_CAN_EXTRA_TESTS. This option
+ enables the build of the interactive CAN tests.
+
+ * test/can_filter: Added interactive message filtering test
+
+ * test/can_hdi: Added interactive hardware description interface
+ test
+
+ * test/can_load: Added interactive message handling (reception,
+ transmission) test.
+
+ * test/can_remote: Added interactive remote response buffer test
+
+ * test/can_tx: Added interactive basic TX test. All tests are not
+ part of the eCos test framework because they are interactive. That
+ means, they require interaction with another user controlled
+ CAN node.
+
+ * include/can.h: Added identifier masks for standard and extended
+ identifiers.
+ Added the line #include CYGDAT_IO_CAN_DEVICE_INL. This enables a
+ device driver to provide an own device inline file. In this inline
+ file the driver may define own data types for CAN messages (for
+ internal storage of CAN messages (see AT91SAM7 CAN driver))
+
+ * include/canio.h: Added baudrate CYGNUM_CAN_KBAUD_AUTO - support of
+ automatic baudrate detection if a driver supports such a feature.
+ Added state CYGNUM_CAN_STATE_CONFIG and mode CYGNUM_CAN_MODE_CONFIG.
+ The application may use these identifiers to set the CAN device into
+ a state where it is safe to add/remove/configure message buffers.
+ Added union data type cyg_can_msg_data. With this data type a 4 byte
+ alignment of message data is guaranteed, an byte, word and dword
+ access to the data is possible and an assignment of two CAN datas are
+ possible now.
+ cyg_can_message now uses cyg_can_msg_data union for CAN data.
+ Replaced SW-Filt flag by autobaud flag in HDI.
+ Added CAN message access macros for read/write acces of CAN message
+ structures. These macros hide implementation of CAN message from
+ application.
+
+ * src/can.c: Added support for device driver defined CAN message
+ data types
+
+2006-12-19 Sergei Gavrikov <sg@sgs.gomel.by>
+
+ * doc/can.sgml: Correctly close para tag.
+
+2006-12-13 Uwe Kindler <uwe_kindler@web.de>
+
+ * doc/can.sgml: CAN driver SGML documentation added.
+
+2006-08-25 Gary Thomas <gary@mlbassoc.com>
+
+ * cdl/io_can.cdl: Set parent for more intuitive ConfigTool layout.
+
+2006-03-27 Uwe Kindler <uwe_kindler@web.de>
+
+ * src/can.c can_rcv_event() Clear the flag field in new event before
+ calling into low level hardware driver.
+
+2006-02-15 Uwe Kindler <uwe_kindler@web.de>
+
+ * include/can_io.h Added message buffer configuration identifier:
+ CYGNUM_CAN_MSGBUF_RESET_ALL, CYGNUM_CAN_MSGBUF_RX_FILTER_ALL ...
+ Added cfg_id field to cyg_can_msgbuf_cfg data structure.
+
+2005-09-11 Uwe Kindler <uwe_kindler@web.de>
+
+ * include/can_io.h Added support for get_config to CAN_LOWLEVEL_FUNS
+ structure.
+ Added additional CAN events.
+ Added support for can state (cyg_can_state) and CAN mode (cyg_can_mode).
+ Changed data type of cyg_can_buf_info_t data structure from cyg_int32
+ to cyg_uint32.
+ Added support for message box configuration (cyg_can_msgbuf_info).
+ Added support for message filtering (cyg_cn_filter).
+ Renamed cyg_can_rtr_buf to cyg_can_remote_buf.
+ Renamed CYGNUM_CAN_RTR_BUF_NA and CYGNUM_CAN_RTR_BUF_INIT to
+ CYGNUM_CAN_MSGBUF_NA and CYGNUM_CAN_MSGBUF_INIT because they are
+ also used for message filtering.
+ Added support for hardware description interface.
+ Added support for CYG_IO_SET_CONFIG_CAN_INPUT_FLUSH,
+ CYG_IO_SET_CONFIG_CAN_OUTPUT_FLUSH and CYG_IO_GET_CONFIG_SERIAL_OUTPUT_DRAIN.
+
+ * doc/can_driver_doc.html Additional configuration options
+ documented.
+
2005-05-24 Uwe Kindler <uwe_kindler@web.de>
* Generic CAN driver package created
cdl_package CYGPKG_IO_CAN {
display "CAN device drivers"
+ parent CYGPKG_IO
active_if CYGPKG_IO
requires CYGPKG_ERROR
include_dir cyg/io
puts $::cdl_header "#endif "
puts $::cdl_header "/****** proc output end ******/"
}
-
+
+ #-----------------------------------------------------------------
+ # Interfaces
+ # A hardware device driver should implement each interface it
+ # supports
+ #
cdl_interface CYGINT_IO_CAN_TIMESTAMP {
display "CAN driver supports timestamps"
}
+ cdl_interface CYGINT_IO_CAN_STD_CAN_ID {
+ display "11 Bit standard CAN ID support"
+ }
+
+ cdl_interface CYGINT_IO_CAN_EXT_CAN_ID {
+ display "29 Bit extended CAN ID support"
+ }
+
+ cdl_interface CYGINT_IO_CAN_RUNTIME_MBOX_CFG {
+ display "CAN driver supports message box runtime configuration"
+ }
+
+ cdl_interface CYGINT_IO_CAN_REMOTE_BUF {
+ display "CAN driver supports remote response buffers"
+ }
+
+ cdl_interface CYGINT_IO_CAN_AUTOBAUD {
+ display "CAN driver supports automatic baudrate detection"
+ }
+
+ cdl_interface CYGINT_IO_CAN_TX_EVENTS {
+ display "CAN driver supports TX events"
+ }
+
+ #-----------------------------------------------------------------
+ # Each single channel of a CAN chip or on chip CAN module should
+ # implement this interface. It counts the number of available
+ # CAN channels
+ #
+ cdl_interface CYGINT_IO_CAN_CHANNELS {
+ display "Number of CAN channels"
+ }
+
+
+ #-----------------------------------------------------------------
+ # Generic CAN driver configuration
+ #
+ cdl_component CYGPKG_IO_CAN_DEVICES {
+ display "Hardware CAN device drivers"
+ flavor bool
+ default_value 1
+ description "
+ This option enables the hardware device drivers
+ for the current platform."
+ }
+
cdl_option CYGOPT_IO_CAN_SUPPORT_TIMESTAMP {
display "Support CAN event timestamps"
requires { CYGINT_IO_CAN_TIMESTAMP > 0 }
+ active_if { CYGINT_IO_CAN_TIMESTAMP > 0 }
default_value 0
description "
If the CAN hardware driver supports some kind of timestamps
cdl_option CYGOPT_IO_CAN_TX_EVENT_SUPPORT {
display "Support TX events"
+ requires { CYGINT_IO_CAN_TX_EVENTS > 0 }
+ active_if { CYGINT_IO_CAN_TX_EVENTS > 0 }
default_value 0
description "
This option enables support for TX events. If a CAN message is
option is enabled the RX event queue will be filled faster."
}
- cdl_component CYGPKG_IO_CAN_DEVICES {
- display "Hardware CAN device drivers"
- flavor bool
+ cdl_option CYGOPT_IO_CAN_STD_CAN_ID {
+ display "11 Bit standard CAN ID support"
+ requires { CYGINT_IO_CAN_STD_CAN_ID > 0 }
+ active_if { CYGINT_IO_CAN_STD_CAN_ID > 0 }
+ default_value { CYGINT_IO_CAN_STD_CAN_ID > 0 ? 1 : 0 }
+ description "
+ This option enables support for 11 Bit standard CAN identifiers.
+ If the application deals only with 29 Bit extended CAN messages
+ then disabling this option may reduce codesize or increase
+ performance."
+ }
+
+ cdl_option CYGOPT_IO_CAN_EXT_CAN_ID {
+ display "29 Bit extended CAN ID support"
+ requires { CYGINT_IO_CAN_EXT_CAN_ID > 0 }
+ active_if { CYGINT_IO_CAN_EXT_CAN_ID > 0 }
+ default_value { CYGINT_IO_CAN_EXT_CAN_ID > 0 ? 1 : 0 }
+ description "
+ This option enables support for 29 Bit extended CAN identifiers.
+ If the application deals only with 11 Bit standard CAN messages
+ then disabling this option may reduce codesize or increase
+ performance."
+ }
+
+ cdl_option CYGOPT_IO_CAN_AUTOBAUD {
+ display "Support automatic baudrate detection."
+ requires { CYGINT_IO_CAN_AUTOBAUD > 0 }
+ active_if { CYGINT_IO_CAN_AUTOBAUD > 0 }
+ default_value 0
+ description "
+ If the CAN hardware device driver supports any kind of automatic
+ baudrate detection then this option enables support for this feature.
+ If automatic baudrate detection is not required, then disabling this
+ option may reduce codesize."
+ }
+
+ cdl_option CYGOPT_IO_CAN_RUNTIME_MBOX_CFG {
+ display "Message box runtime configuration support"
+ requires { CYGINT_IO_CAN_RUNTIME_MBOX_CFG > 0 }
+ active_if { CYGINT_IO_CAN_RUNTIME_MBOX_CFG > 0 }
default_value 1
- description "
- This option enables the hardware device drivers
- for the current platform."
+ description "
+ Message box runtime configuration is required for for hardware message
+ filtering and for hardware remote response buffers. If no hardware
+ filtering is required and if the application does not need remote
+ response buffers this option can be disabled to decrease codesize."
}
+ cdl_option CYGOPT_IO_CAN_REMOTE_BUF {
+ display "Remote response buffer support"
+ requires { CYGOPT_IO_CAN_RUNTIME_MBOX_CFG }
+ requires { CYGINT_IO_CAN_REMOTE_BUF > 0}
+ active_if { CYGINT_IO_CAN_REMOTE_BUF > 0 }
+ default_value 1
+ description "
+ If the driver should handle remote requests automatically then remote
+ response buffers are required. Disabling this option may save some
+ bytes of ROM memory."
+ }
+
cdl_option CYGOPT_IO_CAN_SUPPORT_NONBLOCKING {
display "Support non-blocking read and write calls"
default_value 0
which allows clients to switch read() and write() call
semantics from blocking to non-blocking."
}
-
+
+ cdl_option CYGOPT_IO_CAN_SUPPORT_CALLBACK {
+ display "Support callback on events"
+ default_value 0
+ description "
+ This option enables extra code in the generic CAN driver
+ which allows application to register a callback for
+ events. The callback function is called from DSR
+ context so you should be careful to only call API
+ functions that are safe in DSR context."
+ }
+
cdl_component CYGOPT_IO_CAN_SUPPORT_TIMEOUTS {
display "Support read/write timeouts"
flavor bool
The initial timeout value in clock ticks for cyg_io_write() calls."
}
}
-
- cdl_component CYGPKG_IO_CAN_OPTIONS {
- display "CAN device driver build options"
- flavor none
- description "
- Package specific build options including control over
- compiler flags used only in building this package,
- and details of which tests are built."
-
-
- cdl_option CYGPKG_IO_CAN_CFLAGS_ADD {
- display "Additional compiler flags"
- flavor data
- no_define
- default_value { "" }
- description "
- This option modifies the set of compiler flags for
- building the CAN device drivers. These flags are used in addition
- to the set of global flags."
+
+ cdl_option CYGBLD_IO_CAN_EXTRA_TESTS {
+ display "Build extra CAN tests"
+ default_value 0
+ no_define
+ description "
+ This option enables the building of some extra tests which
+ can be used when testing / debugging CAN drivers. These
+ are not built by default since they do not use the dedicated
+ testing infrastructure. All tests require a properly configured
+ CAN network with a second CAN node that can send and receive
+ CAN messages."
+
+ make -priority 320 {
+ <PREFIX>/bin/can_load : <PACKAGE>/tests/can_load.c
+ @sh -c "mkdir -p tests $(dir $@)"
+ $(CC) -c $(INCLUDE_PATH) -Wp,-MD,deps.tmp -I$(dir $<) $(CFLAGS) -o tests/can_load.o $<
+ @echo $@ ": \\" > $(notdir $@).deps
+ @echo $(wildcard $(PREFIX)/lib/*) " \\" >> $(notdir $@).deps
+ @tail -n +2 deps.tmp >> $(notdir $@).deps
+ @echo >> $(notdir $@).deps
+ @rm deps.tmp
+ $(CC) $(LDFLAGS) -L$(PREFIX)/lib -Ttarget.ld -o $@ tests/can_load.o
}
-
- cdl_option CYGPKG_IO_CAN_CFLAGS_REMOVE {
- display "Suppressed compiler flags"
- flavor data
- no_define
- default_value { "" }
- description "
- This option modifies the set of compiler flags for
- building the CAN device drivers. These flags are removed from
- the set of global flags if present."
+
+ make -priority 320 {
+ <PREFIX>/bin/can_remote : <PACKAGE>/tests/can_remote.c
+ @sh -c "mkdir -p tests $(dir $@)"
+ $(CC) -c $(INCLUDE_PATH) -Wp,-MD,deps.tmp -I$(dir $<) $(CFLAGS) -o tests/can_remote.o $<
+ @echo $@ ": \\" > $(notdir $@).deps
+ @echo $(wildcard $(PREFIX)/lib/*) " \\" >> $(notdir $@).deps
+ @tail -n +2 deps.tmp >> $(notdir $@).deps
+ @echo >> $(notdir $@).deps
+ @rm deps.tmp
+ $(CC) $(LDFLAGS) -L$(PREFIX)/lib -Ttarget.ld -o $@ tests/can_remote.o
+ }
+
+ make -priority 320 {
+ <PREFIX>/bin/can_tx : <PACKAGE>/tests/can_tx.c
+ @sh -c "mkdir -p tests $(dir $@)"
+ $(CC) -c $(INCLUDE_PATH) -Wp,-MD,deps.tmp -I$(dir $<) $(CFLAGS) -o tests/can_tx.o $<
+ @echo $@ ": \\" > $(notdir $@).deps
+ @echo $(wildcard $(PREFIX)/lib/*) " \\" >> $(notdir $@).deps
+ @tail -n +2 deps.tmp >> $(notdir $@).deps
+ @echo >> $(notdir $@).deps
+ @rm deps.tmp
+ $(CC) $(LDFLAGS) -L$(PREFIX)/lib -Ttarget.ld -o $@ tests/can_tx.o
+ }
+
+ make -priority 320 {
+ <PREFIX>/bin/can_filter : <PACKAGE>/tests/can_filter.c
+ @sh -c "mkdir -p tests $(dir $@)"
+ $(CC) -c $(INCLUDE_PATH) -Wp,-MD,deps.tmp -I$(dir $<) $(CFLAGS) -o tests/can_filter.o $<
+ @echo $@ ": \\" > $(notdir $@).deps
+ @echo $(wildcard $(PREFIX)/lib/*) " \\" >> $(notdir $@).deps
+ @tail -n +2 deps.tmp >> $(notdir $@).deps
+ @echo >> $(notdir $@).deps
+ @rm deps.tmp
+ $(CC) $(LDFLAGS) -L$(PREFIX)/lib -Ttarget.ld -o $@ tests/can_filter.o
+ }
+
+ make -priority 320 {
+ <PREFIX>/bin/can_hdi : <PACKAGE>/tests/can_hdi.c
+ @sh -c "mkdir -p tests $(dir $@)"
+ $(CC) -c $(INCLUDE_PATH) -Wp,-MD,deps.tmp -I$(dir $<) $(CFLAGS) -o tests/can_hdi.o $<
+ @echo $@ ": \\" > $(notdir $@).deps
+ @echo $(wildcard $(PREFIX)/lib/*) " \\" >> $(notdir $@).deps
+ @tail -n +2 deps.tmp >> $(notdir $@).deps
+ @echo >> $(notdir $@).deps
+ @rm deps.tmp
+ $(CC) $(LDFLAGS) -L$(PREFIX)/lib -Ttarget.ld -o $@ tests/can_hdi.o
}
-
}
}
<head>
<meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
- <meta name="generator" content="Adobe GoLive 6">
<title>IO/CAN Doc</title>
</head>
const void *buf,<br>
cyg_uint32 *len )<br>
</code></p>
- <p>This function sends <b>one single</b> CAN message (not a buffer of CAN messages) to a device. The size of data to send is contained in <i>*len</i> and the actual size sent will be returned in the same place. A pointer to a <code>cyg_can_message</code> is contained in <i>*buf</i> . If a message was sucessfully sent, the function returns <code>ENOERR</code>. If nonblocking calls are supported and the TX buffer is full then the function returns immediatelly with <code>-EAGAIN</code>. If the driver supports timeouts and nonblocking calls are enabled then this function may also return <code>-EINTR</code> after the timout expired and the TX buffer is still full. This is important for applications where i.e. a watchdog need to be toggled by each task. Because it may happen that no CAN message will arrive for a long time the receiving thread remains blocked if the driver does not support timeouts and the watchdog will never be toggled.</p>
+ <p>This function sends <b>one single</b> CAN message (not a buffer of CAN messages) to a device. The size of data to send is contained in <i>*len</i> and the actual size sent will be returned in the same place. A pointer to a <code>cyg_can_message</code> is contained in <i>*buf</i> . The driver maintains a buffer to hold the data. The size of the intermediate buffer is configurable within the interface module. The data is not modified at all while it is being buffered. On return,<i> *len</i> contains the amount of characters actually consumed - that means <i>*len</i> always contains <code>sizeof(cyg_can_message)</code>.</p>
+ <p>It is possible to configure the write call to be blocking (default) or non-blocking. Non-blocking mode requires both the configuration option <code>CYGOPT_IO_CAN_SUPPORT_NONBLOCKING</code> to be enabled, and the specific device to be set to non-blocking mode for writes (see <code>cyg_io_set_config()</code>). In blocking mode, the call will not return until there is space in the buffer and the content of the CAN message has been consumed. In non-blocking mode, if there is no space in buffer for the CAN message, <code>-EAGAIN</code> is returned and the caller must try again.</p>
+ <p>It is possible to configure the write call to be non-blocking with timeout. None-blocking mode with timeout requires the configuration option <code>CYGOPT_IO_CAN_SUPPORT_NONBLOCKING </code>and<code> CYGOPT_IO_CAN_SUPPORT_TIMEOUTS </code>to be enabled, requires the eCos kernel package to be included and the specific device to be set to non-blocking mode for writes (see <code>cyg_io_set_config()</code>). In non-blocking mode with timeouts, if there is no space in buffer for the CAN message, the driver waits a certain amount of time (the timeout time) for space in the buffer. If there is still no space in buffer after expiration of the timeout time, <code> -EINTR</code> is returned and the caller must try again.</p>
+ <p>If a message was sucessfully sent, the function returns <code>ENOERR</code>. </p>
<p><code>typedef struct can_message<br>
+
{<br>
+
cyg_uint32 id;<br>
+
cyg_uint8 data[8];<br>
+
cyg_can_id_type ext;<br>
+
cyg_can_frame_type rtr;<br>
+
cyg_uint8 dlc;<br>
+
} cyg_can_message;</code></p>
<p>The type <code>cyg_can_message</code> provides a device independent type of CAN message. Before calling the write function this message should be setup properly. The<i> id</i> field contains the 11 Bit or 29 bit CAN message identifier depending on the value of the <i>ext</i> field. The <i>data</i> field contains the 8 data bytes of one CAN message. The <i>ext</i> field configures the type of CAN message identifier (<code>CYGNUM_CAN_ID_STD</code> = standard 11 Bit id,<i> </i><code>CYGNUM_CAN_ID_EXT</code> = extended 29 Bit id). The <i>rtr</i> field contains the frame type. (<code>CYGNUM_CAN_FRAME_DATA</code> = data frame, <code>CYGNUM_CAN_FRAME_RTR</code> = remote transmission request). The <i>dlc</i> field (data length code) contains the number of valid data bytes (0 - 8) in the <i>data</i> field.</p>
<p>Example code for sending one single CAN message:</p>
cyg_uint32 *len )<br>
</code></p>
- <p>This function receives one single event from a device. The desired size of data to receive is contained in <i>*len</i> and the actual size obtained will be returned in the same place. A pointer to a<code> cyg_can_event</code> is contained in <i>*buf</i>. If a message was sucessfully sent, the function returns <code>ENOERR</code>. If nonblocking calls are supported the driver returns <code>-EAGAIN</code> if the RX buffer is empty. If the driver supports timeouts and nonblocking calls are enabled then this function may also return <code>-EINTR</code> if the timout value expired and the RX buffer is still empty.</p>
+ <p>This function receives one single event from a device. The desired size of data to receive is contained in <i>*len</i> and the actual size obtained will be returned in the same place. A pointer to a<code> cyg_can_event</code> is contained in <i>*buf</i>. No manipulation of the data is performed before being transferred. Again, this buffering is completely configurable. On return, <i>*len</i> contains <code>sizeof(cyg_can_event)</code><br>
+ </p>
+ <p>It is possible to configure the read call to be blocking (default) or non-blocking. Non-blocking mode requires both the configuration option <code>CYGOPT_IO_CAN_SUPPORT_NONBLOCKING</code> to be enabled, and the specific device to be set to non-blocking mode for reads (<code>see cyg_io_set_config()</code>). In blocking mode, the call will not return until one single CAN event has been read. In<i> </i>non-blocking mode, if there is no CAN event in buffer, the call returns immediately with <code>-EAGAIN</code> and the caller must try again.</p>
+ <p>It is possible to configure the write call to be non-blocking with timeout. None-blocking mode with timeout requires the configuration option <code>CYGOPT_IO_CAN_SUPPORT_NONBLOCKING </code>and<code> CYGOPT_IO_CAN_SUPPORT_TIMEOUTS </code>to be enabled, requires the eCos kernel package to be included and the specific device to be set to non-blocking mode for reads (see <code>cyg_io_set_config()</code>). In non-blocking mode with timeouts, if there is no CAN event in receive buffer, the driver waits a certain amound of time (the timeout time) for a CAN event to arrive. If there is still no CAN event in buffer after expiration of the timeout time, <code> -EINTR</code> is returned and the caller must try again.</p>
+ <p>If a event was sucessfully received, the function returns <code>ENOERR</code>.</p>
<p><code>typedef struct cyg_can_event_st<br>
{<br>
cyg_uint32 timestamp;<br>
CYGNUM_CAN_EVENT_ENTERING_STANDBY = 0x0400, // CAN hardware enters standby / power down mode<br>
CYGNUM_CAN_EVENT_ARBITRATION_LOST = 0x0800, // arbitration lost<br>
-
CYGNUM_CAN_EVENT_DEVICE_CHANGED = 0x1000, // device changed event<br>
+ </code><code>CYGNUM_CAN_EVENT_PHY_FAULT = 0x2000, // General failure of physical layer detected (if supported by hardware)<br>
+ </code><code>CYGNUM_CAN_EVENT_PHY_H = 0x4000, // Fault on CAN-H detected (Low Speed CAN)<br>
+ </code><code>CYGNUM_CAN_EVENT_PHY_L = 0x8000, // Fault on CAN-L detected (Low Speed CAN)<br>
} cyg_can_event_flags;</code></p>
<p>Often the flags field will contain only one single set flag. But it is possible that a number of flags is set and so the flag field should always be checked by a receiver. I.e. if the <code>CYGNUM_CAN_EVENT_RX </code>is set then also the <code>CYGNUM_CAN_EVENT_OVERRUN_RX </code>may be set if the received message caused an RX overrun.</p>
- <p>The internal receive buffers of the CAN device driver a circular buffers. That means that even if the buffers are completely filled new messages will be received. In this case the newest message will always overwrite the oldes message in receive buffer. If this happens the <code>CYGNUM_CAN_EVENT_OVERRUN_RX </code>flag will be set for this new message that caused overwriting of the old one. </p>
+ <p>The internal receive buffers of the CAN device driver a circular buffers. That means that even if the buffers are completely filled new messages will be received. In this case the newest message will always overwrite the oldest message in receive buffer. If this happens the <code>CYGNUM_CAN_EVENT_OVERRUN_RX </code>flag will be set for this new message that caused overwriting of the old one. The <code>CYGNUM_CAN_EVENT_OVERRUN_RX </code>flag will be set also if a overrun occures in hardware message buffers of the CAN device.</p>
<p>Example code for receiving one single CAN event:</p>
<p><code>cyg_can_event rx_event;<br>
cyg_uint32 len;<br>
<p><code>CYG_IO_GET_CONFIG_READ_BLOCKING<br>
CYG_IO_GET_CONFIG_WRITE_BLOCKING<br>
CYG_IO_GET_CONFIG_CAN_INFO<br>
- CYG_IO_GET_CONFIG_CAN_BUFFER_INFO<br>
+ CYG_IO_GET_CONFIG_CAN_BUFFER_INFO<br>CYG_IO_GET_CONFIG_CAN_MSGBUF_INFO<br>
+
CYG_IO_GET_CONFIG_CAN_TIMEOUT<br>
+ CYG_IO_GET_CONFIG_CAN_HDI<br>
+ CYG_IO_GET_CONFIG_CAN_STATE<br>
</code></p>
<h4>Change configuration of a CAN device</h4>
<p><code>Cyg_ErrNo cyg_io_set_config(<br>
<p><code>CYG_IO_SET_CONFIG_READ_BLOCKING<br>
CYG_IO_SET_CONFIG_WRITE_BLOCKING<br>
CYG_IO_SET_CONFIG_CAN_INFO<br>
+ CYG_IO_SET_CONFIG_CAN_OUTPUT_DRAIN<br>
+ CYG_IO_SET_CONFIG_CAN_OUTPUT_FLUSH<br>
+ CYG_IO_SET_CONFIG_CAN_INPUT_FLUSH<br>
+
- CYG_IO_SET_CONFIG_CAN_TIMEOUT<br>
- CYG_IO_SET_CONFIG_CAN_RTR_BUF<br>
+ CYG_IO_SET_CONFIG_CAN_TIMEOUT<br>CYG_IO_SET_CONFIG_CAN_MSGBUF<br>
+ </code><code>CYG_IO_SET_CONFIG_CAN_MODE<br>
+ <br>
</code></p>
<h3>Runtime Configuration</h3>
<p>Runtime configuration is achieved by exchanging data structures with the driver via the <code>cyg_io_set_config()</code> and <code>cyg_io_get_config()</code> functions.</p>
} cyg_can_buf_info_t;<br>
</code></p>
<p><code>CYG_IO_GET_CONFIG_CAN_BUFFER_INFO - </code>This function retrieves the current state of the software buffers in the serial drivers. For the transmit buffer it returns the the total number of <code>cyg_can_message </code>objects in buffer and the current number of <code>cyg_can_message </code>objects occupied in the buffer. For the recieve buffer it returns the total number of <code>cyg_can_event </code>objects in receive buffer and the current number of <code>cyg_can_event </code>objects occupied in the buffer. It does not take into account any buffering such as FIFOs or holding registers that the CAN hardware device itself may have.</p>
+ <h4>Reading hardware description information</h4>
+ <p><code>typedef struct cyg_can_hdi_st<br>
+ {<br>
+ cyg_uint8 support_flags;<br>
+ cyg_uint8 controller_type;<br>
+ } cyg_can_hdi;</code></p>
+ <p><code>CYG_IO_GET_CONFIG_CAN_HDI - </code>This function retrieves information about the used hardware. The Hardware Description Interface provides a method to gather information about the CAN hardware and the functionality of the driver. For this purpose the structure <code>cyg_can_hdi </code>is defined. The field support_flags contains information about the capabilities of the used CAN hardware. The following flags are available:</p>
+ <table width="600" border="0" cellspacing="2" cellpadding="0">
+ <tr>
+ <td align="center" valign="middle" bgcolor="#c6c6c6" width="70">7</td>
+ <td align="center" valign="middle" bgcolor="#c6c6c6" width="70">6</td>
+ <td align="center" valign="middle" bgcolor="#c6c6c6" width="70">5</td>
+ <td align="center" valign="middle" bgcolor="#c6c6c6" width="70">4</td>
+ <td align="center" valign="middle" bgcolor="#c6c6c6" width="70">3</td>
+ <td align="center" valign="middle" bgcolor="#c6c6c6" width="70">2</td>
+ <td align="center" valign="middle" bgcolor="#c6c6c6" width="70">1</td>
+ <td align="center" valign="middle" bgcolor="#c6c6c6" width="70">0</td>
+ </tr>
+ <tr>
+ <td align="center" valign="middle" width="70">res</td>
+ <td align="center" valign="middle" width="70">res</td>
+ <td align="center" valign="middle" width="70">res</td>
+ <td align="center" valign="middle" width="70">timest.</td>
+ <td align="center" valign="middle" width="70">SW-Filt</td>
+ <td align="center" valign="middle" width="70">FullCAN</td>
+ <td colspan="2" align="center" valign="middle" width="142">Frametype</td>
+ </tr>
+ </table>
+ <p><i>Frametype:<br>
+ </i>Bit 0 and Bit 1 of the structure describe the<i> </i>possibilities of the CAN controller. The following values are defined:</p>
+ <p><code>CYGNUM_CAN_HDI_FRAMETYPE_STD // receives only standard frame<br>
+ CYGNUM_CAN_HDI_FRAMETYPE_EXT_PASSIVE // can recieve but not send extended frames<br>
+ CYGNUM_CAN_HDI_FRAMETYPE_EXT_ACTIVE // can send and receive extended frames<br>
+ </code></p>
+ <p><i>FullCAN:<br>
+ </i>If the Bit 2 is set to one, the CAN controller supports more than one message buffer.</p>
+ <p><code>CYGNUM_CAN_HDI_FULLCAN // supports more than one message buffer<br>
+ </code></p>
+ <p><i>SW-Filter:<br>
+ </i>If Bit3 is set to one then the CAN driver supports some kind of software message filtering.</p>
+ <p><code>CYGNUM_CAN_HDI_FILT_SW // software message filtering supported<br>
+ </code></p>
+ <p><i>Timestamp:<br>
+ </i>If Bit 4 is set to one then the CAN hardware supports timestamps for CAN messages</p>
+ <p><code>CYGNUM_CAN_HDI_TIMESTAMP // CAN hardware supports timestamps<br>
+ </code></p>
+ <h4>Reading message buffer configuration</h4>
+ <p><code>typedef struct cyg_can_msgbox_info_st<br>
+ </code><code>{<br>
+ c</code><code>yg_uint8 count; // number of message buffers available for this device<br>
+ </code><code>cyg_uint8 free; // number of free message buffers<br>
+ </code><code>} cyg_can_msgbuf_info;</code></p>
+ <p><code>CYG_IO_GET_CONFIG_CAN_MSGBUF_INFO</code> - If the CAN hardware supports more than one message buffer for reception of CAN message (flag <code>CYGNUM_CAN_HDI_FULLCAN </code>is set after reading hardware description interface with <code>CYG_IO_GET_CONFIG_CAN_HDI</code>) then this function reads the number of message buffers the CAN hardware supports and the number of free message buffers. The field<i> count</i> contains the number of message buffers supported by device and the field <i>free</i> contains the number of free message buffers. The free message buffers are available for setting up remote buffers (<code>CYG_IO_SET_CONFIG_CAN_REMOTE_BUF)</code> and message filters (<code>CYG_IO_SET_CONFIG_CAN_FILTER_MSG</code>).</p>
+ <h4>Reading state of CAN hardware</h4>
+ <p><code>typedef enum<br>
+ {<br> CYGNUM_CAN_STATE_ACTIVE, // CAN controller is active, no errors<br>
+ </code><code>CYGNUM_CAN_STATE_STOPPED, // CAN controller is in stopped mode<br>
+ </code><code>CYGNUM_CAN_STATE_STANDBY, // CAN controller is in Sleep mode<br>
+ </code><code>CYGNUM_CAN_STATE_BUS_WARN, // CAN controller is active, warning level is reached<br>
+ </code><code>CYGNUM_CAN_STATE_ERR_PASSIVE, // CAN controller went into error passive mode<br>
+ </code><code>CYGNUM_CAN_STATE_BUS_OFF, // CAN controller went into bus off mode<br>
+ </code><code>CYGNUM_CAN_STATE_PHY_FAULT, // General failure of physical layer detected (if supported by hardware)<br>
+ </code><code>CYGNUM_CAN_STATE_PHY_H, // Fault on CAN-H detected (Low Speed CAN)<br>
+ </code><code>CYGNUM_CAN_STATE_PHY_L, // Fault on CAN-L detected (Low Speed CAN)<br>
+ </code><code>} cyg_can_state;</code></p>
+ <p><code>CYG_IO_GET_CONFIG_CAN_STATE</code> - This function retrieves the present state of the CAN controller. Possible values are defined in the <code>cyg_can_state</code> enumeration.</p>
+ <h4>Drain output buffers</h4>
+ <p><code>CYG_IO_SET_CONFIG_CAN_OUTPUT_DRAIN</code> - This function waits for any buffered output to complete. This function only completes when there is no more data remaining to be sent to the device.</p>
+ <h4>Flush output buffers</h4>
+ <p><code>CYG_IO_SET_CONFIG_CAN_OUTPUT_FLUSH</code> - This function discards any buffered output for the device.</p>
+ <h4>Flush input buffers</h4>
+ <p><code>CYG_IO_SET_CONFIG_CAN_INPUT_FLUSH</code> - This function discards any buffered input for the device.</p>
<h4>Configuring blocking/nonblocking calls</h4>
+
+
+
+
By default all calls to <code>cyg_io_read()</code> and<code> cyg_io_write()</code> are blocking calls. The config keys<br>
<br>
<code>CYG_IO_GET_CONFIG_READ_BLOCKING<br>
<br>
</code>enable switching between blocking and nonblocking calls separatly for read and write calls. If blocking calls are configured then the read/write functions return only if a message was stored into TX buffer or a event was received from RX buffer. If nonblocking calls are enabled and there is no space in TX buffer or RX buffer is empty then the function returns immediatelly with <code>-EAGAIN</code>. If nonblocking calls are enabled and additionally timeouts are supported by driver, then the read/write functions wait until timeout value is expired and then return witn <code>-EINTR</code>. If the read/write operation succeeds during the timed wait then the functions return succesfully with<code> ENOERR</code>.
+ <h4>Message buffer configuration</h4>
+ <p><code>typedef struct cyg_can_msgbox_cfg_st<br>
+ </code><code>{<br>
+ </code><code>cyg_can_msgbuf_cfg_id cfg_id; // configuration id - cfg. what to do with message buffer<br>
+ </code><code>cyg_can_msgbuf_handle handle; // handle to message buffer<br>
+ </code><code>cyg_can_message msg; // CAN message - for configuration of buffer<br>
+ </code><code>} cyg_can_msgbuf_cfg;</code></p>
+ <p>Full CAN controllers often support more the one message buffer. These message buffers are often configurable for transmission or reception of certain CAN messages or as a remote buffer. If a CAN hardware supports more than one message buffer then it is possible to configure the CAN hardware to receive only CAN messages with certain identifiers or to configure hardware support for remote buffers. If message filtering is done by hardware, the number of received CAN messages decreases and so also the time for processing received CAN messages and the memory required for buffering received messages decreases. This saves valuable memory and processing time. The eCos CAN driver supports a generic way of adding message filters or remote buffers. By default the CAN driver is configured for reception of any kind of CAN standard and extended frames. Configuration of message buffers is done by calling <code>cyg_io_set_config() </code>with the config key:</p>
+ <p><code>CYG_IO_SET_CONFIG_CAN_MSGBUF<br>
+ </code></p>
+ <p>and exchanging <code>cyg_can_msgbuf_cfg </code>data structures. The <i>cfg_id</i> field contains the configuration ID that tells the driver what to do with a message buffer, the <i>handle</i> field contains a reference to a certain message buffer and the <i>msg</i> field is necessary for configuration of message buffer parameters. The following configuration identifiers are supported:</p>
+ <p><code>CYGNUM_CAN_MSGBUF_RESET_ALL // clears alle message buffers, no message will be received, all remote buffers deleted<br>
+ </code><code>CYGNUM_CAN_MSGBUF_RX_FILTER_ALL // cfg driver for reception of all can messges<br>
+ </code><code>CYGNUM_CAN_MSGBUF_RX_FILTER_ADD // add single message filter<br>
+ </code><code>CYGNUM_CAN_MSGBUF_REMOTE_BUF_ADD // add new remote response buffer<br>
+ </code><code>CYGNUM_CAN_MSGBUF_REMOTE_BUF_WRITE // stores data into existing remote buffer (remote buf handle required)</code></p>
+ <p>Example code for resetting all message buffers:</p>
+ <p><code>cyg_can_msgbuf_cfg msgbox_cfg;</code></p>
+ <p><code>msgbox_cfg.cfg_id = CYGNUM_CAN_MSGBUF_RESET_ALL;<br>
+ </code><code>len = sizeof(msgbox_cfg);<br>
+ </code><code>if (ENOERR != cyg_io_set_config(hDrvFlexCAN, CYG_IO_SET_CONFIG_CAN_MSGBUF ,&msgbox_cfg, &len))<br>
+ </code><code>{<br>
+ </code><code>// handle configuration error<br>
+ </code><code>} </code></p>
<h4>Remote frame response buffer configuration</h4>
<p>The remote frame is a message frame which is transmitted to request a data frame. Some CAN hardware generates receive interrupts when a remote transmission request arrives. Other CAN hardware, i.e. the FlexCAN module, does not generate any receive interrupt. These CAN hardware chips, i.e. the FlexCAN module, can be configured to transmit a data frame automatically in response to a remote frame. In oder to support any kind of CAN hardware the eCos CAN driver provides a generic handling of remote transmission requests.</p>
- <p>The transmission of the data frame in response of the remote frame is completely handled by the CAN driver. If the hardware driver, like the driver for the FlexCAN modul, supports harware message buffers, then the response frame is automatically transmitted if a remote transmission request with a matching ID arrives. If a CAN hardware does provide hardware support for sending the data frames in response to a remote frame, then this need to be implemented in software by the hardware device driver.</p>
- <p>In order to respond to a remote frame, a remote frame reponse buffer need to be initialized before a data frame CAN be sent in response to a remote frame. This is achieved by by exchanging <code>cyg_can_rtr_buf_t </code>data structures with the driver via the <code>cyg_io_set_config()</code> function using the config key <code>CYG_IO_SET_CONFIG_CAN_RTR_BUF</code>. Once the buffer is initialized, the CAN data can be changed at any time by the application.</p>
- <p><code>typedef struct cyg_can_rtr_buf_st<br>
- </code><code>{<br>
- cyg_int8 handle;<br>
- cyg_can_message msg;<br>
- </code><code>} cyg_can_rtr_buf_t;<br>
+ <p>The transmission of the data frame in response to a remote frame is completely handled by the CAN driver. If the hardware driver, like the driver for the FlexCAN modul, supports harware message buffers, then the response frame is automatically transmitted if a remote transmission request with a matching ID arrives. If a CAN hardware does not provide hardware support for sending data frames in response to a remote frame, then this need to be implemented in software by the hardware device driver.</p>
+ <p>It is always possible to add remote response buffers. It does not matter if the driver is configured for reception of all CAN messages or if message filtering is used. As long as there are free message buffers available, it is possible to add remote response buffers.</p>
+ <p>In order to respond to a remote frame, a remote frame reponse buffer need to be initialized before a data frame can be sent in response to a remote frame. This is achieved by by exchanging <code>cyg_can_remote_buf </code>data structures with the driver via the <code>cyg_io_set_config()</code> function using the config key <code>CYG_IO_SET_CONFIG_CAN_MSGBUF</code>. Once the buffer is initialized, the CAN data can be changed at any time by the application.</p>
+ <p><code>typedef struct cyg_can_msgbuf_cfg_st<br>
+ </code><code>{<br> cyg_can_msgbuf_cfg_id cfg_id; // configuration id - cfg. what to do with message buffer<br>
+ </code><code>cyg_can_msgbuf_handle handle; // handle to message buffer<br>
+ </code><code>cyg_can_message msg; // CAN message - for configuration of buffer<br>
+ } cyg_can_remote_buf;<br>
</code></p>
- <p>The CAN frame that should be transmitted in response to a remote frame is stored in the<i> msg</i> field of the <code>cyg_can_rtr_buf_t </code>data structure. If there is no buffer initialized for this data, the value of the <i>handle</i> field need to be set to <code>CYGNUM_CAN_RTR_BUF_INIT</code>. After the call to <code>cyg_io_set_config()</code> the <i>handle</i> field contains a valid value ( >= 0) or the value <code>CYGNUM_CAN_RTR_BUF_NA</code> ( < 0) if no free buffer is available. With the valid handle value the CAN data can be changed later by calling <code>cyg_io_set_config().</code></p>
+ <p>The CAN frame that should be transmitted in response to a remote frame is stored in the<i> msg</i> field of the <code>cyg_can_remote_buf </code>data structure. If there is no buffer initialized for this data, the value of the <i>handle</i> field need to be set to <code>CYGNUM_CAN_MSGBUF_INIT</code>. After the call to <code>cyg_io_set_config()</code> the <i>handle</i> field contains a valid value ( >= 0) or the value <code>CYGNUM_CAN_MSGBUF_NA</code> ( < 0) if no free buffer is available. With the valid handle value the CAN data can be changed later by calling <code>cyg_io_set_config(). </code>Before adding remote buffers the device should be stopped and after configuration it should be set into operational mode again</p>
<p>Example code for setting up a remote response buffer:</p>
- <p><code>cyg_can_rtr_buf_t rtr_buf;<br>
+ <p><code>cyg_can_remote_buf rtr_buf;<br>
<br>
- // prepare the remote response buffer<br>
- </code><code>rtr_buf.handle = CYGNUM_CAN_RTR_BUF_INIT;<br>
+ // prepare the remote response buffer<br>rtr_buf.cfg_id = CYGNUM_CAN_MSGBUF_REMOTE_BUF_ADD;<br>
+ </code><code>rtr_buf.handle = CYGNUM_CAN_MSGBUF_INIT;<br>
</code><code>rtr_buf.msg.id = 0x7FF;<br>
</code><code>rtr_buf.msg.ext = CYGNUM_CAN_ID_STD;<br>
</code><code>rtr_buf.msg.rtr = CYGNUM_CAN_FRAME_DATA;<br>
</code><code>rtr_buf.msg.dlc = 1;<br>
</code><code>rtr_buf.msg.data[0] = 0xAB;<br>
<br>
+
len = sizeof(rtr_buf);<br>
</code><code>if (ENOERR != cyg_io_set_config(hDrvFlexCAN, <br>
+ CYG_IO_SET_CONFIG_CAN_MSGBUF,<br>
- CYG_IO_SET_CONFIG_CAN_RTR_BUF ,<br>
&rtr_buf, &len))<br>
</code><code>{<br>
+
// handle configuration error<br>
</code><code>} <br>
</code><code><br>
- </code><code>if (rtr_buf.handle == CYGNUM_CAN_RTR_BUF_NA)<br>
+ </code><code>if (rtr_buf.handle == CYGNUM_CAN_MSGBUF_NA)<br>
</code><code>{<br>
+
// no free message buffer available - handle this problem here<br>
</code><code>}<br>
- <br>// change CAN data for a buffer that is already initialized<br>
+ <br>
+ <br>
+
+ // change CAN data for a buffer that is already initialized<br>
+ </code><code>rtr_buf.cfg_id = CYGNUM_CAN_MSGBUF_REMOTE_BUF_WRITE;<br>
+
+
rtr_buf.msg.data[0] = 0x11;<br>
<br>
+
+
len = sizeof(rtr_buf);<br>
</code><code>if (ENOERR != cyg_io_set_config(hDrvFlexCAN, <br>
- CYG_IO_SET_CONFIG_CAN_RTR_BUF ,<br>
+ CYG_IO_SET_CONFIG_CAN_MSGBUF,<br>
+
+
&rtr_buf, &len))<br>
</code><code>{<br>
+
+
// handle configuration error<br>
</code><code>} <br>
</code></p>
+ <h4>Message filter configuration</h4>
+ <p> If message filtering is done by hardware the number of received CAN messages decreases and so also the time for processing received CAN messages and the memory required for buffering received messages decreases. This saves valuable memory and processing time. The eCos CAN driver supports a generic way of adding message filters. By default the CAN driver is configured for reception of any kind of CAN standard and extended frames. As soon as a message filter is added, the CAN driver will only receive the CAN frames with the identifier of the CAN filter. By adding a number of message filters it is possible for the CAN hardware to receive an number of different CAN messages.</p>
+ <p>Adding message filters is only possible if driver is not configured for reception of all available CAN messages. If driver is configured for recption of all CAN messages then message buffers neet to be reset before adding single message filters.</p>
+ <p>In order to add a message filter, a message buffer need to be initialized. This is achieved by by exchanging <code>cyg_can_filter </code>data structures with the driver via the <code>cyg_io_set_config()</code> function using the config key <code>CYG_IO_SET_CONFIG_CAN_MSGBUF</code>. Once the buffer is initialized, the CAN hardware can recive messages with the identifier of the filter.</p>
+ <p><code>typedef struct cyg_can_msgbox_cfg_st<br>
+ </code><code>{<br>
+ cyg_can_msgbuf_cfg_id cfg_id;<br>
+ </code><code>cyg_can_msgbuf_handle handle;<br>
+
+ </code><code>cyg_can_message msg;<br>
+ </code><code>} cyg_can_filter;</code></p>
+ <p>After the call to <code>cyg_io_set_config()</code> the <i>handle</i> field contains a valid value ( >= 0) or the value <code>CYGNUM_CAN_MSGBUF_NA</code> ( < 0) if no free buffer is available. Before adding message filters the device should be stopped and after configuration it should be set into operational mode again</p>
+ <p>Example code for setting up a message filter:</p>
+ <p><code>cyg_can_msgbuf_cfg msgbox_cfg;<br>
+ cyg_can_filter rx_filter;<br>
+ <br>
+ // reset all message buffers</code><br>
+ <code>msgbox_cfg.cfg_id = CYGNUM_CAN_MSGBUF_RESET_ALL;<br>
+ </code><code>len = sizeof(msgbox_cfg);<br>
+ </code><code>if (ENOERR != cyg_io_set_config(hDrvFlexCAN, CYG_IO_SET_CONFIG_CAN_MSGBUF ,&msgbox_cfg, &len))<br>
+ </code><code>{<br>
+ </code><code>// handle configuration error<br>
+ </code><code>} <br>
+ <br>
+ </code><code>// prepare the message filter<br>
+ rx_filter.cfg_id = CYGNUM_CAN_MSGBUF_RX_FILTER_ADD<br>
+ </code><code>rx_filter.msg.id = 0x800;<br>
+ rx_filter.msg.ext = CYGNUM_CAN_ID_EXT;<br>
+ <br>
+ len = sizeof(rx_filter);<br>
+ if (ENOERR != cyg_io_set_config(hDrvFlexCAN,<br>
+ CYG_IO_SET_CONFIG_CAN_MSGBUF,<br>
+ &rx_filter, &len))<br>
+ </code><code>{<br>
+ </code><code>// handle configuration error;<br>
+ </code><code>}<br>
+ </code><code>else if (CYGNUM_CAN_MSGBUF_NA == rx_filter.handle)<br>
+ </code><code>{<br>
+ // no free message buffer available - handle this problem here<br>
+ }</code></p>
+ <h4>Receive all CAN messages</h4>After startup of your device the CAN driver is configured for reception of all available CAN messages. If you change this configuration by adding single message filters then you can reset this default state with the configuration ID: <p><code>CYGNUM_CAN_MSGBUF_RX_FILTER_ALL</code> </p>
+ <p>A call to this function will clear all message filters and remote buffers and prepares the CAN hardware for recption of any kind of CAN standard and extended frames. It is not neccesary to reset the message buffer configuration before this configuration is setup because this should be done by device driver.</p>
+ <p>Example code for setup of a receive all CAN frames configuration:</p>
+ <p><code>cyg_can_filter rx_filter;<br>
+ <br>
+ // now setup a RX all configuration<br>
+ </code><code>rx_filter.cfg_id = CYGNUM_CAN_MSGBUF_RX_FILTER_ALL;<br>
+ </code><code>len = sizeof(rx_filter);<br>
+ </code><code>if (ENOERR != cyg_io_set_config(hDrvFlexCAN, CYG_IO_SET_CONFIG_CAN_MSGBUF , &rx_filter, &len))<br>
+ </code><code>{<br>
+ </code><code>CYG_TEST_FAIL_FINISH("Error writing config of /dev/can0");<br>
+ </code><code>}</code></p>
+ <h4>Set mode of CAN hardware</h4>
+ <p><code>typedef enum <br>
+ </code><code>{<br>
+ CYGNUM_CAN_MODE_STOP, // set controller into stop mode<br>
+ </code><code>CYGNUM_CAN_MODE_START, // set controller into operational mode<br>
+ </code><code>CYGNUM_CAN_MODE_STANDBY // set controller into standby / sleep mode<br>
+ } cyg_can_mode;</code></p>
+ <p><code>CYG_IO_SET_CONFIG_CAN_MODE</code> - This function changes the operating mode of the CAN controller. Possible values for mode are defined in the <code>cyg_can_mode</code> enumeration. Befor the hardware configuration of the device is changed, that means if baudrate is changed or the message buffer and filter configuration is changed, the CAN hardware should be set into stop mode and if configuration is finished, then device should be set back into operational mode. Before the device is set into standby mode, the output buffers should be flushed or drained because transmission of a CAN message may wake up the CAN hardware. If a received message wakes up the CAN hardware from standby mode then a <code>CYGNUM_CAN_EVENT_LEAVING_STANDBY</code> event will be inserted into receive message buffer or the <code>CYGNUM_CAN_EVENT_LEAVING_STANDBY </code>flag will be set for the message that caused wake up of CAN hardware.</p>
<h2>FlexCAN device driver</h2>
<p>The FlexCAN module is a communication controller implementing the controller area network (CAN) protocol, an asynchronous communications protocol used in automotive and industrial control systems. It is a high speed (1 Mbit/sec), short distance, priority based protocol which can communicate using a variety of mediums (for example, fiber optic cable or an unshielded twisted pair of wires). The FlexCAN supports both the standard and extended identifier (ID) message formats specified in the CAN protocol specification, revision 2.0, part B.</p>
- <p>It supports up to 16 flexible flexible message buffers of 0–8 bytes data length, each configurable as Rx or Tx, all supporting standard and extended messages.</p>
- <p>The FlexCAN device driver currently supports two message buffers for sending and receiving CAN messages - message buffer 14 for receiving CAN messages and message buffer 15 for transmitting CAN messages. The receive mask of message buffer 14 is configured in a way that it is possible to receive any kind of CAN message. Message buffers 0 - 13 can be used for setting up remote frame response buffers.</p>
+ <p>It supports up to 16 flexible flexible message buffers of 0-8 bytes data length, each configurable as Rx or Tx, all supporting standard and extended messages.</p>
+ <p>The message buffer 16 of the FlexCAN modul is reserved for transmission of CAN messages. Message buffers 1 - 15 are available for configuration of remote buffers and message filters. If the FlexCAN modul is configured for reception of all CAN frames, then the user can select the number of buffers used for reception of CAN frames. The interrupt priority of each message box is configurable.</p>
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\ No newline at end of file
#include <cyg/hal/drv_api.h>
+// define standard and extended id masks
+#define CYG_CAN_STD_ID_MASK 0x7FF
+#define CYG_CAN_EXT_ID_MASK 0x1FFFFFFF
+
+//
+// include device header
+// a device can define its own types of CAN messages and CAN events. It does this
+// in the device header CYGDAT_IO_CAN_DEVICE_INL. Because this header is included
+// here, the device header file can use all definitions in the files included
+// in the include section above
+//
+#ifdef CYGDAT_IO_CAN_DEVICE_INL
+#include CYGDAT_IO_CAN_DEVICE_INL // include device header
+#endif
+
+//
+// If the device did not define its own type of CAN message and CAN event, then
+// we define standard types here and use the types cyg_can_message and cyg_can_event
+// from CAN I/O layer
+//
+#ifndef CYG_CAN_MSG_T
+#define CYG_CAN_MSG_T cyg_can_message
+#define CYG_CAN_EVENT_T cyg_can_event
+#define CYG_CAN_WRITE_MSG(_devmsg_ptr_, _iomsg_ptr_) (*(_devmsg_ptr_) = *(_iomsg_ptr_))
+#define CYG_CAN_READ_EVENT(_ioevent_ptr_, _devevent_ptr_) (*(_ioevent_ptr_) = *(_devevent_ptr_))
+#endif
+
+
//===========================================================================
// FORWARD DECLARATIONS
//===========================================================================
//
struct can_channel
{
- can_lowlevel_funs *funs;
- can_callbacks_t *callbacks;
- void *dev_priv; // Whatever is needed by actual device routines
- cyg_can_info_t config; // Current configuration
- bool init; // true if driver is already initialized
- can_cbuf_t out_cbuf; // buffer for transmit can messages
- can_cbuf_t in_cbuf; // buffer with received can events
+ can_lowlevel_funs *funs;
+ can_callbacks_t *callbacks;
+ void *dev_priv; // Whatever is needed by actual device routines
+ cyg_can_info_t config; // Current configuration
+ bool init; // true if driver is already initialized
+ can_cbuf_t out_cbuf; // buffer for transmit can messages
+ can_cbuf_t in_cbuf; // buffer with received can events
+#ifdef CYGOPT_IO_CAN_SUPPORT_CALLBACK
+ cyg_can_callback_cfg callback_cfg; // Callback configuration
+#endif
};
+#ifdef CYGOPT_IO_CAN_SUPPORT_CALLBACK
+#define CYG_CAN_CALLBACK_INIT , {(cyg_can_event_cb_t) 0, 0, 0}
+#else
+#define CYG_CAN_CALLBACK_INIT
+#endif
#define CAN_CHANNEL_USING_INTERRUPTS(_l, \
false, \
CBUF_INIT(_out_buf, _out_buflen, _TX_TIMEOUT), \
CBUF_INIT(_in_buf, _in_buflen, _RX_TIMEOUT) \
+ CYG_CAN_CALLBACK_INIT \
};
//
struct can_lowlevel_funs
{
- bool (*putmsg)(can_channel *priv, cyg_can_message *pmsg, void *pdata); // send one can message - return true if consumed
- bool (*getevent)(can_channel *priv, cyg_can_event *pevent, void *pdata); // fetch one CAN event from device
- Cyg_ErrNo (*set_config)(can_channel *priv, // Change hardware configuration (baud rate, etc)
+ bool (*putmsg)(can_channel *priv, CYG_CAN_MSG_T *pmsg, void *pdata); // send one can message - return true if consumed
+ bool (*getevent)(can_channel *priv, CYG_CAN_EVENT_T *pevent, void *pdata); // fetch one CAN event from device
+ Cyg_ErrNo (*get_config)(can_channel *priv, // query hardware configuration (baud rate, etc)
+ cyg_uint32 key,
+ const void *xbuf,
+ cyg_uint32 *len);
+ Cyg_ErrNo (*set_config)(can_channel *priv, // Change hardware configuration (baud rate, etc)
cyg_uint32 key,
const void *xbuf,
cyg_uint32 *len);
- void (*start_xmit)(can_channel *priv); // Enable the transmit channel and turn on transmit interrupts
- void (*stop_xmit)(can_channel *priv); // Disable the transmit channel and turn transmit interrupts off
+ void (*start_xmit)(can_channel *priv); // Enable the transmit channel and turn on transmit interrupts
+ void (*stop_xmit)(can_channel *priv); // Disable the transmit channel and turn transmit interrupts off
};
-#define CAN_LOWLEVEL_FUNS(_l,_putmsg,_getevent,_set_config,_start_xmit,_stop_xmit) \
-can_lowlevel_funs _l = { \
- _putmsg, \
- _getevent, \
- _set_config, \
- _start_xmit, \
- _stop_xmit \
+#define CAN_LOWLEVEL_FUNS(_l,_putmsg,_getevent,_get_config,_set_config,_start_xmit,_stop_xmit) \
+can_lowlevel_funs _l = { \
+ _putmsg, \
+ _getevent, \
+ _get_config, \
+ _set_config, \
+ _start_xmit, \
+ _stop_xmit \
};
extern cyg_devio_table_t cyg_io_can_devio;
CYGNUM_CAN_KBAUD_500,
CYGNUM_CAN_KBAUD_800,
CYGNUM_CAN_KBAUD_1000,
+ CYGNUM_CAN_KBAUD_AUTO, // automatic detection of baudrate (if supported by hardware)
} cyg_can_baud_rate_t;
#define CYGNUM_CAN_KBAUD_MIN CYGNUM_CAN_KBAUD_10
#define CYGNUM_CAN_KBAUD_MAX CYGNUM_CAN_KBAUD_1000
CYGNUM_CAN_EVENT_LEAVING_STANDBY = 0x0200, // CAN hardware leaves standby / power don mode or is waked up
CYGNUM_CAN_EVENT_ENTERING_STANDBY = 0x0400, // CAN hardware enters standby / power down mode
CYGNUM_CAN_EVENT_ARBITRATION_LOST = 0x0800, // arbitration lost
- CYGNUM_CAN_EVENT_DEVICE_CHANGED = 0x1000, // device changed event
+ CYGNUM_CAN_EVENT_FILTER_ERR = 0x1000, // CAN message filter / acceptance filter error
+ CYGNUM_CAN_EVENT_PHY_FAULT = 0x2000, // General failure of physical layer detected (if supported by hardware)
+ CYGNUM_CAN_EVENT_PHY_H = 0x4000, // Fault on CAN-H detected (Low Speed CAN)
+ CYGNUM_CAN_EVENT_PHY_L = 0x8000, // Fault on CAN-L detected (Low Speed CAN)
} cyg_can_event_flags;
+//
+// State of CAN controller
+//
+typedef enum e_cyg_can_state
+{
+ CYGNUM_CAN_STATE_ACTIVE, // CAN controller is active, no errors
+ CYGNUM_CAN_STATE_STOPPED, // CAN controller is in stopped mode
+ CYGNUM_CAN_STATE_STANDBY, // CAN controller is in Sleep mode
+ CYGNUM_CAN_STATE_BUS_WARN, // CAN controller is active, warning level is reached
+ CYGNUM_CAN_STATE_ERR_PASSIVE, // CAN controller went into error passive mode
+ CYGNUM_CAN_STATE_BUS_OFF, // CAN controller went into bus off mode
+ CYGNUM_CAN_STATE_PHY_FAULT, // General failure of physical layer detected (if supported by hardware)
+ CYGNUM_CAN_STATE_PHY_H, // Fault on CAN-H detected (Low Speed CAN)
+ CYGNUM_CAN_STATE_PHY_L, // Fault on CAN-L detected (Low Speed CAN)
+ CYGNUM_CAN_STATE_CONFIG, // CAN controller is in configuration state
+} cyg_can_state;
+
+//
+// Identifiers for operating mode of the CAN controller.
+//
+typedef enum e_cyg_can_mode
+{
+ CYGNUM_CAN_MODE_STOP, // set controller into stop mode
+ CYGNUM_CAN_MODE_START, // set controller into operational mode
+ CYGNUM_CAN_MODE_STANDBY,// set controller into standby / sleep mode
+ CYGNUM_CAN_MODE_CONFIG // set controller and driver into a state where it is safe to add/delete message buffers
+} cyg_can_mode;
+
//
// Type of CAN identifier.
//
-typedef enum
+typedef enum e_cyg_can_id_type
{
CYGNUM_CAN_ID_STD = 0x00, // standard ID 11 Bit
CYGNUM_CAN_ID_EXT = 0x01 // extended ID 29 Bit
//
// Type of CAN frame
//
-typedef enum
+typedef enum e_cyg_can_frame_type
{
CYGNUM_CAN_FRAME_DATA = 0x00, // CAN data frame
CYGNUM_CAN_FRAME_RTR = 0x01 // CAN remote transmission request
} cyg_can_frame_type;
+//
+// Message buffer configuration identifier - we do not use an enum here so that
+// a specific device driver can add its own configuration identifier
+//
+typedef cyg_uint8 cyg_can_msgbuf_cfg_id;
+#define CYGNUM_CAN_MSGBUF_RESET_ALL 0 // no message will be received, all remote buffers deleted
+#define CYGNUM_CAN_MSGBUF_RX_FILTER_ALL 1 // cfg driver for reception of all can messges
+#define CYGNUM_CAN_MSGBUF_RX_FILTER_ADD 2 // add single message filter
+#define CYGNUM_CAN_MSGBUF_REMOTE_BUF_ADD 3 // add new remote response buffer
+#define CYGNUM_CAN_MSGBUF_REMOTE_BUF_WRITE 4 // store data into existing remote buffer (remote buf handle required)
+
+
+//
+// CAN message data - this union is a container for the 8 data bytes of a can
+// message and the union is alway part of a can message - no matter if this type
+// is defined by generic CAN layer or by CAN hardware device driver
+//
+typedef union u_cyg_can_msg_data
+{
+ cyg_uint8 bytes[8]; // byte access (array of 8 bytes)
+ cyg_uint16 words[4]; // word access (array of 4 words)
+ cyg_uint32 dwords[2]; // double word access (array of 2 dwords)
+} cyg_can_msg_data;
//
// CAN message type for transport or transmit of CAN messages
+// The message data is a union. This enables byte, word and dword access and
+// also ensures a 4 byte alignment of the message data
//
-typedef struct can_message
+typedef struct st_cyg_can_message
{
cyg_uint32 id; // 11 Bit or 29 Bit CAN identifier - cyg_can_id_type
- cyg_uint8 data[8];// 8 data bytes
+ cyg_can_msg_data data; // CAN data (8 data bytes)
cyg_can_id_type ext; // CYGNUM_CAN_ID_STD = 11 Bit CAN id, CYGNUM_CAN_ID_EXT = 29 Bit CAN id
cyg_can_frame_type rtr; // CYGNUM_CAN_FRAME_DATA = data frame, CYGNUM_CAN_FRAME_RTR = remote transmission request
cyg_uint8 dlc; // data length code (number of bytes (0 - 8) containing valid data
cyg_can_baud_rate_t baud;
} cyg_can_info_t;
+
+#define CYG_CAN_INFO_INIT(_baud) \
+ { _baud}
+
//
// buffer configuration - bufsize and count for tx are the number of messages
// and for rx the number of events
//
typedef struct cyg_can_buf_info_st
{
- cyg_int32 rx_bufsize;
- cyg_int32 rx_count;
- cyg_int32 tx_bufsize;
- cyg_int32 tx_count;
+ cyg_uint32 rx_bufsize;
+ cyg_uint32 rx_count;
+ cyg_uint32 tx_bufsize;
+ cyg_uint32 tx_count;
} cyg_can_buf_info_t;
+//
+// Message box configuration
+//
+typedef struct cyg_can_msgbox_info_st
+{
+ cyg_uint16 count; // number of message buffers available for this device
+ cyg_uint16 free; // number of free message buffers
+} cyg_can_msgbuf_info;
+
+
//
// Timeout configuration
//
cyg_uint32 tx_timeout;
} cyg_can_timeout_info_t;
+
//
-// this data type defines a remote transmission request buffer
+// this data type defines a handle to a message buffer or message box
+// of the CAN hardware device
//
-typedef struct cyg_can_rtr_buf_st
+typedef cyg_int32 cyg_can_msgbuf_handle;
+
+
+//
+// structure for configuration of message buffers
+//
+typedef struct cyg_can_msgbox_cfg_st
{
- cyg_int8 handle;
- cyg_can_message msg;
-} cyg_can_rtr_buf_t;
+ cyg_can_msgbuf_cfg_id cfg_id; // configuration id - cfg. what to do with message buffer
+ cyg_can_msgbuf_handle handle; // handle to message buffer
+ cyg_can_message msg; // CAN message - for configuration of buffer
+} cyg_can_msgbuf_cfg;
//
-// Values for the handle field of the cyg_can_rtr_buf_t data structure
+// this data type defines a CAN message filter. It consits
+// of a handle to a message box or message buffer and a CAN message.
+// For the filtering only the id and the ext field of the CAN message are
+// important. The values of the other fields doesn't matter
//
-#define CYGNUM_CAN_RTR_BUF_NA -0x01 // no free message buffer available
-#define CYGNUM_CAN_RTR_BUF_INIT -0x02 // initialize the remote message buffer
+typedef cyg_can_msgbuf_cfg cyg_can_filter;
+//
+// this data type defines a remote buffer. It consits
+// of a handle to a message box or message buffer and the message data
+// to send on reception of a remote request
+//
+typedef cyg_can_msgbuf_cfg cyg_can_remote_buf;
+
+//
+// Values for the handle field of the cyg_can_rtr_buf, cyg_can_filter and
+// cyg_can_msgbuf_cfg data structure
+//
+#define CYGNUM_CAN_MSGBUF_NA -0x01 // no free message buffer available
+
+
+//
+// The Hardware Description Interface provides a method to gather information
+// about the CAN hardware and the functionality of the driver. For
+// this purpose the following structure is defined:
+//
+// Support flags:
+// | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+// +-------+-------+-------+-------+--------+-------+-------+--------+
+// | res | res | res |timest.|autobaud|FullCAN| Frametype |
+//
+typedef struct cyg_can_hdi_st
+{
+ cyg_uint8 support_flags;
+ cyg_uint8 controller_type;
+} cyg_can_hdi;
+
+//
+// Bit 0 and Bit 1 of the structure member support_flags describe the
+// possibities of the CAN controller. The following values are defined:
+//
+#define CYGNUM_CAN_HDI_FRAMETYPE_STD 0x00 // standard frame (11-bit identifier), 2.0A
+#define CYGNUM_CAN_HDI_FRAMETYPE_EXT_PASSIVE 0x01 // extended frame (29-bit identifier), 2.0B passive
+#define CYGNUM_CAN_HDI_FRAMETYPE_EXT_ACTIVE 0x02 // extended frame (29-bit identifier), 2.0B active
+#define CYGNUM_CAN_HDI_FULLCAN 0x04 // controller supports more than one receive and transmit buffer
+#define CYGNUM_CAN_HDI_AUTBAUD 0x08 // driver supports automatic baudrate detection
+#define CYGNUM_CAN_HDI_TIMESTAMP 0x10 // driver supports timestamps
+
+
+//
+// Callback configuration structure.
+//
+
+typedef void (*cyg_can_event_cb_t)(cyg_uint16, CYG_ADDRWORD);
+//
+// flag_mask should be set with a combination of CYGNUM_CAN_EVENT_* flags.
+// If one of these events happens, the callback function will be called,
+// with the actually event flags passed as a parameter.
+//
+typedef struct cyg_can_callback_cfg_st
+{
+ cyg_can_event_cb_t callback_func; // callback function
+ cyg_uint16 flag_mask; // flags mask
+ CYG_ADDRWORD data; // data passed to callback
+} cyg_can_callback_cfg;
+
+
+//===========================================================================
+// CAN MESSAGE ACCESS MACROS
+//
+// An application should not access a cyg_can_message directly instead it
+// should use these macros for all manipulations to a CAN message.
+//===========================================================================
+
+//---------------------------------------------------------------------------
+// Frame type macros
+//
+#define CYG_CAN_MSG_SET_FRAME_TYPE(_msg_, _type_) ((_msg_).rtr = (_type_))
+#define CYG_CAN_MSG_GET_FRAME_TYPE(_msg_) ((_msg_).rtr)
+#define CYG_CAN_MSG_SET_RTR(_msg_) ((_msg_).rtr = CYGNUM_CAN_FRAME_RTR)
+#define CYG_CAN_MSG_IS_REMOTE(_msg_) ((_msg_).rtr == CYGNUM_CAN_FRAME_RTR)
+
+
+//---------------------------------------------------------------------------
+// ID type macros
+//
+#define CYG_CAN_MSG_SET_ID_TYPE(_msg_, _type_) ((_msg_).ext = (_type_))
+#define CYG_CAN_MSG_GET_ID_TYPE(_msg_) ((_msg_).ext)
+#define CYG_CAN_MSG_SET_EXT(_msg_) ((_msg_).ext = CYGNUM_CAN_ID_EXT)
+#define CYG_CAN_MSG_SET_STD(_msg_) ((_msg_).ext = CYGNUM_CAN_ID_STD)
+#define CYG_CAN_MSG_IS_EXT(_msg_) ((_msg_).ext == CYGNUM_CAN_ID_EXT)
+
+
+//---------------------------------------------------------------------------
+// Identifier access macros
+//
+#define CYG_CAN_MSG_GET_ID(_msg_) ((_msg_).id)
+#define CYG_CAN_MSG_SET_ID(_msg_, _id_) ((_msg_).id = (_id_))
+#define CYG_CAN_MSG_SET_STD_ID(_msg_, _id_) \
+CYG_MACRO_START \
+ CYG_CAN_MSG_SET_ID(_msg_, _id_); \
+ CYG_CAN_MSG_SET_STD(_msg_); \
+CYG_MACRO_END
+
+#define CYG_CAN_MSG_SET_EXT_ID(_msg_, _id_) \
+CYG_MACRO_START \
+ CYG_CAN_MSG_SET_ID(_msg_, _id_); \
+ CYG_CAN_MSG_SET_EXT(_msg_); \
+CYG_MACRO_END
+
+
+//---------------------------------------------------------------------------
+// DLC (data length code) access macros
+//
+#define CYG_CAN_MSG_GET_DATA_LEN(_msg_) ((_msg_).dlc)
+#define CYG_CAN_MSG_SET_DATA_LEN(_msg_, _len_) ((_msg_).dlc = (_len_))
+
+
+//---------------------------------------------------------------------------
+// CAN message data access
+// This macro returns a pointer to a cyg_can_msg_data union
+//
+#define CYG_CAN_MSG_DATA_PTR(_msg_) (&(_msg_).data)
+#define CYG_CAN_MSG_GET_DATA(_msg_, _pos_) ((_msg_).data.bytes[_pos_])
+#define CYG_CAN_MSG_SET_DATA(_msg_, _pos_, _val_) ((_msg_).data.bytes[_pos_] = (_val_))
+
+
+//---------------------------------------------------------------------------
+// Access multiple parameters
+//
+#define CYG_CAN_MSG_SET_PARAM(_msg_, _id_, _ext_, _dlc_, _rtr_) \
+CYG_MACRO_START \
+ CYG_CAN_MSG_SET_ID(_msg_, _id_); \
+ CYG_CAN_MSG_SET_ID_TYPE(_msg_, _ext_); \
+ CYG_CAN_MSG_SET_DATA_LEN(_msg_, _dlc_); \
+ CYG_CAN_MSG_SET_FRAME_TYPE(_msg_, _rtr_); \
+CYG_MACRO_END
+
+#define CYG_CAN_MSG_INIT(_clabel_, _id_, _ext_, _dlc_, _rtr_) \
+cyg_can_message _clabel_ = \
+{ \
+ id : _id_, \
+ ext : _ext_, \
+ rtr : _rtr_, \
+ dlc : _dlc_, \
+}
+
-#define CYG_CAN_INFO_INIT(_baud) \
- { _baud}
#ifdef __cplusplus
}
//
// there is enougth space left so we can store additional data
//
- cyg_can_message *ptxbuf = (cyg_can_message *)cbuf->pdata;
- cyg_can_message *pbuf_message = &ptxbuf[cbuf->put];
+ CYG_CAN_MSG_T *ptxbuf = (CYG_CAN_MSG_T *)cbuf->pdata;
+ CYG_CAN_MSG_T *pbuf_message = &ptxbuf[cbuf->put];
cyg_can_message *pmessage = (cyg_can_message *)_buf;
- *pbuf_message = *pmessage; // copy message
-
+ CYG_CAN_WRITE_MSG(pbuf_message, pmessage); // copy message
+
cbuf->put = (cbuf->put + 1) % cbuf->len;
cbuf->data_cnt++;
size -= sizeof(cyg_can_message);
//
if (cbuf->data_cnt > 0)
{
- cyg_can_event *prxbuf = (cyg_can_event *)cbuf->pdata;
- cyg_can_event *pbuf_event = &prxbuf[cbuf->get];
- cyg_can_event *pevent = (cyg_can_event *)_buf;
-
- *pevent = *pbuf_event; // copy event
+ CYG_CAN_EVENT_T *prxbuf = (CYG_CAN_EVENT_T *)cbuf->pdata;
+ CYG_CAN_EVENT_T *pbuf_event = &prxbuf[cbuf->get];
+ cyg_can_event *pevent = (cyg_can_event *)_buf;
+
+ CYG_CAN_READ_EVENT(pevent, pbuf_event); // copy event
cbuf->get = (cbuf->get + 1) % cbuf->len;
cbuf->data_cnt--;
cyg_can_info_t *pcan_info = (cyg_can_info_t *)xbuf;
can_cbuf_t *out_cbuf = &chan->out_cbuf;
can_cbuf_t *in_cbuf = &chan->in_cbuf;
+ can_lowlevel_funs *funs = chan->funs;
switch (key)
{
+ //
+ // query about CAN configuration like baud rate
+ //
case CYG_IO_GET_CONFIG_CAN_INFO :
if (*len < sizeof(cyg_can_info_t))
{
#endif // CYGOPT_IO_CAN_SUPPORT_TIMEOUTS
#ifdef CYGOPT_IO_CAN_SUPPORT_NONBLOCKING
+ //
+ // check if blocking calls are enabled
+ //
case CYG_IO_GET_CONFIG_READ_BLOCKING:
{
if (*len < sizeof(cyg_uint32))
}
break;
+ //
+ // check if nonblocking calls are enabled
+ //
case CYG_IO_GET_CONFIG_WRITE_BLOCKING:
{
if (*len < sizeof(cyg_uint32))
break;
#endif // CYGOPT_IO_CAN_SUPPORT_NONBLOCKING
+ //
+ // return hardware description interface
+ //
+ case CYG_IO_GET_CONFIG_CAN_HDI :
+ {
+ cyg_can_hdi *hdi = (cyg_can_hdi *)xbuf;
+ if (*len != sizeof(cyg_can_hdi))
+ {
+ return -EINVAL;
+ }
+ hdi = hdi; // avoid compiler warnings
+ *len = sizeof(cyg_can_hdi);
+ //
+ // pass down to low level to gather more information about
+ // CAN hardware
+ //
+ res = (funs->get_config)(chan, key, xbuf, len);
+ }
+ break;
+
default:
- res = -EINVAL;
+ res = (funs->get_config)(chan, key, xbuf, len);
} // switch (key)
return res;
switch (key)
{
#ifdef CYGOPT_IO_CAN_SUPPORT_NONBLOCKING
+ //
+ // Set calls to read function to blocking / nonblocking mode
+ //
case CYG_IO_SET_CONFIG_READ_BLOCKING:
{
if (*len < sizeof(cyg_uint32) || 0 == in_cbuf->len)
in_cbuf->blocking = (1 == *(cyg_uint32*)xbuf) ? true : false;
}
break;
-
+
+ //
+ // set calls to write functions to blocking / nonblocking mode
+ //
case CYG_IO_SET_CONFIG_WRITE_BLOCKING:
{
if (*len < sizeof(cyg_uint32) || 0 == out_cbuf->len)
}
break; // case CYG_IO_GET_CONFIG_CAN_TIMEOUT_INFO
#endif // CYGOPT_IO_CAN_SUPPORT_TIMEOUTS
+
+ case CYG_IO_SET_CONFIG_CAN_INPUT_FLUSH:
+ {
+ //
+ // Flush any buffered input
+ //
+ if (in_cbuf->len == 0)
+ {
+ break; // Nothing to do if not buffered
+ }
+ cyg_drv_mutex_lock(&in_cbuf->lock); // Stop any further input processing
+ cyg_drv_dsr_lock();
+ if (in_cbuf->waiting)
+ {
+ in_cbuf->abort = true;
+ cyg_drv_cond_broadcast(&in_cbuf->wait);
+ in_cbuf->waiting = false;
+ }
+ in_cbuf->get = in_cbuf->put = in_cbuf->data_cnt = 0; // Flush buffered input
+
+ //
+ // Pass to the hardware driver in case it wants to flush FIFOs etc.
+ //
+ (funs->set_config)(chan,
+ CYG_IO_SET_CONFIG_CAN_INPUT_FLUSH,
+ NULL, NULL);
+ cyg_drv_dsr_unlock();
+ cyg_drv_mutex_unlock(&in_cbuf->lock);
+ } // CYG_IO_SET_CONFIG_CAN_INPUT_FLUSH:
+
+ //
+ // flush any buffered output
+ //
+ case CYG_IO_SET_CONFIG_CAN_OUTPUT_FLUSH:
+ {
+ // Throw away any pending output
+ if (out_cbuf->len == 0)
+ {
+ break; // Nothing to do if not buffered
+ }
+ cyg_drv_mutex_lock(&out_cbuf->lock); // Stop any further output processing
+ cyg_drv_dsr_lock();
+ if (out_cbuf->data_cnt > 0)
+ {
+ out_cbuf->get = out_cbuf->put = out_cbuf->data_cnt = 0; // Empties queue!
+ (funs->stop_xmit)(chan); // Done with transmit
+ }
+
+ //
+ // Pass to the hardware driver in case it wants to flush FIFOs etc.
+ //
+ (funs->set_config)(chan,
+ CYG_IO_SET_CONFIG_CAN_OUTPUT_FLUSH,
+ NULL, NULL);
+ if (out_cbuf->waiting)
+ {
+ out_cbuf->abort = true;
+ cyg_drv_cond_broadcast(&out_cbuf->wait);
+ out_cbuf->waiting = false;
+ }// if (out_cbuf->waiting)
+ cyg_drv_dsr_unlock();
+ cyg_drv_mutex_unlock(&out_cbuf->lock);
+ }
+ break; // CYG_IO_GET_CONFIG_CAN_OUTPUT_FLUSH:
+
+ //
+ // wait until all messages in outbut buffer are sent
+ //
+ case CYG_IO_GET_CONFIG_SERIAL_OUTPUT_DRAIN:
+ {
+ // Wait for any pending output to complete
+ if (out_cbuf->len == 0)
+ {
+ break; // Nothing to do if not buffered
+ }
+ cyg_drv_mutex_lock(&out_cbuf->lock); // Stop any further output processing
+ cyg_drv_dsr_lock();
+ while (out_cbuf->pending || (out_cbuf->data_cnt > 0))
+ {
+ out_cbuf->waiting = true;
+ if(!cyg_drv_cond_wait(&out_cbuf->wait))
+ {
+ res = -EINTR;
+ }
+ }
+ cyg_drv_dsr_unlock();
+ cyg_drv_mutex_unlock(&out_cbuf->lock);
+ }
+ break;// CYG_IO_GET_CONFIG_SERIAL_OUTPUT_DRAIN:
+
+ //
+ // Abort any outstanding I/O, including blocked reads
+ // Caution - assumed to be called from 'timeout' (i.e. DSR) code
+ //
+ case CYG_IO_SET_CONFIG_CAN_ABORT :
+ {
+ in_cbuf->abort = true;
+ cyg_drv_cond_broadcast(&in_cbuf->wait);
+
+ out_cbuf->abort = true;
+ cyg_drv_cond_broadcast(&out_cbuf->wait);
+ }
+ break;
+
+#ifdef CYGOPT_IO_CAN_SUPPORT_CALLBACK
+ //
+ // Set callback configuration
+ // To disable callback set flag_mask = 0
+ //
+ case CYG_IO_SET_CONFIG_CAN_CALLBACK:
+ {
+ if (*len != sizeof(cyg_can_callback_cfg))
+ {
+ return -EINVAL;
+ }
+
+ // Copy data under DSR locking
+ cyg_drv_dsr_lock();
+ chan->callback_cfg = *((cyg_can_callback_cfg*) xbuf);
+ cyg_drv_dsr_unlock();
+ }
+ break;
+#endif //CYGOPT_IO_CAN_SUPPORT_CALLBACK
+
default:
//
// pass down to lower layers
//===========================================================================
static void can_rcv_event(can_channel *chan, void *pdata)
{
- can_cbuf_t *cbuf = &chan->in_cbuf;
- cyg_can_event *prxbuf = (cyg_can_event *)cbuf->pdata;
+ can_cbuf_t *cbuf = &chan->in_cbuf;
+ CYG_CAN_EVENT_T *prxbuf = (CYG_CAN_EVENT_T *)cbuf->pdata;
+#ifdef CYGOPT_IO_CAN_SUPPORT_CALLBACK
+ cyg_uint16 flags;
+#endif
//
// cbuf is a ring buffer - if the buffer is full, then we overwrite the
// oldest message in buffer so the user will always get the actual and
// last state of the external hardware that is connected to the
- // CAN bus.
+ // CAN bus. We need to call cyg_drv_dsr_lock() here because this function
+ // may be called from different message box interrupts and so we have to
+ // protect data access here
//
+ cyg_drv_dsr_lock();
+ prxbuf[cbuf->put].flags = 0; // clear flags because it is a new event
if (chan->funs->getevent(chan, &prxbuf[cbuf->put], pdata))
{
if (cbuf->data_cnt < cbuf->len)
prxbuf[cbuf->put].flags |= CYGNUM_CAN_EVENT_OVERRUN_RX;
cbuf->get = (cbuf->get + 1) % cbuf->len;
}
-
+
+#ifdef CYGOPT_IO_CAN_SUPPORT_CALLBACK
+ flags = prxbuf[cbuf->put].flags;
+#endif
+
cbuf->put = (cbuf->put + 1) % cbuf->len;
if (cbuf->waiting)
cbuf->waiting = false;
cyg_drv_cond_broadcast(&cbuf->wait);
}
+#ifdef CYGOPT_IO_CAN_SUPPORT_CALLBACK
+ // Call application callback function, if any of the flag events
+ // are unmasked.
+ if((flags & chan->callback_cfg.flag_mask) &&
+ (chan->callback_cfg.callback_func))
+ {
+ chan->callback_cfg.callback_func(flags,
+ chan->callback_cfg.data);
+ }
+#endif
}
+
+ cyg_drv_dsr_unlock();
}
{
can_cbuf_t *cbuf = &chan->out_cbuf;
can_lowlevel_funs *funs = chan->funs;
- cyg_can_message *ptxbuf = (cyg_can_message *)cbuf->pdata;
- cyg_can_message *pbuf_txmsg;
+ CYG_CAN_MSG_T *ptxbuf = (CYG_CAN_MSG_T *)cbuf->pdata;
+ CYG_CAN_MSG_T *pbuf_txmsg;
//
// transmit messages as long as there are messages in the buffer
+2007-08-13 Alexey Shusharin <mrfinch@mail.ru>
+
+ * include/config_keys.h: Added key set setting CAN callback
+ configuration.
+
+2006-09-21 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * include/config_keys.h: Merge from eCosCentric repository.
+ ChangeLogs incorporated in correct location below.
+
+2006-02-15 Uwe Kindler <uwe_kindler@web.de>
+
+ * include/config_keys.h Replaced CAN configuration keys
+ CYG_IO_SET_CONFIG_CAN_REMOTE_BUF,
+ CYG_IO_SET_CONFIG_CAN_FILTER_ALL and
+ CYG_IO_SET_CONFIG_CAN_FILTER_MSG with new single config key
+ CYG_IO_SET_CONFIG_CAN_MSGBUF
+
+2005-12-02 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/iosys.c:
+ * include/devtab.h: Add comments that bread/bwrite takes there
+ parameters in blocks, not bytes.
+
+2005-09-11 Uwe Kindler <uwe_kindler@web.de>
+
+ * include/config_keys.h Configuration keys for CAN driver added.
+
+2005-01-19 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * include/config_keys.h: Add device close key.
+
2004-12-23 Peter Korsgaard <jacmet@sunsite.dk>
* doc/io.sgml: Match CYG_TTY_IN_FLAGS_ECHO and
* src/iosys.c (cyg_io_lookup): Use union to avoid aliasing problems
with compiler.
-2004-01-19 Nick Garnett <nickg@calivar.com>
+2004-04-15 Nick Garnett <nickg@ecoscentric.com>
+
+ * include/config_keys.h: Added CYG_IO_SET_CONFIG_DISK_MOUNT and
+ CYG_IO_SET_CONFIG_DISK_UMOUNT keys.
+
+2004-01-19 Nick Garnett <nickg@ecoscentric.com>
* include/config_keys.h (CYG_IO_GET_CONFIG_DISK_INFO): Added DISK
IO config key base definition.
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2004, 2006 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2004 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
#define CYG_IO_GET_CONFIG_DISK_INFO 0x700
-// ======== 0x800 CAN ========================================================
-// Get/Set configuration 'key' values for DISK I/O
+#define CYG_IO_SET_CONFIG_DISK_MOUNT 0x781
+#define CYG_IO_SET_CONFIG_DISK_UMOUNT 0x782
+// ======== 0x800 CAN ========================================================
+// Get/Set configuration 'key' values for CAN I/O
#define CYG_IO_GET_CONFIG_CAN_INFO 0x0801
#define CYG_IO_GET_CONFIG_CAN_BUFFER_INFO 0x0802
-#define CYG_IO_GET_CONFIG_CAN_TIMEOUT 0x0803
+#define CYG_IO_GET_CONFIG_CAN_MSGBUF_INFO 0x0803
+#define CYG_IO_GET_CONFIG_CAN_TIMEOUT 0x0804
+#define CYG_IO_GET_CONFIG_CAN_HDI 0x0805
+#define CYG_IO_GET_CONFIG_CAN_STATE 0x0806
#define CYG_IO_SET_CONFIG_CAN_INFO 0x0881
-#define CYG_IO_SET_CONFIG_CAN_TIMEOUT 0x0883
-#define CYG_IO_SET_CONFIG_CAN_RTR_BUF 0x0884
+#define CYG_IO_SET_CONFIG_CAN_OUTPUT_DRAIN 0x0882
+#define CYG_IO_SET_CONFIG_CAN_OUTPUT_FLUSH 0x0883
+#define CYG_IO_SET_CONFIG_CAN_INPUT_FLUSH 0x0884
+#define CYG_IO_SET_CONFIG_CAN_TIMEOUT 0x0885
+#define CYG_IO_SET_CONFIG_CAN_MSGBUF 0x0886
+#define CYG_IO_SET_CONFIG_CAN_MODE 0x0887
+#define CYG_IO_SET_CONFIG_CAN_ABORT 0x0888
+#define CYG_IO_SET_CONFIG_CAN_CALLBACK 0x0889
// ======== 0x1000 Generic ===================================================
// Get/Set configuration 'key' values that can apply to more than one
#define CYG_IO_SET_CONFIG_READ_BLOCKING 0x1081
#define CYG_IO_SET_CONFIG_WRITE_BLOCKING 0x1082
+// Close the underlying device - primarily useful for io/fileio's devfs,
+// but probably more widely applicable. Note that this is not like UNIX
+// close in that there is no reference counting. If that is needed it must
+// be done at a higher level.
+#define CYG_IO_SET_CONFIG_CLOSE 0x1100
#endif /* CYGONCE_CONFIG_KEYS_H */
/* EOF config_keys.h */
void *buf,
cyg_uint32 *len);
Cyg_ErrNo (*bwrite)(cyg_io_handle_t handle,
- const void *buf,
- cyg_uint32 *len,
- cyg_uint32 pos);
+ const void *buf,
+ cyg_uint32 *len, // in blocks
+ cyg_uint32 pos); // in blocks
Cyg_ErrNo (*bread)(cyg_io_handle_t handle,
- void *buf,
- cyg_uint32 *len,
- cyg_uint32 pos);
+ void *buf,
+ cyg_uint32 *len, // in blocks
+ cyg_uint32 pos); // in blocks
cyg_bool (*select)(cyg_io_handle_t handle,
cyg_uint32 which,
CYG_ADDRWORD info);
_set_config, \
};
+// Note: _bwrite and _bread pass len and pos in terms of blocks, not
+// bytes.
#define BLOCK_DEVIO_TABLE(_l,_bwrite,_bread,_select,_get_config,_set_config) \
cyg_devio_table_t _l = { \
cyg_devio_cwrite, \
return t->handlers->read(handle, buf, len);
}
+//
+// 'write' blocks to a device. The len and the position are in terms
+// of blocks, not bytes like the cyg_io_write.
+//
Cyg_ErrNo
cyg_io_bwrite(cyg_io_handle_t handle, const void *buf, cyg_uint32 *len, cyg_uint32 pos)
{
}
//
-// 'read' data from a device.
+// 'read' blocks from a device. The len and the position are in terms of
+// blocks, not bytes like the cyg_io_read.
//
-
Cyg_ErrNo
cyg_io_bread(cyg_io_handle_t handle, void *buf, cyg_uint32 *len, cyg_uint32 pos)
{
+2006-09-21 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * include/disk.h (DISK_CHANNEL): No need for extra _part_dev
+ slot intended for entire disk's own devtab.
+
+ * src/disk.c (disk_lookup): Just access pdevs_dev directly
+ with no adjusted offset.
+ (disk_init): No longer set entry 0 from device devtab.
+ It's unnecessary.
+
+2006-09-20 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * include/disk.h: Merge eCosCentric CVS with public eCos CVS.
+ This merges (and therefore changes) the API. ChangeLog
+ entries have been incorporated in the correct places below.
+ * include/diskio.h: Also merged.
+ * cdl/io_disk.cdl: Also merged.
+ * src/disk.c: Also merged.
+
+2006-08-18 Andy Jackson <andy@xylanta.com>
+
+ * cdl/io_disk.cdl: Made debugging CDL controlled.
+ * src/disk.c: Added support to allow non-CHS disk devices to
+ use LBA information in MBR.
+
+2006-02-03 Nick Garnett <nickg@ecoscentric.com>
+
+ * src/disk.c (read_partition): Switched to favour LBA partition
+ information in partition tables. This also means we don't now rely
+ on the driver reporting a correct CHS size for the disk.
+ (disk_bread, disk_bwrite): API changed to take length in sectors
+ rather than bytes. Also call hardware driver to transfer in
+ (up to) max_transfer sized chunks, rather than a sector at a
+ time. Call in to driver now made with DSR lock claimed, to avoid a
+ race condition between the DSR and the calling thread.
+ (disk_get_config): Added phys_block_size to channel info.
+
+ * include/diskio.h (struct cyg_disk_identify_t): Added
+ phys_block_size and max_transfer fields. These must be filled in
+ by the driver.
+
+2005-12-12 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * include/disk.h (DISK_CHANNEL_INIT): New macro. Allows a
+ DISK_CHANNEL to be defined dynamically.
+
+2005-12-02 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/disk.c: Add comments that bread/bwrite take the position and
+ len in terms of blocks, not bytes.
+
+2005-10-11 Nick Garnett <nickg@ecoscentric.com>
+
+ * src/disk.c (disk_bread, disk_bwrite): Made calls to
+ cyg_thread_yield() dependent on presence ok kernel.
+
+2005-06-01 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * src/disk.c (disk_bwrite): Uncomment the cyg_thread_yield() at
+ the end to prevent thread starvation between threads at the same
+ priority.
+ (disk_bread): Ditto.
+
+2004-07-21 Nick Garnett <nickg@ecoscentric.com>
+
+ * src/disk.c (read_partition): Changed to account for very large
+ disks which report bogus CHS geometry. We can only use the LBA
+ partition parameters in such disks.
+ (disk_set_config): Added some extra debug output.
+
2004-07-01 Savin Zlobec <savin@elatec.si>
* src/disk.c:
radher than malloc. Extended DISK_CHANNEL macro to
support defining maximum number of partitions.
-2004-01-15 Nick Garnett <nickg@calivar.com>
+2004-04-15 Nick Garnett <nickg@ecoscentric.com>
+
+ * src/disk.c:
+ Various changes to support disconnect/reconnect of changeable
+ media.
+
+ * include/diskio.h: Added mount counter to disk_info structure.
+
+ * include/disk.h: Changed disk_disconnected() function to take a
+ pointer to a struct disk_channel rather than a struct
+ cyg_devtab_entry. Added mount count to disk_channel structure.
+ Moved include of diskio.h to end to fix declaration problems.
+
+2004-02-04 Nick Garnett <nickg@ecoscentric.com>
+
+ * src/disk.c: Fixed bug in write routine where controller result
+ field was not being initialized. Added signals on controller queue
+ condition variable after setting controller busy flag to false.
+
+ * include/disk.h: Made controller result and busy fields
+ volatile. Just in case.
+
+2004-01-23 Nick Garnett <nickg@ecoscentric.com>
+
+ * include/disk.h:
+ * src/disk.c:
+ Many changes. Added additional disk_controller data structure to
+ better reflect hardware structure. Added support for serialization
+ of multithreaded accesses to a single controller. Added support
+ for asynchronous, interrupt driven, IO operations. Various
+ tidies.
+
+2004-01-15 Nick Garnett <nickg@ecoscentric.com>
* src/disk.c:
* include/disk.h: Removed block_pos arguments from
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 2003 Savin Zlobec
+// Copyright (C) 2003, 2004, 2005, 2006 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-## Copyright (C) 2003 Savin Zlobec
+## Copyright (C) 2003 eCosCentric Limited.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
compile -library=libextras.a disk.c
define_proc {
- puts $::cdl_header "/***** proc output start *****/"
- puts $::cdl_header "#include <pkgconf/system.h>"
- puts $::cdl_header "#ifdef CYGDAT_IO_DISK_DEVICE_HEADER"
- puts $::cdl_header "# include CYGDAT_IO_DISK_DEVICE_HEADER"
- puts $::cdl_header "#endif "
- puts $::cdl_header "/****** proc output end ******/"
+ puts $::cdl_header "/***** proc output start *****/"
+
puts $::cdl_header "#include <pkgconf/system.h>"
+ puts $::cdl_header "#ifdef CYGDAT_IO_DISK_DEVICE_HEADER"
+ puts $::cdl_header "# include CYGDAT_IO_DISK_DEVICE_HEADER"
+ puts $::cdl_header "#endif "
+ puts $::cdl_header "/****** proc output end ******/"
}
cdl_component CYGPKG_IO_DISK_DEVICES {
default_value 1
description "
This option enables the hardware disk drivers
- for the current platform."
+ for the current platform."
+ }
+
+ cdl_component CYGDBG_IO_DISK_DEBUG {
+ display "Enable debugging output"
+ flavor bool
+ default_value 0
+ description "
+ This option enables debugging information from
+ the disk driver package."
}
cdl_component CYGPKG_IO_DISK_OPTIONS {
display "Disk device driver build options"
flavor none
description "
- Package specific build options including control over
- compiler flags used only in building this package,
- and details of which tests are built."
+ Package specific build options including control over
+ compiler flags used only in building this package,
+ and details of which tests are built."
cdl_option CYGPKG_IO_DISK_CFLAGS_ADD {
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-// Copyright (C) 2003 Savin Zlobec
+// Copyright (C) 2003, 2004, 2005 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
#include <pkgconf/io_disk.h>
#include <cyg/infra/cyg_type.h>
+#include <cyg/io/devtab.h>
#include <cyg/io/io.h>
-#include <cyg/io/diskio.h>
#include <cyg/hal/drv_api.h>
+#include <string.h> /* memset() */
+
+// ---------------------------------------------------------------------------
+
+typedef struct cyg_disk_partition_t cyg_disk_partition_t;
+typedef struct cyg_disk_info_t cyg_disk_info_t;
+typedef struct cyg_disk_identify_t cyg_disk_identify_t;
-typedef struct disk_channel disk_channel;
-typedef struct disk_funs disk_funs;
+typedef struct disk_channel disk_channel;
+typedef struct disk_controller disk_controller;
+typedef struct disk_funs disk_funs;
+
+// ---------------------------------------------------------------------------
// Pointers into upper-level driver
typedef struct {
cyg_disk_identify_t *ident);
// Disk device has been disconnected
- Cyg_ErrNo (*disk_disconnected)(struct cyg_devtab_entry *tab);
+ Cyg_ErrNo (*disk_disconnected)(struct disk_channel *chan);
// Lookup disk device
Cyg_ErrNo (*disk_lookup)(struct cyg_devtab_entry **tab,
struct cyg_devtab_entry *sub_tab,
const char *name);
+
+ // Asynchronous block transfer done
+ void (*disk_transfer_done)(struct disk_channel *chan, Cyg_ErrNo res);
+
} disk_callbacks_t;
-#define DISK_CALLBACKS(_l, \
- _init, \
- _connected, \
- _disconnected, \
- _lookup) \
-disk_callbacks_t _l = { \
- _init, \
- _connected, \
- _disconnected, \
- _lookup \
+#define DISK_CALLBACKS(_l, \
+ _init, \
+ _connected, \
+ _disconnected, \
+ _lookup, \
+ _transfer_done) \
+disk_callbacks_t _l = { \
+ _init, \
+ _connected, \
+ _disconnected, \
+ _lookup, \
+ _transfer_done \
};
extern disk_callbacks_t cyg_io_disk_callbacks;
+// ---------------------------------------------------------------------------
+// Private data which describes a disk controller
+
+struct disk_controller {
+ cyg_drv_mutex_t lock; // Per-controller lock
+ cyg_drv_cond_t queue; // Access wait list
+ cyg_drv_cond_t async; // Async transfer waits here
+ void *priv; // Private data
+ volatile Cyg_ErrNo result; // Last operation result
+ cyg_bool init; // Initialized?
+ volatile cyg_bool busy; // Busy?
+};
+
+#define DISK_CONTROLLER(_l, _priv) \
+static disk_controller _l = { \
+ priv: &_priv, \
+ init: false, \
+ busy: false \
+};
+
+// ---------------------------------------------------------------------------
// Private data which describes this channel
+
struct disk_channel {
disk_funs *funs;
disk_callbacks_t *callbacks;
void *dev_priv; // device private data
+ disk_controller *controller; // pointer to controller
cyg_disk_info_t *info; // disk info
cyg_disk_partition_t *partition; // partition data
struct cyg_devtab_entry *pdevs_dev; // partition devs devtab ents
cyg_bool mbr_support; // true if disk has MBR
cyg_bool valid; // true if device valid
cyg_bool init; // true if initialized
+ cyg_ucount16 mounts; // count of number of mounts
};
// Initialization macro for disk channel
#define DISK_CHANNEL(_l, \
_funs, \
_dev_priv, \
+ _controller, \
_mbr_supp, \
_max_part_num) \
static struct cyg_devtab_entry _l##_part_dev[_max_part_num]; \
&(_funs), \
&cyg_io_disk_callbacks, \
&(_dev_priv), \
+ &(_controller), \
&(_l##_disk_info), \
NULL, \
_l##_part_dev, \
_l##_part_chan, \
_mbr_supp, \
false, \
- false \
+ false, \
+ 0 \
};
+// Initialization macro for disk channel allocated elsewhere.
+#define DISK_CHANNEL_INIT(_dc, \
+ _funs, \
+ _dev_priv, \
+ _controller, \
+ _disk_info, \
+ _part_dev, \
+ _part_chan, \
+ _part_tab, \
+ _mbr_supp, \
+ _max_part_num) \
+ CYG_MACRO_START \
+ memset((_disk_info), 0, sizeof(cyg_disk_info_t)); \
+ (_dc).funs = &(_funs); \
+ (_dc).callbacks = &cyg_io_disk_callbacks; \
+ (_dc).dev_priv = (_dev_priv); \
+ (_dc).controller = &(_controller); \
+ (_dc).info = &(_disk_info); \
+ (_dc).info->partitions = (_part_tab); \
+ (_dc).pdevs_dev = (_part_dev); \
+ (_dc).pdevs_chan = (_part_chan); \
+ (_dc).partition = NULL; \
+ (_dc).mbr_support = (_mbr_supp); \
+ (_dc).valid = false; \
+ (_dc).init = false; \
+ (_dc).mounts = 0; \
+ (_dc).info->partitions_num = (_max_part_num); \
+ CYG_MACRO_END
+
+// ---------------------------------------------------------------------------
// Low level interface functions
+
struct disk_funs {
// Read block data into buf
};
#define DISK_FUNS(_l,_read,_write,_get_config,_set_config) \
-disk_funs _l = { \
+static disk_funs _l = { \
_read, \
_write, \
_get_config, \
extern cyg_devio_table_t cyg_io_disk_devio;
+// ---------------------------------------------------------------------------
+
+#include <cyg/io/diskio.h>
+
+// ---------------------------------------------------------------------------
#endif // CYGONCE_DISK_H
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 2003 Savin Zlobec
+// Copyright (C) 2003, 2004, 2006 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
#include <cyg/infra/cyg_type.h>
#include <cyg/io/config_keys.h>
+#include <cyg/io/devtab.h>
+
#ifdef __cplusplus
extern "C" {
#endif
-
-typedef struct {
+
+struct cyg_disk_identify_t
+{
char serial[20+1]; // serial number
char firmware_rev[8+1]; // firmware revision
char model_num[40+1]; // model number
cyg_uint32 heads_num; // number of heads (CHS)
cyg_uint32 sectors_num; // number of sectors per track (CHS)
cyg_uint32 lba_sectors_num; // total number of sectors in LBA mode
-} cyg_disk_identify_t;
+ cyg_uint32 phys_block_size; // physical block size in sectors
+ cyg_uint32 max_transfer; // Maximum transfer size in bytes
+};
-typedef struct {
+struct cyg_disk_partition_t
+{
cyg_uint8 type; // partition type
cyg_uint8 state; // state 0x00 - inactive, 0x80 - active
cyg_uint32 start; // first sector number
cyg_uint32 end; // last sector number
cyg_uint32 size; // size in sectors
-} cyg_disk_partition_t;
+};
-typedef struct {
- cyg_disk_partition_t *partitions; // partition table
- int partitions_num;// partition table size
- cyg_disk_identify_t ident; // identify data
- cyg_uint32 block_size; // block size
- cyg_uint32 blocks_num; // number of blocks on disk
- cyg_bool connected; // true if device connected
-} cyg_disk_info_t;
+struct cyg_disk_info_t
+{
+ cyg_disk_partition_t *partitions; // partition table
+ int partitions_num;// partition table size
+ cyg_disk_identify_t ident; // identify data
+ cyg_uint32 block_size; // logical block size
+ cyg_uint32 blocks_num; // number of blocks on disk
+ cyg_uint32 phys_block_size; // physical block size
+ cyg_bool connected; // true if device connected
+ cyg_ucount16 mounts; // total number of mounts for all partitions
+};
#ifdef __cplusplus
}
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 2003 Savin Zlobec
+// Copyright (C) 2003. 2004, 2005, 2006 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// ---------------------------------------------------------------------------
-//#define DEBUG 1
+#ifdef CYGDBG_IO_DISK_DEBUG
+#define DEBUG 1
+#endif
#ifdef DEBUG
# define D(_args_) diag_printf _args_
static Cyg_ErrNo disk_connected(struct cyg_devtab_entry *tab,
cyg_disk_identify_t *ident);
-static Cyg_ErrNo disk_disconnected(struct cyg_devtab_entry *tab);
+static Cyg_ErrNo disk_disconnected(struct disk_channel *chan);
static Cyg_ErrNo disk_lookup(struct cyg_devtab_entry **tab,
struct cyg_devtab_entry *sub_tab,
const char *name);
+static void disk_transfer_done(struct disk_channel *chan, Cyg_ErrNo res);
+
DISK_CALLBACKS(cyg_io_disk_callbacks,
disk_init,
disk_connected,
disk_disconnected,
- disk_lookup
+ disk_lookup,
+ disk_transfer_done
);
// ---------------------------------------------------------------------------
-
//
// Read partition from data
//
+
static void
read_partition(cyg_uint8 *data,
cyg_disk_info_t *info,
cyg_disk_partition_t *part)
{
+ cyg_disk_identify_t *ident = &info->ident;
cyg_uint16 c, h, s;
+ cyg_uint32 start, end, size;
+#ifdef DEBUG
+ diag_printf("Partition data:\n");
+ diag_dump_buf( data, 16 );
+ diag_printf("Disk geometry: %d/%d/%d\n",info->ident.cylinders_num,
+ info->ident.heads_num, info->ident.sectors_num );
+#endif
+
+ // Retrieve basic information
part->type = data[4];
part->state = data[0];
+ READ_DWORD(&data[12], part->size);
- READ_CHS(&data[1], c, h, s);
- CHS_TO_LBA(&info->ident, c, h, s, part->start);
+ READ_DWORD(&data[8], start);
+ READ_DWORD(&data[12], size);
- READ_CHS(&data[5], c, h, s);
- CHS_TO_LBA(&info->ident, c, h, s, part->end);
+ // Use the LBA start and size fields if they are valid. Otherwise
+ // fall back to CHS.
- READ_DWORD(&data[12], part->size);
+ if( start > 0 && size > 0 )
+ {
+ READ_DWORD(&data[8], start);
+ end = start + size - 1;
+
+#ifdef DEBUG
+ diag_printf("Using LBA partition parameters\n");
+ diag_printf(" LBA start %d\n",start);
+ diag_printf(" LBA size %d\n",size);
+ diag_printf(" LBA end %d\n",end);
+#endif
+
+ }
+ else
+ {
+ READ_CHS(&data[1], c, h, s);
+ CHS_TO_LBA(ident, c, h, s, start);
+#ifdef DEBUG
+ diag_printf("Using CHS partition parameters\n");
+ diag_printf(" CHS start %d/%d/%d => %d\n",c,h,s,start);
+#endif
+
+ READ_CHS(&data[5], c, h, s);
+ CHS_TO_LBA(ident, c, h, s, end);
+#ifdef DEBUG
+ diag_printf(" CHS end %d/%d/%d => %d\n",c,h,s,end);
+ diag_printf(" CHS size %d\n",size);
+#endif
+
+ }
+
+ part->size = size;
+ part->start = start;
+ part->end = end;
}
+// ---------------------------------------------------------------------------
//
// Read Master Boot Record (partitions)
//
+
static Cyg_ErrNo
read_mbr(disk_channel *chan)
{
cyg_disk_info_t *info = chan->info;
disk_funs *funs = chan->funs;
+ disk_controller *ctlr = chan->controller;
cyg_uint8 buf[512];
Cyg_ErrNo res = ENOERR;
int i;
-
+
+ D(("read MBR\n"));
+
for (i = 0; i < info->partitions_num; i++)
info->partitions[i].type = 0x00;
-
- res = (funs->read)(chan, (void *)buf, 512, 0);
+
+
+
+ cyg_drv_mutex_lock( &ctlr->lock );
+
+ while( ctlr->busy )
+ cyg_drv_cond_wait( &ctlr->queue );
+
+ ctlr->busy = true;
+
+ ctlr->result = -EWOULDBLOCK;
+
+ for( i = 0; i < sizeof(buf); i++ )
+ buf[i] = 0;
+
+ res = (funs->read)(chan, (void *)buf, 1, 0);
+
+ if( res == -EWOULDBLOCK )
+ {
+ // If the driver replys EWOULDBLOCK, then the transfer is
+ // being handled asynchronously and when it is finished it
+ // will call disk_transfer_done(). This will wake us up here
+ // to continue.
+
+ while( ctlr->result == -EWOULDBLOCK )
+ cyg_drv_cond_wait( &ctlr->async );
+
+ res = ctlr->result;
+ }
+
+ ctlr->busy = false;
+
+ cyg_drv_mutex_unlock( &ctlr->lock );
+
if (ENOERR != res)
return res;
+#ifdef DEBUG
+ diag_dump_buf_with_offset( buf, 512, buf );
+#endif
+
if (MBR_SIG_BYTE0 == buf[MBR_SIG_ADDR+0] && MBR_SIG_BYTE1 == buf[MBR_SIG_ADDR+1])
{
int npart;
return ENOERR;
}
+// ---------------------------------------------------------------------------
+
static cyg_bool
disk_init(struct cyg_devtab_entry *tab)
{
if (!chan->init)
{
+ disk_controller *controller = chan->controller;
+
+ if( !controller->init )
+ {
+ cyg_drv_mutex_init( &controller->lock );
+ cyg_drv_cond_init( &controller->queue, &controller->lock );
+ cyg_drv_cond_init( &controller->async, &controller->lock );
+
+ controller->init = true;
+ }
+
info->connected = false;
-
+
// clear partition data
for (i = 0; i < info->partitions_num; i++)
info->partitions[i].type = 0x00;
return true;
}
+// ---------------------------------------------------------------------------
+
static Cyg_ErrNo
disk_connected(struct cyg_devtab_entry *tab,
cyg_disk_identify_t *ident)
if (!chan->init)
return -EINVAL;
+
+ // If the device is already connected, nothing more to do
+ if( info->connected )
+ return ENOERR;
+
+ // If any of these assertions fire, it is probable that the
+ // hardware driver has not been updated to match the current disk
+ // API.
+ CYG_ASSERT( ident->lba_sectors_num > 0, "Bad LBA sector count" );
+ CYG_ASSERT( ident->phys_block_size > 0, "Bad physical block size");
+ CYG_ASSERT( ident->max_transfer > 0, "Bad max transfer size");
info->ident = *ident;
info->block_size = 512;
info->blocks_num = ident->lba_sectors_num;
+ info->phys_block_size = ident->phys_block_size;
D(("disk connected\n"));
- D((" serial = '%s'\n", ident->serial));
- D((" firmware rev = '%s'\n", ident->firmware_rev));
- D((" model num = '%s'\n", ident->model_num));
- D((" block_size = %d\n", info->block_size));
- D((" blocks_num = %d\n", info->blocks_num));
-
+ D((" serial = '%s'\n", ident->serial));
+ D((" firmware rev = '%s'\n", ident->firmware_rev));
+ D((" model num = '%s'\n", ident->model_num));
+ D((" block_size = %d\n", info->block_size));
+ D((" blocks_num = %u\n", info->blocks_num));
+ D((" phys_block_size = %d\n", info->phys_block_size));
+
if (chan->mbr_support)
{
// read disk master boot record
return res;
}
+// ---------------------------------------------------------------------------
+
static Cyg_ErrNo
-disk_disconnected(struct cyg_devtab_entry *tab)
+disk_disconnected(disk_channel *chan)
{
- disk_channel *chan = (disk_channel *) tab->priv;
cyg_disk_info_t *info = chan->info;
int i;
if (!chan->init)
return -EINVAL;
-
+
info->connected = false;
chan->valid = false;
return ENOERR;
}
+// ---------------------------------------------------------------------------
+
static Cyg_ErrNo
disk_lookup(struct cyg_devtab_entry **tab,
struct cyg_devtab_entry *sub_tab,
static Cyg_ErrNo
disk_bread(cyg_io_handle_t handle,
void *buf,
- cyg_uint32 *len,
- cyg_uint32 pos)
+ cyg_uint32 *len, // In blocks
+ cyg_uint32 pos) // In blocks
{
cyg_devtab_entry_t *t = (cyg_devtab_entry_t *) handle;
disk_channel *chan = (disk_channel *) t->priv;
+ disk_controller *ctlr = chan->controller;
disk_funs *funs = chan->funs;
cyg_disk_info_t *info = chan->info;
cyg_uint32 size = *len;
Cyg_ErrNo res = ENOERR;
cyg_uint32 last;
- if (!info->connected || !chan->valid)
- return -EINVAL;
-
- if (NULL != chan->partition)
- {
- pos += chan->partition->start;
- last = chan->partition->end;
- }
- else
- {
- last = info->blocks_num-1;
- }
-
- D(("disk read block=%d len=%d buf=%p\n", pos, *len, buf));
-
- while (size > 0)
+ cyg_drv_mutex_lock( &ctlr->lock );
+
+ while( ctlr->busy )
+ cyg_drv_cond_wait( &ctlr->queue );
+
+ if (info->connected && chan->valid)
{
- if (pos > last)
+ ctlr->busy = true;
+
+ if (NULL != chan->partition)
{
- res = -EIO;
- break;
+ pos += chan->partition->start;
+ last = chan->partition->end;
}
-
- res = (funs->read)(chan, (void*)bbuf, info->block_size, pos);
- if (ENOERR != res)
- break;
-
- if (!info->connected)
+ else
{
- res = -EINVAL;
- break;
+ last = info->blocks_num-1;
}
+
+ D(("disk read block=%d len=%d buf=%p\n", pos, *len, buf));
+
+ while( size > 0 )
+ {
+ cyg_uint32 tfr = size;
+
+ if (pos > last)
+ {
+ res = -EIO;
+ break;
+ }
+
+ if( tfr > info->ident.max_transfer )
+ tfr = info->ident.max_transfer;
+
+ ctlr->result = -EWOULDBLOCK;
+
+ cyg_drv_dsr_lock();
+
+ res = (funs->read)(chan, (void*)bbuf, tfr, pos);
+
+ if( res == -EWOULDBLOCK )
+ {
+ // If the driver replys EWOULDBLOCK, then the transfer is
+ // being handled asynchronously and when it is finished it
+ // will call disk_transfer_done(). This will wake us up here
+ // to continue.
+
+ while( ctlr->result == -EWOULDBLOCK )
+ cyg_drv_cond_wait( &ctlr->async );
+
+ res = ctlr->result;
+ }
+
+ cyg_drv_dsr_unlock();
- bbuf += info->block_size;
- pos++;
- size--;
+ if (ENOERR != res)
+ goto done;
+
+ if (!info->connected)
+ {
+ res = -EINVAL;
+ goto done;
+ }
+
+ bbuf += tfr * info->block_size;
+ pos += tfr;
+ size -= tfr;
+ }
+
+ ctlr->busy = false;
+ cyg_drv_cond_signal( &ctlr->queue );
}
+ else
+ res = -EINVAL;
+
+done:
+
+ cyg_drv_mutex_unlock( &ctlr->lock );
+#ifdef CYGPKG_KERNEL
+ cyg_thread_yield();
+#endif
+
*len -= size;
return res;
}
static Cyg_ErrNo
disk_bwrite(cyg_io_handle_t handle,
const void *buf,
- cyg_uint32 *len,
- cyg_uint32 pos)
+ cyg_uint32 *len, // In blocks
+ cyg_uint32 pos) // In blocks
{
cyg_devtab_entry_t *t = (cyg_devtab_entry_t *) handle;
disk_channel *chan = (disk_channel *) t->priv;
+ disk_controller *ctlr = chan->controller;
disk_funs *funs = chan->funs;
cyg_disk_info_t *info = chan->info;
cyg_uint32 size = *len;
Cyg_ErrNo res = ENOERR;
cyg_uint32 last;
- if (!info->connected || !chan->valid)
- return -EINVAL;
-
- if (NULL != chan->partition)
- {
- pos += chan->partition->start;
- last = chan->partition->end;
- }
- else
- {
- last = info->blocks_num-1;
- }
-
- D(("disk write block=%d len=%d buf=%p\n", pos, *len, buf));
-
- while (size > 0)
+ cyg_drv_mutex_lock( &ctlr->lock );
+
+ while( ctlr->busy )
+ cyg_drv_cond_wait( &ctlr->queue );
+
+ if (info->connected && chan->valid)
{
- if (pos > last)
+ ctlr->busy = true;
+
+ if (NULL != chan->partition)
{
- res = -EIO;
- break;
+ pos += chan->partition->start;
+ last = chan->partition->end;
+ }
+ else
+ {
+ last = info->blocks_num-1;
}
+
+ D(("disk write block=%d len=%d buf=%p\n", pos, *len, buf));
+
+ while( size > 0 )
+ {
+ cyg_uint32 tfr = size;
- res = (funs->write)(chan, (void*)bbuf, info->block_size, pos);
- if (ENOERR != res)
- break;
+ if (pos > last)
+ {
+ res = -EIO;
+ goto done;
+ }
+
+ if( tfr > info->ident.max_transfer )
+ tfr = info->ident.max_transfer;
+
+ ctlr->result = -EWOULDBLOCK;
+
+ cyg_drv_dsr_lock();
+
+ res = (funs->write)(chan, (void*)bbuf, tfr, pos);
+
+ if( res == -EWOULDBLOCK )
+ {
+ // If the driver replys EWOULDBLOCK, then the transfer is
+ // being handled asynchronously and when it is finished it
+ // will call disk_transfer_done(). This will wake us up here
+ // to continue.
+
+ while( ctlr->result == -EWOULDBLOCK )
+ cyg_drv_cond_wait( &ctlr->async );
+
+ res = ctlr->result;
+ }
+
+ cyg_drv_dsr_unlock();
+
+ if (ENOERR != res)
+ goto done;
- if (!info->connected)
- {
- res = -EINVAL;
- break;
+ if (!info->connected)
+ {
+ res = -EINVAL;
+ goto done;
+ }
+
+ bbuf += tfr * info->block_size;
+ pos += tfr;
+ size -= tfr;
+
}
- bbuf += info->block_size;
- pos++;
- size--;
+ ctlr->busy = false;
+ cyg_drv_cond_signal( &ctlr->queue );
}
+ else
+ res = -EINVAL;
+
+done:
+
+ cyg_drv_mutex_unlock( &ctlr->lock );
+#ifdef CYGPKG_KERNEL
+ cyg_thread_yield();
+#endif
+
*len -= size;
return res;
}
// ---------------------------------------------------------------------------
+static void disk_transfer_done(struct disk_channel *chan, Cyg_ErrNo res)
+{
+ disk_controller *ctlr = chan->controller;
+
+ ctlr->result = res;
+
+ cyg_drv_cond_signal( &ctlr->async );
+}
+
+// ---------------------------------------------------------------------------
+
static cyg_bool
disk_select(cyg_io_handle_t handle, cyg_uint32 which, CYG_ADDRWORD info)
{
{
cyg_devtab_entry_t *t = (cyg_devtab_entry_t *) handle;
disk_channel *chan = (disk_channel *) t->priv;
+ disk_controller *ctlr = chan->controller;
cyg_disk_info_t *info = chan->info;
cyg_disk_info_t *buf = (cyg_disk_info_t *) xbuf;
disk_funs *funs = chan->funs;
Cyg_ErrNo res = ENOERR;
- if (!info->connected || !chan->valid)
- return -EINVAL;
+ cyg_drv_mutex_lock( &ctlr->lock );
+
+ while( ctlr->busy )
+ cyg_drv_cond_wait( &ctlr->queue );
- D(("disk get config key=%d\n", key));
+ if (info->connected && chan->valid)
+ {
+ ctlr->busy = true;
- switch (key) {
- case CYG_IO_GET_CONFIG_DISK_INFO:
- if (*len < sizeof(cyg_disk_info_t)) {
- return -EINVAL;
+ D(("disk get config key=%d\n", key));
+
+ switch (key) {
+ case CYG_IO_GET_CONFIG_DISK_INFO:
+ if (*len < sizeof(cyg_disk_info_t)) {
+ res = -EINVAL;
+ break;
+ }
+ D(("chan->info->block_size %u\n", chan->info->block_size ));
+ D(("chan->info->blocks_num %u\n", chan->info->blocks_num ));
+ D(("chan->info->phys_block_size %u\n", chan->info->phys_block_size ));
+ *buf = *chan->info;
+ *len = sizeof(cyg_disk_info_t);
+ break;
+
+ default:
+ // pass down to lower layers
+ res = (funs->get_config)(chan, key, xbuf, len);
}
- *buf = *chan->info;
- *len = sizeof(cyg_disk_info_t);
- break;
-
- default:
- // pass down to lower layers
- res = (funs->get_config)(chan, key, xbuf, len);
+
+ ctlr->busy = false;
+ cyg_drv_cond_signal( &ctlr->queue );
}
-
+ else
+ res = -EINVAL;
+
+ cyg_drv_mutex_unlock( &ctlr->lock );
+
return res;
}
{
cyg_devtab_entry_t *t = (cyg_devtab_entry_t *) handle;
disk_channel *chan = (disk_channel *) t->priv;
+ disk_controller *ctlr = chan->controller;
cyg_disk_info_t *info = chan->info;
disk_funs *funs = chan->funs;
+ Cyg_ErrNo res = ENOERR;
+
+ cyg_drv_mutex_lock( &ctlr->lock );
- if (!info->connected || !chan->valid)
- return -EINVAL;
+ while( ctlr->busy )
+ cyg_drv_cond_wait( &ctlr->queue );
- D(("disk set config key=%d\n", key));
-
- // pass down to lower layers
- return (funs->set_config)(chan, key, xbuf, len);
+ if (info->connected && chan->valid)
+ {
+ ctlr->busy = true;
+
+ D(("disk set config key=%d\n", key));
+
+ switch ( key )
+ {
+ case CYG_IO_SET_CONFIG_DISK_MOUNT:
+ chan->mounts++;
+ info->mounts++;
+ D(("disk mount: chan %d disk %d\n",chan->mounts, info->mounts));
+ break;
+
+ case CYG_IO_SET_CONFIG_DISK_UMOUNT:
+ chan->mounts--;
+ info->mounts--;
+ D(("disk umount: chan %d disk %d\n",chan->mounts, info->mounts));
+ break;
+
+ default:
+ break;
+ }
+
+ // pass down to lower layers
+ res = (funs->set_config)(chan, key, xbuf, len);
+
+ ctlr->busy = false;
+ cyg_drv_cond_signal( &ctlr->queue );
+ }
+ else
+ res = -EINVAL;
+
+ cyg_drv_mutex_unlock( &ctlr->lock );
+
+ return res;
+
}
// ---------------------------------------------------------------------------
+2006-03-26 Uwe Kindler <uwe_kindler@web.de>
+
+ * src/lwip/eth_drv.c Add call to lwip_dhcp_init() for
+ start of DHCP client. Fixed ecosif_output() for
+ lwip 1.1.1 support.
+
+2006-01-18 Gary Thomas <gary@mlbassoc.com>
+
+ * src/net/eth_drv.c (eth_drv_send): Better check for overflow
+ of SG list - pointed out by Ferenc Deak
+
2005-07-29 Andrew Lunn <andrew.lunn@ascom.ch>
* src/net/eth_drv.c (eth_drv_recv): Change of type to remove
extern void lwip_dsr_stuff(void);
extern void lwip_set_addr(struct netif *);
+extern void lwip_dhcp_init(struct netif *);
//DSR called from the low level driver.Signals the input_thread
void
}
}
#endif
-
+ //
+ // we call this after the driver was started successfully
+ //
+ lwip_dhcp_init(netif);
}
//
static err_t
ecosif_output(struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr)
{
-
- p = etharp_output(netif, ipaddr, p);
- if (p) {
- low_level_output(netif, p);
- p = NULL;
- }
- return ERR_OK;
+ // resolve hardware address, then send (or queue) packet
+ return etharp_output(netif, ipaddr, p);
}
END_CONSOLE();
}
#endif
- if ( MAX_ETH_DRV_SG < sg_len ) {
+ if (m->m_next && (MAX_ETH_DRV_SG <= sg_len)) {
#ifdef CYGPKG_IO_ETH_DRIVERS_WARN_NO_MBUFS
int needed = 0;
struct mbuf *m1;
+2008-04-02 Xinghua Yang <yxinghua@sunnorth.com.cn>
+ Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * cdl/fileio.cdl: Use CYGPKG_FILEIO_DIRENT_DTYPE to enable/disable
+ d_type field of struct dirent.
+ * include/dirent.h: Add a d_type field to struct dirent, in order to
+ distinguish file type directly without calling stat.
+ * doc/fileio.sgml: Documentation about this new member and the fact
+ it is not portable.
+
+2007-08-17 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
+
+ tests/fnmatch.c (main): Fix cut/paste error in final pass/fail
+ report.
+
+2007-06-12 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/misc.cxx (cyg_mtab_extra): Only create the array if it has more
+ than 0 entries.
+
+2007-01-27 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * tests/fnmatch.c: Test case for fnmatch.
+
+2007-01-24 Peter Korsgaard <peter.korsgaard@barco.com>
+
+ * cdl/fileio.cdl:
+ * src/fnmatch.c:
+ * include/fnmatch.h: Added fnmatch() implementation (from NetBSD).
+
+2006-05-18 Paul Fine <pfine@dtccom.com>
+
+ * include/fileio.h : Added a key and a structure to extract the
+ disk size and the available free space for a filesystem using
+ the cyg_fs_getinfo() interface.
+
+2006-05-17 Andy Jackson <andy@grapevinetech.co.uk>
+
+ * tests/fileio1.c: Compiler warning fixes.
+ * tests/testfs.c: Compiler warning fixes.
+
+2006-02-16 Peter Korsgaard <jacmet@sunsite.dk>
+
+ * src/misc.cxx (cyg_mtab_lookup): Corrected implementation for
+ relative paths crossing mount points.
+ * tests/fileio1.c (cyg_user_start): Add a test for the above fix.
+
+2005-10-20 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/select.cxx: Needs sys/time.h for struct timeval.
+
2005-08-02 Andrew Lunn <andrew.lunn@ascom.ch>
* tests/socket.c (SHOW_RESULT): Add a cast to avoid compiler
}
+ cdl_option CYGSEM_FILEIO_INFO_DISK_USAGE {
+ display "cyg_fs_getinfo call for disk usage"
+ flavor bool
+ default_value 0
+ description "
+ Enabling this option includes code in some filesystems to
+ implement a call using cyg_fs_getinfo to return the current
+ filesystem block usage."
+ }
+
+ cdl_component CYGPKG_FILEIO_FNMATCH {
+ display "POSIX fnmatch configuration"
+ flavor bool
+ default_value ( CYGINT_ISO_STRING_STRFUNCS && CYGINT_ISO_CTYPE )
+ requires { CYGBLD_ISO_FNMATCH_HEADER == \
+ "<cyg/fileio/fnmatch.h>" }
+ description "
+ This component provides configuration controls for
+ the POSIX fnmatch() function."
+
+ compile fnmatch.c
+ }
+
+ cdl_option CYGPKG_FILEIO_DIRENT_DTYPE {
+ display "Struct dirent contains a d_type field"
+ flavor bool
+ default_value 0
+ description "
+ If this option is enabled then struct dirent contains a
+ d_type field. With this field, file type may be
+ distinguished directly without calling stat. Note: This
+ member is not part of the POSIX standard, however is
+ commonely implemented in Linux, FreeBSD, but not SunOS.
+ Also, not all filesystems support it. So this feature is
+ not portable and should be used with caution."
+ }
+
# ----------------------------------------------------------------
# Tests
display "Fileio tests"
flavor data
no_define
- calculated { "tests/fileio1 tests/socket tests/select tests/stdio tests/pselect" }
+ calculated { "tests/fileio1 tests/socket tests/select tests/stdio tests/pselect tests/fnmatch" }
description "
This option specifies the set of tests for the FileIO package."
}
Most of these considerations are invisible to clients of a filesystem
since they will access directories via the POSIX
<function>opendir()</function>, <function>readdir()</function> and
-<function>closedir()</function> functions.
-</para>
+<function>closedir()</function> functions. The <structname> struct
+dirent</structname> object returned by <function>readdir()</function>
+will always contain <structname>d_name</structname> as required by
+POSIX. When <literal>CYGPKG_FILEIO_DIRENT_DTYPE</literal> is enabled
+it will also contain <structname>d_type</structname>, which is not
+part of POSIX, but often implemented by OSes. Currently only the
+FATFS, RAMFS, ROMFS and JFFS2 filesystem sets this value. For other
+filesystems a value of 0 will be returned in the member.</para>
<para>
Support for the <function>getcwd()</function> function is provided by
<!-- }}} -->
-</part>
\ No newline at end of file
+</part>
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//========================================================================
struct dirent
{
+#ifdef CYGPKG_FILEIO_DIRENT_DTYPE
+
+ mode_t d_type; // Only supported with FATFS, RAMFS, ROMFS,
+ // and JFFS2.
+ // d_type is not part of POSIX so
+ // should be used with caution.
+#endif
char d_name[NAME_MAX+1];
};
#define FS_INFO_GETCWD 3 /* getcwd() */
#define FS_INFO_SYNC 4 /* cyg_fs_fssync() */
#define FS_INFO_ATTRIB 5 /* cyg_fs_(get|set)_attrib() */
-
+#ifdef CYGSEM_FILEIO_INFO_DISK_USAGE
+#define FS_INFO_DISK_USAGE 6 /* get_disk_usage() */
+#endif
//-----------------------------------------------------------------------------
// Types for link()
size_t size; /* size of buffer */
};
+struct cyg_fs_disk_usage{
+ cyg_uint64 total_blocks;
+ cyg_uint64 free_blocks;
+ cyg_uint32 block_size;
+};
+
typedef cyg_uint32 cyg_fs_attrib_t;
//-----------------------------------------------------------------------------
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
FILEIO_RETURN_VALUE( EBADF );
}
+#ifdef CYGPKG_FILEIO_DIRENT_DTYPE
+ // d_type is only supposed by a few filesystems, so make sure other
+ // filesystems return a sane value;
+ entry->d_type = 0;
+#endif
+
res = read( fd, (void *)entry, sizeof(struct dirent));
if( res < 0 )
if( res > 0 )
*result = entry;
+
+#ifdef CYGPKG_FILEIO_DIRENT_DTYPE
+ // Only the lower bits contain the type of file, so and those out.
+ entry->d_type &= S_IFMT;
+#endif
+
FILEIO_RETURN( ENOERR );
}
CYG_HAL_TABLE_BEGIN( cyg_mtab, mtab );
// Extra entries at end of mtab for dynamic mount points.
+#if CYGNUM_FILEIO_MTAB_EXTRA > 0
cyg_mtab_entry cyg_mtab_extra[CYGNUM_FILEIO_MTAB_EXTRA] CYG_HAL_TABLE_EXTRA(mtab) = { { NULL } };
-
+#endif
// End of mount table, set in the linker script.
__externC cyg_mtab_entry cyg_mtab_end;
CYG_HAL_TABLE_END( cyg_mtab_end, mtab );
else return 0;
}
+// -------------------------------------------------------------------------
+// Simple strlen implementation
+
+static int my_strlen(const char *c)
+{
+ int l = 0;
+ while (*c++) l++;
+ return l;
+}
+
// -------------------------------------------------------------------------
// Search the mtab for the entry that matches the longest substring of
// **name.
cyg_mtab_entry *m, *best = NULL;
int best_len = 0;
- // Unrooted file names go straight to current dir
+ // Unrooted file names start from current dir
if( **name != '/' ) {
+ int cwd_len;
if (*mte == (cyg_mtab_entry *)NULL) {
// No known current directory
return -1;
}
- // Current directory is well known
- return 0;
- }
- // Otherwise search the mount table.
- for( m = &cyg_mtab[0]; m != &cyg_mtab_end; m++ )
+ best = *mte;
+ cwd_len = my_strlen((*mte)->name);
+
+ // current dir is not the correct mte if the relative path crosses
+ // mount points - search for best matching mount point
+ for( m = &cyg_mtab[0]; m != &cyg_mtab_end; m++ )
+ {
+ if( m->name != NULL && m->valid )
+ {
+ int len = matchlen(m->name, (*mte)->name);
+ // mount point under cwd?
+ if (len == cwd_len)
+ {
+ if (m->name[len] == '/')
+ len++;
+
+ len = matchlen(*name, &m->name[len]);
+ if (len > best_len)
+ best = m, best_len = len;
+ }
+ }
+ }
+
+ // did we find a better match?
+ if (best != *mte)
+ *dir = best->root;
+ }
+ else
{
- if( m->name != NULL && m->valid )
+ // Otherwise search the mount table.
+ for( m = &cyg_mtab[0]; m != &cyg_mtab_end; m++ )
{
- int len = matchlen(*name,m->name);
- if( len > best_len )
- best = m, best_len = len;
+ if( m->name != NULL && m->valid )
+ {
+ int len = matchlen(*name,m->name);
+ if( len > best_len )
+ best = m, best_len = len;
+ }
}
+
+ // No match found, bad path name...
+ if( best_len == 0 ) return -1;
+
+ *dir = best->root;
}
- // No match found, bad path name...
- if( best_len == 0 ) return -1;
-
*name += best_len;
if( **name == '/' )
(*name)++;
*mte = best;
- *dir = best->root;
return 0;
}
#include "fio.h" // Private header
#include <sys/select.h> // select header
+#include <sys/time.h>
#include <cyg/kernel/sched.hxx> // scheduler definitions
#include <cyg/kernel/thread.hxx> // thread definitions
int i;
int err;
- diag_printf("<INFO>: create file %s size %d\n",name,size);
+ diag_printf("<INFO>: create file %s size %zd\n",name,size);
err = access( name, F_OK );
if( err < 0 && errno != EACCES ) SHOW_RESULT( access, err );
} while( wrote == IOSIZE );
- diag_printf("<INFO>: file size == %d\n",size);
+ diag_printf("<INFO>: file size == %zd\n",size);
err = close( fd );
if( err < 0 ) SHOW_RESULT( close, err );
checkfile( "/ram/tinky");
checkfile( "/ram/laalaa");
comparefiles( "/ram/tinky", "/ram/laalaa" );
+ comparefiles( "/ram/tinky", "ram/laalaa" );
+ comparefiles( "ram/tinky", "/ram/laalaa" );
err = chdir( "/ram" );
if( err < 0 ) SHOW_RESULT( chdir, err );
{
if( j > 0 && (j%4) == 0 )
diag_printf(indent);
- diag_printf(" %3d[%3ld,%3d]",b-block,
+ diag_printf(" %3d[%3ld,%3zd]",(int) (b-block),
(unsigned long)b->pos,b->size);
if( b->u.file != nd )
{
{
if( j > 0 && (j%4) == 0 )
diag_printf(indent);
- diag_printf(" %3d[%7s]",n-node,n->name);
+ diag_printf(" %3d[%7s]",(int) (n-node),n->name);
rc++;
}
}
{
int j;
testfs_node *nd = b->u.file;
- diag_printf(" %3ld %3d %d[%7s]",b->pos,b->size,nd-node,nd->name);
+ diag_printf(" %3ld %3zd %d[%7s]",b->pos,b->size,(int) (nd-node),nd->name);
for( j = 0; j < TESTFS_FILEBLOCKS; j++ )
{
if( nd->u.file.data[j] == b )
+2006-02-21 Oliver Munz <munz@speag.ch>
+ Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/flash.c (flash_init): Allow repeat calls change the function
+ used for printing. There are times you don't want any output, eg you
+ are downloading am image over the serial port.
+
2005-08-02 Andrew Lunn <andrew.lunn@ascom.ch>
* tests/flash1.c (cyg_start): Compiler warning fixes.
struct flash_info flash_info;
// These are the functions in the HW specific driver we need to call.
-typedef void code_fun(void*);
+typedef void code_fun(void *);
externC code_fun flash_query;
externC code_fun flash_erase_block;
{
int err;
- if (flash_info.init) return FLASH_ERR_OK;
flash_info.pf = pf; // Do this before calling into the driver
+ if (flash_info.init) return FLASH_ERR_OK;
+
if ((err = flash_hwr_init()) != FLASH_ERR_OK) {
return err;
}
// Use this function to make function pointers anonymous - forcing the
// compiler to use jumps instead of branches when calling driver
// services.
-static void* __anonymizer(void* p)
+static void *__anonymizer(void *p)
{
return p;
}
// make sense to wait till device structure pointer arguments get
// added as well.
void
-flash_dev_query(void* data)
+flash_dev_query(void *data)
{
- typedef void code_fun(void*);
+ typedef void code_fun(void *);
code_fun *_flash_query;
int d_cache, i_cache;
- _flash_query = (code_fun*) __anonymizer(&flash_query);
+ _flash_query = (code_fun*)__anonymizer(&flash_query);
HAL_FLASH_CACHES_OFF(d_cache, i_cache);
(*_flash_query)(data);
return FLASH_ERR_NOT_INIT;
}
if (((CYG_ADDRESS)target >= (CYG_ADDRESS)flash_info.start) &&
- ((CYG_ADDRESS)target <= ( ((CYG_ADDRESS)flash_info.end) - 1) )) {
+ ((CYG_ADDRESS)target <= ((CYG_ADDRESS)flash_info.end - 1))) {
return FLASH_ERR_OK;
} else {
return FLASH_ERR_INVALID;
return FLASH_ERR_PROTECT;
#endif
- _flash_erase_block = (code_fun*) __anonymizer(&flash_erase_block);
+ _flash_erase_block = (code_fun*)__anonymizer(&flash_erase_block);
block = (unsigned short *)((CYG_ADDRESS)addr & flash_info.block_mask);
- end_addr = (unsigned short *)((CYG_ADDRESS)addr+len);
+ end_addr = (unsigned short *)((CYG_ADDRESS)addr + len);
/* Check to see if end_addr overflowed */
- if( (end_addr < block) && (len > 0) ){
- end_addr = (unsigned short *) ((CYG_ADDRESS) flash_info.end - 1);
+ if ((end_addr < block) && (len > 0)) {
+ end_addr = (unsigned short *)((CYG_ADDRESS)flash_info.end - 1);
}
#ifdef CYGSEM_IO_FLASH_CHATTER
- (*flash_info.pf)("... Erase from %p-%p: ", (void*)block, (void*)end_addr);
+ flash_info.pf("... Erase from %p-%p: ", block, end_addr);
#endif
HAL_FLASH_CACHES_OFF(d_cache, i_cache);
dp = (unsigned char *)block;
for (i = 0; i < flash_info.block_size; i++) {
- if (*dp++ != (unsigned char)0xFF) {
+ if (*dp++ != 0xFF) {
erased = false;
break;
}
stat = flash_hwr_map_error(stat);
}
if (stat) {
- *err_addr = (void *)block;
+ *err_addr = block;
break;
}
// Check to see if block will overflow
tmp_block = block + flash_info.block_size / sizeof(*block);
- if(tmp_block < block){
+ if (tmp_block < block) {
// If block address overflows, set block value to end on this loop
block = end_addr;
- }
- else{
+ } else {
block = tmp_block;
}
#ifdef CYGSEM_IO_FLASH_CHATTER
- (*flash_info.pf)(".");
+ flash_info.pf(".");
#endif
}
- FLASH_Disable(block, end_addr);
+ FLASH_Disable((void *)((CYG_ADDRESS)addr & flash_info.block_mask), end_addr);
HAL_FLASH_CACHES_ON(d_cache, i_cache);
#ifdef CYGSEM_IO_FLASH_CHATTER
- (*flash_info.pf)("\n");
+ flash_info.pf("\n");
#endif
- return (stat);
+ return stat;
}
int
int size;
typedef int code_fun(void *, void *, int, unsigned long, int);
code_fun *_flash_program_buf;
- unsigned char *addr = (unsigned char *)_addr;
- unsigned char *data = (unsigned char *)_data;
+ unsigned char *addr = _addr;
+ unsigned char *data = _data;
CYG_ADDRESS tmp;
int d_cache, i_cache;
return FLASH_ERR_PROTECT;
#endif
- _flash_program_buf = (code_fun*) __anonymizer(&flash_program_buf);
+ _flash_program_buf = (code_fun*)__anonymizer(&flash_program_buf);
#ifdef CYGSEM_IO_FLASH_CHATTER
- (*flash_info.pf)("... Program from %p-%p at %p: ", (void*)data,
- (void*)(((CYG_ADDRESS)data)+len), (void*)addr);
+ flash_info.pf("... Program from %p-%p at %p: ", data,
+ (void *)((CYG_ADDRESS)data + len), addr);
#endif
HAL_FLASH_CACHES_OFF(d_cache, i_cache);
- FLASH_Enable((unsigned short*)addr, (unsigned short *)(addr+len));
+ FLASH_Enable(addr, addr + len);
while (len > 0) {
size = len;
+#if defined(MXCFLASH_SELECT_NAND) || defined(MXCFLASH_SELECT_MMC)
+ if (flash_info.start != 0)
+#endif
if (size > flash_info.block_size) size = flash_info.block_size;
tmp = (CYG_ADDRESS)addr & ~flash_info.block_mask;
if (tmp) {
tmp = flash_info.block_size - tmp;
- if (size>tmp) size = tmp;
-
+ if (size > tmp) size = tmp;
}
stat = (*_flash_program_buf)(addr, data, size,
if (memcmp(addr, data, size) != 0) {
stat = 0x0BAD;
#ifdef CYGSEM_IO_FLASH_CHATTER
- (*flash_info.pf)("V");
+ flash_info.pf("V");
#endif
}
#endif
if (stat) {
- *err_addr = (void *)addr;
+ *err_addr = addr;
break;
}
#ifdef CYGSEM_IO_FLASH_CHATTER
- (*flash_info.pf)(".");
+ flash_info.pf(".");
#endif
len -= size;
addr += size/sizeof(*addr);
data += size/sizeof(*data);
}
- FLASH_Disable((unsigned short*)addr, (unsigned short *)(addr+len));
+ FLASH_Disable(_addr, addr);
HAL_FLASH_CACHES_ON(d_cache, i_cache);
#ifdef CYGSEM_IO_FLASH_CHATTER
- (*flash_info.pf)("\n");
+ flash_info.pf("\n");
#endif
- return (stat);
+ return stat;
}
int
int size;
typedef int code_fun(void *, void *, int, unsigned long, int);
code_fun *_flash_read_buf;
- unsigned char *addr = (unsigned char *)_addr;
- unsigned char *data = (unsigned char *)_data;
+ unsigned char *addr = _addr;
+ unsigned char *data = _data;
CYG_ADDRESS tmp;
int d_cache, i_cache;
return FLASH_ERR_NOT_INIT;
}
- _flash_read_buf = (code_fun*) __anonymizer(&flash_read_buf);
+ _flash_read_buf = (code_fun*)__anonymizer(&flash_read_buf);
-#ifdef CYGSEM_IO_FLASH_CHATTER
- (*flash_info.pf)("... Read from %p-%p at %p: ", (void*)data,
- (void*)(((CYG_ADDRESS)data)+len), (void*)addr);
+#ifdef CYGSEM_IO_FLASH_CHATTER_VERBOSE
+ flash_info.pf("... Read from %p-%p at %p: ", data,
+ (void *)((CYG_ADDRESS)data + len), addr);
#endif
HAL_FLASH_CACHES_OFF(d_cache, i_cache);
- FLASH_Enable((unsigned short*)addr, (unsigned short *)(addr+len));
+ FLASH_Enable(addr, addr + len);
while (len > 0) {
size = len;
+#if defined(MXCFLASH_SELECT_NAND) || defined(MXCFLASH_SELECT_MMC)
+ if (flash_info.start !=0)
+#endif
if (size > flash_info.block_size) size = flash_info.block_size;
tmp = (CYG_ADDRESS)addr & ~flash_info.block_mask;
stat = (*_flash_read_buf)(addr, data, size,
flash_info.block_mask, flash_info.buffer_size);
stat = flash_hwr_map_error(stat);
-#ifdef CYGSEM_IO_FLASH_VERIFY_PROGRAM_
+#ifdef CYGSEM_IO_FLASH_VERIFY_PROGRAM
if (0 == stat) // Claims to be OK
if (memcmp(addr, data, size) != 0) {
stat = 0x0BAD;
-#ifdef CYGSEM_IO_FLASH_CHATTER
- (*flash_info.pf)("V");
+#ifdef CYGSEM_IO_FLASH_CHATTER_VERBOSE
+ flash_info.pf("V");
#endif
}
#endif
if (stat) {
- *err_addr = (void *)addr;
+ *err_addr = addr;
break;
}
-#ifdef CYGSEM_IO_FLASH_CHATTER
- (*flash_info.pf)(".");
+#ifdef CYGSEM_IO_FLASH_CHATTER_VERBOSE
+ flash_info.pf(".");
#endif
len -= size;
- addr += size/sizeof(*addr);
- data += size/sizeof(*data);
+ addr += size / sizeof(*addr);
+ data += size / sizeof(*data);
}
- FLASH_Disable((unsigned short*)addr, (unsigned short *)(addr+len));
+ FLASH_Disable(_addr, addr);
HAL_FLASH_CACHES_ON(d_cache, i_cache);
-#ifdef CYGSEM_IO_FLASH_CHATTER
- (*flash_info.pf)("\n");
+#ifdef CYGSEM_IO_FLASH_CHATTER_VERBOSE
+ flash_info.pf("\n");
#endif
- return (stat);
+ return stat;
#else // CYGSEM_IO_FLASH_READ_INDIRECT
// Direct access to FLASH memory is possible - just move the requested bytes
if (!flash_info.init) {
return FLASH_ERR_PROTECT;
#endif
- _flash_lock_block = (code_fun*) __anonymizer(&flash_lock_block);
+ _flash_lock_block = (code_fun*)__anonymizer(&flash_lock_block);
block = (unsigned short *)((CYG_ADDRESS)addr & flash_info.block_mask);
- end_addr = (unsigned short *)((CYG_ADDRESS)addr+len);
+ end_addr = (unsigned short *)((CYG_ADDRESS)addr + len);
/* Check to see if end_addr overflowed */
- if( (end_addr < block) && (len > 0) ){
- end_addr = (unsigned short *) ((CYG_ADDRESS) flash_info.end - 1);
+ if ((end_addr < block) && (len > 0)) {
+ end_addr = (unsigned short *)((CYG_ADDRESS)flash_info.end - 1);
}
#ifdef CYGSEM_IO_FLASH_CHATTER
- (*flash_info.pf)("... Lock from %p-%p: ", block, end_addr);
+ flash_info.pf("... Lock from %p-%p: ", block, end_addr);
#endif
HAL_FLASH_CACHES_OFF(d_cache, i_cache);
stat = (*_flash_lock_block)(block);
stat = flash_hwr_map_error(stat);
if (stat) {
- *err_addr = (void *)block;
+ *err_addr = block;
break;
}
// Check to see if block will overflow
tmp_block = block + flash_info.block_size / sizeof(*block);
- if(tmp_block < block){
+ if (tmp_block < block) {
// If block address overflows, set block value to end on this loop
block = end_addr;
- }
- else{
+ } else {
block = tmp_block;
}
#ifdef CYGSEM_IO_FLASH_CHATTER
- (*flash_info.pf)(".");
+ flash_info.pf(".");
#endif
}
- FLASH_Disable(block, end_addr);
+ FLASH_Disable((void *)((CYG_ADDRESS)addr & flash_info.block_mask),
+ end_addr);
HAL_FLASH_CACHES_ON(d_cache, i_cache);
#ifdef CYGSEM_IO_FLASH_CHATTER
- (*flash_info.pf)("\n");
+ flash_info.pf("\n");
#endif
- return (stat);
+ return stat;
}
int
flash_unlock(void *addr, int len, void **err_addr)
{
- unsigned short *block, *end_addr;
- int stat = 0;
- typedef int code_fun(unsigned short *, int, int);
- code_fun *_flash_unlock_block;
- int d_cache, i_cache;
+ unsigned short *block, *end_addr;
+ int stat = 0;
+ typedef int code_fun(unsigned short *, int, int);
+ code_fun *_flash_unlock_block;
+ int d_cache, i_cache;
- if (!flash_info.init) {
- return FLASH_ERR_NOT_INIT;
- }
+ if (!flash_info.init) {
+ return FLASH_ERR_NOT_INIT;
+ }
#ifdef CYGSEM_IO_FLASH_SOFT_WRITE_PROTECT
- if (plf_flash_query_soft_wp(addr,len))
- return FLASH_ERR_PROTECT;
+ if (plf_flash_query_soft_wp(addr,len))
+ return FLASH_ERR_PROTECT;
#endif
- _flash_unlock_block = (code_fun*) __anonymizer(&flash_unlock_block);
+ _flash_unlock_block = (code_fun*)__anonymizer(&flash_unlock_block);
- block = (unsigned short *)((CYG_ADDRESS)addr & flash_info.block_mask);
- end_addr = (unsigned short *)((CYG_ADDRESS)addr+len);
+ block = (unsigned short *)((CYG_ADDRESS)addr & flash_info.block_mask);
+ end_addr = (unsigned short *)((CYG_ADDRESS)addr + len);
- /* Check to see if end_addr overflowed */
- if( (end_addr < block) && (len > 0) ){
- end_addr = (unsigned short *) ((CYG_ADDRESS) flash_info.end - 1);
- }
+ /* Check to see if end_addr overflowed */
+ if ((end_addr < block) && (len > 0)) {
+ end_addr = (unsigned short *)((CYG_ADDRESS)flash_info.end - 1);
+ }
#ifdef CYGSEM_IO_FLASH_CHATTER
- (*flash_info.pf)("... Unlock from %p-%p: ", block, end_addr);
+ flash_info.pf("... Unlock from %p-%p: ", block, end_addr);
#endif
- HAL_FLASH_CACHES_OFF(d_cache, i_cache);
- FLASH_Enable(block, end_addr);
- while (block < end_addr) {
- unsigned short *tmp_block;
- stat = (*_flash_unlock_block)(block, flash_info.block_size, flash_info.blocks);
- stat = flash_hwr_map_error(stat);
- if (stat) {
- *err_addr = (void *)block;
- break;
- }
-
- tmp_block = block + flash_info.block_size / sizeof(*block);
- if(tmp_block < block){
- // If block address overflows, set block value to end on this loop
- block = end_addr;
- }
- else{
- block = tmp_block;
- }
+ HAL_FLASH_CACHES_OFF(d_cache, i_cache);
+ FLASH_Enable(block, end_addr);
+ while (block < end_addr) {
+ unsigned short *tmp_block;
+ stat = (*_flash_unlock_block)(block, flash_info.block_size, flash_info.blocks);
+ stat = flash_hwr_map_error(stat);
+ if (stat) {
+ *err_addr = block;
+ break;
+ }
+
+ tmp_block = block + flash_info.block_size / sizeof(*block);
+ if (tmp_block < block) {
+ // If block address overflows, set block value to end on this loop
+ block = end_addr;
+ } else {
+ block = tmp_block;
+ }
#ifdef CYGSEM_IO_FLASH_CHATTER
- (*flash_info.pf)(".");
+ flash_info.pf(".");
#endif
- }
- FLASH_Disable(block, end_addr);
- HAL_FLASH_CACHES_ON(d_cache, i_cache);
+ }
+ FLASH_Disable((void *)((CYG_ADDRESS)addr & flash_info.block_mask),
+ end_addr);
+ HAL_FLASH_CACHES_ON(d_cache, i_cache);
#ifdef CYGSEM_IO_FLASH_CHATTER
- (*flash_info.pf)("\n");
+ flash_info.pf("\n");
#endif
- return (stat);
+ return stat;
}
#endif
display "Additional compiler flags"
flavor data
no_define
- default_value { "" }
+ default_value { "-fno-rtti -Woverloaded-virtual" }
description "
This option modifies the set of compiler flags for
building the generic I2C package. These flags are
display "Suppressed compiler flags"
flavor data
no_define
- default_value { "" }
+ default_value { "-Wno-pointer-sign" }
description "
This option modifies the set of compiler flags for
building the generic I2C package. These flags are
+2008-01-30 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/common/termiostty.c (termios_lookup): Add missing set of
+ init flag. Pointed out by Rainer Arndt.
+
+
+2008-01-30 Rainer Arndt <Arndt-ADT@kieback-peter.de>
+
+ * src/common/termiostty.c (ecosbaud2posixbaud[]): Add missing
+ B1800 entry.
+
+2006-08-31 Ilija Koco <ilijak@siva.com.mk>
+ Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * cdl/termios.cdl:
+ src/common/termiostty.c: added Termios TTY channel #3
+ * cdl/tty.cdl:
+ src/common/tty.c: added TTY mode channel #3
+
+
+2006-08-22 Peter Csordas <csordas@mit.bme.hu>
+
+ * include/serialio.h (cyg_serial_baud_rate_t): Adding baud rate
+ defines for 460800 and 921600 baud.
+
+2006-08-25 Gary Thomas <gary@mlbassoc.com>
+
+ * cdl/io_serial.cdl: Set parent for more intuitive ConfigTool layout.
+
+2006-05-09 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/common/tty.c (tty_init): Fix compiler warning with
+ diag_printf() arguments.
+
2005-09-02 Sebastien Couret <sebastien.couret@elios-informatique.fr>
* src/common/termiostty.c and
cdl_package CYGPKG_IO_SERIAL {
display "Serial device drivers"
+ parent CYGPKG_IO
active_if CYGPKG_IO
requires CYGPKG_ERROR
include_dir cyg/io
}
}
+cdl_component CYGPKG_IO_SERIAL_TERMIOS_TERMIOS3 {
+ display "Termios TTY channel #3"
+ flavor bool
+ default_value 0
+ implements CYGINT_IO_SERIAL_TERMIOS_TERMIOS_TTY
+ description "
+ This option causes '/dev/termios3' to be included in the standard
+ drivers."
+
+ cdl_option CYGDAT_IO_SERIAL_TERMIOS_TERMIOS3_DEV {
+ display "Termios TTY channel #3 device"
+ flavor data
+ default_value {"\"/dev/ser3\""}
+ description "
+ This option selects the physical device to use for
+ '/dev/termios3'."
+ }
+}
+
cdl_option CYGSEM_IO_SERIAL_TERMIOS_USE_SIGNALS {
display "Support signals"
flavor bool
'/dev/tty2'."
}
}
+
+cdl_component CYGPKG_IO_SERIAL_TTY_TTY3 {
+ display "TTY mode channel #3"
+ flavor bool
+ default_value 0
+ description "
+ This option causes '/dev/tty3' to be included in the standard
+ drivers."
+
+ cdl_option CYGDAT_IO_SERIAL_TTY_TTY3_DEV {
+ display "TTY mode channel #3 device"
+ flavor data
+ default_value {"\"/dev/ser3\""}
+ description "
+ This option selects the physical device to use for
+ '/dev/tty3'."
+ }
+}
CYGNUM_SERIAL_BAUD_38400,
CYGNUM_SERIAL_BAUD_57600,
CYGNUM_SERIAL_BAUD_115200,
- CYGNUM_SERIAL_BAUD_230400
+ CYGNUM_SERIAL_BAUD_230400,
+ CYGNUM_SERIAL_BAUD_460800,
+ CYGNUM_SERIAL_BAUD_921600
} cyg_serial_baud_rate_t;
-#define CYGNUM_SERIAL_BAUD_MIN CYGNUM_SERIAL_BAUD_50
-#define CYGNUM_SERIAL_BAUD_MAX CYGNUM_SERIAL_BAUD_230400
+#define CYGNUM_SERIAL_BAUD_MIN CYGNUM_SERIAL_BAUD_50
+#define CYGNUM_SERIAL_BAUD_MAX CYGNUM_SERIAL_BAUD_921600
// Note: two levels of macro are required to get proper expansion.
#define _CYG_SERIAL_BAUD_RATE(n) CYGNUM_SERIAL_BAUD_##n
&termios_private_info2);
#endif
+#ifdef CYGPKG_IO_SERIAL_TERMIOS_TERMIOS3
+static struct termios_private_info termios_private_info3;
+DEVTAB_ENTRY(termios_io3,
+ "/dev/termios3",
+ CYGDAT_IO_SERIAL_TERMIOS_TERMIOS3_DEV,
+ &termios_devio,
+ termios_init,
+ termios_lookup,
+ &termios_private_info3);
+#endif
+
static const cc_t c_cc_init[ NCCS ] = {
0x04, /* EOF == ^D */
0, /* EOL */
// map eCos bitrates to POSIX bitrates.
static speed_t ecosbaud2posixbaud[] = {
- 0, B50, B75, B110, B134, B150, B200, B300, B600, B1200, B2400, B3600,
+ 0, B50, B75, B110, B134, B150, B200, B300, B600, B1200, B1800, B2400, B3600,
B4800, B7200, B9600, B14400, B19200, B38400, B57600, B115200, B230400 };
// map POSIX bitrates to eCos bitrates.
if ( !priv->init ) {
cyg_drv_mutex_lock( &priv->lock );
if ( !priv->init ) { // retest as we may have been pre-empted
+ priv->init = true;
priv->dev_handle = chan;
err = real_termios_init( priv );
}
&tty_private_info2);
#endif
+#ifdef CYGPKG_IO_SERIAL_TTY_TTY3
+static struct tty_private_info tty_private_info3;
+DEVTAB_ENTRY(tty_io3,
+ "/dev/tty3",
+ CYGDAT_IO_SERIAL_TTY_TTY3_DEV,
+ &tty_devio,
+ tty_init,
+ tty_lookup, // Execute this when device is being looked up
+ &tty_private_info3);
+#endif
+
static bool
tty_init(struct cyg_devtab_entry *tab)
{
struct tty_private_info *priv = (struct tty_private_info *)tab->priv;
#ifdef CYGDBG_IO_INIT
- diag_printf("Init tty channel: %x\n", tab);
+ diag_printf("Init tty channel: %p\n", tab);
#endif
priv->dev_info.tty_out_flags = CYG_TTY_OUT_FLAGS_DEFAULT;
priv->dev_info.tty_in_flags = CYG_TTY_IN_FLAGS_DEFAULT;
+2006-02-23 Thomas Siegmund <thomas.siegmund@hach-lange.de>
+
+ * include/usb.h: changed position of __attribute__((packed)) to be
+ compatible with more recent versions of GCC.
+
2001-01-25 Bart Veer <bartv@redhat.com>
* cdl/usb.cdl:
unsigned char index_hi;
unsigned char length_lo;
unsigned char length_hi;
-} usb_devreq __attribute__((packed));
+} __attribute__((packed)) usb_devreq;
// Encoding of the request_type
#define USB_DEVREQ_DIRECTION_OUT 0
unsigned char product_str;
unsigned char serial_number_str;
unsigned char number_configurations;
-} usb_device_descriptor __attribute__((packed));
+} __attribute__((packed)) usb_device_descriptor;
#define USB_DEVICE_DESCRIPTOR_LENGTH 18
#define USB_DEVICE_DESCRIPTOR_TYPE USB_DEVREQ_DESCRIPTOR_TYPE_DEVICE
unsigned char configuration_str;
unsigned char attributes;
unsigned char max_power;
-} usb_configuration_descriptor __attribute__((packed));
+} __attribute__((packed)) usb_configuration_descriptor;
#define USB_CONFIGURATION_DESCRIPTOR_LENGTH 9
#define USB_CONFIGURATION_DESCRIPTOR_TYPE USB_DEVREQ_DESCRIPTOR_TYPE_CONFIGURATION
unsigned char interface_subclass;
unsigned char interface_protocol;
unsigned char interface_str;
-} usb_interface_descriptor __attribute__((packed));
+} __attribute__((packed)) usb_interface_descriptor;
#define USB_INTERFACE_DESCRIPTOR_LENGTH 9
#define USB_INTERFACE_DESCRIPTOR_TYPE USB_DEVREQ_DESCRIPTOR_TYPE_INTERFACE
unsigned char max_packet_lo;
unsigned char max_packet_hi;
unsigned char interval;
-} usb_endpoint_descriptor;
+} __attribute__((packed)) usb_endpoint_descriptor;
#define USB_ENDPOINT_DESCRIPTOR_LENGTH 7
#define USB_ENDPOINT_DESCRIPTOR_TYPE USB_DEVREQ_DESCRIPTOR_TYPE_ENDPOINT
+2006-05-07 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * host/bulk-boundaries.tcl(New): test bulk transfers at
+ boundary cases.
+ * doc/usbs.sgml: Documentation of bulk-boundaries.tcl test.
+
+2006-04-23 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * doc/usbs-testing.html: Correct "format" for "data" when
+ specifiying what the data in the USB message will contain.
+
+2006-04-16 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * host/usbhost.c (tcl_run): Fix compiler warnings
+ * host/usbhost.c (pool_function): sem_wait can exit with a
+ EINTR. If so loop and try again.
+
+ * host/usbchmod.c (usb_scan_devices) propergate previous fix from
+ usbhost.c
+
+2006-04-16 Frank Pagliughi <fpagliughi@mindspring.com>
+
+ *host/usbhost.c (usb_scan_devices) Fix parsing EOL for FC4 and
+ others.
+
+2006-03-10 Bart Veer <bartv@ecoscentric.com>
+
+ * src/usbs.c (usbs_devtab_cwrite, usbs_devtab_cwrite): add
+ DSR locking
+
2005-06-26 Bart Veer <bartv@ecoscentric.com>
* host/usbhost.c, host/configure.in: cope with incompatible
This can be controlled by the argument <TT
CLASS="PARAMETER"
><I
->data</I
+>format</I
></TT
>
which can take one of five values: <TT
><TD
><PRE
CLASS="PROGRAMLISTING"
->bulktest 2 IN 1000 data=wordseq data1=42 \
+>bulktest 2 IN 1000 format=wordseq data1=42 \
data* $usbtest::MULTIPLIER data+ $usbtest::INCREMENT</PRE
></TD
></TR
></DIV
></BODY
></HTML
->
\ No newline at end of file
+>
be used.
</para></listitem>
</varlistentry>
+ <varlistentry><term><filename>bulk-boundaries.tcl</filename></term>
+ <listitem><para> This script performs simple bulk IN and OUT
+ transfers of different sizes around interesting boundaries. This
+ test is useful to ensure the driver correctly handles the case
+ where a transfer is just smaller than, the same size as, and
+ just bigger than the hardware buffer in the endpoint hardware.
+ This script takes no parameters. It determines what endpoints
+ the device has by asking it.
+ </para></listitem>
+ </varlistentry>
</variablelist>
</refsect1>
#include <sys/types.h>
#include <sys/stat.h>
#include <errno.h>
+#include <string.h>
// Note: this code is duplicated in usbhost.c. Any changes here
// should be propagated. For now the routine is too small to warrant
}
}
// Move to the end of the current line.
- do {
+ while ((EOF != ch) && ('\n' != ch)) {
ch = getc(devs_file);
- } while ((EOF != ch) && ('\n' != ch));
+ }
if (EOF != ch) {
ch = getc(devs_file);
}
if (0 != chmod(devname, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH)) {
int old_errno = errno;
fprintf(stderr, "usbchmod: failed to modify access rights on %s\n", devname);
- if ((old_errno >= 0) && (old_errno < sys_nerr)) {
- fprintf(stderr, " : %s\n", sys_errlist[old_errno]);
- }
+ fprintf(stderr, " : %s\n", strerror(old_errno));
exit(EXIT_FAILURE);
}
}
}
// Move to the end of the current line.
- do {
+ while ((EOF != ch) && ('\n' != ch)) {
ch = getc(devs_file);
- } while ((EOF != ch) && ('\n' != ch));
+ }
if (EOF != ch) {
ch = getc(devs_file);
}
}
if (-1 == result) {
fprintf(stderr, "usbhost: error, failed to open \"%s\", errno %d\n", devname, errno);
+ exit(EXIT_FAILURE);
}
VERBOSE(1, "USB device now accessible via file descriptor %d\n", result);
static void
usb_initialise_bulk_out_endpoint(int number, int min_size, int max_size)
{
- char buf[1];
-
+ unsigned char buf[1];
+
// On the SA1110 the hardware comes up with a bogus default value,
// causing the hardware to accept packets before the software has
// set up DMA or in any way prepared for incoming data. This is
pool_function(void* arg)
{
PoolEntry* pool_entry = (PoolEntry*) arg;
+ int ret;
+
for ( ; ; ) {
- sem_wait(&(pool_entry->wakeup));
+ do {
+ ret = sem_wait(&(pool_entry->wakeup));
+ if (ret != 0 && errno != EINTR) {
+ perror("sem_wait");
+ exit(1);
+ }
+ } while (ret != 0);
run_test(&(pool_entry->test));
pool_entry->running = 0;
}
usb_reliable_control_message(usb_master_fd, USB_TYPE_CLASS | USB_RECIP_DEVICE | USB_DIR_IN, USBTEST_GET_RESULT,
0, i, USBTEST_MAX_CONTROL_DATA, (void*) result_buf);
if (!result_buf[0]) {
- Tcl_SetVar(interp, "usbtest::results", &(result_buf[1]),
+ Tcl_SetVar(interp, "usbtest::results", (char *)&(result_buf[1]),
all_ok ? TCL_GLOBAL_ONLY : (TCL_GLOBAL_ONLY | TCL_APPEND_VALUE | TCL_LIST_ELEMENT));
all_ok = 0;
}
usb_reliable_control_message(usb_master_fd, USB_TYPE_CLASS | USB_RECIP_DEVICE | USB_DIR_IN, USBTEST_GET_RESULT,
0, i, USBTEST_MAX_CONTROL_DATA, (void*) result_buf);
if (!result_buf[0]) {
- Tcl_SetVar(interp, "usbtest::results", &(result_buf[1]),
+ Tcl_SetVar(interp, "usbtest::results", (char *)&(result_buf[1]),
all_ok ? TCL_GLOBAL_ONLY : (TCL_GLOBAL_ONLY | TCL_APPEND_VALUE | TCL_LIST_ELEMENT));
all_ok = 0;
}
(*endpoint->start_tx_fn)(endpoint);
cyg_drv_mutex_lock(&wait.lock);
+ cyg_drv_dsr_lock();
while (!wait.completed) {
cyg_drv_cond_wait(&wait.signal);
}
+ cyg_drv_dsr_unlock();
cyg_drv_mutex_unlock(&wait.lock);
if (wait.result < 0) {
result = wait.result;
endpoint->complete_data = (void*) &wait;
(*endpoint->start_rx_fn)(endpoint);
cyg_drv_mutex_lock(&wait.lock);
+ cyg_drv_dsr_lock();
while (!wait.completed) {
cyg_drv_cond_wait(&wait.signal);
}
+ cyg_drv_dsr_unlock();
cyg_drv_mutex_unlock(&wait.lock);
if (wait.result < 0) {
result = wait.result;
test->recovery.protocol = USB_ENDPOINT_DESCRIPTOR_ATTR_BULK;
test->recovery.size = packet_size + usbs_testing_endpoints[ep_index].max_in_padding;
+ CYG_ASSERTC(sizeof(test->buffer) > packet_size);
+
// Make sure the buffer contains the data expected by the host
usbtest_fill_buffer(&(test->test_params.bulk.data), buf, packet_size);
-
+
if (verbose < 3) {
VERBOSE(2, "Bulk OUT test %d: iteration %d, packet size %d\n", test->id, i, packet_size);
} else {
handle_reserved_control_messages(usbs_control_endpoint* endpoint, void* data)
{
usb_devreq* req = (usb_devreq*) endpoint->control_buffer;
- usbs_control_return result;
+ usbs_control_return result = USBS_CONTROL_RETURN_UNKNOWN;
CYG_ASSERT(endpoint == control_endpoint, "control endpoint mismatch");
switch(req->request) {
if (control_in_test_packet_size != len) {
control_in_test->result_pass = 0;
snprintf(control_in_test->result_message, USBTEST_MAX_MESSAGE,
- "Target, control IN transfer on endpoint %d : the host only requested %d bytes instead of %d",
+ "Target, control IN transfer : the host only requested %d bytes instead of %d",
len, control_in_test_packet_size);
cyg_semaphore_post(&(control_in_test->sem));
control_in_test = (UsbTest*) 0;
// function pointer is used to keep track of what operation is actually required.
for (;;) {
void (*handler)(void);
-
+
cyg_semaphore_wait(&main_wakeup);
handler = main_thread_action;
main_thread_action = 0;
+2007-01-14 Gary Thomas <gary@mlbassoc.com>
+
+ * src/wallclock.cxx: Use a mutex for exclusion during get/set
+ operations as the DSR lock may not be appropriate for systems
+ that need to use interrupts to accomplish these functions,
+ (e.g. I2C clock devices).
+
2003-09-23 Dan Jakubiec <firstname.lastname@systech.com>
* src/emulate.cxx (get_hw_seconds): Modified the ticks-to-seconds
static cyg_uint32 epoch_time_stamp;
#endif
+static cyg_drv_mutex_t wallclock_lock;
+
Cyg_WallClock *Cyg_WallClock::wallclock;
//-----------------------------------------------------------------------------
// install instance pointer
wallclock = &wallclock_instance;
+ // Initialize lock used for mutually exclusive access to hardware
+ cyg_drv_mutex_init(&wallclock_lock);
+
// Always allow low-level driver to initialize clock, even though it
// may not be necessary for set-get mode.
init_hw_seconds();
{
cyg_uint32 res;
- cyg_drv_dsr_lock();
+ while (!cyg_drv_mutex_lock(&wallclock_lock));
#ifdef CYGSEM_WALLCLOCK_SET_GET_MODE
res = get_hw_seconds();
res = epoch_time_stamp + get_hw_seconds() - epoch_ticks;
#endif
- cyg_drv_dsr_unlock();
+ cyg_drv_mutex_unlock(&wallclock_lock);
return res;
}
// anything up to a second to complete.
void Cyg_WallClock::set_current_time( cyg_uint32 time_stamp )
{
- cyg_drv_dsr_lock();
+ while (!cyg_drv_mutex_lock(&wallclock_lock));
#ifdef CYGSEM_WALLCLOCK_SET_GET_MODE
set_hw_seconds(time_stamp);
epoch_ticks = get_hw_seconds();
#endif
- cyg_drv_dsr_unlock();
+ cyg_drv_mutex_unlock(&wallclock_lock);
}
//-----------------------------------------------------------------------------
+2007-01-24 Peter Korsgaard <peter.korsgaard@barco.com>
+
+ * cdl/isoinfra.cdl:
+ * include/fnmatch.h: fnmatch() support.
+
+2006-03-17 Sergei Organov <osv@javad.com>
+
+ * include/assert.h: Replace #if defined(CYGINT_ISO_EXIT) with #if
+ CYGINT_ISO_EXIT. CYGINT_ISO_EXIT configuration variable is always
+ defined to either 0 or 1, so check of the former form is always
+ evaluated to true.
+
+2005-10-20 Alexander Neundorf <neundorf@kde.org>
+ Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * include/sys/time.h (new): Basic implementation.
+ * include/time.h: Removed timeval which is now in sys/time.h
+
2005-07-22 Andrew Lunn <andrew.lunn@ascom.ch>
* include/unistd.h: Const correctness to keep the compiler happy.
default_value 0
}
+ cdl_option CYGBLD_ISO_FNMATCH_HEADER {
+ display "fnmatch implementation header"
+ flavor booldata
+ default_value 0
+ }
+
cdl_interface CYGINT_ISO_POSIX_TIMER_TYPES {
display "Number of implementations of POSIX timer types"
requires { 1 >= CYGINT_ISO_POSIX_TIMER_TYPES }
/* First preference is to be standards compliant */
-#if defined(CYGINT_ISO_STDIO_FORMATTED_IO) && defined(CYGINT_ISO_EXIT)
+#if defined(CYGINT_ISO_STDIO_FORMATTED_IO) && CYGINT_ISO_EXIT
# include <stdio.h>
# include <stdlib.h>
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//========================================================================
# define __clock_t_defined
#endif
-#ifdef CYGBLD_ISO_STRUCTTIMEVAL_HEADER
-# include CYGBLD_ISO_STRUCTTIMEVAL_HEADER
-#else
-# ifndef _POSIX_SOURCE
-
-/*
- * Structure returned by gettimeofday(2),
- * and used in other calls such as select(2).
- */
-struct timeval {
- long tv_sec; /* seconds */
- long tv_usec; /* and microseconds */
-};
-
-# endif /* _POSIX_SOURCE */
-#endif
-
-
#ifdef CYGINT_ISO_POSIX_CLOCK_TYPES
# include CYGBLD_ISO_POSIX_CLOCK_TYPES_HEADER
#else
+2007-08-23 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
+
+ * tests/intr0.cxx, tests/kintr0.c: As suggested by Bart Veer,
+ priorities of the interrupts created by intr0 and kintr0 can now
+ be overridden by the HAL through HAL_INTR_TEST_PRIO_x constants.
+
+2007-07-02 Gary Thomas <gary@mlbassoc.com>
+
+ * src/debug/dbg_gdb.cxx:
+ * src/common/thread.cxx (Cyg_IdleThread): Add (char *) casts
+ to make GCC/4.2.x happy.
+
+2007-06-11 Nick Garnett <nickg@ecoscentric.com>
+
+ * tests/klock.c (entry0, entry1): Modify mbox part of test to
+ reflect use of plain mbox implementation. The precise ordering of
+ events is slightly different.
+
+2007-01-07 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/sync/mbox.cxx (Cyg_Mbox::get): Fix compiler warning with gcc
+ version 4.1.2.
+
+2006-12-08 Nick Garnett <nickg@ecoscentric.com>
+
+ * src/sched/mlqueue.cxx (add_thread, yield):
+ * src/sched/sched.cxx (unlock_inner, thread_entry):
+ * include/mlqueue.hxx (class Cyg_SchedThread_Implementation):
+ * include/kapidata.h (CYG_SCHEDTHREAD_TIMESLICE_MEMBER):
+ * include/bitmap.hxx (class Cyg_SchedThread_Implementation):
+ Reimplement timeslicing code. There is now a timeslice_count field
+ in each thread which is moved to and from the per-CPU counter
+ during thread dispatch. This approach has been taken to minimize
+ the changes needed to SMP code. Scheduler specific thread
+ functions handle counter save, restore and reset. These functions
+ are defined (as empty inlines) even when timeslicing is disabled,
+ or in non-timeslicing schedulers, to avoid adding ifdefs to the
+ code (this change actually removes some).
+
+ * tests/timeslice2.c:
+ * cdl/kernel.cdl: Added timeslice2 test to test behaviour of
+ timeslicing while being preempted.
+
+2006-10-12 Nick Garnett <nickg@ecoscentric.com>
+
+ * cdl/synch.cdl: Added CYGIMP_MBOX_USE_MBOXT_PLAIN option. This is
+ tested in various places but was not actually defined. It now is
+ and defaults to 1 so that the plain version of mail boxes is
+ selected.
+
+ * include/mboxt.inl:
+ * include/mboxt2.inl: Moved various CYG_ASSERTCLASS() calls to be
+ within scheduler locked regions. Race conditions could have caused
+ them to fail before.
+
+ * tests/mbox1.cxx:
+ * tests/kmbox1.cxx: Updated tests to work with mboxt
+ implementation. This requires thread 1 to run at lower priority
+ than thread 0.
+
+2006-08-21 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * doc/kernel.sgml: Use reinterpret_cast, not static cast
+ Thanks to Tony Garland for the report in bug 1000299.
+
+2006-05-19 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * host/instr/dump_instr.c: Use CYG_NELEM from infra.
+ * src/instrmnt/meminst.cxx: Use CYG_NELEM from infra.
+
+2006-05-09 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * tests/stress_threads.c: Add string.h to avoid compiler warning.
+
+2006-04-11 Sergei Organov <osv@javad.com>
+
+ * doc/kernel.sgml: Fix typo
+
+2006-04-10 Sergei Organov <osv@javad.com>
+
+ Implement FIFO variant of scheduling of DSRs and make it the
+ default. This is reworked patch originally suggested by Stefan
+ Sommerfeld <sommerfeld@mikrom.com>.
+
+ * cdl/interrupts.cdl (CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST): make it
+ cdl_component.
+ * cdl/interrupts.cdl (CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO):
+ new option for CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST.
+ * include/intr.hxx (class Cyg_Interrupt): new static variable
+ dsr_list_tail.
+ * src/intr/intr.cxx (call_pending_DSRs_inner): add
+ CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO variant.
+ (post_dsr): likewise.
+ * tests/intr0.cxx: fix comments to match actual option names.
+ * tests/kintr0.c: likewise.
+
+2006-03-27 Marco Cruz <marco@daruma.com.br>
+
+ * include/thread.hxx: removed extra qualifier of
+ Cyg_Thread::reinitialize() to permit compile on gcc 4.1.0
+ * include/sched.hxx: removed extra qualifier of
+ Cyg_Scheduler::thread_entry to permit compile on gcc 4.1.0
+
+2006-02-14 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * tests/timeslice.c (STACK_SIZE): Reduce the stack size so it will
+ compile on targets wit h only small amounts of RAM.
+ * tests/fptest.c: Calculate the size of ftp2_values array to fit
+ the amount of RAM in small systems.
+ * tests/clocktruth.cxx: Fix the header.
+
+2006-01-19 Nick Garnett <nickg@ecoscentric.com>
+
+ * src/sched/sched.cxx (thread_entry): Fixed a bug which could
+ cause a thread to be started with a non-zero scheduler lock. The
+ previous code only decremented it by 1 so if the previous thread
+ was executing with the lock > 1 the thread ended up with a
+ non-zero lock. This is fixed by decrementing the lock in a loop
+ until it reaches zero.
+
+ * src/common/thread.cxx (idle_thread_main): Added an assert for a
+ non-zero scheduler lock.
+
+2006-01-10 Nick Garnett <nickg@ecoscentric.com>
+
+ * src/sched/sched.cxx:
+ * include/sched.hxx (class Cyg_Scheduler): Added thread_entry()
+ member function. This handles thread startup housekeeping. Zeroing
+ the scheduler lock is handled by calling unlock() so that DSRs may
+ be run.
+
+ * src/common/thread.cxx (thread_entry): Refactored code to call
+ Cyg_Scheduler::thread_entry() instead of doing all the work here.
+
+2005-11-23 Sergei Organov <osv@javad.com>
+
+ * doc/kernel.sgml: Fix description of CYG_ISR_CALL_DSR and
+ CYG_ISR_HANDLED. Fix example isr_function() accordingly.
+
+2005-10-23 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * include/flag.hxx: We need thread.inl for the empty() function
+ implementation which the compiler wants to inline.
+
2005-08-03 Andrew Lunn <andrew.lunn@ascom.ch>
* tests/ksem1.c: Type fix to fix a compiler warning.
# NOTE: the choice of list vs table should not be two separate
# options. There is a single option which must have one of
# two legal values.
- cdl_option CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST {
+ cdl_component CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST {
display "Use linked lists for DSRs"
default_value 1
implements CYGINT_KERNEL_INTERRUPTS_DSRS
requires that the kernel disable interrupts for a very short
period of time outside interrupt handlers, but there is no
possibility of a table overflow occurring."
+
+ cdl_option CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO {
+ display "Schedule DSRs in FIFO order"
+ flavor bool
+ default_value 1
+ description "When this option is set, DSRs are scheduled
+ in the natural FIFO (first in, first out) order,
+ otherwise they are scheduled in LIFO (last in, first
+ out) order. Applications should not rely on any
+ particular order of scheduling of DSRs. LIFO
+ scheduling is kept for backward compatibility only and
+ is not recommended as it may lead to high (up to 2
+ times higher then FIFO) IRQ-to-DSR latencies at some
+ (typically rare) conditions. If unsure, leave this set."
+ }
+
}
cdl_component CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE {
no_define
calculated {
"tests/bin_sem0 tests/bin_sem1 tests/bin_sem2 tests/bin_sem3 tests/clock0 tests/clock1 tests/clockcnv tests/clocktruth tests/cnt_sem0 tests/cnt_sem1 tests/except1 tests/flag0 tests/flag1 tests/intr0 tests/kill tests/mbox1 tests/mqueue1 tests/mutex0 tests/mutex1 tests/mutex2 tests/mutex3 tests/release tests/sched1 tests/sync2 tests/sync3 tests/thread0 tests/thread1 tests/thread2"
- . ((CYGFUN_KERNEL_API_C) ? " tests/kclock0 tests/kclock1 tests/kexcept1 tests/kflag0 tests/kflag1 tests/kintr0 tests/klock tests/kmbox1 tests/kmutex0 tests/kmutex1 tests/kmutex3 tests/kmutex4 tests/ksched1 tests/ksem0 tests/ksem1 tests/kthread0 tests/kthread1 tests/stress_threads tests/thread_gdb tests/timeslice tests/tm_basic tests/fptest tests/kalarm0" : "")
+ . ((CYGFUN_KERNEL_API_C) ? " tests/kclock0 tests/kclock1 tests/kexcept1 tests/kflag0 tests/kflag1 tests/kintr0 tests/klock tests/kmbox1 tests/kmutex0 tests/kmutex1 tests/kmutex3 tests/kmutex4 tests/ksched1 tests/ksem0 tests/ksem1 tests/kthread0 tests/kthread1 tests/stress_threads tests/thread_gdb tests/timeslice tests/timeslice2 tests/tm_basic tests/fptest tests/kalarm0" : "")
. ((!CYGPKG_INFRA_DEBUG && !CYGPKG_KERNEL_INSTRUMENT && CYGFUN_KERNEL_API_C) ? " tests/dhrystone" : "")
. ((CYGPKG_KERNEL_SMP_SUPPORT && CYGFUN_KERNEL_API_C) ? " tests/smp" : "")
. ((!CYGINT_HAL_TESTS_NO_CACHES && CYGFUN_KERNEL_API_C) ? " tests/kcache1 tests/kcache2" : "")
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2006 eCosCentric Ltd.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
-##
-## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
}
+cdl_option CYGIMP_MBOX_USE_MBOXT_PLAIN {
+ display "Use mboxt_plain mbox implementation"
+ default_value 1
+ description "
+ Use the plain mboxt implementation instead of the mboxt2
+ implementation. The mboxt2 version is designed to provide
+ semantics compatible with UITRON, the plain implementation
+ is adquate in most other situations."
+}
+
cdl_option CYGMFN_KERNEL_SYNCH_MBOXT_PUT_CAN_WAIT {
display "Message box blocking put support"
doc ref/kernel-mail-boxes.html
…
cyg_thread_create( …,
&fred::static_thread_aux,
- static_cast<cyg_addrword_t>(&instance),
+ reinterpret_cast<cyg_addrword_t>(&instance),
…);
…
}
…
- return dsr_required ? CYG_ISR_CALL_DSR : CYG_ISR_HANDLED;
+ return dsr_required ?
+ (CYG_ISR_CALL_DSR | CYG_ISR_HANDLED) :
+ CYG_ISR_HANDLED;
}
</programlisting>
<para>
are especially important, so their ISRs will be as short as possible.
</para>
<para>
-The return value of an ISR is normally one of
-<literal>CYG_ISR_CALL_DSR</literal> or
+The return value of an ISR is normally a bit mask containing zero, one
+or both of the following bits: <literal>CYG_ISR_CALL_DSR</literal> or
<literal>CYG_ISR_HANDLED</literal>. The former indicates that further
processing is required at DSR level, and the interrupt handler's DSR
will be run as soon as possible. The latter indicates that the
-interrupt has been fully handled and no further effort is required.
+interrupt was handled by this ISR so there is no need to call other
+interrupt handlers which might be chained on this interrupt vector. If
+this ISR did not handle the interrupt it should not set the
+CYG_ISR_HANDLED bit so that other chained interrupt handlers may
+handle the interrupt.
</para>
<para>
An ISR is allowed to make very few kernel calls. It can manipulate the
<term>cyg_DSR_t <parameter>dsr</parameter></term>
<listitem><para>
If an interrupt has occurred and the ISR has returned a value
-<literal>CYG_ISR_CALL_DSR</literal>, the system will call the
-deferred service routine or DSR associated with this interrupt
+with <literal>CYG_ISR_CALL_DSR</literal> bit being set, the system
+will call the DSR associated with this interrupt
handler. If the scheduler is not currently locked then the DSR will
run immediately. However if the interrupted thread was in the middle
of a kernel call and had locked the scheduler, then the DSR will be
-
#include <pkgconf/kernel.h>
#include <cyg/kernel/ktypes.h> // base kernel types
#include <cyg/kernel/instrmnt.h>
#ifdef CYGDBG_KERNEL_INSTRUMENT_MSGS
#define CYGDBG_KERNEL_INSTRUMENT_MSGS_DEFINE_TABLE
#include <cyg/kernel/instrument_desc.h>
-#define NELEM(x) (sizeof(x)/sizeof*(x))
+
externC char * cyg_instrument_msg(CYG_WORD16 type) {
struct instrument_desc_s *record;
CYG_WORD cl, event;
record = instrument_desc;
- end_record = &instrument_desc[NELEM(instrument_desc)-1];
+ end_record = &instrument_desc[CYG_NELEM(instrument_desc)-1];
cl = type & 0xff00;
event = type & 0x00ff;
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2006 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// These are not applicable in a bitmap scheduler; placeholders:
inline void rotate_queue( cyg_priority pri ) { };
inline void to_queue_head( void ) { };
+
+ inline void timeslice_save() {};
+ inline void timeslice_restore() {};
+ inline void timeslice_reset() {};
+
};
// -------------------------------------------------------------------------
#include <cyg/infra/cyg_ass.h> // assertion macros
#include <cyg/kernel/thread.hxx> // Cyg_Thread
+#include <cyg/kernel/thread.inl> // queue implementation
// -------------------------------------------------------------------------
// Flag object. This class implements a queue of threads waiting for a
// next DSR in list
Cyg_Interrupt* volatile next_dsr CYGBLD_ANNOTATE_VARIABLE_INTR;
- // static list of pending DSRs
+ // head of static list of pending DSRs
static Cyg_Interrupt* volatile dsr_list[CYGNUM_KERNEL_CPU_MAX]
CYGBLD_ANNOTATE_VARIABLE_INTR;
-
-#endif
+
+# ifdef CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO
+ // tail of static list of pending DSRs
+ static Cyg_Interrupt* volatile dsr_list_tail[CYGNUM_KERNEL_CPU_MAX]
+ CYGBLD_ANNOTATE_VARIABLE_INTR;
+# endif
+
+#endif // defined CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
#ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN
# define CYG_SCHEDTHREAD_CPU_MEMBER
#endif
+#ifdef CYGSEM_KERNEL_SCHED_TIMESLICE
+# define CYG_SCHEDTHREAD_TIMESLICE_MEMBER \
+ cyg_ucount32 timeslice_count; /* per-thread timeslice counter */
+#else
+# define CYG_SCHEDTHREAD_TIMESLICE_MEMBER
+#endif
+
#ifdef CYGSEM_KERNEL_SCHED_TIMESLICE_ENABLE
# define CYG_SCHEDTHREAD_TIMESLICE_ENABLED_MEMBER \
cyg_bool timeslice_enabled; /* per-thread timeslice enable */
cyg_thread *prev; \
cyg_priority_t priority; /* current thread priority */ \
CYG_SCHEDTHREAD_CPU_MEMBER \
+ CYG_SCHEDTHREAD_TIMESLICE_MEMBER \
CYG_SCHEDTHREAD_TIMESLICE_ENABLED_MEMBER
#elif defined(CYGSEM_KERNEL_SCHED_LOTTERY)
# define CYG_SCHEDTHREAD_SCHEDIMP_MEMBERS \
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2006 eCosCentric Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
CYG_INSTRUMENT_MBOXT(WAIT, this, count);
+ CYG_ASSERTCLASS( this, "Bad this pointer");
+
// Allow other threads to run
Cyg_Scheduler::reschedule();
- CYG_ASSERTCLASS( this, "Bad this pointer");
-
switch( self->get_wake_reason() )
{
case Cyg_Thread::DESTRUCT:
#endif
}
+ CYG_ASSERTCLASS( this, "Bad this pointer");
+
// Unlock the scheduler and maybe switch threads
Cyg_Scheduler::unlock();
- CYG_ASSERTCLASS( this, "Bad this pointer");
CYG_REPORT_RETVAL( result );
return result;
}
get_threadq.enqueue( self );
CYG_INSTRUMENT_MBOXT(WAIT, this, count);
-
+
// Allow other threads to run
Cyg_Scheduler::reschedule();
#endif
}
+ CYG_ASSERTCLASS( this, "Bad this pointer");
+
// Unlock the scheduler and maybe switch threads
Cyg_Scheduler::unlock();
- CYG_ASSERTCLASS( this, "Bad this pointer");
CYG_REPORT_RETVAL( result );
return result;
}
{
CYG_REPORT_FUNCTION();
- CYG_ASSERTCLASS( this, "Bad this pointer");
-
// Prevent preemption
Cyg_Scheduler::lock();
+ CYG_ASSERTCLASS( this, "Bad this pointer");
+
CYG_INSTRUMENT_MBOXT(TRY, this, count);
cyg_bool result = ( 0 < count );
{
CYG_REPORT_FUNCTION();
- CYG_ASSERTCLASS( this, "Bad this pointer");
-
// Prevent preemption
Cyg_Scheduler::lock();
+ CYG_ASSERTCLASS( this, "Bad this pointer");
+
CYG_INSTRUMENT_MBOXT(TRY, this, count);
cyg_bool result = ( 0 < count );
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2006 eCosCentric Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
wakeup_putter();
#endif
+ CYG_ASSERTCLASS( this, "Bad this pointer");
+
// Unlock the scheduler and definitely switch threads
Cyg_Scheduler::unlock();
- CYG_ASSERTCLASS( this, "Bad this pointer");
CYG_REPORT_RETVAL( true );
return true;
}
get_threadq.enqueue( self );
CYG_INSTRUMENT_MBOXT(WAIT, this, count);
-
+
+ CYG_ASSERTCLASS( this, "Bad this pointer");
+
// Unlock scheduler and allow other threads to run
Cyg_Scheduler::unlock_reschedule();
default:
break;
}
- CYG_ASSERTCLASS( this, "Bad this pointer");
+
CYG_REPORT_RETVAL( result );
return result;
}
wakeup_putter();
#endif
+ CYG_ASSERTCLASS( this, "Bad this pointer");
+
// Unlock the scheduler and maybe switch threads
Cyg_Scheduler::unlock();
- CYG_ASSERTCLASS( this, "Bad this pointer");
CYG_REPORT_RETVAL( true );
return true;
}
CYG_INSTRUMENT_MBOXT(WAIT, this, count);
}
+ CYG_ASSERTCLASS( this, "Bad this pointer");
+
// Unlock scheduler and allow other threads to run
Cyg_Scheduler::unlock_reschedule();
// clear the timer; if it actually fired, no worries.
self->clear_timer();
- CYG_ASSERTCLASS( this, "Bad this pointer");
-
cyg_bool result = true;
switch( self->get_wake_reason() )
{
{
CYG_REPORT_FUNCTION();
- CYG_ASSERTCLASS( this, "Bad this pointer");
-
// Prevent preemption
Cyg_Scheduler::lock();
+ CYG_ASSERTCLASS( this, "Bad this pointer");
+
CYG_INSTRUMENT_MBOXT(TRY, this, count);
cyg_bool result = ( 0 < count );
{
CYG_REPORT_FUNCTION();
- CYG_ASSERTCLASS( this, "Bad this pointer");
-
// Prevent preemption
Cyg_Scheduler::lock();
+ CYG_ASSERTCLASS( this, "Bad this pointer");
+
CYG_INSTRUMENT_MBOXT(TRY, this, count);
cyg_bool result = ( 0 < count );
CYG_INSTRUMENT_MBOXT(WAIT, this, count);
+ CYG_ASSERTCLASS( this, "Bad this pointer");
+
// when this returns, our item is in the queue.
Cyg_Scheduler::unlock_reschedule(); // unlock, switch threads
- CYG_ASSERTCLASS( this, "Bad this pointer");
-
cyg_bool result = true;
switch( self->get_wake_reason() )
{
if ( !get_threadq.empty() ) {
wakeup_winner( item );
- Cyg_Scheduler::unlock(); // unlock, maybe switch threads
CYG_ASSERTCLASS( this, "Bad this pointer");
+ Cyg_Scheduler::unlock(); // unlock, maybe switch threads
CYG_REPORT_RETVAL( true );
return true;
}
CYG_INSTRUMENT_MBOXT(WAIT, this, count);
}
+ CYG_ASSERTCLASS( this, "Bad this pointer");
+
// when this returns, our item is in the queue.
Cyg_Scheduler::unlock_reschedule(); // unlock, switch threads
break;
}
- CYG_ASSERTCLASS( this, "Bad this pointer");
CYG_REPORT_RETVAL( result );
return result;
}
if ( !get_threadq.empty() ) {
wakeup_winner( item );
- Cyg_Scheduler::unlock(); // unlock, maybe switch threads
CYG_ASSERTCLASS( this, "Bad this pointer");
+ Cyg_Scheduler::unlock(); // unlock, maybe switch threads
CYG_REPORT_RETVAL( true );
return true;
}
itemqueue[ in ] = item;
+ CYG_ASSERTCLASS( this, "Bad this pointer");
+
// Unlock the scheduler and maybe switch threads
Cyg_Scheduler::unlock();
- CYG_ASSERTCLASS( this, "Bad this pointer");
CYG_REPORT_RETVAL( true );
return true;
}
static cyg_ucount32 timeslice_count[CYGNUM_KERNEL_CPU_MAX]
CYGBLD_ANNOTATE_VARIABLE_SCHED;
- static void reset_timeslice_count();
-
#endif
Cyg_Scheduler_Implementation(); // Constructor
need_reschedule[CYG_KERNEL_CPU_THIS()] = true;
}
-#ifdef CYGSEM_KERNEL_SCHED_TIMESLICE
-
-inline void Cyg_Scheduler_Implementation::reset_timeslice_count()
-{
- timeslice_count[CYG_KERNEL_CPU_THIS()] = CYGNUM_KERNEL_SCHED_TIMESLICE_TICKS;
-}
-
-#endif
// -------------------------------------------------------------------------
// Scheduler thread implementation.
// of its queue (not necessarily
// a scheduler queue)
+#ifdef CYGSEM_KERNEL_SCHED_TIMESLICE
+
+ cyg_ucount32 timeslice_count;
+
+ void timeslice_save();
+
+ void timeslice_restore();
+
+ void timeslice_reset();
+
#ifdef CYGSEM_KERNEL_SCHED_TIMESLICE_ENABLE
// This defines whether this thread is subject to timeslicing.
void timeslice_disable();
+#endif
+
+#else
+
+ inline void timeslice_save() {};
+ inline void timeslice_restore() {};
+ inline void timeslice_reset() {};
+
#endif
};
// -------------------------------------------------------------------------
// Cyg_SchedThread_Implementation inlines.
+#ifdef CYGSEM_KERNEL_SCHED_TIMESLICE
+
+inline void Cyg_SchedThread_Implementation::timeslice_save()
+{
+ timeslice_count = Cyg_Scheduler_Implementation::timeslice_count[CYG_KERNEL_CPU_THIS()];
+}
+
+inline void Cyg_SchedThread_Implementation::timeslice_restore()
+{
+ Cyg_Scheduler_Implementation::timeslice_count[CYG_KERNEL_CPU_THIS()] = timeslice_count;
+}
+
+inline void Cyg_SchedThread_Implementation::timeslice_reset()
+{
+ timeslice_count = CYGNUM_KERNEL_SCHED_TIMESLICE_TICKS;
+}
+
#ifdef CYGSEM_KERNEL_SCHED_TIMESLICE_ENABLE
inline void Cyg_SchedThread_Implementation::timeslice_enable()
#endif
+#endif
+
// -------------------------------------------------------------------------
#endif // ifndef CYGONCE_KERNEL_MLQUEUE_HXX
// release the preemption lock without rescheduling
static void unlock_simple();
+
+ // perform thread startup housekeeping
+ void thread_entry( Cyg_Thread *thread );
// Start execution of the scheduler
static void start() CYGBLD_ATTRIB_NORET;
);
// Re-initialize the thread back to it's initial state.
- void Cyg_Thread::reinitialize();
+ void reinitialize();
~Cyg_Thread();
{
CYG_REPORT_FUNCTION();
- Cyg_Scheduler::scheduler.clear_need_reschedule(); // finished rescheduling
- Cyg_Scheduler::scheduler.set_current_thread(thread); // restore current thread pointer
-
- CYG_INSTRUMENT_THREAD(ENTER,thread,0);
-
-#ifdef CYGSEM_KERNEL_SCHED_TIMESLICE
- // Reset the timeslice counter so that this thread gets a full
- // quantum.
- Cyg_Scheduler::reset_timeslice_count();
-#endif
+ // Call the scheduler to do any housekeeping
+ Cyg_Scheduler::scheduler.thread_entry( thread );
- // Zero the lock
- HAL_REORDER_BARRIER (); // Prevent the compiler from moving
- Cyg_Scheduler::zero_sched_lock(); // the assignment into the code above.
- HAL_REORDER_BARRIER();
-
// Call entry point in a loop.
-
for(;;)
{
thread->entry_point(thread->entry_data);
# endif // CYGNUM_KERNEL_THREADS_IDLE_STACK_SIZE
#endif // CYGNUM_HAL_STACK_SIZE_MINIMUM
-static char idle_thread_stack[CYGNUM_KERNEL_CPU_MAX][CYGNUM_KERNEL_THREADS_IDLE_STACK_SIZE];
-
// Loop counter for debugging/housekeeping
cyg_uint32 idle_thread_loops[CYGNUM_KERNEL_CPU_MAX];
+static char idle_thread_stack[CYGNUM_KERNEL_CPU_MAX][CYGNUM_KERNEL_THREADS_IDLE_STACK_SIZE];
+
// -------------------------------------------------------------------------
// Idle thread code.
HAL_IDLE_THREAD_ACTION(idle_thread_loops[CYG_KERNEL_CPU_THIS()]);
+ CYG_ASSERT( Cyg_Scheduler::get_sched_lock() == 0, "Scheduler lock not zero" );
#if 0
// For testing, it is useful to be able to fake
// clock interrupts in the idle thread.
: Cyg_Thread( CYG_THREAD_MIN_PRIORITY,
idle_thread_main,
0,
- "Idle Thread",
+ (char *)"Idle Thread",
(CYG_ADDRESS)idle_thread_stack[this-&idle_thread[0]],
CYGNUM_KERNEL_THREADS_IDLE_STACK_SIZE)
{
char buf[16];
char sign = '+';
cyg_count8 bpos;
- char *digits = "0123456789ABCDEF";
+ char *digits = (char *)"0123456789ABCDEF";
if( n < 0 ) n = -n, sign = '-';
if( thread->get_state() & Cyg_Thread::SUSPENDED )
{
- sbp = dbg_addstr( sbp, "suspended+");
+ sbp = dbg_addstr( sbp, (char *)"suspended+");
}
switch( thread->get_state() & ~Cyg_Thread::SUSPENDED )
{
case Cyg_Thread::RUNNING:
if ( Cyg_Scheduler::get_current_thread() == thread ) {
- s = "running"; break;
+ s = (char *)"running"; break;
}
else if ( thread->get_state() & Cyg_Thread::SUSPENDED ) {
- s = ""; sbp--; /*kill '+'*/ break;
+ s = (char *)""; sbp--; /*kill '+'*/ break;
}
else {
- s = "ready"; break;
+ s = (char *)"ready"; break;
}
case Cyg_Thread::SLEEPING:
- s = "sleeping"; break;
+ s = (char *)"sleeping"; break;
case Cyg_Thread::COUNTSLEEP | Cyg_Thread::SLEEPING:
case Cyg_Thread::COUNTSLEEP:
- s = "counted sleep"; break;
+ s = (char *)"counted sleep"; break;
case Cyg_Thread::CREATING:
- s = "creating"; sbp = statebuf; break;
+ s = (char *)"creating"; sbp = statebuf; break;
case Cyg_Thread::EXITED:
- s = "exited"; sbp = statebuf; break;
+ s = (char *)"exited"; sbp = statebuf; break;
default:
- s = "unknown state"; break;
+ s = (char *)"unknown state"; break;
}
sbp = dbg_addstr( sbp, s );
- sbp = dbg_addstr( sbp, ", Priority: " );
+ sbp = dbg_addstr( sbp, (char *)", Priority: " );
sbp = dbg_adddec( sbp, thread->get_priority() );
info->thread_display = statebuf;
#ifdef CYGDBG_KERNEL_INSTRUMENT_MSGS
#define CYGDBG_KERNEL_INSTRUMENT_MSGS_DEFINE_TABLE
#include <cyg/kernel/instrument_desc.h>
-#define NELEM(x) (sizeof(x)/sizeof*(x))
+
externC char * cyg_instrument_msg(CYG_WORD16 type) {
struct instrument_desc_s *record;
CYG_WORD cl, event;
record = instrument_desc;
- end_record = &instrument_desc[NELEM(instrument_desc)-1];
+ end_record = &instrument_desc[CYG_NELEM(instrument_desc)-1];
cl = type & 0xff00;
event = type & 0x00ff;
Cyg_Interrupt* volatile Cyg_Interrupt::dsr_list[CYGNUM_KERNEL_CPU_MAX];
+# ifdef CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO
+Cyg_Interrupt* volatile Cyg_Interrupt::dsr_list_tail[CYGNUM_KERNEL_CPU_MAX];
+# endif
+
#endif
// -------------------------------------------------------------------------
#ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
+# ifdef CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO
+
+ cyg_uint32 old_intr;
+ HAL_DISABLE_INTERRUPTS(old_intr);
+ Cyg_Interrupt* intr = dsr_list[cpu];
+ CYG_ASSERT(intr != 0, "No DSRs are pended");
+ dsr_list[cpu] = 0;
+ dsr_list_tail[cpu] = 0;
+ while(true)
+ {
+ cyg_count32 count = intr->dsr_count;
+ Cyg_Interrupt* next = intr->next_dsr;
+ intr->dsr_count = 0;
+ intr->next_dsr = 0;
+ HAL_RESTORE_INTERRUPTS(old_intr);
+
+ CYG_ASSERT(intr->dsr != 0, "No DSR defined");
+ CYG_ASSERT(count > 0, "DSR posted but post count is zero");
+ intr->dsr(intr->vector, count, (CYG_ADDRWORD)intr->data);
+
+ if (!next)
+ break;
+
+ intr = next;
+ HAL_DISABLE_INTERRUPTS(old_intr);
+ }
+
+# else // ! defined CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO
+
while( dsr_list[cpu] != NULL )
{
Cyg_Interrupt* intr;
}
-#endif
-
+# endif // ! defined CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO
+
+#endif // defined CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
+
};
externC void
// Only add the interrupt to the dsr list if this is
// the first DSR call.
- // At present DSRs are pushed onto the list and will be
- // called in reverse order. We do not define the order
- // in which DSRs are called, so this is acceptable.
-
if( dsr_count++ == 0 )
{
+# ifdef CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO
+
+ // Add to the tail of the list.
+ Cyg_Interrupt* tail = dsr_list_tail[cpu];
+ dsr_list_tail[cpu] = this;
+ if( tail )
+ {
+ CYG_ASSERT( 0 != dsr_list[cpu] ,
+ "DSR list is not empty but its head is 0");
+ tail->next_dsr = this;
+ }
+ else
+ {
+ CYG_ASSERT( 0 == dsr_list[cpu] ,
+ "DSR list tail is 0 but its head is not");
+ dsr_list[cpu] = this;
+ }
+
+# else // ! defined CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO
+
+ // At present DSRs are pushed onto the list and will be called
+ // in reverse order. We do not define the order in which DSRs
+ // are called, so this is acceptable.
next_dsr = dsr_list[cpu];
dsr_list[cpu] = this;
+
+# endif // ! defined CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO
+
}
-
-#endif
+
+#endif // defined CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
HAL_RESTORE_INTERRUPTS(old_intr);
};
// current thread, request a reschedule.
set_need_reschedule(thread);
+
+ // Also reset the timeslice_count so that this thread gets a full
+ // timeslice once it begins to run.
+
+ thread->timeslice_reset();
#ifdef CYGPKG_KERNEL_SMP_SUPPORT
if( queue->get_head() != thread )
sched->set_need_reschedule();
+ else
+ {
+ // Reset the timeslice counter so that this thread gets a
+ // full quantum as a reward for yielding when it is
+ // eventually rescheduled.
+ thread->timeslice_reset();
+ }
-#ifdef CYGSEM_KERNEL_SCHED_TIMESLICE
- // Reset the timeslice counter so that this thread gets a full
- // quantum.
- else Cyg_Scheduler::reset_timeslice_count();
-#endif
}
// Unlock the scheduler and switch threads
#ifdef CYGFUN_KERNEL_THREADS_STACK_CHECKING
next->check_stack(); // before running it
#endif
-
+ current->timeslice_save();
+
// Switch contexts
HAL_THREAD_SWITCH_CONTEXT( ¤t->stack_ptr,
&next->stack_ptr );
CYG_ASSERTCLASS( current, "Bad current thread" );
current_thread[CYG_KERNEL_CPU_THIS()] = current; // restore current thread pointer
- }
-#ifdef CYGSEM_KERNEL_SCHED_TIMESLICE
- // Reset the timeslice counter so that this thread gets a full
- // quantum.
- reset_timeslice_count();
-#endif
+ current->timeslice_restore();
+ }
clear_need_reschedule(); // finished rescheduling
}
CYG_FAIL( "Should not be executed" );
}
+// -------------------------------------------------------------------------
+// Thread startup. This is called from Cyg_Thread::thread_entry() and
+// performs some housekeeping for a newly started thread.
+
+void Cyg_Scheduler::thread_entry( Cyg_Thread *thread )
+{
+ clear_need_reschedule(); // finished rescheduling
+ set_current_thread(thread); // restore current thread pointer
+
+ CYG_INSTRUMENT_THREAD(ENTER,thread,0);
+
+ thread->timeslice_reset();
+ thread->timeslice_restore();
+
+ // Finally unlock the scheduler. As well as clearing the scheduler
+ // lock this allows any pending DSRs to execute. The new thread
+ // must start with a lock of zero, so we keep unlocking until the
+ // lock reaches zero.
+ while( get_sched_lock() != 0 )
+ unlock();
+}
+
// -------------------------------------------------------------------------
// Start the scheduler. This is called after the initial threads have been
// created to start scheduling. It gets any other CPUs running, and then
void *
Cyg_Mbox::get()
{
- void * p;
+ void * p=NULL;
if ( ! m.get( p ) )
return NULL;
return p;
void *
Cyg_Mbox::get( cyg_tick_count timeout )
{
- void * p;
+ void * p=NULL;
if ( ! m.get( p, timeout ) )
return NULL;
return p;
//
// clocktruth.cxx
//
-// Clock Converter test
+// Clock accuracy test
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
#include <cyg/infra/diag.h>
//#include <cyg/kernel/test/stackmon.h>
-//#include CYGHWR_MEMORY_LAYOUT_H
+#include CYGHWR_MEMORY_LAYOUT_H
//==========================================================================
}
//==========================================================================
-
+#if (CYGMEM_REGION_ram_SIZE / 8 / 2) < 10000
+#define FP2_COUNT (CYGMEM_REGION_ram_SIZE / 8 / 2)
+#else
#define FP2_COUNT 10000
+#endif
static double fpt2_values[FP2_COUNT];
// Description: Very basic test of interrupt objects
// Options:
// CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE
-// CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE
+// CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE
// CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
+// CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO
//####DESCRIPTIONEND####
#include <pkgconf/kernel.h>
#include "testaux.hxx"
+#ifdef HAL_INTR_TEST_PRIO_A
+# define PRIO_A HAL_INTR_TEST_PRIO_A
+#else
+# define PRIO_A 0
+#endif
+
+#ifdef HAL_INTR_TEST_PRIO_B
+# define PRIO_B HAL_INTR_TEST_PRIO_B
+#else
+# define PRIO_B 1
+#endif
+
+#ifdef HAL_INTR_TEST_PRIO_C
+# define PRIO_C HAL_INTR_TEST_PRIO_C
+#else
+# define PRIO_C 1
+#endif
+
static cyg_ISR isr0, isr1;
static cyg_DSR dsr0, dsr1;
static bool flash( void )
{
- Cyg_Interrupt intr0 = Cyg_Interrupt(CYGNUM_HAL_ISR_MIN, 0, (CYG_ADDRWORD)333, isr0, dsr0 );
+ Cyg_Interrupt intr0 = Cyg_Interrupt(CYGNUM_HAL_ISR_MIN, PRIO_A,
+ (CYG_ADDRWORD)333, isr0, dsr0 );
return true;
}
HAL_INTERRUPT_IN_USE( lvl1, in_use );
Cyg_Interrupt* intr0 = NULL;
if (!in_use)
- intr0 = new((void *)&intr0_obj[0]) Cyg_Interrupt( lvl1, 1, (CYG_ADDRWORD)777, isr0, dsr0 );
+ intr0 = new((void *)&intr0_obj[0]) Cyg_Interrupt( lvl1, PRIO_B, (CYG_ADDRWORD)777, isr0, dsr0 );
cyg_vector lvl2 = CYGNUM_HAL_ISR_MIN + ( 15 % CYGNUM_HAL_ISR_COUNT);
HAL_INTERRUPT_IN_USE( lvl2, in_use );
Cyg_Interrupt* intr1 = NULL;
if (!in_use && lvl1 != lvl2)
- intr1 = new((void *)&intr1_obj[0]) Cyg_Interrupt( lvl2, 1, 888, isr1, dsr1 );
+ intr1 = new((void *)&intr1_obj[0]) Cyg_Interrupt( lvl2, PRIO_C, 888, isr1, dsr1 );
// Check these functions at least exist
Cyg_Interrupt::disable_interrupts();
// Description: Very basic test of interrupt objects
// Options:
// CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE
-// CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE_MAX
+// CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE
// CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
+// CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO
//####DESCRIPTIONEND####
*/
#include "testaux.h"
+#ifdef HAL_INTR_TEST_PRIO_A
+# define PRIO_A HAL_INTR_TEST_PRIO_A
+#else
+# define PRIO_A 0
+#endif
+
+#ifdef HAL_INTR_TEST_PRIO_B
+# define PRIO_B HAL_INTR_TEST_PRIO_B
+#else
+# define PRIO_B 1
+#endif
+
+#ifdef HAL_INTR_TEST_PRIO_C
+# define PRIO_C HAL_INTR_TEST_PRIO_C
+#else
+# define PRIO_C 1
+#endif
+
static cyg_interrupt intr_obj[2];
static cyg_handle_t intr0, intr1;
cyg_handle_t handle;
cyg_interrupt intr;
- cyg_interrupt_create(CYGNUM_HAL_ISR_MIN, 0, (cyg_addrword_t)333,
+ cyg_interrupt_create(CYGNUM_HAL_ISR_MIN, PRIO_A, (cyg_addrword_t)333,
isr0, dsr0, &handle, &intr );
cyg_interrupt_delete(handle);
HAL_INTERRUPT_IN_USE( lvl1, in_use );
intr0 = 0;
if (!in_use)
- cyg_interrupt_create(lvl1, 1, (cyg_addrword_t)777, isr0, dsr0,
- &intr0, &intr_obj[0]);
+ cyg_interrupt_create(lvl1, PRIO_B, (cyg_addrword_t)777,
+ isr0, dsr0, &intr0, &intr_obj[0]);
HAL_INTERRUPT_IN_USE( lvl2, in_use );
intr1 = 0;
if (!in_use && lvl1 != lvl2)
- cyg_interrupt_create(lvl2, 1, 888, isr1, dsr1, &intr1, &intr_obj[1]);
+ cyg_interrupt_create(lvl2, PRIO_C, 888,
+ isr1, dsr1, &intr1, &intr_obj[1]);
// Check these functions at least exist
mbret = cyg_mbox_get( mbh );
CYG_TEST_CHECK( mbret == (void *)0xAAAAAAAA , "bad result from cyg_mbox_timed_get()");
thread0_state = 10;
+
+ while( thread1_state < 10 ) cyg_thread_yield();
cyg_mbox_put( mbh, (void *)0xBBBBBBBB );
thread0_state = 11;
#endif
thread1_state = 10;
+ while( thread0_state < 10 ) cyg_thread_yield();
+
#ifdef CYGFUN_KERNEL_THREADS_TIMER
mbret = cyg_mbox_timed_get( mbh, cyg_current_time()+10);
#else
mbret = cyg_mbox_get( mbh );
#endif
+ thread1_state = 11;
CYG_TEST_CHECK( mbret == (void *)0xBBBBBBBB , "bad result from cyg_mbox[_timed]_get()");
- thread1_state = 9;
+ thread1_state = 12;
}
#endif
// --------------------------------------------------
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2006 eCosCentric Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
(void *)stack[0], STACKSIZE, &thread[0], &thread_obj[0]);
cyg_thread_resume(thread[0]);
- cyg_thread_create(4, entry1 , (cyg_addrword_t)1, "kmbox1-1",
+ cyg_thread_create(5, entry1 , (cyg_addrword_t)1, "kmbox1-1",
(void *)stack[1], STACKSIZE, &thread[1], &thread_obj[1]);
cyg_thread_resume(thread[1]);
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2006 eCosCentric Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
{
cyg_count8 u,i;
+ Cyg_Thread::self()->set_priority(4);
+
CYG_TEST_INFO("Testing put() and tryput() without wakeup");
CYG_TEST_CHECK(!m0.waiting_to_get(), "mbox not initialized properly");
CYG_TEST_CHECK(0==m0.peek(), "mbox not initialized properly");
static void entry1( CYG_ADDRWORD data )
{
cyg_count8 i;
+
+ Cyg_Thread::self()->set_priority(5);
+
i = (cyg_count8)m1.get();
CYG_TEST_CHECK(1==q++, "bad synchronization");
m0.PUT((void *)3); // wake t0
#include <stdio.h>
#include <stdlib.h>
+#include <string.h>
#if defined(CYGPKG_LIBM)
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2006 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//==========================================================================
-#define STACK_SIZE CYGNUM_HAL_STACK_SIZE_TYPICAL*5
+#define STACK_SIZE CYGNUM_HAL_STACK_SIZE_TYPICAL
#define NTHREADS_MAX (CYGNUM_KERNEL_CPU_MAX*6)
cyg_start( void )
{
CYG_TEST_INIT();
- CYG_TEST_INFO("SMP test requires:\n"
+ CYG_TEST_INFO("Timeslice test requires:\n"
"CYGSEM_KERNEL_SCHED_TIMESLICE &&\n"
- "CYGPKG_KERNEL_SMP_SUPPORT &&\n"
"CYGFUN_KERNEL_API_C && \n"
"CYGSEM_KERNEL_SCHED_MLQUEUE &&\n"
"CYGVAR_KERNEL_COUNTERS_CLOCK &&\n"
- "!CYGPKG_HAL_I386_LINUX &&\n"
"!CYGDBG_INFRA_DIAG_USE_DEVICE &&\n"
"(CYGNUM_KERNEL_SCHED_PRIORITIES > 12)\n");
- CYG_TEST_NA("SMP test requirements");
+ CYG_TEST_NA("Timeslice test requirements");
}
#endif // CYGSEM_KERNEL_SCHED_TIMESLICE etc.
cyg_uint32 end;
} fun_times;
-#define STACK_SIZE CYGNUM_HAL_STACK_SIZE_MINIMUM
+#define STACK_SIZE (CYGNUM_HAL_STACK_SIZE_TYPICAL+4*1024)
#ifdef CYGMEM_REGION_ram_SIZE
#define CYG_THREAD_OVERHEAD (STACK_SIZE+sizeof(cyg_thread)+(sizeof(fun_times)*2))
+2007-07-02 Gary Thomas <gary@mlbassoc.com>
+
+ * src/locale.cxx: Add (char *) casts to make GCC/4.2.x happy.
+
+2006-08-28 Sergei Gavrikov <w3sg@SoftHome.net>
+
+ * src/wcstombs.cxx (wcstombs): unused variable removed.
+
+2006-08-11 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * src/wcstombs.cxx (wcstombs): Previous change should have
+ disregarded 'n'. Now fixed. Thanks to Klaas Gadeyne.
+
+2006-08-10 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * src/wcstombs.cxx (wcstombs): Follow Single Unix Spec
+ and if string is NULL, return chars that would have been
+ returned.
+
2005-07-30 Andrew Lunn <andrew.lunn@ascom.ch>
* tests/i18nmb.c (main): Really silence the warnings.
display "Additional compiler flags"
flavor data
no_define
- default_value { "" }
+ default_value { "-fno-rtti -Woverloaded-virtual" }
description "
This option modifies the set of compiler flags for
building the C library. These flags are used in addition
display "Suppressed compiler flags"
flavor data
no_define
- default_value { "" }
+ default_value { "-Wno-pointer-sign" }
description "
This option modifies the set of compiler flags for
building the C library. These flags are removed from
// define the "C" locale
static const Cyg_libc_locale_t
C_locale = {
- "C",
- { ".", "", "", "", "", "", "", "", "", "",
+ (char *)"C",
+ { (char *)".", (char *)"", (char *)"", (char *)"", (char *)"", (char *)"", (char *)"", (char *)"", (char *)"", (char *)"",
CHAR_MAX, CHAR_MAX, CHAR_MAX, CHAR_MAX, CHAR_MAX, CHAR_MAX,
CHAR_MAX, CHAR_MAX
},
// constants which optimise nicely
cyg_ucount32 size_used;
size_used = (char *)&static_lconv.int_curr_symbol -
- (char *)&static_lconv;
+ (char *)&static_lconv;
memcpy( &(static_lconv.int_curr_symbol),
&(current_monetary_locale->numdata.int_curr_symbol),
RETURNS
This implementation of <<wcstombs>> returns <<0>> if
-<[s]> is <<NULL>> or is the empty string;
+<[s]> is the empty string;
it returns <<-1>> if CYGINT_LIBC_I18N_MB_REQUIRED and one of the
wide-char characters does not represent a valid multi-byte character;
otherwise it returns the minimum of: <<n>> or the
number of bytes that are transferred to <<s>>, not including the
-nul terminator.
+nul terminator. If <[s]> is <<NULL>> it returns the number of
+bytes that would have been transferred, regardless of <<[n]>>.
If the return value is -1, the state of the <<pwc>> string is
indeterminate. If the input has a length of 0, the output
int count = 0;
- if (n != 0) {
- do {
- if ((*s++ = (char) *pwcs++) == 0)
- break;
- count++;
- } while (--n != 0);
+ if (s == NULL) {
+ while (*pwcs++ != 0) {
+ count++;
+ }
+ } else {
+ if (n != 0) {
+ do {
+ if ((*s++ = (char) *pwcs++) == 0)
+ break;
+ count++;
+ } while (--n != 0);
+ }
}
retval = count;
+2007-09-27 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * src/siginit.cxx (cyg_libc_signals_default_handler): Handle case where
+ CYGINT_ISO_EXIT not available.
+
2003-06-26 Jonathan Larmour <jifl@eCosCentric.com>
* include/signal.h: Remove unused definitions that had been used
// CONFIGURATION
#include <pkgconf/libc_signals.h> // libc signals configuration
+#include <pkgconf/isoinfra.h> // isoinfra defs, including CYGINT_ISO_EXIT
// INCLUDES
CYG_REPORT_FUNCARG1( "signal number = %d", sig );
+#if CYGINT_ISO_EXIT
exit(1000 + sig); // FIXME
+#else
+ CYG_FAIL("Default signal handler called - no exit available");
+#endif
CYG_REPORT_RETURN();
} // cyg_libc_signals_default_handler()
+2007-10-05 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * src/main.cxx (main): Suspend main thread, rather than exit.
+ Thanks to Sergei Organov for the idea.
+
+2007-09-11 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/cstartup.cxx: Change the INIT priority of
+ cyg_libc_startup_obj so that it is always called after the thread
+ has been constructed. Reported by taiyun@sunnorth.com.cn
+
+2007-07-02 Gary Thomas <gary@mlbassoc.com>
+
+ * cdl/startup.cdl: Add (char *) casts to make GCC/4.2.x happy.
+
2003-03-07 Jonathan Larmour <jifl@eCosCentric.com>
* src/mainthread.cxx: Align stack to relevant architecture alignment.
cdl_option CYGDAT_LIBC_ARGUMENTS {
display "Arguments to main()"
flavor data
- default_value {"{\"\", NULL}"}
+ default_value {"{(char *)\"\", (char *)NULL}"}
description "
This option allows the setting of the arguments
to the main function. This only has any effect
};
static cyg_libc_startup_dummy_constructor_class cyg_libc_startup_obj
- CYGBLD_ATTRIB_INIT_PRI(CYG_INIT_LIBC);
+ CYGBLD_ATTRIB_INIT_AFTER(CYG_INIT_LIBC);
#elif defined( CYGSEM_LIBC_STARTUP_MAIN_INITCONTEXT )
#include <cyg/infra/cyg_trac.h> // Common tracing support
#include <cyg/infra/cyg_ass.h> // Common assertion support
+#ifdef CYGPKG_KERNEL
+# include <pkgconf/kernel.h> // kernel configuration
+# include <cyg/kernel/thread.hxx> // For thread suspend
+# include <cyg/kernel/thread.inl>
+#endif
+
// FUNCTION PROTOTYPES
// We provide a weakly named main to allow this to link if the user
// Its better than just exiting
#ifndef CYGPKG_KERNEL
cyg_user_start();
+#else
+ // Otherwise we suspend ourselves. This prevents problems caused by
+ // running atexit() handlers.
+ Cyg_Thread::self()->suspend();
#endif
CYG_REPORT_RETVAL(0);
+2008-07-21 Guenter Ebermann <guenter.ebermann@gmx.at>
+
+ * src/common/fclose.cxx (fclose): Replace config-dependent use of
+ delete with free(), as the memory had been allocated with malloc.
+
+2007-07-02 Gary Thomas <gary@mlbassoc.com>
+
+ * src/output/vfnprintf.cxx: Add (char *) casts to make GCC/4.2.x happy.
+
+2007-02-05 Sergei Organov <osv@javad.com>
+
+ * src/output/vfnprintf.cxx (vfnprintf): while formatting integers
+ in decimal, convert the value to unsigned long from unsigned long
+ long before processing, unless we actually print long long
+ argument. This tremendously speeds-up the formatting.
+
+2007-01-16 Sergei Organov <osv@javad.com>
+
+ Speed-up [v]s[n]printf() functions by a factor of about 2+. In
+ particular, sprintf(s, "%s", "") becomes faster 2.8 times,
+ printing of every character -- 1.7 times, and, as a result, e.g.,
+ printing of a string of length 50 -- 2.2 times.
+
+ * include/stream.hxx (class Cyg_OutputStream): New ABC.
+ (class Cyg_StdioStream): inherit from Cyg_OutputStream; make
+ the destructor, write(), and get_error() virtual.
+
+ * src/output/vfnprintf.cxx (vfnprintf): Use ABC Cyg_OutputStream
+ instead of Cyg_StdioStream.
+
+ * src/common/vsnprintf.cxx (class Cyg_VsnprintfStream): New class
+ that specializes Cyg_OutputStream for output to a string.
+ (vsnprintf): Use Cyg_VsnprintfStream for printing to a string.
+
+2006-12-22 Sergei Organov <osv@javad.com>
+
+ * src/output/vfnprintf.cxx (vfnprintf): Speed-up formatting of
+ decimal integers by replacing modulo operation with multiply and
+ subtract.
+
+2006-09-27 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * include/stdio.h: Make fpos_t be signed to allow negative
+ SEEK_CUR offsets to fseek().
+ * include/stream.inl (set_position): If SEEK_CUR, then if
+ having to reconcile difference between position and underlying
+ file position, then requested seek position needs adjusting
+ for buffer size.
+ Both above reported and analysed by Ivan Djelic.
+
+2006-09-26 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * src/common/stream.cxx (read): Only update position after direct
+ reads from I/O system so it's updated by the correct number of
+ bytes.
+ (write): Reset underlying file position if there had been
+ stuff read from the file left in the buffer so the file positions
+ are inconsistent.
+
2005-07-22 Andrew Lunn <andrew.lunn@ascom.ch>
* src/common/fopen.cxx (fopen): Default the open mode to Read
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-// Copyright (C) 2004 eCosCentric Limited
+// Copyright (C) 2004, 2006 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
// A type capable of specifying uniquely every file position - ISO C
// standard chap 7.9.1
-typedef cyg_ucount32 fpos_t;
+typedef cyg_count32 fpos_t;
// FILE is just cast to an address here. It is uncast internally to the
// TYPE DEFINITIONS
+class Cyg_OutputStream
+{
+public:
+
+ // Provide empty virtual destructor
+ virtual ~Cyg_OutputStream() {}
+
+ // The following two functions aren't made pure virtual not to bring
+ // dependency on C++ runtime to every application.
+
+ virtual Cyg_ErrNo write( const cyg_uint8 *buffer, cyg_ucount32 buffer_length,
+ cyg_ucount32 *bytes_written );
+
+ virtual Cyg_ErrNo get_error( void );
+
+};
+
class Cyg_StdioStream;
__externC Cyg_ErrNo
cyg_libc_stdio_flush_all_but( Cyg_StdioStream * );
-class Cyg_StdioStream
+class Cyg_StdioStream: public Cyg_OutputStream
{
friend int setvbuf( FILE *, char *, int, size_t ) __THROW;
friend Cyg_ErrNo
public:
// DESTRUCTOR
-
+ virtual
~Cyg_StdioStream();
cyg_ucount32
bytes_available_to_read( void );
- Cyg_ErrNo
+ virtual Cyg_ErrNo
write( const cyg_uint8 *buffer, cyg_ucount32 buffer_length,
cyg_ucount32 *bytes_written );
unlock_me( void );
// get error status for this file
- Cyg_ErrNo
+ virtual Cyg_ErrNo
get_error( void );
// set error status for this file.
if (whence == SEEK_CUR) {
position += bytesavail;
+ pos -= bytesavail;
}
} //endif (whence != SEEK_END)
return EOF;
}
-#ifdef CYGFUN_INFRA_EMPTY_DELETE_FUNCTIONS
// Explicitly call destructor - this flushes the output too
real_stream->~Cyg_StdioStream();
// and free it
free(real_stream);
-#else
- delete real_stream;
-#endif // CYGFUN_INFRA_EMPTY_DELETE_FUNCTIONS
// and mark the stream available for use
Cyg_libc_stdio_files::set_file_stream(i, NULL);
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2006 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//========================================================================
flags.readbuf_char_in_use = false;
}
- position += *bytes_read;
-
// if we are unbuffered, we read as much as we can directly from the
// file system at this point.
*bytes_read+=len;
}
+ position += *bytes_read;
+
unlock_me();
return read_err;
}
#ifdef CYGSEM_LIBC_STDIO_WANT_BUFFERED_IO
- if (flags.last_buffer_op_was_read == true)
+ if (flags.last_buffer_op_was_read == true) {
+#ifdef CYGPKG_LIBC_STDIO_FILEIO
+ if ( 0 != io_buf.get_buffer_space_used() )
+ {
+ off_t newpos = position;
+ io_buf.drain_buffer(); // nuke input bytes to prevent confusion
+ Cyg_ErrNo err = cyg_stdio_lseek( my_device, &newpos, SEEK_SET );
+ if (err) {
+ unlock_me();
+ return err;
+ }
+ }
+#else
io_buf.drain_buffer(); // nuke input bytes to prevent confusion
+#endif
+ }
flags.last_buffer_op_was_read = false;
return write_err;
} // write()
+//
+// class Cyg_OutputStream
+//
+
+Cyg_ErrNo
+Cyg_OutputStream::write( const cyg_uint8 *buffer, cyg_ucount32 buffer_length,
+ cyg_ucount32 *bytes_written )
+{
+ CYG_FAIL("Cyg_OutputStream::write(): pure virtual called");
+ return ENOSYS;
+}
+
+Cyg_ErrNo
+Cyg_OutputStream::get_error( void )
+{
+ CYG_FAIL("Cyg_OutputStream::get_error(): pure virtual called");
+ return ENOSYS;
+}
+
+
+
// EOF stream.cxx
#include <stddef.h> // NULL and size_t from compiler
#include <stdio.h> // header for this file
#include <errno.h> // error codes
-#include <cyg/io/devtab.h> // Device table
#include <cyg/libc/stdio/stream.hxx>// Cyg_StdioStream
#include <cyg/libc/stdio/io.inl> // I/O system inlines
-#ifndef CYGPKG_LIBC_STDIO_FILEIO
-
// FUNCTIONS
-static Cyg_ErrNo
-str_write(cyg_stdio_handle_t handle, const void *buf, cyg_uint32 *len)
+class Cyg_VsnprintfStream: public Cyg_OutputStream
{
- cyg_devtab_entry_t *dev = (cyg_devtab_entry_t *)handle;
- cyg_uint8 **str_p = (cyg_uint8 **)dev->priv;
- cyg_ucount32 i;
-
- // I suspect most strings passed to vsnprintf will be relatively short,
- // so we just take the simple approach rather than have the overhead
- // of calling memcpy etc.
+public:
+ Cyg_VsnprintfStream(char* s): s_(s) {}
- // simply copy string until we run out of user space
+ virtual ~Cyg_VsnprintfStream() { *s_ = '\0'; }
- for (i = 0; i < *len; i++, (*str_p)++ )
- {
- **str_p = *((cyg_uint8 *)buf + i);
- } // for
+ virtual Cyg_ErrNo write( const cyg_uint8 *buffer,
+ cyg_ucount32 buffer_length, cyg_ucount32 *bytes_written );
- *len = i;
+ virtual Cyg_ErrNo get_error( void ) { return ENOERR; }
- return ENOERR;
-
-} // str_write()
+private:
+ char* s_;
+};
-static DEVIO_TABLE(devio_table,
- str_write, // write
- NULL, // read
- NULL, // select
- NULL, // get_config
- NULL); // set_config
-
-externC int
-vsnprintf( char *s, size_t size, const char *format, va_list arg ) __THROW
+Cyg_ErrNo
+Cyg_VsnprintfStream::write(
+ const cyg_uint8 *buffer,
+ cyg_ucount32 buffer_length,
+ cyg_ucount32 *bytes_written )
{
- int rc;
- // construct a fake device with the address of the string we've
- // been passed as its private data. This way we can use the data
- // directly
- DEVTAB_ENTRY_NO_INIT(strdev,
- "strdev", // Name
- NULL, // Dependent name (layered device)
- &devio_table, // I/O function table
- NULL, // Init
- NULL, // Lookup
- &s); // private
- Cyg_StdioStream my_stream( &strdev, Cyg_StdioStream::CYG_STREAM_WRITE,
- false, false, _IONBF, 0, NULL );
-
- rc = vfnprintf( (FILE *)&my_stream, size, format, arg );
-
- // Null-terminate it, but note that s has been changed by str_write(), so
- // that it now points to the end of the string
- s[0] = '\0';
-
- return rc;
-
-} // vsnprintf()
-
-#else
+ char *dest = s_;
+ char const *src = (char const *)buffer;
+ char const *end = src + buffer_length;
+ while(src < end)
+ *dest++ = *src++;
+ s_ = dest;
+ *bytes_written = buffer_length;
+ return ENOERR;
+}
externC int
vsnprintf( char *s, size_t size, const char *format, va_list arg ) __THROW
{
- int rc;
-
- Cyg_StdioStream my_stream( Cyg_StdioStream::CYG_STREAM_WRITE,
- size, (cyg_uint8 *)s );
-
- rc = vfnprintf( (FILE *)&my_stream, size, format, arg );
-
- if( rc > 0 )
- s[rc] = '\0';
-
- return rc;
-
+ Cyg_VsnprintfStream stream(s);
+ return vfnprintf( (FILE *)(void *)&stream, size, format, arg );
} // vsnprintf()
-#endif
-
// EOF vsnprintf.cxx
#define PRINT(ptr, len) \
CYG_MACRO_START \
cyg_ucount32 length = MIN( (cyg_ucount32) len, n - ret - 1); \
- if (((Cyg_StdioStream *)stream)->write( (const cyg_uint8 *)ptr, \
+ if (((Cyg_OutputStream *)stream)->write( (const cyg_uint8 *)ptr, \
length, &length )) \
goto error; \
if (length < (cyg_ucount32)len) { \
/* NOSTRICT */
_uquad = (unsigned long)va_arg(arg, void *);
base = HEX;
- xdigs = "0123456789abcdef";
+ xdigs = (char *)"0123456789abcdef";
flags |= HEXPREFIX;
ch = 'x';
goto nosign;
case 's':
if ((cp = va_arg(arg, char *)) == NULL)
- cp = "(null)";
+ cp = (char *)"(null)";
if (prec >= 0) {
/*
* can't use strlen; can only look for the
base = DEC;
goto nosign;
case 'X':
- xdigs = "0123456789ABCDEF";
+ xdigs = (char *)"0123456789ABCDEF";
goto hex;
case 'x':
- xdigs = "0123456789abcdef";
+ xdigs = (char *)"0123456789abcdef";
hex: _uquad = UARG();
base = HEX;
/* leading 0x/X only if non-zero */
break;
case DEC:
- /* many numbers are 1 digit */
- while (_uquad >= 10) {
- *--cp = to_char(_uquad % 10);
- _uquad /= 10;
+ if (!(flags & QUADINT)) {
+ /* many numbers are 1 digit */
+ unsigned long v = (unsigned long)_uquad;
+ while (v >= 10) {
+ /* The following is usually faster than using a modulo */
+ unsigned long next = v / 10;
+ *--cp = to_char(v - (next * 10));
+ v = next;
+ }
+ *--cp = to_char(v);
+ }
+ else {
+ while (_uquad >= 10) {
+ /* The following is usually faster than using a modulo */
+ u_quad_t next = _uquad / 10;
+ *--cp = to_char(_uquad - (next * 10));
+ _uquad = next;
+ }
+ *--cp = to_char(_uquad);
}
- *--cp = to_char(_uquad);
break;
case HEX:
break;
default:
- cp = "bug in vfprintf: bad base";
+ cp = (char *)"bug in vfprintf: bad base";
size = strlen(cp);
goto skipsize;
}
}
done:
error:
- return (((Cyg_StdioStream *) stream)->get_error() ? EOF : ret);
+ return (((Cyg_OutputStream *) stream)->get_error() ? EOF : ret);
/* NOTREACHED */
}
+2005-12-27 Sergei Organov <osv@javad.com>
+
+ * src/strtod.cxx (Ise): 'd' and 'D' aren't allowed in floating
+ formats.
+
2004-08-18 Fredrik Hederstierna <fredrik@wespot.com>
2004-08-18 Jonathan Larmour <jifl@eCosCentric.com>
display "Additional compiler flags"
flavor data
no_define
- default_value { "" }
+ default_value { "-fno-rtti -Woverloaded-virtual" }
description "
This option modifies the set of compiler flags for
building this package. These flags are used in addition
display "Suppressed compiler flags"
flavor data
no_define
- default_value { "" }
+ default_value { "-Wno-pointer-sign" }
description "
This option modifies the set of compiler flags for
building this package. These flags are removed from
// MACROS
-#define Ise(c) ((c == 'e') || (c == 'E') || (c == 'd') || (c == 'D'))
+#define Ise(c) ((c == 'e') || (c == 'E'))
#define Issign(c) ((c == '-') || (c == '+'))
#define Val(c) ((c - '0'))
if(Ise(*nptr))
{
conv_done = 1;
- if(*++nptr != '\0') /* skip e|E|d|D */
+ if(*++nptr != '\0') /* skip e|E */
{ /* ! ([nptr]xxx[.[yyy]]e) */
while(isspace(*nptr)) nptr++; /* Ansi allows spaces after e */
display "Additional compiler flags"
flavor data
no_define
- default_value { "" }
+ default_value { "-fno-rtti -Woverloaded-virtual" }
description "
This option modifies the set of compiler flags for
building the C library. These flags are used in addition
display "Suppressed compiler flags"
flavor data
no_define
- default_value { "" }
+ default_value { "-Wno-pointer-sign" }
description "
This option modifies the set of compiler flags for
building the C library. These flags are removed from
+2007-09-15 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * tests/strptime.c (test): Extend the test so that it triggers the
+ previous bug and shows that the fix works.
+
+2007-08-18 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
+
+ * src/strftime.cxx: Moved CYG_PRECONDITIONs to do_format() to
+ make strftime() only complain about illegal struct tm contents if
+ these are actually used. Fixes a bug with tests/strptime which
+ would fail because tm->tm_yday was uninitialized.
+
+2006-10-02 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * tests/strftime.c (test): Fix %I test.
+
+2006-08-31 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * cdl/time.cdl: Don't bother inlining mktime() or
+ gmtime_r() by default - they're too big to be worth it.
+
+2006-08-24 Alexander Neundorf <alexander.neundorf@jenoptik.com>
+
+ * src/strftime.cxx: Fixed "%I" (Time in 12 hour modus was 1 hour off)
+
+2006-06-16 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * tests/strptime.c: Add a testcase for the previous fix.
+
+2006-06-13 Dan Jakubiec <dan.jakubiec@systech.com>
+
+ * src/strptime.cxx: Removed the initialization of the struct tm fields
+ to prevent clobbering of time values when using the following format
+ specifiers: %D, %r, %R, %T, %X, %x.
+
2005-03-27 Andrew Lunn <andrew.lunn@ascom.ch>
* include/time.h: Added CYGBLD_ATTRIB_STRFTIME_FORMAT where
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2006 eCosCentric Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2006 eCosCentric Ltd.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
cdl_option CYGIMP_LIBC_TIME_MKTIME_INLINE {
display "mktime()"
- default_value 1
+ default_value 0
description "
Allow the mktime() function to be inlined"
}
cdl_option CYGIMP_LIBC_TIME_GMTIME_R_INLINE {
display "gmtime_r()"
requires CYGFUN_LIBC_TIME_POSIX
- default_value 1
+ default_value 0
description "
Allow the gmtime_r() function to be inlined"
}
switch (fmtchar) {
case 'a':
+ CYG_PRECONDITION((timeptr->tm_wday >= 0) && (timeptr->tm_wday < 7),
+ "timeptr->tm_wday out of range!");
if (sizeleft<3)
return -1;
buf[0] = cyg_libc_time_day_name[timeptr->tm_wday][0];
buf[2] = cyg_libc_time_day_name[timeptr->tm_wday][2];
return 3;
case 'A':
+ CYG_PRECONDITION((timeptr->tm_wday >= 0) && (timeptr->tm_wday < 7),
+ "timeptr->tm_wday out of range!");
if (sizeleft < cyg_libc_time_day_name_len[timeptr->tm_wday])
return -1;
for (i=0; i<cyg_libc_time_day_name_len[timeptr->tm_wday]; ++i)
// ** fall through **
#endif
case 'b':
+ CYG_PRECONDITION((timeptr->tm_mon >= 0) && (timeptr->tm_mon < 12),
+ "timeptr->tm_mon out of range!");
if (sizeleft<3)
return -1;
buf[0] = cyg_libc_time_month_name[timeptr->tm_mon][0];
buf[2] = cyg_libc_time_month_name[timeptr->tm_mon][2];
return 3;
case 'B':
+ CYG_PRECONDITION((timeptr->tm_mon >= 0) && (timeptr->tm_mon < 12),
+ "timeptr->tm_mon out of range!");
if (sizeleft < cyg_libc_time_month_name_len[timeptr->tm_mon])
return -1;
for (i=0; i<cyg_libc_time_month_name_len[timeptr->tm_mon]; ++i)
return ((0==i) ? -1 : i);
case 'd':
+ // Currently I don't check _actual_ numbers of days in each month here
+ // FIXME: No reason why not though
+ CYG_PRECONDITION((timeptr->tm_mday >= 1) && (timeptr->tm_mday < 32),
+ "timeptr->tm_mday out of range!");
+
if (sizeleft < 2)
return -1;
buf[0] = (timeptr->tm_mday / 10) + '0';
return 2;
#ifdef CYGFUN_LIBC_TIME_SUS_EXTNS
case 'e':
+ // Currently I don't check _actual_ numbers of days in each month here
+ // FIXME: No reason why not though
+ CYG_PRECONDITION((timeptr->tm_mday >= 1) && (timeptr->tm_mday < 32),
+ "timeptr->tm_mday out of range!");
if (sizeleft < 2)
return -1;
i = (timeptr->tm_mday / 10);
return 2;
#endif
case 'H':
+ CYG_PRECONDITION((timeptr->tm_hour >= 0) && (timeptr->tm_hour < 24),
+ "timeptr->tm_hour out of range!");
if (sizeleft < 2)
return -1;
buf[0] = (timeptr->tm_hour / 10) + '0';
buf[1] = (timeptr->tm_hour % 10) + '0';
return 2;
case 'I':
+ CYG_PRECONDITION((timeptr->tm_hour >= 0) && (timeptr->tm_hour < 24),
+ "timeptr->tm_hour out of range!");
if (sizeleft < 2)
return -1;
- buf[0] = ((timeptr->tm_hour%12 + 1) / 10) + '0';
- buf[1] = ((timeptr->tm_hour%12 + 1) % 10) + '0';
+ buf[0] = (((timeptr->tm_hour%12) ? (timeptr->tm_hour%12) : 12) / 10) + '0';
+ buf[1] = (((timeptr->tm_hour%12) ? (timeptr->tm_hour%12) : 12) % 10) + '0';
return 2;
case 'j':
+ CYG_PRECONDITION((timeptr->tm_yday >= 0) && (timeptr->tm_yday < 366),
+ "timeptr->tm_yday out of range!");
if (sizeleft < 3)
return -1;
buf[0] = (timeptr->tm_yday / 100) + '0';
buf[2] = (timeptr->tm_yday % 10) + '0';
return 3;
case 'm':
+ CYG_PRECONDITION((timeptr->tm_mon >= 0) && (timeptr->tm_mon < 12),
+ "timeptr->tm_mon out of range!");
if (sizeleft < 2)
return -1;
buf[0] = ((timeptr->tm_mon+1) / 10) + '0';
buf[1] = ((timeptr->tm_mon+1) % 10) + '0';
return 2;
case 'M':
+ CYG_PRECONDITION((timeptr->tm_min >= 0) && (timeptr->tm_min < 60),
+ "timeptr->tm_min out of range!");
if (sizeleft < 2)
return -1;
buf[0] = (timeptr->tm_min / 10) + '0';
buf[1] = (timeptr->tm_min % 10) + '0';
return 2;
case 'p':
+ CYG_PRECONDITION((timeptr->tm_hour >= 0) && (timeptr->tm_hour < 24),
+ "timeptr->tm_hour out of range!");
if (sizeleft < 2)
return -1;
buf[0] = (timeptr->tm_hour > 11) ? 'p' : 'a';
buf[1] = 'm';
return 2;
case 'S':
+ CYG_PRECONDITION((timeptr->tm_sec >= 0) && (timeptr->tm_sec < 62),
+ "timeptr->tm_sec out of range!");
if (sizeleft < 2)
return -1;
buf[0] = (timeptr->tm_sec / 10) + '0';
return ((0==i) ? -1 : i);
#endif
case 'U':
+ CYG_PRECONDITION((timeptr->tm_wday >= 0) && (timeptr->tm_wday < 7),
+ "timeptr->tm_wday out of range!");
+ CYG_PRECONDITION((timeptr->tm_yday >= 0) && (timeptr->tm_yday < 366),
+ "timeptr->tm_yday out of range!");
if (sizeleft < 2)
return -1;
i = (timeptr->tm_yday - timeptr->tm_wday + 7) / 7;
buf[1] = (i % 10) + '0';
return 2;
case 'w':
+ CYG_PRECONDITION((timeptr->tm_wday >= 0) && (timeptr->tm_wday < 7),
+ "timeptr->tm_wday out of range!");
// Don't need to check size - we'll always be called with sizeleft > 0
buf[0] = timeptr->tm_wday + '0';
return 1;
case 'W':
+ CYG_PRECONDITION((timeptr->tm_wday >= 0) && (timeptr->tm_wday < 7),
+ "timeptr->tm_wday out of range!");
+ CYG_PRECONDITION((timeptr->tm_yday >= 0) && (timeptr->tm_yday < 366),
+ "timeptr->tm_yday out of range!");
if (sizeleft < 2)
return -1;
i = (timeptr->tm_yday + ((8-timeptr->tm_wday) % 7)) / 7;
return (0==i) ? -1 : i;
case 'y':
+ CYG_PRECONDITION((timeptr->tm_year > -1900) &&
+ (timeptr->tm_year < 8100),
+ "timeptr->tm_year out of range!");
if (sizeleft < 2)
return -1;
buf[0] = ((timeptr->tm_year % 100) / 10) + '0';
buf[1] = ((timeptr->tm_year % 100) % 10) + '0';
return 2;
case 'Y':
+ CYG_PRECONDITION((timeptr->tm_year > -1900) &&
+ (timeptr->tm_year < 8100),
+ "timeptr->tm_year out of range!");
if (sizeleft < 4)
return -1;
buf[0] = ((1900+timeptr->tm_year) / 1000) + '0';
"timeptr is at address %08x",
s, maxsize, format, timeptr);
- CYG_PRECONDITION((timeptr->tm_sec >= 0) && (timeptr->tm_sec < 62),
- "timeptr->tm_sec out of range!");
- CYG_PRECONDITION((timeptr->tm_min >= 0) && (timeptr->tm_min < 60),
- "timeptr->tm_min out of range!");
- CYG_PRECONDITION((timeptr->tm_hour >= 0) && (timeptr->tm_hour < 24),
- "timeptr->tm_hour out of range!");
- // Currently I don't check _actual_ numbers of days in each month here
- // FIXME: No reason why not though
- CYG_PRECONDITION((timeptr->tm_mday >= 1) && (timeptr->tm_mday < 32),
- "timeptr->tm_mday out of range!");
- CYG_PRECONDITION((timeptr->tm_mon >= 0) && (timeptr->tm_mon < 12),
- "timeptr->tm_mon out of range!");
- CYG_PRECONDITION((timeptr->tm_wday >= 0) && (timeptr->tm_wday < 7),
- "timeptr->tm_wday out of range!");
- CYG_PRECONDITION((timeptr->tm_yday >= 0) && (timeptr->tm_yday < 366),
- "timeptr->tm_yday out of range!");
- CYG_PRECONDITION((timeptr->tm_year > -1900) &&
- (timeptr->tm_year < 8100),
- "timeptr->tm_year out of range!");
-
if (!maxsize) {
CYG_REPORT_RETVAL(0);
return 0;
{
char c;
- timeptr->tm_yday = 1; // Initialize to a well known, valid date
- timeptr->tm_isdst = 0; // Tuesday March 18 14:05:00 2003 UTC
- timeptr->tm_sec = 0;
- timeptr->tm_min = 5;
- timeptr->tm_hour = 14;
- timeptr->tm_mday = 18;
- timeptr->tm_mon = 2;
- timeptr->tm_year = 103;
- timeptr->tm_wday = 2;
- timeptr->tm_yday = 77;
-
for (; (c = *format) != '\0'; ++format) {
char *s;
int ret;
"strftime test #7");
size = strftime(s, 1000, "%I", &tm1);
- CYG_TEST_PASS_FAIL((size==2) && !my_strcmp(s, "09"),
+ CYG_TEST_PASS_FAIL((size==2) && !my_strcmp(s, "08"),
"strftime test #8");
size = strftime(s, 1000, "%j", &tm1);
#include <time.h>
#include <cyg/infra/testcase.h>
-
+#include <string.h> // strlen()
// HOW TO START TESTS
# define START_TEST( test ) test(0)
dp = "Fri Jan 24 08:33:14 2003";
fp = "%a %b %d %H:%M:%S %Y";
- sp = strptime(dp, fp, &tm1);
+ sp = strptime(dp, fp, &tm1);
+
+ // Set an invalid year day. The following converters don't use
+ // this, so it should not cause a problem.
+ tm1.tm_yday = 1000;
+
CYG_TEST_PASS_FAIL(((sp!=NULL) && (*sp=='\0')), "strptime test #1");
size = strftime(s, sizeof(s), fp, &tm1);
CYG_TEST_PASS_FAIL(((size==strlen(dp)) && (my_strcmp(s, dp) == 0)), "strptime test #2");
size = strftime(s, sizeof(s), fp, &tm1);
CYG_TEST_PASS_FAIL(((size==strlen(dp)) && (my_strcmp(s, dp) == 0)), "strptime test #4");
+ dp = "2006:06:13 12:22:01";
+ fp = "%x %X";
+ sp = strptime(dp, fp, &tm1);
+ CYG_TEST_PASS_FAIL(((sp!=NULL) && (*sp=='\0')), "strptime test #5");
+ CYG_TEST_PASS_FAIL((tm1.tm_sec == 01) &&
+ (tm1.tm_min == 22) &&
+ (tm1.tm_hour == 12) &&
+ (tm1.tm_mday == 13) &&
+ (tm1.tm_mon == (06 - 1)) &&
+ (tm1.tm_year == (2006 - 1900)), "strptime test #6");
+ size = strftime(s, sizeof(s), fp, &tm1);
CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for C library "
"strptime() function");
} // test()
+2007-09-04 Stephen Finney <shf@pfinc.com>
+2007-09-04 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * src/misc/infconst.c: Declare infinity byte order as dependent on
+ double byte order, not integer.
+ Fixes bug #1000448.
+
2004-04-14 Andrew Lunn <andrew.lunn@ascom.ch>
* src/double/ieee754-core/e_cosh.c (__ieee754_cosh):
// GLOBALS
-#if (CYG_BYTEORDER == CYG_MSBFIRST) // Big endian
+#if (CYG_DOUBLE_BYTEORDER == CYG_MSBFIRST) // Big endian
const Cyg_libm_ieee_double_shape_type cyg_libm_infinity = { {0x7ff00000, 0} };
+2008-01-06 Shaun Louie <sal@microplex.com>
+
+ * include/net/radix.h
+ * src/sys/net/radix.c
+ * src/sys/net/route.c
+ * src/sys/net/rtsock.c
+ * src/sys/netinet/if_ether.c
+ * src/sys/netinet6/icmp6.c
+ * src/sys/netinet6/nd6.c: Change Free to R_Free() so that it
+ corresponds to R_Malloc, and allows Free() wrappers in other
+ places.
+
+2007-09-27 Gary Thomas <gary@mlbassoc.com>
+
+ * src/sys/net/if.c (ifioctl): Add missing ioctl functions
+ (SIOCGIFSTATSUD, SIOCGIFSTATS) Reported by Emmanuel Coullien.
+
+2007-09-11 Daniel Néri <daniel.neri@sigicom.se>
+
+ * include/sys/socketvar.h: Fix very old and subtle macro bug. From
+ FreeBSD revision 1.141.2.3 (RELENG_6 branch): "correctly return an
+ error if M_NOWAIT is passed to sblock() and the operation might
+ block."
+
+2007-07-08 Alexander Aganichev <aaganichev@gmail.com>
+
+ * include/sys/param.h (log_): Really disable logging when
+ it is disabled.
+
+2007-03-21 Jay Foster <jay@systech.com>
+
+ * cdl/freebsd_net.cdl: Added option to enable BOOTP_COMPAT to
+ allow bootp to work.
+
+2006-07-19 Philip Keller <keller@metrolab.ch>
+
+ * src/ecos/support.c (cyg_netint): Don't handle events that don't
+ have handlers registered. Fixes Bug 1000046, whereby an assertion
+ or crash resulted from an ARP package arriving before network
+ initialization was complete.
+
+2006-06-14 Andy Jackson <andy@xylanta.com>
+
+ * cdl/freebsd_net.cdl, src/ecos/support.c, src/ecos/support.c:
+ Changes to make stack sizes CDL configurable.
+
+2006-05-19 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * tests/sysctl1.c: Use CYG_NELEM from infra.
+
+2006-05-08 Andy Jackson <andy@grapevinetech.co.uk>
+
+ * src/ecos/support.c (cyg_net_show_mbufs): Use %p in diag_printf
+ to keep the compiler happy.
+
+2005-10-24 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * include/sys/param.h: Include <string.h> to stop warnings.
+
+2005-10-23 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * include/sys/time.h (Removed): Use the isoinfra sys/time.h
+ * include/net/if.h: We do need sys/time.h for timeval.
+ * src/sys/kern/uipc_socket.c: include sys/time.h for timeval
+ * src/sys/kern/uipc_socket2.c: Ditto
+ * src/sys/netinet6/in6_pcb.c (in6_pcbdetach): remove lvalue cast
+ to keep gcc4.x happy.
+
2005-09-02 Sebastien Couret <sebastien.couret@elios-informatique.fr>
* src/sys/kern/kern_sysctl.c: Silent compiler warning on lvalue
}
cdl_option CYGPKG_NET_MAXSOCKETS {
- display "Max number of open sockets."
+ display "Max number of open sockets"
flavor data
default_value CYGNUM_FILEIO_NFILE
description "
used by the networking code."
}
- cdl_option CYGPKG_NET_THREAD_PRIORITY {
- display "Priority level for backgound network processing."
- flavor data
- default_value 7
- description "
- This option allows the thread priority level used by the
- networking stack to be adjusted by the user. It should be set
- high enough that sufficient CPU resources are available to
- process network data, but may be adjusted so that application
- threads can have precedence over network processing."
+ cdl_component CYGPKG_NET_THREAD {
+ display "Background network processing thread options"
+ flavor none
+ no_define
+
+ cdl_option CYGPKG_NET_THREAD_PRIORITY {
+ display "Priority level for background network processing"
+ flavor data
+ default_value 7
+ description "
+ This option allows the thread priority level used by the
+ networking stack to be adjusted by the user. It should be set
+ high enough that sufficient CPU resources are available to
+ process network data, but may be adjusted so that application
+ threads can have precedence over network processing."
+ }
+
+ cdl_option CYGNUM_NET_THREAD_STACKSIZE {
+ display "Stack size for backgound network processing"
+ flavor data
+ default_value { (CYGPKG_NET_INET6 ?
+ "CYGNUM_HAL_STACK_SIZE_TYPICAL+2048" :
+ "CYGNUM_HAL_STACK_SIZE_TYPICAL") }
+ description "
+ This option allows the thread stack allocated for the
+ networking stack to be adjusted by the user. "
+ }
}
- cdl_option CYGPKG_NET_FAST_THREAD_PRIORITY {
- display "Priority level for fast network processing."
- flavor data
- default_value CYGPKG_NET_THREAD_PRIORITY - 1
- description "
- This option sets the thread priority level used by the fast
- network thread. The fast network thread runs often but briefly, to
- service network device interrupts and network timeout events. This
- thread should have higher priority than the background network
- thread. It is reasonable to set this thread's priority higher than
- application threads for best network throughput, or to set it lower
- than application threads for best latency for those application
- threads themselves, potentially at a cost to network throughput."
+ cdl_component CYGPKG_NET_FAST_THREAD {
+ display "Fast network processing thread options"
+ flavor none
+ no_define
+
+ cdl_option CYGPKG_NET_FAST_THREAD_PRIORITY {
+ display "Priority level for fast network processing"
+ flavor data
+ default_value CYGPKG_NET_THREAD_PRIORITY - 1
+ description "
+ This option sets the thread priority level used by the fast
+ network thread. The fast network thread runs often but briefly, to
+ service network device interrupts and network timeout events. This
+ thread should have higher priority than the background network
+ thread. It is reasonable to set this thread's priority higher than
+ application threads for best network throughput, or to set it lower
+ than application threads for best latency for those application
+ threads themselves, potentially at a cost to network throughput."
+ }
+
+ cdl_option CYGNUM_NET_FAST_THREAD_STACKSIZE {
+ display "Stack size for fast network processing"
+ flavor data
+ default_value { "CYGNUM_HAL_STACK_SIZE_TYPICAL" }
+ description "
+ This option allows the thread stack allocated for the
+ fast networking stack to be adjusted by the user. "
+ }
}
cdl_component CYGPKG_NET_FAST_THREAD_TICKLE_DEVS {
flavor none
no_define
+ cdl_option CYGOPT_NET_FREEBSD_STACK_ACCEPT_UNICAST {
+ display "Accept unicast packets on INADDR_ANY interfaces"
+ flavor bool
+ no_define
+ define BOOTP_COMPAT
+ default_value 0
+ description "This option enables passing of unicast
+ IP packets to the application, when the interface
+ IP address is configured as INADDR_ANY (0.0.0.0).
+ This option is useful for some applications that
+ need to receive unicast IP packets when the interface
+ address is unknown. Such an application is bootp."
+ }
+
cdl_option CYGPKG_NET_FREEBSD_STACK_CFLAGS_ADD {
display "Additional compiler flags"
flavor data
* <net/if.h> does not depend on <sys/time.h> on most other systems. This
* helps userland compatability. (struct timeval ifi_lastchange)
*/
+#ifndef __ECOS
#ifndef _KERNEL
#include <sys/time.h>
#endif
+#else
+#include <sys/time.h>
+#endif
struct ifnet;
#define Bcopy(a, b, n) bcopy(((char *)(a)), ((char *)(b)), (unsigned)(n))
#define Bzero(p, n) bzero((char *)(p), (int)(n));
#define R_Malloc(p, t, n) (p = (t) malloc((unsigned int)(n)))
-#define Free(p) free((char *)p);
+#define R_Free(p) free((char *)p);
#else
#define Bcmp(a, b, n) bcmp(((caddr_t)(a)), ((caddr_t)(b)), (unsigned)(n))
#define Bcopy(a, b, n) bcopy(((caddr_t)(a)), ((caddr_t)(b)), (unsigned)(n))
#define Bzero(p, n) bzero((caddr_t)(p), (unsigned)(n));
#define R_Malloc(p, t, n) (p = (t) malloc((unsigned long)(n), M_RTABLE, M_DONTWAIT))
-#define Free(p) free((caddr_t)p, M_RTABLE);
+#define R_Free(p) free((caddr_t)p, M_RTABLE);
#endif /* _KERNEL */
void rn_init __P((void));
#undef uint8_t
#undef uint16_t
#undef uint32_t
+#undef int8_t
+#undef int16_t
+#undef int32_t
+
typedef __signed char int8_t;
typedef unsigned char u_int8_t;
typedef unsigned char uint8_t;
#include <sys/types.h>
#include <sys/endian.h>
#include <errno.h>
+#include <string.h>
#ifdef _KERNEL
// External [common] variables
#else
#define log(lvl, args...)
#define log_dump(lvl, buf, len)
-#define log_(lvl)
+#define log_(lvl) if (0)
#endif
#endif // _KERNEL
*/
#define sblock(sb, wf) ((sb)->sb_flags & SB_LOCK ? \
(((wf) == M_WAITOK) ? sb_lock(sb) : EWOULDBLOCK) : \
- ((sb)->sb_flags |= SB_LOCK), 0)
+ ((sb)->sb_flags |= SB_LOCK, 0))
/* release lock on sockbuf sb */
#define sbunlock(sb) { \
int cyg_net_log_mask = CYGPKG_NET_FREEBSD_LOGGING;
#endif
-#ifdef CYGPKG_NET_INET6
-#define STACK_SIZE (CYGNUM_HAL_STACK_SIZE_TYPICAL+2048)
-#else
-#define STACK_SIZE CYGNUM_HAL_STACK_SIZE_TYPICAL
-#endif
+#define STACK_SIZE CYGNUM_NET_THREAD_STACKSIZE
+
static char netint_stack[STACK_SIZE];
static cyg_thread netint_thread_data;
static cyg_handle_t netint_thread_handle;
default: type="UNKNOWN"; break;
}
- diag_printf("%08x: %s %04x %08x[%03d] %08x %08x\n",
+ diag_printf("%p: %s %04x %p[%03d] %p %p\n",
m, type,
m->m_hdr.mh_flags,
m->m_hdr.mh_data,
spl = splsoftnet(); // Prevent any overlapping "stack" processing
for (lvl = NETISR_MIN; lvl <= NETISR_MAX; lvl++) {
if (curisr & (1<<lvl)) {
- CYG_ASSERT(_netisr_handlers[lvl] != 0, "unregistered netisr handler");
- (*_netisr_handlers[lvl])();
+ if (NULL != _netisr_handlers[lvl])
+ (*_netisr_handlers[lvl])();
}
}
splx(spl);
static cyg_int32 last_delta;
static cyg_tick_count_t last_set_time;
-#define STACK_SIZE CYGNUM_HAL_STACK_SIZE_TYPICAL
+#define STACK_SIZE CYGNUM_NET_FAST_THREAD_STACKSIZE
+
static char alarm_stack[STACK_SIZE];
static cyg_thread alarm_thread_data;
static cyg_handle_t alarm_thread_handle;
#include <sys/socketvar.h>
#include <cyg/io/file.h>
+#include <sys/time.h>
#ifdef INET
static int do_setopt_accept_filter(struct socket *so, struct sockopt *sopt);
#include <sys/socketvar.h>
#include <cyg/io/file.h>
+#include <sys/time.h>
int maxsockets = CYGPKG_NET_MAXSOCKETS;
case SIOCGLIFPHYADDR:
case SIOCGIFMEDIA:
case SIOCGIFGENERIC:
+ case SIOCGIFSTATS:
+ case SIOCGIFSTATSUD:
if (ifp->if_ioctl == 0)
return (EOPNOTSUPP);
return ((*ifp->if_ioctl)(ifp, cmd, data));
x = rn_insert(cp, mask_rnhead, &maskduplicated, x);
if (maskduplicated) {
log(LOG_ERR, "rn_addmask: mask impossibly already in tree");
- Free(saved_x);
+ R_Free(saved_x);
return (x);
}
/*
* This also frees the gateway, as they are always malloc'd
* together.
*/
- Free(rt_key(rt));
+ R_Free(rt_key(rt));
/*
* and the rtentry itself of course
*/
- Free(rt);
+ R_Free(rt);
}
}
* also add the rt_gwroute if possible.
*/
if ((error = rt_setgate(rt, dst, gateway)) != 0) {
- Free(rt);
+ R_Free(rt);
senderr(error);
}
if (rt->rt_ifa) {
IFAFREE(rt->rt_ifa);
}
- Free(rt_key(rt));
- Free(rt);
+ R_Free(rt_key(rt));
+ R_Free(rt);
senderr(EEXIST);
}
*/
if (old) {
Bcopy(dst, new, dlen);
- Free(old);
+ R_Free(old);
}
/*
if (new_rtm == 0)
senderr(ENOBUFS);
Bcopy(rtm, new_rtm, rtm->rtm_msglen);
- Free(rtm); rtm = new_rtm;
+ R_Free(rtm); rtm = new_rtm;
}
(void)rt_msg2(rtm->rtm_type, &info, (caddr_t)rtm,
(struct walkarg *)0);
if ((so->so_options & SO_USELOOPBACK) == 0) {
if (route_cb.any_count <= 1) {
if (rtm)
- Free(rtm);
+ R_Free(rtm);
m_freem(m);
return (error);
}
m = NULL;
} else if (m->m_pkthdr.len > rtm->rtm_msglen)
m_adj(m, rtm->rtm_msglen - m->m_pkthdr.len);
- Free(rtm);
+ R_Free(rtm);
}
if (rp)
rp->rcb_proto.sp_family = 0; /* Avoid us */
rt->rt_flags &= ~RTF_LLINFO;
if (la->la_hold)
m_freem(la->la_hold);
- Free((caddr_t)la);
+ R_Free((caddr_t)la);
}
}
struct rttimer *rtt;
{
rt->rt_flags |= RTF_PROBEMTU;
- Free(rtt);
+ R_Free(rtt);
}
int *icmp6_sysvars[] = ICMPV6CTL_VARS;
#endif /* IPSEC */
inp->inp_gencnt = ++ipi->ipi_gencnt;
in_pcbremlists(inp);
- sotoinpcb(so) = 0;
+ so->so_pcb = 0;
sofree(so);
if (inp->in6p_inputopts) /* Free all received options. */
static mifi_t nummifs = 0;
static mifi_t reg_mif_num = (mifi_t)-1;
-static struct pim6stat pim6stat;
+struct pim6stat pim6stat;
static int pim6;
/*
rt->rt_flags &= ~RTF_LLINFO;
if (ln->ln_hold)
m_freem(ln->ln_hold);
- Free((caddr_t)ln);
+ R_Free((caddr_t)ln);
}
}
#include <sys/sysctl.h>
#include <cyg/infra/testcase.h>
-#ifndef NELEM
-#define NELEM(x) sizeof(x)/sizeof(*x)
-#endif
#define STACK_SIZE (CYGNUM_HAL_STACK_SIZE_TYPICAL + 0x1000)
static char stack[STACK_SIZE];
/* Test the OID to name function of sysctl*/
oldbuffsize = sizeof(oldbuff);
- ret = sysctl(mib_name_debug_name, NELEM(mib_name_debug_name),
+ ret = sysctl(mib_name_debug_name, CYG_NELEM(mib_name_debug_name),
oldbuff, &oldbuffsize, NULL, 0);
if (ret == -1) CYG_TEST_FAIL("sysclt(mib_name) failed");
CYG_TEST_INFO(oldbuff);
/* Test the name to OID function of sysclt */
oldbuffsize = sizeof(oldbuff);
- ret = sysctl(mib_name2oid, NELEM(mib_name2oid), oldbuff, &oldbuffsize,
+ ret = sysctl(mib_name2oid, CYG_NELEM(mib_name2oid), oldbuff, &oldbuffsize,
name2oid, sizeof(name2oid));
if (ret == -1) CYG_TEST_FAIL("sysclt(mib_name) failed");
CYG_TEST_PASS_FAIL(((ret == 8 ) &&
"sysctl.name2oid");
/* Walk the table using the next function of sysclt */
- num_elem = NELEM(mib_next)+1;
- new_oid = mib + NELEM(mib_next);
+ num_elem = CYG_NELEM(mib_next)+1;
+ new_oid = mib + CYG_NELEM(mib_next);
mib[2] = 0;
do {
memcpy(mib,mib_next,sizeof(mib_next));
}
}
p = pbuff;
- num_elem = NELEM(mib_next) + (ret / 4);
+ num_elem = CYG_NELEM(mib_next) + (ret / 4);
i=0;
while (ret > 0) {
p+=diag_sprintf(p, "%d ",new_oid[i++]);
} while (ret != -1);
/* Tests for sysctlnametomib */
- num_elem = NELEM(mib);
+ num_elem = CYG_NELEM(mib);
ret = sysctlnametomib(name2oid, mib,&num_elem);
if (ret == -1) CYG_TEST_FAIL("sysctlnametomib failed");
CYG_TEST_PASS_FAIL(((num_elem == 2 ) &&
CYG_TEST_PASS_FAIL((ret == -1) && (errno = ENOMEM),
"sysctlnametooid2");
/* This time with an unknown name */
- num_elem = NELEM(mib);
+ num_elem = CYG_NELEM(mib);
ret = sysctlnametomib("unknown.unknown", mib,&num_elem);
CYG_TEST_PASS_FAIL((ret == -1) && (errno = ENOENT),
"sysctlnametooid3");
+2008-04-13 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * tests/server_test.c (server_test): Fix typo with atoi which
+ should really be ultoa(). Cleanup to use diag_sprintf() which is
+ always available. Bug reported by Grant Edwards.
+
+2007-12-21 Oyvind Harboe <oyvind.harboe@zylin.com>
+
+ * src/tftp_client.c, include/arpa/tftp.h, cdl/net.cdl: tftp
+ blksize negotiation support. >512 byte block sizes improves tftp
+ GET performance. Switched to memcpy(), which matters for larger
+ blocks.
+
+2007-01-15 Gary Thomas <gary@mlbassoc.com>
+
+ * src/dhcp_support.c (dhcp_mgt_entry): Better handling when restarting
+ interfaces after expired lease(s). Keep trying in case the DHCP server
+ has gone down.
+
+2007-01-09 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * doc/manpages/net/getaddrinfo.3: Remove obsolete comment about
+ not being thread-safe.
+
+2007-01-07 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/dhcp_support.c:
+ * cdl/net.cdl:
+ Added CDL to control the size of the stack used by
+ the DHCP management thread.
+
+2006-12-18 Sergei Gavrikov <sg@sgs.gomel.by>
+
+ * tests/ga_server_test.c: Updated flags argument in call of
+ getnameinfo().
+
+2006-05-25 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * cdl/net.cdl: Fix calculation of TFTPD stack
+ size. CYGNUM_HAL_STACK_SIZE_TYPICAL is not a CDL variable, it is a
+ #define, so we need to ensure that the compiler evaluates the
+ expression, not the CDL library.
+
+2006-03-26 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * tests/nc_test_framework.h:
+ * tests/nc_test_master.c: Fix the compiler warnings when
+ building for Linux.
+
+2006-02-27 Jay Foster <jay@systech.com>
+
+ * src/dhcp_prot.c: Updated set_fixed_tag(), set_variable_tag(),
+ and unset_tag() to handle TAG_PAD bytes properly. Also updated
+ set_fixed_tag() and set_variable_tag() to permit setting options that
+ already exist, but are a different size, rather than asserting.
+ This corrects problems interacting with mis-behaving DHCP servers
+ that reply with modified versions of a DHCP option sent by the eCos
+ client, such as TAG_HOST_NAME.
+
+2005-10-24 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * include/network.h: Include <string.h> to stop warnings.
+
+2005-10-23 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * test/nc*_test_master.c: gettimeofday is now in POSIX
+
+2005-10-13 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * docs/manpages/sys/socketpair.2: Removed this man page since
+ socketpair(2) is not supported.
+
+2005-09-16 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * tests/server_test.c: use socklen_t.
+ * tests/nc_test_slave.c: use socklen_t and diag_print type fixes
+ to stop warnings with gcc4.x
+ * tests/tcp_echo.c: use socklen_t and diag_print type fixes to
+ stop warnings with gcc4.x
+ * tests/ping_test.c: use socklen_t.
+ * tests/dhcp_test.c: use socklen_t.
+
+2005-09-05 David Vrabel <dvrabel@arcom.com>
+ Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/tftp_client.c, include/tftp_support.h: const parameters
+ where appropriate.
+ * doc/tcpip.sgml: Update for the above.
+
2005-08-02 Andrew Lunn <andrew.lunn@ascom.ch>
* tests/ping_lo_test.c (ping_host): Use socklen_t to avoid
threads can have precedence over TFTP server processing."
}
+ cdl_component CYGPKG_NET_TFTPD_CLIENT_BIG_PACKET {
+ display "Extension to allow negotiation of big packets"
+ requires CYGINT_ISO_STDIO_FORMATTED_IO
+ flavor bool
+ default_value 0
+ description "
+ Implements RFC 2348, an optional extension
+ to the TFTP protocol to allow the client and
+ server to negotiate to use bigger
+ packets. This can make upload/download
+ faster"
+
+ cdl_option CYGPKG_NET_TFTPD_CLIENT_BIG_PACKET_SIZE {
+ display "Packet size to negotiate"
+ flavor data
+ default_value 512
+ legal_values 512 to 65464
+ description "
+ Size of the packets to negotiate. In an error
+ free environment, bigger packets will result
+ in faster transfers."
+ }
+ }
+
+
cdl_option CYGPKG_NET_TFTPD_THREAD_STACK_SIZE {
display "Stack size for TFTP threads."
flavor data
- default_value (CYGNUM_HAL_STACK_SIZE_TYPICAL+(3*(SEGSIZE+4)))
+ default_value { "(CYGNUM_HAL_STACK_SIZE_TYPICAL+(3*(SEGSIZE+4)))" }
description "
This option controls the size of the stack used for the
TFTP server. The default should be sufficient for most cases
network thread itself."
}
+ cdl_option CYGPKG_NET_DHCP_THREAD_STACK_SIZE {
+ display "Stack size for DHCP management threads."
+ flavor data
+ default_value { "(CYGNUM_HAL_STACK_SIZE_TYPICAL+sizeof(struct bootp))" }
+ description "
+ This option controls the size of the stack used for the
+ DHCP mamagement thread. The default should be
+ sufficient for most cases but some applications my
+ require bigger stacks when using for example diag_printf."
+ }
+
cdl_option CYGOPT_NET_DHCP_PARM_REQ_LIST_REPLACE {
display "Replace DHCP request options"
flavor booldata
.Pq RFC2553 .
.\"
.Sh BUGS
-The current implementation is not thread-safe.
-.Pp
The text was shamelessly copied from RFC2553.
<sect1 id="net-common-tcpip-manpages-getdomainname">
<title>getdomainname</title>
<screen>
-GETDOMAINNAME(3) System Library Functions Manual GETDOMAINNAME(3)
+GETDOMAINNAME(3) BSD Library Functions Manual GETDOMAINNAME(3)
NAME
getdomainname, setdomainname - get/set YP domain name of current host
<sect1 id="net-common-tcpip-manpages-gethostname">
<title>gethostname</title>
<screen>
-GETHOSTNAME(3) System Library Functions Manual GETHOSTNAME(3)
+GETHOSTNAME(3) BSD Library Functions Manual GETHOSTNAME(3)
NAME
gethostname, sethostname - get/set name of current host
<sect1 id="net-common-tcpip-manpages-byteorder">
<title>byteorder</title>
<screen>
-BYTEORDER(3) System Library Functions Manual BYTEORDER(3)
+BYTEORDER(3) BSD Library Functions Manual BYTEORDER(3)
NAME
htonl, htons, ntohl, ntohs, htobe32, htobe16, betoh32, betoh16, htole32,
be Big-endian (most significant byte first).
le Little-endian (least significant byte first).
- One of the specified orderings must be `h'. {size} will take these
+ One of the specified orderings must be 'h'. {size} will take these
forms:
- l Long (32-bit, used in conjunction with forms involving `n').
- s Short (16-bit, used in conjunction with forms involving `n').
+ l Long (32-bit, used in conjunction with forms involving 'n').
+ s Short (16-bit, used in conjunction with forms involving 'n').
16
16-bit.
32
The swap functions are of the form: swap{size}.
- Names involving `n' convert quantities between network byte order and
- host byte order. The last letter (`s' or `l') is a mnemonic for the tra-
+ Names involving 'n' convert quantities between network byte order and
+ host byte order. The last letter ('s' or 'l') is a mnemonic for the tra-
ditional names for such quantities, short and long, respectively. Today,
the C concept of short and long integers need not coincide with this tra-
ditional misunderstanding. On machines which have a byte order which is
macros.
The routines mentioned above which have either {src-order} or {dst-order}
- set to `n' are most often used in conjunction with Internet addresses and
+ set to 'n' are most often used in conjunction with Internet addresses and
ports as returned by gethostbyname(3) and getservent(3).
SEE ALSO
<sect1 id="net-common-tcpip-manpages-ethers">
<title>ethers</title>
<screen>
-ETHERS(3) System Library Functions Manual ETHERS(3)
+ETHERS(3) BSD Library Functions Manual ETHERS(3)
NAME
ether_aton, ether_ntoa, ether_addr, ether_ntohost, ether_hostton,
address into the structure passed. Both functions return zero if they
find the requested host name or address, and -1 if not.
- Each call reads /etc/ethers from the beginning; if a `+' appears alone on
+ Each call reads /etc/ethers from the beginning; if a '+' appears alone on
a line in the file, then ether_hostton() will consult the ethers.byname
YP map, and ether_ntohost() will consult the ethers.byaddr YP map.
<sect1 id="net-common-tcpip-manpages-getaddrinfo">
<title>getaddrinfo</title>
<screen>
-GETADDRINFO(3) System Library Functions Manual GETADDRINFO(3)
+GETADDRINFO(3) BSD Library Functions Manual GETADDRINFO(3)
NAME
getaddrinfo, freeaddrinfo, gai_strerror - nodename-to-address translation
<sect1 id="net-common-tcpip-manpages-gethostbyname">
<title>gethostbyname</title>
<screen>
-GETHOSTBYNAME(3) System Library Functions Manual GETHOSTBYNAME(3)
+GETHOSTBYNAME(3) BSD Library Functions Manual GETHOSTBYNAME(3)
NAME
gethostbyname, gethostbyname2, gethostbyaddr, gethostent, sethostent,
The herror() function prints an error message describing the failure. If
its argument string is non-null, it is prepended to the message string
- and separated from it by a colon (`:') and a space. The error message is
+ and separated from it by a colon (':') and a space. The error message is
printed with a trailing newline. The contents of the error message is
the same as that returned by hstrerror() with argument h_errno.
<sect1 id="net-common-tcpip-manpages-getifaddrs">
<title>getifaddrs</title>
<screen>
-GETIFADDRS(3) System Library Functions Manual GETIFADDRS(3)
+GETIFADDRS(3) BSD Library Functions Manual GETIFADDRS(3)
NAME
getifaddrs - get interface addresses
The getifaddrs() function first appeared in BSDI BSD/OS. The function is
supplied on OpenBSD since OpenBSD 2.7.
-BSD February 24, 2003 BSD
+BSD October 13, 2005 BSD
</screen>
</sect1>
<sect1 id="net-common-tcpip-manpages-getnameinfo">
<title>getnameinfo</title>
<screen>
-GETNAMEINFO(3) System Library Functions Manual GETNAMEINFO(3)
+GETNAMEINFO(3) BSD Library Functions Manual GETNAMEINFO(3)
NAME
getnameinfo - address-to-nodename translation in protocol-independent
<sect1 id="net-common-tcpip-manpages-getnetent">
<title>getnetent</title>
<screen>
-GETNETENT(3) System Library Functions Manual GETNETENT(3)
+GETNETENT(3) BSD Library Functions Manual GETNETENT(3)
NAME
getnetent, getnetbyaddr, getnetbyname, setnetent, endnetent - get network
<sect1 id="net-common-tcpip-manpages-getprotoent">
<title>getprotoent</title>
<screen>
-GETPROTOENT(3) System Library Functions Manual GETPROTOENT(3)
+GETPROTOENT(3) BSD Library Functions Manual GETPROTOENT(3)
NAME
getprotoent, getprotobynumber, getprotobyname, setprotoent, endprotoent -
<sect1 id="net-common-tcpip-manpages-getrrsetbyname">
<title>getrrsetbyname</title>
<screen>
-GETRRSETBYNAME(3) System Library Functions Manual GETRRSETBYNAME(3)
+GETRRSETBYNAME(3) BSD Library Functions Manual GETRRSETBYNAME(3)
NAME
getrrsetbyname - retrieve DNS records
<sect1 id="net-common-tcpip-manpages-getservent">
<title>getservent</title>
<screen>
-GETSERVENT(3) System Library Functions Manual GETSERVENT(3)
+GETSERVENT(3) BSD Library Functions Manual GETSERVENT(3)
NAME
getservent, getservbyport, getservbyname, setservent, endservent - get
<sect1 id="net-common-tcpip-manpages-if-nametoindex">
<title>if_nametoindex</title>
<screen>
-IF_NAMETOINDEX(3) System Library Functions Manual IF_NAMETOINDEX(3)
+IF_NAMETOINDEX(3) BSD Library Functions Manual IF_NAMETOINDEX(3)
NAME
if_nametoindex, if_indextoname, if_nameindex, if_freenameindex - convert
<sect1 id="net-common-tcpip-manpages-inet">
<title>inet</title>
<screen>
-INET(3) System Library Functions Manual INET(3)
+INET(3) BSD Library Functions Manual INET(3)
NAME
inet_addr, inet_aton, inet_lnaof, inet_makeaddr, inet_netof,
DESCRIPTION
The routines inet_aton(), inet_addr() and inet_network() interpret char-
- acter strings representing numbers expressed in the Internet standard `.'
+ acter strings representing numbers expressed in the Internet standard '.'
notation. The inet_pton() function converts a presentation format
address (that is, printable form as held in a character string) to net-
work format (usually a struct in_addr or some other internal binary rep-
NULL if a system error occurs (in which case, errno will have been set),
or it returns a pointer to the destination string. The routine
inet_ntoa() takes an Internet address and returns an ASCII string repre-
- senting the address in `.' notation. The routine inet_makeaddr() takes
+ senting the address in '.' notation. The routine inet_makeaddr() takes
an Internet network number and a local network address and constructs an
Internet address from it. The routines inet_netof() and inet_lnaof()
break apart Internet host addresses, returning the network number and
as machine format integer values.
INTERNET ADDRESSES (IP VERSION 4)
- Values specified using the `.' notation take one of the following forms:
+ Values specified using the '.' notation take one of the following forms:
a.b.c.d
a.b.c
When only one part is given, the value is stored directly in the network
address without any byte rearrangement.
- All numbers supplied as ``parts'' in a `.' notation may be decimal,
+ All numbers supplied as ``parts'' in a '.' notation may be decimal,
octal, or hexadecimal, as specified in the C language (i.e., a leading 0x
or 0X implies hexadecimal; otherwise, a leading 0 implies octal; other-
wise, the number is interpreted as decimal).
<sect1 id="net-common-tcpip-manpages-inet6-option-space">
<title>inet6_option_space</title>
<screen>
-INET6_OPTION_SPACE(3) System Library Functions Manual INET6_OPTION_SPACE(3)
+INET6_OPTION_SPACE(3) BSD Library Functions Manual INET6_OPTION_SPACE(3)
NAME
inet6_option_space, inet6_option_init, inet6_option_append,
<sect1 id="net-common-tcpip-manpages-inet6-rthdr-space">
<title>inet6_rthdr_space</title>
<screen>
-INET6_RTHDR_SPACE(3) System Library Functions Manual INET6_RTHDR_SPACE(3)
+INET6_RTHDR_SPACE(3) BSD Library Functions Manual INET6_RTHDR_SPACE(3)
NAME
inet6_rthdr_space, inet6_rthdr_init, inet6_rthdr_add,
<sect1 id="net-common-tcpip-manpages-inet-net">
<title>inet_net</title>
<screen>
-INET_NET(3) System Library Functions Manual INET_NET(3)
+INET_NET(3) BSD Library Functions Manual INET_NET(3)
NAME
inet_net_ntop, inet_net_pton - Internet network number manipulation rou-
When only one part is given, the value is stored directly in the Internet
network number without any byte rearrangement.
- All numbers supplied as ``parts'' in a `.' notation may be decimal,
+ All numbers supplied as ``parts'' in a '.' notation may be decimal,
octal, or hexadecimal, as specified in the C language (i.e., a leading 0x
or 0X implies hexadecimal; otherwise, a leading 0 implies octal; other-
wise, the number is interpreted as decimal).
<sect1 id="net-common-tcpip-manpages-ipx">
<title>ipx</title>
<screen>
-IPX(3) System Library Functions Manual IPX(3)
+IPX(3) BSD Library Functions Manual IPX(3)
NAME
ipx_addr, ipx_ntoa - IPX address conversion routines
Trailing zero fields are suppressed, and each number is printed in hex-
adecimal, in a format suitable for input to ipx_addr(). Any fields lack-
- ing super-decimal digits will have a trailing `H' appended.
+ ing super-decimal digits will have a trailing 'H' appended.
An effort has been made to ensure that ipx_addr() be compatible with most
formats in common use. It will first separate an address into 1 to 3
- fields using a single delimiter chosen from period (`.'), colon (`:'), or
- pound-sign (`#'). Each field is then examined for byte separators (colon
+ fields using a single delimiter chosen from period ('.'), colon (':'), or
+ pound-sign ('#'). Each field is then examined for byte separators (colon
or period). If there are byte separators, each subfield separated is
taken to be a small hexadecimal number, and the entirety is taken as a
network-byte-ordered quantity to be zero extended in the high-network-
order bytes. Next, the field is inspected for hyphens, in which case the
field is assumed to be a number in decimal notation with hyphens separat-
ing the millenia. Next, the field is assumed to be a number: It is
- interpreted as hexadecimal if there is a leading `0x' (as in C), a trail-
- ing `H' (as in Mesa), or there are any super-decimal digits present. It
- is interpreted as octal is there is a leading `0' and there are no super-
+ interpreted as hexadecimal if there is a leading '0x' (as in C), a trail-
+ ing 'H' (as in Mesa), or there are any super-decimal digits present. It
+ is interpreted as octal is there is a leading '0' and there are no super-
octal digits. Otherwise, it is converted as a decimal number.
RETURN VALUES
<sect1 id="net-common-tcpip-manpages-iso-addr">
<title>iso_addr</title>
<screen>
-ISO_ADDR(3) System Library Functions Manual ISO_ADDR(3)
+ISO_ADDR(3) BSD Library Functions Manual ISO_ADDR(3)
NAME
iso_addr, iso_ntoa - network address conversion routines for Open System
<sect1 id="net-common-tcpip-manpages-link-addr">
<title>link_addr</title>
<screen>
-LINK_ADDR(3) System Library Functions Manual LINK_ADDR(3)
+LINK_ADDR(3) BSD Library Functions Manual LINK_ADDR(3)
NAME
link_addr, link_ntoa - elementary address specification routines for link
<sect1 id="net-common-tcpip-manpages-net-addrcmp">
<title>net_addrcmp</title>
<screen>
-NET_ADDRCMP(3) System Library Functions Manual NET_ADDRCMP(3)
+NET_ADDRCMP(3) BSD Library Functions Manual NET_ADDRCMP(3)
NAME
net_addrcmp - compare socket address structures
<sect1 id="net-common-tcpip-manpages-ns">
<title>ns</title>
<screen>
-NS(3) System Library Functions Manual NS(3)
+NS(3) BSD Library Functions Manual NS(3)
NAME
ns_addr, ns_ntoa - Xerox NS(tm) address conversion routines
Trailing zero fields are suppressed, and each number is printed in hex-
adecimal, in a format suitable for input to ns_addr(). Any fields lack-
- ing super-decimal digits will have a trailing `H' appended.
+ ing super-decimal digits will have a trailing 'H' appended.
Unfortunately, no universal standard exists for representing XNS
addresses. An effort has been made to ensure that ns_addr() be compati-
ble with most formats in common use. It will first separate an address
- into 1 to 3 fields using a single delimiter chosen from period (`.'),
- colon (`:'), or pound-sign `#'. Each field is then examined for byte
+ into 1 to 3 fields using a single delimiter chosen from period ('.'),
+ colon (':'), or pound-sign '#'. Each field is then examined for byte
separators (colon or period). If there are byte separators, each sub-
field separated is taken to be a small hexadecimal number, and the
entirety is taken as a network-byte-ordered quantity to be zero extended
hyphens, in which case the field is assumed to be a number in decimal
notation with hyphens separating the millenia. Next, the field is
assumed to be a number: It is interpreted as hexadecimal if there is a
- leading `0x' (as in C), a trailing `H' (as in Mesa), or there are any
+ leading '0x' (as in C), a trailing 'H' (as in Mesa), or there are any
super-decimal digits present. It is interpreted as octal is there is a
- leading `0' and there are no super-octal digits. Otherwise, it is con-
+ leading '0' and there are no super-octal digits. Otherwise, it is con-
verted as a decimal number.
RETURN VALUES
<sect1 id="net-common-tcpip-manpages-resolver">
<title>resolver</title>
<screen>
-RESOLVER(3) System Library Functions Manual RESOLVER(3)
+RESOLVER(3) BSD Library Functions Manual RESOLVER(3)
NAME
res_query, res_search, res_mkquery, res_send, res_init, dn_comp,
<sect1 id="net-common-tcpip-manpages-accept">
<title>accept</title>
<screen>
-ACCEPT(2) System Calls Manual ACCEPT(2)
+ACCEPT(2) BSD System Calls Manual ACCEPT(2)
NAME
accept - accept a connection on a socket
<sect1 id="net-common-tcpip-manpages-bind">
<title>bind</title>
<screen>
-BIND(2) System Calls Manual BIND(2)
+BIND(2) BSD System Calls Manual BIND(2)
NAME
bind - bind a name to a socket
<sect1 id="net-common-tcpip-manpages-connect">
<title>connect</title>
<screen>
-CONNECT(2) System Calls Manual CONNECT(2)
+CONNECT(2) BSD System Calls Manual CONNECT(2)
NAME
connect - initiate a connection on a socket
<sect1 id="net-common-tcpip-manpages-getpeername">
<title>getpeername</title>
<screen>
-GETPEERNAME(2) System Calls Manual GETPEERNAME(2)
+GETPEERNAME(2) BSD System Calls Manual GETPEERNAME(2)
NAME
getpeername - get name of connected peer
<sect1 id="net-common-tcpip-manpages-getsockname">
<title>getsockname</title>
<screen>
-GETSOCKNAME(2) System Calls Manual GETSOCKNAME(2)
+GETSOCKNAME(2) BSD System Calls Manual GETSOCKNAME(2)
NAME
getsockname - get socket name
<sect1 id="net-common-tcpip-manpages-getsockopt">
<title>getsockopt</title>
<screen>
-GETSOCKOPT(2) System Calls Manual GETSOCKOPT(2)
+GETSOCKOPT(2) BSD System Calls Manual GETSOCKOPT(2)
NAME
getsockopt, setsockopt - get and set options on sockets
<sect1 id="net-common-tcpip-manpages-ioctl">
<title>ioctl</title>
<screen>
-IOCTL(2) System Calls Manual IOCTL(2)
+IOCTL(2) BSD System Calls Manual IOCTL(2)
NAME
ioctl - control device
<sect1 id="net-common-tcpip-manpages-poll">
<title>poll</title>
<screen>
-POLL(2) System Calls Manual POLL(2)
+POLL(2) BSD System Calls Manual POLL(2)
NAME
poll - synchronous I/O multiplexing
<sect1 id="net-common-tcpip-manpages-select">
<title>select</title>
<screen>
-SELECT(2) System Calls Manual SELECT(2)
+SELECT(2) BSD System Calls Manual SELECT(2)
NAME
select - synchronous I/O multiplexing
<sect1 id="net-common-tcpip-manpages-send">
<title>send</title>
<screen>
-SEND(2) System Calls Manual SEND(2)
+SEND(2) BSD System Calls Manual SEND(2)
NAME
send, sendto, sendmsg - send a message from a socket
<sect1 id="net-common-tcpip-manpages-shutdown">
<title>shutdown</title>
<screen>
-SHUTDOWN(2) System Calls Manual SHUTDOWN(2)
+SHUTDOWN(2) BSD System Calls Manual SHUTDOWN(2)
NAME
shutdown - shut down part of a full-duplex connection
<sect1 id="net-common-tcpip-manpages-socket">
<title>socket</title>
<screen>
-SOCKET(2) System Calls Manual SOCKET(2)
+SOCKET(2) BSD System Calls Manual SOCKET(2)
NAME
socket - create an endpoint for communication
HISTORY
The socket() function call appeared in 4.2BSD.
-BSD June 4, 1993 BSD
- </screen>
- </sect1>
-
- <sect1 id="net-common-tcpip-manpages-socketpair">
- <title>socketpair</title>
- <screen>
-SOCKETPAIR(2) System Calls Manual SOCKETPAIR(2)
-
-NAME
- socketpair - create a pair of connected sockets
-
-SYNOPSIS
- #include <sys/types.h>
- #include <sys/socket.h>
-
- int
- socketpair(int d, int type, int protocol, int *sv);
-
-DESCRIPTION
- The socketpair() call creates an unnamed pair of connected sockets in the
- specified domain d, of the specified type, and using the optionally spec-
- ified protocol. The descriptors used in referencing the new sockets are
- returned in sv[0] and sv[1]. The two sockets are indistinguishable.
-
-RETURN VALUES
- A 0 is returned if the call succeeds, -1 if it fails.
-
-ERRORS
- The call succeeds unless:
-
- [EMFILE] Too many descriptors are in use by this process.
-
- [EAFNOSUPPORT] The specified address family is not supported on this
- machine.
-
- [EPROTONOSUPPORT] The specified protocol is not supported on this
- machine.
-
- [EOPNOTSUPP] The specified protocol does not support creation of
- socket pairs.
-
- [EFAULT] The address sv does not specify a valid part of the
- process address space.
-
- [ENFILE] The system file table is full.
-
-SEE ALSO
- pipe(2), read(2), write(2)
-
-BUGS
- This call is currently implemented only for the LOCAL domain. Many oper-
- ating systems only accept a protocol of PF_UNSPEC, so that should be used
- instead of PF_LOCAL for maximal portability.
-
-STANDARDS
- The socketpair() function conforms to X/Open Portability Guide Issue 4.2
- (``XPG4.2'').
-
-HISTORY
- The socketpair() function call appeared in 4.2BSD.
-
BSD June 4, 1993 BSD
</screen>
</sect1>
<PARA>
The new API is as follows:
</PARA>
-<PROGRAMLISTING>int tftp_client_get(char *filename,
- char *server,
- int port,
+<PROGRAMLISTING>int tftp_client_get(const char * const filename,
+ const char * const server,
+ const int port,
char *buf,
int len,
- int mode,
- int *err);
+ const int mode,
+ int * const err);
-int tftp_client_put(char *filename,
- char *server,
- int port,
- char *buf,
+int tftp_client_put(const char * const filename,
+ const char * const server,
+ const int port,
+ const char *buf,
int len,
- int mode,
- int *err);
+ const int mode,
+ int *const err);
</PROGRAMLISTING>
<PARA>Currently <varname>server</varname> can only be a numeric IPv4 or
IPv6 address. The resolver is currently not used, but it is planned to
</PARA>
<PARA>
The deprecated API is:
-<PROGRAMLISTING>int tftp_client_get(char *filename,
- struct sockaddr_in *server,
- char *buf,
- int len,
- int mode,
- int *err);
+<PROGRAMLISTING>
+int tftp_get(const char * const filename,
+ const struct sockaddr_in * const server,
+ char * buf,
+ int len,
+ const int mode,
+ int * const error);
-int tftp_client_put(char *filename,
- struct sockaddr_in *server,
- char *buf,
- int len,
- int mode,
- int *err);
+int tftp_put(const char * const filename,
+ const struct sockaddr_in * const server,
+ const char * buffer,
+ int len,
+ const int mode,
+ int * const err);
</PROGRAMLISTING>
</PARA>
<PARA>
#define DATA 03 /* data packet */
#define ACK 04 /* acknowledgement */
#define ERROR 05 /* error code */
+#define OACK 06 /* option acknowledge */
struct tftphdr {
short th_opcode; /* packet type */
#include <netinet/ip.h>
#include <netinet/ip_icmp.h>
#include <net/route.h>
+#include <string.h>
#include <cyg/infra/diag.h>
#include <cyg/kernel/kapi.h>
*/
/* IPv4 and IPv6 */
-__externC int tftp_client_get(char *, char *, int, char *, int, int, int *);
-__externC int tftp_client_put(char *, char *, int, char *, int, int, int *);
+__externC int tftp_client_get(const char * const filename,
+ const char * const server,
+ const int port,
+ char * buff,
+ int len,
+ const int mode,
+ int * const err);
+
+__externC int tftp_client_put(const char * const filename,
+ const char * const server,
+ const int port,
+ const char * buf,
+ int len,
+ const int mode,
+ int * const err);
/* IPv4 only */
-__externC int tftp_get(char *, struct sockaddr_in *, char *, int, int, int *);
-__externC int tftp_put(char *, struct sockaddr_in *, char *, int, int, int *);
+__externC int tftp_get(const char * const filename,
+ const struct sockaddr_in * const server,
+ char * buf,
+ int len,
+ const int mode,
+ int * const error);
+
+__externC int tftp_put(const char * const filename,
+ const struct sockaddr_in * const server,
+ const char * buffer,
+ int len,
+ const int mode,
+ int * const err);
#define TFTP_TIMEOUT_PERIOD 5 // Seconds between retries
#define TFTP_TIMEOUT_MAX 50 // Max timeouts over all blocks
}
#endif
+/* Forward reference prototypes. */
+static int unset_tag( struct bootp *ppkt, unsigned char tag );
+
// ------------------------------------------------------------------------
// Returns a pointer to the end of dhcp message (or NULL if invalid)
// meaning the address of the byte *after* the TAG_END token in the vendor
}
if (*op == tag) // Found it...
break;
- op += *(op+1)+2;
+ if ( *op == TAG_PAD ) {
+ op++;
+ } else {
+ op += *(op+1)+2;
+ }
}
if (*op == tag) { // Found it...
+ /* There are three possibilities:
+ * 1) *(op+1) == len
+ * 2) *(op+1) > len
+ * 3) *(op+1) < len
+ * For 1, just overwrite the existing option data.
+ * For 2, overwrite the existing option data and pullup the
+ * remaining option data (if any).
+ * For 3, pullup any remaining option data to remove the option
+ * and then add the option to the end.
+ * For simplicity, for case 2 and 3, we just call unset_tag()
+ * and re-add the option to the end.
+ */
if ( *(op+1) != len ) {
- CYG_FAIL( "Wrong size in set_fixed_tag" );
- return false; // wrong size
+ /* Remove existing option entry. */
+ unset_tag(ppkt, tag);
+ /* Adjust the op pointer to re-add at the end. */
+ op = scan_dhcp_size(ppkt);
+ CYG_ASSERT(op!=NULL, "Invalid options size in set_fixed_tag" );
+ op--;
+ CYG_ASSERT(*op==TAG_END, "Missing TAG_END in set_fixed_tag");
+ if ( op + len + 2 > &ppkt->bp_vend[BP_VEND_LEN-1] ) {
+ CYG_FAIL( "Oversize DHCP packet in set_fixed_tag replace" );
+ return false;
+ }
+ *op = tag;
+ *(op+1) = len;
+ *(op + len + 2) = TAG_END;
}
}
else { // overwrite the end tag and install a new one
return true;
}
-// Note that this does not permit changing the size of an extant tag.
static int
set_variable_tag( struct bootp *ppkt,
unsigned char tag,
}
if (*op == tag) // Found it...
break;
- op += *(op+1)+2;
+ if ( *op == TAG_PAD ) {
+ op++;
+ } else {
+ op += *(op+1)+2;
+ }
}
if (*op == tag) { // Found it...
+ /* There are three possibilities:
+ * 1) *(op+1) == len
+ * 2) *(op+1) > len
+ * 3) *(op+1) < len
+ * For 1, just overwrite the existing option data.
+ * For 2, overwrite the existing option data and pullup the
+ * remaining option data (if any).
+ * For 3, pullup any remaining option data to remove the option
+ * and then add the option to the end.
+ * For simplicity, for case 2 and 3, we just call unset_tag()
+ * and re-add the option to the end.
+ */
if ( *(op+1) != len ) {
- CYG_FAIL( "Wrong size in set_variable_tag" );
- return false; // wrong size
+ /* Remove existing option entry. */
+ unset_tag(ppkt, tag);
+ /* Adjust the op pointer to re-add at the end. */
+ op = scan_dhcp_size(ppkt);
+ CYG_ASSERT(op!=NULL, "Invalid options size in set_variable_tag" );
+ op--;
+ CYG_ASSERT(*op==TAG_END, "Missing TAG_END in set_variable_tag");
+ if ( op + len + 2 > &ppkt->bp_vend[BP_VEND_LEN-1] ) {
+ CYG_FAIL( "Oversize DHCP packet in set_variable_tag replace" );
+ return false;
+ }
+ *op = tag;
+ *(op+1) = len;
+ *(op + len + 2) = TAG_END;
}
}
else { // overwrite the end tag and install a new one
killp = op; // item to kill
nextp = op + *(op+1)+2; // next item address
}
- op += *(op+1)+2; // scan to the end
+ if ( *op == TAG_PAD ) {
+ op++;
+ } else {
+ op += *(op+1)+2;
+ }
}
if ( !killp )
// ------------------------------------------------------------------------
// The management thread function
+//
+// Note: 2007-01-15
+// This single management thread attempts to keep all configured
+// interfaces alive via DHCP. While this may be sufficient for
+// many systems, it falls short of perfect. There should probably
+// be a separate thread for each possible interface, along with
+// appropriate CDL to control how each inteface is managed.
+//
void dhcp_mgt_entry( cyg_addrword_t loop_on_failure )
{
int j;
+ bool any_interfaces_up;
+
while ( 1 ) {
while ( 1 ) {
cyg_semaphore_wait( &dhcp_needs_attention );
dhcp_halt(); // tear everything down
if ( !loop_on_failure )
return; // exit the thread/return
- init_all_network_interfaces(); // re-initialize
+ do {
+ init_all_network_interfaces(); // re-initialize
+ // If at least one interface is up, then the DHCP machine will run
+ any_interfaces_up = false;
+#ifdef CYGHWR_NET_DRIVER_ETH0
+ any_interfaces_up |= eth0_up;
+#endif
+#ifdef CYGHWR_NET_DRIVER_ETH1
+ any_interfaces_up |= eth1_up;
+#endif
+ } while (!any_interfaces_up);
for ( j = 0; j < CYGPKG_NET_NLOOP; j++ )
init_loopback_interface( j );
#ifdef CYGPKG_SNMPAGENT
cyg_handle_t dhcp_mgt_thread_h = 0;
cyg_thread dhcp_mgt_thread;
-#define STACK_SIZE (CYGNUM_HAL_STACK_SIZE_TYPICAL + sizeof(struct bootp))
-static cyg_uint8 dhcp_mgt_stack[ STACK_SIZE ];
+static cyg_uint8 dhcp_mgt_stack[ CYGPKG_NET_DHCP_THREAD_STACK_SIZE ];
void dhcp_start_dhcp_mgt_thread( void )
{
if ( ! dhcp_mgt_thread_h ) {
cyg_semaphore_init( &dhcp_needs_attention, 0 );
cyg_thread_create(
- CYGPKG_NET_DHCP_THREAD_PRIORITY, /* scheduling info (eg pri) */
- dhcp_mgt_entry, /* entry point function */
+ CYGPKG_NET_DHCP_THREAD_PRIORITY, /* scheduling info (eg pri) */
+ dhcp_mgt_entry, /* entry point function */
CYGOPT_NET_DHCP_DHCP_THREAD_PARAM, /* entry data */
- "DHCP lease mgt", /* optional thread name */
- dhcp_mgt_stack, /* stack base, NULL = alloc */
- STACK_SIZE, /* stack size, 0 = default */
- &dhcp_mgt_thread_h, /* returned thread handle */
- &dhcp_mgt_thread /* put thread here */
+ "DHCP lease mgt", /* optional thread name */
+ dhcp_mgt_stack, /* stack base, NULL = alloc */
+ CYGPKG_NET_DHCP_THREAD_STACK_SIZE, /* stack size, 0 = default */
+ &dhcp_mgt_thread_h, /* returned thread handle */
+ &dhcp_mgt_thread /* put thread here */
);
cyg_thread_resume(dhcp_mgt_thread_h);
#include <network.h>
#include <arpa/tftp.h>
#include <tftp_support.h>
+#include <stdlib.h>
+#include <stdio.h>
#define min(x,y) (x<y ? x : y)
// On error, *err will hold the reason.
// This version uses the server name. This can be a name for DNS lookup
// or a dotty or colony number format for IPv4 or IPv6.
-int tftp_client_get(char *filename,
- char *server,
- int port,
- char *buf,
- int len,
- int mode,
- int *err) {
-
+static int tftp_client_get_inner(char *data,
+ const char * const filename,
+ const char * const server,
+ const int port,
+ char *buf,
+ int len,
+ const int mode,
+ int * const err
+#ifdef CYGPKG_NET_TFTPD_CLIENT_BIG_PACKET
+ ,int negotiate
+#endif
+ ) {
+
+ int blksize=SEGSIZE;
int result = 0;
int s=-1;
int actual_len, data_len;
int error;
struct sockaddr local_addr, from_addr;
- char data[SEGSIZE+sizeof(struct tftphdr)];
struct tftphdr *hdr = (struct tftphdr *)data;
- char *cp, *fp;
+ const char *fp;
+ char *cp, *bp;
struct timeval timeout;
unsigned short last_good_block = 0;
fd_set fds;
}
while (*fp) *cp++ = *fp++;
*cp++ = '\0';
+#ifdef CYGPKG_NET_TFTPD_CLIENT_BIG_PACKET
+ if (negotiate) {
+ fp="blksize";
+ while (*fp)
+ *cp++ = *fp++;
+ *cp++ = '\0';
+ cp+=sprintf(cp, "%d", CYGPKG_NET_TFTPD_CLIENT_BIG_PACKET_SIZE);
+ *cp++ = '\0';
+ }
+#endif
memset(&hints,0,sizeof(hints));
hints.ai_family = PF_UNSPEC;
addrinfo = res;
while (addrinfo) {
s = socket(addrinfo->ai_family, addrinfo->ai_socktype,
- addrinfo->ai_protocol);
+ addrinfo->ai_protocol);
if (s >= 0) {
- memcpy(&local_addr,addrinfo->ai_addr,addrinfo->ai_addrlen);
- switch(addrinfo->ai_addr->sa_family) {
- case AF_INET: {
- struct sockaddr_in * saddr =
- (struct sockaddr_in *) addrinfo->ai_addr;
- struct sockaddr_in * laddr =
- (struct sockaddr_in *) &local_addr;
- if (port) {
- saddr->sin_port = htons(port);
- }
- laddr->sin_port = htons(get_port++);
- laddr->sin_addr.s_addr = INADDR_ANY;
- break;
- }
+ memcpy(&local_addr,addrinfo->ai_addr,addrinfo->ai_addrlen);
+ switch(addrinfo->ai_addr->sa_family) {
+ case AF_INET: {
+ struct sockaddr_in * saddr =
+ (struct sockaddr_in *) addrinfo->ai_addr;
+ struct sockaddr_in * laddr =
+ (struct sockaddr_in *) &local_addr;
+ if (port) {
+ saddr->sin_port = htons(port);
+ }
+ laddr->sin_port = htons(get_port++);
+ laddr->sin_addr.s_addr = INADDR_ANY;
+ break;
+ }
#ifdef CYGPKG_NET_INET6
- case AF_INET6: {
- struct sockaddr_in6 * saddr =
- (struct sockaddr_in6 *) addrinfo->ai_addr;
- struct sockaddr_in6 * laddr =
- (struct sockaddr_in6 *) &local_addr;
- if (port) {
- saddr->sin6_port = htons(port);
- }
- laddr->sin6_port = htons(get_port++);
- laddr->sin6_addr = in6addr_any;
- break;
- }
+ case AF_INET6: {
+ struct sockaddr_in6 * saddr =
+ (struct sockaddr_in6 *) addrinfo->ai_addr;
+ struct sockaddr_in6 * laddr =
+ (struct sockaddr_in6 *) &local_addr;
+ if (port) {
+ saddr->sin6_port = htons(port);
+ }
+ laddr->sin6_port = htons(get_port++);
+ laddr->sin6_addr = in6addr_any;
+ break;
+ }
#endif
- default:
- *err = TFTP_NETERR;
- goto out;
- }
+ default:
+ *err = TFTP_NETERR;
+ goto out;
+ }
- if (bind(s,&local_addr,addrinfo->ai_addrlen) < 0) {
+ if (bind(s,&local_addr,addrinfo->ai_addrlen) < 0) {
*err = TFTP_NETERR;
goto out;
}
-
- // Send request
- if (sendto(s, data, (int)(cp-data), 0,
- addrinfo->ai_addr,
- addrinfo->ai_addrlen) < 0) {
- // Problem sending request
- *err = TFTP_NETERR;
- goto nextaddr;
- }
+
+ // Send request
+ if (sendto(s, data, (int)(cp-data), 0,
+ addrinfo->ai_addr,
+ addrinfo->ai_addrlen) < 0) {
+ // Problem sending request
+ *err = TFTP_NETERR;
+ goto nextaddr;
+ }
- // Read data
- fp = buf;
- while (true) {
- timeout.tv_sec = TFTP_TIMEOUT_PERIOD;
- timeout.tv_usec = 0;
- FD_ZERO(&fds);
- FD_SET(s, &fds);
- if (select(s+1, &fds, 0, 0, &timeout) <= 0) {
+ // Read data
+ bp = buf;
+ while (true) {
+ timeout.tv_sec = TFTP_TIMEOUT_PERIOD;
+ timeout.tv_usec = 0;
+ FD_ZERO(&fds);
+ FD_SET(s, &fds);
+ if (select(s+1, &fds, 0, 0, &timeout) <= 0) {
total_timeouts++;
if ((last_good_block == 0) && (total_timeouts > TFTP_RETRIES_MAX)) {
- // Timeout - no data received. Probably no server.
- *err = TFTP_TIMEOUT;
- goto nextaddr;
+ // Timeout - no data received. Probably no server.
+ *err = TFTP_TIMEOUT;
+ goto nextaddr;
}
- if (total_timeouts > TFTP_TIMEOUT_MAX) {
+ if (total_timeouts > TFTP_TIMEOUT_MAX) {
// Timeout - have received data. Network problem?
*err = TFTP_TIMEOUT;
goto out;
- }
+ }
if (last_good_block == 0 ) {
// Send request
goto out;
}
}
- } else {
- recv_len = sizeof(data);
- from_len = sizeof(from_addr);
- if ((data_len = recvfrom(s, &data, recv_len, 0,
- &from_addr, &from_len)) < 0) {
- // What happened?
- *err = TFTP_NETERR;
- goto out;
- }
- if (ntohs(hdr->th_opcode) == DATA) {
- actual_len = 0;
- if (ntohs(hdr->th_block) == (last_good_block+1)) {
- // Consume this data
- cp = hdr->th_data;
- data_len -= 4; /* Sizeof TFTP header */
- actual_len = data_len;
- result += actual_len;
- while (data_len-- > 0) {
- if (len-- > 0) {
- *fp++ = *cp++;
- } else {
- // Buffer overflow
- *err = TFTP_TOOLARGE;
- goto out;
- }
- }
- last_good_block++;
- } else {
- // To prevent an out-of-sequence packet from
- // terminating transmission prematurely, set
- // actual_len to a full size packet.
- actual_len = SEGSIZE;
- }
- // Send out the ACK
- hdr->th_opcode = htons(ACK);
- hdr->th_block = htons(last_good_block);
- if (sendto(s, data, 4 /* FIXME */, 0,
- &from_addr, from_len) < 0) {
- // Problem sending request
- *err = TFTP_NETERR;
- goto out;
- }
- // A short packet marks the end of the file.
- if ((actual_len >= 0) && (actual_len < SEGSIZE)) {
- // End of data
- close(s);
- freeaddrinfo(res);
- return result;
- }
- } else
- if (ntohs(hdr->th_opcode) == ERROR) {
- *err = ntohs(hdr->th_code);
- goto out;
- } else {
- // What kind of packet is this?
- *err = TFTP_PROTOCOL;
- goto out;
- }
- }
- }
+ } else {
+ recv_len = blksize+sizeof(struct tftphdr);
+ from_len = sizeof(from_addr);
+ if ((data_len = recvfrom(s, data, recv_len, 0,
+ &from_addr, &from_len)) < 0) {
+ // What happened?
+ *err = TFTP_NETERR;
+ goto out;
+ }
+#ifdef CYGPKG_NET_TFTPD_CLIENT_BIG_PACKET
+ if (ntohs(hdr->th_opcode) == OACK) {
+ // We can have only *one* option, the one we sent..
+ if (strncmp(data+2, "blksize", data_len)==0) {
+ blksize=atol(data+2+strlen("blksize")+1);
+ } else {
+ // option ignored, use default.
+ }
+ // Send out the ACK
+ hdr->th_opcode = htons(ACK);
+ hdr->th_block = htons(last_good_block);
+ if (sendto(s, data, 4 /* FIXME */, 0,
+ &from_addr, from_len) < 0) {
+ // Problem sending request
+ *err = TFTP_NETERR;
+ goto out;
+ }
+ } else
+#endif
+ if (ntohs(hdr->th_opcode) == DATA) {
+ actual_len = 0;
+ if (ntohs(hdr->th_block) == (last_good_block+1)) {
+ // Consume this data
+ cp = hdr->th_data;
+ data_len -= 4; /* Sizeof TFTP header */
+ actual_len = data_len;
+ result += actual_len;
+ if (len<data_len)
+ {
+ // Buffer overflow
+ *err = TFTP_TOOLARGE;
+ goto out;
+ }
+ memcpy(bp, cp, data_len);
+ bp+=data_len;
+ len-=data_len;
+ last_good_block++;
+ } else {
+ // To prevent an out-of-sequence packet from
+ // terminating transmission prematurely, set
+ // actual_len to a full size packet.
+ actual_len = blksize;
+ }
+ // Send out the ACK
+ hdr->th_opcode = htons(ACK);
+ hdr->th_block = htons(last_good_block);
+ if (sendto(s, data, 4 /* FIXME */, 0,
+ &from_addr, from_len) < 0) {
+ // Problem sending request
+ *err = TFTP_NETERR;
+ goto out;
+ }
+ // A short packet marks the end of the file.
+ /* 4 = Sizeof TFTP header */
+ if ((actual_len >= 0) && (actual_len < blksize)) {
+ // End of data
+ close(s);
+ freeaddrinfo(res);
+ return result;
+ }
+ } else
+ if (ntohs(hdr->th_opcode) == ERROR) {
+ *err = ntohs(hdr->th_code);
+ goto out;
+ } else {
+ // What kind of packet is this?
+ *err = TFTP_PROTOCOL;
+ goto out;
+ }
+ }
+ }
}
// If we got here, it means there was a problem connecting to the
// server. Try the next address returned by getaddrinfo
nextaddr:
if (-1 != s) {
- close(s);
+ close(s);
}
addrinfo=addrinfo->ai_next;
}
freeaddrinfo(res);
return -1;
}
+
+
+int tftp_client_get(const char * const filename,
+ const char * const server,
+ const int port,
+ char *buf,
+ int len,
+ const int mode,
+ int * const err) {
+ int result;
+#ifdef CYGPKG_NET_TFTPD_CLIENT_BIG_PACKET
+ char *data = malloc(CYGPKG_NET_TFTPD_CLIENT_BIG_PACKET_SIZE+
+ sizeof(struct tftphdr));
+ if (data==NULL) {
+ *err=TFTP_ENOSPACE;
+ return -1;
+ }
+#else
+ char data[SEGSIZE+sizeof(struct tftphdr)];
+#endif
+ result=tftp_client_get_inner(data, filename, server,
+ port, buf, len, mode, err
+#ifdef CYGPKG_NET_TFTPD_CLIENT_BIG_PACKET
+ ,1
+#endif
+ );
+ if (result<0)
+ {
+#ifdef CYGPKG_NET_TFTPD_CLIENT_BIG_PACKET
+ // try without negotiating packet size. The serves that do
+ // not support options negotiation may or may not ignore the
+ // options. If they return an error in the case of options
+ // this code path will try without packet size negotiation.
+ result=tftp_client_get_inner(data, filename, server,
+ port, buf, len, mode, err,
+ 0);
+#endif
+ }
+
+#ifdef CYGPKG_NET_TFTPD_CLIENT_BIG_PACKET
+ free(data);
+#endif
+
+ return result;
+}
+
//
// Read a file from a host into a local buffer. Returns the
// number of bytes actually read, or (-1) if an error occurs.
//
// Depreciated. Use tftp_client_get instead.
int
-tftp_get(char *filename,
- struct sockaddr_in *server,
+tftp_get(const char * const filename,
+ const struct sockaddr_in * const server,
char *buf,
int len,
- int mode,
- int *err)
+ const int mode,
+ int * const err)
{
char server_name[20];
char *ret;
int port;
ret = inet_ntop(AF_INET, (void *)&server->sin_addr,
- server_name, sizeof(server_name));
+ server_name, sizeof(server_name));
if (NULL == ret) {
*err = TFTP_NETERR;
return -1;
// Send data to a file on a server via TFTP.
//
int
-tftp_put(char *filename,
- struct sockaddr_in *server,
- char *buf,
+tftp_put(const char * const filename,
+ const struct sockaddr_in * const server,
+ const char *buf,
int len,
- int mode,
- int *err)
+ const int mode,
+ int * const err)
{
char server_name[20];
char *ret;
int port;
ret = inet_ntop(AF_INET, (void *)&server->sin_addr,
- server_name, sizeof(server_name));
+ server_name, sizeof(server_name));
if (NULL == ret) {
*err = TFTP_NETERR;
return -1;
// On error, *err will hold the reason.
// This version uses the server name. This can be a name for DNS lookup
// or a dotty or colony number format for IPv4 or IPv6.
-int tftp_client_put(char *filename,
- char *server,
- int port,
- char *buf,
- int len,
- int mode,
- int *err) {
+int tftp_client_put(const char * const filename,
+ const char * const server,
+ const int port,
+ const char *buf,
+ int len,
+ const int mode,
+ int * const err) {
int result = 0;
int s = -1, actual_len, data_len;
struct sockaddr local_addr, from_addr;
char data[SEGSIZE+sizeof(struct tftphdr)];
struct tftphdr *hdr = (struct tftphdr *)data;
- char *cp, *fp, *sfp;
+ const char *fp, *sfp;
+ char *cp;
struct timeval timeout;
unsigned short last_good_block = 0;
fd_set fds;
addrinfo = res;
while (addrinfo) {
s = socket(addrinfo->ai_family, addrinfo->ai_socktype,
- addrinfo->ai_protocol);
+ addrinfo->ai_protocol);
if (s >= 0) {
- memcpy(&local_addr,addrinfo->ai_addr,addrinfo->ai_addrlen);
- switch(addrinfo->ai_addr->sa_family) {
- case AF_INET: {
- struct sockaddr_in * saddr =
- (struct sockaddr_in *) addrinfo->ai_addr;
- struct sockaddr_in * laddr =
- (struct sockaddr_in *) &local_addr;
- if (port) {
- saddr->sin_port = htons(port);
- }
- laddr->sin_port = htons(put_port++);
- laddr->sin_addr.s_addr = INADDR_ANY;
- break;
- }
+ memcpy(&local_addr,addrinfo->ai_addr,addrinfo->ai_addrlen);
+ switch(addrinfo->ai_addr->sa_family) {
+ case AF_INET: {
+ struct sockaddr_in * saddr =
+ (struct sockaddr_in *) addrinfo->ai_addr;
+ struct sockaddr_in * laddr =
+ (struct sockaddr_in *) &local_addr;
+ if (port) {
+ saddr->sin_port = htons(port);
+ }
+ laddr->sin_port = htons(put_port++);
+ laddr->sin_addr.s_addr = INADDR_ANY;
+ break;
+ }
#ifdef CYGPKG_NET_INET6
- case AF_INET6: {
- struct sockaddr_in6 * saddr =
- (struct sockaddr_in6 *) addrinfo->ai_addr;
- struct sockaddr_in6 * laddr =
- (struct sockaddr_in6 *) &local_addr;
- if (port) {
- saddr->sin6_port = htons(port);
- }
- laddr->sin6_port = htons(put_port++);
- laddr->sin6_addr = in6addr_any;
- break;
- }
+ case AF_INET6: {
+ struct sockaddr_in6 * saddr =
+ (struct sockaddr_in6 *) addrinfo->ai_addr;
+ struct sockaddr_in6 * laddr =
+ (struct sockaddr_in6 *) &local_addr;
+ if (port) {
+ saddr->sin6_port = htons(port);
+ }
+ laddr->sin6_port = htons(put_port++);
+ laddr->sin6_addr = in6addr_any;
+ break;
+ }
#endif
- default:
- *err = TFTP_NETERR;
- goto out;
- }
- if (bind(s,
- (struct sockaddr *)&local_addr,
- addrinfo->ai_addrlen) < 0) {
- // Problem setting up my end
- *err = TFTP_NETERR;
- goto out;
- }
+ default:
+ *err = TFTP_NETERR;
+ goto out;
+ }
+ if (bind(s,
+ (struct sockaddr *)&local_addr,
+ addrinfo->ai_addrlen) < 0) {
+ // Problem setting up my end
+ *err = TFTP_NETERR;
+ goto out;
+ }
- while (1) {
- // Create initial request
- hdr->th_opcode = htons(WRQ); // Create/write file
- cp = (char *)&hdr->th_stuff;
- fp = filename;
- while (*fp) *cp++ = *fp++;
- *cp++ = '\0';
- if (mode == TFTP_NETASCII) {
+ while (1) {
+ // Create initial request
+ hdr->th_opcode = htons(WRQ); // Create/write file
+ cp = (char *)&hdr->th_stuff;
+ fp = filename;
+ while (*fp) *cp++ = *fp++;
+ *cp++ = '\0';
+ if (mode == TFTP_NETASCII) {
fp = "NETASCII";
- } else if (mode == TFTP_OCTET) {
+ } else if (mode == TFTP_OCTET) {
fp = "OCTET";
- } else {
+ } else {
*err = TFTP_INVALID;
- goto out;
- }
- while (*fp) *cp++ = *fp++;
- *cp++ = '\0';
- // Send request
- if (sendto(s, data, (int)(cp-data), 0,
- addrinfo->ai_addr,
- addrinfo->ai_addrlen) < 0) {
+ goto out;
+ }
+ while (*fp) *cp++ = *fp++;
+ *cp++ = '\0';
+ // Send request
+ if (sendto(s, data, (int)(cp-data), 0,
+ addrinfo->ai_addr,
+ addrinfo->ai_addrlen) < 0) {
// Problem sending request
*err = TFTP_NETERR;
- goto nextaddr;
- }
- // Wait for ACK
- timeout.tv_sec = TFTP_TIMEOUT_PERIOD;
- timeout.tv_usec = 0;
- FD_ZERO(&fds);
- FD_SET(s, &fds);
- if (select(s+1, &fds, 0, 0, &timeout) <= 0) {
+ goto nextaddr;
+ }
+ // Wait for ACK
+ timeout.tv_sec = TFTP_TIMEOUT_PERIOD;
+ timeout.tv_usec = 0;
+ FD_ZERO(&fds);
+ FD_SET(s, &fds);
+ if (select(s+1, &fds, 0, 0, &timeout) <= 0) {
if (++total_timeouts > TFTP_RETRIES_MAX) {
- // Timeout - no ACK received
- *err = TFTP_TIMEOUT;
- goto nextaddr;
+ // Timeout - no ACK received
+ *err = TFTP_TIMEOUT;
+ goto nextaddr;
}
- } else {
+ } else {
recv_len = sizeof(data);
from_len = sizeof(from_addr);
if ((data_len = recvfrom(s, &data, recv_len, 0,
&from_addr, &from_len)) < 0) {
- // What happened?
- *err = TFTP_NETERR;
- goto out;
+ // What happened?
+ *err = TFTP_NETERR;
+ goto out;
}
if (ntohs(hdr->th_opcode) == ACK) {
- // Write request accepted - start sending data
- break;
+ // Write request accepted - start sending data
+ break;
} else
- if (ntohs(hdr->th_opcode) == ERROR) {
+ if (ntohs(hdr->th_opcode) == ERROR) {
*err = ntohs(hdr->th_code);
goto out;
- } else {
+ } else {
// What kind of packet is this?
- goto out;
- }
- }
- }
-
- // Send data
- sfp = buf;
- last_good_block = 1;
- while (result < len) {
- // Build packet of data to send
- data_len = min(SEGSIZE, len-result);
- hdr->th_opcode = htons(DATA);
- hdr->th_block = htons(last_good_block);
- cp = hdr->th_data;
- fp = sfp;
- actual_len = data_len + 4;
- // FIXME - what about "netascii" data?
- while (data_len-- > 0) *cp++ = *fp++;
- // Send data packet
- if (sendto(s, data, actual_len, 0,
- &from_addr, from_len) < 0) {
+ goto out;
+ }
+ }
+ }
+
+ // Send data
+ sfp = buf;
+ last_good_block = 1;
+ while (result < len) {
+ // Build packet of data to send
+ data_len = min(SEGSIZE, len-result);
+ hdr->th_opcode = htons(DATA);
+ hdr->th_block = htons(last_good_block);
+ cp = hdr->th_data;
+ fp = sfp;
+ actual_len = data_len + 4;
+ // FIXME - what about "netascii" data?
+ while (data_len-- > 0) *cp++ = *fp++;
+ // Send data packet
+ if (sendto(s, data, actual_len, 0,
+ &from_addr, from_len) < 0) {
// Problem sending request
*err = TFTP_NETERR;
- goto out;
- }
- // Wait for ACK
- timeout.tv_sec = TFTP_TIMEOUT_PERIOD;
- timeout.tv_usec = 0;
- FD_ZERO(&fds);
- FD_SET(s, &fds);
- if (select(s+1, &fds, 0, 0, &timeout) <= 0) {
+ goto out;
+ }
+ // Wait for ACK
+ timeout.tv_sec = TFTP_TIMEOUT_PERIOD;
+ timeout.tv_usec = 0;
+ FD_ZERO(&fds);
+ FD_SET(s, &fds);
+ if (select(s+1, &fds, 0, 0, &timeout) <= 0) {
if (++total_timeouts > TFTP_TIMEOUT_MAX) {
- // Timeout - no data received
- *err = TFTP_TIMEOUT;
- goto out;
+ // Timeout - no data received
+ *err = TFTP_TIMEOUT;
+ goto out;
}
- } else {
+ } else {
recv_len = sizeof(data);
from_len = sizeof(from_addr);
if ((data_len = recvfrom(s, &data, recv_len, 0,
&from_addr, &from_len)) < 0) {
- // What happened?
- *err = TFTP_NETERR;
- goto out;
+ // What happened?
+ *err = TFTP_NETERR;
+ goto out;
}
if (ntohs(hdr->th_opcode) == ACK) {
- if (ntohs(hdr->th_block) == last_good_block) {
- // Advance pointers, etc
- sfp = fp;
- result += (actual_len - 4);
- last_good_block++;
- } else {
- diag_printf("Send block #%d, got ACK for #%d\n",
- last_good_block, ntohs(hdr->th_block));
- }
+ if (ntohs(hdr->th_block) == last_good_block) {
+ // Advance pointers, etc
+ sfp = fp;
+ result += (actual_len - 4);
+ last_good_block++;
+ } else {
+ diag_printf("Send block #%d, got ACK for #%d\n",
+ last_good_block, ntohs(hdr->th_block));
+ }
} else
- if (ntohs(hdr->th_opcode) == ERROR) {
+ if (ntohs(hdr->th_opcode) == ERROR) {
*err = ntohs(hdr->th_code);
goto out;
- } else {
+ } else {
// What kind of packet is this?
*err = TFTP_PROTOCOL;
- goto out;
- }
- }
- }
- close (s);
- return result;
+ goto out;
+ }
+ }
+ }
+ close (s);
+ return result;
}
// If we got here, it means there was a problem connecting to the
// server. Try the next address returned by getaddrinfo
nextaddr:
if (-1 != s) {
- close(s);
+ close(s);
}
addrinfo=addrinfo->ai_next;
}
cyg_tick_count_t *tp;
long *dp;
struct sockaddr_in from;
- int i, len, fromlen;
+ int i, len;
+ socklen_t fromlen;
ok_recv = 0;
bogus_recv = 0;
{
unsigned char pkt[MAX_PACKET];
struct sockaddr_in from;
- int len, fromlen;
+ int len;
+ socklen_t fromlen;
diag_printf("PING listener...\n" );
for (;;) {
static void
ftp_test(struct bootp *bp)
{
- int s, len, slen;
+ int s, slen;
+ socklen_t len;
struct sockaddr_in host, local;
struct servent *sent;
char buf[256];
if (getnameinfo (&client_addr, client_len,
host_addr_buf, sizeof(host_addr_buf),
host_port_buf, sizeof(host_port_buf),
- NI_NUMERIC) == EAI_NONE) {
+ NI_NUMERICHOST) == EAI_NONE) {
diag_printf("connection from %s(%s)\n", host_addr_buf, host_port_buf);
diag_sprintf(buf, "Hello %s(%s)\n", host_addr_buf, host_port_buf);
} else {
for (i = 0; i < 32; i++) {
m[i] = m_get(M_DONTWAIT, MT_DATA);
- diag_printf("allocate mbuf = %x\n", m[i]);
+ diag_printf("allocate mbuf = 0x%p\n", m[i]);
}
cyg_test_exit();
}
#ifdef __ECOS
-#ifndef CYGPKG_SNMPLIB
+# ifdef CYGPKG_POSIX
+# #include <pkgconf/posix.h>
+# endif
+# ifndef CYGPKG_POSIX_TIMERS
int
gettimeofday(struct timeval *tv, struct timezone *tz)
{
tv->tv_sec = cur_time / 100;
tv->tv_usec = (cur_time % 100) * 10000;
}
-#else
-int
-gettimeofday(struct timeval *tv, struct timezone *tz);
-#endif
+# endif
#endif
+
void
show_results(const char *msg, struct timeval *start,
struct timeval *end, int nbufs, int buflen,
#include <netinet/in.h>
#include <netinet/ip.h>
#include <netinet/ip_icmp.h>
+#include <string.h>
#include <netdb.h>
#ifndef EAI_NONE
#define test_printf diag_printf
typedef cyg_addrword_t test_param_t;
#else
+#include <stdio.h>
#define test_printf printf
typedef void *test_param_t;
#endif
extern void
cyg_test_exit(void);
#else
+#include <stdlib.h>
void
cyg_test_exit(void)
{
}
#ifdef __ECOS
-#ifndef CYGPKG_SNMPLIB
+# ifdef CYGPKG_POSIX
+# #include <pkgconf/posix.h>
+# endif
+# ifndef CYGPKG_POSIX_TIMERS
int
gettimeofday(struct timeval *tv, struct timezone *tz)
{
tv->tv_sec = cur_time / 100;
tv->tv_usec = (cur_time % 100) * 10000;
}
-#else
-int
-gettimeofday(struct timeval *tv, struct timezone *tz);
-#endif
+# endif
#endif
+
void
show_results(const char *msg, struct timeval *start,
struct timeval *end, int nbufs, int buflen,
static void
do_tcp_test(int s1, struct nc_request *req, struct sockaddr_in *master)
{
- int i, s, len, td_len, seq, seq_errors, lost, test_chan, res;
+ int i, s, td_len, seq, seq_errors, lost, test_chan, res;
+ socklen_t len;
struct sockaddr_in test_chan_slave, test_chan_master;
struct nc_test_results results;
struct nc_test_data *tdp;
static void
nc_slave(test_param_t param)
{
- int s, masterlen;
+ int s;
+ socklen_t masterlen;
struct sockaddr_in my_addr, master;
struct nc_request req;
struct nc_reply reply;
load_idle = idle_thread_count;
start_load(0); // Shut down background load
percent_load = 100 - ((load_idle * 100) / no_load_idle);
- diag_printf("High Load[%d] = %d => %d%%\n", load_thread_level,
+ diag_printf("High Load[%ld] = %d => %d%%\n", load_thread_level,
(int)idle_thread_count, percent_load);
if ( percent_load > desired_load )
break; // HIGH level is indeed higher
load_idle = idle_thread_count;
start_load(0); // Shut down background load
percent_load = 100 - ((load_idle * 100) / no_load_idle);
- diag_printf("Load[%d] = %d => %d%%\n", load_thread_level,
+ diag_printf("Load[%ld] = %d => %d%%\n", load_thread_level,
(int)idle_thread_count, percent_load);
if (((high-low) <= 1) || (abs(desired_load-percent_load) <= 2)) break;
if (percent_load < desired_load) {
load_idle = idle_thread_count;
start_load(0); // Shut down background load
percent_load = 100 - ((load_idle * 100) / no_load_idle);
- diag_printf("Final load[%d] = %d => %d%%\n", load_thread_level,
+ diag_printf("Final load[%ld] = %d => %d%%\n", load_thread_level,
(int)idle_thread_count, percent_load);
// no_load_idle_count_1_second = no_load_idle;
}
cyg_tick_count_t *tp;
long *dp;
struct sockaddr_in from;
- int i, len, fromlen;
+ int i, len;
+ socklen_t fromlen;
ok_recv = 0;
bogus_recv = 0;
static void
server_test(struct bootp *bp)
{
- int s, client, client_len;
+ int s, client;
+ socklen_t client_len;
struct sockaddr_in client_addr, local;
char buf[256];
int one = 1;
getpeername(client, (struct sockaddr *)&client_addr, &client_len);
diag_printf("connection from %s:%d\n", inet_ntoa(client_addr.sin_addr), ntohs(client_addr.sin_port));
-#ifdef CYGPKG_LIBC_STDIO
- sprintf(buf, "Hello %s:%d\n", inet_ntoa(client_addr.sin_addr), ntohs(client_addr.sin_port));
-#else
- strcpy(buf, "Hello ");
- strcat(buf, inet_ntoa(client_addr.sin_addr));
- strcat(buf,":");
- strcat(buf, atoi(ntohs(client_addr.sin_port)));
- strcat(buf,"\n");
-#endif
+ diag_sprintf(buf, "Hello %s:%d\n", inet_ntoa(client_addr.sin_addr), ntohs(client_addr.sin_port));
write(client, buf, strlen(buf));
tv.tv_sec = 5;
load_idle = idle_thread_count;
start_load(0); // Shut down background load
percent_load = 100 - ((load_idle * 100) / no_load_idle);
- diag_printf("High Load[%d] = %d => %d%%\n", load_thread_level,
+ diag_printf("High Load[%ld] = %d => %d%%\n", load_thread_level,
(int)idle_thread_count, percent_load);
if ( percent_load > desired_load )
break; // HIGH level is indeed higher
load_idle = idle_thread_count;
start_load(0); // Shut down background load
percent_load = 100 - ((load_idle * 100) / no_load_idle);
- diag_printf("Load[%d] = %d => %d%%\n", load_thread_level,
+ diag_printf("Load[%ld] = %d => %d%%\n", load_thread_level,
(int)idle_thread_count, percent_load);
if (((high-low) <= 1) || (abs(desired_load-percent_load) <= 2)) break;
if (percent_load < desired_load) {
load_idle = idle_thread_count;
start_load(0); // Shut down background load
percent_load = 100 - ((load_idle * 100) / no_load_idle);
- diag_printf("Final load[%d] = %d => %d%%\n", load_thread_level,
+ diag_printf("Final load[%ld] = %d => %d%%\n", load_thread_level,
(int)idle_thread_count, percent_load);
no_load_idle_count_1_second = no_load_idle;
}
struct sockaddr_in e_source_addr, e_sink_addr, local;
int one = 1;
fd_set in_fds;
- int i, num, len;
+ int i, num;
+ socklen_t len;
struct test_params params,nparams;
struct test_status status,nstatus;
params.bufsize = ntohl(nparams.bufsize);
params.load = ntohl(nparams.load);
- diag_printf("Using %d buffers of %d bytes each, %d%% background load\n",
+ diag_printf("Using %ld buffers of %ld bytes each, %ld%% background load\n",
params.nbufs, params.bufsize, params.load);
// Tell the sink what the parameters are
cyg_semaphore_wait(&idle_thread_sem); // Stop idle thread
start_load(0); // Shut down background load
i = 100 - ((idle_thread_count * 100) / no_load_idle_count_1_second );
- diag_printf("Final load[%d] = %d => %d%%\n", load_thread_level,
+ diag_printf("Final load[%ld] = %d => %d%%\n", load_thread_level,
(int)idle_thread_count, i);
//#ifdef CYGDBG_USE_ASSERTS
+2006-09-11 Daniel Néri <daniel.neri@sigicom.se>
+
+ * src/ftpclient.c (send_cmd): Use correct variable in error check.
+
2005-07-30 Andrew Lunn <andrew.lunn@ascom.ch>
* src/ftpclient.c (connect_to_server): Use socklen_t to avoid
int slen = strlen(msgbuf);
if ((len = write(s,msgbuf,slen)) != slen) {
- if (slen < 0) {
+ if (len < 0) {
ftp_printf(1,"write %s\n",strerror(errno));
return FTP_BAD;
} else {
#include "lkvm.h"
#include "getopt.h"
+#define FTP_SERV "192.168.1.125"
+#define FTP_USER "george"
+#define FTP_PASS "allen"
+
#define MAX_ARGV 32
#ifdef CYGHWR_NET_DRIVER_ETH0
do_load(boot_info);
- len = ftp_get("192.168.1.125", "gthomas", "Zorkle!!", "TEST.dat",
+ len = ftp_get(FTP_SERV, FTP_USER, FTP_PASS, "TEST.dat",
(char *)0x200000, 0x100000, ftpclient_printf);
diag_printf("res = %d\n", len);
if (len <= 0) exit(0);
- wlen = ftp_put("192.168.1.125", "gthomas", "Zorkle!!", "TEST2.dat",
+ wlen = ftp_put(FTP_SERV, FTP_USER, FTP_PASS, "TEST2.dat",
(char *)0x200000, len, ftpclient_printf);
diag_printf("res = %d\n", wlen);
err = deflateInit(&dp.stream, Z_DEFAULT_COMPRESSION);
diag_printf("err = %d\n", err);
- wlen = ftp_put_var("192.168.1.125", "gthomas", "Zorkle!!", "TEST3.dat.gz",
+ wlen = ftp_put_var(FTP_SERV, FTP_USER, FTP_PASS, "TEST3.dat.gz",
_ftp_write_gz, &dp, ftpclient_printf);
diag_printf("res = %d\n", wlen);
deflateEnd(&dp.stream);
+2006-07-28 Jochen Gerster <JochenGerster@gmx.de>
+
+ * src/monitor.c (cyg_monitor_network): Calling the network monitor
+ html handler can trigger an exception when the function
+ getifaddrs() fails because we are out of memory. Check the
+ return code and return failure if this happens.
+
2005-07-30 Andrew Lunn <andrew.lunn@ascom.ch>
* src/httpd.c (cyg_httpd_server): Use socklen_t to avoid compiler
{
struct ifaddrs *iflist, *ifp;
- getifaddrs(&iflist);
+ if(getifaddrs(&iflist)!=0)
+ return 0;
html_begin(client);
+2007-03-22 John Eigelaar <jeigelaar@mweb.co.za>
+
+ * include/lwip/netif.h, include/lwip/inet.h: Added externC macro
+ to public fucntions to make them C++ compliant.
+
+2006-05-09 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/ecos/init.c (arp_timer): Only compile this function when
+ Ethernet is supported.
+ * include/lwipopts.h: PAP_SUPPORT & CHAP_SUPPORT must be either 0
+ or 1 otherwise we get compiler errors.
+
+2006-03-26 Uwe Kindler <uwe_kindler@web.de>
+
+ * Updated the complete lwIP source to the latest lwIP
+ CVS version 1.1.1
+ * src/ecos/init.c Added call to netif_set_up(netif) in
+ function lwip_set_addr() - this is required since lwIP
+ version 1.0.0
+ * cdl/lwip_net.cdl Minor modifications for UDP configuration
+ options. Renamed CYGNUM_LWIP_TCPIP_THREAD_PRIORITY to
+ CYGNUM_LWIP_NETWORK_THREAD_PRIORITY and moved option outside
+ CYGPKG_LWIP_TCPIP component because the network thread needs to
+ run in all configurations.
+ * tests/nc_slave.c
+ * tests/tcpecho.c
+ * tests/udpecho.c
+ * tests/sockets.c
+ * tests/httpd.c Added eCos test infrastructure to tests and
+ made tests applicable depending on lwip configuration.
+
+2006-03-15 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * tests/nc_test_slave.c (nc_slave): Fix some of the compiler
+ warnings.
+
+2006-03-13 Uwe Kindler <uwe_kindler@web.de>
+
+ * cdl/lwip_net.cdl Changed default value of
+ CYGNUM_LWIP_MEMP_NUM_SYS_TIMEOUT (required for DHCP).
+ Replaced CYGPKG_LWIP_DHCP_OPTIONS with CYGPKG_LWIP_DHCP
+ and add CYGOPT_LWIP_DHCP_MANAGEMENT for automatic DHCP
+ management.
+ * include/lwip/ip_addr.h Add macro ip_addr_netcmp()
+ (copied from lwIP CVS).
+ * include/netif/etharp.h Updated file to version of
+ lwIP CVS.
+ * src/ecos/init.c Add include <pkgconf/net_lwip.h>
+ Add lwip_dhcp_fine_tmr() and lwip_dhcp_coarse_tmr()
+ for DHCP processing.
+ Change tcpip_init_done() to start DHCP timers and
+ ARP timer.
+ Changed lwip_set_addr() to properly setup IP adress
+ if DHCP is used.
+ Added lwip_dhcp_init() for start of DHCP client.
+ Removed start of ARP timer from ecosclue_init().
+ * src/netif/etharp.c Updated file to version of
+ lwIP CVS.
+
+2006-03-02 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * cdl/lwip_net.cdl: Add the interfaces CYGPKG_NET_STACK,
+ CYGPKG_NET_STACK_INET and CYGPKG_NET_STACK_INET6 and say that we
+ implement a network stack and an IPv4 stack. Without these interfaces
+ some of the Ethernet device drivers won't be compiled.
+
+2006-02-24 Uwe Kindler <uwe_kindler@web.de>
+
+ * cdl/lwip_net.cdl: Changed names of configuration options
+ according to eCos configuration option naming convention in
+ component writers guide.
+ * include/lwipopts.h: Changed mapping of eCos configuration
+ parameters to lwip configuration parameters. The mapping
+ was wrong because it expected a disabled eCos configuration
+ option is defined as 0 but a disabled eCos configuration option
+ is not defined.
+ * include/lwip/api.h Enumeration values of netconn_type are
+ defined conditional now to avoid compiler warnings if these
+ values are not evaluated in a switch statement.
+ * src/api/api_lib.c Compilation of code in several switch
+ statements is now conditional depending on configured
+ functionality.
+ * src/api/sockets.c Compilation of some code is now conditional
+ depending on configured functionality.
+ * src/ecos/init.c Changed initialisation values to match the
+ new configuration option names.
+
+2005-10-07 Uwe Kindler <uwe_kindler@web.de>
+
+ * src/core/tcp_in.c: pbuf_free() assert triggered by
+ NULLified inseg.p
+ * include/lwip/tcp.h Do no longer try to free pbuf
+ when TCP_EVENT_RECV() is called without a callback
+ handler, and without packet.
+ * tests/nc_test_slave.c Fixed test_printf and diag_printf
+ format strings that caused errors or warnings.
+ * tests/nc_test_slave.c Included <lwip/inet.h> - required
+ for compilation
+ * src/ecos/init.c Added structs ip_addr ipaddr, netmask and gw
+ in lwip_init() if loop interface is used
+
2004-05-05 Jani Monoses <jani@iv.ro>
* src/netif/ppp/ppp.c: Decrease sleep period in main thread
description "Lightweight TCP/IP stack"
requires {(CYGPKG_LWIP_ETH == 1) || (CYGPKG_LWIP_SLIP == 1) || (CYGPKG_LWIP_PPP == 1)}
+ cdl_interface CYGPKG_NET_STACK {
+ display "Suitable network stack implementation"
+ description "
+ Normally the interface if declared in the net common
+ package. However LWIP does not use that package
+ so we declare this interface here. Some of the device
+ drivers use it to decide if they should be build."
+ }
+ cdl_interface CYGPKG_NET_STACK_INET {
+ display "Network stack support for IPv4"
+ }
+
+ cdl_interface CYGPKG_NET_STACK_INET6 {
+ display "Network stack support for IPv6"
+ }
+
+ implements CYGPKG_NET_STACK
+ implements CYGPKG_NET_STACK_INET
+
compile core/mem.c \
core/memp.c \
core/netif.c \
ecos/init.c
- cdl_component CYGPKG_LWIP_STATS {
- display "Turn ON/OFF statistics"
+ cdl_option CYGDBG_LWIP_STATS {
+ display "Maintain traffic statistics"
flavor bool
default_value 0
description "
Check this box to turn ON statistics options for lwIP."
}
- cdl_component CYGPKG_LWIP_DEBUG {
- display "Turn ON/OFF debug options"
+ cdl_component CYGDBG_LWIP_DEBUG {
+ display "Support printing debug information"
flavor bool
default_value 0
description "
Check this box to turn ON debug options for lwIP."
- cdl_option CYGPKG_LWIP_DEBUG_TCP {
+ cdl_option CYGDBG_LWIP_DEBUG_TCP {
display "Control TCP debug"
flavor bool
default_value 0
}
- cdl_component CYGPKG_LWIP_ASSERTS {
- display "Turn ON/OFF assertions"
+ cdl_option CYGDBG_LWIP_ASSERTS {
+ display "Enable assertions"
flavor bool
default_value 0
description "
description "
See suboptions to define gateway IP, local IP and netmask."
- cdl_option CYGPKG_LWIP_SERV_ADDR {
+ cdl_option CYGDAT_LWIP_SERV_ADDR {
display "Gateway IP"
flavor data
default_value {"192,168,1,1"}
Gateway's IP address."
}
- cdl_option CYGPKG_LWIP_MY_ADDR {
+
+ cdl_option CYGDAT_LWIP_MY_ADDR {
display "My IP"
flavor data
default_value {"192,168,1,222"}
The IP address for this device."
}
- cdl_option CYGPKG_LWIP_NETMASK {
+
+ cdl_option CYGDAT_LWIP_NETMASK {
display "Netmask"
flavor data
default_value {"255,255,255,0"}
no_define
description "
Tunables for various aspects of memory usage throughout the stack."
-
-
-
- cdl_option CYGPKG_LWIP_MEM_ALIGNMENT {
+
+ cdl_option CYGNUM_LWIP_MEM_ALIGNMENT {
display "Memory alignment"
flavor data
default_value 4
lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4,
2 byte alignment -> define MEM_ALIGNMENT to 2."
}
- cdl_option CYGPKG_LWIP_MEM_SIZE {
+ cdl_option CYGNUM_LWIP_MEM_SIZE {
display "Memory size"
flavor data
default_value 4000
description "
MEM_SIZE: the size of the heap memory. If the application will send
- a lot of data that needs to be copied, this should be set high."
-
+ a lot of data that needs to be copied, this should be set high."
}
- cdl_option CYGPKG_LWIP_MEMP_NUM_PBUF {
+
+ cdl_option CYGNUM_LWIP_MEMP_NUM_PBUF {
display "Number of memp struct pbufs"
flavor data
default_value 8
should be set high."
}
- cdl_option CYGPKG_LWIP_MEMP_NUM_UDP_PCB {
+ cdl_option CYGNUM_LWIP_MEMP_NUM_UDP_PCB {
display "Simultaneous UDP control blocks "
flavor data
default_value 4
per active UDP 'connection'."
}
- cdl_option CYGPKG_LWIP_MEMP_NUM_TCP_PCB {
+ cdl_option CYGNUM_LWIP_MEMP_NUM_TCP_PCB {
display "Simultaneous active TCP connections "
flavor data
default_value 5
connections."
}
- cdl_option CYGPKG_LWIP_MEMP_NUM_TCP_PCB_LISTEN {
+ cdl_option CYGNUM_LWIP_MEMP_NUM_TCP_PCB_LISTEN {
display "Listening TCP connections"
flavor data
default_value 8
connections."
}
- cdl_option CYGPKG_LWIP_MEMP_NUM_TCP_SEG {
+ cdl_option CYGNUM_LWIP_MEMP_NUM_TCP_SEG {
display "Simultaneous TCP segments queued"
flavor data
default_value 8
segments."
}
- cdl_option CYGPKG_LWIP_MEMP_NUM_SYS_TIMEOUT {
+ cdl_option CYGNUM_LWIP_MEMP_NUM_SYS_TIMEOUT {
display "Simultaneous active timeouts"
flavor data
- default_value 3
+ default_value CYGPKG_LWIP_DHCP ? 6 : 4
description "
MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
timeouts."
}
- cdl_component CYGPKG_LWIP_CYGPKG_LWIP_MEM_SEQ_API {
+ cdl_component CYGPKG_LWIP_MEM_SEQ_API {
display "Sequential API settings"
flavor none
no_define
description "
The following four are used only with the sequential API and can be
- set to 0 if the application only will use the raw API."
+ set to 0 if the application only will use the raw API."
- cdl_option CYGPKG_LWIP_MEMP_NUM_NETBUF {
+ cdl_option CYGNUM_LWIP_MEMP_NUM_NETBUF {
display "Struct netbufs"
flavor data
default_value 2
MEMP_NUM_NETBUF: the number of struct netbufs."
}
- cdl_option CYGPKG_LWIP_MEMP_NUM_NETCONN {
+ cdl_option CYGNUM_LWIP_MEMP_NUM_NETCONN {
display "Struct netconns"
flavor data
default_value 4
MEMP_NUM_NETCONN: the number of struct netconns."
}
- cdl_option CYGPKG_LWIP_MEMP_NUM_APIMSG {
+ cdl_option CYGNUM_LWIP_MEMP_NUM_APIMSG {
display "Struct api_msgs"
flavor data
default_value 8
programs."
}
- cdl_option CYGPKG_LWIP_MEMP_NUM_TCPIP_MSG {
+ cdl_option CYGNUM_LWIP_MEMP_NUM_TCPIP_MSG {
display "Struct tcpip_msgs"
flavor data
default_value 8
Packet buffer related tunings."
- cdl_option CYGPKG_LWIP_PBUF_POOL_SIZE {
+ cdl_option CYGNUM_LWIP_PBUF_POOL_SIZE {
display "PBUF pool size"
flavor data
default_value 60
}
- cdl_option CYGPKG_LWIP_PBUF_POOL_BUFSIZE {
+ cdl_option CYGNUM_LWIP_PBUF_POOL_BUFSIZE {
display "PBUF buffer size"
flavor data
default_value 1024
description "
PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool."
-
- }
- cdl_option CYGPKG_LWIP_PBUF_LINK_HLEN {
+ }
+
+ cdl_option CYGNUM_LWIP_PBUF_LINK_HLEN {
display "Allocation for a link level header"
flavor data
calculated {CYGPKG_LWIP_SLIP || CYGPKG_LWIP_PPP ? 0 : 16}
}
}
- cdl_component CYGPKG_LWIP_TCP_OPTIONS {
- display "TCP"
- flavor none
- no_define
+ cdl_component CYGPKG_LWIP_TCP {
+ display "TCP"
+ flavor bool
+ default_value 1
description "
- Tune the TCP protocol details"
-
- cdl_option CYGPKG_LWIP_TCP {
- display "Activate TCP"
- flavor bool
- default_value 1
- description ""
-
- }
+ Support TCP protocol."
- cdl_option CYGPKG_LWIP_TCPIP_THREAD_PRIORITY {
- display "tcpip thread priority"
- flavor data
- default_value 7
- description "Pririty of the lwIP network thread.This thread handles all API messages and
- network packets."
- }
-
- cdl_option CYGPKG_LWIP_TCP_TTL {
+ cdl_option CYGNUM_LWIP_TCP_TTL {
display "Time To Live"
flavor data
default_value 255
description ""
}
- cdl_option CYGPKG_LWIP_TCP_QUEUE_OOSEQ {
+ cdl_option CYGIMP_LWIP_TCP_QUEUE_OOSEQ {
display "Queue segments"
flavor bool
default_value 1
description "
Controls if TCP should queue segments that arrive out of
- order. Define to 0 if your device is low on memory."
+ order. Disable this option if your device is low on memory."
}
- cdl_option CYGPKG_LWIP_TCP_MSS {
+ cdl_option CYGNUM_LWIP_TCP_MSS {
display "Maximum segment size"
flavor data
default_value 2048
description "
TCP Maximum segment size."
- }
- cdl_option CYGPKG_LWIP_TCP_SND_BUF {
+ }
+
+ cdl_option CYGNUM_LWIP_TCP_SND_BUF {
display "Sender buffer space"
flavor data
default_value 2048
TCP sender buffer space (bytes)."
}
- cdl_option CYGPKG_LWIP_TCP_SND_QUEUELEN {
+ cdl_option CYGNUM_LWIP_TCP_SND_QUEUELEN {
display "Sender pbufs"
flavor data
- calculated "4 * CYGPKG_LWIP_TCP_SND_BUF/CYGPKG_LWIP_TCP_MSS"
+ calculated CYGPKG_LWIP_TCP ? "4 * CYGNUM_LWIP_TCP_SND_BUF/CYGNUM_LWIP_TCP_MSS" : 0
description "
TCP sender buffer space (pbufs). This must be at least = 2 *
TCP_SND_BUF/TCP_MSS for things to work."
}
- cdl_option CYGPKG_LWIP_TCP_WND {
+ cdl_option CYGNUM_LWIP_TCP_WND {
display "Receive window"
flavor data
default_value 4096
TCP receive window."
}
- cdl_option CYGPKG_LWIP_TCP_MAXRTX {
+ cdl_option CYGNUM_LWIP_TCP_MAXRTX {
display "Segment retransmissions"
flavor data
default_value 12
Maximum number of retransmissions of data segments."
}
- cdl_option CYGPKG_LWIP_TCP_SYNMAXRTX {
+ cdl_option CYGNUM_LWIP_TCP_SYNMAXRTX {
display "Syn retransmissions"
flavor data
default_value 4
flavor none
no_define
- cdl_option CYGPKG_LWIP_ARP_TABLE_SIZE {
+ cdl_option CYGNUM_LWIP_ARP_TABLE_SIZE {
display "ARP table size"
flavor data
default_value 10
flavor none
no_define
- cdl_option CYGPKG_LWIP_IP_FORWARD {
- display "IP forwarding"
+ cdl_option CYGFUN_LWIP_IP_FORWARD {
+ display "Support IP forwarding"
flavor bool
default_value 1
description "
- Define IP_FORWARD to 1 if you wish to have the ability to forward
+ Enable this option if you wish to have the ability to forward
IP packets across network interfaces. If you are going to run lwIP
- on a device with only one network interface, define this to 0."
+ on a device with only one network interface, disable this option."
}
- cdl_option CYGPKG_LWIP_IP_OPTIONS {
+ cdl_option CYGFUN_LWIP_IP_OPTIONS {
display "Allow IP options"
flavor bool
default_value 1
description "
- If defined to 1, IP options are allowed (but not parsed). If
- defined to 0, all packets with IP options are dropped."
+ If enabled, IP options are allowed (but not parsed). If
+ disabled, all packets with IP options are dropped."
}
- cdl_option CYGPKG_LWIP_IP_FRAG {
+ cdl_option CYGFUN_LWIP_IP_FRAG {
display "Support IP fragmentation"
flavor bool
default_value 1
"
}
- cdl_option CYGPKG_LWIP_IP_REASS {
+ cdl_option CYGFUN_LWIP_IP_REASS {
display "Support IP reassembly"
flavor bool
default_value 1
flavor none
no_define
- cdl_option CYGPKG_LWIP_ICMP_TTL {
+ cdl_option CYGNUM_LWIP_ICMP_TTL {
display "ICMP Time To Live"
flavor data
default_value 255
}
}
- cdl_component CYGPKG_LWIP_DHCP_OPTIONS {
- display "DHCP"
- flavor none
- no_define
-
-
- cdl_option CYGPKG_LWIP_DHCP {
- display "Activate DHCP"
- flavor bool
- default_value 0
- description "
- Define LWIP_DHCP to 1 if you want DHCP configuration of
- interfaces."
- compile core/dhcp.c
- }
-
-
- cdl_option CYGPKG_LWIP_DHCP_DOES_ARP_CHECK {
+ cdl_component CYGPKG_LWIP_DHCP {
+ display "DHCP"
+ flavor bool
+ requires CYGPKG_LWIP_UDP
+ default_value 0
+ requires { CYGNUM_LWIP_MEMP_NUM_SYS_TIMEOUT >= 6 }
+ description "
+ Provide DHCP support for initializing the IP address of network interfaces."
+ compile core/dhcp.c
+
+ cdl_option CYGOPT_LWIP_DHCP_MANAGEMENT {
+ display "DHCP management"
+ flavor bool
+ default_value 1
+ description "
+ If enabled then the lwIP stack automatically calls dhcp_start(),
+ dhcp_fine_tmr() and dhcp_coarse_tmr(). The DHCP stuff is handled
+ in the TCP/IP thread. If this causes trouble on high traffic loads
+ or if the application need to be aware of the DHCP state then it
+ is better to disable this option. In this case managing the DHCP
+ state in an application aware thread is recommended."
+ }
+
+ cdl_option CYGOPT_LWIP_DHCP_DOES_ARP_CHECK {
display "Check offered address"
flavor bool
- default_value 0
+ default_value 1
description "
- 1 if you want to do an ARP check on the offered address
+ Enable this option if you want to do an ARP check on the offered address
(recommended)."
}
}
- cdl_component CYGPKG_LWIP_LOOPIF {
+ cdl_component CYGFUN_LWIP_LOOPIF {
display "Support loop interface (127.0.0.1)"
flavor bool
default_value 1
description "Ethernet support"
compile netif/etharp.c
- cdl_option CYGPKG_LWIP_ETH_THREAD_PRIORITY {
+ cdl_option CYGNUM_LWIP_ETH_THREAD_PRIORITY {
display "ethernet input thread priority"
flavor data
default_value 6
}
}
+
+ cdl_option CYGNUM_LWIP_NETWORK_THREAD_PRIORITY {
+ display "Network thread priority"
+ flavor data
+ default_value 7
+ description "Priority of the lwIP network thread.This thread handles all API messages and
+ network packets."
+ }
cdl_component CYGPKG_LWIP_SLIP {
display "SLIP"
description "IP over Serial Line"
compile netif/slipif.c ecos/sio.c
- cdl_option CYGPKG_LWIP_SLIPIF_THREAD_PRIORITY {
+ cdl_option CYGNUM_LWIP_SLIPIF_THREAD_PRIORITY {
display "SLIP thread priority"
flavor data
default_value 8
description "Priority of the SLIP input thread"
}
- cdl_option CYGPKG_LWIP_SLIP_DEV {
+ cdl_option CYGDAT_LWIP_SLIP_DEV {
display "Serial device"
flavor data
default_value {"\"/dev/ser0\""}
description "
- Which serial port to use SLIP on."
+ Which serial port to use SLIP on."
}
}
ecos/sio.c
- cdl_option CYGPKG_LWIP_PPP_PAP_AUTH {
+ cdl_option CYGIMP_LWIP_PPP_PAP_AUTH {
display "Support PAP authentication"
flavor bool
default_value 1
compile netif/ppp/pap.c
}
- cdl_option CYGPKG_LWIP_PPP_CHAP_AUTH {
+ cdl_option CYGIMP_LWIP_PPP_CHAP_AUTH {
display "Support CHAP authentication"
flavor bool
default_value 1
compile netif/ppp/chap.c
}
- cdl_option CYGPKG_LWIP_PPP_DEV {
+ cdl_option CYGDAT_LWIP_PPP_DEV {
display "Serial device for PPP"
flavor data
default_value {"\"/dev/ser0\""}
Which serial port to use PPP on."
}
- cdl_option CYGPKG_LWIP_PPP_THREAD_PRIORITY {
+ cdl_option CYGNUM_LWIP_PPP_THREAD_PRIORITY {
display "PPP main thread priority"
flavor data
default_value 8
}
}
- cdl_component CYGPKG_LWIP_UDP_OPTIONS {
+ cdl_component CYGPKG_LWIP_UDP {
display "UDP"
- flavor none
- no_define
-
- cdl_option CYGPKG_LWIP_UDP {
- display "Activate UDP"
- flavor bool
- default_value 1
- description ""
- compile core/udp.c
- }
+ flavor bool
+ default_value 1
+ description "Support UDP protocol."
+ compile core/udp.c
- cdl_option CYGPKG_LWIP_UDP_TTL {
+ cdl_option CYGNUM_LWIP_UDP_TTL {
display "Time To Live"
flavor data
default_value 255
}
}
- cdl_option CYGPKG_LWIP_RAW {
+ cdl_option CYGFUN_LWIP_RAW {
display "Enable RAW socket support"
flavor bool
default_value 1
description ""
compile core/raw.c
}
+
+ cdl_option CYGFUN_LWIP_COMPAT_SOCKETS {
+ display "Provide compatible socket API"
+ flavor bool
+ default_value 1
+ description "
+ The lwIP socket API uses defines to map the lwip socket functions
+ (lwip_accept(), lwip_bind(), lwip_listen()...) to BSD like names
+ (accept(), bind(), listen()...). If this causes trouble or naming
+ conficts for your application, then disable this option"
+ }
cdl_component CYGPKG_LWIP_APP_MEM_OPTIONS {
display "Memory options for apps"
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
#ifndef __ARCH_CC_H__
#define __ARCH_CC_H__
typedef signed long s32_t;
typedef unsigned long mem_ptr_t;
+#define U16_F "u"
+#define S16_F "d"
+#define X16_F "x"
+#define U32_F "lu"
+#define S32_F "ld"
+#define X32_F "lx"
#define PACK_STRUCT_FIELD(x) x __attribute__((packed))
#define PACK_STRUCT_STRUCT __attribute__((packed))
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
#ifndef __PERF_H__
#define __PERF_H__
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+
#ifndef __SYS_ECOS_H__
#define __SYS_ECOS_H__
#define SYS_MBOX_NULL (sys_mbox_t)NULL
#define SYS_SEM_NULL (sys_sem_t)NULL
-typedef cyg_sem_t * sys_sem_t;
+typedef cyg_sem_t* sys_sem_t;
typedef cyg_handle_t sys_mbox_t;
-typedef cyg_thread * sys_thread_t;
+typedef cyg_handle_t sys_thread_t;
#endif /* __SYS_ECOS_H__ */
struct {
void *dataptr;
u16_t len;
- unsigned char copy;
+ u8_t copy;
} w;
sys_mbox_t mbox;
u16_t len;
/** print debug message only if debug message type is enabled...
* AND is of correct type AND is at least DBG_LEVEL
*/
-# define LWIP_DEBUGF(debug,x) do { if (((debug) & DBG_ON) && ((debug) & DBG_TYPES_ON) && (((debug) & DBG_MASK_LEVEL) >= DBG_MIN_LEVEL)) { LWIP_PLATFORM_DIAG(x); if ((debug) & DBG_HALT) while(1); } } while(0)
+# define LWIP_DEBUGF(debug,x) do { if (((debug) & DBG_ON) && ((debug) & DBG_TYPES_ON) && ((s16_t)((debug) & DBG_MASK_LEVEL) >= DBG_MIN_LEVEL)) { LWIP_PLATFORM_DIAG(x); if ((debug) & DBG_HALT) while(1); } } while(0)
# define LWIP_ERROR(x) do { LWIP_PLATFORM_DIAG(x); } while(0)
#else /* LWIP_DEBUG */
# define LWIP_DEBUGF(debug,x)
struct ip_addr offered_sn_mask;
struct ip_addr offered_gw_addr;
struct ip_addr offered_bc_addr;
+#define DHCP_MAX_DNS 2
+ u32_t dns_count; /* actual number of DNS servers obtained */
+ struct ip_addr offered_dns_addr[DHCP_MAX_DNS]; /* DNS server addresses */
+
u32_t offered_t0_lease; /* lease period (in seconds) */
u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */
u32_t offered_t2_rebind; /* recommended rebind time (usually 66% of lease period) */
PACK_STRUCT_FIELD(u8_t file[DHCP_FILE_LEN]);
PACK_STRUCT_FIELD(u32_t cookie);
#define DHCP_MIN_OPTIONS_LEN 68U
+/** make sure user does not configure this too small */
+#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN))
+# undef DHCP_OPTIONS_LEN
+#endif
/** allow this to be configured in lwipopts.h, but not too small */
-#if ((!defined(DHCP_OPTIONS_LEN)) || (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN))
+#if (!defined(DHCP_OPTIONS_LEN))
/** set this to be sufficient for your options in outgoing DHCP msgs */
# define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN
#endif
/** start DHCP configuration */
err_t dhcp_start(struct netif *netif);
+/** enforce early lease renewal (not needed normally)*/
+err_t dhcp_renew(struct netif *netif);
+/** release the DHCP lease, usually called before dhcp_stop()*/
+err_t dhcp_release(struct netif *netif);
/** stop DHCP configuration */
void dhcp_stop(struct netif *netif);
-/** enforce lease renewal */
-err_t dhcp_renew(struct netif *netif);
-/** inform server of our IP address */
+/** inform server of our manual IP address */
void dhcp_inform(struct netif *netif);
/** if enabled, check whether the offered IP address is not in use, using ARP */
/** BootP options */
#define DHCP_OPTION_PAD 0
#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */
-#define DHCP_OPTION_ROUTER 3
+#define DHCP_OPTION_ROUTER 3
+#define DHCP_OPTION_DNS_SERVER 6
#define DHCP_OPTION_HOSTNAME 12
#define DHCP_OPTION_IP_TTL 23
#define DHCP_OPTION_MTU 26
#include "lwip/ip_addr.h"
u16_t inet_chksum(void *dataptr, u16_t len);
+#if 0 /* optimized routine */
+u16_t inet_chksum4(u8_t *dataptr, u16_t len);
+#endif
u16_t inet_chksum_pbuf(struct pbuf *p);
u16_t inet_chksum_pseudo(struct pbuf *p,
struct ip_addr *src, struct ip_addr *dest,
u8_t proto, u16_t proto_len);
-u32_t inet_addr(const char *cp);
-int inet_aton(const char *cp, struct in_addr *addr);
-char *inet_ntoa(struct in_addr addr); /* returns ptr to static buffer; not reentrant! */
+externC u32_t inet_addr(const char *cp);
+externC s8_t inet_aton(const char *cp, struct in_addr *addr);
+externC char *inet_ntoa(struct in_addr addr); /* returns ptr to static buffer; not reentrant! */
#ifdef htons
#undef htons
#define htonl lwip_htonl
#define ntohl lwip_ntohl
#endif
-u16_t htons(u16_t x);
-u16_t ntohs(u16_t x);
-u32_t htonl(u32_t x);
-u32_t ntohl(u32_t x);
+externC u16_t htons(u16_t x);
+externC u16_t ntohs(u16_t x);
+externC u32_t htonl(u32_t x);
+externC u32_t ntohl(u32_t x);
#endif
#endif /* __LWIP_INET_H__ */
#include "lwip/err.h"
-struct netif;
void ip_init(void);
struct netif *ip_route(struct ip_addr *dest);
#define IPH_V(hdr) (ntohs((hdr)->_v_hl_tos) >> 12)
#define IPH_HL(hdr) ((ntohs((hdr)->_v_hl_tos) >> 8) & 0x0f)
-#define IPH_TOS(hdr) (htons((ntohs((hdr)->_v_hl_tos) & 0xff)))
+#define IPH_TOS(hdr) (ntohs((hdr)->_v_hl_tos) & 0xff)
#define IPH_LEN(hdr) ((hdr)->_len)
#define IPH_ID(hdr) ((hdr)->_id)
#define IPH_OFFSET(hdr) ((hdr)->_offset)
#define ip_addr_set(dest, src) (dest)->addr = \
((src) == NULL? 0:\
(src)->addr)
-#define ip_addr_maskcmp(addr1, addr2, mask) (((addr1)->addr & \
+/**
+ * Determine if two address are on the same network.
+ *
+ * @arg addr1 IP address 1
+ * @arg addr2 IP address 2
+ * @arg mask network identifier mask
+ * @return !0 if the network identifiers of both address match
+ */
+#define ip_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \
(mask)->addr) == \
((addr2)->addr & \
(mask)->addr))
#define ip_addr_ismulticast(addr1) (((addr1)->addr & ntohl(0xf0000000)) == ntohl(0xe0000000))
-#define ip_addr_debug_print(debug, ipaddr) LWIP_DEBUGF(debug, ("%u.%u.%u.%u", \
- ipaddr?(unsigned int)(ntohl((ipaddr)->addr) >> 24) & 0xff:0, \
- ipaddr?(unsigned int)(ntohl((ipaddr)->addr) >> 16) & 0xff:0, \
- ipaddr?(unsigned int)(ntohl((ipaddr)->addr) >> 8) & 0xff:0, \
- ipaddr?(unsigned int)ntohl((ipaddr)->addr) & 0xff:0U))
+#define ip_addr_debug_print(debug, ipaddr) LWIP_DEBUGF(debug, ("%"U16_F".%"U16_F".%"U16_F".%"U16_F, \
+ ipaddr?(u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff:0, \
+ ipaddr?(u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff:0, \
+ ipaddr?(u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff:0, \
+ ipaddr?(u16_t)ntohl((ipaddr)->addr) & 0xff:0U))
/* cast to unsigned int, as it is used as argument to printf functions
- * which expect integer arguments */
-#define ip4_addr1(ipaddr) ((unsigned int)(ntohl((ipaddr)->addr) >> 24) & 0xff)
-#define ip4_addr2(ipaddr) ((unsigned int)(ntohl((ipaddr)->addr) >> 16) & 0xff)
-#define ip4_addr3(ipaddr) ((unsigned int)(ntohl((ipaddr)->addr) >> 8) & 0xff)
-#define ip4_addr4(ipaddr) ((unsigned int)(ntohl((ipaddr)->addr)) & 0xff)
+ * which expect integer arguments. CSi: use cc.h formatters (conversion chars)! */
+#define ip4_addr1(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff)
+#define ip4_addr2(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff)
+#define ip4_addr3(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff)
+#define ip4_addr4(ipaddr) ((u16_t)(ntohl((ipaddr)->addr)) & 0xff)
#endif /* __LWIP_IP_ADDR_H__ */
#include "lwip/netif.h"
#include "lwip/ip_addr.h"
-struct pbuf * ip_reass(struct pbuf *);
-err_t ip_frag(struct pbuf *, struct netif *, struct ip_addr *);
+void ip_reass_tmr(void);
+struct pbuf * ip_reass(struct pbuf *p);
+err_t ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest);
#endif /* __LWIP_IP_FRAG_H__ */
/** whether the network interface is 'up'. this is
* a software flag used to control whether this network
- * interface is enabled and processes traffic */
+ * interface is enabled and processes traffic.
+ */
#define NETIF_FLAG_UP 0x1U
/** if set, the netif has broadcast capability */
#define NETIF_FLAG_BROADCAST 0x2U
/** if set, the interface is configured using DHCP */
#define NETIF_FLAG_DHCP 0x08U
/** if set, the interface has an active link
- * (set by the interface) */
+ * (set by the network interface driver) */
#define NETIF_FLAG_LINK_UP 0x10U
-/** generic data structure used for all lwIP network interfaces */
+/** Generic data structure used for all lwIP network interfaces.
+ * The following fields should be filled in by the initialization
+ * function for the device driver: hwaddr_len, hwaddr[], mtu, flags */
+
struct netif {
/** pointer to next in linked list */
struct netif *next;
- /** The following fields should be filled in by the
- initialization function for the device driver. */
-
+
/** IP address configuration in network byte order */
struct ip_addr ip_addr;
struct ip_addr netmask;
struct ip_addr gw;
/** This function is called by the network device driver
- to pass a packet up the TCP/IP stack. */
+ * to pass a packet up the TCP/IP stack. */
err_t (* input)(struct pbuf *p, struct netif *inp);
/** This function is called by the IP module when it wants
- to send a packet on the interface. This function typically
- first resolves the hardware address, then sends the packet. */
+ * to send a packet on the interface. This function typically
+ * first resolves the hardware address, then sends the packet. */
err_t (* output)(struct netif *netif, struct pbuf *p,
struct ip_addr *ipaddr);
/** This function is called by the ARP module when it wants
- to send a packet on the interface. This function outputs
- the pbuf as-is on the link medium. */
+ * to send a packet on the interface. This function outputs
+ * the pbuf as-is on the link medium. */
err_t (* linkoutput)(struct netif *netif, struct pbuf *p);
/** This field can be set by the device driver and could point
- to state information for the device. */
+ * to state information for the device. */
void *state;
#if LWIP_DHCP
/** the DHCP client state information for this netif */
struct dhcp *dhcp;
#endif
/** number of bytes used in hwaddr */
- unsigned char hwaddr_len;
+ u8_t hwaddr_len;
/** link level hardware address of this interface */
- unsigned char hwaddr[NETIF_MAX_HWADDR_LEN];
+ u8_t hwaddr[NETIF_MAX_HWADDR_LEN];
/** maximum transfer unit (in bytes) */
u16_t mtu;
+ /** flags (see NETIF_FLAG_ above) */
+ u8_t flags;
+ /** link type */
+ u8_t link_type;
/** descriptive abbreviation */
char name[2];
/** number of this interface */
u8_t num;
- /** NETIF_FLAG_* */
- u8_t flags;
};
/** The list of network interfaces. */
extern struct netif *netif_default;
/* netif_init() must be called first. */
-void netif_init(void);
+externC void netif_init(void);
-struct netif *netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
+externC struct netif *netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
struct ip_addr *gw,
void *state,
err_t (* init)(struct netif *netif),
err_t (* input)(struct pbuf *p, struct netif *netif));
-void
+externC void
netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask,
struct ip_addr *gw);
-void netif_remove(struct netif * netif);
+externC void netif_remove(struct netif * netif);
/* Returns a network interface given its name. The name is of the form
"et0", where the first two letters are the "name" field in the
netif structure, and the digit is in the num field in the same
structure. */
-struct netif *netif_find(char *name);
+externC struct netif *netif_find(char *name);
-void netif_set_default(struct netif *netif);
+externC void netif_set_default(struct netif *netif);
-void netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr);
-void netif_set_netmask(struct netif *netif, struct ip_addr *netmast);
-void netif_set_gw(struct netif *netif, struct ip_addr *gw);
+externC void netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr);
+externC void netif_set_netmask(struct netif *netif, struct ip_addr *netmast);
+externC void netif_set_gw(struct netif *netif, struct ip_addr *gw);
+externC void netif_set_up(struct netif *netif);
+externC void netif_set_down(struct netif *netif);
+externC u8_t netif_is_up(struct netif *netif);
#endif /* __LWIP_NETIF_H__ */
#endif
#ifndef MEMP_SANITY_CHECK
-#define MEMP_SANITY_CHECK 0
+#define MEMP_SANITY_CHECK 0
#endif
/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
#endif
/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
- link level header. */
+ link level header. Defaults to 14 for Ethernet. */
#ifndef PBUF_LINK_HLEN
-#define PBUF_LINK_HLEN 0
+#define PBUF_LINK_HLEN 14
#endif
/**
* If enabled, outgoing packets are queued during hardware address
- * resolution. The etharp.c implementation queues 1 packet only.
+ * resolution.
+ *
+ * This feature has not stabilized yet. Single-packet queueing is
+ * believed to be stable, multi-packet queueing is believed to
+ * clash with the TCP segment queueing.
+ *
+ * As multi-packet-queueing is currently disabled, enabling this
+ * _should_ work, but we need your testing feedback on lwip-users.
+ *
*/
#ifndef ARP_QUEUEING
#define ARP_QUEUEING 1
#endif
-/** If enabled, the first packet queued will not be overwritten by
- * later packets. If disabled, later packets overwrite early packets
- * in the queue. Default is disabled, which is recommended.
- */
-#ifndef ARP_QUEUE_FIRST
-#define ARP_QUEUE_FIRST 0
+
+/* This option is deprecated */
+#ifdef ETHARP_QUEUE_FIRST
+#error ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h.
#endif
/* This option is removed to comply with the ARP standard */
/* Support loop interface (127.0.0.1) */
#ifndef LWIP_HAVE_LOOPIF
-#define LWIP_HAVE_LOOPIF 1
+#define LWIP_HAVE_LOOPIF 0
#endif
#ifndef LWIP_EVENT_API
/* ---------- Socket Options ---------- */
/* Enable SO_REUSEADDR and SO_REUSEPORT options */
-#ifndef SO_REUSE
-# define SO_REUSE 1
+#define SO_REUSE 0
+#if SO_REUSE
+/* I removed the lot since this was an ugly hack. It broke the raw-API.
+ It also came with many ugly goto's, Christiaan Simons. */
+#error "SO_REUSE currently unavailable, this was a hack"
#endif
#endif
#ifndef LINK_STATS
-#define LINK_STATS 1
+#define LINK_STATS 1
#endif
#ifndef IP_STATS
-#define IP_STATS 1
+#define IP_STATS 1
#endif
#ifndef IPFRAG_STATS
-#define IPFRAG_STATS 1
+#define IPFRAG_STATS 1
#endif
#ifndef ICMP_STATS
-#define ICMP_STATS 1
+#define ICMP_STATS 1
#endif
#ifndef UDP_STATS
-#define UDP_STATS 1
+#define UDP_STATS 1
#endif
#ifndef TCP_STATS
-#define TCP_STATS 1
+#define TCP_STATS 1
#endif
#ifndef MEM_STATS
-#define MEM_STATS 1
+#define MEM_STATS 1
#endif
#ifndef MEMP_STATS
-#define MEMP_STATS 1
+#define MEMP_STATS 1
#endif
#ifndef PBUF_STATS
-#define PBUF_STATS 1
+#define PBUF_STATS 1
#endif
#ifndef SYS_STATS
-#define SYS_STATS 1
+#define SYS_STATS 1
#endif
#ifndef RAW_STATS
-#define RAW_STATS 0
+#define RAW_STATS 0
#endif
#else
-#define LINK_STATS 0
-#define IP_STATS 0
-#define IPFRAG_STATS 0
-#define ICMP_STATS 0
-#define UDP_STATS 0
-#define TCP_STATS 0
-#define MEM_STATS 0
-#define MEMP_STATS 0
-#define PBUF_STATS 0
-#define SYS_STATS 0
-#define RAW_STATS 0
-#define LWIP_STATS_DISPLAY 0
+#define LINK_STATS 0
+#define IP_STATS 0
+#define IPFRAG_STATS 0
+#define ICMP_STATS 0
+#define UDP_STATS 0
+#define TCP_STATS 0
+#define MEM_STATS 0
+#define MEMP_STATS 0
+#define PBUF_STATS 0
+#define SYS_STATS 0
+#define RAW_STATS 0
+#define LWIP_STATS_DISPLAY 0
#endif /* LWIP_STATS */
PBUF_POOL
} pbuf_flag;
-/* Definitions for the pbuf flag field (these are not the flags that
- are passed to pbuf_alloc()). */
+/* Definitions for the pbuf flag field. These are NOT the flags that
+ * are passed to pbuf_alloc(). */
#define PBUF_FLAG_RAM 0x00U /* Flags that pbuf data is stored in RAM */
#define PBUF_FLAG_ROM 0x01U /* Flags that pbuf data is stored in ROM */
#define PBUF_FLAG_POOL 0x02U /* Flags that the pbuf comes from the pbuf pool */
*/
u16_t tot_len;
- /* length of this buffer */
+ /** length of this buffer */
u16_t len;
- /* flags telling the type of pbuf */
+ /** flags telling the type of pbuf, see PBUF_FLAG_ */
u16_t flags;
/**
};
-/* pbuf_init():
-
- Initializes the pbuf module. The num parameter determines how many
- pbufs that should be allocated to the pbuf pool, and the size
- parameter specifies the size of the data allocated to those. */
void pbuf_init(void);
struct pbuf *pbuf_alloc(pbuf_layer l, u16_t size, pbuf_flag flag);
u16_t protocol;
- int (* recv)(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+ u8_t (* recv)(void *arg, struct raw_pcb *pcb, struct pbuf *p,
struct ip_addr *addr);
void *recv_arg;
};
err_t raw_connect (struct raw_pcb *pcb, struct ip_addr *ipaddr);
void raw_recv (struct raw_pcb *pcb,
- int (* recv)(void *arg, struct raw_pcb *pcb,
+ u8_t (* recv)(void *arg, struct raw_pcb *pcb,
struct pbuf *p,
struct ip_addr *addr),
void *recv_arg);
-err_t raw_send_to (struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr);
+err_t raw_sendto (struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr);
err_t raw_send (struct raw_pcb *pcb, struct pbuf *p);
/* The following functions are the lower layer interface to RAW. */
-int raw_input (struct pbuf *p, struct netif *inp);
+u8_t raw_input (struct pbuf *p, struct netif *inp);
void raw_init (void);
* only define this in sockets.c so it does not interfere
* with other projects namespaces where timeval is present
*/
-#ifdef LWIP_TIMEVAL_PRIVATE
+#ifndef LWIP_TIMEVAL_PRIVATE
+#define LWIP_TIMEVAL_PRIVATE 1
+#endif
+
+#if LWIP_TIMEVAL_PRIVATE
struct timeval {
long tv_sec; /* seconds */
long tv_usec; /* and microseconds */
/* Used within the TCP code only: */
err_t tcp_output (struct tcp_pcb *pcb);
void tcp_rexmit (struct tcp_pcb *pcb);
+void tcp_rexmit_rto (struct tcp_pcb *pcb);
#define TCP_SEQ_LEQ(a,b) ((s32_t)((a)-(b)) <= 0)
#define TCP_SEQ_GT(a,b) ((s32_t)((a)-(b)) > 0)
#define TCP_SEQ_GEQ(a,b) ((s32_t)((a)-(b)) >= 0)
-
+/* is b<=a<=c? */
+#if 0 /* see bug #10548 */
+#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b))
+#endif
+#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c))
#define TCP_FIN 0x01U
#define TCP_SYN 0x02U
#define TCP_RST 0x04U
TIME_WAIT = 10
};
-
/* the TCP protocol control block */
struct tcp_pcb {
-/* Common members of all PCB types */
+/** common PCB members */
IP_PCB;
-
-/* Protocol specific PCB members */
-
- struct tcp_pcb *next; /* for the linked list */
-
- enum tcp_state state; /* TCP state */
-
+/** protocol specific PCB members */
+ struct tcp_pcb *next; /* for the linked list */
+ enum tcp_state state; /* TCP state */
u8_t prio;
void *callback_arg;
#define TF_GOT_FIN (u8_t)0x20U /* Connection was closed by the remote end. */
#define TF_NODELAY (u8_t)0x40U /* Disable Nagle algorithm */
- /* receiver varables */
+ /* receiver variables */
u32_t rcv_nxt; /* next seqno expected */
u16_t rcv_wnd; /* receiver window */
u16_t mss; /* maximum segment size */
- /* RTT estimation variables. */
- u16_t rttest; /* RTT estimate in 500ms ticks */
+ /* RTT (round trip time) estimation variables */
+ u32_t rttest; /* RTT estimate in 500ms ticks */
u32_t rtseq; /* sequence number being timed */
- s16_t sa, sv;
+ s16_t sa, sv; /* @todo document this */
u16_t rto; /* retransmission time-out */
u8_t nrtx; /* number of retransmissions */
#define TCP_EVENT_RECV(pcb,p,err,ret) \
if((pcb)->recv != NULL) \
{ ret = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err)); } else { \
- pbuf_free(p); }
+ if (p) pbuf_free(p); }
#define TCP_EVENT_CONNECTED(pcb,err,ret) \
if((pcb)->connected != NULL) \
(ret = (pcb)->connected((pcb)->callback_arg,(pcb),(err)))
(errf)((arg),(err))
#endif /* LWIP_EVENT_API */
-/* This structure is used to repressent TCP segments when queued. */
+/* This structure represents a TCP segment on the unsent and unacked queues */
struct tcp_seg {
struct tcp_seg *next; /* used when putting segements on a queue */
struct pbuf *p; /* buffer containing data + TCP header */
void tcp_debug_print_flags(u8_t flags);
void tcp_debug_print_state(enum tcp_state s);
void tcp_debug_print_pcbs(void);
-int tcp_pcbs_sane(void);
+s16_t tcp_pcbs_sane(void);
#else
# define tcp_debug_print(tcphdr)
# define tcp_debug_print_flags(flags)
void udp_init (void);
#if UDP_DEBUG
-int udp_debug_print(struct udp_hdr *udphdr);
+void udp_debug_print(struct udp_hdr *udphdr);
#else
#define udp_debug_print(udphdr)
#endif
/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
byte alignment -> define MEM_ALIGNMENT to 2. */
-#define MEM_ALIGNMENT CYGPKG_LWIP_MEM_ALIGNMENT
+#define MEM_ALIGNMENT CYGNUM_LWIP_MEM_ALIGNMENT
/* MEM_SIZE: the size of the heap memory. If the application will send
a lot of data that needs to be copied, this should be set high. */
-#define MEM_SIZE CYGPKG_LWIP_MEM_SIZE
+#define MEM_SIZE CYGNUM_LWIP_MEM_SIZE
/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
sends a lot of data out of ROM (or other static memory), this
should be set high. */
-#define MEMP_NUM_PBUF CYGPKG_LWIP_MEMP_NUM_PBUF
+#define MEMP_NUM_PBUF CYGNUM_LWIP_MEMP_NUM_PBUF
/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
per active UDP "connection". */
-#define MEMP_NUM_UDP_PCB CYGPKG_LWIP_MEMP_NUM_UDP_PCB
+#define MEMP_NUM_UDP_PCB CYGNUM_LWIP_MEMP_NUM_UDP_PCB
/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
connections. */
-#define MEMP_NUM_TCP_PCB CYGPKG_LWIP_MEMP_NUM_TCP_PCB
+#define MEMP_NUM_TCP_PCB CYGNUM_LWIP_MEMP_NUM_TCP_PCB
/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
connections. */
-#define MEMP_NUM_TCP_PCB_LISTEN CYGPKG_LWIP_MEMP_NUM_TCP_PCB_LISTEN
+#define MEMP_NUM_TCP_PCB_LISTEN CYGNUM_LWIP_MEMP_NUM_TCP_PCB_LISTEN
/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
segments. */
-#define MEMP_NUM_TCP_SEG CYGPKG_LWIP_MEMP_NUM_TCP_SEG
+#define MEMP_NUM_TCP_SEG CYGNUM_LWIP_MEMP_NUM_TCP_SEG
/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
timeouts. */
-#define MEMP_NUM_SYS_TIMEOUT CYGPKG_LWIP_MEMP_NUM_SYS_TIMEOUT
+#define MEMP_NUM_SYS_TIMEOUT CYGNUM_LWIP_MEMP_NUM_SYS_TIMEOUT
/* The following four are used only with the sequential API and can be
set to 0 if the application only will use the raw API. */
/* MEMP_NUM_NETBUF: the number of struct netbufs. */
-#define MEMP_NUM_NETBUF CYGPKG_LWIP_MEMP_NUM_NETBUF
+#define MEMP_NUM_NETBUF CYGNUM_LWIP_MEMP_NUM_NETBUF
/* MEMP_NUM_NETCONN: the number of struct netconns. */
-#define MEMP_NUM_NETCONN CYGPKG_LWIP_MEMP_NUM_NETCONN
+#define MEMP_NUM_NETCONN CYGNUM_LWIP_MEMP_NUM_NETCONN
/* MEMP_NUM_APIMSG: the number of struct api_msg, used for
communication between the TCP/IP stack and the sequential
programs. */
-#define MEMP_NUM_API_MSG CYGPKG_LWIP_MEMP_NUM_APIMSG
+#define MEMP_NUM_API_MSG CYGNUM_LWIP_MEMP_NUM_APIMSG
/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used
for sequential API communication and incoming packets. Used in
src/api/tcpip.c. */
-#define MEMP_NUM_TCPIP_MSG CYGPKG_LWIP_MEMP_NUM_TCPIP_MSG
+#define MEMP_NUM_TCPIP_MSG CYGNUM_LWIP_MEMP_NUM_TCPIP_MSG
/* ---------- Pbuf options ---------- */
/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
-#define PBUF_POOL_SIZE CYGPKG_LWIP_PBUF_POOL_SIZE
+#define PBUF_POOL_SIZE CYGNUM_LWIP_PBUF_POOL_SIZE
/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
-#define PBUF_POOL_BUFSIZE CYGPKG_LWIP_PBUF_POOL_BUFSIZE
+#define PBUF_POOL_BUFSIZE CYGNUM_LWIP_PBUF_POOL_BUFSIZE
/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
link level header. */
-#define PBUF_LINK_HLEN CYGPKG_LWIP_PBUF_LINK_HLEN
+#define PBUF_LINK_HLEN CYGNUM_LWIP_PBUF_LINK_HLEN
/* ---------- TCP options ---------- */
-#define LWIP_TCP defined (CYGPKG_LWIP_TCP)
-#define TCP_TTL CYGPKG_LWIP_TCP_TTL
+#define LWIP_TCP defined(CYGPKG_LWIP_TCP)
+#define TCP_TTL CYGNUM_LWIP_TCP_TTL
/* Controls if TCP should queue segments that arrive out of
order. Define to 0 if your device is low on memory. */
-#define TCP_QUEUE_OOSEQ CYGPKG_LWIP_TCP_QUEUE_OOSEQ
-
+#define TCP_QUEUE_OOSEQ defined(CYGIMP_LWIP_TCP_QUEUE_OOSEQ)
+
/* TCP Maximum segment size. */
-#define TCP_MSS CYGPKG_LWIP_TCP_MSS
+#define TCP_MSS CYGNUM_LWIP_TCP_MSS
/* TCP sender buffer space (bytes). */
-#define TCP_SND_BUF CYGPKG_LWIP_TCP_SND_BUF
+#define TCP_SND_BUF CYGNUM_LWIP_TCP_SND_BUF
#define TCP_SNDLOWAT TCP_SND_BUF/2
/* TCP sender buffer space (pbufs). This must be at least = 2 *
TCP_SND_BUF/TCP_MSS for things to work. */
-#define TCP_SND_QUEUELEN CYGPKG_LWIP_TCP_SND_QUEUELEN
+#define TCP_SND_QUEUELEN CYGNUM_LWIP_TCP_SND_QUEUELEN
/* TCP receive window. */
-#define TCP_WND CYGPKG_LWIP_TCP_WND
+#define TCP_WND CYGNUM_LWIP_TCP_WND
/* Maximum number of retransmissions of data segments. */
-#define TCP_MAXRTX CYGPKG_LWIP_TCP_MAXRTX
+#define TCP_MAXRTX CYGNUM_LWIP_TCP_MAXRTX
/* Maximum number of retransmissions of SYN segments. */
-#define TCP_SYNMAXRTX CYGPKG_LWIP_TCP_SYNMAXRTX
+#define TCP_SYNMAXRTX CYGNUM_LWIP_TCP_SYNMAXRTX
/* ---------- ARP options ---------- */
-#define ARP_TABLE_SIZE CYGPKG_LWIP_ARP_TABLE_SIZE
+#define ARP_TABLE_SIZE CYGNUM_LWIP_ARP_TABLE_SIZE
/* ---------- IP options ---------- */
/* Define IP_FORWARD to 1 if you wish to have the ability to forward
IP packets across network interfaces. If you are going to run lwIP
on a device with only one network interface, define this to 0. */
-#define IP_FORWARD CYGPKG_LWIP_IP_FORWARD
+#define IP_FORWARD defined(CYGFUN_LWIP_IP_FORWARD)
+
/* If defined to 1, IP options are allowed (but not parsed). If
defined to 0, all packets with IP options are dropped. */
-#define IP_OPTIONS CYGPKG_LWIP_IP_OPTIONS
+#define IP_OPTIONS defined(CYGFUN_LWIP_IP_OPTIONS)
+
/* ---------- ICMP options ---------- */
-#define ICMP_TTL CYGPKG_LWIP_ICMP_TTL
+#define ICMP_TTL CYGNUM_LWIP_ICMP_TTL
/* ---------- DHCP options ---------- */
/* Define LWIP_DHCP to 1 if you want DHCP configuration of
interfaces.*/
+#define LWIP_DHCP defined(CYGPKG_LWIP_DHCP)
+#define DHCP_DOES_ARP_CHECK defined(CYGOPT_LWIP_DHCP_DOES_ARP_CHECK)
-#ifdef CYGPKG_LWIP_DHCP
-#define LWIP_DHCP CYGPKG_LWIP_DHCP
-
-/* 1 if you want to do an ARP check on the offered address
- (recommended). */
-#define DHCP_DOES_ARP_CHECK CYGPKG_LWIP_DHCP_DOES_ARP_CHECK
-#endif
/* ---------- UDP options ---------- */
-#define LWIP_UDP CYGPKG_LWIP_UDP
-#define UDP_TTL CYGPKG_LWIP_UDP_TTL
+#define LWIP_UDP defined(CYGPKG_LWIP_UDP)
+#define UDP_TTL CYGNUM_LWIP_UDP_TTL
/* ---------- RAW socket support ---------- */
-#define LWIP_RAW CYGPKG_LWIP_RAW
+#define LWIP_RAW defined(CYGFUN_LWIP_RAW)
/* ---------- SLIP options --------- */
#define LWIP_SLIP defined(CYGPKG_LWIP_SLIP)
-#define SLIP_DEV CYGPKG_LWIP_SLIP_DEV
+#define SLIP_DEV CYGDAT_LWIP_SLIP_DEV
+
+/* ---------- LOOPIF options --------- */
+#define LWIP_HAVE_LOOPIF defined(CYGFUN_LWIP_LOOPIF)
-#define LWIP_HAVE_LOOPIF defined (CYGPKG_LWIP_LOOPIF)
-/* ---------- PPP options --------- */
+/* ---------- PPP options --------- */
#define PPP_SUPPORT defined(CYGPKG_LWIP_PPP)
-#define PPP_DEV CYGPKG_LWIP_PPP_DEV
+#define PPP_DEV CYGDAT_LWIP_PPP_DEV
#define MD5_SUPPORT 1
-
-#if defined(CYGPKG_LWIP_PPP_PAP_AUTH)
-#define PAP_SUPPORT 1
+#ifdef CYGIMP_LWIP_PPP_PAP_AUTH
+#define PAP_SUPPORT 1
#else
-#define PAP_SUPPORT 0
+#define PAP_SUPPORT 0
#endif
-
-#if defined(CYGPKG_LWIP_PPP_CHAP_AUTH)
-#define CHAP_SUPPORT 1
+#ifdef CYGIMP_LWIP_PPP_CHAP_AUTH
+#define CHAP_SUPPORT 1
#else
-#define CHAP_SUPPORT 0
+#define CHAP_SUPPORT 0
#endif
+
/* ------- Thread priorities ---------------*/
-#define TCPIP_THREAD_PRIO CYGPKG_LWIP_TCPIP_THREAD_PRIORITY
-#define SLIPIF_THREAD_PRIO CYGPKG_LWIP_SLIPIF_THREAD_PRIORITY
-#define PPP_THREAD_PRIO CYGPKG_LWIP_PPP_THREAD_PRIORITY
+#define TCPIP_THREAD_PRIO CYGNUM_LWIP_NETWORK_THREAD_PRIORITY
+#define SLIPIF_THREAD_PRIO CYGNUM_LWIP_SLIPIF_THREAD_PRIORITY
+#define PPP_THREAD_PRIO CYGNUM_LWIP_PPP_THREAD_PRIORITY
+
+
/* ---------- Statistics options ---------- */
-#define LWIP_STATS defined(CYGPKG_LWIP_STATS)
+#define LWIP_STATS defined(CYGDBG_LWIP_STATS)
+
+
+// --------- Sockets options --------------
+#define LWIP_COMPAT_SOCKETS defined(CYGFUN_LWIP_COMPAT_SOCKETS)
+
/* ---------- Debug options ---------- */
-#if !defined(CYGPKG_LWIP_ASSERTS)
+#if !defined(CYGDBG_LWIP_ASSERTS)
#define LWIP_NOASSERT
#endif
-#if defined(CYGPKG_LWIP_DEBUG)
+#if defined(CYGDBG_LWIP_DEBUG)
#define LWIP_DEBUG
#define MEM_DEBUG DBG_ON
#define MEMP_DEBUG DBG_ON
#ifndef __NETIF_ETHARP_H__
#define __NETIF_ETHARP_H__
-#ifndef PAD_ETH_SIZE
-#define PAD_ETH_SIZE 0
+#ifndef ETH_PAD_SIZE
+#define ETH_PAD_SIZE 0
#endif
#include "lwip/pbuf.h"
PACK_STRUCT_FIELD(u8_t addr[6]);
} PACK_STRUCT_STRUCT;
PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
PACK_STRUCT_BEGIN
struct eth_hdr {
-#if PAD_ETH_SIZE
- PACK_STRUCT_FIELD(u8_t padding[PAD_ETH_SIZE]);
+#if ETH_PAD_SIZE
+ PACK_STRUCT_FIELD(u8_t padding[ETH_PAD_SIZE]);
#endif
PACK_STRUCT_FIELD(struct eth_addr dest);
PACK_STRUCT_FIELD(struct eth_addr src);
PACK_STRUCT_FIELD(u16_t type);
} PACK_STRUCT_STRUCT;
PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
PACK_STRUCT_BEGIN
/** the ARP message */
struct etharp_hdr {
PACK_STRUCT_FIELD(struct ip_addr2 dipaddr);
} PACK_STRUCT_STRUCT;
PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
PACK_STRUCT_BEGIN
struct ethip_hdr {
PACK_STRUCT_FIELD(struct eth_hdr eth);
PACK_STRUCT_FIELD(struct ip_hdr ip);
-};
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
#ifdef PACK_STRUCT_USE_INCLUDES
# include "arch/epstruct.h"
#endif
-#define ARP_TMR_INTERVAL 10000
+/** 5 seconds period */
+#define ARP_TMR_INTERVAL 5000
#define ETHTYPE_ARP 0x0806
#define ETHTYPE_IP 0x0800
void etharp_init(void);
void etharp_tmr(void);
-struct pbuf *etharp_ip_input(struct netif *netif, struct pbuf *p);
-struct pbuf *etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr,
+void etharp_ip_input(struct netif *netif, struct pbuf *p);
+void etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr,
struct pbuf *p);
-struct pbuf *etharp_output(struct netif *netif, struct ip_addr *ipaddr,
+err_t etharp_output(struct netif *netif, struct ip_addr *ipaddr,
struct pbuf *q);
err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q);
-
-
+err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr);
#endif /* __NETIF_ARP_H__ */
-/* network.h for compatibility with the other eCos network stacks */
+#ifndef CYGONCE_NETWORK_H
+#define CYGONCE_NETWORK_H
+//=============================================================================
+//
+// network.h
+//
+// Misc network support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Nick Garnett
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Jani Monoses
+// Contributors: Jani Monoses
+// Date: 2006-03-23
+// Purpose:
+// Description:
+//
+//
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
-#include <lwip/sys.h> /* lwIP stack includes */
-#define LWIP_COMPAT_SOCKETS 1
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//=============================================================================
+// INCLUDES
+//=============================================================================
+#include <lwip/sys.h> // lwIP stack includes
#include <lwip/sockets.h>
#include <lwip/inet.h>
+
+
+#ifdef __cplusplus
+}
+#endif
+
+//-----------------------------------------------------------------------------
+#endif // #ifndef CYGONCE_NETWORK_H
offset -= p->len;
} else {
for(i = offset; i < p->len; ++i) {
- ((char *)dataptr)[left] = ((char *)p->payload)[i];
+ ((u8_t *)dataptr)[left] = ((u8_t *)p->payload)[i];
if (++left >= len) {
return;
}
if (conn->recvmbox != SYS_MBOX_NULL) {
while (sys_arch_mbox_fetch(conn->recvmbox, &mem, 1) != SYS_ARCH_TIMEOUT) {
if (conn->type == NETCONN_TCP) {
- pbuf_free((struct pbuf *)mem);
+ if(mem != NULL)
+ pbuf_free((struct pbuf *)mem);
} else {
- netbuf_delete((struct netbuf *)mem);
+ netbuf_delete((struct netbuf *)mem);
}
}
sys_mbox_free(conn->recvmbox);
case NETCONN_UDPLITE:
case NETCONN_UDPNOCHKSUM:
case NETCONN_UDP:
+#if LWIP_UDP
if (conn->pcb.udp == NULL ||
((conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0))
return ERR_CONN;
*addr = (conn->pcb.udp->remote_ip);
*port = conn->pcb.udp->remote_port;
+#endif
break;
+
case NETCONN_TCP:
+#if LWIP_TCP
if (conn->pcb.tcp == NULL)
return ERR_CONN;
*addr = (conn->pcb.tcp->remote_ip);
*port = conn->pcb.tcp->remote_port;
+#endif
break;
}
return (conn->err = ERR_OK);
{
switch (conn->type) {
case NETCONN_RAW:
+#if LWIP_RAW
*addr = &(conn->pcb.raw->local_ip);
*port = conn->pcb.raw->protocol;
+#endif
break;
case NETCONN_UDPLITE:
case NETCONN_UDPNOCHKSUM:
case NETCONN_UDP:
+#if LWIP_UDP
*addr = &(conn->pcb.udp->local_ip);
*port = conn->pcb.udp->local_port;
+#endif
break;
+
case NETCONN_TCP:
+#if LWIP_TCP
*addr = &(conn->pcb.tcp->local_ip);
*port = conn->pcb.tcp->local_port;
+#endif
break;
}
return (conn->err = ERR_OK);
api_msg_post(msg);
sys_mbox_fetch(conn->mbox, NULL);
if (conn->err == ERR_OK) {
- dataptr = (void *)((char *)dataptr + len);
+ dataptr = (void *)((u8_t *)dataptr + len);
size -= len;
} else if (conn->err == ERR_MEM) {
conn->err = ERR_OK;
#include "lwip/tcpip.h"
#if LWIP_RAW
-static int
+static u8_t
recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p,
struct ip_addr *addr)
{
/* Allocate a PCB for this connection */
switch(msg->conn->type) {
-#if LWIP_RAW
case NETCONN_RAW:
+#if LWIP_RAW
msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field */
raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
- break;
#endif
-#if LWIP_UDP
+ break;
+
+
case NETCONN_UDPLITE:
+#if LWIP_UDP
msg->conn->pcb.udp = udp_new();
if(msg->conn->pcb.udp == NULL) {
msg->conn->err = ERR_MEM;
udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
break;
+#endif /* LWIP_UDP */
case NETCONN_UDPNOCHKSUM:
+#if LWIP_UDP
msg->conn->pcb.udp = udp_new();
if(msg->conn->pcb.udp == NULL) {
msg->conn->err = ERR_MEM;
udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
break;
+#endif /* LWIP_UDP */
case NETCONN_UDP:
+#if LWIP_UDP
msg->conn->pcb.udp = udp_new();
if(msg->conn->pcb.udp == NULL) {
msg->conn->err = ERR_MEM;
break;
}
udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
- break;
#endif /* LWIP_UDP */
-#if LWIP_TCP
+ break;
+
case NETCONN_TCP:
+#if LWIP_TCP
msg->conn->pcb.tcp = tcp_new();
if(msg->conn->pcb.tcp == NULL) {
msg->conn->err = ERR_MEM;
break;
}
setup_tcp(msg->conn);
- break;
#endif
+ break;
}
{
switch (msg->conn->type) {
-#if LWIP_RAW
case NETCONN_RAW:
/* Do nothing as connecting is only a helper for upper lwip layers */
break;
-#endif
-#if LWIP_UDP
+
case NETCONN_UDPLITE:
/* FALLTHROUGH */
case NETCONN_UDPNOCHKSUM:
/* FALLTHROUGH */
case NETCONN_UDP:
+#if LWIP_UDP
udp_disconnect(msg->conn->pcb.udp);
+#endif
break;
-#endif
case NETCONN_TCP:
break;
}
{
if (msg->conn->pcb.tcp != NULL) {
switch (msg->conn->type) {
-#if LWIP_RAW
+
case NETCONN_RAW:
+#if LWIP_RAW
LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen RAW: cannot listen for RAW.\n"));
- break;
#endif
-#if LWIP_UDP
+ break;
+
case NETCONN_UDPLITE:
/* FALLTHROUGH */
case NETCONN_UDPNOCHKSUM:
/* FALLTHROUGH */
case NETCONN_UDP:
+#if LWIP_UDP
LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen UDP: cannot listen for UDP.\n"));
- break;
#endif /* LWIP_UDP */
-#if LWIP_TCP
+ break;
+
+
case NETCONN_TCP:
+#if LWIP_TCP
msg->conn->pcb.tcp = tcp_listen(msg->conn->pcb.tcp);
- if (msg->conn->pcb.tcp == NULL) {
- msg->conn->err = ERR_MEM;
- } else {
- if (msg->conn->acceptmbox == SYS_MBOX_NULL) {
- msg->conn->acceptmbox = sys_mbox_new();
- if (msg->conn->acceptmbox == SYS_MBOX_NULL) {
- msg->conn->err = ERR_MEM;
- break;
- }
- }
- tcp_arg(msg->conn->pcb.tcp, msg->conn);
- tcp_accept(msg->conn->pcb.tcp, accept_function);
+ if (msg->conn->pcb.tcp == NULL)
+ {
+ msg->conn->err = ERR_MEM;
+ }
+ else
+ {
+ if (msg->conn->acceptmbox == SYS_MBOX_NULL)
+ {
+ msg->conn->acceptmbox = sys_mbox_new();
+ if (msg->conn->acceptmbox == SYS_MBOX_NULL)
+ {
+ msg->conn->err = ERR_MEM;
+ break;
+ }
+ }
+ tcp_arg(msg->conn->pcb.tcp, msg->conn);
+ tcp_accept(msg->conn->pcb.tcp, accept_function);
}
#endif
+ break;
+
default:
break;
}
{
if (msg->conn->pcb.tcp != NULL) {
switch (msg->conn->type) {
-#if LWIP_RAW
+
case NETCONN_RAW:
+#if LWIP_RAW
LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept RAW: cannot accept for RAW.\n"));
- break;
#endif
-#if LWIP_UDP
+ break;
+
case NETCONN_UDPLITE:
/* FALLTHROUGH */
case NETCONN_UDPNOCHKSUM:
/* FALLTHROUGH */
- case NETCONN_UDP:
+ case NETCONN_UDP:
+#if LWIP_UDP
LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept UDP: cannot accept for UDP.\n"));
- break;
#endif /* LWIP_UDP */
+ break;
case NETCONN_TCP:
break;
}
{
if (msg->conn->pcb.tcp != NULL) {
switch (msg->conn->type) {
-#if LWIP_RAW
+
case NETCONN_RAW:
+#if LWIP_RAW
raw_send(msg->conn->pcb.raw, msg->msg.p);
- break;
#endif
-#if LWIP_UDP
+ break;
+
case NETCONN_UDPLITE:
/* FALLTHROUGH */
case NETCONN_UDPNOCHKSUM:
/* FALLTHROUGH */
case NETCONN_UDP:
+#if LWIP_UDP
udp_send(msg->conn->pcb.udp, msg->msg.p);
- break;
#endif /* LWIP_UDP */
+ break;
+
case NETCONN_TCP:
break;
}
#endif
if (msg->conn->pcb.tcp != NULL) {
switch (msg->conn->type) {
-#if LWIP_RAW
+
case NETCONN_RAW:
+#if LWIP_RAW
msg->conn->err = ERR_VAL;
- break;
#endif
-#if LWIP_UDP
+ break;
+
+
case NETCONN_UDPLITE:
/* FALLTHROUGH */
case NETCONN_UDPNOCHKSUM:
/* FALLTHROUGH */
case NETCONN_UDP:
+#if LWIP_UDP
msg->conn->err = ERR_VAL;
- break;
#endif /* LWIP_UDP */
-#if LWIP_TCP
- case NETCONN_TCP:
+ break;
+
+ case NETCONN_TCP:
+#if LWIP_TCP
err = tcp_write(msg->conn->pcb.tcp, msg->msg.w.dataptr,
msg->msg.w.len, msg->msg.w.copy);
/* This is the Nagle algorithm: inhibit the sending of new TCP
(*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDMINUS, msg->msg.w.len);
}
#endif
+ break;
+
+
default:
break;
}
if (msg->conn->pcb.tcp != NULL) {
switch (msg->conn->type) {
-#if LWIP_RAW
+
case NETCONN_RAW:
break;
-#endif
-#if LWIP_UDP
+
+
case NETCONN_UDPLITE:
/* FALLTHROUGH */
case NETCONN_UDPNOCHKSUM:
/* FALLTHROUGH */
case NETCONN_UDP:
break;
-#endif /* LWIP_UDP */
-#if LWIP_TCP
+
+
case NETCONN_TCP:
+#if LWIP_TCP
if (msg->conn->pcb.tcp->state == LISTEN) {
err = tcp_close(msg->conn->pcb.tcp);
}
msg->conn->err = err;
#endif
+ break;
+
default:
break;
}
*
*/
+#include <string.h>
+#include <errno.h>
+
#include "lwip/opt.h"
#include "lwip/api.h"
#include "lwip/arch.h"
#include "lwip/sys.h"
-#define LWIP_TIMEVAL_PRIVATE
#include "lwip/sockets.h"
#define NUM_SOCKETS MEMP_NUM_NETCONN
EADDRINUSE /* ERR_USE -10 Address in use. */
};
+#define ERR_TO_ERRNO_TABLE_SIZE \
+ (sizeof(err_to_errno_table)/sizeof(err_to_errno_table[0]))
+
#define err_to_errno(err) \
- ((err) < (sizeof(err_to_errno_table)/sizeof(int))) ? \
- err_to_errno_table[-(err)] : EIO
+ (-(err) >= 0 && -(err) < ERR_TO_ERRNO_TABLE_SIZE ? \
+ err_to_errno_table[-(err)] : EIO)
#ifdef ERRNO
#define set_errno(err) errno = (err)
ip_addr_debug_print(SOCKETS_DEBUG, addr);
LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen));
} else {
-#if SOCKETS_DEBUG > 0
+#if SOCKETS_DEBUG
addr = netbuf_fromaddr(buf);
port = netbuf_fromport(buf);
lwip_send(int s, void *data, int size, unsigned int flags)
{
struct lwip_socket *sock;
- struct netbuf *buf;
err_t err;
LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%d, flags=0x%x)\n", s, data, size, flags));
}
switch (netconn_type(sock->conn)) {
+#if LWIP_RAW
case NETCONN_RAW:
+#endif
+#if LWIP_UDP
case NETCONN_UDP:
case NETCONN_UDPLITE:
case NETCONN_UDPNOCHKSUM:
+ {
+ struct netbuf *buf;
/* create a buffer */
buf = netbuf_new();
/* deallocated the buffer */
netbuf_delete(buf);
- break;
+ }
+ break;
+#endif
+#if LWIP_TCP
case NETCONN_TCP:
err = netconn_write(sock->conn, data, size, NETCONN_COPY);
break;
+#endif
default:
err = ERR_ARG;
break;
/* create a netconn */
switch (type) {
+#if LWIP_RAW
case SOCK_RAW:
conn = netconn_new_with_proto_and_callback(NETCONN_RAW, protocol, event_callback);
LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
break;
+#endif
+#if LWIP_UDP
case SOCK_DGRAM:
conn = netconn_new_with_callback(NETCONN_UDP, event_callback);
LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
break;
+#endif
+#if LWIP_TCP
case SOCK_STREAM:
conn = netconn_new_with_callback(NETCONN_TCP, event_callback);
LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
break;
+#endif
default:
LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n", domain, type, protocol));
set_errno(EINVAL);
case SO_TYPE:
switch (sock->conn->type) {
+#if LWIP_RAW
case NETCONN_RAW:
*(int*)optval = SOCK_RAW;
break;
+#endif
+#if LWIP_TCP
case NETCONN_TCP:
*(int*)optval = SOCK_STREAM;
break;
+#endif
+#if LWIP_UDP
case NETCONN_UDP:
case NETCONN_UDPLITE:
case NETCONN_UDPNOCHKSUM:
*(int*)optval = SOCK_DGRAM;
break;
+#endif
default: /* unrecognized socket type */
*(int*)optval = sock->conn->type;
LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n", s, *(int *)optval));
LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n", s, (*(int*)optval)?"on":"off") );
break;
case TCP_KEEPALIVE:
- *(int*)optval = sock->conn->pcb.tcp->keepalive;
+ *(int*)optval = (int)sock->conn->pcb.tcp->keepalive;
LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPALIVE) = %d\n", s, *(int *)optval));
break;
} /* switch */
break;
case TCP_KEEPALIVE:
sock->conn->pcb.tcp->keepalive = (u32_t)(*(int*)optval);
- LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %u\n", s, sock->conn->pcb.tcp->keepalive));
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %lu\n", s, sock->conn->pcb.tcp->keepalive));
break;
} /* switch */
break;
#include "lwip/pbuf.h"
#include "lwip/ip.h"
+#include "lwip/ip_frag.h"
#include "lwip/udp.h"
#include "lwip/tcp.h"
static void (* tcpip_init_done)(void *arg) = NULL;
static void *tcpip_init_done_arg;
static sys_mbox_t mbox;
+
#if LWIP_TCP
static int tcpip_tcp_timer_active = 0;
-
-
static void
tcpip_tcp_timer(void *arg)
{
(void)arg;
+ /* call TCP timer handler */
tcp_tmr();
+ /* timer still needed? */
if (tcp_active_pcbs || tcp_tw_pcbs) {
+ /* restart timer */
sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
} else {
- tcpip_tcp_timer_active = 0;
+ /* disable timer */
+ tcpip_tcp_timer_active = 0;
}
}
+#if !NO_SYS
void
tcp_timer_needed(void)
{
+ /* timer is off but needed again? */
if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) {
- tcpip_tcp_timer_active = 1;
+ /* enable and start timer */
+ tcpip_tcp_timer_active = 1;
sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
}
}
+#endif /* !NO_SYS */
#endif /* LWIP_TCP */
+#if IP_REASSEMBLY
+static void
+ip_timer(void *data)
+{
+ LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: ip_reass_tmr()\n"));
+ ip_reass_tmr();
+ sys_timeout(1000, ip_timer, NULL);
+}
+#endif
+
static void
tcpip_thread(void *arg)
{
#endif
#if LWIP_TCP
tcp_init();
+#endif
+#if IP_REASSEMBLY
+ sys_timeout(1000, ip_timer, NULL);
#endif
if (tcpip_init_done != NULL) {
tcpip_init_done(tcpip_init_done_arg);
* init.c - misc lwip ecos glue functions
*/
#include <pkgconf/system.h>
+#include <pkgconf/net_lwip.h>
#include "lwip/opt.h"
#include "lwip/sys.h"
#include "lwip/memp.h"
}
-void tcpip_init_done(void * arg)
-{
- sys_sem_t *sem = arg;
- sys_sem_signal(*sem);
-}
-
struct netif mynetif, loopif;
void lwip_set_addr(struct netif *netif);
#if PPP_SUPPORT
struct netif ecos_loopif;
#endif
+#ifdef CYGPKG_LWIP_ETH
+static void
+arp_timer(void *arg)
+{
+ etharp_tmr();
+ sys_timeout(ARP_TMR_INTERVAL, (sys_timeout_handler) arp_timer, NULL);
+}
+#endif
+
+#if LWIP_DHCP
+static void lwip_dhcp_fine_tmr(void *arg)
+{
+ dhcp_fine_tmr();
+ sys_timeout(500, (sys_timeout_handler) lwip_dhcp_fine_tmr, NULL);
+}
+
+static void lwip_dhcp_coarse_tmr(void *arg)
+{
+ dhcp_coarse_tmr();
+ sys_timeout(60000, (sys_timeout_handler) lwip_dhcp_coarse_tmr, NULL);
+}
+#endif
+
+
+//
+// This function is called when tcpip thread finished initialisation.
+// We start several timers here - these timers are all handled in the
+// tcpip thread. That means that also the DHCP stuff is handled in the
+// TCPIP thread. If this causes any trouble than it may be necessaray to
+// use an own DHCP thread insted.
+//
+void tcpip_init_done(void * arg)
+{
+#ifdef CYGPKG_LWIP_ETH
+ sys_timeout(ARP_TMR_INTERVAL, (sys_timeout_handler) arp_timer, NULL);
+#endif
+#ifdef CYGOPT_LWIP_DHCP_MANAGEMENT
+ sys_timeout(500, (sys_timeout_handler) lwip_dhcp_fine_tmr, NULL);
+ sys_timeout(60000, (sys_timeout_handler) lwip_dhcp_coarse_tmr, NULL);
+#endif
+ sys_sem_t *sem = arg;
+ sys_sem_signal(*sem);
+}
+
+
/*
* Called by the eCos application at startup
* wraps various init calls
int
lwip_init(void)
{
+#if LWIP_HAVE_LOOPIF
struct ip_addr ipaddr, netmask, gw;
+#endif
static int inited = 0;
sys_sem_t sem;
if (inited)
return 0;
}
+
+err_t lwip_dummy_netif_init(struct netif *netif)
+{
+ return ERR_OK;
+}
+
+
void
lwip_set_addr(struct netif *netif)
{
struct ip_addr ipaddr, netmask, gw;
+
+#if LWIP_DHCP
+ IP4_ADDR(&gw, 0,0,0,0);
+ IP4_ADDR(&ipaddr, 0,0,0,0);
+ IP4_ADDR(&netmask, 0,0,0,0);
+
+ netif_add(netif, &ipaddr, &netmask, &gw, netif->state, lwip_dummy_netif_init, tcpip_input);
+ netif_set_default(netif);
+ netif_set_up(netif); // new step from lwip 1.0.0
+#else
+ IP_ADDR(&gw, CYGDAT_LWIP_SERV_ADDR);
+ IP_ADDR(&ipaddr, CYGDAT_LWIP_MY_ADDR);
+ IP_ADDR(&netmask, CYGDAT_LWIP_NETMASK);
+
+ netif_add(netif, &ipaddr, &netmask, &gw, netif->state, lwip_dummy_netif_init, tcpip_input);
+ netif_set_default(netif);
+ netif_set_up(netif); // new step from lwip 1.0.0
+#endif
+}
- IP_ADDR(&gw, CYGPKG_LWIP_SERV_ADDR);
- IP_ADDR(&ipaddr, CYGPKG_LWIP_MY_ADDR);
- IP_ADDR(&netmask, CYGPKG_LWIP_NETMASK);
- netif_set_addr(netif, &ipaddr, &netmask, &gw);
- netif->next = netif_list;
- netif_list = netif;
-
- netif->input = tcpip_input;
- //netif->input = ip_input;
+void lwip_dhcp_init(struct netif *netif)
+{
+#ifdef CYGOPT_LWIP_DHCP_MANAGEMENT
+ dhcp_start(netif);
+#endif
}
+
#ifdef CYGPKG_LWIP_ETH
//io eth stuff
}
+
// Initialize all network devices
static void
init_hw_drivers(void)
}
}
-static void
-arp_timer(void *arg)
-{
- etharp_tmr();
- sys_timeout(ARP_TMR_INTERVAL, (sys_timeout_handler) arp_timer, NULL);
-}
-
+extern struct netif *netif_default;
static void
ecosglue_init(void)
{
- cyg_semaphore_init(&delivery, 0);
- init_hw_drivers();
- sys_thread_new(input_thread, (void*)0, CYGPKG_LWIP_ETH_THREAD_PRIORITY);
- etharp_init();
- sys_timeout(ARP_TMR_INTERVAL, (sys_timeout_handler) arp_timer, NULL);
+ etharp_init();
+ cyg_semaphore_init(&delivery, 0);
+ //
+ // start input thread before hardware drivers are initialized because
+ // init_hw_drivers() calls dhcp_init() if DHCP support is configured
+ // and dhcp_init() requires a running input thread
+ //
+ sys_thread_new(input_thread, (void*)0, CYGNUM_LWIP_ETH_THREAD_PRIORITY);
+ init_hw_drivers();
}
#endif //CYGPKG_LWIP_ETH
(char *)arg , stack, CYGNUM_LWIP_THREAD_STACK_SIZE, &(nt->th), &(nt->t) );
cyg_thread_resume(nt->th);
- return NULL;
+ return nt->th;
}
/*
* to a physical address when sending a packet, and the second part answers
* requests from other machines for our physical address.
*
- * This implementation complies with RFC 826 (Ethernet ARP) and supports
- * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6.
+ * This implementation complies with RFC 826 (Ethernet ARP). It supports
+ * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6
+ * if an interface calls etharp_query(our_netif, its_ip_addr, NULL) upon
+ * address change.
*/
/*
*
* This file is part of the lwIP TCP/IP stack.
*
- * Author: Adam Dunkels <adam@sics.se>
- *
*/
-/**
- * TODO:
- * - pbufs should be sent from the queue once an ARP entry state
- * goes from PENDING to STABLE.
- * - Non-PENDING entries MUST NOT have queued packets.
- */
-
-/*
- * TODO:
- *
-RFC 3220 4.6 IP Mobility Support for IPv4 January 2002
-
- - A Gratuitous ARP [45] is an ARP packet sent by a node in order
- to spontaneously cause other nodes to update an entry in their
- ARP cache. A gratuitous ARP MAY use either an ARP Request or
- an ARP Reply packet. In either case, the ARP Sender Protocol
- Address and ARP Target Protocol Address are both set to the IP
- address of the cache entry to be updated, and the ARP Sender
- Hardware Address is set to the link-layer address to which this
- cache entry should be updated. When using an ARP Reply packet,
- the Target Hardware Address is also set to the link-layer
- address to which this cache entry should be updated (this field
- is not used in an ARP Request packet).
-
- In either case, for a gratuitous ARP, the ARP packet MUST be
- transmitted as a local broadcast packet on the local link. As
- specified in [36], any node receiving any ARP packet (Request
- or Reply) MUST update its local ARP cache with the Sender
- Protocol and Hardware Addresses in the ARP packet, if the
- receiving node has an entry for that IP address already in its
- ARP cache. This requirement in the ARP protocol applies even
- for ARP Request packets, and for ARP Reply packets that do not
- match any ARP Request transmitted by the receiving node [36].
-*
- My suggestion would be to send a ARP request for our newly obtained
- address upon configuration of an Ethernet interface.
-
-*/
-
#include "lwip/opt.h"
#include "lwip/inet.h"
#include "netif/etharp.h"
# include "lwip/dhcp.h"
#endif
-/* allows new queueing code to be disabled (0) for regression testing */
-#define ARP_NEW_QUEUE 1
-
-/** the time an ARP entry stays valid after its last update, (120 * 10) seconds = 20 minutes. */
-#define ARP_MAXAGE 120
-/** the time an ARP entry stays pending after first request, (1 * 10) seconds = 10 seconds. */
-#define ARP_MAXPENDING 1
+/** the time an ARP entry stays valid after its last update,
+ * (240 * 5) seconds = 20 minutes.
+ */
+#define ARP_MAXAGE 240
+/** the time an ARP entry stays pending after first request,
+ * (2 * 5) seconds = 10 seconds.
+ *
+ * @internal Keep this number at least 2, otherwise it might
+ * run out instantly if the timeout occurs directly after a request.
+ */
+#define ARP_MAXPENDING 2
#define HWTYPE_ETHERNET 1
ETHARP_STATE_EMPTY,
ETHARP_STATE_PENDING,
ETHARP_STATE_STABLE,
- /** @internal convenience transitional state used in etharp_tmr() */
+ /** @internal transitional state used in etharp_tmr() for convenience*/
ETHARP_STATE_EXPIRED
};
struct etharp_entry {
- struct ip_addr ipaddr;
- struct eth_addr ethaddr;
- enum etharp_state state;
#if ARP_QUEUEING
/**
* Pointer to queue of pending outgoing packets on this ARP entry.
- * Must be at most a single packet for now. */
- struct pbuf *p;
+ */
+ struct pbuf *p;
#endif
+ struct ip_addr ipaddr;
+ struct eth_addr ethaddr;
+ enum etharp_state state;
u8_t ctime;
};
static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}};
static struct etharp_entry arp_table[ARP_TABLE_SIZE];
-static s8_t find_arp_entry(void);
-/** ask update_arp_entry() to add instead of merely update an ARP entry */
-#define ARP_INSERT_FLAG 1
-static struct pbuf *update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags);
+/**
+ * Try hard to create a new entry - we want the IP address to appear in
+ * the cache (even if this means removing an active entry or so). */
+#define ETHARP_TRY_HARD 1
+
+static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags);
+static err_t update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags);
/**
* Initializes ARP module.
*/
void
etharp_init(void)
{
- s8_t i;
+ u8_t i;
/* clear ARP entries */
for(i = 0; i < ARP_TABLE_SIZE; ++i) {
arp_table[i].state = ETHARP_STATE_EMPTY;
/**
* Clears expired entries in the ARP table.
*
- * This function should be called every ETHARP_TMR_INTERVAL microseconds (10 seconds),
+ * This function should be called every ETHARP_TMR_INTERVAL microseconds (5 seconds),
* in order to expire entries in the ARP table.
*/
void
etharp_tmr(void)
{
- s8_t i;
+ u8_t i;
LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n"));
/* remove expired entries from the ARP table */
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
arp_table[i].ctime++;
- /* a resolved/stable entry? */
+ /* stable entry? */
if ((arp_table[i].state == ETHARP_STATE_STABLE) &&
/* entry has become old? */
(arp_table[i].ctime >= ARP_MAXAGE)) {
- LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired stable entry %u.\n", i));
- arp_table[i].state = ETHARP_STATE_EXPIRED;
- /* an unresolved/pending entry? */
- } else if ((arp_table[i].state == ETHARP_STATE_PENDING) &&
- /* entry unresolved/pending for too long? */
- (arp_table[i].ctime >= ARP_MAXPENDING)) {
- LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired pending entry %u.\n", i));
+ LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired stable entry %"U16_F".\n", (u16_t)i));
arp_table[i].state = ETHARP_STATE_EXPIRED;
+ /* pending entry? */
+ } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+ /* entry unresolved/pending for too long? */
+ if (arp_table[i].ctime >= ARP_MAXPENDING) {
+ LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired pending entry %"U16_F".\n", (u16_t)i));
+ arp_table[i].state = ETHARP_STATE_EXPIRED;
+#if ARP_QUEUEING
+ } else if (arp_table[i].p != NULL) {
+ /* resend an ARP query here */
+#endif
+ }
}
/* clean up entries that have just been expired */
if (arp_table[i].state == ETHARP_STATE_EXPIRED) {
/* and empty packet queue */
if (arp_table[i].p != NULL) {
/* remove all queued packets */
- LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: freeing entry %u, packet queue %p.\n", i, (void *)(arp_table[i].p)));
+ LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].p)));
pbuf_free(arp_table[i].p);
arp_table[i].p = NULL;
}
}
/**
- * Return an empty ARP entry (possibly recycling the oldest stable entry).
- *
- * @return The ARP entry index that is available, ERR_MEM if no usable
- * entry is found.
+ * Search the ARP table for a matching or new entry.
+ *
+ * If an IP address is given, return a pending or stable ARP entry that matches
+ * the address. If no match is found, create a new entry with this address set,
+ * but in state ETHARP_EMPTY. The caller must check and possibly change the
+ * state of the returned entry.
+ *
+ * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY.
+ *
+ * In all cases, attempt to create new entries from an empty entry. If no
+ * empty entries are available and ETHARP_TRY_HARD flag is set, recycle
+ * old entries. Heuristic choose the least important entry for recycling.
+ *
+ * @param ipaddr IP address to find in ARP cache, or to add if not found.
+ * @param flags
+ * - ETHARP_TRY_HARD: Try hard to create a entry by allowing recycling of
+ * active (stable or pending) entries.
+ *
+ * @return The ARP entry index that matched or is created, ERR_MEM if no
+ * entry is found or could be recycled.
*/
-static s8_t
-find_arp_entry(void)
+static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags)
{
- s8_t i, j;
- u8_t maxtime = 0;
+ s8_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE;
+ s8_t empty = ARP_TABLE_SIZE;
+ u8_t i = 0, age_pending = 0, age_stable = 0;
+#if ARP_QUEUEING
+ /* oldest entry with packets on queue */
+ s8_t old_queue = ARP_TABLE_SIZE;
+ /* its age */
+ u8_t age_queue = 0;
+#endif
+
+ /**
+ * a) do a search through the cache, remember candidates
+ * b) select candidate entry
+ * c) create new entry
+ */
+
+ /* a) in a single search sweep, do all of this
+ * 1) remember the first empty entry (if any)
+ * 2) remember the oldest stable entry (if any)
+ * 3) remember the oldest pending entry without queued packets (if any)
+ * 4) remember the oldest pending entry with queued packets (if any)
+ * 5) search for a matching IP entry, either pending or stable
+ * until 5 matches, or all entries are searched for.
+ */
- j = ARP_TABLE_SIZE;
- /* search ARP table for an unused or old entry */
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
- /* empty entry? */
- if (arp_table[i].state == ETHARP_STATE_EMPTY) {
- LWIP_DEBUGF(ETHARP_DEBUG, ("find_arp_entry: returning empty entry %u\n", i));
- return i;
- /* stable entry? */
- } else if (arp_table[i].state == ETHARP_STATE_STABLE) {
- /* remember entry with oldest stable entry in j */
- if (arp_table[i].ctime >= maxtime) maxtime = arp_table[j = i].ctime;
+ /* no empty entry found yet and now we do find one? */
+ if ((empty == ARP_TABLE_SIZE) && (arp_table[i].state == ETHARP_STATE_EMPTY)) {
+ LWIP_DEBUGF(ETHARP_DEBUG, ("find_entry: found empty entry %"U16_F"\n", (u16_t)i));
+ /* remember first empty entry */
+ empty = i;
+ }
+ /* pending entry? */
+ else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+ /* if given, does IP address match IP address in ARP entry? */
+ if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching pending entry %"U16_F"\n", (u16_t)i));
+ /* found exact IP address match, simply bail out */
+ return i;
+#if ARP_QUEUEING
+ /* pending with queued packets? */
+ } else if (arp_table[i].p != NULL) {
+ if (arp_table[i].ctime >= age_queue) {
+ old_queue = i;
+ age_queue = arp_table[i].ctime;
+ }
+#endif
+ /* pending without queued packets? */
+ } else {
+ if (arp_table[i].ctime >= age_pending) {
+ old_pending = i;
+ age_pending = arp_table[i].ctime;
+ }
+ }
+ }
+ /* stable entry? */
+ else if (arp_table[i].state == ETHARP_STATE_STABLE) {
+ /* if given, does IP address match IP address in ARP entry? */
+ if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching stable entry %"U16_F"\n", (u16_t)i));
+ /* found exact IP address match, simply bail out */
+ return i;
+ /* remember entry with oldest stable entry in oldest, its age in maxtime */
+ } else if (arp_table[i].ctime >= age_stable) {
+ old_stable = i;
+ age_stable = arp_table[i].ctime;
+ }
}
}
- /* no empty entry found? */
- if (i == ARP_TABLE_SIZE) {
- LWIP_DEBUGF(ETHARP_DEBUG, ("find_arp_entry: found oldest stable entry %u\n", j));
- /* fall-back to oldest stable */
- i = j;
+ /* { we have no match } => try to create a new entry */
+
+ /* no empty entry found and not allowed to recycle? */
+ if ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_TRY_HARD) == 0))
+ {
+ return (s8_t)ERR_MEM;
}
- /* no available entry found? */
- if (i == ARP_TABLE_SIZE) {
- LWIP_DEBUGF(ETHARP_DEBUG, ("find_arp_entry: no replacable entry could be found\n"));
- /* return failure */
- return ERR_MEM;
+
+ /* b) choose the least destructive entry to recycle:
+ * 1) empty entry
+ * 2) oldest stable entry
+ * 3) oldest pending entry without queued packets
+ * 4) oldest pending entry without queued packets
+ *
+ * { ETHARP_TRY_HARD is set at this point }
+ */
+
+ /* 1) empty entry available? */
+ if (empty < ARP_TABLE_SIZE) {
+ i = empty;
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting empty entry %"U16_F"\n", (u16_t)i));
}
-
- /* clean up the recycled stable entry */
- if (arp_table[i].state == ETHARP_STATE_STABLE) {
+ /* 2) found recyclable stable entry? */
+ else if (old_stable < ARP_TABLE_SIZE) {
+ /* recycle oldest stable*/
+ i = old_stable;
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest stable entry %"U16_F"\n", (u16_t)i));
#if ARP_QUEUEING
- /* and empty the packet queue */
- if (arp_table[i].p != NULL) {
- /* remove all queued packets */
- LWIP_DEBUGF(ETHARP_DEBUG, ("find_arp_entry: freeing entry %u, packet queue %p.\n", i, (void *)(arp_table[i].p)));
- pbuf_free(arp_table[i].p);
- arp_table[i].p = NULL;
- }
+ /* no queued packets should exist on stable entries */
+ LWIP_ASSERT("arp_table[i].p == NULL", arp_table[i].p == NULL);
#endif
- LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_arp_entry: recycling oldest stable entry %u\n", i));
- arp_table[i].state = ETHARP_STATE_EMPTY;
+ /* 3) found recyclable pending entry without queued packets? */
+ } else if (old_pending < ARP_TABLE_SIZE) {
+ /* recycle oldest pending */
+ i = old_pending;
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F" (without queue)\n", (u16_t)i));
+#if ARP_QUEUEING
+ /* 4) found recyclable pending entry with queued packets? */
+ } else if (old_queue < ARP_TABLE_SIZE) {
+ /* recycle oldest pending */
+ i = old_queue;
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F", freeing packet queue %p\n", (u16_t)i, (void *)(arp_table[i].p)));
+ pbuf_free(arp_table[i].p);
+ arp_table[i].p = NULL;
+#endif
+ /* no empty or recyclable entries found */
+ } else {
+ return (s8_t)ERR_MEM;
}
- LWIP_DEBUGF(ETHARP_DEBUG, ("find_arp_entry: returning %u\n", i));
- return i;
+
+ /* { empty or recyclable entry found } */
+ LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
+
+ /* recycle entry (no-op for an already empty entry) */
+ arp_table[i].state = ETHARP_STATE_EMPTY;
+
+ /* IP address given? */
+ if (ipaddr != NULL) {
+ /* set IP address */
+ ip_addr_set(&arp_table[i].ipaddr, ipaddr);
+ }
+ arp_table[i].ctime = 0;
+ return (err_t)i;
}
/**
* @param ipaddr IP address of the inserted ARP entry.
* @param ethaddr Ethernet address of the inserted ARP entry.
* @param flags Defines behaviour:
- * - ARP_INSERT_FLAG Allows ARP to insert this as a new item. If not specified,
+ * - ETHARP_TRY_HARD Allows ARP to insert this as a new item. If not specified,
* only existing ARP entries will be updated.
*
- * @return pbuf If non-NULL, a packet that was queued on a pending entry.
- * You should sent it and must call pbuf_free() afterwards.
+ * @return
+ * - ERR_OK Succesfully updated ARP cache.
+ * - ERR_MEM If we could not add a new ARP entry when ETHARP_TRY_HARD was set.
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
*
* @see pbuf_free()
*/
-static struct pbuf *
+static err_t
update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags)
{
s8_t i, k;
LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 3, ("update_arp_entry()\n"));
LWIP_ASSERT("netif->hwaddr_len != 0", netif->hwaddr_len != 0);
- LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: %u.%u.%u.%u - %02x:%02x:%02x:%02x:%02x:%02x\n",
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n",
ip4_addr1(ipaddr), ip4_addr2(ipaddr), ip4_addr3(ipaddr), ip4_addr4(ipaddr),
ethaddr->addr[0], ethaddr->addr[1], ethaddr->addr[2],
ethaddr->addr[3], ethaddr->addr[4], ethaddr->addr[5]));
- /* do not update for 0.0.0.0 addresses */
- if (ipaddr->addr == 0) {
- LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: will not add 0.0.0.0 to ARP cache\n"));
- return NULL;
+ /* non-unicast address? */
+ if (ip_addr_isany(ipaddr) ||
+ ip_addr_isbroadcast(ipaddr, netif) ||
+ ip_addr_ismulticast(ipaddr)) {
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: will not add non-unicast IP address to ARP cache\n"));
+ return ERR_ARG;
}
- /* Walk through the ARP mapping table and try to find an entry to
- update. If none is found, the IP -> MAC address mapping is
- inserted in the ARP table. */
- for (i = 0; i < ARP_TABLE_SIZE; ++i) {
- /* Check if the source IP address of the incoming packet matches
- the IP address in this ARP table entry. */
- if (arp_table[i].state != ETHARP_STATE_EMPTY &&
- ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
- /* pending entry? */
- if (arp_table[i].state == ETHARP_STATE_PENDING) {
- LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: pending entry %u goes stable\n", i));
- /* A pending entry was found, mark it stable */
- arp_table[i].state = ETHARP_STATE_STABLE;
- /* fall-through to next if */
- }
- /* stable entry? (possibly just marked to become stable) */
- if (arp_table[i].state == ETHARP_STATE_STABLE) {
-#if ARP_QUEUEING
- struct pbuf *p;
- struct eth_hdr *ethhdr;
-#endif
- LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: updating stable entry %u\n", i));
- /* An old entry found, update this and return. */
- for (k = 0; k < netif->hwaddr_len; ++k) {
- arp_table[i].ethaddr.addr[k] = ethaddr->addr[k];
- }
- /* reset time stamp */
- arp_table[i].ctime = 0;
+ /* find or create ARP entry */
+ i = find_entry(ipaddr, flags);
+ /* bail out if no entry could be found */
+ if (i < 0) return (err_t)i;
+
+ /* mark it stable */
+ arp_table[i].state = ETHARP_STATE_STABLE;
+
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: updating stable entry %"S16_F"\n", (s16_t)i));
+ /* update address */
+ for (k = 0; k < netif->hwaddr_len; ++k) {
+ arp_table[i].ethaddr.addr[k] = ethaddr->addr[k];
+ }
+ /* reset time stamp */
+ arp_table[i].ctime = 0;
/* this is where we will send out queued packets! */
#if ARP_QUEUEING
- while (arp_table[i].p != NULL) {
- /* get the first packet on the queue (if any) */
- p = arp_table[i].p;
- /* remember (and reference) remainder of queue */
- arp_table[i].p = pbuf_dequeue(p);
- /* fill-in Ethernet header */
- ethhdr = p->payload;
- for (k = 0; k < netif->hwaddr_len; ++k) {
- ethhdr->dest.addr[k] = ethaddr->addr[k];
- ethhdr->src.addr[k] = netif->hwaddr[k];
- }
- ethhdr->type = htons(ETHTYPE_IP);
- LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: sending queued IP packet %p.\n", (void *)p));
- /* send the queued IP packet */
- netif->linkoutput(netif, p);
- /* free the queued IP packet */
- pbuf_free(p);
- }
-#endif
- /* IP addresses should only occur once in the ARP entry, we are done */
- return NULL;
- }
- } /* if STABLE */
- } /* for all ARP entries */
-
- /* no matching ARP entry was found */
- LWIP_ASSERT("update_arp_entry: i == ARP_TABLE_SIZE", i == ARP_TABLE_SIZE);
-
- LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: IP address not yet in table\n"));
- /* allowed to insert a new entry? */
- if (flags & ARP_INSERT_FLAG)
- {
- LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: adding entry to table\n"));
- /* find an empty or old entry. */
- i = find_arp_entry();
- if (i == ERR_MEM) {
- LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: no available entry found\n"));
- return NULL;
- }
- /* set IP address */
- ip_addr_set(&arp_table[i].ipaddr, ipaddr);
- /* set Ethernet hardware address */
+ while (arp_table[i].p != NULL) {
+ /* get the first packet on the queue */
+ struct pbuf *p = arp_table[i].p;
+ /* Ethernet header */
+ struct eth_hdr *ethhdr = p->payload;
+ /* remember (and reference) remainder of queue */
+ /* note: this will also terminate the p pbuf chain */
+ arp_table[i].p = pbuf_dequeue(p);
+ /* fill-in Ethernet header */
for (k = 0; k < netif->hwaddr_len; ++k) {
- arp_table[i].ethaddr.addr[k] = ethaddr->addr[k];
+ ethhdr->dest.addr[k] = ethaddr->addr[k];
+ ethhdr->src.addr[k] = netif->hwaddr[k];
}
- /* reset time-stamp */
- arp_table[i].ctime = 0;
- /* mark as stable */
- arp_table[i].state = ETHARP_STATE_STABLE;
- /* no queued packet */
-#if ARP_QUEUEING
- arp_table[i].p = NULL;
-#endif
- }
- else
- {
- LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: no matching stable entry to update\n"));
+ ethhdr->type = htons(ETHTYPE_IP);
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: sending queued IP packet %p.\n", (void *)p));
+ /* send the queued IP packet */
+ netif->linkoutput(netif, p);
+ /* free the queued IP packet */
+ pbuf_free(p);
}
- return NULL;
+#endif
+ return ERR_OK;
}
/**
*
* @see pbuf_free()
*/
-struct pbuf *
+void
etharp_ip_input(struct netif *netif, struct pbuf *p)
{
struct ethip_hdr *hdr;
-
+ LWIP_ASSERT("netif != NULL", netif != NULL);
/* Only insert an entry if the source IP address of the
incoming IP packet comes from a host on the local network. */
hdr = p->payload;
- /* source is on local network? */
- if (!ip_addr_maskcmp(&(hdr->ip.src), &(netif->ip_addr), &(netif->netmask))) {
+ /* source is not on the local network? */
+ if (!ip_addr_netcmp(&(hdr->ip.src), &(netif->ip_addr), &(netif->netmask))) {
/* do nothing */
- return NULL;
+ return;
}
LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_ip_input: updating ETHARP table.\n"));
- /* update ARP table, ask to insert entry */
- update_arp_entry(netif, &(hdr->ip.src), &(hdr->eth.src), ARP_INSERT_FLAG);
- return NULL;
+ /* update ARP table */
+ /* @todo We could use ETHARP_TRY_HARD if we think we are going to talk
+ * back soon (for example, if the destination IP address is ours. */
+ update_arp_entry(netif, &(hdr->ip.src), &(hdr->eth.src), 0);
}
*
* @see pbuf_free()
*/
-struct pbuf *
+void
etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, struct pbuf *p)
{
struct etharp_hdr *hdr;
u8_t i;
u8_t for_us;
+ LWIP_ASSERT("netif != NULL", netif != NULL);
+
/* drop short ARP packets */
if (p->tot_len < sizeof(struct etharp_hdr)) {
- LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 1, ("etharp_arp_input: packet dropped, too short (%d/%d)\n", p->tot_len, sizeof(struct etharp_hdr)));
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 1, ("etharp_arp_input: packet dropped, too short (%"S16_F"/%"S16_F")\n", p->tot_len, sizeof(struct etharp_hdr)));
pbuf_free(p);
- return NULL;
+ return;
}
hdr = p->payload;
if (for_us) {
/* add IP address in ARP cache; assume requester wants to talk to us.
* can result in directly sending the queued packets for this host. */
- update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), ARP_INSERT_FLAG);
+ update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), ETHARP_TRY_HARD);
/* ARP message not directed to us? */
} else {
/* update the source IP address in the cache, if present */
}
break;
case ARP_REPLY:
- /* ARP reply. We insert or update the ARP table later. */
+ /* ARP reply. We already updated the ARP cache earlier. */
LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP reply\n"));
#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK)
- /* DHCP wants to know about ARP replies to our wanna-have-address */
- if (for_us) dhcp_arp_reply(netif, &sipaddr);
+ /* DHCP wants to know about ARP replies from any host with an
+ * IP address also offered to us by the DHCP server. We do not
+ * want to take a duplicate IP address on a single network.
+ * @todo How should we handle redundant (fail-over) interfaces?
+ * */
+ dhcp_arp_reply(netif, &sipaddr);
#endif
break;
default:
- LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP unknown opcode type %d\n", htons(hdr->opcode)));
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP unknown opcode type %"S16_F"\n", htons(hdr->opcode)));
break;
}
/* free ARP packet */
pbuf_free(p);
- p = NULL;
- /* nothing to send, we did it! */
- return NULL;
}
/**
* Resolve and fill-in Ethernet address header for outgoing packet.
*
- * If ARP has the Ethernet address in cache, the given packet is
- * returned, ready to be sent.
- *
- * If ARP does not have the Ethernet address in cache the packet is
- * queued (if enabled and space available) and a ARP request is sent.
- * This ARP request is returned as a pbuf, which should be sent by
- * the caller.
+ * For IP multicast and broadcast, corresponding Ethernet addresses
+ * are selected and the packet is transmitted on the link.
*
- * A returned non-NULL packet should be sent by the caller.
- *
- * If ARP failed to allocate resources, NULL is returned.
+ * For unicast addresses, the packet is submitted to etharp_query(). In
+ * case the IP address is outside the local network, the IP address of
+ * the gateway is used.
*
* @param netif The lwIP network interface which the IP packet will be sent on.
* @param ipaddr The IP address of the packet destination.
* @param pbuf The pbuf(s) containing the IP packet to be sent.
*
- * @return If non-NULL, a packet ready to be sent by caller.
- *
+ * @return
+ * - ERR_RTE No route to destination (no gateway to external networks),
+ * or the return type of either etharp_query() or netif->linkoutput().
*/
-struct pbuf *
+err_t
etharp_output(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q)
{
struct eth_addr *dest, *srcaddr, mcastaddr;
struct eth_hdr *ethhdr;
- s8_t i;
+ u8_t i;
- /* make room for Ethernet header */
+ /* make room for Ethernet header - should not fail */
if (pbuf_header(q, sizeof(struct eth_hdr)) != 0) {
- /* The pbuf_header() call shouldn't fail, and we'll just bail
- out if it does.. */
+ /* bail out */
LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_output: could not allocate room for header.\n"));
LINK_STATS_INC(link.lenerr);
- return NULL;
+ return ERR_BUF;
}
/* assume unresolved Ethernet address */
dest = NULL;
- /* Construct Ethernet header. Start with looking up deciding which
- MAC address to use as a destination address. Broadcasts and
- multicasts are special, all other addresses are looked up in the
- ARP table. */
+ /* Determine on destination hardware address. Broadcasts and multicasts
+ * are special, other IP addresses are looked up in the ARP table. */
- /* destination IP address is an IP broadcast address? */
- if (ip_addr_isany(ipaddr) || ip_addr_isbroadcast(ipaddr, netif)) {
+ /* broadcast destination IP address? */
+ if (ip_addr_isbroadcast(ipaddr, netif)) {
/* broadcast on Ethernet also */
dest = (struct eth_addr *)ðbroadcast;
- }
- /* destination IP address is an IP multicast address? */
- else if (ip_addr_ismulticast(ipaddr)) {
- /* Hash IP multicast address to MAC address. */
+ /* multicast destination IP address? */
+ } else if (ip_addr_ismulticast(ipaddr)) {
+ /* Hash IP multicast address to MAC address.*/
mcastaddr.addr[0] = 0x01;
mcastaddr.addr[1] = 0x00;
mcastaddr.addr[2] = 0x5e;
mcastaddr.addr[5] = ip4_addr4(ipaddr);
/* destination Ethernet address is multicast */
dest = &mcastaddr;
- }
- /* destination IP address is an IP unicast address */
- else {
- /* destination IP network address not on local network?
- * IP layer wants us to forward to the default gateway */
- if (!ip_addr_maskcmp(ipaddr, &(netif->ip_addr), &(netif->netmask))) {
+ /* unicast destination IP address? */
+ } else {
+ /* outside local network? */
+ if (!ip_addr_netcmp(ipaddr, &(netif->ip_addr), &(netif->netmask))) {
/* interface has default gateway? */
- if (netif->gw.addr != 0)
- {
- /* route to default gateway IP address */
+ if (netif->gw.addr != 0) {
+ /* send to hardware address of default gateway IP address */
ipaddr = &(netif->gw);
+ /* no default gateway available */
+ } else {
+ /* no route to destination error (default gateway missing) */
+ return ERR_RTE;
}
- /* no gateway available? */
- else
- {
- /* IP destination address outside local network, but no gateway available */
- /* { packet is discarded } */
- return NULL;
- }
- }
-
- /* Ethernet address for IP destination address is in ARP cache? */
- for (i = 0; i < ARP_TABLE_SIZE; ++i) {
- /* match found? */
- if (arp_table[i].state == ETHARP_STATE_STABLE &&
- ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
- dest = &arp_table[i].ethaddr;
- break;
- }
- }
- /* could not find the destination Ethernet address in ARP cache? */
- if (dest == NULL) {
- /* ARP query for the IP address, submit this IP packet for queueing */
- /* TODO: How do we handle netif->ipaddr == ipaddr? */
- etharp_query(netif, ipaddr, q);
- /* { packet was queued (ERR_OK), or discarded } */
- /* return nothing */
- return NULL;
- }
- /* destination Ethernet address resolved from ARP cache */
- else
- {
- /* fallthrough */
}
+ /* queue on destination Ethernet address belonging to ipaddr */
+ return etharp_query(netif, ipaddr, q);
}
- /* destination Ethernet address known */
- if (dest != NULL) {
- /* obtain source Ethernet address of the given interface */
- srcaddr = (struct eth_addr *)netif->hwaddr;
-
- /* A valid IP->MAC address mapping was found, fill in the
- * Ethernet header for the outgoing packet */
- ethhdr = q->payload;
-
- for(i = 0; i < netif->hwaddr_len; i++) {
- ethhdr->dest.addr[i] = dest->addr[i];
- ethhdr->src.addr[i] = srcaddr->addr[i];
- }
-
- ethhdr->type = htons(ETHTYPE_IP);
- /* return the outgoing packet */
- return q;
+ /* continuation for multicast/broadcast destinations */
+ /* obtain source Ethernet address of the given interface */
+ srcaddr = (struct eth_addr *)netif->hwaddr;
+ ethhdr = q->payload;
+ for (i = 0; i < netif->hwaddr_len; i++) {
+ ethhdr->dest.addr[i] = dest->addr[i];
+ ethhdr->src.addr[i] = srcaddr->addr[i];
}
- /* never reached; here for safety */
- return NULL;
+ ethhdr->type = htons(ETHTYPE_IP);
+ /* send packet directly on the link */
+ return netif->linkoutput(netif, q);
}
/**
- * Send an ARP request for the given IP address.
+ * Send an ARP request for the given IP address and/or queue a packet.
+ *
+ * If the IP address was not yet in the cache, a pending ARP cache entry
+ * is added and an ARP request is sent for the given address. The packet
+ * is queued on this entry.
*
- * Sends an ARP request for the given IP address, unless
- * a request for this address is already pending. Optionally
- * queues an outgoing packet on the resulting ARP entry.
+ * If the IP address was already pending in the cache, a new ARP request
+ * is sent for the given address. The packet is queued on this entry.
*
- * @param netif The lwIP network interface where ipaddr
+ * If the IP address was already stable in the cache, and a packet is
+ * given, it is directly sent and no ARP request is sent out.
+ *
+ * If the IP address was already stable in the cache, and no packet is
+ * given, an ARP request is sent out.
+ *
+ * @param netif The lwIP network interface on which ipaddr
* must be queried for.
* @param ipaddr The IP address to be resolved.
- * @param q If non-NULL, a pbuf that must be queued on the
- * ARP entry for the ipaddr IP address.
- *
- * @return NULL.
+ * @param q If non-NULL, a pbuf that must be delivered to the IP address.
+ * q is not freed by this function.
*
- * @note Might be used in the future by manual IP configuration
- * as well.
+ * @return
+ * - ERR_BUF Could not make room for Ethernet header.
+ * - ERR_MEM Hardware address unknown, and no more ARP entries available
+ * to query for address or queue the packet.
+ * - ERR_MEM Could not queue packet due to memory shortage.
+ * - ERR_RTE No route to destination (no gateway to external networks).
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
*
- * TODO: use the ctime field to see how long ago an ARP request was sent,
- * possibly retry.
*/
err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q)
{
- struct eth_addr *srcaddr;
- struct etharp_hdr *hdr;
- err_t result = ERR_OK;
- s8_t i;
- u8_t perform_arp_request = 1;
- /* prevent 'unused argument' warning if ARP_QUEUEING == 0 */
- (void)q;
- srcaddr = (struct eth_addr *)netif->hwaddr;
- /* bail out if this IP address is pending */
- for (i = 0; i < ARP_TABLE_SIZE; ++i) {
- if (arp_table[i].state != ETHARP_STATE_EMPTY &&
- ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
- if (arp_table[i].state == ETHARP_STATE_PENDING) {
- LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | DBG_STATE, ("etharp_query: requested IP already pending as entry %u\n", i));
- /* break out of for-loop, user may wish to queue a packet on a pending entry */
- /* TODO: we will issue a new ARP request, which should not occur too often */
- /* we might want to run a faster timer on ARP to limit this */
- break;
- }
- else if (arp_table[i].state == ETHARP_STATE_STABLE) {
- LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | DBG_STATE, ("etharp_query: requested IP already stable as entry %u\n", i));
- /* User wishes to queue a packet on a stable entry (or does she want to send
- * out the packet immediately, we will not know), so we force an ARP request.
- * Upon response we will send out the queued packet in etharp_update().
- *
- * Alternatively, we could accept the stable entry, and just send out the packet
- * immediately. I chose to implement the former approach.
- */
- perform_arp_request = (q?1:0);
- break;
- }
- }
+ struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr;
+ err_t result = ERR_MEM;
+ s8_t i; /* ARP entry index */
+ u8_t k; /* Ethernet address octet index */
+
+ /* non-unicast address? */
+ if (ip_addr_isbroadcast(ipaddr, netif) ||
+ ip_addr_ismulticast(ipaddr) ||
+ ip_addr_isany(ipaddr)) {
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n"));
+ return ERR_ARG;
}
- /* queried address not yet in ARP table? */
- if (i == ARP_TABLE_SIZE) {
- LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: IP address not found in ARP table\n"));
- /* find an available (unused or old) entry */
- i = find_arp_entry();
- /* bail out if no ARP entries are available */
- if (i == ERR_MEM) {
- LWIP_DEBUGF(ETHARP_DEBUG | 2, ("etharp_query: no more ARP entries available. Should seldom occur.\n"));
- return ERR_MEM;
- }
- /* i is available, create ARP entry */
+
+ /* find entry in ARP cache, ask to create entry if queueing packet */
+ i = find_entry(ipaddr, ETHARP_TRY_HARD);
+
+ /* could not find or create entry? */
+ if (i < 0)
+ {
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not create ARP entry\n"));
+ if (q) LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: packet dropped\n"));
+ return (err_t)i;
+ }
+
+ /* mark a fresh entry as pending (we just sent a request) */
+ if (arp_table[i].state == ETHARP_STATE_EMPTY) {
arp_table[i].state = ETHARP_STATE_PENDING;
- ip_addr_set(&arp_table[i].ipaddr, ipaddr);
}
- /* { i is now valid } */
-#if ARP_QUEUEING /* queue packet (even on a stable entry, see above) */
- /* copy any PBUF_REF referenced payloads into PBUF_RAM */
- q = pbuf_take(q);
- pbuf_queue(arp_table[i].p, q);
+
+ /* { i is either a STABLE or (new or existing) PENDING entry } */
+ LWIP_ASSERT("arp_table[i].state == PENDING or STABLE",
+ ((arp_table[i].state == ETHARP_STATE_PENDING) ||
+ (arp_table[i].state == ETHARP_STATE_STABLE)));
+
+ /* do we have a pending entry? or an implicit query request? */
+ if ((arp_table[i].state == ETHARP_STATE_PENDING) || (q == NULL)) {
+ /* try to resolve it; send out ARP request */
+ result = etharp_request(netif, ipaddr);
+ }
+
+ /* packet given? */
+ if (q != NULL) {
+ /* stable entry? */
+ if (arp_table[i].state == ETHARP_STATE_STABLE) {
+ /* we have a valid IP->Ethernet address mapping,
+ * fill in the Ethernet header for the outgoing packet */
+ struct eth_hdr *ethhdr = q->payload;
+ for(k = 0; k < netif->hwaddr_len; k++) {
+ ethhdr->dest.addr[k] = arp_table[i].ethaddr.addr[k];
+ ethhdr->src.addr[k] = srcaddr->addr[k];
+ }
+ ethhdr->type = htons(ETHTYPE_IP);
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: sending packet %p\n", (void *)q));
+ /* send the packet */
+ result = netif->linkoutput(netif, q);
+ /* pending entry? (either just created or already pending */
+ } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+#if ARP_QUEUEING /* queue the given q packet */
+ struct pbuf *p;
+ /* copy any PBUF_REF referenced payloads into PBUF_RAM */
+ /* (the caller of lwIP assumes the referenced payload can be
+ * freed after it returns from the lwIP call that brought us here) */
+ p = pbuf_take(q);
+ /* packet could be taken over? */
+ if (p != NULL) {
+ /* queue packet ... */
+ if (arp_table[i].p == NULL) {
+ /* ... in the empty queue */
+ pbuf_ref(p);
+ arp_table[i].p = p;
+#if 0 /* multi-packet-queueing disabled, see bug #11400 */
+ } else {
+ /* ... at tail of non-empty queue */
+ pbuf_queue(arp_table[i].p, p);
#endif
- /* ARP request? */
- if (perform_arp_request)
- {
- struct pbuf *p;
- /* allocate a pbuf for the outgoing ARP request packet */
- p = pbuf_alloc(PBUF_LINK, sizeof(struct etharp_hdr), PBUF_RAM);
- /* could allocate pbuf? */
- if (p != NULL) {
- u8_t j;
- LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: sending ARP request.\n"));
- hdr = p->payload;
- hdr->opcode = htons(ARP_REQUEST);
- for (j = 0; j < netif->hwaddr_len; ++j)
- {
- hdr->shwaddr.addr[j] = srcaddr->addr[j];
- /* the hardware address is what we ask for, in
- * a request it is a don't-care, we use 0's */
- hdr->dhwaddr.addr[j] = 0x00;
+ }
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"S16_F"\n", (void *)q, (s16_t)i));
+ result = ERR_OK;
+ } else {
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
+ /* { result == ERR_MEM } through initialization */
}
- hdr->dipaddr = *(struct ip_addr2 *)ipaddr;
- hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr;
+#else /* ARP_QUEUEING == 0 */
+ /* q && state == PENDING && ARP_QUEUEING == 0 => result = ERR_MEM */
+ /* { result == ERR_MEM } through initialization */
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: Ethernet destination address unknown, queueing disabled, packet %p dropped\n", (void *)q));
+#endif
+ }
+ }
+ return result;
+}
- hdr->hwtype = htons(HWTYPE_ETHERNET);
- ARPH_HWLEN_SET(hdr, netif->hwaddr_len);
+err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr)
+{
+ struct pbuf *p;
+ struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr;
+ err_t result = ERR_OK;
+ u8_t k; /* ARP entry index */
+
+ /* allocate a pbuf for the outgoing ARP request packet */
+ p = pbuf_alloc(PBUF_LINK, sizeof(struct etharp_hdr), PBUF_RAM);
+ /* could allocate a pbuf for an ARP request? */
+ if (p != NULL) {
+ struct etharp_hdr *hdr = p->payload;
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_request: sending ARP request.\n"));
+ hdr->opcode = htons(ARP_REQUEST);
+ for (k = 0; k < netif->hwaddr_len; k++)
+ {
+ hdr->shwaddr.addr[k] = srcaddr->addr[k];
+ /* the hardware address is what we ask for, in
+ * a request it is a don't-care value, we use zeroes */
+ hdr->dhwaddr.addr[k] = 0x00;
+ }
+ hdr->dipaddr = *(struct ip_addr2 *)ipaddr;
+ hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr;
- hdr->proto = htons(ETHTYPE_IP);
- ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr));
- for (j = 0; j < netif->hwaddr_len; ++j)
- {
- hdr->ethhdr.dest.addr[j] = 0xff;
- hdr->ethhdr.src.addr[j] = srcaddr->addr[j];
- }
- hdr->ethhdr.type = htons(ETHTYPE_ARP);
- /* send ARP query */
- result = netif->linkoutput(netif, p);
- /* free ARP query packet */
- pbuf_free(p);
- p = NULL;
- } else {
- result = ERR_MEM;
- LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_query: could not allocate pbuf for ARP request.\n"));
+ hdr->hwtype = htons(HWTYPE_ETHERNET);
+ ARPH_HWLEN_SET(hdr, netif->hwaddr_len);
+
+ hdr->proto = htons(ETHTYPE_IP);
+ ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr));
+ for (k = 0; k < netif->hwaddr_len; ++k)
+ {
+ /* broadcast to all network interfaces on the local network */
+ hdr->ethhdr.dest.addr[k] = 0xff;
+ hdr->ethhdr.src.addr[k] = srcaddr->addr[k];
}
+ hdr->ethhdr.type = htons(ETHTYPE_ARP);
+ /* send ARP query */
+ result = netif->linkoutput(netif, p);
+ /* free ARP query packet */
+ pbuf_free(p);
+ p = NULL;
+ /* could not allocate pbuf for ARP request */
+ } else {
+ result = ERR_MEM;
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_request: could not allocate pbuf for ARP request.\n"));
}
return result;
}
struct ip_addr *ipaddr)
{
struct pbuf *q, *r;
- char *ptr;
+ u8_t *ptr;
void **arg;
#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP)
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
+#include <string.h>
+
#include "ppp.h"
#if PPP_SUPPORT > 0
#include "auth.h"
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
+
+#include <string.h>
+
#include "ppp.h"
#if PPP_SUPPORT > 0
#include "fsm.h"
ho->neg_mru = 1; /* Remember he sent MRU */
ho->mru = cishort; /* And remember value */
#if TRACELCP > 0
- sprintf(&traceBuf[traceNdx], " MRU %d", cishort);
+ snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MRU %d", cishort);
traceNdx = strlen(traceBuf);
#endif
break;
ho->neg_asyncmap = 1;
ho->asyncmap = cilong;
#if TRACELCP > 0
- sprintf(&traceBuf[traceNdx], " ASYNCMAP=%lX", cilong);
+ snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ASYNCMAP=%lX", cilong);
traceNdx = strlen(traceBuf);
#endif
break;
}
ho->neg_upap = 1;
#if TRACELCP > 0
- sprintf(&traceBuf[traceNdx], " PAP (%X)", cishort);
+ snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PAP (%X)", cishort);
traceNdx = strlen(traceBuf);
#endif
break;
break;
}
#if TRACELCP > 0
- sprintf(&traceBuf[traceNdx], " CHAP %X,%d", cishort, cichar);
+ snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CHAP %X,%d", cishort, cichar);
traceNdx = strlen(traceBuf);
#endif
ho->chap_mdtype = cichar; /* save md type */
GETSHORT(cishort, p);
GETLONG(cilong, p);
#if TRACELCP > 0
- sprintf(&traceBuf[traceNdx], " QUALITY (%x %x)", cishort, (unsigned int) cilong);
+ snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " QUALITY (%x %x)", cishort, (unsigned int) cilong);
traceNdx = strlen(traceBuf);
#endif
}
GETLONG(cilong, p);
#if TRACELCP > 0
- sprintf(&traceBuf[traceNdx], " MAGICNUMBER (%lX)", cilong);
+ snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MAGICNUMBER (%lX)", cilong);
traceNdx = strlen(traceBuf);
#endif
case CI_PCOMPRESSION:
#if TRACELCP > 0
- sprintf(&traceBuf[traceNdx], " PCOMPRESSION");
+ snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PCOMPRESSION");
traceNdx = strlen(traceBuf);
#endif
if (!ao->neg_pcompression ||
case CI_ACCOMPRESSION:
#if TRACELCP > 0
- sprintf(&traceBuf[traceNdx], " ACCOMPRESSION");
+ snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ACCOMPRESSION");
traceNdx = strlen(traceBuf);
#endif
if (!ao->neg_accompression ||
case CI_MRRU:
#if TRACELCP > 0
- sprintf(&traceBuf[traceNdx], " CI_MRRU");
+ snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_MRRU");
traceNdx = strlen(traceBuf);
#endif
orc = CONFREJ;
case CI_SSNHF:
#if TRACELCP > 0
- sprintf(&traceBuf[traceNdx], " CI_SSNHF");
+ snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_SSNHF");
traceNdx = strlen(traceBuf);
#endif
orc = CONFREJ;
case CI_EPDISC:
#if TRACELCP > 0
- sprintf(&traceBuf[traceNdx], " CI_EPDISC");
+ snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_EPDISC");
traceNdx = strlen(traceBuf);
#endif
orc = CONFREJ;
default:
#if TRACELCP
- sprintf(&traceBuf[traceNdx], " unknown %d", citype);
+ snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " unknown %d", citype);
traceNdx = strlen(traceBuf);
#endif
orc = CONFREJ;
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
+
+#include <string.h>
+
#include "ppp.h"
#if PPP_SUPPORT > 0
#include "randm.h"
* for a 16 bit processor.
*/
+#include <string.h>
+
#include "ppp.h"
#include "vj.h"
#include "pppdebug.h"
-
#if VJ_SUPPORT > 0
#if LINK_STATS
*/
/*
- * This is an arch independent SLIP netif. The specific serial hooks must be provided
- * by another file.They are sio_open, sio_recv and sio_send
- */
+ * This is an arch independent SLIP netif. The specific serial hooks must be
+ * provided by another file. They are sio_open, sio_recv and sio_send
+ */
#include "netif/slipif.h"
#include "lwip/opt.h"
* Send a pbuf doing the necessary SLIP encapsulation
*
* Uses the serial layer's sio_send()
- */
+ */
err_t
slipif_output(struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr)
{
struct pbuf *q;
- int i;
+ u16_t i;
u8_t c;
/* Send pbuf out on the serial I/O device. */
sio_send(SLIP_END, netif->state);
- for(q = p; q != NULL; q = q->next) {
- for(i = 0; i < q->len; i++) {
+ for (q = p; q != NULL; q = q->next) {
+ for (i = 0; i < q->len; i++) {
c = ((u8_t *)q->payload)[i];
switch (c) {
case SLIP_END:
- sio_send(SLIP_ESC, netif->state);
- sio_send(SLIP_ESC_END, netif->state);
- break;
+ sio_send(SLIP_ESC, netif->state);
+ sio_send(SLIP_ESC_END, netif->state);
+ break;
case SLIP_ESC:
- sio_send(SLIP_ESC, netif->state);
- sio_send(SLIP_ESC_ESC, netif->state);
- break;
+ sio_send(SLIP_ESC, netif->state);
+ sio_send(SLIP_ESC_ESC, netif->state);
+ break;
default:
- sio_send(c, netif->state);
- break;
+ sio_send(c, netif->state);
+ break;
}
}
}
* Poll the serial layer by calling sio_recv()
*
* @return The IP packet when SLIP_END is received
- */
+ */
static struct pbuf *
-slipif_input( struct netif * netif )
+slipif_input(struct netif *netif)
{
u8_t c;
struct pbuf *p, *q;
- int recved;
- int i;
+ u16_t recved;
+ u16_t i;
q = p = NULL;
recved = i = 0;
switch (c) {
case SLIP_END:
if (recved > 0) {
- /* Received whole packet. */
- pbuf_realloc(q, recved);
-
- LINK_STATS_INC(link.recv);
-
- LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet\n"));
- return q;
+ /* Received whole packet. */
+ pbuf_realloc(q, recved);
+
+ LINK_STATS_INC(link.recv);
+
+ LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet\n"));
+ return q;
}
break;
c = sio_recv(netif->state);
switch (c) {
case SLIP_ESC_END:
- c = SLIP_END;
- break;
+ c = SLIP_END;
+ break;
case SLIP_ESC_ESC:
- c = SLIP_ESC;
- break;
+ c = SLIP_ESC;
+ break;
}
/* FALLTHROUGH */
-
+
default:
if (p == NULL) {
- LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n"));
- p = pbuf_alloc(PBUF_LINK, PBUF_POOL_BUFSIZE, PBUF_POOL);
-
- if (p == NULL) {
- LINK_STATS_INC(link.drop);
- LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n"));
- }
-
- if (q != NULL) {
- pbuf_cat(q, p);
- } else {
- q = p;
- }
+ LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n"));
+ p = pbuf_alloc(PBUF_LINK, PBUF_POOL_BUFSIZE, PBUF_POOL);
+
+ if (p == NULL) {
+ LINK_STATS_INC(link.drop);
+ LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n"));
+ }
+
+ if (q != NULL) {
+ pbuf_cat(q, p);
+ } else {
+ q = p;
+ }
}
if (p != NULL && recved < MAX_SIZE) {
- ((u8_t *)p->payload)[i] = c;
- recved++;
- i++;
- if (i >= p->len) {
- i = 0;
- p = NULL;
- }
+ ((u8_t *)p->payload)[i] = c;
+ recved++;
+ i++;
+ if (i >= p->len) {
+ i = 0;
+ if (p->next != NULL && p->next->len > 0)
+ p = p->next;
+ else
+ p = NULL;
+ }
}
break;
}
-
+
}
return NULL;
}
/**
- * The SLIP input thread
+ * The SLIP input thread.
*
* Feed the IP layer with incoming packets
- */
+ */
static void
slipif_loop(void *nf)
{
*
* Call the arch specific sio_open and remember
* the opened device in the state field of the netif.
- */
+ */
err_t
slipif_init(struct netif *netif)
{
-
- LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%x\n", (int)netif->num));
+
+ LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%"U16_F"\n", (u16_t)netif->num));
netif->name[0] = 's';
netif->name[1] = 'l';
netif->output = slipif_output;
- netif->mtu = 1500;
+ netif->mtu = 1500;
netif->flags = NETIF_FLAG_POINTTOPOINT;
netif->state = sio_open(netif->num);
if (!netif->state)
- return ERR_IF;
+ return ERR_IF;
sys_thread_new(slipif_loop, netif, SLIPIF_THREAD_PRIO);
return ERR_OK;
*/
#include "lwip/debug.h"
-
#include "lwip/stats.h"
-
#include "lwip/tcp.h"
+#include <cyg/infra/testcase.h>
+
+#ifdef CYGPKG_LWIP_TCP
struct http_state {
- char *file;
+ const char *file;
u32_t left;
u8_t retries;
};
}
}
- hs->file = &sdata;
+ hs->file = sdata;
hs->left = sizeof(sdata);
pbuf_free(p);
static cyg_handle_t thread_handle;
void
-cyg_user_start(void)
+httpd_main(void)
{
+ CYG_TEST_INIT();
// Create a main thread, so we can run the scheduler and have time 'pass'
cyg_thread_create(10, // Priority - just a number
tmain, // entry
&thread_data // Thread data structure
);
cyg_thread_resume(thread_handle); // Start it
+ cyg_scheduler_start();
+ CYG_TEST_FAIL_FINISH("Not reached");
+}
+
+externC void
+cyg_start( void )
+{
+ httpd_main();
+}
+
+#else // def CYGPKG_LWIP_TCP
+#define N_A_MSG "TCP support disabled"
+#endif // def CYGFUN_KERNEL_API_C
+
+#ifdef N_A_MSG
+externC void
+cyg_start( void )
+{
+ CYG_TEST_INIT();
+ CYG_TEST_NA(N_A_MSG);
}
+#endif // N_A_MSG
#include "nc_test_framework.h"
-#include <cyg/error/errno.h>
-#include <cyg/error/codes.h>
-#include <cyg/error/strerror.h>
#include <cyg/infra/diag.h>
#include <lwip/inet.h>
#include <lwip/arch.h>
-#define LWIP_TIMEVAL_PRIVATE
+#include <lwip/sys.h>
+#define LWIP_TIMEVAL_PRIVATE 1
#include <lwip/sockets.h>
+#include <cyg/infra/testcase.h>
#ifndef CYGPKG_LIBC_STDIO
+#include <cyg/error/errno.h>
#define perror(s) diag_printf(#s ": %s\n", strerror(errno))
+#else
+#include <stdio.h>
#endif
#define STACK_SIZE (CYGNUM_HAL_STACK_SIZE_TYPICAL + 0x1000)
#define MAX_LOAD_THREAD_LEVEL 20
#define MAIN_THREAD_PRIORITY CYGPKG_NET_THREAD_PRIORITY-2
#define DESIRED_BACKGROUND_LOAD 20
#define CYGHWR_NET_DRIVERS 1
+
+#if SO_REUSE
+#ifdef CYGPKG_LWIP_TCP
+#ifdef CYGPKG_LWIP_UDP
+
+
+#if 0
static char main_thread_stack[CYGHWR_NET_DRIVERS][STACK_SIZE];
static cyg_thread main_thread_data[CYGHWR_NET_DRIVERS];
static cyg_handle_t main_thread_handle[CYGHWR_NET_DRIVERS];
+#endif
+
+
static char idle_thread_stack[STACK_SIZE];
static cyg_thread idle_thread_data;
static cyg_handle_t idle_thread_handle;
seq_errors++;
}
} else {
- test_printf("Bad data packet - key: %x/%x, seq: %d\n",
+ test_printf("Bad data packet - key: %lx/%lx, seq: %d\n",
ntohl(tdp->key1), ntohl(tdp->key2),
ntohl(tdp->seq));
}
seq_errors++;
}
} else {
- test_printf("Bad data packet - key: %x/%x, seq: %d\n",
+ test_printf("Bad data packet - key: %lx/%lx, seq: %d\n",
ntohl(tdp->key1), ntohl(tdp->key2),
ntohl(tdp->seq));
}
}
void
-net_test(test_param_t param)
+net_test(void *arg)
{
+ test_param_t param = (test_param_t)arg;
// int i;
if (param == 0) {
test_printf("Start Network Characterization - SLAVE\n");
load_idle = idle_thread_count;
start_load(0); // Shut down background load
percent_load = 100 - ((load_idle * 100) / no_load_idle);
- diag_printf("High Load[%d] = %d => %d%%\n", load_thread_level,
+ diag_printf("High Load[%ld] = %d => %d%%\n", load_thread_level,
(int)idle_thread_count, percent_load);
if ( percent_load > desired_load )
break; // HIGH level is indeed higher
load_idle = idle_thread_count;
start_load(0); // Shut down background load
percent_load = 100 - ((load_idle * 100) / no_load_idle);
- diag_printf("Load[%d] = %d => %d%%\n", load_thread_level,
+ diag_printf("Load[%ld] = %d => %d%%\n", load_thread_level,
(int)idle_thread_count, percent_load);
if (((high-low) <= 1) || (abs(desired_load-percent_load) <= 2)) break;
if (percent_load < desired_load) {
load_idle = idle_thread_count;
start_load(0); // Shut down background load
percent_load = 100 - ((load_idle * 100) / no_load_idle);
- diag_printf("Final load[%d] = %d => %d%%\n", load_thread_level,
+ diag_printf("Final load[%ld] = %d => %d%%\n", load_thread_level,
(int)idle_thread_count, percent_load);
// no_load_idle_count_1_second = no_load_idle;
}
static cyg_handle_t thread_handle;
void
-cyg_user_start(void)
+nc_slave_main(void)
{
int i;
+
+ CYG_TEST_INIT();
// Create the idle thread environment
cyg_semaphore_init(&idle_thread_sem, 0);
cyg_thread_create(IDLE_THREAD_PRIORITY, // Priority
&thread_data // Thread data structure
);
cyg_thread_resume(thread_handle); // Start it
+ cyg_scheduler_start();
+ CYG_TEST_FAIL_FINISH("Not reached");
+}
+
+
+externC void
+cyg_start( void )
+{
+ nc_slave_main();
+}
+
+#else // def CYGPKG_LWIP_UDP
+#define N_A_MSG "UDP support disabled"
+#endif // def CYGPKG_LWIP_UDP
+#else // def CYGPKG_LWIP_TCP
+#define N_A_MSG "TCP support disabled"
+#endif // def CYGPKG_LWIP_TCP
+#else // SO_REUSE
+#define N_A_MSG "SO_REUSE currently unavailable"
+#endif // SO_REUSE
+
+#ifdef N_A_MSG
+externC void
+cyg_start( void )
+{
+ CYG_TEST_INIT();
+ CYG_TEST_NA(N_A_MSG);
}
+#endif // N_A_MSG
/* Simple test-case for the BSD socket API : echo on TCP port 7 */
-#include "lwip/sys.h"
+#include <lwip/sys.h>
+#undef LWIP_COMPAT_SOCKETS
#define LWIP_COMPAT_SOCKETS 1
-#include "lwip/sockets.h"
+#include <lwip/sockets.h>
+#include <lwip/inet.h>
+#include <cyg/infra/testcase.h>
+
+#ifdef CYGPKG_LWIP_TCP
char buf[400];
static void
static cyg_handle_t thread_handle;
void
-cyg_user_start(void)
+socket_main(void)
{
+ CYG_TEST_INIT();
// Create a main thread, so we can run the scheduler and have time 'pass'
cyg_thread_create(10, // Priority - just a number
tmain, // entry
&thread_data // Thread data structure
);
cyg_thread_resume(thread_handle); // Start it
+ cyg_scheduler_start();
+ CYG_TEST_FAIL_FINISH("Not reached");
+}
+
+externC void
+cyg_start( void )
+{
+ socket_main();
+}
+
+#else // def CYGPKG_LWIP_TCP
+#define N_A_MSG "TCP support disabled"
+#endif // def CYGFUN_KERNEL_API_C
+
+#ifdef N_A_MSG
+externC void
+cyg_start( void )
+{
+ CYG_TEST_INIT();
+ CYG_TEST_NA(N_A_MSG);
}
+#endif // N_A_MSG
#include "lwip/sys.h"
#include "lwip/api.h"
+#include <cyg/infra/testcase.h>
+
+#ifdef CYGPKG_LWIP_TCP
static void
tcpecho_thread(void *arg)
static cyg_handle_t thread_handle;
void
-cyg_user_start(void)
+tcpecho_main(void)
{
+ CYG_TEST_INIT();
+
// Create a main thread, so we can run the scheduler and have time 'pass'
cyg_thread_create(10, // Priority - just a number
tmain, // entry
&thread_handle, // Handle
&thread_data // Thread data structure
);
- cyg_thread_resume(thread_handle); // Start it
+
+ cyg_thread_resume(thread_handle); // Start it
+ cyg_scheduler_start();
+ CYG_TEST_FAIL_FINISH("Not reached");
+}
+
+externC void
+cyg_start( void )
+{
+ tcpecho_main();
}
+#else // def CYGPKG_LWIP_TCP
+#define N_A_MSG "TCP support disabled"
+#endif // def CYGFUN_KERNEL_API_C
+
+#ifdef N_A_MSG
+externC void
+cyg_start( void )
+{
+ CYG_TEST_INIT();
+ CYG_TEST_NA(N_A_MSG);
+}
+#endif // N_A_MSG
#include "lwip/api.h"
#include "lwip/sys.h"
+#include <cyg/infra/testcase.h>
+
+#ifdef CYGPKG_LWIP_UDP
/*-----------------------------------------------------------------------------------*/
char buffer[100];
static cyg_handle_t thread_handle;
void
-cyg_user_start(void)
+udpecho_main(void)
{
+ CYG_TEST_INIT();
// Create a main thread, so we can run the scheduler and have time 'pass'
cyg_thread_create(10, // Priority - just a number
tmain, // entry
&thread_data // Thread data structure
);
cyg_thread_resume(thread_handle); // Start it
+
+ cyg_scheduler_start();
+
+ CYG_TEST_FAIL_FINISH("Not reached");
+}
+
+externC void
+cyg_start( void )
+{
+ udpecho_main();
}
+#else // def CYGPKG_LWIP_UDP
+#define N_A_MSG "UDP support disabled"
+#endif // def CYGFUN_KERNEL_API_C
+
+#ifdef N_A_MSG
+externC void
+cyg_start( void )
+{
+ CYG_TEST_INIT();
+ CYG_TEST_NA(N_A_MSG);
+}
+#endif // N_A_MSG
+
+
+2006-05-19 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * tests/dns1.c (dns_test_thread): Use CYG_NELEM from infra.
+
2005-07-29 Andrew Lunn <andrew.lunn@ascom.ch>
* src/dns.c Various casts and type fixes to stop gcc 4 warnings.
static cyg_thread thread_data;
static cyg_handle_t thread_handle;
-#define NELEM(x) (sizeof(x) / sizeof(x[0]))
-
struct test_info_s {
char * dns_server_v4;
char * dns_server_v6;
CYG_TEST_INFO("Starting dns1 test");
- for (i = 0; i < NELEM(test_info); i++) {
+ for (i = 0; i < CYG_NELEM(test_info); i++) {
dns_test(&test_info[i]);
}
+2008-04-28 Daniel Néri <daniel.neri@sigicom.com>
+
+ * src/ipcp.c (ipcp_init): Negotiate both primary and secondary DNS
+ resolver addresses when CYGOPT_PPP_NS_NEGOTIATE is enabled.
+
+2006-07-18 John Paul King <john.king@transdatainc.com>
+
+ * src/sys-ecos.c (cyg_ppp_up): Bring semaphore init earlier to avoid
+ race condition if pppd thread is higher priority than the current
+ thread.
+
+2005-11-23 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * cdl/ppp.cdl: Require CYGPKG_POSIX_CLOCKS not *_TIMERS
+
+2005-10-23 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * cdl/ppp.cdl: Require CYGPKG_POSIX_TIMERS
+ * src/sys-ecos.c (gettimeofday): Removed, now get it from POSIX
+
2005-07-30 Andrew Lunn <andrew.lunn@ascom.ch>
* src/ppp_io.c (cyg_ppp_pppread): caddrt_t to stop compiler warnings.
requires CYGOPT_IO_SERIAL_SUPPORT_NONBLOCKING
requires CYGPKG_NET
requires CYGPKG_IO_SERIAL_FLOW_CONTROL
+ requires CYGPKG_POSIX_CLOCKS
description "PPP support for eCos. This package contains the PPP
daemon functionality, BSD kernel device drivers for
#define establish_ppp cyg_ppp_establish_ppp
#define get_host_seed cyg_ppp_get_host_seed
#define get_idle_time cyg_ppp_get_idle_time
-#define gettimeofday cyg_ppp_gettimeofday
#define mrand48 cyg_ppp_mrand48
#define netmask cyg_ppp_netmask
#define output cyg_ppp_output
wo->default_route = ppp_tty.options->default_route;
#ifdef CYGOPT_PPP_NS_NEGOTIATE
- wo->neg_dns1 = 1;
+ wo->neg_dns1 = 1;
+ wo->neg_dns2 = 1;
#endif
/* max slots and slot-id compression are currently hardwired in */
// Wait for the PPPD thread to get going and start the PPP
// initialization phase.
- while(phase == PHASE_DEAD )
+ while(phase == PHASE_DEAD)
cyg_thread_delay(100);
// Now loop until the link goes back down.
ppp_tty.options = options;
+ cyg_semaphore_init( &ppp_tty.tx_sem, 0 );
+
// Start the PPPD thread
cyg_thread_create(CYGNUM_PPP_PPPD_THREAD_PRIORITY,
cyg_pppd_main,
cyg_thread_resume(ppp_tty.pppd_thread);
// Start the TX thread
- cyg_semaphore_init( &ppp_tty.tx_sem, 0 );
-
cyg_thread_create(CYGNUM_PPP_PPPD_THREAD_PRIORITY+1,
cyg_ppp_tx_thread,
(CYG_ADDRWORD)&ppp_tty,
// Wait for the PPPD thread to get going and start the PPP
// initialization phase.
- while(phase == PHASE_DEAD )
+ while(phase == PHASE_DEAD)
cyg_thread_delay(100);
return (cyg_ppp_handle_t)&ppp_tty;
//=====================================================================
-int gettimeofday(struct timeval *tv, struct timezone *tz)
-{
- cyg_tick_count_t time = cyg_current_time();
-
- tv->tv_sec = time/CYGNUM_HAL_RTC_DENOMINATOR;
- tv->tv_usec = (time%CYGNUM_HAL_RTC_DENOMINATOR)*10000;
-
-// db_printf("%s: %d %d\n", __PRETTY_FUNCTION__, tv->tv_sec, tv->tv_usec);
-
- return 0;
-}
-
-//=====================================================================
-
char *crypt (const char *key, const char *salt)
{
static char res[13];
+2008-07-02 Bart Veer <bartv@ecoscentric.com>
+
+ * include/snmpusm.h: add missing definition needed for the CERT
+ fix below.
+
+2008-06-11 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * src/scapi.c: Fix CVE-2008-0960 (CERT/CC VU#481564).
+
+2006-07-27 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * include/config.h (HAVE_GETTIMEOFDAY): Add missing hash (reported
+ by Richard Jennings).
+
+2005-10-23 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * include/config.h: POSIX provides gettimeofday()
+ * cdl/snmplib.cdl: We require gettimeofday from POSIX
+
2003-03-24 Jonathan Larmour <jifl@eCosCentric.com>
* src/keytools.c (decode_keychange): Avoid undefined behaviour.
requires { 0 != CYGINT_ISO_ERRNO }
requires { 0 != CYGINT_ISO_ERRNO_CODES }
requires CYGPKG_NET
+ requires CYGPKG_POSIX_TIMERS
description "SNMP protocol support library based on the UCD-SNMP project."
compile \
//#define HAVE_GETPID 1
/* Define if you have the gettimeofday function. */
-//#define HAVE_GETTIMEOFDAY 1
+#define HAVE_GETTIMEOFDAY 1
/* Define if you have the if_freenameindex function. */
//#define HAVE_IF_FREENAMEINDEX 1
#define USM_MAX_KEYEDHASH_LENGTH 128 /* In BITS. */
#define USM_TIME_WINDOW 150
+#define USM_MD5_AND_SHA_AUTH_LEN 12 /* bytes */
/*
}
+ if (maclen != USM_MD5_AND_SHA_AUTH_LEN) {
+ QUITFUN(SNMPERR_GENERR, sc_check_keyed_hash_quit);
+ }
+
/*
* Generate a full hash of the message, then compare
* the result with the given MAC which may shorter than
+2006-11-08 Andre Mas <andrejohn.mas@gmail.com>
+
+ * src/sntp.c: Removed optional KeyIdentifer and MessageDigest
+ fields, which weren't being used, and caused certain servers
+ not to respond when these fields were included with null values.
+
2005-07-30 Andrew Lunn <andrew.lunn@ascom.ch>
* src/sntp.c: Compiler warning fixes.
NTP_TIMESTAMP ReceiveTimestamp;
NTP_TIMESTAMP TransmitTimestamp;
- cyg_uint32 KeyIdentifier; /* Optional */
- cyg_uint8 MessageDigest[16]; /* Optional */
+// cyg_uint32 KeyIdentifier; /* Optional */
+// cyg_uint8 MessageDigest[16]; /* Optional */
} NTP_PACKET;
#define NTP_PACKET_MINLEN 48 /* Packet size - optional fields */
+2005-10-23 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/sys/kern/kern_subr.c (uiomove): Remove lvalue cast to
+ keep GCC4.x happy.
+
2003-12-10 Gary Thomas <gary@mlbassoc.com>
* include/netinet/in.h: Prototype for inet_ntoa_r()
break;
#endif
}
- (char *)(iov->iov_base) += cnt;
+ iov->iov_base = (char *)iov->iov_base + cnt;
iov->iov_len -= cnt;
uio->uio_resid -= cnt;
uio->uio_offset += cnt;
+2007-08-28 Gary Thomas <gary@mlbassoc.com>
+
+ * src/flash.c (do_flash_init): Memory allocation was slightly
+ incorrect - 'workspace_end' should always be used to find
+ the end of available memory.
+
+2007-08-08 Peter Korsgaard <peter.korsgaard@barco.com>
+
+ * include/net/http.h:
+ * src/net/http_client.c: Add HTTP_FORBIDDEN error code for 403
+ Forbidden response.
+
+2007-06-03 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/net/net_io.c: (do_ip_addr): Option to set domain name.
+ * doc/redboot_cmds.sgml: Document new option.
+
+2007-06-03 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
+
+ * cdl/redboot.cdl: CDL to control the use of DNS domain name.
+ * src/net/bootp.c: Get the domain name from the reply.
+ * src/net/dns.c: Domain name from CDL, fconfig and DHCP.
+
+2007-06-02 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
+
+ * src/flash.c: (fis_list): fis list will now list an image
+ which happens to start at address 0.
+
+2007-04-11 Gary Thomas <gary@mlbassoc.com>
+2007-04-11 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * src/fs/fileio.c: Temporary kludge to treat flash correctly if either
+ flash v1 or flash v2 used with this file.
+ (do_mount): silence warning. Include accidentally omitted printf arg.
+ (do_list): silence warning.
+
+2007-01-22 Peter Korsgaard <peter.korsgaard@barco.com>
+
+ * src/load.c (do_load): Reset entry address before load so
+ go/exec commands will fail after an incomplete upload.
+
+2006-11-28 David Fernandez <dfernandez@cct.co.uk>
+
+ * cdl/redboot.cdl: Modified to change the option
+ CYGDAT_REDBOOT_DEFAULT_NETWORK_DEVICE to make it independent of
+ CYGSEM_REDBOOT_FLASH_CONFIG, changes in net_io.c will allow to
+ specify a default interface in terms of the name and its position
+ in the table of interfaces for the driver.
+
+ * src/net/net_io.c: Modified to allow
+ CYGDAT_REDBOOT_DEFAULT_NETWORK_DEVICE to be used even with no flash
+ available.
+ Bug regarding CYGSEM_REDBOOT_NETWORK_INIT_ONE_DEVICE fixed, so that
+ when working with several network interfaces, and the default one
+ fails to initialize, only the first successfully initialized one is
+ used.
+
+2006-11-19 Andrew Lunn <lunn@laptop.lunn.ch>
+
+ * src/load.c: Only call valid_address() if
+ CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS is enabled.
+
+2006-09-06 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * cdl/redboot.cdl: Fix description of CYGSEM_REDBOOT_DISK_IDE.
+ Error pointed out by Wang Cui
+
+2006-08-28 Sergei Gavrikov <w3sg@SoftHome.net>
+
+ * src/net/tftp_client.c (tftp_error_ack): Fix compiler warnings.
+
+2006-07-21 David Ho <davidkwho@gmail.com>
+
+ * src/flash.c (fis_start_update_directory): Fix build error when
+ redundant FIS selected and locking is not enabled/supported.
+
+2006-05-24 Gary Thomas <gary@mlbassoc.com>
+
+ * src/net/net_io.c (do_ip_addr): Bail out if no networking.
+
+2006-05-23 Gary Thomas <gary@mlbassoc.com>
+
+ * src/flash.c (fis_update_directory): Fix problems building on systems
+ with no FLASH locking.
+
+2006-04-19 Alexander Neundorf <alexander.neundorf@jenoptik.com>
+ * src/flash.c, src/main.c, src/fconfig.c:
+ * include/fis.h, include/redboot.h:
+ * cdl/redboot.cdl:
+ add support for redundant FIS tables, configurable via
+ CYGOPT_REDBOOT_REDUNDANT_FIS
+
+2006-04-07 Grant Edwards <grante@visi.com>
+
+ * src/net/net_io.c (net_io_getc_nonblock):
+ Handle TELNET_WILL (reject same as TELNET_DO)
+
+2006-04-03 Lars Povlsen <lpovlsen@vitesse.com>
+
+ * src/flash.c (fis_update_directory): Fixed flash region size when
+ CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG is enabled.
+
+2006-03-27 Gary Thomas <gary@mlbassoc.com>
+
+ * src/net/tcp.c (__tcp_write_block): Fix calculation of actual
+ total number of bytes sent (from Wolfgang Koebler)
+
+2006-02-25 Oliver Munz <munz@speag.ch>
+ Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/xyzModem.c (xyzModem_stream_open): Fix compiler warnings.
+ * src/flash_load.c (NEW): Implements access to flash
+ * src/load.c: Allow load command to load directly into flash
+ * cdl/redboot.c (CYGBLD_REDBOOT_LOAD_INTO_FLASH) Control new
+ feature, disabled by default.
+ * cdl/main.c (cyg_start): Assert check to see if we have
+ overflowed the workspace.
+ * doc/redboot_cmds.sgml: Document new flag.
+
+2006-02-24 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * src/fs/fileio.c (do_list): Use getcwd for current directory,
+ rather than "." which may not be implemented in the FS.
+
+2006-02-17 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/flash.c (fis_lock & fis_unlock): Allow compilation without
+ FIS being enabled.
+ * src/flash.c (fis_update_directory): When reading/writing flash
+ use the full size of the fis directory, not just one block.
+
+2005-11-23 Peter Korsgaard <peter.korsgaard@barco.com>
+
+ * src/gunzip.c (do_gunzip): Fixed diag_printf format string warnings.
+
+2005-10-17 Gary Thomas <gary@mlbassoc.com>
+
+ * src/iomem.c (do_iopeek): Correct number of options.
+
+2005-09-13 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * src/parse.c (redboot_exec): Conditionalise use of
+ __mem_fault_handler to only be when stubs are included.
+ (error_handler): Ditto for this function.
+
+ * src/main.c (cyg_start): Conditionalise use of
+ __mem_fault_handler to only be when stubs are included.
+ (do_go): Ditto.
+ (error_handler): Ditto for this function.
+
2005-09-09 Andrew Dyer <adyer@righthandtech.com>
* src/load.c: add calls to redboot_getc_terminate before exiting
* src/net/arp.c: use correct sizeof(rt->enet_addr) in
__arp_lookup()
+2005-01-26 Nick Garnett <nickg@ecoscentric.com>
+
+ * src/fs/fileio.c (do_mkdir, do_deldir, do_del, do_write): Added
+ some extra argument checking to these functions.
+
2005-01-22 Andrew Lunn <andrew.lunn@ascom.ch>
* src/main.c (cyg_start): Fix compiler warning with
HAL_THREAD_INIT_CONTEXT and the worspace end address.
* src/fs/disk.c (find_dos_partitions): Removed unused variable.
+2005-01-19 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * src/fs/fileio.c (do_mount): Only support -f with "legacy" flash
+ block devices.
+ Clear mount table on failure.
+ (do_move): Silence rename undefined warning.
+ (do_write): Silence warnings.
+ (do_info): Support longer device names.
+
+ * src/decompress.c (ZLIB_COMPRESSION_OVERHEAD):
+ Increase substantially if jffs2 is present.
+
2005-01-05 David Vrabel <dvrabel@arcom.com>
* src/fs/fileio.c (do_ls): Remove useless "getcwd" message.
* src/net/bootp.c (__bootp_find_local_ip): Only print the
"waiting for BOOTP" message when after first retry.
+2004-12-17 Nick Garnett <nickg@ecoscentric.com>
+
+ * src/fs/fileio.c: Fixed some bugs in handling of mounts. The
+ strings used in the mount table must be copied, otherwise the
+ mount table is corrupted by later commands. Also toughened up some
+ error testing.
+
+2004-12-16 Nick Garnett <nickg@ecoscentric.com>
+
+ * doc/redboot_cmds.sgml: Added file mode documentation to load
+ command.
+
2004-12-01 Andrea Michelotti <amichelotti@atmel.com>
* main.c :
* mcmp.c : Changes required for use with GCC v4 - cast as lvalue
is no longer supported.
+2004-11-26 Nick Garnett <nickg@ecoscentric.com>
+
+ * doc/redboot_cmds.sgml: Added documentation of filesystem access
+ commands.
+
+ * src/fs/fileio.c (do_write): Added O_TRUNC to the open call to
+ ensure that the file is resized to fit the new data.
+
+2004-11-24 Nick Garnett <nickg@ecoscentric.com>
+
+ * src/fs/fileio.c: Significantly reorganized to present an
+ interface similar to the fis commands. Added a variety of command
+ to manipulate files and directories in a filesystem.
+
+ * src/parse.c: Added redboot_exec() to provide an internal
+ interface for executing RedBoot commands. Added err_printf() which
+ allows an error message to be printed before longjumping out to an
+ enclosing call to redboot_exec(). Where redboot_exec() is not
+ involved, it just behaves like diag_printf().
+
+ * src/main.c: Removed unnecessary delay during startup. Changed
+ diag_printf() in do_go() into err_printf().
+
+ * src/load.c: Changed some calls to diag_printf() to err_printf().
+
+ * src/net/net_io.c: Changed init priority to RedBoot_INIT_NET.
+
+ * include/redboot.h: Added some extra initialization
+ priorities. Added prototypes for redboot_exec() and err_printf().
+
2004-11-09 Ian Campbell <icampbell@arcom.com>
* cdl/redboot.cdl, doc/redboot_cmds.sgml, src/iomem.c: Add support
compile -library=libextras.a xyzModem.c
}
+ cdl_option CYGBLD_REDBOOT_LOAD_INTO_FLASH {
+ display "Allow the load-command write into Flash."
+ default_value 0
+ active_if CYGPKG_REDBOOT_FLASH
+ requires CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS
+ compile flash_load.c
+ description "
+ Write images direct to Flash via the load command.
+ We assume anything which is invalid RAM is flash, hence
+ the requires statement"
+ }
+
cdl_option CYGBLD_BUILD_REDBOOT_WITH_WINCE_SUPPORT {
display "Include MS Windows CE support"
doc ref/wince.html
compile -library=libextras.a mxc_usb.c
}
+ cdl_option CYGBLD_BUILD_REDBOOT_WITH_IMXOTG {
+ display "Include support for i.MX USB OTG downloads"
+ no_define
+ default_value 0
+ compile -library=libextras.a imx_usb.c
+ }
+
cdl_option CYGBLD_BUILD_REDBOOT_WITH_CKSUM {
display "Include POSIX checksum command"
doc ref/cksum-command.html
This option sets the IP of the default DNS. The IP can be
changed at runtime as well."
}
-
+
cdl_option CYGNUM_REDBOOT_NETWORKING_DNS_TIMEOUT {
display "Timeout in DNS lookup"
flavor data
address via the DNS. Default is 10 seconds."
}
+ cdl_component CYGPKG_REDBOOT_NETWORKING_DNS_WITH_DOMAIN {
+ display "Support the use of a domain name"
+ flavor bool
+ default_value 0
+ description "
+ This option controls if Redboot supports domain
+ names when performing DNS lookups"
+
+ cdl_option CYGPKG_REDBOOT_NETWORKING_DNS_DEFAULT_DOMAIN {
+ display "Default DNS domain"
+ flavor booldata
+ default_value 0
+ description "
+ This option sets the default DNS domain name.
+ This value will be overwritten by the value in
+ flash or a domain returned by DHCP"
+ }
+
+ cdl_option CYGPKG_REDBOOT_NETWORKING_DNS_FCONFIG_DOMAIN {
+ display "Get DNS domain from Flash"
+ flavor bool
+ active_if CYGSEM_REDBOOT_FLASH_CONFIG
+ default_value 0
+ description "
+ This option enables getting the domain name
+ from the flash configuration. This can later be
+ overwritten by a value learnt from DHCP"
+ }
+
+ cdl_option CYGPKG_REDBOOT_NETWORKING_DNS_DHCP_DOMAIN {
+ display "Use DNS domain from DHCP"
+ flavor bool
+ default_value 0
+ description "
+ This option enables the use of the domain name
+ returned by DHCP."
+ }
+
+ cdl_option CYGNUM_REDBOOT_NETWORK_DNS_DOMAIN_BUFSIZE {
+ display "BOOTP/DHCP DNS domain buffer size"
+ flavor data
+ default_value 32
+ description "
+ This options sets the size of the static
+ buffer used by BOOTP/DHCP to store the DNS
+ domain name. The domain name will not be
+ set if the buffer is too small to hold it."
+ }
+ }
}
cdl_option CYGDAT_REDBOOT_DEFAULT_NETWORK_DEVICE {
display "Default network device driver"
flavor data
- active_if { CYGSEM_REDBOOT_FLASH_CONFIG && CYGHWR_NET_DRIVERS > 1 }
+ active_if { CYGHWR_NET_DRIVERS > 1 }
default_value { "\"\"" }
description "
This is the name of the default network device to use."
}
cdl_option CYGSEM_REDBOOT_VARIABLE_BAUD_RATE {
- display "Let RedBoot adjust the baud off the serial console."
+ display "Let RedBoot adjust the baud rate of the serial console."
flavor bool
default_value 1
active_if CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
means the last but one block."
}
+ cdl_component CYGOPT_REDBOOT_REDUNDANT_FIS {
+ display "Redundant Flash Image System Directory Support"
+ default_value 0
+ requires { 0 == CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG }
+ description "
+ This option enables the use of a redundant FIS
+ directory within RedBoot. If enabled a flash block
+ will be reserved for a second copy of the fis
+ directory. Doing this allow for power failure safe
+ updates of the directory by the application."
+
+ cdl_option CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK {
+ display "Flash block containing the backup Directory"
+ flavor data
+ default_value (-3)
+ requires { CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK !=
+ CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK }
+ description "
+ Which block of flash should hold the redundant
+ directory information. Positive numbers are
+ absolute block numbers. Negative block numbers
+ count backwards from the last block. eg 2 means
+ block 2, -2 means the last but one block."
+ }
+ }
+
cdl_option CYGOPT_REDBOOT_FIS_RESERVED_BASE {
display "Pseudo-file to describe reserved area"
active_if { 0 != CYGNUM_REDBOOT_FLASH_RESERVED_BASE }
flavor bool
default_value 1
description "
- When this option is enabled, RedBoot will support IDE disks."
+ When this option is enabled, RedBoot will support EXT2
+ filesystems."
compile -library=libextras.a fs/e2fs.c
}
ip_address [-l <local_ip_address>[/<mask_length>]] [-h <server_address>]
Load a file
load [-r] [-v] [-d] [-h <host>] [-m {TFTP | HTTP | {x|y}MODEM -c <channel_number>}]
- [-b <base_address>] <file_name>
+ [-f <flash_address>] [-b <base_address>] <file_name>
Compare two blocks of memory
mcmp -s <location> -d <location> -l <length> [-1|-2|-4]
Fill a block of memory with a pattern
Display the current network settings.
<screen>
RedBoot> <userinput>ip_address</userinput>
-IP: 192.168.1.31, Default server: 192.168.1.101, DNS server IP: 0.0.0.0
+IP: 192.168.1.31, Default server: 192.168.1.101, DNS server IP: 0.0.0.0, DNS domain name:
</screen>
</para>
<para>
Change the DNS server address.
<screen>
RedBoot> <userinput>ip_address -d 192.168.1.101</userinput>
-IP: 192.168.1.31, Default server: 192.168.1.101, DNS server IP: 192.168.1.101
+IP: 192.168.1.31, Default server: 192.168.1.101, DNS server IP: 192.168.1.101, DNS domain name:
+</screen>
+</para>
+<para>
+Change the DNS domain name.
+<screen>
+RedBoot> <userinput>ip_address -D example.com</userinput>
+IP: 192.168.1.31, Default server: 192.168.1.101, DNS server IP: 192.168.1.101, DNS domain name: example.com
</screen>
</para>
<para>
Change the default server address.
<screen>
RedBoot> <userinput>ip_address -h 192.168.1.104</userinput>
-IP: 192.168.1.31, Default server: 192.168.1.104, DNS server IP: 192.168.1.101
+IP: 192.168.1.31, Default server: 192.168.1.104, DNS server IP: 192.168.1.101, DNS domain name:
</screen>
</para>
<para>
Set the IP address to something new, with a 255.255.255.0 netmask
<screen>
RedBoot> <userinput>ip_address -l 192.168.1.32/24</userinput>
-IP: 192.168.1.32, Default server: 192.168.1.104, DNS server IP: 192.168.1.101
+IP: 192.168.1.32, Default server: 192.168.1.104, DNS server IP: 192.168.1.101, DNS domain name:
</screen>
</para>
</refsect1>
<arg choice="req"><group>
<arg>xmodem</arg>
<arg>ymodem</arg>
- </group></arg>
- <arg>tftp</arg>
- <arg>disk</arg>
+ <arg>tftp</arg>
+ <arg>disk</arg>
+ <arg>file</arg></group>
+ </arg>
</group>
</arg>
<arg>-h <replaceable> server_IP_address</replaceable></arg>
+ <arg>-f <replaceable> location</replaceable></arg>
<arg>-b <replaceable> location</replaceable></arg>
<arg>-c <replaceable> channel</replaceable></arg>
<arg><replaceable>file_name</replaceable></arg>
<row>
<entry>-r</entry>
<entry>Boolean</entry>
- <entry>Raw (or binary) data</entry>
+ <entry>Raw (or binary) data. -b or -f must be used</entry>
<entry><emphasis>formatted (S-records, ELF image, etc)</emphasis></entry>
</row>
<row>
<entry>Transfer data from a local disk.</entry>
<entry><acronym>TFTP</acronym></entry>
</row>
+ <row>
+ <entry>-m file</entry>
+ <entry></entry>
+ <entry>Transfer data from a local filesystem such as
+ JFFS2 or FAT.</entry>
+ <entry><acronym>TFTP</acronym></entry>
+ </row>
<row>
<entry>-h <replaceable>server_IP_address</replaceable></entry>
<entry>Numeric IP or DNS name</entry>
<entry>-b <replaceable>location</replaceable></entry>
<entry>Number</entry>
<entry>Address in memory to load the data. Formatted data streams will have
+an implied load address which this option may override.</entry>
+ <entry><emphasis>Depends on data format</emphasis></entry>
+ </row>
+ <row>
+ <entry>-f <replaceable>location</replaceable></entry>
+ <entry>Number</entry>
+ <entry>Address in flash to load the data. Formatted data streams will have
an implied load address which this option may override.</entry>
<entry><emphasis>Depends on data format</emphasis></entry>
</row>
<screen>
RedBoot> <userinput>load -mode disk hda1:hello.elf</userinput>
Entry point: 0x00020000, address range: 0x00020000-0x0002fd70
+</screen>
+ </para>
+ <para>
+Load an ELF file from /jffs2/applications which should be a directory
+in a JFFS2 filesystem:
+<screen>
+RedBoot> <userinput>load -mode file /jffs2/applications/hello.elf</userinput>
+Entry point: 0x00020000, address range: 0x00020000-0x0002fd70
</screen>
</para>
</refsect1>
<refsynopsisdiv>
<cmdsynopsis>
<command>fis list</command>
- <arg><replaceable>-f</replaceable></arg>
+ <arg><replaceable>-c</replaceable></arg>
+ <arg><replaceable>-d</replaceable></arg>
</cmdsynopsis>
</refsynopsisdiv>
<refsect1>
<row>
<entry>-l</entry>
<entry>Number</entry>
- <entry>Length of flash area to occopy. If specified, and
+ <entry>Length of flash area to occupy. If specified, and
the named image already exists, the length must match
the value in the FIS directory.</entry>
<entry>Length of area reserved in FIS directory if the
<refsect1>
<title>Description</title>
<para>This command is used to write-protect (lock) a portion of flash memory,
-to prevent accidental overwriting of images. In order to make make any modifications
+to prevent accidental overwriting of images. In order to make any modifications
to the flash, a matching <command>fis unlock</command> command must be
issued. This command is optional and will only be provided on hardware
which can support write-protection of the flash space.</para>
</para>
</refsect1>
</refentry>
+</sect1>
+
+<sect1 id="filesystem-commands">
+<title>Filesystem Interface</title>
+
+<para>
+<indexterm><primary>commands</primary><secondary>filesystem access
+</secondary></indexterm><indexterm><primary>filesystem commands</primary>
+</indexterm><indexterm><primary>commands</primary><secondary>fs</secondary>
+</indexterm><indexterm><primary>fs commands</primary></indexterm>
+
+If the platform has access to secondary storage, then RedBoot may be
+able to access a filesystem stored on this device. RedBoot can access
+FAT filesystems stored on IDE disks or CompactFlash devices and can
+use JFFS2 filesystems stored in FLASH memory. The
+<command>fs</command> command is used to manipulate files on
+filesystems. Applications may be loaded into memory using the
+<emphasis>file</emphasis> mode of the <command>load</command> command.
+</para>
+
+<!-- ******** fs info ************************************************ -->
+
+<refentry id="fs-info-command">
+ <refnamediv>
+ <refname>fs info</refname>
+ <refpurpose>Print filesystem information</refpurpose>
+ </refnamediv>
+ <refsynopsisdiv>
+ <cmdsynopsis>
+ <command>fs info</command>
+ </cmdsynopsis>
+ </refsynopsisdiv>
+ <refsect1>
+ <title>Arguments</title>
+ <para>
+ The command takes no arguments.
+ </para>
+ </refsect1>
+ <refsect1>
+ <title>Description</title>
+<para>This command prints information about the filesystems that are
+available. Three lists are produced. The first is a list of the
+filsystem implementations available in RedBoot; names from this list
+may be used in the <parameter>-t</parameter> option to the <command>fs
+mount</command> command. The second list describes the block devices
+that are available for mounting a filesystem; names from this list may
+be used in the <parameter>-d</parameter> option to the <command>fs
+mount</command> command. The last list describes the filesystems that
+are already mounted.
+</para>
+</refsect1>
+
+ <refsect1>
+ <title>Examples</title>
+ <para>
+<screen>
+RedBoot> <userinput>fs info</userinput>
+Filesystems available:
+ramfs
+jffs2
+
+Devices available:
+/dev/flash1
+
+Mounted filesystems:
+ Device Filesystem Mounted on
+ <undefined> ramfs /
+ /dev/flash1 jffs2 /flash
+RedBoot></screen>
+ </para>
+ </refsect1>
+</refentry>
+
+<!-- ******** fs mount ************************************************ -->
+
+<refentry id="fs-mount-command">
+ <refnamediv>
+ <refname>fs mount</refname>
+ <refpurpose>Mount a filesystem</refpurpose>
+ </refnamediv>
+ <refsynopsisdiv>
+ <cmdsynopsis>
+ <command>fs mount</command>
+ <arg choice="opt">-d <replaceable>device</replaceable></arg>
+ <arg choice="req">-t <replaceable>fstype</replaceable></arg>
+ <arg choice="req">mountpoint</arg>
+ </cmdsynopsis>
+ </refsynopsisdiv>
+ <refsect1>
+ <title>Arguments</title>
+ <informaltable frame="all">
+ <tgroup cols="4" colsep="1" rowsep="1" align="left">
+ <colspec colname="c1">
+ <colspec colname="c2">
+ <colspec colname="c3">
+ <colspec colname="c4">
+ <thead>
+ <row>
+ <entry>Name</entry>
+ <entry>Type</entry>
+ <entry>Description</entry>
+ <entry>Default</entry>
+ </row>
+ </thead>
+ <tbody>
+ <row>
+ <entry><replaceable>device</replaceable></entry>
+ <entry>Number</entry>
+ <entry>Device containing filsystem to mount.</entry>
+ <entry>undefined</entry>
+ </row>
+ <row>
+ <entry><replaceable>fstype</replaceable></entry>
+ <entry>Number</entry>
+ <entry>Filesystem type.</entry>
+ <entry></entry>
+ </row>
+ <row>
+ <entry><replaceable>mountpoint</replaceable></entry>
+ <entry>String</entry>
+ <entry>Pathname for filesystem root.</entry>
+ <entry>/</entry>
+ </row>
+ </tbody>
+ </tgroup>
+ </informaltable>
+ </refsect1>
+ <refsect1>
+ <title>Description</title>
+<para>This command is used make a filesystem available for access with
+the filesystem access commands. Three things need to be defined to do
+this. First, the name of the device on which the filesystem is stored
+needs to be given to the <parameter>-d</parameter> option. Secondly,
+the type of filesystem it is needs to be given to the
+<parameter>-t</parameter> option. Finally, the pathname by which the
+new filesystem will be accessed needs to be supplied. Following a
+successful mount, the root of the filesystem will be accessible
+at the mountpoint.
+</para>
+</refsect1>
+
+ <refsect1>
+ <title>Examples</title>
+<para>Mount a JFF2 partititon:
+<screen>
+RedBoot> <userinput>fs info</userinput>
+Filesystems available:
+ramfs
+jffs2
+
+Devices available:
+/dev/flash1
+
+Mounted filesystems:
+ Device Filesystem Mounted on
+ <undefined> ramfs /
+RedBoot> <userinput>fs mount -d /dev/flash1 -t jffs2 /flash</userinput>
+RedBoot> <userinput>fs info</userinput>
+Filesystems available:
+ramfs
+jffs2
+
+Devices available:
+/dev/flash1
+
+Mounted filesystems:
+ Device Filesystem Mounted on
+ <undefined> ramfs /
+ /dev/flash1 jffs2 /flash
+RedBoot>
+</screen>
+ </para>
+ </refsect1>
+</refentry>
+
+<!-- ******** fs umount ************************************************ -->
+
+<refentry id="fs-umount-command">
+ <refnamediv>
+ <refname>fs umount</refname>
+ <refpurpose>Unmount filesystem</refpurpose>
+ </refnamediv>
+ <refsynopsisdiv>
+ <cmdsynopsis>
+ <command>fs umount</command>
+ <arg choice="req"><replaceable>mountpoint</replaceable></arg>
+ </cmdsynopsis>
+ </refsynopsisdiv>
+ <refsect1>
+ <title>Arguments</title>
+ <informaltable frame="all">
+ <tgroup cols="4" colsep="1" rowsep="1" align="left">
+ <colspec colname="c1">
+ <colspec colname="c2">
+ <colspec colname="c3">
+ <colspec colname="c4">
+ <thead>
+ <row>
+ <entry>Name</entry>
+ <entry>Type</entry>
+ <entry>Description</entry>
+ <entry>Default</entry>
+ </row>
+ </thead>
+ <tbody>
+ <row>
+ <entry><replaceable>mountpoint</replaceable></entry>
+ <entry>String</entry>
+ <entry>Mountpoint of filesystem to unmount.</entry>
+ <entry></entry>
+ </row>
+ </tbody>
+ </tgroup>
+ </informaltable>
+ </refsect1>
+ <refsect1>
+ <title>Description</title>
+<para>This command removes a filesystem from being accessible using
+the filesystem commands. The single argument needs to be the
+mountpoint that was used when mounting the filesystem. This command
+will fail if the current directory is currently within the filesystem
+to be unmounted.
+</para>
+</refsect1>
+
+ <refsect1>
+ <title>Examples</title>
+<para>Unmount a JFF2 partititon:
+<screen>
+RedBoot> <userinput>fs info</userinput>
+Filesystems available:
+ramfs
+jffs2
+
+Devices available:
+/dev/flash1
+
+Mounted filesystems:
+ Device Filesystem Mounted on
+ <undefined> ramfs /
+ /dev/flash1 jffs2 /flash
+RedBoot> <userinput>fs umount /flash</userinput>
+RedBoot> <userinput>fs info</userinput>
+Filesystems available:
+ramfs
+jffs2
+
+Devices available:
+/dev/flash1
+
+Mounted filesystems:
+ Device Filesystem Mounted on
+ <undefined> ramfs /
+RedBoot>
+</screen>
+ </para>
+ </refsect1>
+</refentry>
+
+<!-- ******** fs cd ************************************************ -->
+
+<refentry id="fs-cd-command">
+ <refnamediv>
+ <refname>fs cd</refname>
+ <refpurpose>Change filesystem directory</refpurpose>
+ </refnamediv>
+ <refsynopsisdiv>
+ <cmdsynopsis>
+ <command>fs cd</command>
+ <arg choice="opt"><replaceable>directory</replaceable></arg>
+ </cmdsynopsis>
+ </refsynopsisdiv>
+ <refsect1>
+ <title>Arguments</title>
+ <informaltable frame="all">
+ <tgroup cols="4" colsep="1" rowsep="1" align="left">
+ <colspec colname="c1">
+ <colspec colname="c2">
+ <colspec colname="c3">
+ <colspec colname="c4">
+ <thead>
+ <row>
+ <entry>Name</entry>
+ <entry>Type</entry>
+ <entry>Description</entry>
+ <entry>Default</entry>
+ </row>
+ </thead>
+ <tbody>
+ <row>
+ <entry><replaceable>directory</replaceable></entry>
+ <entry>String</entry>
+ <entry>Pathname to directory to change to.</entry>
+ <entry>Root directory</entry>
+ </row>
+ </tbody>
+ </tgroup>
+ </informaltable>
+ </refsect1>
+ <refsect1>
+ <title>Description</title>
+<para>This command changes the current filesystem
+directory. Subsequent filesystem commands will be executed in the new
+directory. If no argument is given, then the current directory is set
+back to the root of the filesystem name space.
+</para>
+</refsect1>
+
+ <refsect1>
+ <title>Examples</title>
+ <para>Change current directory:
+<screen>
+RedBoot> <userinput>fs list</userinput>
+212416 d--------- 3 size 128 .
+212416 d--------- 3 size 128 ..
+211392 d--------- 2 size 96 tests
+210368 ---------- 1 size 4096 image
+RedBoot> <userinput>fs cd tests</userinput>
+RedBoot> <userinput>fs list</userinput>
+211392 d--------- 2 size 96 .
+212416 d--------- 3 size 128 ..
+205760 ---------- 1 size 16384 test1
+RedBoot>
+</screen>
+ </para>
+ </refsect1>
+</refentry>
+
+<!-- ******** fs mkdir ************************************************ -->
+
+<refentry id="fs-mkdir-command">
+ <refnamediv>
+ <refname>fs mkdir</refname>
+ <refpurpose>Create filesystem directory</refpurpose>
+ </refnamediv>
+ <refsynopsisdiv>
+ <cmdsynopsis>
+ <command>fs mkdir</command>
+ <arg choice="req"><replaceable>directory</replaceable></arg>
+ </cmdsynopsis>
+ </refsynopsisdiv>
+ <refsect1>
+ <title>Arguments</title>
+ <informaltable frame="all">
+ <tgroup cols="4" colsep="1" rowsep="1" align="left">
+ <colspec colname="c1">
+ <colspec colname="c2">
+ <colspec colname="c3">
+ <colspec colname="c4">
+ <thead>
+ <row>
+ <entry>Name</entry>
+ <entry>Type</entry>
+ <entry>Description</entry>
+ <entry>Default</entry>
+ </row>
+ </thead>
+ <tbody>
+ <row>
+ <entry><replaceable>directory</replaceable></entry>
+ <entry>String</entry>
+ <entry>Pathname to directory to delete.</entry>
+ <entry></entry>
+ </row>
+ </tbody>
+ </tgroup>
+ </informaltable>
+ </refsect1>
+ <refsect1>
+ <title>Description</title>
+<para>This command creates (makes) a directory in the filesystem.
+</para>
+</refsect1>
+
+ <refsect1>
+ <title>Examples</title>
+ <para>Create directory:
+<screen>
+RedBoot> <userinput>fs list</userinput>
+212416 d--------- 2 size 128 .
+212416 d--------- 2 size 128 ..
+210368 ---------- 1 size 4096 image
+RedBoot> <userinput>fs mkdir tests</userinput>
+RedBoot> <userinput>fs list</userinput>
+212416 d--------- 3 size 128 .
+212416 d--------- 3 size 128 ..
+211392 d--------- 2 size 64 tests
+210368 ---------- 1 size 4096 image
+RedBoot>
+</screen>
+ </para>
+ </refsect1>
+</refentry>
+
+<!-- ******** fs deldir ************************************************ -->
+
+<refentry id="fs-deldir-command">
+ <refnamediv>
+ <refname>fs deldir</refname>
+ <refpurpose>Delete filesystem directory</refpurpose>
+ </refnamediv>
+ <refsynopsisdiv>
+ <cmdsynopsis>
+ <command>fs deldir</command>
+ <arg choice="req"><replaceable>directory</replaceable></arg>
+ </cmdsynopsis>
+ </refsynopsisdiv>
+ <refsect1>
+ <title>Arguments</title>
+ <informaltable frame="all">
+ <tgroup cols="4" colsep="1" rowsep="1" align="left">
+ <colspec colname="c1">
+ <colspec colname="c2">
+ <colspec colname="c3">
+ <colspec colname="c4">
+ <thead>
+ <row>
+ <entry>Name</entry>
+ <entry>Type</entry>
+ <entry>Description</entry>
+ <entry>Default</entry>
+ </row>
+ </thead>
+ <tbody>
+ <row>
+ <entry><replaceable>directory</replaceable></entry>
+ <entry>String</entry>
+ <entry>Pathname to directory to delete.</entry>
+ <entry></entry>
+ </row>
+ </tbody>
+ </tgroup>
+ </informaltable>
+ </refsect1>
+ <refsect1>
+ <title>Description</title>
+<para>This command deletes a directory from the filesystem. If the
+directory contains files or other directories then this command will
+fail.
+</para>
+</refsect1>
+
+ <refsect1>
+ <title>Examples</title>
+ <para>Delete directory:
+<screen>
+RedBoot> <userinput>fs list</userinput>
+212416 d--------- 3 size 128 .
+212416 d--------- 3 size 128 ..
+211392 d--------- 2 size 96 tests
+210368 ---------- 1 size 4096 image
+RedBoot> <userinput>fs deldir tests</userinput>
+RedBoot> <userinput>fs list</userinput>
+212416 d--------- 2 size 128 .
+212416 d--------- 2 size 128 ..
+210368 ---------- 1 size 4096 image
+RedBoot>
+</screen>
+ </para>
+ </refsect1>
+</refentry>
+
+<!-- ******** fs del ************************************************ -->
+
+<refentry id="fs-del-command">
+ <refnamediv>
+ <refname>fs del</refname>
+ <refpurpose>Delete file</refpurpose>
+ </refnamediv>
+ <refsynopsisdiv>
+ <cmdsynopsis>
+ <command>fs del</command>
+ <arg choice="req"><replaceable>file</replaceable></arg>
+ </cmdsynopsis>
+ </refsynopsisdiv>
+ <refsect1>
+ <title>Arguments</title>
+ <informaltable frame="all">
+ <tgroup cols="4" colsep="1" rowsep="1" align="left">
+ <colspec colname="c1">
+ <colspec colname="c2">
+ <colspec colname="c3">
+ <colspec colname="c4">
+ <thead>
+ <row>
+ <entry>Name</entry>
+ <entry>Type</entry>
+ <entry>Description</entry>
+ <entry>Default</entry>
+ </row>
+ </thead>
+ <tbody>
+ <row>
+ <entry><replaceable>file</replaceable></entry>
+ <entry>String</entry>
+ <entry>Pathname of file to delete.</entry>
+ <entry></entry>
+ </row>
+ </tbody>
+ </tgroup>
+ </informaltable>
+ </refsect1>
+ <refsect1>
+ <title>Description</title>
+<para>This command deletes a file from the filesystem.
+</para>
+</refsect1>
+
+ <refsect1>
+ <title>Examples</title>
+ <para>Change current directory:
+<screen>
+RedBoot> <userinput>fs list tests</userinput>
+211392 d--------- 2 size 96 .
+212416 d--------- 3 size 128 ..
+205760 ---------- 1 size 16384 test1
+RedBoot> <userinput>fs del tests/test1</userinput>
+RedBoot> <userinput>fs list tests</userinput>
+211392 d--------- 2 size 96 .
+212416 d--------- 3 size 128 ..
+RedBoot>
+</screen>
+ </para>
+ </refsect1>
+</refentry>
+
+<!-- ******** fs move ************************************************ -->
+
+<refentry id="fs-move-command">
+ <refnamediv>
+ <refname>fs move</refname>
+ <refpurpose>Move file</refpurpose>
+ </refnamediv>
+ <refsynopsisdiv>
+ <cmdsynopsis>
+ <command>fs move</command>
+ <arg choice="req"><replaceable>source</replaceable></arg>
+ <arg choice="req"><replaceable>dest</replaceable></arg>
+ </cmdsynopsis>
+ </refsynopsisdiv>
+ <refsect1>
+ <title>Arguments</title>
+ <informaltable frame="all">
+ <tgroup cols="4" colsep="1" rowsep="1" align="left">
+ <colspec colname="c1">
+ <colspec colname="c2">
+ <colspec colname="c3">
+ <colspec colname="c4">
+ <thead>
+ <row>
+ <entry>Name</entry>
+ <entry>Type</entry>
+ <entry>Description</entry>
+ <entry>Default</entry>
+ </row>
+ </thead>
+ <tbody>
+ <row>
+ <entry><replaceable>source</replaceable></entry>
+ <entry>String</entry>
+ <entry>Pathname of file to move.</entry>
+ <entry></entry>
+ </row>
+ <row>
+ <entry><replaceable>dest</replaceable></entry>
+ <entry>String</entry>
+ <entry>Pathname to new file location.</entry>
+ <entry></entry>
+ </row>
+ </tbody>
+ </tgroup>
+ </informaltable>
+ </refsect1>
+ <refsect1>
+ <title>Description</title>
+<para>This command moves a file within a filesystem. This command will
+fail if the destination file already exists, or is in a different
+filesystem.
+</para>
+</refsect1>
+
+ <refsect1>
+ <title>Examples</title>
+ <para>Rename a file:
+<screen>
+RedBoot> <userinput>fs list tests</userinput>
+211392 d--------- 2 size 96 .
+212416 d--------- 3 size 128 ..
+205760 ---------- 1 size 12288 test1
+RedBoot> <userinput>fs move tests/test1 tests/test2</userinput>
+RedBoot> <userinput>fs list tests</userinput>
+211392 d--------- 2 size 128 .
+212416 d--------- 3 size 128 ..
+205760 ---------- 1 size 12288 test2
+RedBoot>
+</screen>
+ </para>
+ </refsect1>
+</refentry>
+
+<!-- ******** fs list ************************************************ -->
+
+<refentry id="fs-list-command">
+ <refnamediv>
+ <refname>fs list</refname>
+ <refpurpose>List filesystem directory</refpurpose>
+ </refnamediv>
+ <refsynopsisdiv>
+ <cmdsynopsis>
+ <command>fs list</command>
+ <arg choice="opt"><replaceable>directory</replaceable></arg>
+ </cmdsynopsis>
+ </refsynopsisdiv>
+ <refsect1>
+ <title>Arguments</title>
+ <informaltable frame="all">
+ <tgroup cols="4" colsep="1" rowsep="1" align="left">
+ <colspec colname="c1">
+ <colspec colname="c2">
+ <colspec colname="c3">
+ <colspec colname="c4">
+ <thead>
+ <row>
+ <entry>Name</entry>
+ <entry>Type</entry>
+ <entry>Description</entry>
+ <entry>Default</entry>
+ </row>
+ </thead>
+ <tbody>
+ <row>
+ <entry><replaceable>directory</replaceable></entry>
+ <entry>String</entry>
+ <entry>Pathname to directory to list.</entry>
+ <entry>Current directory</entry>
+ </row>
+ </tbody>
+ </tgroup>
+ </informaltable>
+ </refsect1>
+ <refsect1>
+ <title>Description</title>
+<para>This command prints a list of the contents of the named
+directory. Each line of the listing starts with the file's inode
+number, which is its address in the filesystem. Following is a set of
+UNIX-like access flags, the first character of this will be a
+”d“ if this entry is a directory. The third item indicates
+the number of links to the file. Following this is the size of the
+file in bytes and the last item is its name.
+</para>
+</refsect1>
+
+ <refsect1>
+ <title>Examples</title>
+ <para>List the current directory:
+<screen>
+RedBoot> <userinput>fs list</userinput>
+212416 d--------- 3 size 128 .
+212416 d--------- 3 size 128 ..
+211392 ---------- 1 size 4096 image
+206784 d--------- 2 size 96 tests
+RedBoot>
+</screen>
+ </para>
+<para>
+List a subdirectory:
+<screen>
+RedBoot> fs list tests
+206784 d--------- 2 size 96 .
+212416 d--------- 3 size 128 ..
+205760 ---------- 1 size 16384 test1
+RedBoot>
+</screen>
+</para>
+ </refsect1>
+</refentry>
+
+<!-- ******** fs write ************************************************ -->
+
+<refentry id="fs-write-command">
+ <refnamediv>
+ <refname>fs write</refname>
+ <refpurpose>Write to filesystem</refpurpose>
+ </refnamediv>
+ <refsynopsisdiv>
+ <cmdsynopsis>
+ <command>fs write</command>
+ <arg choice="opt">-b <replaceable>mem_address</replaceable></arg>
+ <arg choice="opt">-l <replaceable>length</replaceable></arg>
+ <arg choice="req">name</arg>
+ </cmdsynopsis>
+ </refsynopsisdiv>
+ <refsect1>
+ <title>Arguments</title>
+ <informaltable frame="all">
+ <tgroup cols="4" colsep="1" rowsep="1" align="left">
+ <colspec colname="c1">
+ <colspec colname="c2">
+ <colspec colname="c3">
+ <colspec colname="c4">
+ <thead>
+ <row>
+ <entry>Name</entry>
+ <entry>Type</entry>
+ <entry>Description</entry>
+ <entry>Default</entry>
+ </row>
+ </thead>
+ <tbody>
+ <row>
+ <entry><replaceable>mem_address</replaceable></entry>
+ <entry>Number</entry>
+ <entry>Address of data to be written to flash.</entry>
+ <entry>Address of last loaded file. If not set by a load
+ operation it must be specified.</entry>
+ </row>
+ <row>
+ <entry><replaceable>length</replaceable></entry>
+ <entry>Number</entry>
+ <entry>Length of data to be written.</entry>
+ <entry>Length of last loaded file.</entry>
+ </row>
+ <row>
+ <entry><replaceable>name</replaceable></entry>
+ <entry>String</entry>
+ <entry>Name of file to create.</entry>
+ <entry></entry>
+ </row>
+ </tbody>
+ </tgroup>
+ </informaltable>
+ </refsect1>
+ <refsect1>
+ <title>Description</title>
+<para>This command is used to write data from memory to a file. If the
+file does not exist it will be created. If it does exist, then it will
+be overwritten with the new contents.</para>
+</refsect1>
+
+ <refsect1>
+ <title>Examples</title>
+<para>Write an area of data to a file
+<screen>
+RedBoot> <userinput>fs write -b 0x0606f000 -l 0x1000 image</userinput>
+RedBoot> <userinput>fs list</userinput>
+212416 d--------- 3 size 128 .
+212416 d--------- 3 size 128 ..
+211392 ---------- 1 size 4096 image
+206784 d--------- 2 size 96 tests
+RedBoot>
+</screen>
+ </para>
+ </refsect1>
+</refentry>
+
+
</sect1>
+
+
<sect1 id="Persistent-State-Flash">
<title>Persistent State Flash-based Configuration and Control</title>
<para><indexterm><primary>persistent state flash-based configuration and control
Local IP address: 192.168.1.29
Default server IP address: 192.168.1.101
DNS server IP address: 192.168.1.1
+DNS domain name: example.com
GDB connection port: 9000
Network debug at boot time: false
</screen></para>
#ifdef CYGOPT_REDBOOT_FIS
#include <cyg/infra/cyg_type.h>
+//the version can be tested via the VV calls to check for compatibility
+#define CYG_REDBOOT_FIS_VERSION (1)
+
+// the following defines will be used if RedBoot is configured
+// with support for redundant FIS tables, which enable failsafe updating
+#ifdef CYGOPT_REDBOOT_REDUNDANT_FIS
+
+#define CYG_REDBOOT_RFIS_VALID_MAGIC_LENGTH 10
+#define CYG_REDBOOT_RFIS_VALID_MAGIC ".FisValid" // exactly 10 bytes
+
+#define CYG_REDBOOT_RFIS_VALID (0xa5) // this FIS table is valid, the only "good" value
+#define CYG_REDBOOT_RFIS_IN_PROGRESS (0xfd) // this FIS table is being modified
+#define CYG_REDBOOT_RFIS_EMPTY (0xff) // this FIS table is empty
+
+struct fis_valid_info
+{
+ char magic_name[CYG_REDBOOT_RFIS_VALID_MAGIC_LENGTH];
+ unsigned char valid_flag[2]; // one of the flags defined above
+ unsigned long version_count; // with each successfull update the version count will increase by 1
+};
+
+#endif // CYGOPT_REDBOOT_REDUNDANT_FIS
+
#define FIS_IMAGE_DESC_SIZE_UNPADDED \
(16 + 4 * sizeof(unsigned long) + 3 * sizeof(CYG_ADDRESS))
struct fis_image_desc {
+ union
+ {
unsigned char name[16]; // Null terminated name
+ #ifdef CYGOPT_REDBOOT_REDUNDANT_FIS
+ struct fis_valid_info valid_info;
+ #endif
+ } u;
CYG_ADDRESS flash_base; // Address within FLASH of image
CYG_ADDRESS mem_base; // Address in memory where it executes
unsigned long size; // Length of image
#define _HTTP_H_
extern int http_stream_open(connection_info_t *info, int *err);
-extern int http_stream_read(char *buf, int len, int *err);
+extern int http_stream_read(void *buf, int len, int *err);
extern void http_stream_close(int *err);
extern char *http_error(int err);
-#define HTTP_NOERR 0 // No error
-#define HTTP_BADHDR 1 // Invalid HTTP header (response)
-#define HTTP_OPEN 2 // Problems opening connection
-#define HTTP_IO 3 // Misc I/O problems
-#define HTTP_BADREQ 4 // Bad request
-#define HTTP_NOFILE 5 // No such file
+#define HTTP_NOERR 0 // No error
+#define HTTP_BADHDR 1 // Invalid HTTP header (response)
+#define HTTP_OPEN 2 // Problems opening connection
+#define HTTP_IO 3 // Misc I/O problems
+#define HTTP_BADREQ 4 // Bad request
+#define HTTP_NOFILE 5 // No such file
+#define HTTP_FORBIDDEN 6 // Forbidden
extern getc_io_funcs_t http_io;
#endif // _HTTP_H_
#define ETH_TYPE_IP 0x800
#define ETH_TYPE_ARP 0x806
#define ETH_TYPE_RARP 0x8053
-} eth_header_t;
+} __attribute__((aligned(4),packed)) eth_header_t;
/*
word pkt_bytes; /* number of data bytes in buf */
word bufsize; /* size of buf */
word *buf;
-} pktbuf_t;
+} __attribute__((aligned(4),packed)) pktbuf_t;
/* protocol handler */
struct _udp_socket *next;
word our_port;
word pad;
- void (*handler)(struct _udp_socket *skt, char *buf, int len,
+ void (*handler)(struct _udp_socket *skt, void *buf, int len,
ip_route_t *src_route, word src_port);
} udp_socket_t;
-typedef void (*udp_handler_t)(udp_socket_t *skt, char *buf, int len,
+typedef void (*udp_handler_t)(udp_socket_t *skt, void *buf, int len,
ip_route_t *src_route, word src_port);
#endif
#ifdef CYGPKG_REDBOOT_NETWORKING_DNS
+#ifdef CYGPKG_REDBOOT_NETWORKING_DNS_DHCP_DOMAIN
+extern char __bootp_dns_domain[CYGNUM_REDBOOT_NETWORK_DNS_DOMAIN_BUFSIZE];
+extern cyg_bool __bootp_dns_domain_set;
+#endif
extern struct in_addr __bootp_dns_addr;
extern cyg_bool __bootp_dns_set;
#endif
/*
* Send a UDP packet.
*/
-extern int __udp_send(char *buf, int len, ip_route_t *dest_ip,
+extern int __udp_send(void *buf, int len, ip_route_t *dest_ip,
word dest_port, word src_port);
// Send a UDP packet
-extern int __udp_sendto(char *buf, int len,
+extern int __udp_sendto(void *buf, int len,
struct sockaddr_in *server, struct sockaddr_in *local);
// Receive a UDP packet
-extern int __udp_recvfrom(char *buf, int len,
+extern int __udp_recvfrom(void *buf, int len,
struct sockaddr_in *from, struct sockaddr_in *local,
struct timeval *timeout);
* Returns number of bytes read.
* If connection is closed, returns -1.
*/
-extern int __tcp_read(tcp_socket_t *s, char *buf, int len);
+extern int __tcp_read(tcp_socket_t *s, void *buf, int len);
/*
* Write up to 'len' bytes without blocking.
* Returns number of bytes written.
* If connection is closed, returns -1.
*/
-extern int __tcp_write(tcp_socket_t *s, char *buf, int len);
+extern int __tcp_write(tcp_socket_t *s, void *buf, int len);
/*
* Write up to 'len' bytes, blocking until sent (not ACK'd).
* Returns number of bytes written.
* If connection is closed, returns -1.
*/
-extern int __tcp_write_block(tcp_socket_t *s, char *buf, int len);
+extern int __tcp_write_block(tcp_socket_t *s, void *buf, int len);
/*
* Returns number of bytes read.
* Doesn't block.
*/
-extern int __skt_read(tcp_socket_t *s, char *buf, int len);
+extern int __skt_read(tcp_socket_t *s, void *buf, int len);
/*
* Write 'len' bytes to the given socket.
* Returns number of bytes written.
* May not write all data if connection closes.
*/
-extern int __skt_write(tcp_socket_t *s, char *buf, int len);
+extern int __skt_write(tcp_socket_t *s, void *buf, int len);
// Initialize the network stack - logical driver layer, etc.
extern void net_init(void);
*/
extern int tftp_stream_open(connection_info_t *info, int *err);
-extern int tftp_stream_read(char *buf, int len, int *err);
+extern int tftp_stream_read(void *buf, int len, int *err);
extern void tftp_stream_close(int *err);
extern void tftp_stream_terminate(bool abort, int (*getc)(void));
extern char *tftp_error(int err);
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Red Hat, Inc.
// Copyright (C) 2002, 2003, 2004, 2005 Gary Thomas
+// Copyright (C) 2004, 2005 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
#define NO_MEMORY (unsigned char *)0xFFFFFFFF
EXTERN bool valid_address(unsigned char *addr);
EXTERN void cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end);
-EXTERN unsigned char *workspace_start, *workspace_end;
+EXTERN unsigned char *workspace_start, *workspace_end, *workspace_end_init;
// Data squirreled away after a load operation
EXTERN unsigned long entry_address;
#endif
#ifdef CYGFUN_REDBOOT_BOOT_SCRIPT
-EXTERN unsigned char *script;
+EXTERN char *script;
EXTERN int script_timeout;
#ifdef CYGSEM_REDBOOT_VARIABLE_BAUD_RATE
EXTERN int console_baud_rate;
int (*open)(connection_info_t *info, int *err);
void (*close)(int *err);
void (*terminate)(bool abort, int (*getc)(void));
- int (*read)(char *buf, int size, int *err);
+ int (*read)(void *buf, int size, int *err);
char *(*error)(int err);
} getc_io_funcs_t;
static _cmd_entry(_s_,_h_,_u_,_f_,0,0,_n_)
// Initialization functions
-#define RedBoot_INIT_FIRST 0000
-#define RedBoot_INIT_SECOND 0100
+#define RedBoot_INIT_FIRST 0000
+#define RedBoot_INIT_SECOND 0100
// Specify a 3 digit numeric value for proper prioritizing
#define RedBoot_INIT_PRIO(_n_) 1##_n_
-#define RedBoot_INIT_LAST 9999
+#define RedBoot_INIT_BEFORE_NET 6900
+#define RedBoot_INIT_NET 7000
+#define RedBoot_INIT_AFTER_NET 7100
+#define RedBoot_INIT_LAST 9999
typedef void void_fun(void);
typedef void_fun *void_fun_ptr;
struct init_tab_entry {
struct option_info *opts, int num_opts,
void *def_arg, int def_arg_type, char *def_descr);
+externC int redboot_exec(char *command, ... );
+
+externC void err_printf(const char *fmt, ... );
+
#ifdef CYGNUM_HAL_VIRTUAL_VECTOR_AUX_CHANNELS
#define CYGNUM_HAL_VIRTUAL_VECTOR_NUM_CHANNELS \
(CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS+CYGNUM_HAL_VIRTUAL_VECTOR_AUX_CHANNELS)
externC void set_dns(char* new_ip);
externC void show_dns(void);
externC struct hostent *gethostbyname(const char *host);
+externC int setdomainname(const char *, size_t);
// Error reporting
externC int h_errno;
/* The ARM monitor may be using a different memory mapping than RedBoot */
#ifndef _ADDR_REDBOOT_TO_ARM
-# define _ADDR_REDBOOT_TO_ARM(x) (x)
+# define _ADDR_REDBOOT_TO_ARM(x)
#endif
/* Filetypes */
#endif
#ifdef CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA_FLASH
-externC bool do_flash_init(void);
+externC int do_flash_init(void);
externC int flash_read(void *flash_base, void *ram_base, int len, void **err_address);
#endif
while (dp < &p->config_data[sizeof(config->config_data)]) {
len = 4 + CONFIG_OBJECT_KEYLEN(dp) + CONFIG_OBJECT_ENABLE_KEYLEN(dp) +
config_length(CONFIG_OBJECT_TYPE(dp));
- val_ptr = (void *)CONFIG_OBJECT_VALUE(dp);
+ val_ptr = CONFIG_OBJECT_VALUE(dp);
switch (CONFIG_OBJECT_TYPE(dp)) {
// Note: the data may be unaligned in the configuration data
return CONFIG_OK; // Disabled field
}
}
- lp = line; *lp = '\0';
- val_ptr = (void *)CONFIG_OBJECT_VALUE(dp);
+ lp = line;
+ *lp = '\0';
+ val_ptr = CONFIG_OBJECT_VALUE(dp);
if (LIST_OPT_NICKNAMES & list_opt)
diag_printf("%s: ", CONFIG_OBJECT_KEY(dp));
if (LIST_OPT_FULLNAMES & list_opt) {
- if (title != (char *)NULL) {
+ if (title != NULL) {
diag_printf("%s: ", title);
} else {
diag_printf("%s: ", CONFIG_OBJECT_KEY(dp));
}
#endif
memcpy(backup_config, config, sizeof(struct _config));
- script = (unsigned char *)0;
+ script = NULL;
init_opts(&opts[0], 'l', false, OPTION_ARG_TYPE_FLG,
- (void *)&list_only, (bool *)0, "list configuration only");
+ &list_only, NULL, "list configuration only");
init_opts(&opts[1], 'n', false, OPTION_ARG_TYPE_FLG,
- (void *)&nicknames, (bool *)0, "show nicknames");
+ &nicknames, NULL, "show nicknames");
init_opts(&opts[2], 'f', false, OPTION_ARG_TYPE_FLG,
- (void *)&fullnames, (bool *)0, "show full names");
+ &fullnames, NULL, "show full names");
init_opts(&opts[3], 'i', false, OPTION_ARG_TYPE_FLG,
- (void *)&init, (bool *)0, "initialize configuration database");
+ &init, NULL, "initialize configuration database");
init_opts(&opts[4], 'd', false, OPTION_ARG_TYPE_FLG,
- (void *)&dumbterminal, (bool *)0, "dumb terminal: no clever edits");
+ &dumbterminal, NULL, "dumb terminal: no clever edits");
// First look to see if we are setting or getting a single option
// by just quoting its nickname
need_update = true;
}
- dp = &config->config_data[0];
+ dp = config->config_data;
while (dp < &config->config_data[sizeof(config->config_data)]) {
if (CONFIG_OBJECT_TYPE(dp) == CONFIG_EMPTY) {
break;
}
len = 4 + CONFIG_OBJECT_KEYLEN(dp) + CONFIG_OBJECT_ENABLE_KEYLEN(dp) +
- config_length(CONFIG_OBJECT_TYPE(dp));
+ config_length(CONFIG_OBJECT_TYPE(dp));
// Provide a title for well known [i.e. builtin] objects
- title = (char *)NULL;
+ title = NULL;
opt = __CONFIG_options_TAB__;
while (opt != optend) {
if (strcmp(opt->key, CONFIG_OBJECT_KEY(dp)) == 0) {
}
opt++;
}
- if ( onlyone && 0 != strcmp(CONFIG_OBJECT_KEY(dp), onlyone) )
+ if (onlyone && 0 != strcmp(CONFIG_OBJECT_KEY(dp), onlyone))
ret = CONFIG_OK; // skip this entry
else {
doneone = true;
dp += len;
break;
case CONFIG_BACK:
- dp = &config->config_data[0];
+ dp = config->config_data;
continue;
case CONFIG_BAD:
// Nothing - make him do it again
}
make_alias(name, argv[1]);
opt.type = CONFIG_STRING;
- opt.enable = (char *)0;
+ opt.enable = NULL;
opt.enable_sense = 1;
opt.key = name;
opt.dflt = (CYG_ADDRESS)argv[2];
} else {
dp = flash_lookup_config(alias);
if (dp) {
- val_ptr = (void *)CONFIG_OBJECT_VALUE(dp);
+ val_ptr = CONFIG_OBJECT_VALUE(dp);
switch (type = CONFIG_OBJECT_TYPE(dp)) {
case CONFIG_BOOL:
memcpy(&hold_bool_val, val_ptr, sizeof(bool));
break;
#endif
case CONFIG_SCRIPT:
- return (char *) val_ptr;
+ return val_ptr;
break;
default:
- return (char *)NULL;
+ return NULL;
}
return alias_buf;
}
- return (char *)NULL;
+ return NULL;
}
}
fis_update_directory();
#else
#ifdef CYGSEM_REDBOOT_FLASH_LOCK_SPECIAL
- // Insure [quietly] that the config page is unlocked before trying to update
- flash_unlock((void *)cfg_base, cfg_size, (void **)&err_addr);
+ // Ensure [quietly] that the config page is unlocked before trying to update
+ flash_unlock(cfg_base, cfg_size, &err_addr);
#endif
- if ((stat = flash_erase(cfg_base, cfg_size, (void **)&err_addr)) != 0) {
+ if ((stat = flash_erase(cfg_base, cfg_size, &err_addr)) != 0) {
diag_printf(" initialization failed at %p: %s\n", err_addr, flash_errmsg(stat));
} else {
conf_endian_fixup(config);
- if ((stat = FLASH_PROGRAM(cfg_base, config, sizeof(struct _config), (void **)&err_addr)) != 0) {
+ if ((stat = FLASH_PROGRAM(cfg_base, config, sizeof(struct _config), &err_addr)) != 0) {
diag_printf("Error writing config data at %p: %s\n",
err_addr, flash_errmsg(stat));
}
conf_endian_fixup(config);
}
#ifdef CYGSEM_REDBOOT_FLASH_LOCK_SPECIAL
- // Insure [quietly] that the config data is locked after the update
- flash_lock((void *)cfg_base, cfg_size, (void **)&err_addr);
+ // Ensure [quietly] that the config data is locked after the update
+ flash_lock(cfg_base, cfg_size, &err_addr);
#endif
#endif // CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
#else // CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA_FLASH
unsigned char *dp;
int len;
- if (!config_ok) return (unsigned char *)NULL;
+ if (!config_ok) return NULL;
- dp = &config->config_data[0];
+ dp = config->config_data;
while (dp < &config->config_data[sizeof(config->config_data)]) {
len = 4 + CONFIG_OBJECT_KEYLEN(dp) + CONFIG_OBJECT_ENABLE_KEYLEN(dp) +
config_length(CONFIG_OBJECT_TYPE(dp));
if (!config_ok) return false;
- if ((dp = flash_lookup_config(key)) != (unsigned char *)NULL) {
+ if ((dp = flash_lookup_config(key)) != NULL) {
if (CONFIG_OBJECT_TYPE(dp) == type) {
- val_ptr = (void *)CONFIG_OBJECT_VALUE(dp);
+ val_ptr = CONFIG_OBJECT_VALUE(dp);
switch (type) {
// Note: the data may be unaligned in the configuration data
case CONFIG_BOOL:
if (!config_ok) return false;
- if ((dp = flash_lookup_config(key)) != (unsigned char *)NULL) {
+ if ((dp = flash_lookup_config(key)) != NULL) {
if (CONFIG_OBJECT_TYPE(dp) == type) {
- val_ptr = (void *)CONFIG_OBJECT_VALUE(dp);
+ val_ptr = CONFIG_OBJECT_VALUE(dp);
switch (type) {
// Note: the data may be unaligned in the configuration data
case CONFIG_BOOL:
switch (opt->type) {
// Note: the data may be unaligned in the configuration data
case CONFIG_BOOL:
- memcpy(dp, (void *)&opt->dflt, sizeof(bool));
+ memcpy(dp, &opt->dflt, sizeof(bool));
break;
case CONFIG_INT:
- memcpy(dp, (void *)&opt->dflt, sizeof(unsigned long));
+ memcpy(dp, &opt->dflt, sizeof(unsigned long));
break;
#ifdef CYGPKG_REDBOOT_NETWORKING
case CONFIG_IP:
- memcpy(dp, (void *)&opt->dflt, sizeof(in_addr_t));
+ memcpy(dp, &opt->dflt, sizeof(in_addr_t));
break;
case CONFIG_ESA:
memcpy(dp, (void *)opt->dflt, sizeof(enet_addr_t));
// If data item is already present, just update it
// Note: only the data value can be thusly changed
- if ((dp = flash_lookup_config(opt->key)) != (unsigned char *)NULL) {
+ if ((dp = flash_lookup_config(opt->key)) != NULL) {
flash_config_insert_value(CONFIG_OBJECT_VALUE(dp), opt);
if (update) {
flash_write_config(true);
return true;
}
// Add the data item
- dp = &config->config_data[0];
+ dp = config->config_data;
size = 0;
while (size < sizeof(config->config_data)) {
if (CONFIG_OBJECT_TYPE(dp) == CONFIG_EMPTY) {
load_flash_config(void)
{
bool use_boot_script;
- unsigned char *cfg_temp = (unsigned char *)workspace_end;
+ unsigned char *cfg_temp = workspace_end;
#ifdef CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA_FLASH
void *err_addr;
#endif
config_ok = false;
- script = (unsigned char *)0;
+ script = NULL;
cfg_temp -= sizeof(struct _config); // Space for primary config data
config = (struct _config *)cfg_temp;
cfg_temp -= sizeof(struct _config); // Space for backup config data
#endif
workspace_end = cfg_temp;
#ifdef CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA_FLASH
- if (!do_flash_init()) return;
+ if (do_flash_init()<0) return;
#ifdef CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
cfg_size = _rup(sizeof(struct _config), sizeof(struct fis_image_desc));
if ((fisdir_size-cfg_size) < (CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_COUNT *
_rup(sizeof(struct _config), flash_block_size);
if (CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK < 0) {
cfg_base = (void *)((CYG_ADDRESS)flash_end + 1 -
- _rup(_rup((-CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK*flash_block_size), cfg_size), flash_block_size));
+ _rup(_rup((-CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK * flash_block_size), cfg_size),
+ flash_block_size));
} else {
cfg_base = (void *)((CYG_ADDRESS)flash_start +
- _rup(_rup((CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK*flash_block_size), cfg_size), flash_block_size));
+ _rup(_rup((CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK * flash_block_size), cfg_size),
+ flash_block_size));
}
#endif
FLASH_READ(cfg_base, config, sizeof(struct _config), &err_addr);
//==========================================================================
//
-// flash.c
+// flash.c
//
-// RedBoot - FLASH memory support
+// RedBoot - FLASH memory support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
-// Author(s): gthomas
+// Author(s): gthomas
// Contributors: gthomas, tkoeller
-// Date: 2000-07-28
-// Purpose:
-// Description:
-//
+// Date: 2000-07-28
+// Purpose:
+// Description:
+//
// This code is part of RedBoot (tm).
//
//####DESCRIPTIONEND####
//==========================================================================
#include <redboot.h>
+#define _FLASH_PRIVATE_
#include <cyg/io/flash.h>
#include <fis.h>
#include <sib.h>
-#include <cyg/infra/cyg_ass.h> // assertion macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#ifdef CYGBLD_BUILD_REDBOOT_WITH_WINCE_SUPPORT
+#include <wince.h>
+#endif
#ifdef CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
// Note horrid intertwining of functions, to save precious FLASH
#ifdef CYGOPT_REDBOOT_FIS
// Image management functions
local_cmd_entry("init",
- "Initialize FLASH Image System [FIS]",
- "[-f]",
- fis_init,
- FIS_cmds
+ "Initialize FLASH Image System [FIS]",
+ "[-f]",
+ fis_init,
+ FIS_cmds
);
#ifdef CYGSEM_REDBOOT_FIS_CRC_CHECK
# define FIS_LIST_OPTS "[-c] [-d]"
# define FIS_LIST_OPTS "[-d]"
#endif
local_cmd_entry("list",
- "Display contents of FLASH Image System [FIS]",
- FIS_LIST_OPTS,
- fis_list,
- FIS_cmds
+ "Display contents of FLASH Image System [FIS]",
+ FIS_LIST_OPTS,
+ fis_list,
+ FIS_cmds
);
local_cmd_entry("free",
- "Display free [available] locations within FLASH Image System [FIS]",
- "",
- fis_free,
- FIS_cmds
+ "Display free [available] locations within FLASH Image System [FIS]",
+ "",
+ fis_free,
+ FIS_cmds
);
local_cmd_entry("delete",
- "Delete an image from FLASH Image System [FIS]",
- "name",
- fis_delete,
- FIS_cmds
+ "Delete an image from FLASH Image System [FIS]",
+ "name",
+ fis_delete,
+ FIS_cmds
);
-static char fis_load_usage[] =
+static char fis_load_usage[] =
+#ifdef CYGPRI_REDBOOT_ZLIB_FLASH
+ "[-d] "
+#endif
+ "[-b <memory_load_address>] [-c] "
+#ifdef CYGBLD_BUILD_REDBOOT_WITH_WINCE_SUPPORT
+ "[-w]"
+#endif
+ "name\n"
+ "Options:\n"
#ifdef CYGPRI_REDBOOT_ZLIB_FLASH
- "[-d] "
+ "\t-d: decompress\n"
+#endif
+ "\t-c: print checksum\n"
+#ifdef CYGBLD_BUILD_REDBOOT_WITH_WINCE_SUPPORT
+ "\t-w: load as Windows CE image\n"
#endif
- "[-b <memory_load_address>] [-c] name";
+ ;
local_cmd_entry("load",
- "Load image from FLASH Image System [FIS] into RAM",
- fis_load_usage,
- fis_load,
- FIS_cmds
+ "Load image from FLASH Image System [FIS] into RAM",
+ fis_load_usage,
+ fis_load,
+ FIS_cmds
);
local_cmd_entry("create",
- "Create an image",
- "[-b <mem_base>] [-l <image_length>] [-s <data_length>]\n"
- " [-f <flash_addr>] [-e <entry_point>] [-r <ram_addr>] [-n] <name>",
- fis_create,
- FIS_cmds
+ "Create an image",
+ "[-b <mem_base>] [-l <image_length>] [-s <data_length>]\n"
+ " [-f <flash_addr>] [-e <entry_point>] [-r <ram_addr>] [-n] <name>",
+ fis_create,
+ FIS_cmds
);
#endif
// Raw flash access functions
local_cmd_entry("erase",
- "Erase FLASH contents",
- "-f <flash_addr> -l <length>",
- fis_erase,
- FIS_cmds
+ "Erase FLASH contents",
+ "-f <flash_addr> -l <length>",
+ fis_erase,
+ FIS_cmds
);
#ifdef CYGHWR_IO_FLASH_BLOCK_LOCKING
local_cmd_entry("lock",
- "LOCK FLASH contents",
- "[-f <flash_addr> -l <length>] [name]",
- fis_lock,
- FIS_cmds
+ "LOCK FLASH contents",
+ "[-f <flash_addr> -l <length>] [name]",
+ fis_lock,
+ FIS_cmds
);
local_cmd_entry("unlock",
- "UNLOCK FLASH contents",
- "[-f <flash_addr> -l <length>] [name]",
- fis_unlock,
- FIS_cmds
+ "UNLOCK FLASH contents",
+ "[-f <flash_addr> -l <length>] [name]",
+ fis_unlock,
+ FIS_cmds
);
#endif
local_cmd_entry("write",
- "Write raw data directly to FLASH",
- "-f <flash_addr> -b <mem_base> -l <image_length>",
- fis_write,
- FIS_cmds
+ "Write raw data directly to FLASH",
+ "-f <flash_addr> -b <mem_base> -l <image_length>",
+ fis_write,
+ FIS_cmds
);
// Define table boundaries
// CLI function
static cmd_fun do_fis;
-RedBoot_nested_cmd("fis",
- "Manage FLASH images",
- "{cmds}",
- do_fis,
- __FIS_cmds_TAB__, &__FIS_cmds_TAB_END__
+RedBoot_nested_cmd("fis",
+ "Manage FLASH images",
+ "{cmds}",
+ do_fis,
+ __FIS_cmds_TAB__, &__FIS_cmds_TAB_END__
);
// Local data used by these routines
#ifdef CYGOPT_REDBOOT_FIS
void *fis_work_block;
void *fis_addr;
+#ifdef CYGOPT_REDBOOT_REDUNDANT_FIS
+void *redundant_fis_addr;
+#endif
int fisdir_size; // Size of FIS directory.
#endif
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
-extern void *cfg_base; // Location in Flash of config data
-extern int cfg_size; // Length of config data - rounded to Flash block size
+extern void *cfg_base; // Location in Flash of config data
+extern int cfg_size; // Length of config data - rounded to Flash block size
extern struct _config *config;
#endif
cmd_usage(__FIS_cmds_TAB__, &__FIS_cmds_TAB_END__, "fis ");
}
-static void
+static void
_show_invalid_flash_address(CYG_ADDRESS flash_addr, int stat)
{
diag_printf("Invalid FLASH address %p: %s\n", (void *)flash_addr, flash_errmsg(stat));
- diag_printf(" valid range is %p-%p\n", (void *)flash_start, (void *)flash_end);
+ diag_printf(" valid range is %p-%p\n", flash_start, flash_end);
}
#ifdef CYGOPT_REDBOOT_FIS
int cnt = fisdir_size / sizeof(struct fis_image_desc);
while (cnt-- > 0) {
- p->flash_base = CYG_SWAP32(p->flash_base);
- p->mem_base = CYG_SWAP32(p->mem_base);
- p->size = CYG_SWAP32(p->size);
- p->entry_point = CYG_SWAP32(p->entry_point);
- p->data_length = CYG_SWAP32(p->data_length);
- p->desc_cksum = CYG_SWAP32(p->desc_cksum);
- p->file_cksum = CYG_SWAP32(p->file_cksum);
- p++;
+ p->flash_base = CYG_SWAP32(p->flash_base);
+ p->mem_base = CYG_SWAP32(p->mem_base);
+ p->size = CYG_SWAP32(p->size);
+ p->entry_point = CYG_SWAP32(p->entry_point);
+ p->data_length = CYG_SWAP32(p->data_length);
+ p->desc_cksum = CYG_SWAP32(p->desc_cksum);
+ p->file_cksum = CYG_SWAP32(p->file_cksum);
+ p++;
}
#endif
}
{
void *err_addr;
- FLASH_READ(fis_addr, fis_work_block, fisdir_size, (void **)&err_addr);
+ FLASH_READ(fis_addr, fis_work_block, fisdir_size, &err_addr);
fis_endian_fixup(fis_work_block);
}
fis_read_directory();
img = (struct fis_image_desc *)fis_work_block;
- for (i = 0; i < fisdir_size/sizeof(*img); i++, img++) {
- if ((img->name[0] != (unsigned char)0xFF) &&
- (strcasecmp(name, img->name) == 0)) {
- if (num) *num = i;
- return img;
- }
- }
- return (struct fis_image_desc *)0;
+ for (i = 0; i < fisdir_size/sizeof(*img); i++, img++) {
+ if ((img->u.name[0] != 0xFF) &&
+ (strcasecmp(name, img->u.name) == 0)) {
+ if (num) *num = i;
+ return img;
+ }
+ }
+ return NULL;
}
-void
-fis_update_directory(void)
+int fis_start_update_directory(int autolock)
+{
+#ifdef CYGOPT_REDBOOT_REDUNDANT_FIS
+#ifdef CYGHWR_IO_FLASH_BLOCK_LOCKING
+#ifdef CYGSEM_REDBOOT_FLASH_LOCK_SPECIAL
+ // Ensure [quietly] that the directory is unlocked before trying to update and locked again afterwards
+ int do_autolock = 1;
+#else
+ int do_autolock = autolock;
+#endif
+#endif
+
+ struct fis_image_desc *img;
+ void *err_addr;
+ void *tmp_fis_addr;
+
+ /*exchange old and new valid fis tables*/
+ tmp_fis_addr = fis_addr;
+ fis_addr = redundant_fis_addr;
+ redundant_fis_addr = tmp_fis_addr;
+
+ //adjust the contents of the new fis table
+ img = fis_work_block;
+
+ memcpy(img->u.valid_info.magic_name, CYG_REDBOOT_RFIS_VALID_MAGIC,
+ CYG_REDBOOT_RFIS_VALID_MAGIC_LENGTH);
+ img->u.valid_info.valid_flag[0] = CYG_REDBOOT_RFIS_IN_PROGRESS;
+ img->u.valid_info.valid_flag[1] = CYG_REDBOOT_RFIS_IN_PROGRESS;
+ img->u.valid_info.version_count = img->u.valid_info.version_count+1;
+
+ //ready to go....
+#ifdef CYGHWR_IO_FLASH_BLOCK_LOCKING
+ if (do_autolock)
+ flash_unlock((void *)fis_addr, fisdir_size, &err_addr);
+#endif
+
+ flash_erase(fis_addr, fisdir_size, &err_addr);
+ //now magic is 0xffffffff
+ fis_endian_fixup(fis_work_block);
+ flash_program(fis_addr, fis_work_block, flash_block_size, &err_addr);
+ fis_endian_fixup(fis_work_block);
+ //now magic is 0xff1234ff, valid is IN_PROGRESS, version_count is the old one +1
+
+#else
+ /* nothing to do here without redundant fis */
+#endif
+ return 0;
+
+}
+
+int
+fis_update_directory(int autolock, int error)
{
+ void *err_addr;
+
+#ifdef CYGHWR_IO_FLASH_BLOCK_LOCKING
+#ifdef CYGSEM_REDBOOT_FLASH_LOCK_SPECIAL
+ // Ensure [quietly] that the directory is unlocked before trying to update and locked again afterwards
+ int do_autolock = 1;
+#else
+ int do_autolock = autolock;
+#endif
+#endif
+
+#ifdef CYGOPT_REDBOOT_REDUNDANT_FIS
+
+ struct fis_image_desc *img = fis_work_block;
+
+ // called from invalid state
+ if (img->u.valid_info.valid_flag[0] != CYG_REDBOOT_RFIS_IN_PROGRESS)
+ return -1;
+
+ //if it failed, reset is0Valid to the state before startUpdateDirectory()
+ //g_data.fisTable hasn't been changed yet, so it doesn't have to be reset now
+ //then reread the contents from flash
+ //setting the valid flag of the failed table to "INVALID" might also be not too bad
+ //but IN_PROGRESS is also good enough I think
+ if (error != 0) {
+ void *swap_fis_addr = fis_addr;
+ fis_addr = redundant_fis_addr;
+ redundant_fis_addr = swap_fis_addr;
+ } else {
+ //success
+ void *tmp_fis_addr = (void *)((CYG_ADDRESS)fis_addr +
+ CYG_REDBOOT_RFIS_VALID_MAGIC_LENGTH);
+
+ img->u.valid_info.valid_flag[0] = CYG_REDBOOT_RFIS_VALID;
+ img->u.valid_info.valid_flag[1] = CYG_REDBOOT_RFIS_VALID;
+
+ flash_program(tmp_fis_addr, img->u.valid_info.valid_flag,
+ sizeof(img->u.valid_info.valid_flag), &err_addr);
+ }
+#ifdef CYGHWR_IO_FLASH_BLOCK_LOCKING
+ if (do_autolock)
+ flash_lock((void *)fis_addr, fisdir_size, &err_addr);
+#endif
+
+#else // CYGOPT_REDBOOT_REDUNDANT_FIS
+ int blk_size = fisdir_size;
int stat;
- void *err_addr;
fis_endian_fixup(fis_work_block);
#ifdef CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
memcpy((char *)fis_work_block+fisdir_size, config, cfg_size);
conf_endian_fixup((char *)fis_work_block+fisdir_size);
+ blk_size += cfg_size;
#endif
-#ifdef CYGSEM_REDBOOT_FLASH_LOCK_SPECIAL
- // Ensure [quietly] that the directory is unlocked before trying to update
- flash_unlock((void *)fis_addr, flash_block_size, (void **)&err_addr);
+#ifdef CYGHWR_IO_FLASH_BLOCK_LOCKING
+ if (do_autolock)
+ flash_unlock((void *)fis_addr, blk_size, &err_addr);
#endif
- if ((stat = flash_erase(fis_addr, flash_block_size, (void **)&err_addr)) != 0) {
- diag_printf("Error erasing FIS directory at %p: %s\n", err_addr, flash_errmsg(stat));
+ if ((stat = flash_erase(fis_addr, flash_block_size, &err_addr)) != 0) {
+ diag_printf("Error erasing FIS directory at %p: %s\n", err_addr, flash_errmsg(stat));
} else {
- if ((stat = FLASH_PROGRAM(fis_addr, fis_work_block,
- flash_block_size, (void **)&err_addr)) != 0) {
- diag_printf("Error writing FIS directory at %p: %s\n",
- err_addr, flash_errmsg(stat));
- }
+ if ((stat = FLASH_PROGRAM(fis_addr, fis_work_block,
+ flash_block_size, &err_addr)) != 0) {
+ diag_printf("Error writing FIS directory at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ }
+ }
+ fis_endian_fixup(fis_work_block);
+#ifdef CYGHWR_IO_FLASH_BLOCK_LOCKING
+ if (do_autolock)
+ flash_lock((void *)fis_addr, blk_size, &err_addr);
+#endif
+
+#endif // CYGOPT_REDBOOT_REDUNDANT_FIS
+
+ return 0;
+}
+
+#ifdef CYGOPT_REDBOOT_REDUNDANT_FIS
+
+int
+fis_get_valid_buf(struct fis_image_desc *img0, struct fis_image_desc *img1, int *update_was_interrupted)
+{
+ *update_was_interrupted = 0;
+ if (strncmp(img1->u.valid_info.magic_name, CYG_REDBOOT_RFIS_VALID_MAGIC,
+ CYG_REDBOOT_RFIS_VALID_MAGIC_LENGTH) != 0) {
+ //buf0 must be valid
+ if (img0->u.valid_info.version_count > 0) {
+ *update_was_interrupted = 1;
+ }
+ return 0;
+ } else if (strncmp(img0->u.valid_info.magic_name, CYG_REDBOOT_RFIS_VALID_MAGIC,
+ CYG_REDBOOT_RFIS_VALID_MAGIC_LENGTH) != 0) {
+ //buf1 must be valid
+ if (img1->u.valid_info.version_count > 0) {
+ *update_was_interrupted = 1;
+ }
+ return 1;
+ }
+ //magic is ok for both, now check the valid flag
+ if ((img1->u.valid_info.valid_flag[0] != CYG_REDBOOT_RFIS_VALID) ||
+ (img1->u.valid_info.valid_flag[1] != CYG_REDBOOT_RFIS_VALID)) {
+ //buf0 must be valid
+ *update_was_interrupted = 1;
+ return 0;
+ } else if ((img0->u.valid_info.valid_flag[0] != CYG_REDBOOT_RFIS_VALID) ||
+ (img0->u.valid_info.valid_flag[1] != CYG_REDBOOT_RFIS_VALID)) {
+ //buf1 must be valid
+ *update_was_interrupted = 1;
+ return 1;
+ }
+
+ //now check the version
+ return img1->u.valid_info.version_count == (img0->u.valid_info.version_count + 1);
+}
+
+void
+fis_erase_redundant_directory(void)
+{
+ int stat;
+ void *err_addr;
+
+#ifdef CYGSEM_REDBOOT_FLASH_LOCK_SPECIAL
+ // Ensure [quietly] that the directory is unlocked before trying
+ // to update
+ flash_unlock((void *)redundant_fis_addr, fisdir_size,
+ &err_addr);
+#endif
+ if ((stat = flash_erase(redundant_fis_addr, fisdir_size,
+ &err_addr)) != 0) {
+ diag_printf("Error erasing FIS directory at %p: %s\n",
+ err_addr, flash_errmsg(stat));
}
#ifdef CYGSEM_REDBOOT_FLASH_LOCK_SPECIAL
// Ensure [quietly] that the directory is locked after the update
- flash_lock((void *)fis_addr, flash_block_size, (void **)&err_addr);
+ flash_lock((void *)redundant_fis_addr, fisdir_size, &err_addr);
#endif
- fis_endian_fixup(fis_work_block);
}
+#endif
static void
fis_init(int argc, char *argv[])
CYG_ADDRESS redboot_flash_start;
unsigned long redboot_image_size;
- init_opts(&opts[0], 'f', false, OPTION_ARG_TYPE_FLG,
- (void *)&full_init, (bool *)0, "full initialization, erases all of flash");
- if (!scan_opts(argc, argv, 2, opts, 1, 0, 0, ""))
- {
- return;
+ init_opts(&opts[0], 'f', false, OPTION_ARG_TYPE_FLG,
+ &full_init, NULL, "full initialization, erases all of flash");
+ if (!scan_opts(argc, argv, 2, opts, 1, 0, 0, "")) {
+ return;
}
if (!verify_action("About to initialize [format] FLASH image system")) {
- diag_printf("** Aborted\n");
- return;
+ diag_printf("** Aborted\n");
+ return;
}
diag_printf("*** Initialize FLASH Image System\n");
#define MIN_REDBOOT_IMAGE_SIZE CYGBLD_REDBOOT_MIN_IMAGE_SIZE
- redboot_image_size = flash_block_size > MIN_REDBOOT_IMAGE_SIZE ?
- flash_block_size : MIN_REDBOOT_IMAGE_SIZE;
+ redboot_image_size = flash_block_size > MIN_REDBOOT_IMAGE_SIZE ?
+ flash_block_size : MIN_REDBOOT_IMAGE_SIZE;
- // Create a pseudo image for RedBoot
- img = (struct fis_image_desc *)fis_work_block;
+ img = fis_work_block;
memset(img, 0xFF, fisdir_size); // Start with erased data
+
+#ifdef CYGOPT_REDBOOT_REDUNDANT_FIS
+ //create the valid flag entry
+ memset(img, 0, sizeof(struct fis_image_desc));
+ strcpy(img->u.valid_info.magic_name, CYG_REDBOOT_RFIS_VALID_MAGIC);
+ img->u.valid_info.valid_flag[0] = CYG_REDBOOT_RFIS_VALID;
+ img->u.valid_info.valid_flag[1] = CYG_REDBOOT_RFIS_VALID;
+ img->u.valid_info.version_count = 0;
+ img++;
+#endif
+
+ // Create a pseudo image for RedBoot
#ifdef CYGOPT_REDBOOT_FIS_RESERVED_BASE
memset(img, 0, sizeof(*img));
- strcpy(img->name, "(reserved)");
+ strcpy(img->u.name, "(reserved)");
img->flash_base = (CYG_ADDRESS)flash_start;
img->mem_base = (CYG_ADDRESS)flash_start;
img->size = CYGNUM_REDBOOT_FLASH_RESERVED_BASE;
redboot_flash_start = (CYG_ADDRESS)flash_start + CYGBLD_REDBOOT_FLASH_BOOT_OFFSET;
#ifdef CYGOPT_REDBOOT_FIS_REDBOOT
memset(img, 0, sizeof(*img));
- strcpy(img->name, "RedBoot");
+ strcpy(img->u.name, "RedBoot");
img->flash_base = redboot_flash_start;
img->mem_base = redboot_flash_start;
img->size = redboot_image_size;
redboot_flash_start = (CYG_ADDRESS)flash_start + CYGNUM_REDBOOT_FIS_REDBOOT_POST_OFFSET;
#endif
memset(img, 0, sizeof(*img));
- strcpy(img->name, "RedBoot[post]");
+ strcpy(img->u.name, "RedBoot[post]");
img->flash_base = redboot_flash_start;
img->mem_base = redboot_flash_start;
img->size = redboot_image_size;
#ifdef CYGOPT_REDBOOT_FIS_REDBOOT_BACKUP
// And a backup image
memset(img, 0, sizeof(*img));
- strcpy(img->name, "RedBoot[backup]");
+ strcpy(img->u.name, "RedBoot[backup]");
img->flash_base = redboot_flash_start;
img->mem_base = redboot_flash_start;
img->size = redboot_image_size;
#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA_FLASH)
// And a descriptor for the configuration data
memset(img, 0, sizeof(*img));
- strcpy(img->name, "RedBoot config");
+ strcpy(img->u.name, "RedBoot config");
img->flash_base = (CYG_ADDRESS)cfg_base;
img->mem_base = (CYG_ADDRESS)cfg_base;
img->size = cfg_size;
#endif
// And a descriptor for the descriptor table itself
memset(img, 0, sizeof(*img));
- strcpy(img->name, "FIS directory");
+ strcpy(img->u.name, "FIS directory");
img->flash_base = (CYG_ADDRESS)fis_addr;
img->mem_base = (CYG_ADDRESS)fis_addr;
img->size = fisdir_size;
img++;
+ //create the entry for the redundant fis table
+#ifdef CYGOPT_REDBOOT_REDUNDANT_FIS
+ memset(img, 0, sizeof(*img));
+ strcpy(img->u.name, "Redundant FIS");
+ img->flash_base = (CYG_ADDRESS)redundant_fis_addr;
+ img->mem_base = (CYG_ADDRESS)redundant_fis_addr;
+ img->size = fisdir_size;
+ img++;
+#endif
+
#ifdef CYGOPT_REDBOOT_FIS_DIRECTORY_ARM_SIB_ID
// FIS gets the size of a full block - note, this should be changed
// if support is added for multi-block FIS structures.
// Add a footer so the FIS will be recognized by the ARM Boot
// Monitor as a reserved area.
{
- tFooter* footer_p = (tFooter*)((CYG_ADDRESS)img - sizeof(tFooter));
- cyg_uint32 check = 0;
- cyg_uint32 *check_ptr = (cyg_uint32 *)footer_p;
- cyg_int32 count = (sizeof(tFooter) - 4) >> 2;
-
- // Prepare footer. Try to protect all but the reserved space
- // and the first RedBoot image (which is expected to be
- // bootable), but fall back to just protecting the FIS if it's
- // not at the default position in the flash.
+ tFooter *footer_p = (tFooter*)((CYG_ADDRESS)img - sizeof(tFooter));
+ cyg_uint32 check = 0;
+ cyg_uint32 *check_ptr = (cyg_uint32 *)footer_p;
+ cyg_int32 count = (sizeof(tFooter) - 4) >> 2;
+
+ // Prepare footer. Try to protect all but the reserved space
+ // and the first RedBoot image (which is expected to be
+ // bootable), but fall back to just protecting the FIS if it's
+ // not at the default position in the flash.
#if defined(CYGOPT_REDBOOT_FIS_RESERVED_BASE) && (-1 == CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK)
- footer_p->blockBase = (char*)_ADDR_REDBOOT_TO_ARM(flash_start);
- footer_p->blockBase += CYGNUM_REDBOOT_FLASH_RESERVED_BASE + redboot_image_size;
+ footer_p->blockBase = (char*)_ADDR_REDBOOT_TO_ARM(flash_start);
+ footer_p->blockBase += CYGNUM_REDBOOT_FLASH_RESERVED_BASE + redboot_image_size;
#else
- footer_p->blockBase = (char*)_ADDR_REDBOOT_TO_ARM(fis_work_block);
-#endif
- footer_p->infoBase = NULL;
- footer_p->signature = FLASH_FOOTER_SIGNATURE;
- footer_p->type = TYPE_REDHAT_REDBOOT;
-
- // and compute its checksum
- for ( ; count > 0; count--) {
- if (*check_ptr > ~check)
- check++;
- check += *check_ptr++;
- }
- footer_p->checksum = ~check;
+ footer_p->blockBase = (char*)_ADDR_REDBOOT_TO_ARM(fis_work_block);
+#endif
+ footer_p->infoBase = NULL;
+ footer_p->signature = FLASH_FOOTER_SIGNATURE;
+ footer_p->type = TYPE_REDHAT_REDBOOT;
+
+ // and compute its checksum
+ for ( ; count > 0; count--) {
+ if (*check_ptr > ~check)
+ check++;
+ check += *check_ptr++;
+ }
+ footer_p->checksum = ~check;
}
#endif
// calculates where the high water mark of default RedBoot images is.
if (full_init) {
- unsigned long erase_size;
- CYG_ADDRESS erase_start;
- // Erase everything except default RedBoot images, fis block,
- // and config block.
- // First deal with the possible first part, before RedBoot images:
+ unsigned long erase_size;
+ CYG_ADDRESS erase_start;
+ // Erase everything except default RedBoot images, fis block,
+ // and config block.
+ // First deal with the possible first part, before RedBoot images:
#if (CYGBLD_REDBOOT_FLASH_BOOT_OFFSET > CYGNUM_REDBOOT_FLASH_RESERVED_BASE)
- erase_start = (CYG_ADDRESS)flash_start + CYGNUM_REDBOOT_FLASH_RESERVED_BASE;
- erase_size = (CYG_ADDRESS)flash_start + CYGBLD_REDBOOT_FLASH_BOOT_OFFSET;
- if ( erase_size > erase_start ) {
- erase_size -= erase_start;
- if ((stat = flash_erase((void *)erase_start, erase_size,
- (void **)&err_addr)) != 0) {
- diag_printf(" initialization failed at %p: %s\n",
- err_addr, flash_errmsg(stat));
- }
- }
-#endif
- // second deal with the larger part in the main:
- erase_start = redboot_flash_start; // high water of created images
- // Now the empty bits between the end of Redboot and the cfg and dir
- // blocks.
+ erase_start = (CYG_ADDRESS)flash_start + CYGNUM_REDBOOT_FLASH_RESERVED_BASE;
+ erase_size = (CYG_ADDRESS)flash_start + CYGBLD_REDBOOT_FLASH_BOOT_OFFSET;
+ if ( erase_size > erase_start ) {
+ erase_size -= erase_start;
+ if ((stat = flash_erase((void *)erase_start, erase_size,
+ &err_addr)) != 0) {
+ diag_printf(" initialization failed at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ }
+ }
+#endif
+ // second deal with the larger part in the main:
+ erase_start = redboot_flash_start; // high water of created images
+ // Now the empty bits between the end of Redboot and the cfg and dir
+ // blocks.
#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && \
defined(CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA_FLASH) && \
!defined(CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG)
- if (fis_addr > cfg_base) {
- erase_size = (CYG_ADDRESS)cfg_base - erase_start; // the gap between HWM and config data
- } else {
- erase_size = (CYG_ADDRESS)fis_addr - erase_start; // the gap between HWM and fis data
- }
- if ((stat = flash_erase((void *)erase_start, erase_size,
- (void **)&err_addr)) != 0) {
- diag_printf(" initialization failed %p: %s\n",
- err_addr, flash_errmsg(stat));
- }
- erase_start += (erase_size + flash_block_size);
- if (fis_addr > cfg_base) {
- erase_size = (CYG_ADDRESS)fis_addr - erase_start; // the gap between config and fis data
- } else {
- erase_size = (CYG_ADDRESS)cfg_base - erase_start; // the gap between fis and config data
- }
- if ((stat = flash_erase((void *)erase_start, erase_size,
- (void **)&err_addr)) != 0) {
- diag_printf(" initialization failed %p: %s\n",
- err_addr, flash_errmsg(stat));
- }
- erase_start += (erase_size + flash_block_size);
-#else // !CYGSEM_REDBOOT_FLASH_CONFIG
- erase_size = (CYG_ADDRESS)fis_addr - erase_start; // the gap between HWM and fis data
- if ((stat = flash_erase((void *)erase_start, erase_size,
- (void **)&err_addr)) != 0) {
- diag_printf(" initialization failed %p: %s\n",
- err_addr, flash_errmsg(stat));
- }
- erase_start += (erase_size + flash_block_size);
-#endif
- // Lastly, anything at the end, if there is any
- if ( erase_start < (((CYG_ADDRESS)flash_end)+1) ) {
- erase_size = ((CYG_ADDRESS)flash_end - erase_start) + 1;
- if ((stat = flash_erase((void *)erase_start, erase_size,
- (void **)&err_addr)) != 0) {
- diag_printf(" initialization failed at %p: %s\n",
- err_addr, flash_errmsg(stat));
- }
- }
+ if (fis_addr > cfg_base) {
+ erase_size = (CYG_ADDRESS)cfg_base - erase_start; // the gap between HWM and config data
+ } else {
+ erase_size = (CYG_ADDRESS)fis_addr - erase_start; // the gap between HWM and fis data
+ }
+ if ((stat = flash_erase((void *)erase_start, erase_size,
+ &err_addr)) != 0) {
+ diag_printf(" initialization failed %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ }
+ erase_start += erase_size + flash_block_size;
+ if (fis_addr > cfg_base) {
+ erase_size = (CYG_ADDRESS)fis_addr - erase_start; // the gap between config and fis data
+ } else {
+ erase_size = (CYG_ADDRESS)cfg_base - erase_start; // the gap between fis and config data
+ }
+ if ((stat = flash_erase((void *)erase_start, erase_size,
+ &err_addr)) != 0) {
+ diag_printf(" initialization failed %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ }
+ erase_start += erase_size + flash_block_size;
+#else // !CYGSEM_REDBOOT_FLASH_CONFIG
+ erase_size = (CYG_ADDRESS)fis_addr - erase_start; // the gap between HWM and fis data
+ if ((stat = flash_erase((void *)erase_start, erase_size,
+ &err_addr)) != 0) {
+ diag_printf(" initialization failed %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ }
+ erase_start += erase_size + flash_block_size;
+#endif
+ // Lastly, anything at the end, if there is any
+ if ( erase_start < (((CYG_ADDRESS)flash_end)+1) ) {
+ erase_size = ((CYG_ADDRESS)flash_end - erase_start) + 1;
+ if ((stat = flash_erase((void *)erase_start, erase_size,
+ &err_addr)) != 0) {
+ diag_printf(" initialization failed at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ }
+ }
#ifndef CYGDAT_REDBOOT_FIS_MAX_FREE_CHUNKS
- // In this case, 'fis free' works by scanning for erased blocks. Since the
- // "-f" option was not supplied, there may be areas which are not used but
- // don't appear to be free since they are not erased - thus the warning
+ // In this case, 'fis free' works by scanning for erased blocks. Since the
+ // "-f" option was not supplied, there may be areas which are not used but
+ // don't appear to be free since they are not erased - thus the warning
} else {
- diag_printf(" Warning: device contents not erased, some blocks may not be usable\n");
+ diag_printf(" Warning: device contents not erased, some blocks may not be usable\n");
#endif
}
- fis_update_directory();
+ fis_start_update_directory(0);
+ fis_update_directory(0, 0);
+#ifdef CYGOPT_REDBOOT_REDUNDANT_FIS
+ fis_erase_redundant_directory();
+#endif
}
static void
fis_list(int argc, char *argv[])
{
struct fis_image_desc *img;
- int i, image_indx;
+ int i = 0, image_indx;
bool show_cksums = false;
bool show_datalen = false;
struct option_info opts[2];
return;
#endif
- init_opts(&opts[0], 'd', false, OPTION_ARG_TYPE_FLG,
- (void *)&show_datalen, (bool *)0, "display data length");
+ init_opts(&opts[i++], 'd', false, OPTION_ARG_TYPE_FLG,
+ &show_datalen, NULL, "display data length");
#ifdef CYGSEM_REDBOOT_FIS_CRC_CHECK
- init_opts(&opts[1], 'c', false, OPTION_ARG_TYPE_FLG,
- (void *)&show_cksums, (bool *)0, "display checksums");
- i = 2;
-#else
- i = 1;
+ init_opts(&opts[i++], 'c', false, OPTION_ARG_TYPE_FLG,
+ &show_cksums, NULL, "display checksums");
#endif
if (!scan_opts(argc, argv, 2, opts, i, 0, 0, "")) {
- return;
+ return;
}
fis_read_directory();
// Let diag_printf do the formatting in both cases, rather than counting
// cols by hand....
diag_printf("%-16s %-10s %-10s %-10s %-s\n",
- "Name","FLASH addr",
- show_cksums ? "Checksum" : "Mem addr",
- show_datalen ? "Datalen" : "Length",
- "Entry point" );
+ "Name","FLASH addr",
+ show_cksums ? "Checksum" : "Mem addr",
+ show_datalen ? "Datalen" : "Length",
+ "Entry point" );
last_addr = 0;
image_indx = 0;
do {
- image_found = false;
- lowest_addr = 0xFFFFFFFF;
- img = (struct fis_image_desc *) fis_work_block;
- for (i = 0; i < fisdir_size/sizeof(*img); i++, img++) {
- if (img->name[0] != (unsigned char)0xFF) {
- if ((img->flash_base > last_addr) && (img->flash_base < lowest_addr)) {
- lowest_addr = img->flash_base;
- image_found = true;
- image_indx = i;
- }
- }
- }
- if (image_found) {
- img = (struct fis_image_desc *) fis_work_block;
- img += image_indx;
- diag_printf("%-16s 0x%08lX 0x%08lX 0x%08lX 0x%08lX\n", img->name,
- (unsigned long)img->flash_base,
+ image_found = false;
+ lowest_addr = 0xFFFFFFFF;
+ img = fis_work_block;
+ for (i = 0; i < fisdir_size/sizeof(*img); i++, img++) {
+ if (img->u.name[0] != 0xFF) {
+ if ((img->flash_base >= last_addr) && (img->flash_base < lowest_addr)) {
+ lowest_addr = img->flash_base;
+ image_found = true;
+ image_indx = i;
+ }
+ }
+ }
+ if (image_found) {
+ img = fis_work_block;
+ img += image_indx;
+ diag_printf("%-16s 0x%08lX 0x%08lX 0x%08lX 0x%08lX\n", img->u.name,
+ (unsigned long)img->flash_base,
#ifdef CYGSEM_REDBOOT_FIS_CRC_CHECK
- show_cksums ? img->file_cksum : img->mem_base,
- show_datalen ? img->data_length : img->size,
+ show_cksums ? img->file_cksum : img->mem_base,
+ show_datalen ? img->data_length : img->size,
#else
- img->mem_base,
- img->size,
+ img->mem_base,
+ img->size,
#endif
- (unsigned long)img->entry_point);
- }
- last_addr = lowest_addr;
+ (unsigned long)img->entry_point);
+ }
+ last_addr = lowest_addr + 1;
} while (image_found == true);
}
int num_chunks = 1;
// Do not search the area reserved for pre-RedBoot systems:
- fis_ptr = (CYG_ADDRESS *)((CYG_ADDRESS)flash_start +
- CYGNUM_REDBOOT_FLASH_RESERVED_BASE);
+ fis_ptr = (CYG_ADDRESS *)((CYG_ADDRESS)flash_start +
+ CYGNUM_REDBOOT_FLASH_RESERVED_BASE);
fis_end = (CYG_ADDRESS *)flash_end;
- chunks[num_chunks-1].start = (CYG_ADDRESS)fis_ptr;
- chunks[num_chunks-1].end = (CYG_ADDRESS)fis_end;
+ chunks[num_chunks - 1].start = (CYG_ADDRESS)fis_ptr;
+ chunks[num_chunks - 1].end = (CYG_ADDRESS)fis_end;
fis_read_directory();
- img = (struct fis_image_desc *) fis_work_block;
+ img = fis_work_block;
for (i = 0; i < fisdir_size/sizeof(*img); i++, img++) {
- if (img->name[0] != (unsigned char)0xFF) {
- // Figure out which chunk this is in and split it
- for (idx = 0; idx < num_chunks; idx++) {
- if ((img->flash_base >= chunks[idx].start) &&
- (img->flash_base <= chunks[idx].end)) {
- if (img->flash_base == chunks[idx].start) {
- chunks[idx].start += img->size;
- if (chunks[idx].start >= chunks[idx].end) {
- // This free chunk has collapsed
- while (idx < (num_chunks-1)) {
- chunks[idx] = chunks[idx+1];
- idx++;
- }
- num_chunks--;
- }
- } else if ((img->flash_base+img->size) == chunks[idx].end) {
- chunks[idx].end = img->flash_base;
- } else {
- // Split chunk into two parts
- if ((img->flash_base+img->size) < (CYG_ADDRESS)fis_end) {
- int j;
- // make room for new chunk
- for (j = num_chunks; j > (idx+1); j--)
- chunks[j] = chunks[j-1];
- chunks[idx+1].start = img->flash_base + img->size;
- chunks[idx+1].end = chunks[idx].end;
- if (++num_chunks == CYGDAT_REDBOOT_FIS_MAX_FREE_CHUNKS) {
- diag_printf("Warning: too many free chunks\n");
- return num_chunks;
- }
- }
- chunks[idx].end = img->flash_base;
- }
- break;
- }
- }
- }
+ if (img->u.name[0] != 0xFF) {
+ // Figure out which chunk this is in and split it
+ for (idx = 0; idx < num_chunks; idx++) {
+ if ((img->flash_base >= chunks[idx].start) &&
+ (img->flash_base <= chunks[idx].end)) {
+ if (img->flash_base == chunks[idx].start) {
+ chunks[idx].start += img->size;
+ if (chunks[idx].start >= chunks[idx].end) {
+ // This free chunk has collapsed
+ while (idx < (num_chunks-1)) {
+ chunks[idx] = chunks[idx+1];
+ idx++;
+ }
+ num_chunks--;
+ }
+ } else if ((img->flash_base+img->size) == chunks[idx].end) {
+ chunks[idx].end = img->flash_base;
+ } else {
+ // Split chunk into two parts
+ if ((img->flash_base+img->size) < (CYG_ADDRESS)fis_end) {
+ int j;
+ // make room for new chunk
+ for (j = num_chunks; j > idx + 1; j--)
+ chunks[j] = chunks[j-1];
+ chunks[idx+1].start = img->flash_base + img->size;
+ chunks[idx+1].end = chunks[idx].end;
+ if (++num_chunks == CYGDAT_REDBOOT_FIS_MAX_FREE_CHUNKS) {
+ diag_printf("Warning: too many free chunks\n");
+ return num_chunks;
+ }
+ }
+ chunks[idx].end = img->flash_base;
+ }
+ break;
+ }
+ }
+ }
}
return num_chunks;
}
void *err_addr;
// Do not search the area reserved for pre-RedBoot systems:
- fis_ptr = (unsigned long *)((CYG_ADDRESS)flash_start +
- CYGNUM_REDBOOT_FLASH_RESERVED_BASE);
+ fis_ptr = (unsigned long *)((CYG_ADDRESS)flash_start +
+ CYGNUM_REDBOOT_FLASH_RESERVED_BASE);
fis_end = (unsigned long *)(CYG_ADDRESS)flash_end;
area_start = fis_ptr;
while (fis_ptr < fis_end) {
- flash_read(fis_ptr, &flash_data, sizeof(unsigned long), (void **)&err_addr);
- if (flash_data != (unsigned long)0xFFFFFFFF) {
- if (area_start != fis_ptr) {
- // Assume that this is something
- diag_printf(" 0x%08lX .. 0x%08lX\n",
- (CYG_ADDRESS)area_start, (CYG_ADDRESS)fis_ptr);
- }
- // Find next blank block
- area_start = fis_ptr;
- while (area_start < fis_end) {
- flash_read(area_start, &flash_data, sizeof(unsigned long), (void **)&err_addr);
- if (flash_data == (unsigned long)0xFFFFFFFF) {
- break;
- }
- area_start += flash_block_size / sizeof(CYG_ADDRESS);
- }
- fis_ptr = area_start;
- } else {
- fis_ptr += flash_block_size / sizeof(CYG_ADDRESS);
- }
+ flash_read(fis_ptr, &flash_data, sizeof(unsigned long), &err_addr);
+ if (flash_data != 0xFFFFFFFF) {
+ if (area_start != fis_ptr) {
+ // Assume that this is something
+ diag_printf(" 0x%08x .. 0x%08x\n",
+ (CYG_ADDRESS)area_start, (CYG_ADDRESS)fis_ptr);
+ }
+ // Find next blank block
+ area_start = fis_ptr;
+ while (area_start < fis_end) {
+ flash_read(area_start, &flash_data, sizeof(unsigned long), &err_addr);
+ if (flash_data == 0xFFFFFFFF) {
+ break;
+ }
+ area_start += flash_block_size / sizeof(CYG_ADDRESS);
+ }
+ fis_ptr = area_start;
+ } else {
+ fis_ptr += flash_block_size / sizeof(CYG_ADDRESS);
+ }
}
if (area_start != fis_ptr) {
- diag_printf(" 0x%08lX .. 0x%08lX\n",
- (CYG_ADDRESS)area_start, (CYG_ADDRESS)fis_ptr);
+ diag_printf(" 0x%08x .. 0x%08x\n",
+ (CYG_ADDRESS)area_start, (CYG_ADDRESS)fis_ptr);
}
#else
struct free_chunk chunks[CYGDAT_REDBOOT_FIS_MAX_FREE_CHUNKS];
int idx, num_chunks;
num_chunks = find_free(chunks);
- for (idx = 0; idx < num_chunks; idx++) {
- diag_printf(" 0x%08lX .. 0x%08lX\n",
- (unsigned long)chunks[idx].start,
- (unsigned long)chunks[idx].end);
+ for (idx = 0; idx < num_chunks; idx++) {
+ diag_printf(" 0x%08x .. 0x%08x\n",
+ chunks[idx].start,
+ chunks[idx].end);
}
#endif
}
void *err_addr;
// Do not search the area reserved for pre-RedBoot systems:
- fis_ptr = (unsigned long *)((CYG_ADDRESS)flash_start +
- CYGNUM_REDBOOT_FLASH_RESERVED_BASE);
+ fis_ptr = (unsigned long *)((CYG_ADDRESS)flash_start +
+ CYGNUM_REDBOOT_FLASH_RESERVED_BASE);
fis_end = (unsigned long *)(CYG_ADDRESS)flash_end;
area_start = fis_ptr;
while (fis_ptr < fis_end) {
- flash_read(fis_ptr, &flash_data, sizeof(unsigned long), (void **)&err_addr);
- if (flash_data != (unsigned long)0xFFFFFFFF) {
- if (area_start != fis_ptr) {
- // Assume that this is something
- if ((fis_ptr-area_start) >= (length/sizeof(unsigned))) {
- *addr = (CYG_ADDRESS)area_start;
- return true;
- }
- }
- // Find next blank block
- area_start = fis_ptr;
- while (area_start < fis_end) {
- flash_read(area_start, &flash_data, sizeof(unsigned long), (void **)&err_addr);
- if (flash_data == (unsigned long)0xFFFFFFFF) {
- break;
- }
- area_start += flash_block_size / sizeof(CYG_ADDRESS);
- }
- fis_ptr = area_start;
- } else {
- fis_ptr += flash_block_size / sizeof(CYG_ADDRESS);
- }
+ flash_read(fis_ptr, &flash_data, sizeof(unsigned long), &err_addr);
+ if (flash_data != 0xFFFFFFFF) {
+ if (area_start != fis_ptr) {
+ // Assume that this is something
+ if ((fis_ptr - area_start) >= (length/sizeof(unsigned))) {
+ *addr = (CYG_ADDRESS)area_start;
+ return true;
+ }
+ }
+ // Find next blank block
+ area_start = fis_ptr;
+ while (area_start < fis_end) {
+ flash_read(area_start, &flash_data, sizeof(unsigned long), &err_addr);
+ if (flash_data == 0xFFFFFFFF) {
+ break;
+ }
+ area_start += flash_block_size / sizeof(CYG_ADDRESS);
+ }
+ fis_ptr = area_start;
+ } else {
+ fis_ptr += flash_block_size / sizeof(CYG_ADDRESS);
+ }
}
if (area_start != fis_ptr) {
- if ((fis_ptr-area_start) >= (length/sizeof(unsigned))) {
- *addr = (CYG_ADDRESS)area_start;
- return true;
- }
+ if (fis_ptr - area_start >= length / sizeof(unsigned)) {
+ *addr = (CYG_ADDRESS)area_start;
+ return true;
+ }
}
return false;
#else
int idx, num_chunks;
num_chunks = find_free(chunks);
- for (idx = 0; idx < num_chunks; idx++) {
- if ((chunks[idx].end - chunks[idx].start) >= length) {
- *addr = (CYG_ADDRESS)chunks[idx].start;
- return true;
- }
+ for (idx = 0; idx < num_chunks; idx++) {
+ if (chunks[idx].end + 1 - chunks[idx].start >= length) {
+ *addr = (CYG_ADDRESS)chunks[idx].start;
+ return true;
+ }
}
return false;
#endif
struct option_info opts[7];
bool prog_ok = true;
- init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM,
- (void *)&mem_addr, (bool *)&mem_addr_set, "memory base address");
- init_opts(&opts[1], 'r', true, OPTION_ARG_TYPE_NUM,
- (void *)&exec_addr, (bool *)&exec_addr_set, "ram base address");
- init_opts(&opts[2], 'e', true, OPTION_ARG_TYPE_NUM,
- (void *)&entry_addr, (bool *)&entry_addr_set, "entry point address");
- init_opts(&opts[3], 'f', true, OPTION_ARG_TYPE_NUM,
- (void *)&flash_addr, (bool *)&flash_addr_set, "FLASH memory base address");
- init_opts(&opts[4], 'l', true, OPTION_ARG_TYPE_NUM,
- (void *)&length, (bool *)&length_set, "image length [in FLASH]");
- init_opts(&opts[5], 's', true, OPTION_ARG_TYPE_NUM,
- (void *)&img_size, (bool *)&img_size_set, "image size [actual data]");
- init_opts(&opts[6], 'n', false, OPTION_ARG_TYPE_FLG,
- (void *)&no_copy, (bool *)0, "don't copy from RAM to FLASH, just update directory");
- if (!scan_opts(argc, argv, 2, opts, 7, (void *)&name, OPTION_ARG_TYPE_STR, "file name"))
- {
- fis_usage("invalid arguments");
- return;
- }
+ init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM,
+ &mem_addr, &mem_addr_set, "memory base address");
+ init_opts(&opts[1], 'r', true, OPTION_ARG_TYPE_NUM,
+ &exec_addr, &exec_addr_set, "ram base address");
+ init_opts(&opts[2], 'e', true, OPTION_ARG_TYPE_NUM,
+ &entry_addr, &entry_addr_set, "entry point address");
+ init_opts(&opts[3], 'f', true, OPTION_ARG_TYPE_NUM,
+ &flash_addr, &flash_addr_set, "FLASH memory base address");
+ init_opts(&opts[4], 'l', true, OPTION_ARG_TYPE_NUM,
+ &length, &length_set, "image length [in FLASH]");
+ init_opts(&opts[5], 's', true, OPTION_ARG_TYPE_NUM,
+ &img_size, &img_size_set, "image size [actual data]");
+ init_opts(&opts[6], 'n', false, OPTION_ARG_TYPE_FLG,
+ &no_copy, NULL, "don't copy from RAM to FLASH, just update directory");
+ if (!scan_opts(argc, argv, 2, opts, 7, &name, OPTION_ARG_TYPE_STR, "file name")) {
+ fis_usage("invalid arguments");
+ return;
+ }
fis_read_directory();
defaults_assumed = false;
if (name) {
- // Search existing files to acquire defaults for params not specified:
- img = fis_lookup(name, NULL);
- if (img) {
- // Found it, so get image size from there
- if (!length_set) {
- length_set = true;
- length = img->size;
- defaults_assumed = true;
- }
- }
+ // Search existing files to acquire defaults for params not specified:
+ img = fis_lookup(name, NULL);
+ if (img) {
+ // Found it, so get image size from there
+ if (!length_set) {
+ length_set = true;
+ length = img->size;
+ defaults_assumed = true;
+ }
+ }
}
if (!mem_addr_set && (load_address >= (CYG_ADDRESS)ram_start) &&
- (load_address_end) < (CYG_ADDRESS)ram_end) {
- mem_addr = load_address;
- mem_addr_set = true;
- defaults_assumed = true;
- // Get entry address from loader, unless overridden
- if (!entry_addr_set)
- entry_addr = entry_address;
- if (!length_set) {
- length = load_address_end - load_address;
- length_set = true;
- } else if (defaults_assumed && !img_size_set) {
- /* We got length from the FIS table, so the size of the
- actual loaded image becomes img_size */
- img_size = load_address_end - load_address;
- img_size_set = true;
- }
+ (load_address_end) < (CYG_ADDRESS)ram_end) {
+ mem_addr = load_address;
+ mem_addr_set = true;
+ defaults_assumed = true;
+ // Get entry address from loader, unless overridden
+ if (!entry_addr_set)
+ entry_addr = entry_address;
+ if (!length_set) {
+ length = load_address_end - load_address;
+ length_set = true;
+ } else if (defaults_assumed && !img_size_set) {
+ /* We got length from the FIS table, so the size of the
+ actual loaded image becomes img_size */
+ img_size = load_address_end - load_address;
+ img_size_set = true;
+ }
}
// Get the remaining fall-back values from the fis
if (img) {
- if (!exec_addr_set) {
- // Preserve "normal" behaviour
- exec_addr_set = true;
- exec_addr = flash_addr_set ? flash_addr : mem_addr;
- }
- if (!flash_addr_set) {
- flash_addr_set = true;
- flash_addr = img->flash_base;
- defaults_assumed = true;
- }
+ if (!exec_addr_set) {
+ // Preserve "normal" behaviour
+ exec_addr_set = true;
+ exec_addr = flash_addr_set ? flash_addr : mem_addr;
+ }
+ if (!flash_addr_set) {
+ flash_addr_set = true;
+ flash_addr = img->flash_base;
+ defaults_assumed = true;
+ }
}
if ((!no_copy && !mem_addr_set) || (no_copy && !flash_addr_set) ||
- !length_set || !name) {
- fis_usage("required parameter missing");
- return;
+ !length_set || !name) {
+ fis_usage("required parameter missing");
+ return;
}
if (!img_size_set) {
- img_size = length;
+ img_size = length;
}
// 'length' is size of FLASH image, 'img_size' is actual data size
// Round up length to FLASH block size
#ifndef CYGPKG_HAL_MIPS // FIXME: compiler is b0rken
length = ((length + flash_block_size - 1) / flash_block_size) * flash_block_size;
if (length < img_size) {
- diag_printf("Invalid FLASH image size/length combination\n");
- return;
+ diag_printf("Invalid FLASH image size/length combination\n");
+ return;
}
#endif
if (flash_addr_set &&
- ((stat = flash_verify_addr((void *)flash_addr)) ||
- (stat = flash_verify_addr((void *)(flash_addr+length-1))))) {
- _show_invalid_flash_address(flash_addr, stat);
- return;
+ ((stat = flash_verify_addr((void *)flash_addr)) ||
+ (stat = flash_verify_addr((void *)(flash_addr + length - 1))))) {
+ _show_invalid_flash_address(flash_addr, stat);
+ return;
}
- if (flash_addr_set && ((flash_addr & (flash_block_size-1)) != 0)) {
- diag_printf("Invalid FLASH address: %p\n", (void *)flash_addr);
- diag_printf(" must be 0x%x aligned\n", flash_block_size);
- return;
+ if (flash_addr_set && ((flash_addr & (flash_block_size - 1)) != 0)) {
+ diag_printf("Invalid FLASH address: %p\n", (void *)flash_addr);
+ diag_printf(" must be 0x%x aligned\n", flash_block_size);
+ return;
}
- if (strlen(name) >= sizeof(img->name)) {
- diag_printf("Name is too long, must be less than %d chars\n", (int)sizeof(img->name));
- return;
+ if (strlen(name) >= sizeof(img->u.name)) {
+ diag_printf("Name is too long, must be less than %d chars\n", sizeof(img->u.name));
+ return;
}
if (!no_copy) {
- if ((mem_addr < (CYG_ADDRESS)ram_start) ||
- ((mem_addr+img_size) >= (CYG_ADDRESS)ram_end)) {
- diag_printf("** WARNING: RAM address: %p may be invalid\n", (void *)mem_addr);
- diag_printf(" valid range is %p-%p\n", (void *)ram_start, (void *)ram_end);
- }
- if (!flash_addr_set && !fis_find_free(&flash_addr, length)) {
- diag_printf("Can't locate %lx(%ld) bytes free in FLASH\n", length, length);
- return;
- }
+ if ((mem_addr < (CYG_ADDRESS)ram_start) ||
+ ((mem_addr+img_size) >= (CYG_ADDRESS)ram_end)) {
+ diag_printf("** WARNING: RAM address: %p may be invalid\n", (void *)mem_addr);
+ diag_printf(" valid range is %p-%p\n", (void *)ram_start, (void *)ram_end);
+ }
+ if (!flash_addr_set && !fis_find_free(&flash_addr, length)) {
+ diag_printf("Can't locate %lx(%ld) bytes free in FLASH\n", length, length);
+ return;
+ }
}
// First, see if the image by this name has agreable properties
if (img) {
- if (flash_addr_set && (img->flash_base != flash_addr)) {
- diag_printf("Image found, but flash address (%p)\n"
- " is incorrect (present image location %p)\n",
- (void*)flash_addr, (void*)img->flash_base);
-
- return;
- }
- if (img->size != length) {
- diag_printf("Image found, but length (0x%lx, necessitating image size 0x%lx)\n"
- " is incorrect (present image size 0x%lx)\n",
- img_size, length, img->size);
- return;
- }
- if (!verify_action("An image named '%s' exists", name)) {
- return;
- } else {
- if (defaults_assumed) {
- if (no_copy &&
- !verify_action("* CAUTION * about to program '%s'\n at %p..%p from %p",
- name, (void *)flash_addr, (void *)(flash_addr+img_size-1),
- (void *)mem_addr)) {
- return; // The guy gave up
- }
- }
- }
+ if (flash_addr_set && (img->flash_base != flash_addr)) {
+ diag_printf("Image found, but flash address (%p)\n"
+ " is incorrect (present image location %p)\n",
+ (void *)flash_addr, (void *)img->flash_base);
+
+ return;
+ }
+ if (img->size != length) {
+ diag_printf("Image found, but length (0x%lx, necessitating image size 0x%lx)\n"
+ " is incorrect (present image size 0x%lx)\n",
+ img_size, length, img->size);
+ return;
+ }
+ if (!verify_action("An image named '%s' exists", name)) {
+ return;
+ } else {
+ if (defaults_assumed) {
+ if (no_copy &&
+ !verify_action("* CAUTION * about to program '%s'\n at %p..%p from %p",
+ name, (void *)flash_addr, (void *)(flash_addr+img_size-1),
+ (void *)mem_addr)) {
+ return; // The guy gave up
+ }
+ }
+ }
} else {
#ifdef CYGDAT_REDBOOT_FIS_MAX_FREE_CHUNKS
- // Make sure that any FLASH address specified directly is truly free
- if (flash_addr_set && !no_copy) {
- struct free_chunk chunks[CYGDAT_REDBOOT_FIS_MAX_FREE_CHUNKS];
- int idx, num_chunks;
- bool is_free = false;
-
- num_chunks = find_free(chunks);
- for (idx = 0; idx < num_chunks; idx++) {
- if ((flash_addr >= chunks[idx].start) &&
- ((flash_addr+length-1) <= chunks[idx].end)) {
- is_free = true;
- }
- }
- if (!is_free) {
- diag_printf("Invalid FLASH address - not free!\n");
- return;
- }
- }
-#endif
- // If not image by that name, try and find an empty slot
- img = (struct fis_image_desc *)fis_work_block;
- for (i = 0; i < fisdir_size/sizeof(*img); i++, img++) {
- if (img->name[0] == (unsigned char)0xFF) {
- break;
- }
- }
- if (i >= fisdir_size/sizeof(*img)) {
- diag_printf("Can't find an empty slot in FIS directory!\n");
- return;
+ // Make sure that any FLASH address specified directly is truly free
+ if (flash_addr_set && !no_copy) {
+ struct free_chunk chunks[CYGDAT_REDBOOT_FIS_MAX_FREE_CHUNKS];
+ int idx, num_chunks;
+ bool is_free = false;
+
+ num_chunks = find_free(chunks);
+ for (idx = 0; idx < num_chunks; idx++) {
+ if ((flash_addr >= chunks[idx].start) &&
+ ((flash_addr+length-1) <= chunks[idx].end)) {
+ is_free = true;
+ }
+ }
+ if (!is_free) {
+ diag_printf("Invalid FLASH address - not free!\n");
+ return;
+ }
}
+#endif
+ // If not image by that name, try and find an empty slot
+ img = fis_work_block;
+ for (i = 0; i < fisdir_size/sizeof(*img); i++, img++) {
+ if (img->u.name[0] == 0xFF) {
+ break;
+ }
+ }
+ if (i >= fisdir_size/sizeof(*img)) {
+ diag_printf("Can't find an empty slot in FIS directory!\n");
+ return;
+ }
}
if (!no_copy) {
- // Safety check - make sure the address range is not within the code we're running
- if (flash_code_overlaps((void *)flash_addr, (void *)(flash_addr+img_size-1))) {
- diag_printf("Can't program this region - contains code in use!\n");
- return;
- }
- if (prog_ok) {
- // Erase area to be programmed
- if ((stat = flash_erase((void *)flash_addr, length, (void **)&err_addr)) != 0) {
- diag_printf("Can't erase region at %p: %s\n", err_addr, flash_errmsg(stat));
- prog_ok = false;
- }
- }
- if (prog_ok) {
- // Now program it
- if ((stat = FLASH_PROGRAM((void *)flash_addr, (void *)mem_addr, img_size, (void **)&err_addr)) != 0) {
- diag_printf("Can't program region at %p: %s\n", err_addr, flash_errmsg(stat));
- prog_ok = false;
- }
- }
+ // Safety check - make sure the address range is not within the code we're running
+ if (flash_code_overlaps((void *)flash_addr, (void *)(flash_addr+img_size-1))) {
+ diag_printf("Can't program this region - contains code in use!\n");
+ return;
+ }
+ if (prog_ok) {
+ // Erase area to be programmed
+ if ((stat = flash_erase((void *)flash_addr, length, &err_addr)) != 0) {
+ diag_printf("Can't erase region at %p: %s\n", err_addr, flash_errmsg(stat));
+ prog_ok = false;
+ }
+ }
+ if (prog_ok) {
+ // Now program it
+ if ((stat = FLASH_PROGRAM((void *)flash_addr, (void *)mem_addr, img_size, &err_addr)) != 0) {
+ diag_printf("Can't program region at %p: %s\n", err_addr, flash_errmsg(stat));
+ prog_ok = false;
+ }
+ }
}
if (prog_ok) {
- // Update directory
- memset(img, 0, sizeof(*img));
- strcpy(img->name, name);
- img->flash_base = flash_addr;
- img->mem_base = exec_addr_set ? exec_addr : (mem_addr_set ? mem_addr : flash_addr);
- img->entry_point = entry_addr_set ? entry_addr : (CYG_ADDRESS)entry_address; // Hope it's been set
- img->size = length;
- img->data_length = img_size;
+ // Update directory
+ memset(img, 0, sizeof(*img));
+ strcpy(img->u.name, name);
+ img->flash_base = flash_addr;
+ img->mem_base = exec_addr_set ? exec_addr : (mem_addr_set ? mem_addr : flash_addr);
+ img->entry_point = entry_addr_set ? entry_addr : (CYG_ADDRESS)entry_address; // Hope it's been set
+ img->size = length;
+ img->data_length = img_size;
#ifdef CYGSEM_REDBOOT_FIS_CRC_CHECK
- if (!no_copy) {
- img->file_cksum = cyg_crc32((unsigned char *)mem_addr, img_size);
- } else {
- // No way to compute this, sorry
- img->file_cksum = 0;
- }
-#endif
- fis_update_directory();
+ if (!no_copy) {
+ img->file_cksum = cyg_crc32((unsigned char *)mem_addr, img_size);
+ } else {
+ // No way to compute this, sorry
+ img->file_cksum = 0;
+ }
+#endif
+ fis_start_update_directory(0);
+ fis_update_directory(0, 0);
}
}
void *err_addr;
struct fis_image_desc *img;
- if (!scan_opts(argc, argv, 2, 0, 0, (void *)&name, OPTION_ARG_TYPE_STR, "image name"))
- {
- fis_usage("invalid arguments");
- return;
- }
+ if (!scan_opts(argc, argv, 2, 0, 0, &name, OPTION_ARG_TYPE_STR, "image name")) {
+ fis_usage("invalid arguments");
+ return;
+ }
#ifdef CYGHWR_REDBOOT_ARM_FLASH_SIB
// FIXME: this is somewhat half-baked
arm_fis_delete(name);
img = fis_lookup(name, &i);
if (img) {
- if (i < num_reserved) {
- diag_printf("Sorry, '%s' is a reserved image and cannot be deleted\n", img->name);
- return;
- }
- if (!verify_action("Delete image '%s'", name)) {
- return;
- }
+ if (i < num_reserved) {
+ diag_printf("Sorry, '%s' is a reserved image and cannot be deleted\n", img->u.name);
+ return;
+ }
+ if (!verify_action("Delete image '%s'", name)) {
+ return;
+ }
} else {
- diag_printf("No image '%s' found\n", name);
- return;
+ diag_printf("No image '%s' found\n", name);
+ return;
}
// Erase Data blocks (free space)
- if ((stat = flash_erase((void *)img->flash_base, img->size, (void **)&err_addr)) != 0) {
- diag_printf("Error erasing at %p: %s\n", err_addr, flash_errmsg(stat));
+ if ((stat = flash_erase((void *)img->flash_base, img->size, &err_addr)) != 0) {
+ diag_printf("Error erasing at %p: %s\n", err_addr, flash_errmsg(stat));
} else {
- img->name[0] = (unsigned char)0xFF;
- fis_update_directory();
+ img->u.name[0] = 0xFF;
+ fis_start_update_directory(0);
+ fis_update_directory(0, 0);
}
}
CYG_ADDRESS mem_addr;
bool mem_addr_set = false;
bool show_cksum = false;
- struct option_info opts[3];
+ bool load_ce = false;
+ struct option_info opts[4];
#if defined(CYGSEM_REDBOOT_FIS_CRC_CHECK)
unsigned long cksum;
#endif
- int num_options;
+ int num_options = 0;
#if defined(CYGPRI_REDBOOT_ZLIB_FLASH) || defined(CYGSEM_REDBOOT_FIS_CRC_CHECK)
bool decompress = false;
#endif
void *err_addr;
- init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM,
- (void *)&mem_addr, (bool *)&mem_addr_set, "memory [load] base address");
- init_opts(&opts[1], 'c', false, OPTION_ARG_TYPE_FLG,
- (void *)&show_cksum, (bool *)0, "display checksum");
- num_options = 2;
+ init_opts(&opts[num_options++], 'b', true, OPTION_ARG_TYPE_NUM,
+ &mem_addr, &mem_addr_set, "memory [load] base address");
+ init_opts(&opts[num_options++], 'c', false, OPTION_ARG_TYPE_FLG,
+ &show_cksum, NULL, "display checksum");
+#ifdef CYGBLD_BUILD_REDBOOT_WITH_WINCE_SUPPORT
+ init_opts(&opts[num_options++], 'w', false, OPTION_ARG_TYPE_FLG,
+ &load_ce, NULL, "parse as Windows CE image");
+#endif
#ifdef CYGPRI_REDBOOT_ZLIB_FLASH
- init_opts(&opts[num_options], 'd', false, OPTION_ARG_TYPE_FLG,
- (void *)&decompress, 0, "decompress");
- num_options++;
+ init_opts(&opts[num_options++], 'd', false, OPTION_ARG_TYPE_FLG,
+ &decompress, 0, "decompress");
#endif
- CYG_ASSERT(num_options <= NUM_ELEMS(opts), "Too many options");
+ CYG_ASSERT(num_options <= num_options, "Too many options");
- if (!scan_opts(argc, argv, 2, opts, num_options, (void *)&name, OPTION_ARG_TYPE_STR, "image name"))
- {
- fis_usage("invalid arguments");
- return;
+ if (!scan_opts(argc, argv, 2, opts, num_options, &name,
+ OPTION_ARG_TYPE_STR, "image name")) {
+ fis_usage("invalid arguments");
+ return;
}
- if ((img = fis_lookup(name, NULL)) == (struct fis_image_desc *)0) {
- diag_printf("No image '%s' found\n", name);
- return;
+ if ((img = fis_lookup(name, NULL)) == NULL) {
+ diag_printf("No image '%s' found\n", name);
+ return;
}
- if (!mem_addr_set) {
- mem_addr = img->mem_base;
+ if (!mem_addr_set || load_ce) {
+ mem_addr = img->mem_base;
}
// Load image from FLASH into RAM
#ifdef CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS
if (!valid_address((void *)mem_addr)) {
- diag_printf("Not a loadable image - try using -b ADDRESS option\n");
- return;
+ if (!load_ce) {
+ diag_printf("Not a loadable image - try using -b ADDRESS option\n");
+ } else {
+ diag_printf("Not a loadable image\n");
+ }
+ return;
+ }
+#endif
+#ifdef CYGBLD_BUILD_REDBOOT_WITH_WINCE_SUPPORT
+ if (load_ce) {
+ if (mem_addr_set) {
+ diag_printf("Warning: -b argument ignored for Windows CE image\n");
+ }
+ FLASH_Enable((void *)img->flash_base, (void *)(img->flash_base + img->size));
+ if (!ce_is_bin_image((void *)img->flash_base, img->size)) {
+ diag_printf("** Error: This does not seem to be a valid Windows CE image\n");
+ return;
+ }
+ if (!ce_bin_load((void *)img->flash_base, img->size)) {
+ diag_printf("** Error: Failed to load Windows CE image\n");
+ }
+ FLASH_Disable((void *)img->flash_base, (void *)(img->flash_base + img->size));
+ // Set load address/top
+ load_address = mem_addr;
+ load_address_end = mem_addr + img->data_length;
+ return;
}
#endif
#ifdef CYGPRI_REDBOOT_ZLIB_FLASH
if (decompress) {
- int err;
- _pipe_t fis_load_pipe;
- _pipe_t* p = &fis_load_pipe;
- p->out_buf = (unsigned char*) mem_addr;
- p->out_max = p->out_size = -1;
- p->in_buf = (unsigned char*) img->flash_base;
- p->in_avail = img->data_length;
-
- err = (*_dc_init)(p);
-
- if (0 == err)
- err = (*_dc_inflate)(p);
-
- // Free used resources, do final translation of
- // error value.
- err = (*_dc_close)(p, err);
-
- if (0 != err && p->msg) {
- diag_printf("decompression error: %s\n", p->msg);
- } else {
- diag_printf("Image loaded from %p-%p\n", (unsigned char *)mem_addr, p->out_buf);
- }
-
- // Set load address/top
- load_address = mem_addr;
- load_address_end = (unsigned long)p->out_buf;
-
- // Reload fis directory
- fis_read_directory();
+ int err;
+ _pipe_t fis_load_pipe;
+ _pipe_t *p = &fis_load_pipe;
+ p->out_buf = (unsigned char*) mem_addr;
+ p->out_max = p->out_size = -1;
+ p->in_buf = (unsigned char*) img->flash_base;
+ p->in_avail = img->data_length;
+
+ err = (*_dc_init)(p);
+
+ if (0 == err)
+ err = (*_dc_inflate)(p);
+
+ // Free used resources, do final translation of
+ // error value.
+ err = (*_dc_close)(p, err);
+
+ if (0 != err && p->msg) {
+ diag_printf("decompression error: %s\n", p->msg);
+ } else {
+ diag_printf("Image loaded from %p-%p\n", (unsigned char *)mem_addr, p->out_buf);
+ }
+
+ // Set load address/top
+ load_address = mem_addr;
+ load_address_end = (unsigned long)p->out_buf;
+
+ // Reload fis directory
+ fis_read_directory();
} else // dangling block
#endif
- {
- flash_read((void *)img->flash_base, (void *)mem_addr, img->data_length, (void **)&err_addr);
-
- // Set load address/top
- load_address = mem_addr;
- load_address_end = mem_addr + img->data_length;
- }
+ {
+ if (flash_read((void *)img->flash_base, (void *)mem_addr,
+ img->data_length, &err_addr) != FLASH_ERR_OK) {
+ diag_printf("** Error: Failed to load image from flash\n");
+ return;
+ }
+
+ // Set load address/top
+ load_address = mem_addr;
+ load_address_end = mem_addr + img->data_length;
+ }
entry_address = (unsigned long)img->entry_point;
#ifdef CYGSEM_REDBOOT_FIS_CRC_CHECK
cksum = cyg_crc32((unsigned char *)mem_addr, img->data_length);
if (show_cksum) {
- diag_printf("Checksum: 0x%08lx\n", cksum);
+ diag_printf("Checksum: 0x%08lx\n", cksum);
}
// When decompressing, leave CRC checking to decompressor
if (!decompress && img->file_cksum) {
- if (cksum != img->file_cksum) {
- diag_printf("** Warning - checksum failure. stored: 0x%08lx, computed: 0x%08lx\n",
- img->file_cksum, cksum);
- entry_address = (unsigned long)NO_MEMORY;
- }
+ if (cksum != img->file_cksum) {
+ diag_printf("** Warning - checksum failure. stored: 0x%08lx, computed: 0x%08lx\n",
+ img->file_cksum, cksum);
+ entry_address = (unsigned long)NO_MEMORY;
+ }
}
#endif
+ diag_printf("image loaded 0x%08lx-0x%08lx, assumed entry at 0x%08lx\n",
+ load_address, load_address_end - 1, entry_address);
}
#endif // CYGOPT_REDBOOT_FIS
struct option_info opts[3];
bool prog_ok;
- init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM,
- (void *)&mem_addr, (bool *)&mem_addr_set, "memory base address");
- init_opts(&opts[1], 'f', true, OPTION_ARG_TYPE_NUM,
- (void *)&flash_addr, (bool *)&flash_addr_set, "FLASH memory base address");
- init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM,
- (void *)&length, (bool *)&length_set, "image length [in FLASH]");
+ init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM,
+ &mem_addr, &mem_addr_set, "memory base address");
+ init_opts(&opts[1], 'f', true, OPTION_ARG_TYPE_NUM,
+ &flash_addr, &flash_addr_set, "FLASH memory base address");
+ init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM,
+ &length, &length_set, "image length [in FLASH]");
if (!scan_opts(argc, argv, 2, opts, 3, 0, 0, 0))
- {
- fis_usage("invalid arguments");
- return;
- }
+ {
+ fis_usage("invalid arguments");
+ return;
+ }
if (!mem_addr_set || !flash_addr_set || !length_set) {
- fis_usage("required parameter missing");
- return;
+ fis_usage("required parameter missing");
+ return;
}
// Round up length to FLASH block size
length = ((length + flash_block_size - 1) / flash_block_size) * flash_block_size;
#endif
if (flash_addr_set &&
- ((stat = flash_verify_addr((void *)flash_addr)) ||
- (stat = flash_verify_addr((void *)(flash_addr+length-1))))) {
- _show_invalid_flash_address(flash_addr, stat);
- return;
+ ((stat = flash_verify_addr((void *)flash_addr)) ||
+ (stat = flash_verify_addr((void *)(flash_addr + length - 1))))) {
+ _show_invalid_flash_address(flash_addr, stat);
+ return;
}
if (flash_addr_set && flash_addr & (flash_block_size-1)) {
- diag_printf("Invalid FLASH address: %p\n", (void *)flash_addr);
- diag_printf(" must be 0x%x aligned\n", flash_block_size);
- return;
+ diag_printf("Invalid FLASH address: %p\n", (void *)flash_addr);
+ diag_printf(" must be 0x%x aligned\n", flash_block_size);
+ return;
}
if ((mem_addr < (CYG_ADDRESS)ram_start) ||
- ((mem_addr+length) >= (CYG_ADDRESS)ram_end)) {
- diag_printf("** WARNING: RAM address: %p may be invalid\n", (void *)mem_addr);
- diag_printf(" valid range is %p-%p\n", (void *)ram_start, (void *)ram_end);
+ ((mem_addr+length) >= (CYG_ADDRESS)ram_end)) {
+ diag_printf("** WARNING: RAM address: %p may be invalid\n", (void *)mem_addr);
+ diag_printf(" valid range is %p-%p\n", (void *)ram_start, (void *)ram_end);
}
// Safety check - make sure the address range is not within the code we're running
- if (flash_code_overlaps((void *)flash_addr, (void *)(flash_addr+length-1))) {
- diag_printf("Can't program this region - contains code in use!\n");
- return;
+ if (flash_code_overlaps((void *)flash_addr, (void *)(flash_addr + length - 1))) {
+ diag_printf("Can't program this region - contains code in use!\n");
+ return;
}
- if (!verify_action("* CAUTION * about to program FLASH\n at %p..%p from %p",
- (void *)flash_addr, (void *)(flash_addr+length-1),
- (void *)mem_addr)) {
- return; // The guy gave up
+ if (!verify_action("* CAUTION * about to program FLASH\n at %p..%p from %p",
+ (void *)flash_addr, (void *)(flash_addr + length - 1),
+ (void *)mem_addr)) {
+ return; // The guy gave up
}
prog_ok = true;
if (prog_ok) {
- // Erase area to be programmed
- if ((stat = flash_erase((void *)flash_addr, length, (void **)&err_addr)) != 0) {
- diag_printf("Can't erase region at %p: %s\n", err_addr, flash_errmsg(stat));
- prog_ok = false;
- }
+ // Erase area to be programmed
+ if ((stat = flash_erase((void *)flash_addr, length, &err_addr)) != 0) {
+ diag_printf("Can't erase region at %p: %s\n", err_addr, flash_errmsg(stat));
+ prog_ok = false;
+ }
}
if (prog_ok) {
- // Now program it
- if ((stat = FLASH_PROGRAM((void *)flash_addr, (void *)mem_addr, length, (void **)&err_addr)) != 0) {
- diag_printf("Can't program region at %p: %s\n", err_addr, flash_errmsg(stat));
- prog_ok = false;
- }
+ // Now program it
+ if ((stat = FLASH_PROGRAM((void *)flash_addr, (void *)mem_addr, length, &err_addr)) != 0) {
+ diag_printf("Can't program region at %p: %s\n", err_addr, flash_errmsg(stat));
+ prog_ok = false;
+ }
}
}
void *err_addr;
struct option_info opts[2];
- init_opts(&opts[0], 'f', true, OPTION_ARG_TYPE_NUM,
- (void *)&flash_addr, (bool *)&flash_addr_set, "FLASH memory base address");
- init_opts(&opts[1], 'l', true, OPTION_ARG_TYPE_NUM,
- (void *)&length, (bool *)&length_set, "length");
- if (!scan_opts(argc, argv, 2, opts, 2, (void **)0, 0, ""))
- {
- fis_usage("invalid arguments");
- return;
- }
+ init_opts(&opts[0], 'f', true, OPTION_ARG_TYPE_NUM,
+ &flash_addr, &flash_addr_set, "FLASH memory base address");
+ init_opts(&opts[1], 'l', true, OPTION_ARG_TYPE_NUM,
+ &length, &length_set, "length");
+ if (!scan_opts(argc, argv, 2, opts, 2, NULL, 0, NULL))
+ {
+ fis_usage("invalid arguments");
+ return;
+ }
if (!flash_addr_set || !length_set) {
- fis_usage("missing argument");
- return;
+ fis_usage("missing argument");
+ return;
}
if (flash_addr_set &&
- ((stat = flash_verify_addr((void *)flash_addr)) ||
- (stat = flash_verify_addr((void *)(flash_addr+length-1))))) {
- _show_invalid_flash_address(flash_addr, stat);
- return;
+ ((stat = flash_verify_addr((void *)flash_addr)) ||
+ (stat = flash_verify_addr((void *)(flash_addr + length - 1))))) {
+ _show_invalid_flash_address(flash_addr, stat);
+ return;
}
if (flash_addr_set && flash_addr & (flash_block_size-1)) {
- diag_printf("Invalid FLASH address: %p\n", (void *)flash_addr);
- diag_printf(" must be 0x%x aligned\n", flash_block_size);
- return;
+ diag_printf("Invalid FLASH address: %p\n", (void *)flash_addr);
+ diag_printf(" must be 0x%x aligned\n", flash_block_size);
+ return;
}
// Safety check - make sure the address range is not within the code we're running
- if (flash_code_overlaps((void *)flash_addr, (void *)(flash_addr+length-1))) {
- diag_printf("Can't erase this region - contains code in use!\n");
- return;
+ if (flash_code_overlaps((void *)flash_addr, (void *)(flash_addr + length - 1))) {
+ diag_printf("Can't erase this region - contains code in use!\n");
+ return;
}
- if ((stat = flash_erase((void *)flash_addr, length, (void **)&err_addr)) != 0) {
- diag_printf("Error erasing at %p: %s\n", err_addr, flash_errmsg(stat));
+ if ((stat = flash_erase((void *)flash_addr, length, &err_addr)) != 0) {
+ diag_printf("Error erasing at %p: %s\n", err_addr, flash_errmsg(stat));
}
}
void *err_addr;
struct option_info opts[2];
- init_opts(&opts[0], 'f', true, OPTION_ARG_TYPE_NUM,
- (void *)&flash_addr, (bool *)&flash_addr_set, "FLASH memory base address");
- init_opts(&opts[1], 'l', true, OPTION_ARG_TYPE_NUM,
- (void *)&length, (bool *)&length_set, "length");
+ init_opts(&opts[0], 'f', true, OPTION_ARG_TYPE_NUM,
+ &flash_addr, &flash_addr_set, "FLASH memory base address");
+ init_opts(&opts[1], 'l', true, OPTION_ARG_TYPE_NUM,
+ &length, &length_set, "length");
if (!scan_opts(argc, argv, 2, opts, 2, &name, OPTION_ARG_TYPE_STR, "image name"))
- {
- fis_usage("invalid arguments");
- return;
- }
-
+ {
+ fis_usage("invalid arguments");
+ return;
+ }
+#ifdef CYGOPT_REDBOOT_FIS
/* Get parameters from image if specified */
if (name) {
- struct fis_image_desc *img;
- if ((img = fis_lookup(name, NULL)) == (struct fis_image_desc *)0) {
- diag_printf("No image '%s' found\n", name);
- return;
- }
-
- flash_addr = img->flash_base;
- length = img->size;
- } else if (!flash_addr_set || !length_set) {
- fis_usage("missing argument");
- return;
- }
+ struct fis_image_desc *img;
+ if ((img = fis_lookup(name, NULL)) == NULL) {
+ diag_printf("No image '%s' found\n", name);
+ return;
+ }
+
+ flash_addr = img->flash_base;
+ length = img->size;
+ } else
+#endif
+ if (!flash_addr_set || !length_set) {
+ fis_usage("missing argument");
+ return;
+ }
if (flash_addr_set &&
- ((stat = flash_verify_addr((void *)flash_addr)) ||
- (stat = flash_verify_addr((void *)(flash_addr+length-1))))) {
- _show_invalid_flash_address(flash_addr, stat);
- return;
+ ((stat = flash_verify_addr((void *)flash_addr)) ||
+ (stat = flash_verify_addr((void *)(flash_addr + length - 1))))) {
+ _show_invalid_flash_address(flash_addr, stat);
+ return;
}
- if ((stat = flash_lock((void *)flash_addr, length, (void **)&err_addr)) != 0) {
- diag_printf("Error locking at %p: %s\n", err_addr, flash_errmsg(stat));
+ if ((stat = flash_lock((void *)flash_addr, length, &err_addr)) != 0) {
+ diag_printf("Error locking at %p: %s\n", err_addr, flash_errmsg(stat));
}
}
void *err_addr;
struct option_info opts[2];
- init_opts(&opts[0], 'f', true, OPTION_ARG_TYPE_NUM,
- (void *)&flash_addr, (bool *)&flash_addr_set, "FLASH memory base address");
- init_opts(&opts[1], 'l', true, OPTION_ARG_TYPE_NUM,
- (void *)&length, (bool *)&length_set, "length");
+ init_opts(&opts[0], 'f', true, OPTION_ARG_TYPE_NUM,
+ &flash_addr, &flash_addr_set, "FLASH memory base address");
+ init_opts(&opts[1], 'l', true, OPTION_ARG_TYPE_NUM,
+ &length, &length_set, "length");
if (!scan_opts(argc, argv, 2, opts, 2, &name, OPTION_ARG_TYPE_STR, "image name"))
- {
- fis_usage("invalid arguments");
- return;
- }
-
+ {
+ fis_usage("invalid arguments");
+ return;
+ }
+#ifdef CYGOPT_REDBOOT_FIS
if (name) {
- struct fis_image_desc *img;
- if ((img = fis_lookup(name, NULL)) == (struct fis_image_desc *)0) {
- diag_printf("No image '%s' found\n", name);
- return;
- }
-
- flash_addr = img->flash_base;
- length = img->size;
- } else if (!flash_addr_set || !length_set) {
- fis_usage("missing argument");
- return;
- }
+ struct fis_image_desc *img;
+ if ((img = fis_lookup(name, NULL)) == NULL) {
+ diag_printf("No image '%s' found\n", name);
+ return;
+ }
+
+ flash_addr = img->flash_base;
+ length = img->size;
+ } else
+#endif
+ if (!flash_addr_set || !length_set) {
+ fis_usage("missing argument");
+ return;
+ }
if (flash_addr_set &&
- ((stat = flash_verify_addr((void *)flash_addr)) ||
- (stat = flash_verify_addr((void *)(flash_addr+length-1))))) {
- _show_invalid_flash_address(flash_addr, stat);
- return;
+ ((stat = flash_verify_addr((void *)flash_addr)) ||
+ (stat = flash_verify_addr((void *)(flash_addr + length - 1))))) {
+ _show_invalid_flash_address(flash_addr, stat);
+ return;
}
- if ((stat = flash_unlock((void *)flash_addr, length, (void **)&err_addr)) != 0) {
- diag_printf("Error unlocking at %p: %s\n", err_addr, flash_errmsg(stat));
+ if ((stat = flash_unlock((void *)flash_addr, length, &err_addr)) != 0) {
+ diag_printf("Error unlocking at %p: %s\n", err_addr, flash_errmsg(stat));
}
}
#endif
_flash_info(void)
{
if (!__flash_init) return;
- diag_printf("FLASH: %p - 0x%x, %d blocks of %p bytes each.\n",
- flash_start, (CYG_ADDRWORD)flash_end + 1, flash_num_blocks, (void *)flash_block_size);
+ diag_printf("FLASH: %p - 0x%x, %d blocks of 0x%08x bytes each.\n",
+ flash_start, (CYG_ADDRWORD)flash_end + 1, flash_num_blocks, flash_block_size);
}
-bool
+/* Returns -1 on failure, 0 on success, 1 if it was successfull
+ but a failed fis update was detected */
+int
do_flash_init(void)
{
- int stat;
-
- if (!__flash_init) {
- __flash_init = 1;
- if ((stat = flash_init(diag_printf)) != 0) {
- diag_printf("FLASH: driver init failed: %s\n", flash_errmsg(stat));
- return false;
- }
- flash_get_limits((void *)0, (void **)&flash_start, (void **)&flash_end);
- // Keep 'end' address as last valid location, to avoid wrap around problems
- flash_end = (void *)((CYG_ADDRESS)flash_end - 1);
- flash_get_block_info(&flash_block_size, &flash_num_blocks);
+ int stat;
+
+#ifdef CYGOPT_REDBOOT_REDUNDANT_FIS
+ struct fis_image_desc img0;
+ struct fis_image_desc img1;
+ int fis_update_was_interrupted = 0;
+ void *err_addr;
+
+ //check the size of fis_valid_info
+ CYG_ASSERT((sizeof(struct fis_valid_info) <= sizeof(img0.u.name)),
+ "fis_valid_info size mismatch");
+ //try to check the alignment of version_count
+ CYG_ASSERT(((&img0.u.valid_info.version_count - &img0) % sizeof(unsigned long) == 0),
+ "alignment problem");
+#endif
+ if (!__flash_init) {
+ __flash_init = 1;
+ if ((stat = flash_init(diag_printf)) != 0) {
+ diag_printf("FLASH: driver init failed: %s\n", flash_errmsg(stat));
+ return -1;
+ }
+ flash_get_limits(NULL, &flash_start, &flash_end);
+ // Keep 'end' address as last valid location, to avoid wrap around problems
+ flash_end = (void *)((CYG_ADDRESS)flash_end - 1);
+ flash_get_block_info(&flash_block_size, &flash_num_blocks);
#ifdef CYGOPT_REDBOOT_FIS
- fisdir_size = CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_COUNT * CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_SIZE;
- fisdir_size = ((fisdir_size + flash_block_size - 1) / flash_block_size) * flash_block_size;
+ fisdir_size = CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_COUNT * CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_SIZE;
+ fisdir_size = ((fisdir_size + flash_block_size - 1) / flash_block_size) * flash_block_size;
# if defined(CYGPRI_REDBOOT_ZLIB_FLASH) && defined(CYGOPT_REDBOOT_FIS_ZLIB_COMMON_BUFFER)
- fis_work_block = fis_zlib_common_buffer;
- if(CYGNUM_REDBOOT_FIS_ZLIB_COMMON_BUFFER_SIZE < fisdir_size) {
- diag_printf("FLASH: common buffer too small\n");
- return false;
- }
+ fis_work_block = fis_zlib_common_buffer;
+ if (CYGNUM_REDBOOT_FIS_ZLIB_COMMON_BUFFER_SIZE < fisdir_size) {
+ diag_printf("FLASH: common buffer too small\n");
+ return -1;
+ }
# else
- workspace_end = (unsigned char *)(workspace_end-fisdir_size);
- fis_work_block = workspace_end;
+ workspace_end = (unsigned char *)(workspace_end - fisdir_size);
+ fis_work_block = workspace_end;
# endif
- if (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK < 0) {
- fis_addr = (void *)((CYG_ADDRESS)flash_end + 1 +
- (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK*flash_block_size));
- } else {
- fis_addr = (void *)((CYG_ADDRESS)flash_start +
- (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK*flash_block_size));
- }
- if (((CYG_ADDRESS)fis_addr + fisdir_size - 1) > (CYG_ADDRESS)flash_end) {
- diag_printf("FIS directory doesn't fit\n");
- return false;
- }
- fis_read_directory();
+ if (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK < 0) {
+ fis_addr = (void *)((CYG_ADDRESS)flash_end + 1 +
+ (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK * flash_block_size));
+ } else {
+ fis_addr = (void *)((CYG_ADDRESS)flash_start +
+ (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK * flash_block_size));
+ }
+#if defined(CYGHWR_DEVS_FLASH_MXC_MULTI) && defined(MXCFLASH_SELECT_NAND)
+ extern int mxc_nand_fis_start(void);
+ if (IS_FIS_FROM_NAND()) {
+ fis_addr = (void *)((CYG_ADDRESS)flash_start + mxc_nand_fis_start());
+ }
+#endif
+
+#if defined(IMXFLASH_SELECT_SPI_NOR)
+ extern int mxc_spi_nor_fis_start(void);
+ if (IS_FIS_FROM_SPI_NOR()) {
+ fis_addr = (void *)((CYG_ADDRESS)flash_start + mxc_spi_nor_fis_start());
+ }
+#endif
+
+#if defined(MXCFLASH_SELECT_MMC)
+ if (IS_FIS_FROM_MMC()) {
+ fis_addr = (void *)REDBOOT_IMAGE_SIZE;
+ }
+#endif
+
+ if (((CYG_ADDRESS)fis_addr + fisdir_size - 1) > (CYG_ADDRESS)flash_end) {
+ diag_printf("FIS directory doesn't fit\n");
+ return -1;
+ }
+#ifdef CYGOPT_REDBOOT_REDUNDANT_FIS
+
+ if (CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK < 0) {
+ redundant_fis_addr = (void *)((CYG_ADDRESS)flash_end + 1 +
+ (CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK *
+ flash_block_size));
+ } else {
+ redundant_fis_addr = (void *)((CYG_ADDRESS)flash_start +
+ (CYGNUM_REDBOOT_FIS_REDUNDANT_DIRECTORY_BLOCK *
+ flash_block_size));
+ }
+
+ if (((CYG_ADDRESS)redundant_fis_addr + fisdir_size - 1) > (CYG_ADDRESS)flash_end) {
+ diag_printf("Redundant FIS directory doesn't fit\n");
+ return -1;
+ }
+ FLASH_READ(fis_addr, &img0, sizeof(img0), &err_addr);
+ FLASH_READ(redundant_fis_addr, &img1, sizeof(img1), &err_addr);
+
+ if (strncmp(img0.u.valid_info.magic_name, CYG_REDBOOT_RFIS_VALID_MAGIC,
+ CYG_REDBOOT_RFIS_VALID_MAGIC_LENGTH) != 0) {
+ memset(&img0, 0, sizeof(img0));
+ }
+
+ if (strncmp(img1.u.valid_info.magic_name, CYG_REDBOOT_RFIS_VALID_MAGIC,
+ CYG_REDBOOT_RFIS_VALID_MAGIC_LENGTH) != 0) {
+ memset(&img1, 0, sizeof(img0));
+ }
+
+#ifdef REDBOOT_FLASH_REVERSE_BYTEORDER
+ img0.u.valid_info.version_count = CYG_SWAP32(img0.u.valid_info.version_count);
+ img1.u.valid_info.version_count = CYG_SWAP32(img1.u.valid_info.version_count);
+#endif
+
+ if (fis_get_valid_buf(&img0, &img1, &fis_update_was_interrupted) == 1) {
+ // Valid, so swap primary and secondary
+ void *tmp;
+ tmp = fis_addr;
+ fis_addr = redundant_fis_addr;
+ redundant_fis_addr = tmp;
+ }
+#endif
+ fis_read_directory();
+#endif
+ }
+#ifdef CYGOPT_REDBOOT_REDUNDANT_FIS
+ if (fis_update_was_interrupted)
+ return 1;
+ else
+ return 0;
+#else
+ return 0;
#endif
- }
- return true;
}
// Wrapper to avoid compiler warnings
struct cmd *cmd;
if (argc < 2) {
- fis_usage("too few arguments");
- return;
+ fis_usage("too few arguments");
+ return;
}
- if (!do_flash_init()) {
- diag_printf("Sorry, no FLASH memory is available\n");
- return;
+ if (do_flash_init() < 0) {
+ diag_printf("Sorry, no FLASH memory is available\n");
+ return;
}
- if ((cmd = cmd_search(__FIS_cmds_TAB__, &__FIS_cmds_TAB_END__,
- argv[1])) != (struct cmd *)0) {
- (cmd->fun)(argc, argv);
- return;
+ if ((cmd = cmd_search(__FIS_cmds_TAB__, &__FIS_cmds_TAB_END__,
+ argv[1])) != NULL) {
+ (cmd->fun)(argc, argv);
+ return;
}
fis_usage("unrecognized command");
}
-
-// EOF flash.c
// Author(s): Oliver Munz
// Contributors: om, asl
// Date: 2006-02-21
-// Purpose:
-// Description:
-//
+// Purpose:
+// Description:
+//
// This code is part of RedBoot (tm).
//
//####DESCRIPTIONEND####
static int flash_block_size;
-static cyg_uint8 * current_flash_page;
+static cyg_uint8 *current_flash_page;
/* Allocation of the flash-sector size RAM-buffer is done */
-static bool init_done = false;
+static bool init_done = false;
/* We have initialized the current page ready for writing */
-static bool flash_page_init = false;
+static bool flash_page_init = false;
static cyg_uint8 *flash_buffer;
// If the io flash code outputs when erasing/writing it will upset the
// download over the communications channel. So we install a dummy
// print function.
-static int dummy_printf(const char *fmt, ...){
- return 0;
+static int dummy_printf(const char *fmt, ...)
+{
+ return 0;
}
// Calculate the address of the first byte in a flash block
-static cyg_uint8 * flash_block_begin(cyg_uint32 addr)
+static cyg_uint8 *flash_block_begin(cyg_uint32 addr)
{
- return (cyg_uint8 *)
- ((addr / flash_block_size) * flash_block_size);
+ return (cyg_uint8 *)
+ ((addr / flash_block_size) * flash_block_size);
}
// Initialize the loading process
void flash_load_start(void)
{
- flash_init(dummy_printf);
-
- init_done = true;
- flash_page_init = false;
+ flash_init(dummy_printf);
+
+ init_done = true;
+ flash_page_init = false;
}
// Write a byte into flash. We maintain a copy in RAM of the FLASH
// or the flash_load_finish function is called.
void flash_load_write(cyg_uint8 *flash_addr, cyg_uint8 value)
{
-
- cyg_uint32 retcode = FLASH_ERR_OK;
- void * err_addr;
- cyg_uint32 addr = (cyg_uint32)flash_addr;
- cyg_uint32 offset;
-
- if (!flash_page_init) {
- /* First Byte for the current flash block. Read the current contents */
- current_flash_page = flash_block_begin(addr);
- flash_read(flash_buffer, current_flash_page, flash_block_size, &err_addr);
- flash_page_init = true;
- }
- if (flash_block_begin(addr) != current_flash_page) {
- /* We have moved into the next flash page. Write the current
- page so we can move on */
- retcode = flash_erase(current_flash_page, flash_block_size, &err_addr);
- if (retcode != FLASH_ERR_OK){ /* Flash ERROR */
- diag_printf("Error erase at %p: %s\n", err_addr, flash_errmsg(retcode));
- return;
- }
-
- retcode = flash_program(current_flash_page, flash_buffer,
- flash_block_size, &err_addr);
- if (retcode != FLASH_ERR_OK){
- diag_printf("Error writing at %p: %s\n",
- err_addr, flash_errmsg(retcode));
- return;
- }
- current_flash_page = flash_block_begin(addr);
- flash_read(flash_buffer, current_flash_page, flash_block_size, &err_addr);
- }
-
- offset = flash_addr - current_flash_page;
- CYG_ASSERT(offset < flash_block_size, "offset not inside flash block");
-
- flash_buffer[offset] = value;
+
+ cyg_uint32 retcode = FLASH_ERR_OK;
+ void *err_addr;
+ cyg_uint32 addr = (cyg_uint32)flash_addr;
+ cyg_uint32 offset;
+
+ if (!flash_page_init) {
+ /* First Byte for the current flash block. Read the current contents */
+ current_flash_page = flash_block_begin(addr);
+ flash_read(flash_buffer, current_flash_page, flash_block_size, &err_addr);
+ flash_page_init = true;
+ }
+ if (flash_block_begin(addr) != current_flash_page) {
+ /* We have moved into the next flash page. Write the current
+ page so we can move on */
+ retcode = flash_erase(current_flash_page, flash_block_size, &err_addr);
+ if (retcode != FLASH_ERR_OK){ /* Flash ERROR */
+ diag_printf("Error erase at %p: %s\n", err_addr, flash_errmsg(retcode));
+ return;
+ }
+
+ retcode = flash_program(current_flash_page, flash_buffer,
+ flash_block_size, &err_addr);
+ if (retcode != FLASH_ERR_OK){
+ diag_printf("Error writing at %p: %s\n",
+ err_addr, flash_errmsg(retcode));
+ return;
+ }
+ current_flash_page = flash_block_begin(addr);
+ flash_read(flash_buffer, current_flash_page, flash_block_size, &err_addr);
+ }
+
+ offset = flash_addr - current_flash_page;
+ CYG_ASSERT(offset < flash_block_size, "offset not inside flash block");
+
+ flash_buffer[offset] = value;
}
// Program the current page into flash.
void flash_load_finish(void)
{
- cyg_uint32 retcode = FLASH_ERR_OK;
- void * err_addr;
-
- if (init_done && flash_page_init) {
- flash_page_init = false;
-
- retcode = flash_erase(current_flash_page, flash_block_size, &err_addr);
- if (retcode != FLASH_ERR_OK){
- diag_printf("Error erase at %p: %s\n", err_addr, flash_errmsg(retcode));
- } else {
- retcode = flash_program(current_flash_page, flash_buffer,
- flash_block_size, &err_addr);
- if (retcode != FLASH_ERR_OK){
- diag_printf("Error writing at %p: %s\n",
- err_addr, flash_errmsg(retcode));
- }
- }
- }
- flash_init(diag_printf);
+ cyg_uint32 retcode = FLASH_ERR_OK;
+ void *err_addr;
+
+ if (init_done && flash_page_init) {
+ flash_page_init = false;
+
+ retcode = flash_erase(current_flash_page, flash_block_size, &err_addr);
+ if (retcode != FLASH_ERR_OK){
+ diag_printf("Error erase at %p: %s\n", err_addr, flash_errmsg(retcode));
+ } else {
+ retcode = flash_program(current_flash_page, flash_buffer,
+ flash_block_size, &err_addr);
+ if (retcode != FLASH_ERR_OK){
+ diag_printf("Error writing at %p: %s\n",
+ err_addr, flash_errmsg(retcode));
+ }
+ }
+ }
+ flash_init(diag_printf);
}
// This is called during redboot start up. We allocate a buffer the
void
flash_load_init(void)
{
- int flash_blocks;
+ int flash_blocks;
- flash_get_block_info(&flash_block_size, &flash_blocks);
- workspace_end -= flash_block_size;
-
- flash_buffer = workspace_end;
+ flash_get_block_info(&flash_block_size, &flash_blocks);
+ workspace_end -= flash_block_size;
+
+ flash_buffer = workspace_end;
}
// Register this initialization function in the table
RedBoot_init(flash_load_init, RedBoot_INIT_LAST);
-
-
-
{
int sb_block = 1;
cyg_uint32 sb_buf[E2FS_MIN_BLOCK_SIZE/sizeof(cyg_uint32)];
- struct e2fs_super_block *sb = (struct e2fs_super_block *)sb_buf;
+ struct e2fs_super_block *sb = (struct e2fs_super_block *)((void *)sb_buf);
e2fs->part = part;
if (!PARTITION_READ(part, sb_block*(E2FS_MIN_BLOCK_SIZE/SECTOR_SIZE),
- (cyg_uint32 *)sb, E2FS_MIN_BLOCK_SIZE/SECTOR_SIZE))
+ sb_buf, E2FS_MIN_BLOCK_SIZE/SECTOR_SIZE))
return -1;
if (SWAB_LE16(sb->magic) != E2FS_SUPER_MAGIC) {
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2002, 2003, 2004 Gary Thomas
+// Copyright (C) 2004, 2005, 2006 eCosCentric Limited.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
-// Author(s): dwmw2, msalter
-// Date: 2003-11-27
+// Author(s): nickg
+// Contributors: dwmw2, msalter
+// Date: 2004-11-21
// Purpose:
// Description:
//
#include <unistd.h>
#include <string.h>
#ifdef CYGPKG_IO_FLASH
+#include <pkgconf/io_flash.h>
#include <cyg/io/io.h>
#include <cyg/io/flash.h>
#include <cyg/io/config_keys.h>
#endif
+#include <cyg/io/devtab.h>
#include <cyg/fileio/fileio.h>
#include <cyg/infra/cyg_ass.h> // assertion macros
+//==========================================================================
+
+// Define table boundaries
+CYG_HAL_TABLE_BEGIN( __FS_cmds_TAB__, FS_cmds);
+CYG_HAL_TABLE_END( __FS_cmds_TAB_END__, FS_cmds);
+
+extern struct cmd __FS_cmds_TAB__[], __FS_cmds_TAB_END__;
+
+//==========================================================================
+
+static void
+fs_usage(char *why)
+{
+ diag_printf("*** invalid 'fs' command: %s\n", why);
+ cmd_usage(__FS_cmds_TAB__, &__FS_cmds_TAB_END__, "fs ");
+}
+
+
+//==========================================================================
+
+#define MAX_MOUNTS 4
+
+static int mount_count = 0;
+
+static struct
+{
+ char dev_str[PATH_MAX];
+ char mp_str[PATH_MAX];
+ char type_str[PATH_MAX];
+} mounts[MAX_MOUNTS];
+
+//==========================================================================
+
static void do_mount(int argc, char *argv[]);
static void do_umount(int argc, char *argv[]);
-#ifdef CYGPKG_IO_FLASH_BLOCK_DEVICE
+/* Temporary hack until flashv2 merged to trunk. We can't tell whether we're
+ * working with flash v1 or v2 from the package version. So if legacy device isn't
+ * defined we check whether, if there is a block device, there's a tell-tale define
+ * that only exists with the v1 version.
+ */
+#if !defined(CYGPKG_IO_FLASH_BLOCK_DEVICE_LEGACY) && \
+ defined(CYGPKG_IO_FLASH_BLOCK_DEVICE) && \
+ defined(CYGINT_IO_FLASH_BLOCK_CFG_1)
+# define CYGPKG_IO_FLASH_BLOCK_DEVICE_LEGACY 1
+#endif
+
+#ifdef CYGPKG_IO_FLASH_BLOCK_DEVICE_LEGACY
#define FLASHPART "[-f <partition>] "
#else
#define FLASHPART
#endif
-RedBoot_cmd("mount",
- "Mount file system",
- FLASHPART "[-d <device>] -t fstype",
- do_mount
+local_cmd_entry("mount",
+ "Mount file system",
+ FLASHPART "[-d <device>] -t <fstype> [<mountpoint>]",
+ do_mount,
+ FS_cmds
);
-RedBoot_cmd("umount",
- "Unmount file system",
- "",
- do_umount
+local_cmd_entry("umount",
+ "Unmount file system",
+ "<mountpoint>",
+ do_umount,
+ FS_cmds
);
-int fileio_mounted = 0;
+//==========================================================================
// Mount disk/filesystem
static void
do_mount(int argc, char *argv[])
{
- char *part_str, *dev_str, *type_str;
- bool part_set = false, dev_set = false, type_set = false;
+ char *dev_str = "<undefined>", *type_str, *mp_str;
+ bool dev_set = false, type_set = false;
struct option_info opts[3];
int err, num_opts = 2;
+ int i,m=0; /* Set to 0 to silence warning */
+#ifdef CYGPKG_IO_FLASH_BLOCK_DEVICE_LEGACY
+ char *part_str;
+ bool part_set = false;
+#endif
init_opts(&opts[0], 'd', true, OPTION_ARG_TYPE_STR,
(void *)&dev_str, &dev_set, "device");
init_opts(&opts[1], 't', true, OPTION_ARG_TYPE_STR,
(void *)&type_str, &type_set, "fstype");
-#ifdef CYGPKG_IO_FLASH_BLOCK_DEVICE
+#ifdef CYGPKG_IO_FLASH_BLOCK_DEVICE_LEGACY
init_opts(&opts[2], 'f', true, OPTION_ARG_TYPE_STR,
(void *)&part_str, &part_set, "partition");
num_opts++;
CYG_ASSERT(num_opts <= NUM_ELEMS(opts), "Too many options");
- if (!scan_opts(argc, argv, 1, opts, num_opts, NULL, 0, NULL))
+ if (!scan_opts(argc, argv, 1, opts, num_opts, &mp_str, OPTION_ARG_TYPE_STR, "mountpoint"))
return;
if (!type_set) {
- diag_printf("Must specify file system type\n");
+ err_printf("fs mount: Must specify file system type\n");
return;
}
- if (fileio_mounted) {
- diag_printf("A file system is already mounted\n");
+
+ if( mp_str == 0 )
+ mp_str = "/";
+
+ if( mount_count >= MAX_MOUNTS )
+ {
+ err_printf("fs mount: Maximum number of mounts exceeded\n");
return;
}
-#ifdef CYGPKG_IO_FLASH_BLOCK_DEVICE
+
+#ifdef CYGPKG_IO_FLASH_BLOCK_DEVICE_LEGACY
if (part_set) {
- int len;
+ cyg_uint32 len;
cyg_io_handle_t h;
if (dev_set && strcmp(dev_str, CYGDAT_IO_FLASH_BLOCK_DEVICE_NAME_1)) {
-
diag_printf("May only set one of <device> or <partition>\n");
+
err_printf("fs mount: May only set one of <device> or <partition>\n");
return;
}
dev_str = CYGDAT_IO_FLASH_BLOCK_DEVICE_NAME_1;
- len = strlen(part_str);
+ len = (cyg_uint32)strlen(part_str);
err = cyg_io_lookup(dev_str, &h);
if (err < 0) {
- diag_printf("cyg_io_lookup of \"%s\" returned %d\n", err);
+ err_printf("fs mount: cyg_io_lookup of \"%s\" returned %d\n", dev_str, err);
return;
}
err = cyg_io_set_config(h, CYG_IO_SET_CONFIG_FLASH_FIS_NAME,
part_str, &len);
if (err < 0) {
- diag_printf("FIS partition \"%s\" not found\n",
+ diag_printf("fs mount: FIS partition \"%s\" not found\n",
part_str);
return;
}
}
#endif
- err = mount(dev_str, "/", type_str);
-
- if (err) {
- diag_printf("Mount failed %d\n", err);
- } else {
-// diag_printf("Mount %s file system succeeded\n", type_str);
- fileio_mounted = 1;
-#ifdef CYGBLD_REDBOOT_FILEIO_WITH_LS
- chdir("/");
-#endif
+
+ for( i = 0; i < MAX_MOUNTS; i++ )
+ {
+ if( mounts[i].mp_str[0] != '\0' )
+ {
+ if( strcmp(mounts[i].dev_str, dev_str ) == 0 )
+ {
+ err_printf("fs mount: Device %s already mounted\n",dev_str);
+ return;
+ }
+ }
+ else
+ m = i;
+ }
+
+ strcpy( mounts[m].mp_str, mp_str );
+ strcpy( mounts[m].dev_str, dev_str );
+ strcpy( mounts[m].type_str, type_str );
+
+ err = mount(mounts[m].dev_str, mounts[m].mp_str, mounts[m].type_str);
+
+ if (err)
+ {
+ err_printf("fs mount: mount(%s,%s,%s) failed %d\n", dev_str, mp_str, type_str, errno);
+ mounts[m].mp_str[0] = '\0'; // mount failed so don't let it appear mounted
+ }
+ else
+ {
+ if( mount_count == 0 )
+ chdir( "/" );
+ mount_count++;
}
}
+//==========================================================================
+
static void
do_umount(int argc, char *argv[])
{
- if (!fileio_mounted) {
+ char *dir_str;
+ int err;
+ int i;
+
+ if( mount_count == 0 )
+ {
+ err_printf("fs: No filesystems mounted\n");
+ return;
+ }
+
+ if (!scan_opts(argc, argv, 1, NULL, 0, &dir_str, OPTION_ARG_TYPE_STR, "mountpoint"))
return;
+
+ if( dir_str == 0 )
+ dir_str = "/";
+
+ for( i = 0; i < MAX_MOUNTS; i++ )
+ {
+ if( strcmp(mounts[i].mp_str, dir_str ) == 0 )
+ break;
+ }
+
+ if( i == MAX_MOUNTS )
+ {
+ err_printf("fs unmount: unknown mountpoint %s\n",dir_str);
+ return;
+ }
+
+ err = umount (dir_str);
+
+ if (err)
+ err_printf("fs umount: unmount failed %d\n", errno);
+ else
+ {
+ mounts[i].mp_str[0] = '\0';
+ mount_count--;
+ if( mount_count == 0 )
+ chdir( "/" );
}
- umount ("/");
- fileio_mounted = 0;
+
}
-#ifdef CYGBLD_REDBOOT_FILEIO_WITH_LS
+//==========================================================================
+
#include <dirent.h>
static char rwx[8][4] = { "---", "r--", "-w-", "rw-", "--x", "r-x", "-wx", "rwx" };
static void
-do_ls(int argc, char * argv[])
+do_list(int argc, char * argv[])
{
char * dir_str;
- struct option_info opts[1];
- bool dir_set = false;
DIR *dirp;
- char cwd[PATH_MAX];
char filename[PATH_MAX];
+ char cwd[PATH_MAX];
struct stat sbuf;
int err;
-
- init_opts(&opts[0], 'd', true, OPTION_ARG_TYPE_STR,
- (void *)&dir_str, &dir_set, "directory");
-
- if (!fileio_mounted) {
- diag_printf("No filesystem mounted\n");
- return;
+
+ if( mount_count == 0 )
+ {
+ err_printf("fs: No filesystems mounted\n");
+ return;
}
- if (!scan_opts(argc, argv, 1, opts, 1, NULL, 0, NULL))
+ if (!scan_opts(argc, argv, 1, NULL, 0, &dir_str, OPTION_ARG_TYPE_STR, "directory"))
return;
- if (!dir_set) {
- getcwd(cwd,sizeof(cwd));
- dir_str = cwd;
+ if( dir_str == 0 )
+ {
+ dir_str = getcwd(cwd, sizeof(cwd));
}
- diag_printf("directory %s\n",dir_str);
dirp = opendir(dir_str);
if (dirp==NULL) {
- diag_printf("no such directory %s\n",dir_str);
+ err_printf("fs list: no such directory %s\n",dir_str);
return;
}
rwx[(sbuf.st_mode & S_IRWXG) >> 19],
rwx[(sbuf.st_mode & S_IRWXO) >> 22]);
diag_printf(" %2d size %6d %s\n",
- sbuf.st_nlink,sbuf.st_size,
+ sbuf.st_nlink,(int)sbuf.st_size,
entry->d_name);
}
return;
}
-RedBoot_cmd("ls",
- "list directory contents",
- "[-d directory]",
- do_ls
+local_cmd_entry("list",
+ "list directory contents",
+ "[<directory>]",
+ do_list,
+ FS_cmds
+ );
+
+
+//==========================================================================
+
+
+static void
+do_mkdir(int argc, char * argv[])
+{
+ char *dir_str;
+ int err;
+
+ if( mount_count == 0 )
+ {
+ err_printf("fs: No filesystems mounted\n");
+ return;
+ }
+
+ if (!scan_opts(argc, argv, 1, NULL, 0, &dir_str, OPTION_ARG_TYPE_STR, "directory") ||
+ dir_str == NULL)
+ {
+ fs_usage("invalid arguments");
+ return;
+ }
+
+ err = mkdir( dir_str, 0 );
+
+ if( err != 0 )
+ err_printf("fs mkdir: failed to create directory %s\n",dir_str);
+}
+
+local_cmd_entry("mkdir",
+ "create directory",
+ "<directory>",
+ do_mkdir,
+ FS_cmds
+ );
+
+//==========================================================================
+
+static void
+do_deldir(int argc, char * argv[])
+{
+ char *dir_str;
+ int err;
+
+ if( mount_count == 0 )
+ {
+ err_printf("fs: No filesystems mounted\n");
+ return;
+ }
+
+ if (!scan_opts(argc, argv, 1, NULL, 0, &dir_str, OPTION_ARG_TYPE_STR, "directory") ||
+ dir_str == NULL)
+ {
+ fs_usage("invalid arguments");
+ return;
+ }
+
+ err = rmdir( dir_str );
+
+ if( err != 0 )
+ err_printf("fs deldir: failed to remove directory %s\n",dir_str);
+}
+
+local_cmd_entry("deldir",
+ "delete directory",
+ "<directory>",
+ do_deldir,
+ FS_cmds
+ );
+
+//==========================================================================
+
+static void
+do_del(int argc, char * argv[])
+{
+ char *name_str = NULL;
+ int err;
+
+ if( mount_count == 0 )
+ {
+ err_printf("fs: No filesystems mounted\n");
+ return;
+ }
+
+ if (!scan_opts(argc, argv, 1, NULL, 0, &name_str, OPTION_ARG_TYPE_STR, "file") ||
+ name_str == NULL)
+ {
+ fs_usage("invalid arguments");
+ return;
+ }
+
+ err = unlink( name_str );
+
+ if( err != 0 )
+ err_printf("fs del: failed to delete file %s\n",name_str);
+}
+
+local_cmd_entry("del",
+ "delete file",
+ "<file>",
+ do_del,
+ FS_cmds
+ );
+
+//==========================================================================
+
+static void
+do_move(int argc, char * argv[])
+{
+ int err;
+ __externC int rename( const char *oldname, const char *newname );
+ if( mount_count == 0 )
+ {
+ err_printf("fs: No filesystems mounted\n");
+ return;
+ }
+
+ if( argc != 3 )
+ fs_usage("bad arguments to move command\n");
+
+ err = rename( argv[1], argv[2] );
+
+ if( err != 0 )
+ err_printf("fs move: failed to move file %s to %s\n",argv[1],argv[2]);
+}
+
+local_cmd_entry("move",
+ "move file",
+ "<from> <to>",
+ do_move,
+ FS_cmds
+ );
+
+//==========================================================================
+
+static void
+do_cd(int argc, char * argv[])
+{
+ char *dir_str;
+ int err;
+
+ if( mount_count == 0 )
+ {
+ err_printf("fs: No filesystems mounted\n");
+ return;
+ }
+
+ if (!scan_opts(argc, argv, 1, NULL, 0, &dir_str, OPTION_ARG_TYPE_STR, "directory"))
+ return;
+
+ if( dir_str == NULL )
+ dir_str = "/";
+
+ err = chdir( dir_str );
+
+ if( err != 0 )
+ err_printf("fs cd: failed to change directory %s\n",dir_str);
+}
+
+local_cmd_entry("cd",
+ "change directory",
+ "[<directory>]",
+ do_cd,
+ FS_cmds
+ );
+
+//==========================================================================
+
+static void
+do_write(int argc, char * argv[])
+{
+ char *name_str = NULL;
+ int err;
+ struct option_info opts[2];
+ CYG_ADDRESS mem_addr = 0;
+ unsigned long length = 0;
+ bool mem_addr_set = false;
+ bool length_set = false;
+ int fd;
+
+ if( mount_count == 0 )
+ {
+ err_printf("fs: No filesystems mounted\n");
+ return;
+ }
+
+ init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM,
+ (void *)&mem_addr, (bool *)&mem_addr_set, "memory base address");
+ init_opts(&opts[1], 'l', true, OPTION_ARG_TYPE_NUM,
+ (void *)&length, (bool *)&length_set, "image length");
+
+ if (!scan_opts(argc, argv, 1, opts, 2, &name_str, OPTION_ARG_TYPE_STR, "file name") ||
+ name_str == NULL)
+ {
+ fs_usage("invalid arguments");
+ return;
+ }
+
+// diag_printf("load_address %08x %08x\n",load_address,load_address_end);
+// diag_printf("ram %08x %08x\n",ram_start, ram_end);
+// diag_printf("file name %08x >%s<\n",name_str,name_str);
+
+ if (!mem_addr_set &&
+ (load_address >= (CYG_ADDRESS)ram_start) &&
+ ((load_address_end) < (CYG_ADDRESS)ram_end))
+ {
+ mem_addr = load_address;
+ mem_addr_set = true;
+ if (!length_set)
+ {
+ length = load_address_end - load_address;
+ length_set = true;
+ // maybe get length from existing file size if no loaded
+ // image?
+ }
+ }
+
+ fd = open( name_str, O_WRONLY|O_CREAT|O_TRUNC );
+
+ if( fd < 0 )
+ {
+ err_printf("fs write: Cannot open %s\n", name_str );
+ return;
+ }
+
+// diag_printf("write %08x %08x\n",mem_addr, length );
+
+ err = write( fd, (void *)mem_addr, length );
+
+ if( err != length )
+ {
+ err_printf("fs write: failed to write to file %d(%d) %d\n",err,length,errno);
+ }
+
+ err = close( fd );
+
+ if( err != 0 )
+ err_printf("fs write: close failed\n");
+}
+
+local_cmd_entry("write",
+ "write data to file",
+ "-b <mem_base> -l <image_length> <file_name>",
+ do_write,
+ FS_cmds
+ );
+
+//==========================================================================
+
+__externC cyg_fstab_entry cyg_fstab[];
+__externC cyg_fstab_entry cyg_fstab_end;
+__externC cyg_mtab_entry cyg_mtab[];
+__externC cyg_mtab_entry cyg_mtab_end;
+
+static void
+do_info(int argc, char * argv[])
+{
+ cyg_bool found = false;
+ cyg_fstab_entry *f;
+ cyg_devtab_entry_t *t;
+
+ for( f = &cyg_fstab[0] ; f != &cyg_fstab_end; f++ )
+ {
+ if( !found )
+ {
+ diag_printf("Filesystems available:\n");
+ found = true;
+ }
+ diag_printf("%s\n",f->name);
+ }
+
+ found = false;
+ for (t = &__DEVTAB__[0]; t != &__DEVTAB_END__; t++)
+ {
+ if( (t->status & CYG_DEVTAB_STATUS_BLOCK) == 0 ||
+ (t->status & CYG_DEVTAB_STATUS_AVAIL) == 0 )
+ continue;
+
+ if( !found )
+ {
+ diag_printf("\nDevices available:\n");
+ found = true;
+ }
+ diag_printf("%s\n",t->name);
+ }
+
+ if( mount_count != 0 )
+ {
+ int i;
+
+ diag_printf("\nMounted filesystems:\n");
+ diag_printf(" Device Filesystem Mounted on\n");
+
+ for( i = 0; i < MAX_MOUNTS; i++ )
+ {
+ if( mounts[i].mp_str[0] != '\0' )
+ diag_printf("%32s %10s %s\n", mounts[i].dev_str, mounts[i].type_str, mounts[i].mp_str);
+ }
+ }
+}
+
+local_cmd_entry("info",
+ "filesystem info",
+ "",
+ do_info,
+ FS_cmds
);
-#endif // CYGBLD_REDBOOT_FILEIO_WITH_LS
+//==========================================================================
+
+static void
+do_fs(int argc, char *argv[])
+{
+ struct cmd *cmd;
+
+ if (argc < 2) {
+ fs_usage("too few arguments");
+ return;
+ }
+ if ((cmd = cmd_search(__FS_cmds_TAB__, &__FS_cmds_TAB_END__,
+ argv[1])) != (struct cmd *)0) {
+ (cmd->fun)(argc-1, argv+1);
+ return;
+ }
+ fs_usage("unrecognized command");
+}
+
+RedBoot_nested_cmd("fs",
+ "Manage Filesystem files",
+ "{cmds}",
+ do_fs,
+ __FS_cmds_TAB__, &__FS_cmds_TAB_END__
+ );
+
+
+//==========================================================================
+
static int fd;
externC int
{
char *filename = info->filename;
- if (!fileio_mounted) {
- diag_printf("No file system mounted\n");
- return -1;
- }
+ if( mount_count == 0 )
+ {
+ diag_printf("fs: No filesystems mounted\n");
+ return -1;
+ }
+
fd = open(filename, O_RDONLY);
if (fd < 0) {
- diag_printf("Open failed, error %d\n", errno);
+ diag_printf("fs: Open failed, error %d\n", errno);
return -1;
}
return 0;
{
static char myerr[10];
- diag_sprintf(myerr, "error %d\n", err);
+ diag_sprintf(myerr, "error %d", err);
return myerr;
}
0, fileio_stream_read, fileio_error);
RedBoot_load(file, fileio_io, true, true, 0);
+//==========================================================================
+// End of fileio.c
+
&set_16bit, 0, "output 16 bit units");
init_opts(&opts[3], '1', false, OPTION_ARG_TYPE_FLG,
&set_8bit, 0, "output 8 bit units");
- if (!scan_opts(argc, argv, 1, opts, 5, 0, 0, "")) {
+ if (!scan_opts(argc, argv, 1, opts, 4, 0, 0, "")) {
return;
}
if (!base_set) {
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2002, 2003, 2004 Gary Thomas
+// Copyright (C) 2004 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
#endif
#endif
#include <cyg/infra/cyg_ass.h> // assertion macros
+#ifdef CYGBLD_REDBOOT_LOAD_INTO_FLASH
+#include <cyg/io/flash.h>
+#include "flash_load.h"
+#endif
static char usage[] = "[-r] [-v] [-z to swap endianness on 16 bit] "
#ifdef CYGBLD_BUILD_REDBOOT_WITH_ZLIB
"[-m <varies>] "
#if CYGNUM_HAL_VIRTUAL_VECTOR_NUM_CHANNELS > 1
"[-c <channel_number>] "
+#endif
+#ifdef CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ "[-f <flash_address>] "
#endif
"\n [-b <base_address>] <file_name>";
// Buffers, data used by redboot_getc
#define BUF_SIZE CYGNUM_REDBOOT_GETC_BUFFER
struct {
- getc_io_funcs_t *io;
- int (*fun)(char *, int len, int *err);
- unsigned char buf[BUF_SIZE];
- unsigned char *bufp;
- int avail, len, err;
- int verbose, decompress, tick;
+ getc_io_funcs_t *io;
+ int (*fun)(void *, int len, int *err);
+ unsigned char buf[BUF_SIZE];
+ unsigned char *bufp;
+ int avail, len, err;
+ int verbose, decompress, tick;
#ifdef CYGBLD_BUILD_REDBOOT_WITH_ZLIB
- int (*raw_fun)(char *, int len, int *err);
- _pipe_t load_pipe;
- unsigned char _buffer[CYGNUM_REDBOOT_LOAD_ZLIB_BUFFER];
+ int (*raw_fun)(void *, int len, int *err);
+ _pipe_t load_pipe;
+ unsigned char _buffer[CYGNUM_REDBOOT_LOAD_ZLIB_BUFFER];
#endif
} getc_info;
static int
redboot_getc(void)
{
- static char spin[] = "|/-\\|-";
- if (getc_info.avail < 0) {
- return -1;
- }
- if (getc_info.avail == 0) {
- if (getc_info.verbose) {
- diag_printf("%c\b", spin[getc_info.tick++]);
- if (getc_info.tick >= sizeof(spin)) {
- getc_info.tick = 0;
- }
- }
- if (getc_info.len < BUF_SIZE) {
- // No more data available
- if (getc_info.verbose) diag_printf("\n");
- return -1;
- }
- getc_info.bufp = getc_info.buf;
- getc_info.len = (*getc_info.fun)(getc_info.bufp, BUF_SIZE, &getc_info.err);
- if ((getc_info.avail = getc_info.len) <= 0) {
- if (getc_info.len < 0) {
- diag_printf("I/O error: %s\n", (getc_info.io->error)(getc_info.err));
- }
- if (getc_info.verbose) diag_printf("\n");
- return -1;
- }
- }
- getc_info.avail--;
- return *getc_info.bufp++;
+ static char spin[] = "|/-\\|-";
+ if (getc_info.avail < 0) {
+ return -1;
+ }
+ if (getc_info.avail == 0) {
+ if (getc_info.verbose) {
+ err_printf("%c\b", spin[getc_info.tick++]);
+ if (getc_info.tick >= sizeof(spin)) {
+ getc_info.tick = 0;
+ }
+ }
+ if (getc_info.len < BUF_SIZE) {
+ // No more data available
+ if (getc_info.verbose) diag_printf("\n");
+ return -1;
+ }
+ getc_info.bufp = getc_info.buf;
+ getc_info.len = (*getc_info.fun)(getc_info.bufp, BUF_SIZE, &getc_info.err);
+ if ((getc_info.avail = getc_info.len) <= 0) {
+ if (getc_info.len < 0) {
+ diag_printf("I/O error: %s\n", (getc_info.io->error)(getc_info.err));
+ }
+ if (getc_info.verbose) diag_printf("\n");
+ return -1;
+ }
+ }
+ getc_info.avail--;
+ return *getc_info.bufp++;
}
#ifdef CYGBLD_BUILD_REDBOOT_WITH_ZLIB
// Called to fetch a new chunk of data and decompress it
//
static int
-_decompress_stream(char *buf, int len, int *err)
+_decompress_stream(void *buf, int len, int *err)
{
- _pipe_t* p = &getc_info.load_pipe;
- int res, total;
-
- total = 0;
- while (len > 0) {
- if (p->in_avail == 0) {
- p->in_buf = &getc_info._buffer[0];
- res = (*getc_info.raw_fun)(p->in_buf, CYGNUM_REDBOOT_LOAD_ZLIB_BUFFER,
- &getc_info.err);
- if ((p->in_avail = res) <= 0) {
- // No more data
- return total;
- }
- }
- p->out_buf = buf;
- p->out_size = 0;
- p->out_max = len;
- res = (*_dc_inflate)(p);
- if (res != 0) {
- *err = res;
- return total;
- }
- len -= p->out_size;
- buf += p->out_size;
- total += p->out_size;
- }
- return total;
+ _pipe_t *p = &getc_info.load_pipe;
+ int res, total;
+
+ total = 0;
+ while (len > 0) {
+ if (p->in_avail == 0) {
+ p->in_buf = &getc_info._buffer[0];
+ res = (*getc_info.raw_fun)(p->in_buf, CYGNUM_REDBOOT_LOAD_ZLIB_BUFFER,
+ &getc_info.err);
+ if ((p->in_avail = res) <= 0) {
+ // No more data
+ return total;
+ }
+ }
+ p->out_buf = buf;
+ p->out_size = 0;
+ p->out_max = len;
+ res = (*_dc_inflate)(p);
+ if (res != 0) {
+ *err = res;
+ return total;
+ }
+ len -= p->out_size;
+ buf = (char *)buf + p->out_size;
+ total += p->out_size;
+ }
+ return total;
}
#endif
redboot_getc_init(connection_info_t *info, getc_io_funcs_t *funcs,
int verbose, int decompress)
{
- int res;
-
- res = (funcs->open)(info, &getc_info.err);
- if (res < 0) {
- diag_printf("Can't load '%s': %s\n", info->filename, (funcs->error)(getc_info.err));
- return res;
- }
- getc_info.io = funcs;
- getc_info.fun = funcs->read;
- getc_info.avail = 0;
- getc_info.len = BUF_SIZE;
- getc_info.verbose = verbose;
- getc_info.decompress = decompress;
- getc_info.tick = 0;
+ int res;
+
+ res = (funcs->open)(info, &getc_info.err);
+ if (res < 0) {
+ err_printf("Can't load '%s': %s\n", info->filename, (funcs->error)(getc_info.err));
+ return res;
+ }
+ getc_info.io = funcs;
+ getc_info.fun = funcs->read;
+ getc_info.avail = 0;
+ getc_info.len = BUF_SIZE;
+ getc_info.verbose = verbose;
+ getc_info.decompress = decompress;
+ getc_info.tick = 0;
#ifdef CYGBLD_BUILD_REDBOOT_WITH_ZLIB
- if (decompress) {
- _pipe_t* p = &getc_info.load_pipe;
- p->out_buf = &getc_info.buf[0];
- p->out_size = 0;
- p->in_avail = 0;
- getc_info.raw_fun = getc_info.fun;
- getc_info.fun = _decompress_stream;
- getc_info.err = (*_dc_init)(p);
- if (0 != getc_info.err && p->msg) {
- diag_printf("open decompression error: %s\n", p->msg);
- }
- }
-#endif
- return 0;
+ if (decompress) {
+ _pipe_t *p = &getc_info.load_pipe;
+ p->out_buf = &getc_info.buf[0];
+ p->out_size = 0;
+ p->in_avail = 0;
+ getc_info.raw_fun = getc_info.fun;
+ getc_info.fun = _decompress_stream;
+ getc_info.err = (*_dc_init)(p);
+ if (0 != getc_info.err && p->msg) {
+ err_printf("open decompression error: %s\n", p->msg);
+ }
+ }
+#endif
+ return 0;
}
static void
redboot_getc_rewind(void)
{
- getc_info.bufp = getc_info.buf;
- getc_info.avail = getc_info.len;
+ getc_info.bufp = getc_info.buf;
+ getc_info.avail = getc_info.len;
}
static void
redboot_getc_terminate(bool abort)
{
- if (getc_info.io->terminate) {
- (getc_info.io->terminate)(abort, redboot_getc);
- }
+ if (getc_info.io->terminate) {
+ (getc_info.io->terminate)(abort, redboot_getc);
+ }
}
static void
redboot_getc_close(void)
{
- (getc_info.io->close)(&getc_info.err);
+ (getc_info.io->close)(&getc_info.err);
#ifdef CYGBLD_BUILD_REDBOOT_WITH_ZLIB
- if (getc_info.decompress) {
- _pipe_t* p = &getc_info.load_pipe;
- int err = getc_info.err;
- if (0 != err && p->msg) {
- diag_printf("decompression error: %s\n", p->msg);
- }
- err = (*_dc_close)(p, getc_info.err);
- }
+ if (getc_info.decompress) {
+ _pipe_t *p = &getc_info.load_pipe;
+ int err = getc_info.err;
+ if (0 != err && p->msg) {
+ diag_printf("decompression error: %s\n", p->msg);
+ }
+ err = (*_dc_close)(p, getc_info.err);
+ }
#endif
}
static int
_read(int (*getc)(void), unsigned char *buf, int len)
{
- int total = 0;
- int ch;
- while (len-- > 0) {
- ch = (*getc)();
- if (ch < 0) {
- // EOF or error
- break;
- }
- *buf++ = ch;
- total++;
- }
- return total;
+ int total = 0;
+ int ch;
+ while (len-- > 0) {
+ ch = (*getc)();
+ if (ch < 0) {
+ // EOF or error
+ break;
+ }
+ *buf++ = ch;
+ total++;
+ }
+ return total;
}
#endif
load_elf_image(getc_t getc, unsigned long base, bool swap16bit)
{
#ifdef CYGSEM_REDBOOT_ELF
- Elf32_Ehdr ehdr;
+ Elf32_Ehdr ehdr;
#define MAX_PHDR 8
- Elf32_Phdr phdr[MAX_PHDR];
- unsigned long offset = 0;
- int phx, len, ch;
- unsigned char *addr, *addr_swap;
- unsigned long addr_offset = 0;
- unsigned long highest_address = 0;
- unsigned long lowest_address = 0xFFFFFFFF;
- unsigned char *SHORT_DATA = "Short data reading ELF file\n";
-
- // Read the header
- if (_read(getc, (unsigned char *)&ehdr, sizeof(ehdr)) != sizeof(ehdr)) {
- diag_printf("Can't read ELF header\n");
- redboot_getc_terminate(true);
- return 0;
- }
- offset += sizeof(ehdr);
+ Elf32_Phdr phdr[MAX_PHDR];
+ unsigned long offset = 0;
+ int phx, len, ch;
+ unsigned char *addr, *addr_swap;
+ unsigned long addr_offset = 0;
+ unsigned long highest_address = 0;
+ unsigned long lowest_address = 0xFFFFFFFF;
+ const char *SHORT_DATA = "Short data reading ELF file\n";
+
+ // Read the header
+ if (_read(getc, (unsigned char *)&ehdr, sizeof(ehdr)) != sizeof(ehdr)) {
+ err_printf("Can't read ELF header\n");
+ redboot_getc_terminate(true);
+ return 0;
+ }
+ offset += sizeof(ehdr);
#if 0 // DEBUG
- diag_printf("Type: %d, Machine: %d, Version: %d, Entry: %p, PHoff: %p/%d/%d, SHoff: %p/%d/%d\n",
- ehdr.e_type, ehdr.e_machine, ehdr.e_version, ehdr.e_entry,
- ehdr.e_phoff, ehdr.e_phentsize, ehdr.e_phnum,
- ehdr.e_shoff, ehdr.e_shentsize, ehdr.e_shnum);
-#endif
- if (ehdr.e_type != ET_EXEC) {
- diag_printf("Only absolute ELF images supported\n");
- redboot_getc_terminate(true);
- return 0;
- }
- if (ehdr.e_phnum > MAX_PHDR) {
- diag_printf("Too many program headers\n");
- redboot_getc_terminate(true);
- return 0;
- }
- while (offset < ehdr.e_phoff) {
- if ((*getc)() < 0) {
- diag_printf(SHORT_DATA);
- redboot_getc_terminate(true);
- return 0;
- }
- offset++;
- }
- for (phx = 0; phx < ehdr.e_phnum; phx++) {
- if (_read(getc, (unsigned char *)&phdr[phx], sizeof(phdr[0])) != sizeof(phdr[0])) {
- diag_printf("Can't read ELF program header\n");
- redboot_getc_terminate(true);
- return 0;
- }
+ diag_printf("Type: %d, Machine: %d, Version: %d, Entry: %p, PHoff: %p/%d/%d, SHoff: %p/%d/%d\n",
+ ehdr.e_type, ehdr.e_machine, ehdr.e_version, ehdr.e_entry,
+ ehdr.e_phoff, ehdr.e_phentsize, ehdr.e_phnum,
+ ehdr.e_shoff, ehdr.e_shentsize, ehdr.e_shnum);
+#endif
+ if (ehdr.e_type != ET_EXEC) {
+ err_printf("Only absolute ELF images supported\n");
+ redboot_getc_terminate(true);
+ return 0;
+ }
+ if (ehdr.e_phnum > MAX_PHDR) {
+ err_printf("Too many program headers\n");
+ redboot_getc_terminate(true);
+ return 0;
+ }
+ while (offset < ehdr.e_phoff) {
+ if ((*getc)() < 0) {
+ err_printf(SHORT_DATA);
+ redboot_getc_terminate(true);
+ return 0;
+ }
+ offset++;
+ }
+ for (phx = 0; phx < ehdr.e_phnum; phx++) {
+ if (_read(getc, (unsigned char *)&phdr[phx], sizeof(phdr[0])) != sizeof(phdr[0])) {
+ err_printf("Can't read ELF program header\n");
+ redboot_getc_terminate(true);
+ return 0;
+ }
#if 0 // DEBUG
- diag_printf("Program header: type: %d, off: %p, va: %p, pa: %p, len: %d/%d, flags: %d\n",
- phdr[phx].p_type, phdr[phx].p_offset, phdr[phx].p_vaddr, phdr[phx].p_paddr,
- phdr[phx].p_filesz, phdr[phx].p_memsz, phdr[phx].p_flags);
-#endif
- offset += sizeof(phdr[0]);
- }
- if (base) {
- // Set address offset based on lowest address in file.
- addr_offset = 0xFFFFFFFF;
- for (phx = 0; phx < ehdr.e_phnum; phx++) {
-#ifdef CYGOPT_REDBOOT_ELF_VIRTUAL_ADDRESS
- if ((phdr[phx].p_type == PT_LOAD) && (phdr[phx].p_vaddr < addr_offset)) {
- addr_offset = phdr[phx].p_vaddr;
+ diag_printf("Program header: type: %d, off: %p, va: %p, pa: %p, len: %d/%d, flags: %d\n",
+ phdr[phx].p_type, phdr[phx].p_offset, phdr[phx].p_vaddr, phdr[phx].p_paddr,
+ phdr[phx].p_filesz, phdr[phx].p_memsz, phdr[phx].p_flags);
+#endif
+ offset += sizeof(phdr[0]);
+ }
+ if (base) {
+ // Set address offset based on lowest address in file.
+ addr_offset = 0xFFFFFFFF;
+ for (phx = 0; phx < ehdr.e_phnum; phx++) {
+#ifdef CYGOPT_REDBOOT_ELF_VIRTUAL_ADDRESS
+ if ((phdr[phx].p_type == PT_LOAD) && (phdr[phx].p_vaddr < addr_offset)) {
+ addr_offset = phdr[phx].p_vaddr;
#else
- if ((phdr[phx].p_type == PT_LOAD) && (phdr[phx].p_paddr < addr_offset)) {
- addr_offset = phdr[phx].p_paddr;
-#endif
- }
- }
- addr_offset = (unsigned long)base - addr_offset;
- } else {
- addr_offset = 0;
- }
- for (phx = 0; phx < ehdr.e_phnum; phx++) {
- if (phdr[phx].p_type == PT_LOAD) {
- // Loadable segment
+ if ((phdr[phx].p_type == PT_LOAD) && (phdr[phx].p_paddr < addr_offset)) {
+ addr_offset = phdr[phx].p_paddr;
+#endif
+ }
+ }
+ addr_offset = (unsigned long)base - addr_offset;
+ } else {
+ addr_offset = 0;
+ }
+ for (phx = 0; phx < ehdr.e_phnum; phx++) {
+ if (phdr[phx].p_type == PT_LOAD) {
+ // Loadable segment
#ifdef CYGOPT_REDBOOT_ELF_VIRTUAL_ADDRESS
- addr = (unsigned char *)phdr[phx].p_vaddr;
-#else
- addr = (unsigned char *)phdr[phx].p_paddr;
-#endif
- len = phdr[phx].p_filesz;
- if ((unsigned long)addr < lowest_address) {
- lowest_address = (unsigned long)addr;
- }
- addr += addr_offset;
- if (offset > phdr[phx].p_offset) {
- if ((phdr[phx].p_offset + len) < offset) {
- diag_printf("Can't load ELF file - program headers out of order\n");
- redboot_getc_terminate(true);
- return 0;
- }
- addr += offset - phdr[phx].p_offset;
- } else {
- while (offset < phdr[phx].p_offset) {
- if ((*getc)() < 0) {
- diag_printf(SHORT_DATA);
- redboot_getc_terminate(true);
- return 0;
- }
- offset++;
- }
- }
-
- // Copy data into memory
- while (len-- > 0) {
+ addr = (unsigned char *)phdr[phx].p_vaddr;
+#else
+ addr = (unsigned char *)phdr[phx].p_paddr;
+#endif
+ len = phdr[phx].p_filesz;
+ if ((unsigned long)addr < lowest_address) {
+ lowest_address = (unsigned long)addr;
+ }
+ addr += addr_offset;
+ if (offset > phdr[phx].p_offset) {
+ if ((phdr[phx].p_offset + len) < offset) {
+ err_printf("Can't load ELF file - program headers out of order\n");
+ redboot_getc_terminate(true);
+ return 0;
+ }
+ addr += offset - phdr[phx].p_offset;
+ } else {
+ while (offset < phdr[phx].p_offset) {
+ if ((*getc)() < 0) {
+ err_printf(SHORT_DATA);
+ redboot_getc_terminate(true);
+ return 0;
+ }
+ offset++;
+ }
+ }
+
+ // Copy data into memory
+ while (len-- > 0) {
+#ifdef CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS
+ if (!(valid_address(addr)
+#ifdef CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ || (flash_verify_addr(addr) == FLASH_ERR_OK)
+#endif
+ )) {
+ redboot_getc_terminate(true);
+ err_printf("*** Abort! Attempt to load ELF data to address: %p which is not valid\n",
+ (void*)addr);
+ return 0;
+ }
+#endif
+ if ((ch = (*getc)()) < 0) {
+ err_printf(SHORT_DATA);
+ redboot_getc_terminate(true);
+ return 0;
+ }
+
+ /* In case of multicore and the core we wanna load the image for is not in the same endianness
+ that the core we run redboot from, have to invert bytes on 16-bit boundary (16-bit memory)*/
+ if (swap16bit) {
+ // addr is even, have to write char data to the last address
+ if (((unsigned long)addr) % 2) {
+ addr_swap = addr - 1;
+ *addr_swap = ch;
+ } else {
+ // addr is odd, have to write char data to the next address
+ addr_swap = addr + 1;
+ *addr_swap = ch;
+ }
+ addr++;
+ }
+ else {
#ifdef CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS
- if (!valid_address(addr)) {
- redboot_getc_terminate(true);
- diag_printf("*** Abort! Attempt to load ELF data to address: %p which is not in RAM\n", (void*)addr);
- return 0;
- }
-#endif
- if ((ch = (*getc)()) < 0) {
- diag_printf(SHORT_DATA);
- redboot_getc_terminate(true);
- return 0;
- }
-
- /* In case of multicore and the core we wanna load the image for is not in the same endianness
- that the core we run redboot from, have to invert bytes on 16-bit boundary (16-bit memory)*/
- if(swap16bit){
- // addr is even, have to write char data to the last address
- if(((unsigned long)addr)%2){
- addr_swap=addr-1;
- *addr_swap = ch;
- }
- // addr is odd, have to write char data to the next address
- else{
- addr_swap=addr+1;
- *addr_swap = ch;
- }
- addr++;
- }
- else {
- *addr++ = ch;
- }
- offset++;
- if ((unsigned long)(addr-addr_offset) > highest_address) {
- highest_address = (unsigned long)(addr - addr_offset);
- }
- }
- }
- }
-
- // Save load base/top and entry
- if (base) {
- load_address = base;
- load_address_end = base + (highest_address - lowest_address);
- entry_address = base + (ehdr.e_entry - lowest_address);
- } else {
- load_address = lowest_address;
- load_address_end = highest_address;
- entry_address = ehdr.e_entry;
- }
-
- // nak everything to stop the transfer, since redboot
- // usually doesn't read all the way to the end of the
- // elf files.
- redboot_getc_terminate(true);
- if (addr_offset) diag_printf("Address offset = %p\n", (void *)addr_offset);
- diag_printf("Entry point: %p, address range: %p-%p\n",
- (void*)entry_address, (void *)load_address, (void *)load_address_end);
- return 1;
+ if (valid_address(addr))
+#endif
+ *addr++ = ch;
+
+#ifdef CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ else {
+ flash_load_write(addr, ch);
+ addr++;
+ }
+#endif
+ }
+ offset++;
+ if ((unsigned long)(addr-addr_offset) > highest_address) {
+ highest_address = (unsigned long)(addr - addr_offset);
+ }
+ }
+ }
+ }
+
+ // Save load base/top and entry
+ if (base) {
+ load_address = base;
+ load_address_end = base + (highest_address - lowest_address);
+ entry_address = base + (ehdr.e_entry - lowest_address);
+ } else {
+ load_address = lowest_address;
+ load_address_end = highest_address;
+ entry_address = ehdr.e_entry;
+ }
+
+ // nak everything to stop the transfer, since redboot
+ // usually doesn't read all the way to the end of the
+ // elf files.
+ redboot_getc_terminate(true);
+ if (addr_offset) diag_printf("Address offset = %p\n", (void *)addr_offset);
+ diag_printf("Entry point: %p, address range: %p-%p\n",
+ (void*)entry_address, (void *)load_address, (void *)load_address_end);
+ return 1;
#else // CYGSEM_REDBOOT_ELF
- diag_printf("Loading ELF images not supported\n");
- return 0;
+ err_printf("Loading ELF images not supported\n");
+ return 0;
#endif // CYGSEM_REDBOOT_ELF
}
-
//
// Scan a string of hex bytes and update the checksum
//
static long
_hex2(int (*getc)(void), int len, long *sum)
{
- int val, byte;
- char c1, c2;
-
- val = 0;
- while (len-- > 0) {
- c1 = (*getc)();
- c2 = (*getc)();
- if (_is_hex(c1) && _is_hex(c2)) {
- val <<= 8;
- byte = (_from_hex(c1)<<4) | _from_hex(c2);
- val |= byte;
- if (sum) {
- *sum += byte;
- }
- } else {
- return (-1);
- }
- }
- return (val);
+ int val, byte;
+ char c1, c2;
+
+ val = 0;
+ while (len-- > 0) {
+ c1 = getc();
+ c2 = getc();
+ if (_is_hex(c1) && _is_hex(c2)) {
+ val <<= 8;
+ byte = (_from_hex(c1) << 4) | _from_hex(c2);
+ val |= byte;
+ if (sum) {
+ *sum += byte;
+ }
+ } else {
+ return -1;
+ }
+ }
+ return val;
}
//
static unsigned long
load_srec_image(getc_t getc, unsigned long base, bool swap16bit)
{
- int c;
- long offset = 0, count, sum, val, cksum;
- unsigned char *addr, *base_addr, *addr_swap;
- char type;
- bool first_addr = true;
- unsigned long addr_offset = 0;
- unsigned long highest_address = 0;
- unsigned long lowest_address = 0xFFFFFFFF;
-
- while ((c = (*getc)()) > 0) {
- // Start of line
- if (c != 'S') {
- redboot_getc_terminate(true);
- diag_printf("Invalid S-record at offset %p, input: %c\n",
- (void *)offset, c);
- return 0;
- }
- type = (*getc)();
- offset += 2;
- sum = 0;
- if ((count = _hex2(getc, 1, &sum)) < 0) {
- redboot_getc_terminate(true);
- diag_printf("Bad S-record count at offset %p\n", (void *)offset);
- return 0;
- }
- offset += 1;
- switch (type) {
- case '0':
- break;
- case '1':
- case '2':
- case '3':
- base_addr = addr = (unsigned char *)_hex2(getc, (type-'1'+2), &sum);
- offset += (type-'1'+2);
- if (first_addr) {
- if (base) {
- addr_offset = (unsigned long)base - (unsigned long)addr;
- } else {
- addr_offset = 0;
- }
- first_addr = false;
- }
- addr += addr_offset;
- if ((unsigned long)(addr-addr_offset) < lowest_address) {
- lowest_address = (unsigned long)(addr - addr_offset);
- }
+ int c;
+ long offset = 0, count, sum, val, cksum;
+ unsigned char *addr, *base_addr, *addr_swap;
+ char type;
+ bool first_addr = true;
+ unsigned long addr_offset = 0;
+ unsigned long highest_address = 0;
+ unsigned long lowest_address = 0xFFFFFFFF;
+
+ while ((c = (*getc)()) > 0) {
+ // Start of line
+ if (c != 'S') {
+ redboot_getc_terminate(true);
+ err_printf("Invalid S-record at offset %p, input: %c\n",
+ (void *)offset, c);
+ return 0;
+ }
+ type = (*getc)();
+ offset += 2;
+ sum = 0;
+ if ((count = _hex2(getc, 1, &sum)) < 0) {
+ redboot_getc_terminate(true);
+ err_printf("Bad S-record count at offset %p\n", (void *)offset);
+ return 0;
+ }
+ offset += 1;
+ switch (type) {
+ case '0':
+ break;
+ case '1':
+ case '2':
+ case '3':
+ base_addr = addr = (unsigned char *)_hex2(getc, type - '1' + 2, &sum);
+ offset += type - '1' + 2;
+ if (first_addr) {
+ if (base) {
+ addr_offset = (unsigned long)base - (unsigned long)addr;
+ } else {
+ addr_offset = 0;
+ }
+ first_addr = false;
+ }
+ addr += addr_offset;
+ if ((unsigned long)(addr-addr_offset) < lowest_address) {
+ lowest_address = (unsigned long)(addr - addr_offset);
+ }
#ifdef CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS
- if (!valid_address(addr)) {
- // Only if there is no need to stop the download before printing
- // output can we ask confirmation questions.
- redboot_getc_terminate(true);
- diag_printf("*** Abort! Attempt to load S-record to address: %p, which is not in RAM\n",(void*)addr);
- return 0;
- }
-#endif
- count -= ((type-'1'+2)+1);
- offset += count;
- while (count-- > 0) {
- val = _hex2(getc, 1, &sum);
- /* In case of multicore and the core we wanna load the image for is not in the same endianness
- that the core we run redboot from, have to invert bytes on 16-bit boundary (16-bit memory)*/
- if(swap16bit){
- // addr is even, have to write char data to the last address
- if(((unsigned long)addr)%2){
- addr_swap=addr-1;
- *addr_swap = val;
- }
- // addr is odd, have to write char data to the next address
- else{
- addr_swap=addr+1;
- *addr_swap = val;
- }
- addr++;
- }
- else {
- *addr++ = val;
- }
- }
- cksum = _hex2(getc, 1, 0);
- offset += 1;
- sum = sum & 0xFF;
- cksum = (~cksum & 0xFF);
- if (cksum != sum) {
- redboot_getc_terminate(true);
- diag_printf("*** Warning! Checksum failure - Addr: %lx, %02lX <> %02lX\n",
- (unsigned long)base_addr, sum, cksum);
- return 0;
- }
- if ((unsigned long)(addr-addr_offset) > highest_address) {
- highest_address = (unsigned long)(addr - addr_offset);
- }
- break;
- case '7':
- case '8':
- case '9':
- addr = (unsigned char *)_hex2(getc, ('9'-type+2), &sum);
- offset += ('9'-type+2);
- // Save load base/top, entry address
- if (base) {
- load_address = base;
- load_address_end = base + (highest_address - lowest_address);
- entry_address = (unsigned long)(base + (addr - lowest_address));
- } else {
- load_address = lowest_address;
- load_address_end = highest_address;
- entry_address = (unsigned long)addr;
- }
- redboot_getc_terminate(false);
- if (addr_offset) diag_printf("Address offset = %p\n", (void *)addr_offset);
- diag_printf("Entry point: %p, address range: %p-%p\n",
- (void*)entry_address, (void *)load_address, (void *)load_address_end);
-
- return load_address_end;
- default:
- redboot_getc_terminate(true);
- diag_printf("Invalid S-record at offset 0x%lx, type: %x\n",
- (unsigned long)offset, type);
- return 0;
- }
- while ((c = (*getc)()) != '\n') offset++;
- }
- return 0;
+ if (!(valid_address(addr)
+#ifdef CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ || (flash_verify_addr(addr) == FLASH_ERR_OK)
+#endif
+ )) {
+ // Only if there is no need to stop the download before printing
+ // output can we ask confirmation questions.
+ redboot_getc_terminate(true);
+ err_printf("*** Abort! Attempt to load S-record to address: %p, which is not valid\n",(void*)addr);
+ return 0;
+ }
+#endif
+ count -= type - '1' + 2 + 1;
+ offset += count;
+ while (count-- > 0) {
+ val = _hex2(getc, 1, &sum);
+ /* In case of multicore and the core we wanna load the image for is not in the same endianness
+ that the core we run redboot from, have to invert bytes on 16-bit boundary (16-bit memory)*/
+ if (swap16bit) {
+ // addr is even, have to write char data to the last address
+ if (((unsigned long)addr) % 2) {
+ addr_swap = addr - 1;
+ *addr_swap = val;
+ } else {
+ // addr is odd, have to write char data to the next address
+ addr_swap = addr + 1;
+ *addr_swap = val;
+ }
+ addr++;
+ } else {
+#ifdef CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS
+ if (valid_address(addr))
+#endif
+ *addr++ = val;
+
+#ifdef CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ else {
+ flash_load_write(addr, val);
+ addr++;
+ }
+#endif
+ }
+ }
+ cksum = _hex2(getc, 1, 0);
+ offset += 1;
+ sum = sum & 0xFF;
+ cksum = ~cksum & 0xFF;
+ if (cksum != sum) {
+ redboot_getc_terminate(true);
+ err_printf("*** Warning! Checksum failure - Addr: %lx, %02lX <> %02lX\n",
+ (unsigned long)base_addr, sum, cksum);
+ return 0;
+ }
+ if ((unsigned long)(addr-addr_offset) > highest_address) {
+ highest_address = (unsigned long)(addr - addr_offset);
+ }
+ break;
+ case '7':
+ case '8':
+ case '9':
+ addr = (unsigned char *)_hex2(getc, '9' - type + 2, &sum);
+ offset += '9' - type + 2;
+ // Save load base/top, entry address
+ if (base) {
+ load_address = base;
+ load_address_end = base + (highest_address - lowest_address);
+ entry_address = (unsigned long)(base + (addr - lowest_address));
+ } else {
+ load_address = lowest_address;
+ load_address_end = highest_address;
+ entry_address = (unsigned long)addr;
+ }
+ redboot_getc_terminate(false);
+ if (addr_offset) diag_printf("Address offset = %p\n", (void *)addr_offset);
+ diag_printf("Entry point: %p, address range: %p-%p\n",
+ (void*)entry_address, (void *)load_address, (void *)load_address_end);
+
+ return load_address_end;
+ default:
+ redboot_getc_terminate(true);
+ err_printf("Invalid S-record at offset 0x%lx, type: %x\n",
+ (unsigned long)offset, type);
+ return 0;
+ }
+ while ((c = getc()) != '\n') offset++;
+ }
+ return 0;
}
//
#ifdef CYGBLD_BUILD_REDBOOT_WITH_ZLIB
// -d - Decompress data [packed via 'zlib']
#endif
+#ifdef CYGBLD_REDBOOT_LOAD_INTO_FLASH
+// -f - specify a flash address
+#endif
//
void
do_load(int argc, char *argv[])
{
- int res, num_options;
- int i, err;
- bool verbose, raw, swap16bit;
- bool base_addr_set, mode_str_set;
- char *mode_str;
+ int res, num_options;
+ int i, err;
+ bool verbose, raw, swap16bit;
+ bool base_addr_set, mode_str_set;
+ char *mode_str;
#ifdef CYGPKG_REDBOOT_NETWORKING
- struct sockaddr_in host;
- bool hostname_set, port_set;
- unsigned int port; // int because it's an OPTION_ARG_TYPE_NUM,
+ struct sockaddr_in host;
+ bool hostname_set, port_set;
+ unsigned int port; // int because it's an OPTION_ARG_TYPE_NUM,
// but will be cast to short
- char *hostname;
+ char *hostname;
+#endif
+#ifdef CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ bool flash_addr_set = false;
#endif
- bool decompress = false;
- int chan = -1;
+ bool decompress = false;
+ int chan = -1;
#if CYGNUM_HAL_VIRTUAL_VECTOR_NUM_CHANNELS > 1
- bool chan_set;
-#endif
- unsigned long base = 0;
- unsigned long end = 0;
- char type[4];
- char *filename = 0;
- struct option_info opts[9];
- connection_info_t info;
- getc_io_funcs_t *io = NULL;
- struct load_io_entry *io_tab;
+ bool chan_set;
+#endif
+ unsigned long base = 0;
+ unsigned long end = 0;
+ char type[4];
+ char *filename = 0;
+ struct option_info opts[9];
+ connection_info_t info;
+ getc_io_funcs_t *io = NULL;
+ struct load_io_entry *io_tab;
#ifdef CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS
- bool spillover_ok = false;
+ bool spillover_ok = false;
#endif
#ifdef CYGPKG_REDBOOT_NETWORKING
- memset((char *)&host, 0, sizeof(host));
- host.sin_len = sizeof(host);
- host.sin_family = AF_INET;
- host.sin_addr = my_bootp_info.bp_siaddr;
- host.sin_port = 0;
-#endif
-
- init_opts(&opts[0], 'v', false, OPTION_ARG_TYPE_FLG,
- (void *)&verbose, 0, "verbose");
- init_opts(&opts[1], 'r', false, OPTION_ARG_TYPE_FLG,
- (void *)&raw, 0, "load raw data");
- init_opts(&opts[2], 'b', true, OPTION_ARG_TYPE_NUM,
- (void *)&base, (bool *)&base_addr_set, "load address");
- init_opts(&opts[3], 'm', true, OPTION_ARG_TYPE_STR,
- (void *)&mode_str, (bool *)&mode_str_set, "download mode (TFTP, xyzMODEM, or disk)");
- init_opts(&opts[4], 'z', false, OPTION_ARG_TYPE_FLG,
- (void *)&swap16bit, 0, "swap endianness on 16 bit");
- num_options = 5;
+ memset((char *)&host, 0, sizeof(host));
+ host.sin_len = sizeof(host);
+ host.sin_family = AF_INET;
+ host.sin_addr = my_bootp_info.bp_siaddr;
+ host.sin_port = 0;
+#endif
+
+ init_opts(&opts[0], 'v', false, OPTION_ARG_TYPE_FLG,
+ (void *)&verbose, 0, "verbose");
+ init_opts(&opts[1], 'r', false, OPTION_ARG_TYPE_FLG,
+ (void *)&raw, 0, "load raw data");
+ init_opts(&opts[2], 'b', true, OPTION_ARG_TYPE_NUM,
+ (void *)&base, (bool *)&base_addr_set, "load address");
+ init_opts(&opts[3], 'm', true, OPTION_ARG_TYPE_STR,
+ (void *)&mode_str, (bool *)&mode_str_set, "download mode (TFTP, xyzMODEM, or disk)");
+ init_opts(&opts[4], 'z', false, OPTION_ARG_TYPE_FLG,
+ (void *)&swap16bit, 0, "swap endianness on 16 bit");
+ num_options = 5;
#if CYGNUM_HAL_VIRTUAL_VECTOR_NUM_CHANNELS > 1
- init_opts(&opts[num_options], 'c', true, OPTION_ARG_TYPE_NUM,
- (void *)&chan, (bool *)&chan_set, "I/O channel");
- num_options++;
+ init_opts(&opts[num_options], 'c', true, OPTION_ARG_TYPE_NUM,
+ (void *)&chan, (bool *)&chan_set, "I/O channel");
+ num_options++;
#endif
#ifdef CYGPKG_REDBOOT_NETWORKING
- init_opts(&opts[num_options], 'h', true, OPTION_ARG_TYPE_STR,
- (void *)&hostname, (bool *)&hostname_set, "host name or IP address");
- num_options++;
- init_opts(&opts[num_options], 'p', true, OPTION_ARG_TYPE_NUM,
- (void *)&port, (bool *)&port_set, "TCP port");
- num_options++;
+ init_opts(&opts[num_options], 'h', true, OPTION_ARG_TYPE_STR,
+ (void *)&hostname, (bool *)&hostname_set, "host name or IP address");
+ num_options++;
+ init_opts(&opts[num_options], 'p', true, OPTION_ARG_TYPE_NUM,
+ (void *)&port, (bool *)&port_set, "TCP port");
+ num_options++;
#endif
#ifdef CYGBLD_BUILD_REDBOOT_WITH_ZLIB
- init_opts(&opts[num_options], 'd', false, OPTION_ARG_TYPE_FLG,
- (void *)&decompress, 0, "decompress");
- num_options++;
+ init_opts(&opts[num_options], 'd', false, OPTION_ARG_TYPE_FLG,
+ (void *)&decompress, 0, "decompress");
+ num_options++;
#endif
-
- CYG_ASSERT(num_options <= NUM_ELEMS(opts), "Too many options");
+#ifdef CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ init_opts(&opts[num_options], 'f', true, OPTION_ARG_TYPE_NUM,
+ (void *)&base, (bool *)&flash_addr_set, "flash address");
+ num_options++;
+#endif
+ CYG_ASSERT(num_options <= NUM_ELEMS(opts), "Too many options");
- if (!scan_opts(argc, argv, 1, opts, num_options,
- (void *)&filename, OPTION_ARG_TYPE_STR, "file name")) {
- return;
- }
+ if (!scan_opts(argc, argv, 1, opts, num_options,
+ (void *)&filename, OPTION_ARG_TYPE_STR, "file name")) {
+ return;
+ }
+
+ /* make sure any future go/exec's will fail until a successful upload */
+ entry_address = (unsigned long)NO_MEMORY;
+
#ifdef CYGPKG_REDBOOT_NETWORKING
- if (hostname_set) {
- ip_route_t rt;
- if (!_gethostbyname(hostname, (in_addr_t *)&host)) {
- diag_printf("Invalid host: %s\n", hostname);
- return;
- }
- /* check that the host can be accessed */
- if (__arp_lookup((ip_addr_t *)&host.sin_addr, &rt) < 0) {
- diag_printf("Unable to reach host %s (%s)\n",
- hostname, inet_ntoa((in_addr_t *)&host));
- return;
- }
- }
- if (port_set)
- host.sin_port = port;
-#endif
- if (chan >= CYGNUM_HAL_VIRTUAL_VECTOR_NUM_CHANNELS) {
- diag_printf("Invalid I/O channel: %d\n", chan);
- return;
- }
- if (mode_str_set) {
- for (io_tab = __RedBoot_LOAD_TAB__;
- io_tab != &__RedBoot_LOAD_TAB_END__; io_tab++) {
- if (strncasecmp(&mode_str[0], io_tab->name, strlen(&mode_str[0])) == 0) {
- io = io_tab->funcs;
- break;
- }
- }
- if (!io) {
- diag_printf("Invalid 'mode': %s. Valid modes are:", mode_str);
- for (io_tab = __RedBoot_LOAD_TAB__;
- io_tab != &__RedBoot_LOAD_TAB_END__; io_tab++) {
- diag_printf(" %s", io_tab->name);
- }
- diag_printf("\n");
- }
- if (!io) {
- return;
- }
- verbose &= io_tab->can_verbose;
- if (io_tab->need_filename && !filename) {
- diag_printf("File name required\n");
- diag_printf("usage: load %s\n", usage);
- return;
- }
- } else {
- char *which;
- io_tab = (struct load_io_entry *)NULL; // Default
+ if (hostname_set) {
+ ip_route_t rt;
+ if (!_gethostbyname(hostname, (in_addr_t *)&host)) {
+ err_printf("Invalid host: %s\n", hostname);
+ return;
+ }
+ /* check that the host can be accessed */
+ if (__arp_lookup((ip_addr_t *)&host.sin_addr, &rt) < 0) {
+ err_printf("Unable to reach host %s (%s)\n",
+ hostname, inet_ntoa((in_addr_t *)&host));
+ return;
+ }
+ }
+ if (port_set)
+ host.sin_port = port;
+#endif
+ if (chan >= CYGNUM_HAL_VIRTUAL_VECTOR_NUM_CHANNELS) {
+ err_printf("Invalid I/O channel: %d\n", chan);
+ return;
+ }
+ if (mode_str_set) {
+ for (io_tab = __RedBoot_LOAD_TAB__;
+ io_tab != &__RedBoot_LOAD_TAB_END__; io_tab++) {
+ if (strncasecmp(&mode_str[0], io_tab->name, strlen(&mode_str[0])) == 0) {
+ io = io_tab->funcs;
+ break;
+ }
+ }
+ if (!io) {
+ diag_printf("Invalid 'mode': %s. Valid modes are:", mode_str);
+ for (io_tab = __RedBoot_LOAD_TAB__;
+ io_tab != &__RedBoot_LOAD_TAB_END__; io_tab++) {
+ diag_printf(" %s", io_tab->name);
+ }
+ err_printf("\n");
+ }
+ if (!io) {
+ return;
+ }
+ verbose &= io_tab->can_verbose;
+ if (io_tab->need_filename && !filename) {
+ diag_printf("File name required\n");
+ err_printf("usage: load %s\n", usage);
+ return;
+ }
+ } else {
+ char *which = "";
+ io_tab = (struct load_io_entry *)NULL; // Default
#ifdef CYGPKG_REDBOOT_NETWORKING
#ifdef CYGSEM_REDBOOT_NET_TFTP_DOWNLOAD
- which = "TFTP";
- io = &tftp_io;
+ which = "TFTP";
+ io = &tftp_io;
#elif defined(CYGSEM_REDBOOT_NET_HTTP_DOWNLOAD)
- which = "HTTP";
- io = &http_io;
+ which = "HTTP";
+ io = &http_io;
#endif
#endif
-#ifdef CYGPKG_REDBOOT_FILEIO
- // Make file I/O default if mounted
- if (fileio_mounted) {
- which = "file";
- io = &fileio_io;
- }
+#if 0 //def CYGPKG_REDBOOT_FILEIO
+ // Make file I/O default if mounted
+ if (fileio_mounted) {
+ which = "file";
+ io = &fileio_io;
+ }
#endif
- if (!io) {
+ if (!io) {
#ifdef CYGBLD_BUILD_REDBOOT_WITH_XYZMODEM
- which = "Xmodem";
- io = &xyzModem_io;
- verbose = false;
+ which = "Xmodem";
+ io = &xyzModem_io;
+ verbose = false;
#else
- diag_printf("No default protocol!\n");
- return;
+ err_printf("No default protocol!\n");
+ return;
#endif
- }
- diag_printf("Using default protocol (%s)\n", which);
- }
+ }
+ diag_printf("Using default protocol (%s)\n", which);
+ }
#ifdef CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS
- if (base_addr_set && !valid_address((unsigned char *)base)) {
- if (!verify_action("Specified address (%p) is not believed to be in RAM", (void*)base))
- return;
- spillover_ok = true;
- }
-#endif
- if (raw && !base_addr_set) {
- diag_printf("Raw load requires a memory address\n");
- return;
- }
- info.filename = filename;
- info.chan = chan;
- info.mode = io_tab ? io_tab->mode : 0;
+#ifdef CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ if (flash_addr_set && flash_verify_addr((unsigned char *)base)) {
+ if (!verify_action("Specified address (%p) is not believed to be in FLASH", (void*)base))
+ return;
+ spillover_ok = true;
+ }
+#endif
+ if (base_addr_set && !valid_address((unsigned char *)base)) {
+ if (!verify_action("Specified address (%p) is not believed to be in RAM", (void*)base))
+ return;
+ spillover_ok = true;
+ }
+#endif
+ if (raw && !(base_addr_set
+#ifdef CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ || flash_addr_set
+#endif
+ )) {
+ err_printf("Raw load requires a memory address\n");
+ return;
+ }
+ info.filename = filename;
+ info.chan = chan;
+ info.mode = io_tab ? io_tab->mode : 0;
#ifdef CYGPKG_REDBOOT_NETWORKING
- info.server = &host;
-#endif
- res = redboot_getc_init(&info, io, verbose, decompress);
- if (res < 0) {
- return;
- }
-
- // Stream open, process the data
- if (raw) {
- unsigned char *mp = (unsigned char *)base;
- unsigned char *addr_swap;
- err = 0;
- while ((res = redboot_getc()) >= 0) {
+ info.server = &host;
+#endif
+ res = redboot_getc_init(&info, io, verbose, decompress);
+ if (res < 0) {
+ return;
+ }
+#ifdef CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ flash_load_start();
+#endif
+ // Stream open, process the data
+ if (raw) {
+ unsigned char *mp = (unsigned char *)base;
+ unsigned char *addr_swap;
+ err = 0;
+ load_address = base;
+ while ((res = redboot_getc()) >= 0) {
#ifdef CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS
- if (!valid_address(mp) && !spillover_ok) {
- // Only if there is no need to stop the download
- // before printing output can we ask confirmation
- // questions.
- redboot_getc_terminate(true);
- diag_printf("*** Abort! RAW data spills over limit of user RAM at %p\n",(void*)mp);
- err = -1;
- break;
- }
-#endif
-
- /* In case of multicore and the core we wanna load the image for is not in the same endianness
- that the core we run redboot from, have to invert bytes on 16-bit boundary (16-bit memory)*/
- if(swap16bit){
- // addr is even, have to write char data to the last address
- if(((unsigned long)mp)%2){
- addr_swap=mp-1;
- *addr_swap = res;
- }
- // addr is odd, have to write char data to the next address
- else{
- addr_swap=mp+1;
- *addr_swap = res;
- }
- mp++;
- }
- else {
- *mp++ = res;
- }
- }
- end = (unsigned long) mp;
-
- // Save load base/top
- load_address = base;
- load_address_end = end;
- entry_address = base; // best guess
-
- redboot_getc_terminate(false);
- if (0 == err)
- diag_printf("Raw file loaded %p-%p, assumed entry at %p\n",
- (void *)base, (void *)(end - 1), (void*)base);
- } else {
- // Read initial header - to determine file [image] type
- for (i = 0; i < sizeof(type); i++) {
- if ((res = redboot_getc()) < 0) {
- err = getc_info.err;
- break;
- }
- type[i] = res;
- }
- if (res >= 0) {
- redboot_getc_rewind(); // Restore header to stream
- // Treat data as some sort of executable image
- if (strncmp(&type[1], "ELF", 3) == 0) {
- if(swap16bit) {
- end = load_elf_image(redboot_getc, base, true);
- }
- else {
- end = load_elf_image(redboot_getc, base, false);
- }
- } else if ((type[0] == 'S') &&
- ((type[1] >= '0') && (type[1] <= '9'))) {
- if(swap16bit) {
- end = load_srec_image(redboot_getc, base, true);
- }
- else {
- end = load_srec_image(redboot_getc, base, false);
- }
- } else {
- redboot_getc_terminate(true);
- diag_printf("Unrecognized image type: 0x%lx\n", *(unsigned long *)type);
- }
- }
- }
-
- redboot_getc_close(); // Clean up
- return;
+#ifdef CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ if (flash_addr_set && flash_verify_addr(mp) && !spillover_ok) {
+ // Only if there is no need to stop the download
+ // before printing output can we ask confirmation
+ // questions.
+ redboot_getc_terminate(true);
+ err_printf("*** Abort! RAW data spills over limit of FLASH at %p\n",(void*)mp);
+ err = -1;
+ break;
+ }
+#endif
+ if (base_addr_set && !valid_address(mp) && !spillover_ok) {
+ // Only if there is no need to stop the download
+ // before printing output can we ask confirmation
+ // questions.
+ redboot_getc_terminate(true);
+ err_printf("*** Abort! RAW data spills over limit of user RAM at %p\n",(void*)mp);
+ err = -1;
+ break;
+ }
+#endif
+
+ /* In case of multicore and the core we wanna load the image for is not in the same endianness
+ that the core we run redboot from, have to invert bytes on 16-bit boundary (16-bit memory)*/
+ if (swap16bit) {
+ // addr is even, have to write char data to the last address
+ if (((unsigned long)mp) % 2) {
+ addr_swap=mp-1;
+ *addr_swap = res;
+ } else {
+ // addr is odd, have to write char data to the next address
+ addr_swap = mp + 1;
+ *addr_swap = res;
+ }
+ mp++;
+ } else {
+#ifdef CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ if (flash_addr_set) {
+ flash_load_write(mp, res);
+ mp++;
+ res++;
+ } else
+#endif
+ *mp++ = res;
+ }
+ }
+ end = (unsigned long) mp;
+
+ // Save load base/top
+
+ load_address_end = end;
+ entry_address = base; // best guess
+
+ redboot_getc_terminate(false);
+ if (0 == err)
+ diag_printf("Raw file loaded %p-%p, assumed entry at %p\n",
+ (void *)load_address, (void *)(load_address_end - 1), (void*)entry_address);
+ } else {
+ // Read initial header - to determine file [image] type
+ for (i = 0; i < sizeof(type); i++) {
+ if ((res = redboot_getc()) < 0) {
+ err = getc_info.err;
+ break;
+ }
+ type[i] = res;
+ }
+ if (res >= 0) {
+ redboot_getc_rewind(); // Restore header to stream
+ // Treat data as some sort of executable image
+ if (strncmp(&type[1], "ELF", 3) == 0) {
+ if (swap16bit) {
+ end = load_elf_image(redboot_getc, base, true);
+ } else {
+ end = load_elf_image(redboot_getc, base, false);
+ }
+ } else if ((type[0] == 'S') &&
+ ((type[1] >= '0') && (type[1] <= '9'))) {
+ if (swap16bit) {
+ end = load_srec_image(redboot_getc, base, true);
+ } else {
+ end = load_srec_image(redboot_getc, base, false);
+ }
+ } else {
+ redboot_getc_terminate(true);
+ err_printf("Unrecognized image type: 0x%lx\n", *(unsigned long *)type);
+ }
+ }
+ }
+#ifdef CYGBLD_REDBOOT_LOAD_INTO_FLASH
+ flash_load_finish();
+#endif
+
+ redboot_getc_close(); // Clean up
+ return;
}
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004 Red Hat, Inc.
// Copyright (C) 2002, 2003, 2004 Gary Thomas
+// Copyright (C) 2003, 2004, 2005, 2006 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
-// Contributors: gthomas, tkoeller
+// Contributors: gthomas, tkoeller, eCosCentric
// Date: 2000-07-14
// Purpose:
// Description:
#ifdef HAL_PLATFORM_CPU
diag_printf("Platform: %s (%s) %s\n", HAL_PLATFORM_BOARD, HAL_PLATFORM_CPU, HAL_PLATFORM_EXTRA);
#endif
- diag_printf("Copyright (C) 2000, 2001, 2002, 2003, 2004 Red Hat, Inc.\n\n");
+ diag_printf("Copyright (C) 2000, 2001, 2002, 2003, 2004 Red Hat, Inc.\n");
+ diag_printf("Copyright (C) 2003, 2004, 2005, 2006 eCosCentric Limited\n\n");
diag_printf("RAM: %p-%p, ", (void*)ram_start, (void*)ram_end);
diag_printf("[%p-%p]", mem_segments[0].start, mem_segments[0].end);
diag_printf(" available\n");
//
static hal_jmp_buf error_jmpbuf;
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
-externC
-#endif
- void* volatile __mem_fault_handler;
+__externC void* volatile __mem_fault_handler;
static void error_handler(void)
{
hal_longjmp(error_jmpbuf, 1);
}
+#endif
//
console_selected = false;
#endif
console_echo = true;
- CYGACC_CALL_IF_DELAY_US((cyg_int32)2*100000);
ram_start = (unsigned char *)CYGMEM_REGION_ram;
ram_end = (unsigned char *)(CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE);
workspace_end = (unsigned char *)(CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE);
#endif
- if ( ram_end < workspace_end ) {
+ if (ram_end < workspace_end) {
// when *less* SDRAM is installed than the possible maximum,
// but the heap1 region remains greater...
workspace_end = ram_end;
}
+ workspace_end_init=workspace_end;
+
// Nothing has ever been loaded into memory
entry_address = (unsigned long)NO_MEMORY;
script_timeout = CYGNUM_REDBOOT_BOOT_SCRIPT_DEFAULT_TIMEOUT;
#endif
- for (init_entry = __RedBoot_INIT_TAB__; init_entry != &__RedBoot_INIT_TAB_END__; init_entry++) {
+ for (init_entry = __RedBoot_INIT_TAB__; init_entry != &__RedBoot_INIT_TAB_END__; init_entry++) {
(*init_entry->fun)();
}
#ifdef CYGFUN_REDBOOT_BOOT_SCRIPT
# ifdef CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT
if (!script) {
- script = CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT;
+ script = CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT;
}
# endif
if (script) {
- // Give the guy a chance to abort any boot script
- unsigned char *hold_script = script;
- int script_timeout_ms = script_timeout * CYGNUM_REDBOOT_BOOT_SCRIPT_TIMEOUT_RESOLUTION;
- diag_printf("== Executing boot script in %d.%03d seconds - enter ^C to abort\n",
- script_timeout_ms/1000, script_timeout_ms%1000);
- script = (unsigned char *)0;
- res = _GETS_CTRLC; // Treat 0 timeout as ^C
- while (script_timeout_ms >= CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT) {
- res = _rb_gets(line, sizeof(line), CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT);
- if (res >= _GETS_OK) {
- diag_printf("== Executing boot script in %d.%03d seconds - enter ^C to abort\n",
- script_timeout_ms/1000, script_timeout_ms%1000);
- continue; // Ignore anything but ^C
- }
- if (res != _GETS_TIMEOUT) break;
- script_timeout_ms -= CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT;
- }
- if (res == _GETS_CTRLC) {
- script = (unsigned char *)0; // Disable script
- } else {
- script = hold_script; // Re-enable script
- }
+ // Give the guy a chance to abort any boot script
+ unsigned char *hold_script = script;
+ int script_timeout_ms = script_timeout * CYGNUM_REDBOOT_BOOT_SCRIPT_TIMEOUT_RESOLUTION;
+ diag_printf("== Executing boot script in %d.%03d seconds - enter ^C to abort\n",
+ script_timeout_ms / 1000, script_timeout_ms % 1000);
+ script = NULL;
+ res = _GETS_CTRLC; // Treat 0 timeout as ^C
+ while (script_timeout_ms >= CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT) {
+ res = _rb_gets(line, sizeof(line), CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT);
+ if (res >= _GETS_OK) {
+ diag_printf("== Executing boot script in %d.%03d seconds - enter ^C to abort\n",
+ script_timeout_ms / 1000, script_timeout_ms % 1000);
+ } else if (res != _GETS_TIMEOUT) {
+ break;
+ }
+ script_timeout_ms -= CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT;
+ }
+ if (res == _GETS_CTRLC) {
+ script = NULL; // Disable script
+ } else {
+ script = hold_script; // Re-enable script
+ }
}
#endif
-
+ CYG_ASSERT(workspace_start < workspace_end,
+ "negative workspace size");
while (true) {
if (prompt) {
diag_printf("RedBoot> ");
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
// set up a temporary context that will take us to the trampoline
- HAL_THREAD_INIT_CONTEXT((CYG_ADDRWORD)workspace_end,
+ HAL_THREAD_INIT_CONTEXT(workspace_end,
breakpoint, trampoline,0);
// switch context to trampoline (get GDB stubs started)
#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
{
expand_aliases(line, sizeof(line));
- command = (char *)&line;
+ command = line;
if ((*command == '#') || (*command == '=')) {
// Special cases
if (*command == '=') {
}
} else {
while (strlen(command) > 0) {
- if ((cmd = parse(&command, &argc, &argv[0])) != (struct cmd *)0) {
+ if ((cmd = parse(&command, &argc, &argv[0])) != NULL) {
// Try to handle aborts - messy because of the stack unwinding...
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
__mem_fault_handler = error_handler;
+#endif
if (hal_setjmp(error_jmpbuf)) {
diag_printf("** command abort - illegal memory access?\n");
} else {
(cmd->fun)(argc, argv);
}
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
__mem_fault_handler = 0;
+#endif
} else {
diag_printf("** Error: Illegal command: \"%s\"\n", argv[0]);
}
}
if (show) {
diag_printf("%s\n %s %s %s\n", cmd->help, pre, cmd->str, cmd->usage);
- if ((cmd->sub_cmds != (struct cmd *)0) && (which != (char *)0)) {
+ if ((cmd->sub_cmds != NULL) && (which != NULL)) {
show_help(cmd->sub_cmds, cmd->sub_cmds_end, 0, cmd->str);
}
}
do_help(int argc, char *argv[])
{
struct cmd *cmd;
- char *which = (char *)0;
+ char *which = NULL;
- if (!scan_opts(argc, argv, 1, 0, 0, (void *)&which, OPTION_ARG_TYPE_STR, "<topic>")) {
+ if (!scan_opts(argc, argv, 1, 0, 0, &which, OPTION_ARG_TYPE_STR, "<topic>")) {
diag_printf("Invalid argument\n");
return;
}
void
do_go(int argc, char *argv[])
{
- int i, cur, num_options;
+ int i, cur, num_options = 0;
unsigned long entry;
unsigned long oldints;
bool wait_time_set;
char line[8];
hal_virtual_comm_table_t *__chan;
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
__mem_fault_handler = 0; // Let GDB handle any faults directly
+#endif
entry = entry_address; // Default from last 'load' operation
- init_opts(&opts[0], 'w', true, OPTION_ARG_TYPE_NUM,
- (void *)&wait_time, (bool *)&wait_time_set, "wait timeout");
- init_opts(&opts[1], 'c', false, OPTION_ARG_TYPE_FLG,
- (void *)&cache_enabled, (bool *)0, "go with caches enabled");
- num_options = 2;
+ init_opts(&opts[num_options++], 'w', true, OPTION_ARG_TYPE_NUM,
+ &wait_time, &wait_time_set, "wait timeout");
+ init_opts(&opts[num_options++], 'c', false, OPTION_ARG_TYPE_FLG,
+ &cache_enabled, NULL, "go with caches enabled");
#ifdef CYGPKG_IO_ETH_DRIVERS
- init_opts(&opts[2], 'n', false, OPTION_ARG_TYPE_FLG,
- (void *)&stop_net, (bool *)0, "go with network driver stopped");
- num_options++;
+ init_opts(&opts[num_options++], 'n', false, OPTION_ARG_TYPE_FLG,
+ &stop_net, NULL, "go with network driver stopped");
#endif
CYG_ASSERT(num_options <= NUM_ELEMS(opts), "Too many options");
- if (!scan_opts(argc, argv, 1, opts, num_options, (void *)&entry, OPTION_ARG_TYPE_NUM, "starting address"))
- {
+ if (!scan_opts(argc, argv, 1, opts, num_options, &entry,
+ OPTION_ARG_TYPE_NUM, "starting address")) {
return;
}
if (entry == (unsigned long)NO_MEMORY) {
- diag_printf("No entry point known - aborted\n");
+ err_printf("No entry point known - aborted\n");
return;
}
if (wait_time_set) {
int script_timeout_ms = wait_time * 1000;
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
unsigned char *hold_script = script;
- script = (unsigned char *)0;
+ script = NULL;
#endif
diag_printf("About to start execution at %p - abort with ^C within %d seconds\n",
(void *)entry, wait_time);
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
// set up a temporary context that will take us to the trampoline
- HAL_THREAD_INIT_CONTEXT((CYG_ADDRWORD)workspace_end,
+ HAL_THREAD_INIT_CONTEXT(workspace_end,
entry, trampoline, 0);
// switch context to trampoline
#endif
init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM,
- (void *)&new_rate, (bool *)&new_rate_set, "new baud rate");
+ &new_rate, &new_rate_set, "new baud rate");
if (!scan_opts(argc, argv, 1, opts, 1, 0, 0, "")) {
return;
}
}
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
opt.type = CONFIG_INT;
- opt.enable = (char *)0;
+ opt.enable = NULL;
opt.enable_sense = 1;
opt.key = "console_baud_rate";
opt.dflt = new_rate;
int seg;
for (seg = 0; seg < CYGBLD_REDBOOT_MAX_MEM_SEGMENTS; seg++) {
- if (mem_segments[seg].start != NO_MEMORY) {
+ if (mem_segments[seg].start != NO_MEMORY) {
if ((addr >= mem_segments[seg].start) && (addr < mem_segments[seg].end)) {
return true;
}
#endif
static void
-bootp_handler(udp_socket_t *skt, char *buf, int len,
+bootp_handler(udp_socket_t *skt, void *buf, int len,
ip_route_t *src_route, word src_port)
{
bootp_header_t *b;
unsigned char *p, expected = 0;
#endif
- b = (bootp_header_t *)buf;
+ b = buf;
if (bp_info) {
memset(bp_info,0,sizeof *bp_info);
if (len > sizeof *bp_info)
#define AddOption(p,d) do {memcpy(p,d,sizeof d); p += sizeof d;} while (0)
-static int get_xid()
+static int get_xid(void)
{
#if CYGINT_ISO_RAND
return rand();
#endif
int txSize;
bool abort = false;
- int xid;
#ifdef CYGSEM_REDBOOT_NETWORKING_DHCP
dhcpState = DHCP_NONE;
__udp_send((char *)&b, txSize, &r, IPPORT_BOOTPS, IPPORT_BOOTPC);
// If we're retrying, inform the user
- if (retry == (MAX_RETRIES-1))
+ if (retry == (MAX_RETRIES - 1))
diag_printf("... waiting for BOOTP information\n");
do {
memcpy(&__bootp_dns_addr, p, 4);
__bootp_dns_set = 1;
break;
-#endif
+#ifdef CYGPKG_REDBOOT_NETWORKING_DNS_DHCP_DOMAIN
+ case TAG_DOMAIN_NAME:
+ if(optlen < sizeof(__bootp_dns_domain)) {
+ memcpy(__bootp_dns_domain, p, optlen);
+ __bootp_dns_domain[optlen] = '\0';
+ __bootp_dns_domain_set = 1;
+ } else {
+ diag_printf("DNS domain name too long\n");
+ }
+ break;
+#endif //CYGPKG_REDBOOT_NETWORKING_DNS_DHCP_DOMAIN
+#endif //CYGPKG_REDBOOT_NETWORKING_DNS
default:
break;
}
return 0;
}
#endif
- if (_rb_break(1)) {
- // The user typed ^C on the console
- abort = true;
- break;
- }
- start--; /* account for time spent in _rb_break() */
+ if (retry < MAX_RETRIES) {
+ if (_rb_break(1)) {
+ // The user typed ^C on the console
+ abort = true;
+ break;
+ }
+ start--; /* account for time spent in _rb_break() */
+ }
} while ((int)(MS_TICKS_DELAY() - start) < RETRY_TIME);
} while (!abort && (retry-- > 0));
CONFIG_IP,
0
);
+
+RedBoot_config_option("DNS domain name",
+ dns_domain,
+ ALWAYS_ENABLED, true,
+ CONFIG_STRING,
+ 0
+ );
#endif
/* So we remember which ports have been used */
struct in_addr __bootp_dns_addr;
cyg_bool __bootp_dns_set = false;
+/* DNS domain name possibly returned from bootp */
+#ifdef CYGPKG_REDBOOT_NETWORKING_DNS_DHCP_DOMAIN
+char __bootp_dns_domain[CYGNUM_REDBOOT_NETWORK_DNS_DOMAIN_BUFSIZE];
+cyg_bool __bootp_dns_domain_set = false;
+#endif
+
struct sockaddr_in server;
/* static buffers so we can make do without malloc */
void
show_dns(void)
{
- diag_printf(", DNS server IP: %s", inet_ntoa((in_addr_t *)&server.sin_addr));
+ diag_printf("\nDNS server IP: %s, DNS domain name: %s",
+ inet_ntoa((in_addr_t *)&server.sin_addr),
+ domainname);
if (0 == server.sin_addr.s_addr) {
s = -1;
}
int
redboot_dns_res_init(void)
{
+#ifdef CYGPKG_REDBOOT_NETWORKING_DNS_FCONFIG_DOMAIN
+ char *dns_domain = NULL;
+#endif
memset((char *)&server, 0, sizeof(server));
server.sin_len = sizeof(server);
server.sin_family = AF_INET;
server.sin_port = htons(DOMAIN_PORT);
cyg_drv_mutex_init(&dns_mutex);
- /* If we got a DNS server address from the DHCP/BOOTP, then use that address */
+ /* Set the default DNS domain first, so that it can be overwritten
+ latter */
+#ifdef CYGPKG_REDBOOT_NETWORKING_DNS_DEFAULT_DOMAIN
+ setdomainname(__Xstr(CYGPKG_REDBOOT_NETWORKING_DNS_DEFAULT_DOMAIN),
+ strlen(__Xstr(CYGPKG_REDBOOT_NETWORKING_DNS_DEFAULT_DOMAIN)));
+#endif
+ /* Set the domain name from flash so that DHCP can later
+ overwrite it. */
+#ifdef CYGPKG_REDBOOT_NETWORKING_DNS_FCONFIG_DOMAIN
+ flash_get_config("dns_domain", &dns_domain, CONFIG_STRING);
+ if(dns_domain != NULL && dns_domain[0] != '\0')
+ setdomainname(dns_domain, strlen(dns_domain));
+#endif
+
+ /* If we got a DNS server address from the DHCP/BOOTP, then use
+ that address */
if ( __bootp_dns_set ) {
- memcpy(&server.sin_addr, &__bootp_dns_addr, sizeof(__bootp_dns_addr) );
- s = 0;
+ memcpy(&server.sin_addr, &__bootp_dns_addr,
+ sizeof(__bootp_dns_addr) );
+
+#ifdef CYGPKG_REDBOOT_NETWORKING_DNS_DHCP_DOMAIN
+ if(__bootp_dns_domain_set)
+ setdomainname(__bootp_dns_domain, strlen(__bootp_dns_domain));
+#endif
+ /* server config is valid */
+ s = 0;
}
else {
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
ip_addr_t dns_ip;
flash_get_config("dns_ip", &dns_ip, CONFIG_IP);
- if (dns_ip[0] == 0 && dns_ip[1] == 0 && dns_ip[2] == 0 && dns_ip[3] == 0)
+ if (dns_ip[0] == 0 && dns_ip[1] == 0 &&
+ dns_ip[2] == 0 && dns_ip[3] == 0)
return -1;
memcpy(&server.sin_addr, &dns_ip, sizeof(dns_ip));
/* server config is valid */
s = 0;
}
#else
- // Use static configuration
- set_dns(__Xstr(CYGPKG_REDBOOT_NETWORKING_DNS_IP));
+ // Use static configuration. If CYGPKG_REDBOOT_NETWORKING_DNS_IP
+ // is valid s will set set as a side effect.
+ set_dns(__Xstr(CYGPKG_REDBOOT_NETWORKING_DNS_IP));
#endif
}
}
int
-http_stream_read(char *buf,
+http_stream_read(void *buf,
int len,
int *err)
{
case 400:
*err = HTTP_BADREQ;
break;
+ case 403:
+ *err = HTTP_FORBIDDEN;
+ break;
case 404:
*err = HTTP_NOFILE;
break;
memcpy(buf, s->bufp, cnt);
s->avail -= cnt;
s->bufp += cnt;
- buf += cnt;
+ buf = (char *)buf + cnt;
total += cnt;
len -= cnt;
}
return "Can't connect to host";
case HTTP_IO:
return "I/O error";
+ case HTTP_FORBIDDEN:
+ return "Forbidden (check permissions)";
}
return errmsg;
}
// Special characters used by Telnet - must be interpretted here
#define TELNET_IAC 0xFF // Interpret as command (escape)
#define TELNET_IP 0xF4 // Interrupt process
-#define TELNET_WONT 0xFC // I Won't do it
+#define TELNET_WILL 0xFB // I Will do XXX
+#define TELNET_WONT 0xFC // I Won't do XXX
#define TELNET_DO 0xFD // Will you XXX
+#define TELNET_DONT 0xFE // Don't you XXX
#define TELNET_TM 0x06 // Time marker (special DO/WONT after IP)
static cyg_bool
net_io_putc(__ch_data, TELNET_WONT);
net_io_putc(__ch_data, esc);
return false; // Ignore this whole thing!
+ case TELNET_WILL:
+ // Telnet WILL option
+ while (!_net_io_getc_nonblock(__ch_data, &esc)) ;
+ // Respond with DONT option
+ net_io_putc(__ch_data, TELNET_IAC);
+ net_io_putc(__ch_data, TELNET_DONT);
+ net_io_putc(__ch_data, esc);
+ return false; // Ignore this whole thing!
default:
return false;
}
CYG_HAL_TABLE_BEGIN( __NETDEVTAB__, netdev );
CYG_HAL_TABLE_END( __NETDEVTAB_END__, netdev );
-RedBoot_init(net_init, RedBoot_INIT_LAST);
+RedBoot_init(net_init, RedBoot_INIT_NET);
static void
show_addrs(void)
unsigned index;
struct eth_drv_sc *primary_net = (struct eth_drv_sc *)0;
#if defined(CYGHWR_NET_DRIVERS) && (CYGHWR_NET_DRIVERS > 1)
- char *default_devname;
+ char *default_devname = CYGDAT_REDBOOT_DEFAULT_NETWORK_DEVICE;
int default_index;
#endif
#ifdef CYGDAT_REDBOOT_DEFAULT_BOOTP_SERVER_IP_ADDR
primary_net = __local_enet_sc;
} else
#endif
-#endif
+#endif // (CYGHWR_NET_DRIVERS) && (CYGHWR_NET_DRIVERS > 1)
for (index = 0; (t = net_devtab_entry(index)) != NULL; index++) {
#ifdef CYGSEM_REDBOOT_NETWORK_INIT_ONE_DEVICE
if (index == default_index)
primary_net = __local_enet_sc;
}
#if defined(CYGHWR_NET_DRIVERS) && (CYGHWR_NET_DRIVERS > 1)
+# ifdef CYGSEM_REDBOOT_NETWORK_INIT_ONE_DEVICE
+ break;
+# else
if (index == default_index) {
primary_net = __local_enet_sc;
}
+# endif // CYGSEM_REDBOOT_NETWORK_INIT_ONE_DEVICE
#endif
}
}
have_net = true; // Assume values in FLASH were OK
// Tell the world that we are using this fixed IP address
if (__arp_request((ip_addr_t *)__local_ip_addr, &enet_addr, 1) >= 0) {
- diag_printf("Warning: IP address %s in use\n", inet_ntoa((in_addr_t *)&__local_ip_addr));
+ diag_printf("Warning: IP address %s in use\n",
+ inet_ntoa((in_addr_t *)&__local_ip_addr));
}
}
}
static char usage[] = "[-b] [-l <local_ip_address>[/<mask_len>]] [-h <server_address>]"
#ifdef CYGPKG_REDBOOT_NETWORKING_DNS
- " [-d <dns_server_address]"
+ " [-d <dns_server_address>]"
+#ifdef CYGPKG_REDBOOT_NETWORKING_DNS_FCONFIG_DOMAIN
+ " [-D <dns_domain_name>]"
+#endif
#endif
;
void
do_ip_addr(int argc, char *argv[])
{
- struct option_info opts[4];
+ struct option_info opts[5];
char *ip_addr, *host_addr;
bool ip_addr_set, host_addr_set;
bool do_bootp = false;
#ifdef CYGPKG_REDBOOT_NETWORKING_DNS
char *dns_addr;
bool dns_addr_set;
+#ifdef CYGPKG_REDBOOT_NETWORKING_DNS_FCONFIG_DOMAIN
+ char *dns_domain;
+ bool dns_domain_set;
+#endif
#endif
int num_opts;
+
+ if (!have_net) {
+ net_init();
+ }
+ if (!have_net) {
+ diag_printf("Sorry, networking is not available.\n");
+ return;
+ }
init_opts(&opts[0], 'l', true, OPTION_ARG_TYPE_STR,
- (void *)&ip_addr, (bool *)&ip_addr_set, "local IP address");
+ &ip_addr, &ip_addr_set, "local IP address");
init_opts(&opts[1], 'h', true, OPTION_ARG_TYPE_STR,
- (void *)&host_addr, (bool *)&host_addr_set, "default server address");
+ &host_addr, &host_addr_set, "default server address");
init_opts(&opts[2], 'b', false, OPTION_ARG_TYPE_FLG,
&do_bootp, 0, "use BOOTP");
num_opts = 3;
init_opts(&opts[num_opts], 'd', true, OPTION_ARG_TYPE_STR,
(void *)&dns_addr, (bool *)&dns_addr_set, "DNS server address");
num_opts++;
+#ifdef CYGPKG_REDBOOT_NETWORKING_DNS_FCONFIG_DOMAIN
+ init_opts(&opts[num_opts], 'D', true, OPTION_ARG_TYPE_STR,
+ (void *)&dns_domain, (bool *)&dns_domain_set, "DNS domain");
+ num_opts++;
+#endif
#endif
-
CYG_ASSERT(num_opts <= NUM_ELEMS(opts), "Too many options");
if (!scan_opts(argc, argv, 1, opts, num_opts, 0, 0, "")) {
char *slash_pos;
/* see if the (optional) mask length was given */
if( (slash_pos = strchr(ip_addr, '/')) ) {
- unsigned long mask_len;
+ unsigned long mask_len;
unsigned long mask;
*slash_pos = '\0';
slash_pos++;
- if (!parse_num(slash_pos, &mask_len, 0, 0) ||
+ if( !parse_num(slash_pos, &mask_len, 0, 0) ||
mask_len <= 0 || mask_len > 32 ) {
diag_printf("Invalid mask length: %s\n", slash_pos);
return;
if (dns_addr_set) {
set_dns(dns_addr);
}
+#ifdef CYGPKG_REDBOOT_NETWORKING_DNS_FCONFIG_DOMAIN
+ if (dns_domain_set) {
+ setdomainname(dns_domain, strlen(dns_domain));
+ }
+#endif
#endif
show_addrs();
if (!have_net) {
//==========================================================================
//
-// ping.c
+// ping.c
//
-// Network utility - ping
+// Network utility - ping
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
-// Author(s): gthomas
+// Author(s): gthomas
// Contributors: gthomas
-// Date: 2001-01-22
-// Purpose:
-// Description:
-//
+// Date: 2001-01-22
+// Purpose:
+// Description:
+//
// This code is part of RedBoot (tm).
//
//####DESCRIPTIONEND####
#else
static void do_ping(int argc, char *argv[]);
-RedBoot_cmd("ping",
- "Network connectivity test",
- "[-v] [-n <count>] [-l <length>] [-t <timeout>] [-r <rate>]\n"
- " [-i <IP_addr>] -h <IP_addr>",
- do_ping
+RedBoot_cmd("ping",
+ "Network connectivity test",
+ "[-v] [-n <count>] [-l <length>] [-t <timeout>] [-r <rate>]\n"
+ " [-i <IP_addr>] -h <IP_addr>",
+ do_ping
);
static bool icmp_received;
icmp->type = ICMP_TYPE_ECHOREPLY;
icmp->checksum = 0;
- cksum = __sum((word *)icmp, pkt->pkt_bytes, 0);
+ cksum = __sum((word *)icmp, pkt->pkt_bytes, 0);
icmp->checksum = htons(cksum);
- __ip_send(pkt, IP_PROTO_ICMP, src_route);
+ __ip_send(pkt, IP_PROTO_ICMP, src_route);
} else if (icmp->type == ICMP_TYPE_ECHOREPLY) {
- memcpy(&hold_hdr, icmp, sizeof(*icmp));
- icmp_received = true;
+ memcpy(&hold_hdr, icmp, sizeof(*icmp));
+ icmp_received = true;
}
}
+#include <cyg/hal/hal_soc.h>
static void
do_ping(int argc, char *argv[])
{
struct option_info opts[7];
long count, timeout, length, rate, start_time, end_time, timer, received, tries;
char *local_ip_addr, *host_ip_addr;
- bool local_ip_addr_set, host_ip_addr_set, count_set,
- timeout_set, length_set, rate_set, verbose;
+ bool local_ip_addr_set, host_ip_addr_set, count_set,
+ timeout_set, length_set, rate_set, verbose;
struct sockaddr_in local_addr, host_addr;
ip_addr_t hold_addr;
icmp_header_t *icmp;
unsigned short cksum;
ip_route_t dest_ip;
- init_opts(&opts[0], 'n', true, OPTION_ARG_TYPE_NUM,
- (void *)&count, (bool *)&count_set, "<count> - number of packets to test");
- init_opts(&opts[1], 't', true, OPTION_ARG_TYPE_NUM,
- (void *)&timeout, (bool *)&timeout_set, "<timeout> - max #ms per packet [rount trip]");
- init_opts(&opts[2], 'i', true, OPTION_ARG_TYPE_STR,
- (void *)&local_ip_addr, (bool *)&local_ip_addr_set, "local IP address");
- init_opts(&opts[3], 'h', true, OPTION_ARG_TYPE_STR,
- (void *)&host_ip_addr, (bool *)&host_ip_addr_set, "host name or IP address");
- init_opts(&opts[4], 'l', true, OPTION_ARG_TYPE_NUM,
- (void *)&length, (bool *)&length_set, "<length> - size of payload");
- init_opts(&opts[5], 'v', false, OPTION_ARG_TYPE_FLG,
- (void *)&verbose, (bool *)0, "verbose operation");
- init_opts(&opts[6], 'r', true, OPTION_ARG_TYPE_NUM,
- (void *)&rate, (bool *)&rate_set, "<rate> - time between packets");
- if (!scan_opts(argc, argv, 1, opts, 7, (void **)0, 0, "")) {
- diag_printf("PING - Invalid option specified\n");
- return;
- }
+ init_opts(&opts[0], 'n', true, OPTION_ARG_TYPE_NUM,
+ &count, &count_set, "<count> - number of packets to test");
+ init_opts(&opts[1], 't', true, OPTION_ARG_TYPE_NUM,
+ &timeout, &timeout_set, "<timeout> - max #ms per packet [rount trip]");
+ init_opts(&opts[2], 'i', true, OPTION_ARG_TYPE_STR,
+ &local_ip_addr, &local_ip_addr_set, "local IP address");
+ init_opts(&opts[3], 'h', true, OPTION_ARG_TYPE_STR,
+ &host_ip_addr, &host_ip_addr_set, "host name or IP address");
+ init_opts(&opts[4], 'l', true, OPTION_ARG_TYPE_NUM,
+ &length, &length_set, "<length> - size of payload");
+ init_opts(&opts[5], 'v', false, OPTION_ARG_TYPE_FLG,
+ &verbose, NULL, "verbose operation");
+ init_opts(&opts[6], 'r', true, OPTION_ARG_TYPE_NUM,
+ &rate, &rate_set, "<rate> - time between packets");
+ if (!scan_opts(argc, argv, 1, opts, 7, NULL, 0, "")) {
+ diag_printf("PING - Invalid option specified\n");
+ return;
+ }
// Set defaults; this has to be done _after_ the scan, since it will
// have destroyed all values not explicitly set.
if (local_ip_addr_set) {
- if (!_gethostbyname(local_ip_addr, (in_addr_t *)&local_addr)) {
- diag_printf("PING - Invalid local name: %s\n", local_ip_addr);
- return;
- }
+ if (!_gethostbyname(local_ip_addr, (in_addr_t *)&local_addr)) {
+ diag_printf("PING - Invalid local name: %s\n", local_ip_addr);
+ return;
+ }
} else {
- memcpy((in_addr_t *)&local_addr, __local_ip_addr, sizeof(__local_ip_addr));
+ memcpy((in_addr_t *)&local_addr, __local_ip_addr, sizeof(__local_ip_addr));
}
if (host_ip_addr_set) {
- if (!_gethostbyname(host_ip_addr, (in_addr_t *)&host_addr)) {
- diag_printf("PING - Invalid host name: %s\n", host_ip_addr);
- return;
- }
- if (__arp_lookup((ip_addr_t *)&host_addr.sin_addr, &dest_ip) < 0) {
- diag_printf("PING: Cannot reach server '%s' (%s)\n",
- host_ip_addr, inet_ntoa((in_addr_t *)&host_addr));
- return;
- }
+ if (!_gethostbyname(host_ip_addr, (in_addr_t *)&host_addr)) {
+ diag_printf("PING - Invalid host name: %s\n", host_ip_addr);
+ return;
+ }
+ if (__arp_lookup((ip_addr_t *)&host_addr.sin_addr, &dest_ip) < 0) {
+ diag_printf("PING: Cannot reach server '%s' (%s)\n",
+ host_ip_addr, inet_ntoa((in_addr_t *)&host_addr));
+ return;
+ }
} else {
- diag_printf("PING - host name or IP address required\n");
- return;
+ diag_printf("PING - host name or IP address required\n");
+ return;
}
-#define DEFAULT_LENGTH 64
-#define DEFAULT_COUNT 10
-#define DEFAULT_TIMEOUT 1000
-#define DEFAULT_RATE 1000
+#define DEFAULT_LENGTH 64
+#define DEFAULT_COUNT 10
+#define DEFAULT_TIMEOUT 1000
+#define DEFAULT_RATE 1000
if (!rate_set) {
- rate = DEFAULT_RATE;
+ rate = DEFAULT_RATE;
}
if (!length_set) {
- length = DEFAULT_LENGTH;
+ length = DEFAULT_LENGTH;
}
if ((length < 64) || (length > 1400)) {
- diag_printf("Invalid length specified: %ld\n", length);
- return;
+ diag_printf("Invalid length specified: %ld\n", length);
+ return;
}
if (!count_set) {
- count = DEFAULT_COUNT;
+ count = DEFAULT_COUNT;
}
if (!timeout_set) {
- timeout = DEFAULT_TIMEOUT;
+ timeout = DEFAULT_TIMEOUT;
}
// Note: two prints here because 'inet_ntoa' returns a static pointer
diag_printf("Network PING - from %s",
- inet_ntoa((in_addr_t *)&local_addr));
+ inet_ntoa((in_addr_t *)&local_addr));
diag_printf(" to %s\n",
- inet_ntoa((in_addr_t *)&host_addr));
- received = 0;
+ inet_ntoa((in_addr_t *)&host_addr));
+ received = 0;
__icmp_install_listener(handle_icmp);
// Save default "local" address
memcpy(hold_addr, __local_ip_addr, sizeof(hold_addr));
for (tries = 0; tries < count; tries++) {
- // The network stack uses the global variable '__local_ip_addr'
- memcpy(__local_ip_addr, &local_addr, sizeof(__local_ip_addr));
- // Build 'ping' request
- if ((pkt = __pktbuf_alloc(ETH_MAX_PKTLEN)) == NULL) {
- // Give up if no packets - something is wrong
- break;
- }
-
- icmp = pkt->icmp_hdr;
- ip = pkt->ip_hdr;
- pkt->pkt_bytes = length + sizeof(icmp_header_t);
+ // The network stack uses the global variable '__local_ip_addr'
+ memcpy(__local_ip_addr, &local_addr, sizeof(__local_ip_addr));
+ // Build 'ping' request
+ if ((pkt = __pktbuf_alloc(ETH_MAX_PKTLEN)) == NULL) {
+ // Give up if no packets - something is wrong
+ break;
+ }
+
+ icmp = pkt->icmp_hdr;
+ ip = pkt->ip_hdr;
+ pkt->pkt_bytes = length + sizeof(icmp_header_t);
icmp->type = ICMP_TYPE_ECHOREQUEST;
- icmp->code = 0;
+ icmp->code = 0;
icmp->checksum = 0;
- icmp->seqnum = htons(tries+1);
- cksum = __sum((word *)icmp, pkt->pkt_bytes, 0);
+ icmp->seqnum = htons(tries+1);
+ cksum = __sum((word *)icmp, pkt->pkt_bytes, 0);
icmp->checksum = htons(cksum);
-
- memcpy(ip->source, (in_addr_t *)&local_addr, sizeof(ip_addr_t));
- memcpy(ip->destination, (in_addr_t *)&host_addr, sizeof(ip_addr_t));
- ip->protocol = IP_PROTO_ICMP;
- ip->length = htons(pkt->pkt_bytes);
-
- __ip_send(pkt, IP_PROTO_ICMP, &dest_ip);
- __pktbuf_free(pkt);
-
- start_time = MS_TICKS();
- timer = start_time + timeout;
- icmp_received = false;
- while (!icmp_received && (MS_TICKS_DELAY() < timer)) {
- if (_rb_break(1)) {
- goto abort;
- }
+
+ memcpy(ip->source, (in_addr_t *)&local_addr, sizeof(ip_addr_t));
+ memcpy(ip->destination, (in_addr_t *)&host_addr, sizeof(ip_addr_t));
+ ip->protocol = IP_PROTO_ICMP;
+ ip->length = htons(pkt->pkt_bytes);
+
+ __ip_send(pkt, IP_PROTO_ICMP, &dest_ip);
+ __pktbuf_free(pkt);
+
+ start_time = MS_TICKS();
+ timer = start_time + timeout;
+ icmp_received = false;
+ while (!icmp_received && (MS_TICKS_DELAY() < timer)) {
+ if (_rb_break(1)) {
+ goto abort;
+ }
timer--; /* account for time spent in _rb_break() */
- __enet_poll();
- }
- end_time = MS_TICKS();
-
- timer = MS_TICKS() + rate;
- while (MS_TICKS_DELAY() < timer) {
- if (_rb_break(1)) {
- goto abort;
- }
+ __enet_poll();
+ }
+ end_time = MS_TICKS();
+
+ timer = MS_TICKS() + rate;
+ while (MS_TICKS_DELAY() < timer) {
+ if (_rb_break(1)) {
+ goto abort;
+ }
timer--; /* account for time spent in _rb_break() */
__enet_poll();
- }
-
- if (icmp_received) {
- received++;
- if (verbose) {
- diag_printf(" seq: %d, time: %ld (ticks)\n",
- ntohs(hold_hdr.seqnum), end_time-start_time);
- }
- }
+ }
+
+ if (icmp_received) {
+ received++;
+ if (verbose) {
+ diag_printf(" seq: %d, time: %ld (ticks)\n",
+ ntohs(hold_hdr.seqnum), end_time - start_time);
+ }
+ }
}
abort:
__icmp_remove_listener();
* Read up to 'len' bytes without blocking.
*/
int
-__tcp_read(tcp_socket_t *s, char *buf, int len)
+__tcp_read(tcp_socket_t *s, void *buf, int len)
{
int nread;
pktbuf_t *pkt;
BSPLOG(bsp_log("tcp_read: read %d bytes. pkt[%x] freed.\n",
s->rxcnt, s->rxlist));
nread += s->rxcnt;
- buf += s->rxcnt;
+ buf = (char *)buf + s->rxcnt;
len -= s->rxcnt;
/* setup for next packet in list */
* Write up to 'len' bytes without blocking
*/
int
-__tcp_write(tcp_socket_t *s, char *buf, int len)
+__tcp_write(tcp_socket_t *s, void *buf, int len)
{
tcp_header_t *tcp = s->pkt.tcp_hdr;
* If connection collapses, return -1
*/
int
-__tcp_write_block(tcp_socket_t *s, char *buf, int len)
+__tcp_write_block(tcp_socket_t *s, void *buf, int len)
{
int total = 0;
int n;
n = __tcp_write(s, buf, len);
if (n > 0) {
len -= n;
- buf += n;
+ buf = (char *)buf + n;
+ total += n;
}
__tcp_poll();
}
while (*fp) *cp++ = *fp++;
*cp++ = '\0';
- memset((char *)&tftp_stream.local_addr, 0, sizeof(tftp_stream.local_addr));
+ memset(&tftp_stream.local_addr, 0, sizeof(tftp_stream.local_addr));
tftp_stream.local_addr.sin_family = AF_INET;
tftp_stream.local_addr.sin_addr.s_addr = htonl(INADDR_ANY);
tftp_stream.local_addr.sin_port = htons(get_port++);
struct tftphdr *hdr = (struct tftphdr *)tftp_stream.data;
if (strlen(msg) > (SEGSIZE-1)) {
- *(msg + SEGSIZE) = '\0';
+ *(msg + SEGSIZE) = 0;
}
if (tftp_stream.packets_received > 0) {
hdr->th_opcode = htons(ERROR);
hdr->th_code = code;
- strcpy((char*)&hdr->th_data, msg);
+ strcpy((char *)&hdr->th_data, msg);
if (__udp_sendto(tftp_stream.data, (5 + strlen(msg)),
&tftp_stream.from_addr, &tftp_stream.local_addr) < 0) {
// Problem sending ACK
}
int
-tftp_stream_read(char *buf,
+tftp_stream_read(void *buf,
int len,
int *err)
{
size = tftp_stream.avail;
if (size > (len - total_bytes)) size = len - total_bytes;
memcpy(buf, tftp_stream.bufp, size);
- buf += size;
+ buf = (char *)buf + size;
tftp_stream.bufp += size;
tftp_stream.avail -= size;
total_bytes += size;
prev = NULL;
t = tmr_list;
while (t) {
- if ((MS_TICKS_DELAY() - t->start) >= t->delay) {
+ if ((MS_TICKS() - t->start) >= t->delay) {
/* remove it before calling handler */
if (prev)
* Send a UDP packet.
*/
int
-__udp_send(char *buf, int len, ip_route_t *dest_ip,
+__udp_send(void *buf, int len, ip_route_t *dest_ip,
word dest_port, word src_port)
{
pktbuf_t *pkt;
}
int
-__udp_sendto(char *data, int len, struct sockaddr_in *server,
+__udp_sendto(void *data, int len, struct sockaddr_in *server,
struct sockaddr_in *local)
{
ip_route_t rt;
static struct sockaddr_in *recvfrom_server;
static void
-__udp_recvfrom_handler(udp_socket_t *skt, char *buf, int len,
+__udp_recvfrom_handler(udp_socket_t *skt, void *buf, int len,
ip_route_t *src_route, word src_port)
{
if (recvfrom_server == NULL || recvfrom_buf == NULL)
if (recvfrom_server) {
recvfrom_server->sin_port = htons(src_port);
memcpy(&recvfrom_server->sin_addr, &src_route->ip_addr, sizeof(src_route->ip_addr));
- recvfrom_buf = (char *)0; // Tell reader we got a packet
+ recvfrom_buf = NULL; // Tell reader we got a packet
} else {
diag_printf("udp_recvfrom - dropped packet of %d bytes\n", len);
}
}
int
-__udp_recvfrom(char *data, int len, struct sockaddr_in *server,
+__udp_recvfrom(void *data, int len, struct sockaddr_in *server,
struct sockaddr_in *local, struct timeval *timo)
{
int res, my_port, total_ms;
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2004, 2005, 2006 eCosCentric Limited
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
-// Contributors: gthomas
+// Contributors: gthomas, eCosCentric
// Date: 2000-07-14
// Purpose:
// Description:
}
}
+//
+// Handle illegal memory accesses (and other abort conditions)
+//
+static hal_jmp_buf error_jmpbuf;
+static cyg_bool redboot_exec_call = false;
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+__externC void* volatile __mem_fault_handler;
+
+static void error_handler(void)
+{
+ hal_longjmp(error_jmpbuf, 1);
+}
+#endif
+
+// Routine to allow code to invoke RedBoot commands. This is useful
+// during initialization and in platform specific code.
+//
+// Call it like this:
+//
+// result = redboot_exec( "load", "-m", "file", "foo", 0 );
+//
+// Note the terminating zero. The result will be zero if the command
+// succeeded, and <0 if something went wrong.
+
+#define ARGV_MAX 20
+int redboot_exec( char *command, ... )
+{
+ int argc;
+ char *argv[ARGV_MAX+1];
+ va_list ap;
+ struct cmd *cmd;
+ int result = 0;
+
+ va_start(ap, command);
+
+ argv[0] = command;
+ for( argc = 1; argc < ARGV_MAX; argc++ )
+ {
+ char *arg = va_arg(ap, char *);
+ if( arg == 0 )
+ break;
+ argv[argc] = arg;
+ }
+ argv[argc] = NULL;
+
+ if(( cmd = cmd_search(__RedBoot_CMD_TAB__, &__RedBoot_CMD_TAB_END__, command) ))
+ {
+ // Try to handle aborts - messy because of the stack unwinding...
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ __mem_fault_handler = error_handler;
+#endif
+ redboot_exec_call = true;
+ if (hal_setjmp(error_jmpbuf))
+ result = -1;
+ else
+ (cmd->fun)(argc, argv);
+
+ redboot_exec_call = false;
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ __mem_fault_handler = 0;
+#endif
+ }
+ else
+ result = -1;
+
+ va_end(ap);
+
+ return result;
+}
+
+externC void err_printf(const char *fmt, ... )
+{
+ va_list ap;
+
+ va_start(ap, fmt);
+
+ diag_vprintf( fmt, ap );
+
+ va_end(ap);
+
+ // If we are not in redboot_exec() just return as usual. If we are
+ // inside a call to redboot_exec(), longjump out to terminate the command.
+
+ if( redboot_exec_call )
+ {
+ diag_printf("err_printf: aborting command\n");
+ hal_longjmp(error_jmpbuf, 1);
+ }
+}
+
+
// Option processing
// Initialize option table entry (required because these entries
struct option_info *opt;
if (def_arg && (def_arg_type == OPTION_ARG_TYPE_STR)) {
- *(char **)def_arg = (char *)0;
+ *(char **)def_arg = NULL;
}
opt = opts;
for (j = 0; j < num_opts; j++, opt++) {
for (j = 0; j < num_opts; j++, opt++) {
if (c == opt->flag) {
if (opt->arg_set && *opt->arg_set) {
- diag_printf("** Error: %s already specified\n", opt->name);
+ diag_printf("** Error: option '-%c' already specified\n", opt->flag);
ok = false;
}
if (opt->takes_arg) {
#include <redboot.h>
+#include <cyg/io/flash.h>
#include <net/net.h>
#include CYGHWR_MEMORY_LAYOUT_H
#include <wince.h>
#define CE_WINCE_VRAM_BASE 0x80000000
#define CE_FIX_ADDRESS(a) (((a) - CE_WINCE_VRAM_BASE) + CE_RAM_BASE)
+#ifdef CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA_FLASH
+extern void *flash_start, *flash_end;
+
+static inline int is_rom_addr(void *addr)
+{
+ return addr >= flash_start && addr <= flash_end;
+}
+#else
+#define is_rom_addr(p) 0
+#endif
+
+static inline int is_ram_addr(unsigned long addr)
+{
+ return addr >= CE_RAM_BASE && addr < CE_RAM_END;
+}
+
// Bin image parse states
#define CE_PS_RTI_ADDR 0
#define CE_PS_RTI_LEN 1
///////////////////////////////////////////////////////////////////////////////////////////////
// Local types
typedef struct {
- unsigned int rtiPhysAddr;
- unsigned int rtiPhysLen;
- unsigned int ePhysAddr;
- unsigned int ePhysLen;
- unsigned int eChkSum;
+ unsigned long rtiPhysAddr;
+ unsigned long rtiPhysLen;
+ unsigned long ePhysAddr;
+ unsigned long ePhysLen;
+ unsigned long eChkSum;
- unsigned int eEntryPoint;
- unsigned int eRamStart;
- unsigned int eRamLen;
- unsigned int eDrvGlb;
+ unsigned long eEntryPoint;
+ unsigned long eRamStart;
+ unsigned long eRamLen;
+ unsigned long eDrvGlb;
unsigned char parseState;
- unsigned int parseChkSum;
+ unsigned long parseChkSum;
int parseLen;
unsigned char *parsePtr;
- int secion;
+ int section;
int dataLen;
unsigned char *data;
bool ce_lookup_ep_bin(ce_bin *bin);
void ce_prepare_run_bin(ce_bin *bin);
void ce_run_bin(ce_bin *bin);
-void ce_redboot_version(unsigned int *vhigh, unsigned int *vlow);
#ifdef CYGPKG_REDBOOT_NETWORKING
// Redboot network based routines
bool ce_is_bin_image(void *image, int imglen)
{
if (imglen < CE_BIN_SIGN_LEN) {
+ diag_printf("Not a valid CE image: image size %u shorter than minimum %u\n",
+ imglen, CE_BIN_SIGN_LEN);
return 0;
}
+ if (is_rom_addr(image)) {
+ unsigned char sign_buf[CE_BIN_SIGN_LEN];
+ void *err_addr;
- return (memcmp(image, CE_BIN_SIGN, CE_BIN_SIGN_LEN) == 0);
+ if (flash_read(image, sign_buf,
+ CE_BIN_SIGN_LEN, &err_addr) != FLASH_ERR_OK) {
+ return 0;
+ }
+ return memcmp(sign_buf, CE_BIN_SIGN, CE_BIN_SIGN_LEN) == 0;
+ }
+ return memcmp(image, CE_BIN_SIGN, CE_BIN_SIGN_LEN) == 0;
}
void ce_bin_init_parser()
{
// No buffer address by now, will be specified
- // latter by the ce_bin_parse_next routine
-
+ // later by the ce_bin_parse_next routine
ce_init_bin(&g_bin, NULL);
}
if (pbLen) {
if (bin->binLen == 0) {
// Check for the .BIN signature first
-
if (!ce_is_bin_image(pbData, pbLen)) {
- diag_printf("Error: Invalid or corrupted .BIN image!\n");
+ diag_printf("** Error: Invalid or corrupted .BIN image!\n");
return CE_PR_ERROR;
}
diag_printf("Loading Windows CE .BIN image ...\n");
// Skip signature
-
pbLen -= CE_BIN_SIGN_LEN;
pbData += CE_BIN_SIGN_LEN;
}
copyLen = CE_MIN(sizeof(unsigned int) - bin->parseLen, pbLen);
- memcpy(&bin->parsePtr[ bin->parseLen ], pbData, copyLen);
+ if (is_rom_addr(pbData)) {
+ void *err_addr;
+ if (flash_read(pbData, &bin->parsePtr[bin->parseLen],
+ copyLen, &err_addr) != FLASH_ERR_OK) {
+ return CE_PR_ERROR;
+ }
+ } else {
+ memcpy(&bin->parsePtr[bin->parseLen], pbData, copyLen);
+ }
bin->parseLen += copyLen;
pbLen -= copyLen;
pbData += copyLen;
if (bin->parseLen == sizeof(unsigned int)) {
if (bin->parseState == CE_PS_RTI_ADDR) {
bin->rtiPhysAddr = CE_FIX_ADDRESS(bin->rtiPhysAddr);
+ if (!is_ram_addr(bin->rtiPhysAddr)) {
+ diag_printf("Invalid address %08lx in CE_PS_RTI_ADDR section\n",
+ bin->rtiPhysAddr);
+ return CE_PR_ERROR;
+ }
} else if (bin->parseState == CE_PS_E_ADDR) {
if (bin->ePhysAddr) {
bin->ePhysAddr = CE_FIX_ADDRESS(bin->ePhysAddr);
+ if (!is_ram_addr(bin->ePhysAddr)) {
+ diag_printf("Invalid address %08lx in CE_PS_E_ADDR section\n",
+ bin->ePhysAddr);
+ return CE_PR_ERROR;
+ }
}
}
bin->parseState ++;
bin->parseLen = 0;
bin->parsePtr += sizeof(unsigned int);
-
if (bin->parseState == CE_PS_E_DATA) {
if (bin->ePhysAddr) {
bin->parsePtr = (unsigned char*)(bin->ePhysAddr);
bin->parseChkSum = 0;
} else {
// EOF
-
pbLen = 0;
bin->endOfBin = 1;
}
break;
case CE_PS_E_DATA:
-
if (bin->ePhysAddr) {
copyLen = CE_MIN(bin->ePhysLen - bin->parseLen, pbLen);
bin->parseLen += copyLen;
pbLen -= copyLen;
+ if (is_rom_addr(pbData)) {
+ void *err_addr;
- while (copyLen --) {
- bin->parseChkSum += *pbData;
- *bin->parsePtr ++ = *pbData ++;
+ if (flash_read(pbData, bin->parsePtr,
+ copyLen, &err_addr) != FLASH_ERR_OK) {
+ return CE_PR_ERROR;
+ }
+ pbData += copyLen;
+ while (copyLen--) {
+ bin->parseChkSum += *bin->parsePtr++;
+ }
+ } else {
+ while (copyLen--) {
+ bin->parseChkSum += *pbData;
+ *bin->parsePtr ++ = *pbData ++;
+ }
}
-
if (bin->parseLen == bin->ePhysLen) {
- diag_printf("Section [%02d]: address 0x%08X, size 0x%08X, checksum %s\n",
- bin->secion,
+ diag_printf("Section [%02d]: address 0x%08lX, size 0x%08lX, checksum %s\n",
+ bin->section,
bin->ePhysAddr,
bin->ePhysLen,
(bin->eChkSum == bin->parseChkSum) ? "ok" : "fail");
return CE_PR_ERROR;
}
- bin->secion ++;
+ bin->section ++;
bin->parseState = CE_PS_E_ADDR;
bin->parseLen = 0;
bin->parsePtr = (unsigned char*)(&bin->ePhysAddr);
// Find entry point
if (!ce_lookup_ep_bin(bin)) {
- diag_printf("Error: entry point not found!\n");
+ diag_printf("** Error: entry point not found!\n");
bin->binLen = 0;
return CE_PR_ERROR;
}
- diag_printf("Entry point: 0x%08X, address range: 0x%08X-0x%08X\n",
+ diag_printf("Entry point: 0x%08lX, address range: 0x%08lX-0x%08lX\n",
bin->eEntryPoint,
bin->rtiPhysAddr,
bin->rtiPhysAddr + bin->rtiPhysLen);
unsigned int i;
// Check image Table Of Contents (TOC) signature
-
if (*(unsigned int*)(bin->rtiPhysAddr + ROM_SIGNATURE_OFFSET) != ROM_SIGNATURE) {
// Error: Did not find image TOC signature!
// Lookup entry point
-
header = (ce_rom_hdr*)CE_FIX_ADDRESS(*(unsigned int*)(bin->rtiPhysAddr +
ROM_SIGNATURE_OFFSET +
sizeof(unsigned int)));
for (i = 0; i < header->nummods; i ++) {
// Look for 'nk.exe' module
-
if (strcmp((char*)CE_FIX_ADDRESS(tentry[ i ].fileName), "nk.exe") == 0) {
// Save entry point and RAM addresses
e32 = (e32_rom*)CE_FIX_ADDRESS(tentry[ i ].e32Offset);
- bin->eEntryPoint = CE_FIX_ADDRESS(tentry[ i ].loadOffset) + e32->e32_entryrva;
+ bin->eEntryPoint = CE_FIX_ADDRESS(tentry[ i ].loadOffset) +
+ e32->e32_entryrva;
bin->eRamStart = CE_FIX_ADDRESS(header->ramStart);
bin->eRamLen = header->ramEnd - header->ramStart;
// DRV_GLB 83B00000 00001000 RESERVED
//
- bin->eDrvGlb = CE_FIX_ADDRESS(header->ramEnd);
-
+ bin->eDrvGlb = CE_FIX_ADDRESS(header->ramEnd) -
+ sizeof(ce_driver_globals);
return 1;
}
}
return 0;
}
-void ce_prepare_run_bin(ce_bin *bin)
+void setup_drv_globals(ce_driver_globals *drv_glb)
{
- ce_driver_globals *drv_glb;
+ diag_printf("%s %p\n", __FUNCTION__, drv_glb);
- // Clear os RAM area (if needed)
+ // Fill out driver globals
+ memset(drv_glb, 0, sizeof(ce_driver_globals));
- if (1 || bin->edbgConfig.flags & EDBG_FL_CLEANBOOT) {
- diag_printf("Preparing clean boot ... ");
- memset((void*)bin->eRamStart, 0, bin->eRamLen);
- diag_printf("ok\n");
- }
+ // Signature
+ drv_glb->signature = DRV_GLB_SIGNATURE;
- // Prepare driver globals (if needed)
+ // No flags by now
+ drv_glb->flags = 0;
- if (bin->eDrvGlb) {
- drv_glb = (ce_driver_globals*)bin->eDrvGlb;
+#ifdef CYGPKG_REDBOOT_NETWORKING
+ // Local ethernet MAC address
+ memcpy(drv_glb->macAddr, __local_enet_addr, sizeof(__local_enet_addr));
+
+ // Local IP address
+ memcpy(&drv_glb->ipAddr, __local_ip_addr, sizeof(__local_ip_addr));
+
+ // Subnet mask
+ memcpy(&drv_glb->ipMask, __local_ip_mask, sizeof(__local_ip_mask));
+
+ // Gateway config
+#ifdef CYGSEM_REDBOOT_NETWORKING_USE_GATEWAY
+ // Getway IP address
+ memcpy(&drv_glb->ipGate, __local_ip_gate, sizeof(__local_ip_gate));
+#endif
+#endif
+}
- // Fill out driver globals
- memset(drv_glb, 0, sizeof(ce_driver_globals));
+#if WINCE_ALTERNATE_ARG_BASE
+void setup_alt_drv_globals(ce_alt_driver_globals *alt_drv_glb)
+{
+ diag_printf("%s %p\n", __FUNCTION__, alt_drv_glb);
+ // Fill out driver globals
+ memset(alt_drv_glb, 0, sizeof(ce_alt_driver_globals));
- // Signature
- drv_glb->signature = DRV_GLB_SIGNATURE;
+ alt_drv_glb->header.signature = ALT_DRV_GLB_SIGNATURE;
+ alt_drv_glb->header.oalVersion = 1;
+ alt_drv_glb->header.bspVersion = 1;
- // No flags by now
- drv_glb->flags = 0;
+ alt_drv_glb->kitl.flags = 0;
+ diag_sprintf(alt_drv_glb->deviceId, "Triton");
#ifdef CYGPKG_REDBOOT_NETWORKING
- // Local ethernet MAC address
- memcpy(drv_glb->macAddr, __local_enet_addr, sizeof(__local_enet_addr));
+ memcpy(&alt_drv_glb->kitl.mac[0], __local_enet_addr, sizeof(__local_enet_addr));
+ diag_sprintf(alt_drv_glb->deviceId, "Triton%02X", __local_enet_addr[5]);
- // Local IP address
- memcpy(&drv_glb->ipAddr, __local_ip_addr, sizeof(__local_ip_addr));
+ // Local IP address
+ memcpy(&alt_drv_glb->kitl.ipAddress, __local_ip_addr, sizeof(__local_ip_addr));
- // Subnet mask
- memcpy(&drv_glb->ipMask, __local_ip_mask, sizeof(__local_ip_mask));
+ // Subnet mask
+ memcpy(&alt_drv_glb->kitl.ipMask, __local_ip_mask, sizeof(__local_ip_mask));
- // Gateway config
+ // Gateway config
#ifdef CYGSEM_REDBOOT_NETWORKING_USE_GATEWAY
- // Getway IP address
- memcpy(&drv_glb->ipGate, __local_ip_gate, sizeof(__local_ip_gate));
+ // Getway IP address
+ memcpy(&alt_drv_glb->kitl.ipRoute, __local_ip_gate, sizeof(__local_ip_gate));
#endif
+#endif
+}
#else
- // Local ethernet MAC address
- memset(drv_glb->macAddr, 0, sizeof(drv_glb->macAddr));
+#define setup_alt_drv_globals(x) CYG_EMPTY_STATEMENT
+#endif
- // Local IP address
- memset(&drv_glb->ipAddr, 0, sizeof(drv_glb->ipAddr));
+void ce_prepare_run_bin(ce_bin *bin)
+{
+ ce_driver_globals *drv_glb;
- // Subnet mask
- memset(&drv_glb->ipMask, 0, sizeof(drv_glb->ipMask));
+ diag_printf("%s\n", __FUNCTION__);
- // Getway IP address
- memset(&drv_glb->ipGate, 0, sizeof(drv_glb->ipGate));
-#endif // CYGPKG_REDBOOT_NETWORKING
- // EDBG services config
- memcpy(&drv_glb->edbgConfig, &bin->edbgConfig, sizeof(bin->edbgConfig));
+#if WINCE_ALTERNATE_ARG_BASE
+ ce_alt_driver_globals *alt_drv_glb = &_KARO_CECFG_START;
+ char *karo_magic = &_KARO_MAGIC[0];
+ unsigned long *karo_structure_size = &_KARO_STRUCT_SIZE;
- // Equotip specific
-#ifdef CYGPKG_HAL_ARM_XSCALE_TRITON270_EQT32
- // Copy configuration
+ memcpy(karo_magic, "KARO_CE6", sizeof(_KARO_MAGIC));
+ *karo_structure_size = sizeof(ce_alt_driver_globals);
+#endif
+ // Clear os RAM area (if needed)
+ if (bin->edbgConfig.flags & EDBG_FL_CLEANBOOT) {
+ diag_printf("Preparing clean boot ... ");
+ memset((void *)bin->eRamStart, 0, bin->eRamLen);
+ diag_printf("ok\n");
+ }
- drv_glb->contrastDefault = eedat.lcd_contrast;
- drv_glb->contrastBand = eedat.lcd_contrast_band;
- drv_glb->backlight = eedat.lcd_backlight;
- drv_glb->backlightOffset = eedat.lcd_backlight_offset;
+ // Prepare driver globals (if needed)
+ if (bin->eDrvGlb) {
+ drv_glb = (ce_driver_globals *)bin->eDrvGlb;
- memcpy(drv_glb->macAddr, eedat.mac_address, sizeof(drv_glb->macAddr));
-#endif
+ setup_drv_globals(drv_glb);
+ setup_alt_drv_globals(alt_drv_glb);
+
+ // EDBG services config
+ memcpy(&drv_glb->edbgConfig, &bin->edbgConfig, sizeof(bin->edbgConfig));
}
// Update global RedBoot entry point address
pow = 1;
p = pver + strlen(pver) - 1;
- while (len --) {
+ while (len--) {
if (*p >= '0' && *p <= '9') {
*ver += ((*p - '0') * pow);
pow *= 10;
break;
}
}
- p --;
+ p--;
}
}
if (g_bin.binLen) {
// Try to receive edbg commands from host
-
ce_init_edbg_link(&g_net);
if (verbose) {
}
// Prepare WinCE image for execution
-
ce_prepare_run_bin(&g_bin);
// Launch WinCE, if necessary
-
if (g_net.gotJumpingRequest) {
ce_run_bin(&g_bin);
}
{
eth_dbg_hdr *header;
edbg_bootme_data *data;
- int verHigh, verLow;
+ unsigned int verHigh, verLow;
// Fill out BOOTME packet
memset(net->data, 0, BOOTME_PKT_SIZE);
// Some diag output ...
if (net->verbose) {
diag_printf("Sending BOOTME request [%d] to %s\n",
- (int)net->secNum,
- inet_ntoa((in_addr_t *)&net->srvAddrSend));
+ net->secNum,
+ inet_ntoa((in_addr_t *)&net->srvAddrSend));
}
// Send packet
#ifndef __WINCEINC_H__
#define __WINCEINC_H__
+#define WINCE_ALTERNATE_ARG_BASE 1
+
#pragma pack(1)
// Edbg BOOTME packet structures
-typedef struct
+typedef struct
{
- unsigned int id; // Protocol identifier ("EDBG" on the wire)
+ unsigned int id; // Protocol identifier ("EDBG" on the wire)
unsigned char service; // Service identifier
unsigned char flags; // Flags (see defs below)
unsigned char seqNum; // For detection of dropped packets
unsigned char cmd; // For administrative messages
- unsigned char data[1]; // Cmd specific data starts here (format is determined by
- // Cmd, len is determined by UDP packet size)
-}
-eth_dbg_hdr;
+ unsigned char data[1]; // Cmd specific data starts here (format is determined by
+ // Cmd, len is determined by UDP packet size)
+} eth_dbg_hdr;
-#define OFFSETOF(s,m) ((unsigned int)&(((s*)0)->m))
-#define EDBG_DATA_OFFSET (OFFSETOF(eth_dbg_hdr, data))
+#define OFFSETOF(s,m) ((unsigned int)&(((s*)0)->m))
+#define EDBG_DATA_OFFSET (OFFSETOF(eth_dbg_hdr, data))
-typedef struct
+typedef struct
{
- unsigned char versionMajor; // Bootloader version
- unsigned char versionMinor; // Bootloader version
- unsigned short macAddr[3]; // Ether address of device (net byte order)
- unsigned int ipAddr; // IP address of device (net byte order)
- char platformId[17]; // Platform Id string (NULL terminated)
- char deviceName[17]; // Device name string (NULL terminated). Should include
- // platform and number based on Ether address (e.g. Odo42, CEPCLS2346, etc)
- unsigned char cpuId; // CPU identifier (upper nibble = type)
- // The following fields were added in CE 3.0 Platform Builder release
- unsigned char bootmeVer; // BOOTME Version. Must be in the range 2 -> EDBG_CURRENT_BOOTME_VERSION, or
- // remaining fields will be ignored by Eshell and defaults will be used.
- unsigned int bootFlags; // Boot Flags
- unsigned short downloadPort; // Download Port (net byte order) (0 -> EDBG_DOWNLOAD_PORT)
- unsigned short svcPort; // Service Port (net byte order) (0 -> EDBG_SVC_PORT)
-
+ unsigned char versionMajor; // Bootloader version
+ unsigned char versionMinor; // Bootloader version
+ unsigned short macAddr[3]; // Ether address of device (net byte order)
+ unsigned int ipAddr; // IP address of device (net byte order)
+ char platformId[17]; // Platform Id string (NULL terminated)
+ char deviceName[17]; // Device name string (NULL terminated). Should include
+ // platform and number based on Ether address (e.g. Odo42, CEPCLS2346, etc)
+ unsigned char cpuId; // CPU identifier (upper nibble = type)
+ // The following fields were added in CE 3.0 Platform Builder release
+ unsigned char bootmeVer; // BOOTME Version.
+ // Must be in the range 2 -> EDBG_CURRENT_BOOTME_VERSION, or
+ // remaining fields will be ignored by Eshell and defaults will be used.
+ unsigned int bootFlags; // Boot Flags
+ unsigned short downloadPort; // Download Port (net byte order) (0 -> EDBG_DOWNLOAD_PORT)
+ unsigned short svcPort; // Service Port (net byte order) (0 -> EDBG_SVC_PORT)
} edbg_bootme_data;
// Packet size
-
-#define BOOTME_PKT_SIZE (EDBG_DATA_OFFSET + sizeof(edbg_bootme_data))
+#define BOOTME_PKT_SIZE (EDBG_DATA_OFFSET + sizeof(edbg_bootme_data))
// WinCE .BIN file format signature
-
-#define CE_BIN_SIGN "B000FF\x0A"
+#define CE_BIN_SIGN "B000FF\x0A"
#define CE_BIN_SIGN_LEN 7
-
typedef struct
{
- unsigned char sign[ CE_BIN_SIGN_LEN ];
+ unsigned char sign[CE_BIN_SIGN_LEN];
unsigned int rtiPhysAddr;
unsigned int rtiPhysLen;
-}
-ce_bin_hdr;
+} ce_bin_hdr;
typedef struct
{
unsigned int physAddr;
unsigned int physLen;
unsigned int chkSum;
- unsigned char data[ 1 ];
-}
-ce_bin_entry;
+ unsigned char data[1];
+} ce_bin_entry;
// CE ROM image structures
-
-#define ROM_SIGNATURE_OFFSET 0x40 // Offset from the image's physfirst address to the ROM signature.
-#define ROM_SIGNATURE 0x43454345 // Signature
-#define ROM_TOC_POINTER_OFFSET 0x44 // Offset from the image's physfirst address to the TOC pointer.
-#define ROM_TOC_OFFSET_OFFSET 0x48 // Offset from the image's physfirst address to the TOC offset (from physfirst).
+#define ROM_SIGNATURE_OFFSET 0x40 // Offset from the image's physfirst address to the ROM signature.
+#define ROM_SIGNATURE 0x43454345 // Signature
+#define ROM_TOC_POINTER_OFFSET 0x44 // Offset from the image's physfirst address to the TOC pointer.
+#define ROM_TOC_OFFSET_OFFSET 0x48 // Offset from the image's physfirst address to the TOC offset (from physfirst).
typedef struct
{
- unsigned int dllfirst; // first DLL address
- unsigned int dlllast; // last DLL address
- unsigned int physfirst; // first physical address
- unsigned int physlast; // highest physical address
- unsigned int nummods; // number of TOCentry's
- unsigned int ramStart; // start of RAM
- unsigned int ramFree; // start of RAM free space
- unsigned int ramEnd; // end of RAM
- unsigned int copyEntries; // number of copy section entries
- unsigned int copyOffset; // offset to copy section
- unsigned int profileLen; // length of PROFentries RAM
- unsigned int profileOffset; // offset to PROFentries
- unsigned int numfiles; // number of FILES
- unsigned int kernelFlags; // optional kernel flags from ROMFLAGS .bib config option
- unsigned int fsRamPercent; // Percentage of RAM used for filesystem
- // from FSRAMPERCENT .bib config option
- // byte 0 = #4K chunks/Mbyte of RAM for filesystem 0-2Mbytes 0-255
- // byte 1 = #4K chunks/Mbyte of RAM for filesystem 2-4Mbytes 0-255
- // byte 2 = #4K chunks/Mbyte of RAM for filesystem 4-6Mbytes 0-255
- // byte 3 = #4K chunks/Mbyte of RAM for filesystem > 6Mbytes 0-255
-
- unsigned int drivglobStart; // device driver global starting address
- unsigned int drivglobLen; // device driver global length
- unsigned short cpuType; // CPU (machine) Type
- unsigned short miscFlags; // Miscellaneous flags
- void* extensions; // pointer to ROM Header extensions
- unsigned int trackingStart; // tracking memory starting address
- unsigned int trackingLen; // tracking memory ending address
-}
-ce_rom_hdr;
+ unsigned int dllfirst; // first DLL address
+ unsigned int dlllast; // last DLL address
+ unsigned int physfirst; // first physical address
+ unsigned int physlast; // highest physical address
+ unsigned int nummods; // number of TOCentry's
+ unsigned int ramStart; // start of RAM
+ unsigned int ramFree; // start of RAM free space
+ unsigned int ramEnd; // end of RAM
+ unsigned int copyEntries; // number of copy section entries
+ unsigned int copyOffset; // offset to copy section
+ unsigned int profileLen; // length of PROFentries RAM
+ unsigned int profileOffset; // offset to PROFentries
+ unsigned int numfiles; // number of FILES
+ unsigned int kernelFlags; // optional kernel flags from ROMFLAGS .bib config option
+ unsigned int fsRamPercent; // Percentage of RAM used for filesystem
+ // from FSRAMPERCENT .bib config option
+ // byte 0 = #4K chunks/Mbyte of RAM for filesystem 0-2Mbytes 0-255
+ // byte 1 = #4K chunks/Mbyte of RAM for filesystem 2-4Mbytes 0-255
+ // byte 2 = #4K chunks/Mbyte of RAM for filesystem 4-6Mbytes 0-255
+ // byte 3 = #4K chunks/Mbyte of RAM for filesystem > 6Mbytes 0-255
+
+ unsigned int drivglobStart; // device driver global starting address
+ unsigned int drivglobLen; // device driver global length
+ unsigned short cpuType; // CPU (machine) Type
+ unsigned short miscFlags; // Miscellaneous flags
+ void* extensions; // pointer to ROM Header extensions
+ unsigned int trackingStart; // tracking memory starting address
+ unsigned int trackingLen; // tracking memory ending address
+} ce_rom_hdr;
// Win32 FILETIME strcuture
{
unsigned int loDateTime;
unsigned int hiDateTime;
-}
-ce_file_time;
+} ce_file_time;
// Table Of Contents entry structure
typedef struct
-{
+{
unsigned int fileAttributes;
ce_file_time fileTime;
unsigned int fileSize;
unsigned int e32Offset; // Offset to E32 structure
unsigned int o32Offset; // Offset to O32 structure
unsigned int loadOffset; // MODULE load buffer offset
-}
-ce_toc_entry;
+} ce_toc_entry;
-typedef struct
+typedef struct
{ /* Extra information header block */
unsigned int rva; /* Virtual relative address of info */
unsigned int size; /* Size of information block */
-}
-e32_info;
+} e32_info;
#define ROM_EXTRA 9
unsigned int e32_timestamp; /* Time EXE/DLL was created/modified */
e32_info e32_unit[ ROM_EXTRA ]; /* Array of extra info units */
unsigned short e32_subsys; /* The subsystem type */
-}
-e32_rom;
-
-#pragma pack()
-
+} e32_rom;
#pragma pack(1)
-
-// OS config msg
-
+// OS config msg
#define EDBG_FL_DBGMSG 0x01 // Debug messages
#define EDBG_FL_PPSH 0x02 // Text shell
#define EDBG_FL_KDBG 0x04 // Kernel debugger
typedef struct
{
- unsigned char flags; // Flags that will be used to determine what features are
- // enabled over ethernet (saved in driver globals by bootloader)
- unsigned char kitlTransport; // Tells KITL which transport to start
+ unsigned char flags; // Flags that will be used to determine what features are
+ // enabled over ethernet (saved in driver globals by bootloader)
+ unsigned char kitlTransport; // Tells KITL which transport to start
+
+ // The following specify addressing info, only valid if the corresponding
+ // flag is set in the Flags field.
- // The following specify addressing info, only valid if the corresponding
- // flag is set in the Flags field.
-
unsigned int dbgMsgIPAddr;
- unsigned short dbgMsgPort;
- unsigned int ppshIPAddr;
- unsigned short ppshPort;
- unsigned int kdbgIPAddr;
- unsigned short kdbgPort;
-
+ unsigned short dbgMsgPort;
+ unsigned int ppshIPAddr;
+ unsigned short ppshPort;
+ unsigned int kdbgIPAddr;
+ unsigned short kdbgPort;
} edbg_os_config_data;
-
// Driver globals structure
// Used to pass driver globals info from RedBoot to WinCE core
-#define DRV_GLB_SIGNATURE 0x424C4744 // "DGLB"
+#define DRV_GLB_SIGNATURE 0x424C4744 // "DGLB"
+#define ALT_DRV_GLB_SIGNATURE 0x53475241 // "ARGS"
typedef struct
{
- unsigned int signature; // Signature
- unsigned int flags; // Misc flags
- unsigned int ipAddr; // IP address of device (net byte order)
- unsigned int ipGate; // IP address of gateway (net byte order)
- unsigned int ipMask; // Subnet mask
- unsigned short macAddr[3]; // Ether address of device (net byte order)
+ unsigned int signature; // Signature
+ unsigned int flags; // Misc flags
+ unsigned int ipAddr; // IP address of device (net byte order)
+ unsigned int ipGate; // IP address of gateway (net byte order)
+ unsigned int ipMask; // Subnet mask
+ unsigned short macAddr[3]; // Ether address of device (net byte order)
edbg_os_config_data edbgConfig; // EDBG services info
+} ce_driver_globals;
-#ifdef CYGPKG_HAL_ARM_XSCALE_TRITON270_EQT32
+#pragma pack(4)
- unsigned int contrastDefault;
- unsigned int contrastBand;
- unsigned int backlight;
- unsigned int backlightOffset;
+typedef struct {
+ unsigned long signature;
+ unsigned short oalVersion;
+ unsigned short bspVersion;
+} OAL_ARGS_HEADER;
-#endif
+typedef struct _DEVICE_LOCATION
+{
+ unsigned long IfcType;
+ unsigned long BusNumber;
+ unsigned long LogicalLoc;
+ void *PhysicalLoc;
+ unsigned long Pin;
+} DEVICE_LOCATION;
+
+typedef struct
+{
+ unsigned long flags;
+ DEVICE_LOCATION devLoc;
+ union {
+ struct {
+ unsigned long baudRate;
+ unsigned long dataBits;
+ unsigned long stopBits;
+ unsigned long parity;
+ };
+ struct {
+ unsigned short mac[3];
+ unsigned long ipAddress;
+ unsigned long ipMask;
+ unsigned long ipRoute;
+ };
+ };
+} OAL_KITL_ARGS;
+
+typedef struct
+{
+ OAL_ARGS_HEADER header;
+ char deviceId[16]; // Device identification
+ OAL_KITL_ARGS kitl;
}
-ce_driver_globals;
+ce_alt_driver_globals;
+externC ce_alt_driver_globals _KARO_CECFG_START;
+externC char _KARO_MAGIC[8];
+externC unsigned long _KARO_STRUCT_SIZE;
#pragma pack()
-
// Default UDP ports used for Ethernet download and EDBG messages. May be overriden
// by device in BOOTME message.
-#define EDBG_DOWNLOAD_PORT 980 // For downloading images to bootloader via TFTP
-#define EDBG_SVC_PORT 981 // Other types of transfers
+#define EDBG_DOWNLOAD_PORT 980 // For downloading images to bootloader via TFTP
+#define EDBG_SVC_PORT 981 // Other types of transfers
// Byte string for Id field (note - must not conflict with valid TFTP
// opcodes (0-5), as we share the download port with TFTP)
-#define EDBG_ID 0x47424445 // "EDBG"
+#define EDBG_ID 0x47424445 // "EDBG"
// Defs for reserved values of the Service field
-#define EDBG_SVC_DBGMSG 0 // Debug messages
-#define EDBG_SVC_PPSH 1 // Text shell and PPFS file system
-#define EDBG_SVC_KDBG 2 // Kernel debugger
-#define EDBG_SVC_ADMIN 0xFF // Administrative messages
+#define EDBG_SVC_DBGMSG 0 // Debug messages
+#define EDBG_SVC_PPSH 1 // Text shell and PPFS file system
+#define EDBG_SVC_KDBG 2 // Kernel debugger
+#define EDBG_SVC_ADMIN 0xFF // Administrative messages
// Commands
-#define EDBG_CMD_READ_REQ 1 // Read request
-#define EDBG_CMD_WRITE_REQ 2 // Write request
-#define EDBG_CMD_WRITE 3 // Host ack
-#define EDBG_CMD_WRITE_ACK 4 // Target ack
-#define EDBG_CMD_ERROR 5 // Error
+#define EDBG_CMD_READ_REQ 1 // Read request
+#define EDBG_CMD_WRITE_REQ 2 // Write request
+#define EDBG_CMD_WRITE 3 // Host ack
+#define EDBG_CMD_WRITE_ACK 4 // Target ack
+#define EDBG_CMD_ERROR 5 // Error
// Service Ids from 3-FE are used for user apps
-#define NUM_DFLT_EDBG_SERVICES 3
+#define NUM_DFLT_EDBG_SERVICES 3
// Size of send and receive windows (except for stop and wait mode)
-#define EDBG_WINDOW_SIZE 8
+#define EDBG_WINDOW_SIZE 8
// The window size can be negotiated up to this amount if a client provides
// enough memory.
-#define EDBG_MAX_WINDOW_SIZE 16
+#define EDBG_MAX_WINDOW_SIZE 16
// Max size for an EDBG frame. Based on ethernet MTU - protocol overhead.
// Limited to one MTU because we don't do IP fragmentation on device.
// Definitions for Cmd field (used for administrative messages)
// Msgs from device
-#define EDBG_CMD_BOOTME 0 // Initial bootup message from device
-
+#define EDBG_CMD_BOOTME 0 // Initial bootup message from device
// Msgs from PC
-
-#define EDBG_CMD_SETDEBUG 1 // Used to set debug zones on device (TBD)
-#define EDBG_CMD_JUMPIMG 2 // Command to tell bootloader to jump to existing
- // flash or RAM image. Data is same as CMD_OS_CONFIG.
-#define EDBG_CMD_OS_CONFIG 3 // Configure OS for debug ethernet services
-#define EDBG_CMD_QUERYINFO 4 // "Ping" device, and return information (same fmt as bootme)
-#define EDBG_CMD_RESET 5 // Command to have platform perform SW reset (e.g. so it
- // can be reprogrammed). Support for this command is
- // processor dependant, and may not be implemented
- // on all platforms (requires HW mods for Odo).
-
-// Msgs from device or PC
-
-#define EDBG_CMD_SVC_CONFIG 6
-#define EDBG_CMD_SVC_DATA 7
-
-#define EDBG_CMD_DEBUGBREAK 8 // Break into debugger
+#define EDBG_CMD_SETDEBUG 1 // Used to set debug zones on device (TBD)
+#define EDBG_CMD_JUMPIMG 2 // Command to tell bootloader to jump to existing
+ // flash or RAM image. Data is same as CMD_OS_CONFIG.
+#define EDBG_CMD_OS_CONFIG 3 // Configure OS for debug ethernet services
+#define EDBG_CMD_QUERYINFO 4 // "Ping" device, and return information (same fmt as bootme)
+#define EDBG_CMD_RESET 5 // Command to have platform perform SW reset (e.g. so it
+ // can be reprogrammed). Support for this command is
+ // processor dependant, and may not be implemented
+ // on all platforms (requires HW mods for Odo).
+// Msgs from device or PC
+#define EDBG_CMD_SVC_CONFIG 6
+#define EDBG_CMD_SVC_DATA 7
+#define EDBG_CMD_DEBUGBREAK 8 // Break into debugger
// Structures for Data portion of EDBG packets
-
-#define EDBG_MAX_DEV_NAMELEN 16
+#define EDBG_MAX_DEV_NAMELEN 16
// BOOTME message - Devices broadcast this message when booted to request configuration
-
-#define EDBG_CURRENT_BOOTME_VERSION 2
+#define EDBG_CURRENT_BOOTME_VERSION 2
//
// Capability and boot Flags for dwBootFlags in EDBG_BOOTME_DATA
//
// Always download image
-
-#define EDBG_BOOTFLAG_FORCE_DOWNLOAD 0x00000001
+#define EDBG_BOOTFLAG_FORCE_DOWNLOAD 0x00000001
// Support passive-kitl
-
-#define EDBG_CAPS_PASSIVEKITL 0x00010000
+#define EDBG_CAPS_PASSIVEKITL 0x00010000
// Defs for CPUId
-
-#define EDBG_CPU_TYPE_SHX 0x10
-#define EDBG_CPU_TYPE_MIPS 0x20
-#define EDBG_CPU_TYPE_X86 0x30
-#define EDBG_CPU_TYPE_ARM 0x40
-#define EDBG_CPU_TYPE_PPC 0x50
-#define EDBG_CPU_TYPE_THUMB 0x60
-
-#define EDBG_CPU_SH3 (EDBG_CPU_TYPE_SHX | 0)
-#define EDBG_CPU_SH4 (EDBG_CPU_TYPE_SHX | 1)
-#define EDBG_CPU_R3000 (EDBG_CPU_TYPE_MIPS | 0)
-#define EDBG_CPU_R4101 (EDBG_CPU_TYPE_MIPS | 1)
-#define EDBG_CPU_R4102 (EDBG_CPU_TYPE_MIPS | 2)
-#define EDBG_CPU_R4111 (EDBG_CPU_TYPE_MIPS | 3)
-#define EDBG_CPU_R4200 (EDBG_CPU_TYPE_MIPS | 4)
-#define EDBG_CPU_R4300 (EDBG_CPU_TYPE_MIPS | 5)
-#define EDBG_CPU_R5230 (EDBG_CPU_TYPE_MIPS | 6)
-#define EDBG_CPU_R5432 (EDBG_CPU_TYPE_MIPS | 7)
-#define EDBG_CPU_i486 (EDBG_CPU_TYPE_X86 | 0)
-#define EDBG_CPU_SA1100 (EDBG_CPU_TYPE_ARM | 0)
-#define EDBG_CPU_ARM720 (EDBG_CPU_TYPE_ARM | 1)
-#define EDBG_CPU_PPC821 (EDBG_CPU_TYPE_PPC | 0)
-#define EDBG_CPU_PPC403 (EDBG_CPU_TYPE_PPC | 1)
-#define EDBG_CPU_THUMB720 (EDBG_CPU_TYPE_THUMB | 0)
+#define EDBG_CPU_TYPE_SHX 0x10
+#define EDBG_CPU_TYPE_MIPS 0x20
+#define EDBG_CPU_TYPE_X86 0x30
+#define EDBG_CPU_TYPE_ARM 0x40
+#define EDBG_CPU_TYPE_PPC 0x50
+#define EDBG_CPU_TYPE_THUMB 0x60
+
+#define EDBG_CPU_SH3 (EDBG_CPU_TYPE_SHX | 0)
+#define EDBG_CPU_SH4 (EDBG_CPU_TYPE_SHX | 1)
+#define EDBG_CPU_R3000 (EDBG_CPU_TYPE_MIPS | 0)
+#define EDBG_CPU_R4101 (EDBG_CPU_TYPE_MIPS | 1)
+#define EDBG_CPU_R4102 (EDBG_CPU_TYPE_MIPS | 2)
+#define EDBG_CPU_R4111 (EDBG_CPU_TYPE_MIPS | 3)
+#define EDBG_CPU_R4200 (EDBG_CPU_TYPE_MIPS | 4)
+#define EDBG_CPU_R4300 (EDBG_CPU_TYPE_MIPS | 5)
+#define EDBG_CPU_R5230 (EDBG_CPU_TYPE_MIPS | 6)
+#define EDBG_CPU_R5432 (EDBG_CPU_TYPE_MIPS | 7)
+#define EDBG_CPU_i486 (EDBG_CPU_TYPE_X86 | 0)
+#define EDBG_CPU_SA1100 (EDBG_CPU_TYPE_ARM | 0)
+#define EDBG_CPU_ARM720 (EDBG_CPU_TYPE_ARM | 1)
+#define EDBG_CPU_PPC821 (EDBG_CPU_TYPE_PPC | 0)
+#define EDBG_CPU_PPC403 (EDBG_CPU_TYPE_PPC | 1)
+#define EDBG_CPU_THUMB720 (EDBG_CPU_TYPE_THUMB | 0)
#endif
int
xyzModem_stream_open(connection_info_t *info, int *err)
{
- int console_chan, stat;
+ int console_chan, stat=0;
int retries = xyzModem_MAX_RETRIES;
int crc_retries = xyzModem_MAX_RETRIES_WITH_CRC;
// skip filename
while (*xyz.bufp++);
// get the length
- parse_num(xyz.bufp, &xyz.file_length, NULL, " ");
+ parse_num((char *)xyz.bufp, &xyz.file_length, NULL, " ");
#endif
// The rest of the file name data block quietly discarded
xyz.tx_ack = true;
}
int
-xyzModem_stream_read(char *buf, int size, int *err)
+xyzModem_stream_read(void *buf, int size, int *err)
{
int stat, total, len;
int retries;
if (size < len) len = size;
memcpy(buf, xyz.bufp, len);
size -= len;
- buf += len;
+ buf = (char *)buf + len;
total += len;
xyz.len -= len;
xyz.bufp += len;
int xyzModem_stream_open(connection_info_t *info, int *err);
void xyzModem_stream_close(int *err);
void xyzModem_stream_terminate(int method, int (*getc)(void));
-int xyzModem_stream_read(char *buf, int size, int *err);
+int xyzModem_stream_read(void *buf, int size, int *err);
char *xyzModem_error(int err);
extern getc_io_funcs_t xyzModem_io;
+2005-10-16 Peter Korsgaard <jacmet@sunsite.dk>
+
+ * cdl/compress_zlib.cdl (CYGFUN_COMPRESS_ZLIB_GZIO): New option to
+ include zlib stdio-like utility functions.
+
2005-07-27 Peter Korsgaard <jacmet@sunsite.dk>
* src/ChangeLog:
infrastructure."
}
+ cdl_option CYGFUN_COMPRESS_ZLIB_GZIO {
+ display "Include stdio-like utility functions"
+ flavor bool
+ requires CYGINT_ISO_STDIO_FILEPOS
+ requires CYGINT_ISO_STRING_STRFUNCS
+ requires CYGINT_ISO_STDIO_FORMATTED_IO
+ requires CYGINT_ISO_STDIO_FILEACCESS
+ default_value { CYGPKG_LIBC_STDIO_OPEN ? 1 : 0 }
+ compile gzio.c
+ description "
+ This option enables the stdio-like zlib utility functions
+ (gzread/gzwrite and friends) provided in gzio.c."
+ }
+
# ====================================================================
+2006-01-23 Peter Korsgaard <jacmet@sunsite.dk>
+
+ * src/ezxml.c:
+ * include/ezxml.h:
+ * doc/ezxml.txt:
+ * doc/ezxml.html:
+ * doc/license.txt: Upgrade to ezxml-0.8.5
+
2005-01-31 Andrew Lunn <andrew.lunn@ascom.ch>
* Import of the ezxml XML parsing library
<head><title>ezXML</title></head>
<body>
<h1>ezXML - XML Parsing C Library</h1>
- <h3>version 0.8</h3>
+ <h3>version 0.8.5</h3>
<p>
ezXML is a C library for parsing XML documents inspired by
<a href="http://www.php.net/SimpleXML">simpleXML</a> for
- PHP. As the name implies, it's easy to use. It's ideal for parsing xml
+ PHP. As the name implies, it's easy to use. It's ideal for parsing XML
configuration files or REST web service responses. It's also fast and
- lightweight (11k compiled). The latest version is available here:
- <a href="http://prdownloads.sf.net/ezxml/ezxml-0.8.tar.gz?download"
- >ezxml-0.8.tar.gz</a>
+ lightweight (less than 20k compiled). The latest version is available
+ here:
+ <a href="http://prdownloads.sf.net/ezxml/ezxml-0.8.5.tar.gz?download"
+ >ezxml-0.8.5.tar.gz</a>
</p>
<b>Example Usage</b>
<p>
- Given the following example xml document:
+ Given the following example XML document:
</p>
<code>
<?xml version="1.0"?><br />
</formula1>
</code>
<p>
- This code snipped prints out a list of drivers, which team they drive for,
+ This code snippet prints out a list of drivers, which team they drive for,
and how many championship points they have:
</p>
<code>
</code>
<p>
Alternately, the following would print out the name of the second driver
- of the first team:
+ on the first team:
</p>
<code>
ezxml_t f1 = ezxml_parse_file("formula1.xml");<br />
<b>Known Limitations</b>
<ul>
<li>
- No support for UTF-16, however UTF-8 is handled correctly. UTF-16
- support is required for XML 1.0 conformity and will be implimented for
- the 1.0 release.
+ ezXML is not a validating parser.
<br />
</li>
<li>
- Loads the entire xml document into memory at once and does not allow for
- documents to be passed in a chunk at a time. Large xml files can still
+ Loads the entire XML document into memory at once and does not allow for
+ documents to be passed in a chunk at a time. Large XML files can still
be handled though through <code>ezxml_parse_file()</code> and
<code>ezxml_parse_fd()</code>, which use mmap to map the file to a
virtual address space and rely on the virtual memory system to page in
<br />
</li>
<li>
- Ignores DTDs. Parsing of the internal DTD subset is required for XML 1.0
- conformity and will be implimented for the 1.0 release. ezXML is not,
- and is not likely to become, a validating parser.
+ Does not currently recognize all possible well-formedness errors. It
+ should correctly handle all well-formed XML documents and will either
+ ignore or halt XML processing on well-formedness errors. More
+ well-formedness checking will be added in subsiquent releases.
<br />
</li>
<li>
<code>"line one\nline two"</code>, and <code><br/></code> is
reported as a sub tag, but the location of <code><br/></code>
within the character data is not. The function
- <code>ezxml_toxml()</code> will convert an ezXML structure back to xml
+ <code>ezxml_toxml()</code> will convert an ezXML structure back to XML
with sub tag locations intact.
</p>
</li>
ezXML - XML Parsing C Library
-version 0.8
+version 0.8.5
ezXML is a C library for parsing XML documents inspired by simpleXML for PHP.
-As the name implies, it's easy to use. It's ideal for parsing xml configuration
-files or REST web service responses. It's also fast and lightweight (11k
-compiled). The latest version is available here:
-http://prdownloads.sf.net/ezxml/ezxml-0.8.tar.gz?download
+As the name implies, it's easy to use. It's ideal for parsing XML configuration
+files or REST web service responses. It's also fast and lightweight (less than
+20k compiled). The latest verions is available here:
+http://prdownloads.sf.net/ezxml/ezxml-0.8.5.tar.gz?download
Example Usage
-Given the following example xml document:
+Given the following example XML document:
<?xml version="1.0"?>
<formula1>
</team>
</formula1>
-This code snipped prints out a list of drivers, which team they drive for,
+This code snippet prints out a list of drivers, which team they drive for,
and how many championship points they have:
ezxml_t f1 = ezxml_parse_file("formula1.xml"), team, driver;
}
ezxml_free(f1);
-Alternately, the following would print out the name of the second driver of the
+Alternately, the following would print out the name of the second driver on the
first team:
ezxml_t f1 = ezxml_parse_file("formula1.xml");
Known Limitations
-- No support for UTF-16, however UTF-8 is handled correctly. UTF-16 support is
- required for XML 1.0 conformity and will be implimented for the 1.0 release.
+- ezXML is not a validating parser
-- Loads the entire xml document into memory at once and does not allow for
- documents to be passed in a chunk at a time. Large xml files can still be
+- Loads the entire XML document into memory at once and does not allow for
+ documents to be passed in a chunk at a time. Large XML files can still be
handled though through ezxml_parse_file() and ezxml_parse_fd(), which use mmap
to map the file to a virtual address space and rely on the virtual memory
system to page in data as needed.
-- Ignores DTDs. Parsing of the internal DTD subset is required for XML 1.0
- conformity and will be implimented for the 1.0 release. ezXML is not, and is
- not likely to become, a validating parser.
+- Does not currently recognize all possible well-formedness errors. It should
+ correctly handle all well-formed XML documents and will either ignore or halt
+ XML processing on well-formedness errors. More well-formedness checking will
+ be added in subsiquent releases.
- In making the character content of tags easy to access, there is no way
provided to keep track of the location of sub tags relative to the character
The character content of the doc tag is reported as "line one\nline two", and
<br/> is reported as a sub tag, but the location of <br/> within the
character data is not. The function ezxml_toxml() will convert an ezXML
- structure back to xml with sub tag locations intact.
+ structure back to XML with sub tag locations intact.
Licensing
-Copyright 2004 Aaron Voisine <aaron@voisine.org>
+Copyright 2004
, 2005 Aaron Voisine <aaron@voisine.org>
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
/* ezxml.h
*
- * Copyright 2004 Aaron Voisine <aaron@voisine.org>
+ * Copyright 2004
, 2005 Aaron Voisine <aaron@voisine.org>
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
extern "C" {
#endif
-#define EZXML_BUFSIZE 1024
-
-// returns the next tag of the same name in the same section and depth or NULL
-// if not found
-#define ezxml_next(xml) xml->next
-
-// returns the tag character content or empty string if none
-#define ezxml_txt(xml) xml->txt
+#define EZXML_BUFSIZE 1024 // size of internal memory buffers
+#define EZXML_NAMEM 0x80 // name is malloced
+#define EZXML_TXTM 0x40 // txt is malloced
+#define EZXML_DUP 0x20 // attribute name and value are strduped
typedef struct ezxml *ezxml_t;
struct ezxml {
char *name; // tag name
char **attr; // tag attributes { name, value, name, value, ... NULL }
char *txt; // tag character content, empty string if none
- size_t off; // tag offset in parent tag character content
+ size_t off; // tag offset from start of parent tag character content
ezxml_t next; // next tag with same name in this section at this depth
ezxml_t sibling; // next tag with different name in same section and depth
ezxml_t ordered; // next tag, same section and depth, in original order
ezxml_t child; // head of sub tag list, NULL if none
ezxml_t parent; // parent tag, NULL if current tag is root tag
- short flags; // additional information, only used internally for now
+ short flags; // additional information
};
-
+
// Given a string of xml data and its length, parses it and creates an ezxml
// structure. For efficiency, modifies the data by adding null terminators
// and decoding ampersand sequences. If you don't want this, copy the data and
// stream into memory and then parses it. For xml files, use ezxml_parse_file()
// or ezxml_parse_fd()
ezxml_t ezxml_parse_fp(FILE *fp);
-
-// returns the first child tag (one level deeper) with the given name or NULL if
-// not found
+
+// returns the first child tag (one level deeper) with the given name or NULL
+// if not found
ezxml_t ezxml_child(ezxml_t xml, const char *name);
+// returns the next tag of the same name in the same section and depth or NULL
+// if not found
+#define ezxml_next(xml) ((xml) ? xml->next : NULL)
+
// Returns the Nth tag with the same name in the same section at the same depth
// or NULL if not found. An index of 0 returns the tag given.
ezxml_t ezxml_idx(ezxml_t xml, int idx);
+// returns the name of the given tag
+#define ezxml_name(xml) ((xml) ? xml->name : NULL)
+
+// returns the given tag's character content or empty string if none
+#define ezxml_txt(xml) ((xml) ? xml->txt : "")
+
// returns the value of the requested tag attribute, or NULL if not found
const char *ezxml_attr(ezxml_t xml, const char *attr);
-// Traverses the ezxml sturcture to retrive a specific subtag. Takes a variable
-// length list of tag names and indexes. Final index must be -1. Example:
+// Traverses the ezxml sturcture to retrieve a specific subtag. Takes a
+// variable length list of tag names and indexes. The argument list must be
+// terminated by either an index of -1 or an empty string tag name. Example:
// title = ezxml_get(library, "shelf", 0, "book", 2, "title", -1);
// This retrieves the title of the 3rd book on the 1st shelf of library.
// Returns NULL if not found.
// returns parser error message or empty string if none
const char *ezxml_error(ezxml_t xml);
+// returns a new empty ezxml structure with the given root tag name
+ezxml_t ezxml_new(const char *name);
+
+// wrapper for ezxml_new() that strdup()s name
+#define ezxml_new_d(name) ezxml_set_flag(ezxml_new(strdup(name)), EZXML_NAMEM)
+
+// Adds a child tag. off is the offset of the child tag relative to the start
+// of the parent tag's character content. Returns the child tag.
+ezxml_t ezxml_add_child(ezxml_t xml, const char *name, size_t off);
+
+// wrapper for ezxml_add_child() that strdup()s name
+#define ezxml_add_child_d(xml, name, off) \
+ ezxml_set_flag(ezxml_add_child(xml, strdup(name), off), EZXML_NAMEM)
+
+// sets the character content for the given tag and returns the tag
+ezxml_t ezxml_set_txt(ezxml_t xml, const char *txt);
+
+// wrapper for ezxml_set_txt() that strdup()s txt
+#define ezxml_set_txt_d(xml, txt) \
+ ezxml_set_flag(ezxml_set_txt(xml, strdup(txt)), EZXML_TXTM)
+
+// Sets the given tag attribute or adds a new attribute if not found. A value
+// of NULL will remove the specified attribute.
+void ezxml_set_attr(ezxml_t xml, const char *name, const char *value);
+
+// Wrapper for ezxml_set_attr() that strdup()s name/value. Value cannot be NULL
+#define ezxml_set_attr_d(xml, name, value) \
+ ezxml_set_attr(ezxml_set_flag(xml, EZXML_DUP), strdup(name), strdup(value))
+
+// sets a flag for the given tag and returns the tag
+ezxml_t ezxml_set_flag(ezxml_t xml, short flag);
+
+// removes a tag along with all its subtags
+void ezxml_remove(ezxml_t xml);
+
#ifdef __cplusplus
}
#endif
//==========================================================================
//
-// crc32.c
+// ezxml.h
//
-// Gary S. Brown's 32 bit CRC
+// Simple XML parser
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
//
//==========================================================================
-
/* ezxml.c
*
- * Copyright 2004 Aaron Voisine <aaron@voisine.org>
+ * Copyright 2004
, 2005 Aaron Voisine <aaron@voisine.org>
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
+#define EZXML_NOMMAP // no mmap on eCos
+
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#include <ctype.h>
#include <unistd.h>
#include <sys/types.h>
-#ifndef __ECOS__
+#ifndef EZXML_NOMMAP
#include <sys/mman.h>
-#endif
+#endif // EZXML_NOMMAP
#include <sys/stat.h>
#include "ezxml.h"
#include <pkgconf/system.h>
-#define EZXML_TXTM 0x80 // flag value meaning txt was malloced
-#define EZXML_WS "\t\r\n " // whitespace
-
-// called when parser finds close of tag
-#define ezxml_close_tag(root) root->cur = root->cur->parent;
+#define EZXML_WS "\t\r\n " // whitespace
+#define EZXML_ERRL 128 // maximum error string length
typedef struct ezxml_root *ezxml_root_t;
-struct ezxml_root { // additional data for the root tag
- struct ezxml xml; // is a super-struct built on top of ezxml struct
- ezxml_t cur; // current xml tree insertion point
- void *m; // original xml string
- size_t len; // length of allocated memory for mmap, or -1 for malloc
- const char *err; // error string
- char ***pi; // processing instructions
+struct ezxml_root { // additional data for the root tag
+ struct ezxml xml; // is a super-struct built on top of ezxml struct
+ ezxml_t cur; // current xml tree insertion point
+ char *m; // original xml string
+ size_t len; // length of allocated memory for mmap, -1 for malloc
+ char *u; // UTF-8 conversion of string if original was UTF-16
+ char *s; // start of work area
+ char *e; // end of work area
+ char **ent; // general entities (ampersand sequences)
+ char ***attr; // default attributes
+ char ***pi; // processing instructions
+ short standalone; // non-zero if <?xml standalone="yes"?>
+ char err[EZXML_ERRL]; // error string
};
+char *EZXML_NIL[] = { NULL }; // empty, null terminated array of strings
+
// returns the first child tag with the given name or NULL if not found
ezxml_t ezxml_child(ezxml_t xml, const char *name)
{
- if (! xml) return NULL;
- xml = xml->child;
+ xml = (xml) ? xml->child : NULL;
while (xml && strcmp(name, xml->name)) xml = xml->sibling;
-
return xml;
}
// returns the value of the requested tag attribute or NULL if not found
const char *ezxml_attr(ezxml_t xml, const char *attr)
{
- int i = 0;
+ int i = 0, j = 1;
+ ezxml_root_t root = (ezxml_root_t)xml;
- if (! xml) return NULL;
+ if (! xml || ! xml->attr) return NULL;
while (xml->attr[i] && strcmp(attr, xml->attr[i])) i += 2;
- return (xml->attr[i]) ? xml->attr[i + 1] : NULL;
+ if (xml->attr[i]) return xml->attr[i + 1]; // found attribute
+
+ while (root->xml.parent) root = (ezxml_root_t)root->xml.parent; // root tag
+ for (i = 0; root->attr[i] && strcmp(xml->name, root->attr[i][0]); i++);
+ if (! root->attr[i]) return NULL; // no matching default attributes
+ while (root->attr[i][j] && strcmp(attr, root->attr[i][j])) j += 3;
+ return (root->attr[i][j]) ? root->attr[i][j + 1] : NULL; // found default
}
-// same as ezxml_get but takes an alredy initialized va_list
+// same as ezxml_get but takes an already initialized va_list
ezxml_t ezxml_vget(ezxml_t xml, va_list ap)
{
char *name = va_arg(ap, char *);
- int idx = va_arg(ap, int);
+ int idx = -1;
- xml = ezxml_child(xml, name);
+ if (name && *name) {
+ idx = va_arg(ap, int);
+ xml = ezxml_child(xml, name);
+ }
return (idx < 0) ? xml : ezxml_vget(ezxml_idx(xml, idx), ap);
}
-// Traverses the xml tree to retrive a specific subtag. Takes a variable
-// length list of tag names and indexes. Final index must be -1. Example:
+// Traverses the xml tree to retrieve a specific subtag. Takes a variable
+// length list of tag names and indexes. The argument list must be terminated
+// by either an index of -1 or an empty string tag name. Example:
// title = ezxml_get(library, "shelf", 0, "book", 2, "title", -1);
// This retrieves the title of the 3rd book on the 1st shelf of library.
// Returns NULL if not found.
ezxml_t ezxml_get(ezxml_t xml, ...)
{
va_list ap;
- ezxml_t ret;
+ ezxml_t r;
va_start(ap, xml);
- ret = ezxml_vget(xml, ap);
+ r = ezxml_vget(xml, ap);
va_end(ap);
-
- return ret;
+ return r;
}
-// returns a NULL terminated array of processing instructions for the given
+// returns a null terminated array of processing instructions for the given
// target
const char **ezxml_pi(ezxml_t xml, const char *target)
{
- static const char *nopi = NULL;
- ezxml_root_t root;
+ ezxml_root_t root = (ezxml_root_t)xml;
int i = 0;
- while (xml->parent) xml = xml->parent;
- root = (ezxml_root_t)xml;
-
- if (! root->pi) return &nopi;
- while (root->pi[i] && strcmp(target, root->pi[i][0])) i++;
- return (root->pi[i]) ? (const char **)root->pi[i] + 1 : &nopi;
+ if (! root) return (const char **)EZXML_NIL;
+ while (root->xml.parent) root = (ezxml_root_t)root->xml.parent; // root tag
+ while (root->pi[i] && strcmp(target, root->pi[i][0])) i++; // find target
+ return (const char **)((root->pi[i]) ? root->pi[i] + 1 : EZXML_NIL);
}
-// Converts \r or \r\n to a single \n. If decode is non-zero, decodes ampersand
-// sequences in place. Returns s.
-char *ezxml_decode(char *s, int decode)
+// set an error string and return root
+ezxml_t ezxml_err(ezxml_root_t root, char *s, const char *err, ...)
{
- int b;
- char *e, *ret = s;
- long c, d;
+ va_list ap;
+ int line = 1;
+ char *t, fmt[EZXML_ERRL];
+
+ for (t = root->s; t < s; t++) if (*t == '\n') line++;
+ snprintf(fmt, EZXML_ERRL, "[error near line %d]: %s", line, err);
- for (;;) {
- while (*s && *s != '\r' && *s != '&') s++;
+ va_start(ap, err);
+ vsnprintf(root->err, EZXML_ERRL, fmt, ap);
+ va_end(ap);
- if (! *s) return ret;
- else if (*s == '\r') {
+ return &root->xml;
+}
+
+// Recursively decodes entity and character references and normalizes new lines
+// ent is a null terminated array of alternating entity names and values. set t
+// to '&' for general entity decoding, '%' for parameter entity decoding, 'c'
+// for cdata sections, ' ' for attribute normalization, or '*' for non-cdata
+// attribute normalization. Returns s, or if the decoded string is longer than
+// s, returns a malloced string that must be freed.
+char *ezxml_decode(char *s, char **ent, char t)
+{
+ char *e, *r = s, *m = s;
+ long b, c, d, l;
+
+ for (; *s; s++) { // normalize line endings
+ while (*s == '\r') {
*(s++) = '\n';
- if (*s == '\n') memmove((void *)s, (void *)(s + 1), strlen(s));
- continue;
+ if (*s == '\n') memmove(s, (s + 1), strlen(s));
}
- else if (! decode) { s++; continue; }
- else if (! strncmp(s, "<", 4)) *(s++) = '<';
- else if (! strncmp(s, ">", 4)) *(s++) = '>';
- else if (! strncmp(s, """, 6)) *(s++) = '"';
- else if (! strncmp(s, "'", 6)) *(s++) = '\'';
- else if (! strncmp(s, "&", 5)) s++;
- else if (! strncmp(s, "&#", 2)) {
- if (s[2] == 'x') c = strtol(s + 3, &e, 16);
- else c = strtol(s + 2, &e, 10);
- if (! c || *e != ';') { s++; continue; }
-
- if (c < 0x80) *(s++) = (char)c; // US-ASCII subset
+ }
+
+ for (s = r; ; ) {
+ while (*s && *s != '&' && (*s != '%' || t != '%') && !isspace(*s)) s++;
+
+ if (! *s) break;
+ else if (t != 'c' && ! strncmp(s, "&#", 2)) { // character reference
+ if (s[2] == 'x') c = strtol(s + 3, &e, 16); // base 16
+ else c = strtol(s + 2, &e, 10); // base 10
+ if (! c || *e != ';') { s++; continue; } // not a character ref
+
+ if (c < 0x80) *(s++) = c; // US-ASCII subset
else { // multi-byte UTF-8 sequence
for (b = 0, d = c; d; d /= 2) b++; // number of bits in c
b = (b - 2) / 5; // number of bytes in payload
*(s++) = (0xFF << (7 - b)) | (c >> (6 * b)); // head
while (b) *(s++) = 0x80 | ((c >> (6 * --b)) & 0x3F); // payload
}
+
+ memmove(s, strchr(s, ';') + 1, strlen(strchr(s, ';')));
}
- else { s++; continue; }
-
- memmove((void *)s, (void *)(strchr(s, ';') + 1), strlen(strchr(s, ';')));
- }
+ else if ((*s == '&' && (t == '&' || t == ' ' || t == '*')) ||
+ (*s == '%' && t == '%')) { // entity reference
+ for (b = 0; ent[b] && strncmp(s + 1, ent[b], strlen(ent[b]));
+ b += 2); // find entity in entity list
+
+ if (ent[b++]) { // found a match
+ if ((c = strlen(ent[b])) - 1 > (e = strchr(s, ';')) - s) {
+ l = (d = (s - r)) + c + strlen(e); // new length
+ r = (r == m) ? strcpy(malloc(l), r) : realloc(r, l);
+ e = strchr((s = r + d), ';'); // fix up pointers
+ }
+
+ memmove(s + c, e + 1, strlen(e)); // shift rest of string
+ strncpy(s, ent[b], c); // copy in replacement text
+ }
+ else s++; // not a known entity
+ }
+ else if ((t == ' ' || t == '*') && isspace(*s)) *(s++) = ' ';
+ else s++; // no decoding needed
+ }
+
+ if (t == '*') { // normalize spaces for non-cdata attributes
+ for (s = r; *s; s++) {
+ if ((l = strspn(s, " "))) memmove(s, s + l, strlen(s + l) + 1);
+ while (*s && *s != ' ') s++;
+ }
+ if (--s >= r && *s == ' ') *s = '\0'; // trim any trailing space
+ }
+ return r;
}
// called when parser finds start of new tag
void ezxml_open_tag(ezxml_root_t root, char *name, char **attr)
{
ezxml_t xml = root->cur;
+
+ if (xml->name) xml = ezxml_add_child(xml, name, strlen(xml->txt));
+ else xml->name = name; // first open tag
- if (xml->name) { // not root tag
- if (xml->child) { // already have sub tags
- xml = xml->child;
- while (xml->ordered) xml = xml->ordered;
- xml->ordered = (ezxml_t)malloc(sizeof(struct ezxml));
- xml->ordered->parent = root->cur;
- root->cur = xml->ordered;
- xml = xml->parent->child;
-
- while (strcmp(xml->name, name) && xml->sibling) xml = xml->sibling;
- if (! strcmp(xml->name, name)) { // already have this tag type
- while (xml->next) xml = xml->next;
- xml = xml->next = root->cur;
- }
- else xml = xml->sibling = root->cur;
- }
- else { // first sub tag
- xml->child = (ezxml_t)malloc(sizeof(struct ezxml));
- xml->child->parent = xml;
- root->cur = xml = xml->child;
- }
-
- xml->off = strlen(xml->parent->txt); // offset in parent char content
- }
-
- // initialize new tag
- xml->name = name;
xml->attr = attr;
- xml->next = xml->child = xml->sibling = xml->ordered = NULL;
- xml->txt = "";
- xml->flags = 0;
+ root->cur = xml; // update tag insertion point
}
// called when parser finds character content between open and closing tag
-void ezxml_char_content(ezxml_root_t root, char *s, size_t len, short decode)
+void ezxml_char_content(ezxml_root_t root, char *s, size_t len, char t)
{
ezxml_t xml = root->cur;
+ char *m = s;
size_t l;
- if (! xml || ! xml->name || ! len) return;
+ if (! xml || ! xml->name || ! len) return; // sanity check
- s[len] = '\0';
- ezxml_decode(s, decode);
+ s[len] = '\0'; // null terminate text (calling functions anticipate this)
+ len = strlen(s = ezxml_decode(s, root->ent, t)) + 1;
- if (! *(xml->txt)) xml->txt = s;
+ if (! *(xml->txt)) xml->txt = s; // initial character content
else { // allocate our own memory and make a copy
- l = strlen(xml->txt);
- if (! (xml->flags & EZXML_TXTM)) {
- xml->txt = strcpy((char *)malloc(l + len + 1), xml->txt);
- xml->flags |= EZXML_TXTM;
- }
- else xml->txt = (char *)realloc((void *)(xml->txt), l + len + 1);
- strcpy(xml->txt + l, s);
+ xml->txt = (xml->flags & EZXML_TXTM) // allocate some space
+ ? realloc(xml->txt, (l = strlen(xml->txt)) + len)
+ : strcpy(malloc((l = strlen(xml->txt)) + len), xml->txt);
+ strcpy(xml->txt + l, s); // add new char content
+ if (s != m) free(s); // free s if it was malloced by ezxml_decode()
}
+
+ if (xml->txt != m) ezxml_set_flag(xml, EZXML_TXTM);
}
-// called when the parser finds an xml processing instruction
+// called when parser finds closing tag
+ezxml_t ezxml_close_tag(ezxml_root_t root, char *name, char *s)
+{
+ if (! root->cur || ! root->cur->name || strcmp(name, root->cur->name))
+ return ezxml_err(root, s, "unexpected closing tag </%s>", name);
+
+ root->cur = root->cur->parent;
+ return NULL;
+}
+
+// checks for circular entity references, returns non-zero if no circular
+// references are found, zero otherwise
+int ezxml_ent_ok(char *name, char *s, char **ent)
+{
+ int i;
+
+ for (; ; s++) {
+ while (*s && *s != '&') s++; // find next entity reference
+ if (! *s) return 1;
+ if (! strncmp(s + 1, name, strlen(name))) return 0; // circular ref.
+ for (i = 0; ent[i] && strncmp(ent[i], s + 1, strlen(ent[i])); i += 2);
+ if (ent[i] && ! ezxml_ent_ok(name, ent[i + 1], ent)) return 0;
+ }
+}
+
+// called when the parser finds a processing instruction
void ezxml_proc_inst(ezxml_root_t root, char *s, size_t len)
{
int i = 0, j = 1;
char *target = s;
s[len] = '\0'; // null terminate instruction
- *(s += strcspn(s, EZXML_WS)) = '\0'; // null terminate target
- s += strspn(s + 1, EZXML_WS) + 1; // skip whitespace after target
+ if (*(s += strcspn(s, EZXML_WS))) {
+ *s = '\0'; // null terminate target
+ s += strspn(s + 1, EZXML_WS) + 1; // skip whitespace after target
+ }
+
+ if (! strcmp(target, "xml")) { // <?xml ... ?>
+ if ((s = strstr(s, "standalone")) && ! strncmp(s + strspn(s + 10,
+ EZXML_WS "='\"") + 10, "yes", 3)) root->standalone = 1;
+ return;
+ }
- if (! root->pi) *(root->pi = (char ***)malloc(sizeof(char**))) = NULL;
+ if (! root->pi[0]) *(root->pi = malloc(sizeof(char **))) = NULL; //first pi
- while (root->pi[i] && strcmp(target, root->pi[i][0])) i++;
+ while (root->pi[i] && strcmp(target, root->pi[i][0])) i++; // find target
if (! root->pi[i]) { // new target
- root->pi = (char ***)realloc(root->pi, sizeof(char **) * (i + 2));
- root->pi[i] = (char **)malloc(sizeof(char *) * 2);
+ root->pi = realloc(root->pi, sizeof(char **) * (i + 2));
+ root->pi[i] = malloc(sizeof(char *) * 3);
root->pi[i][0] = target;
- root->pi[i + 1] = NULL; // null terminate lists
- root->pi[i][1] = (char *)root->pi[i + 1];
+ root->pi[i][1] = (char *)(root->pi[i + 1] = NULL); // terminate pi list
+ root->pi[i][2] = strdup(""); // empty document position list
}
- while (root->pi[i][j]) j++;
- root->pi[i] = (char **)realloc(root->pi[i], sizeof(char *) * (j + 2));
- root->pi[i][j] = s;
- root->pi[i][j + 1] = NULL;
+ while (root->pi[i][j]) j++; // find end of instruction list for this target
+ root->pi[i] = realloc(root->pi[i], sizeof(char *) * (j + 3));
+ root->pi[i][j + 2] = realloc(root->pi[i][j + 1], j + 1);
+ strcpy(root->pi[i][j + 2] + j - 1, (root->xml.name) ? ">" : "<");
+ root->pi[i][j + 1] = NULL; // null terminate pi list for this target
+ root->pi[i][j] = s; // set instruction
}
-// set an error string and return root
-ezxml_t ezxml_seterr(ezxml_root_t root, const char *err)
+// called when the parser finds an internal doctype subset
+short ezxml_internal_dtd(ezxml_root_t root, char *s, size_t len)
{
- root->err = err;
- return (ezxml_t)root;
+ char q, *c, *t, *n = NULL, *v, **ent, **pe;
+ int i, j;
+
+ pe = memcpy(malloc(sizeof(EZXML_NIL)), EZXML_NIL, sizeof(EZXML_NIL));
+
+ for (s[len] = '\0'; s; ) {
+ while (*s && *s != '<' && *s != '%') s++; // find next declaration
+
+ if (! *s) break;
+ else if (! strncmp(s, "<!ENTITY", 8)) { // parse entity definitions
+ c = s += strspn(s + 8, EZXML_WS) + 8; // skip white space separator
+ n = s + strspn(s, EZXML_WS "%"); // find name
+ *(s = n + strcspn(n, EZXML_WS)) = ';'; // append ; to name
+
+ v = s + strspn(s + 1, EZXML_WS) + 1; // find value
+ if ((q = *(v++)) != '"' && q != '\'') { // skip externals
+ s = strchr(s, '>');
+ continue;
+ }
+
+ for (i = 0, ent = (*c == '%') ? pe : root->ent; ent[i]; i++);
+ ent = realloc(ent, (i + 3) * sizeof(char *)); // space for next ent
+ if (*c == '%') pe = ent;
+ else root->ent = ent;
+
+ *(++s) = '\0'; // null terminate name
+ if ((s = strchr(v, q))) *(s++) = '\0'; // null terminate value
+ ent[i + 1] = ezxml_decode(v, pe, '%'); // set value
+ ent[i + 2] = NULL; // null terminate entity list
+ if (! ezxml_ent_ok(n, ent[i + 1], ent)) { // circular reference
+ if (ent[i + 1] != v) free(ent[i + 1]);
+ ezxml_err(root, v, "circular entity declaration &%s", n);
+ break;
+ }
+ else ent[i] = n; // set entity name
+ }
+ else if (! strncmp(s, "<!ATTLIST", 9)) { // parse default attributes
+ t = s + strspn(s + 9, EZXML_WS) + 9; // skip whitespace separator
+ if (! *t) { ezxml_err(root, t, "unclosed <!ATTLIST"); break; }
+ if (*(s = t + strcspn(t, EZXML_WS ">")) == '>') continue;
+ else *s = '\0'; // null terminate tag name
+ for (i = 0; root->attr[i] && strcmp(n, root->attr[i][0]); i++);
+
+ while (*(n = ++s + strspn(s, EZXML_WS)) && *n != '>') {
+ if (*(s = n + strcspn(n, EZXML_WS))) *s = '\0'; // attr name
+ else { ezxml_err(root, t, "malformed <!ATTLIST"); break; }
+
+ s += strspn(s + 1, EZXML_WS) + 1; // find next token
+ c = (strncmp(s, "CDATA", 5)) ? "*" : " "; // is it cdata?
+ if (! strncmp(s, "NOTATION", 8))
+ s += strspn(s + 8, EZXML_WS) + 8;
+ s = (*s == '(') ? strchr(s, ')') : s + strcspn(s, EZXML_WS);
+ if (! s) { ezxml_err(root, t, "malformed <!ATTLIST"); break; }
+
+ s += strspn(s, EZXML_WS ")"); // skip white space separator
+ if (! strncmp(s, "#FIXED", 6))
+ s += strspn(s + 6, EZXML_WS) + 6;
+ if (*s == '#') { // no default value
+ s += strcspn(s, EZXML_WS ">") - 1;
+ if (*c == ' ') continue; // cdata is default, nothing to do
+ v = NULL;
+ }
+ else if ((*s == '"' || *s == '\'') && // default value
+ (s = strchr(v = s + 1, *s))) *s = '\0';
+ else { ezxml_err(root, t, "malformed <!ATTLIST"); break; }
+
+ if (! root->attr[i]) { // new tag name
+ root->attr = (! i) ? malloc(2 * sizeof(char **))
+ : realloc(root->attr,
+ (i + 2) * sizeof(char **));
+ root->attr[i] = malloc(2 * sizeof(char *));
+ root->attr[i][0] = t; // set tag name
+ root->attr[i][1] = (char *)(root->attr[i + 1] = NULL);
+ }
+
+ for (j = 1; root->attr[i][j]; j += 3); // find end of list
+ root->attr[i] = realloc(root->attr[i],
+ (j + 4) * sizeof(char *));
+
+ root->attr[i][j + 3] = NULL; // null terminate list
+ root->attr[i][j + 2] = c; // is it cdata?
+ root->attr[i][j + 1] = (v) ? ezxml_decode(v, root->ent, *c)
+ : NULL;
+ root->attr[i][j] = n; // attribute name
+ }
+ }
+ else if (! strncmp(s, "<!--", 4)) s = strstr(s + 4, "-->"); // comments
+ else if (! strncmp(s, "<?", 2)) { // processing instructions
+ if ((s = strstr(c = s + 2, "?>")))
+ ezxml_proc_inst(root, c, s++ - c);
+ }
+ else if (*s == '<') s = strchr(s, '>'); // skip other declarations
+ else if (*(s++) == '%' && ! root->standalone) break;
+ }
+
+ free(pe);
+ return ! *root->err;
}
-// parse the given xml string and return an ezxml structure
-ezxml_t ezxml_parse_str(char *s, size_t len)
+// Converts a UTF-16 string to UTF-8. Returns a new string that must be freed
+// or NULL if no conversion was needed.
+char *ezxml_str2utf8(char **s, size_t *len)
{
- ezxml_root_t root = (ezxml_root_t)malloc(sizeof(struct ezxml_root));
- char *d, **attr, q, e;
- static char *noattr[] = { NULL };
- int l;
+ char *u;
+ size_t l = 0, sl, max = *len;
+ long c, d;
+ int b, be = (**s == '\xFE') ? 1 : (**s == '\xFF') ? 0 : -1;
+
+ if (be == -1) return NULL; // not UTF-16
+
+ u = malloc(max);
+ for (sl = 2; sl < *len - 1; sl += 2) {
+ c = (be) ? (((*s)[sl] & 0xFF) << 8) | ((*s)[sl + 1] & 0xFF) //UTF-16BE
+ : (((*s)[sl + 1] & 0xFF) << 8) | ((*s)[sl] & 0xFF); //UTF-16LE
+ if (c >= 0xD800 && c <= 0xDFFF && (sl += 2) < *len - 1) { // high-half
+ d = (be) ? (((*s)[sl] & 0xFF) << 8) | ((*s)[sl + 1] & 0xFF)
+ : (((*s)[sl + 1] & 0xFF) << 8) | ((*s)[sl] & 0xFF);
+ c = (((c & 0x3FF) << 10) | (d & 0x3FF)) + 0x10000;
+ }
+
+ while (l + 6 > max) u = realloc(u, max += EZXML_BUFSIZE);
+ if (c < 0x80) u[l++] = c; // US-ASCII subset
+ else { // multi-byte UTF-8 sequence
+ for (b = 0, d = c; d; d /= 2) b++; // bits in c
+ b = (b - 2) / 5; // bytes in payload
+ u[l++] = (0xFF << (7 - b)) | (c >> (6 * b)); // head
+ while (b) u[l++] = 0x80 | ((c >> (6 * --b)) & 0x3F); // payload
+ }
+ }
+ return *s = realloc(u, *len = l);
+}
- if (! root) return NULL;
+// frees a tag attribute list
+void ezxml_free_attr(char **attr) {
+ int i = 0;
+ char *m;
- // initialize root tag
- memset((void *)root, '\0', sizeof (struct ezxml_root));
- root->xml.attr = noattr;
- root->cur = (ezxml_t)root;
- root->m = (void *)s;
- root->err = root->xml.txt = "";
+ if (! attr || attr == EZXML_NIL) return; // nothing to free
+ while (attr[i]) i += 2; // find end of attribute list
+ m = attr[i + 1]; // list of which names and values are malloced
+ for (i = 0; m[i]; i++) {
+ if (m[i] & EZXML_NAMEM) free(attr[i * 2]);
+ if (m[i] & EZXML_TXTM) free(attr[(i * 2) + 1]);
+ }
+ free(m);
+ free(attr);
+}
- if (! len) return ezxml_seterr(root, "root tag missing");
- e = s[len - 1];
- s[len - 1] = '\0';
+// parse the given xml string and return an ezxml structure
+ezxml_t ezxml_parse_str(char *s, size_t len)
+{
+ ezxml_root_t root = (ezxml_root_t)ezxml_new(NULL);
+ char q, e, *d, **attr, **a = NULL; // initialize a to avoid compile warning
+ int l, i, j;
+
+ root->m = s;
+ if (! len) return ezxml_err(root, s, "root tag missing");
+ root->u = ezxml_str2utf8(&s, &len); // convert utf-16 to utf-8
+ root->e = (root->s = s) + len; // record start and end of work area
+
+ e = s[len - 1]; // save end char
+ s[len - 1] = '\0'; // turn end char into null terminator
while (*s && *s != '<') s++; // find first tag
- if (! *s) return ezxml_seterr(root, "root tag missing");
+ if (! *s) return ezxml_err(root, s, "root tag missing");
- for (;;) {
- attr = noattr;
+ for (; ; ) {
+ attr = (char **)EZXML_NIL;
d = ++s;
if (isalpha(*s) || *s == '_' || *s == ':') { // new tag
- if (! root->cur) return ezxml_seterr(root, "unmatched closing tag");
+ if (! root->cur)
+ return ezxml_err(root, d, "markup outside of root element");
s += strcspn(s, EZXML_WS "/>");
- if (isspace(*s)) *(s++) = '\0';
+ while (isspace(*s)) *(s++) = '\0'; // null terminate tag name
- l = 0;
- while (*s && *s != '/' && *s != '>') { // new tag attribute
- while (isspace(*s)) s++;
-
- attr = (char **)((! l) ? malloc(3 * sizeof (char *)) :
- realloc((void *)attr, (l + 3) * sizeof (char *)));
- attr[l] = s;
+ if (*s && *s != '/' && *s != '>') // find tag in default attr list
+ for (i = 0; (a = root->attr[i]) && strcmp(a[0], d); i++);
+
+ for (l = 0; *s && *s != '/' && *s != '>'; l += 2) { // new attrib
+ attr = (l) ? realloc(attr, (l + 4) * sizeof(char *))
+ : malloc(4 * sizeof(char *)); // allocate space
+ attr[l + 3] = (l) ? realloc(attr[l + 1], (l / 2) + 2)
+ : malloc(2); // mem for list of maloced vals
+ strcpy(attr[l + 3] + (l / 2), " "); // value is not malloced
+ attr[l + 2] = NULL; // null terminate list
+ attr[l + 1] = ""; // temporary attribute value
+ attr[l] = s; // set attribute name
s += strcspn(s, EZXML_WS "=/>");
if (*s == '=' || isspace(*s)) {
- *(s++) = '\0';
+ *(s++) = '\0'; // null terminate tag attribute name
q = *(s += strspn(s, EZXML_WS "="));
if (q == '"' || q == '\'') { // attribute value
attr[l + 1] = ++s;
while (*s && *s != q) s++;
- if (*s) *(s++) = '\0';
+ if (*s) *(s++) = '\0'; // null terminate attribute val
else {
- free(attr);
- return ezxml_seterr(root, (q == '"') ?
- "missing \"" : "missing '");
+ ezxml_free_attr(attr);
+ return ezxml_err(root, d, "missing %c", q);
}
- ezxml_decode(attr[l + 1], 1);
+
+ for (j = 1; a && a[j] && strcmp(a[j], attr[l]); j +=3);
+ attr[l + 1] = ezxml_decode(attr[l + 1], root->ent, (a
+ && a[j]) ? *a[j + 2] : ' ');
+ if (attr[l + 1] < d || attr[l + 1] > s)
+ attr[l + 3][l / 2] = EZXML_TXTM; // value malloced
}
- else attr[l + 1] = "";
}
- else attr[l + 1] = "";
-
- attr[(l += 2)] = NULL;
+ while (isspace(*s)) s++;
}
if (*s == '/') { // self closing tag
*(s++) = '\0';
if ((*s && *s != '>') || (! *s && e != '>')) {
- if (l) free(attr);
- return ezxml_seterr(root, "missing >");
+ if (l) ezxml_free_attr(attr);
+ return ezxml_err(root, d, "missing >");
}
ezxml_open_tag(root, d, attr);
- ezxml_close_tag(root);
+ ezxml_close_tag(root, d, s);
}
- else if (*s == '>' || (! *s && e == '>')) { // open tag
- q = *s;
- *s = '\0';
+ else if ((q = *s) == '>' || (! *s && e == '>')) { // open tag
+ *s = '\0'; // temporarily null terminate tag name
ezxml_open_tag(root, d, attr);
*s = q;
}
else {
- if (l) free(attr);
- return ezxml_seterr(root, "missing >");
+ if (l) ezxml_free_attr(attr);
+ return ezxml_err(root, d, "missing >");
}
}
else if (*s == '/') { // close tag
- if (! root->cur) return ezxml_seterr(root, "unmatched closing tag");
- ezxml_close_tag(root);
- while (*s && *s != '>') s++;
- if (! *s && e != '>') return ezxml_seterr(root, "missing >");
+ s += strcspn(d = s + 1, EZXML_WS ">") + 1;
+ if (! (q = *s) && e != '>') return ezxml_err(root, d, "missing >");
+ *s = '\0'; // temporarily null terminate tag name
+ if (ezxml_close_tag(root, d, s)) return &root->xml;
+ if (isspace(*s = q)) s += strspn(s, EZXML_WS);
}
else if (! strncmp(s, "!--", 3)) { // comment
- do { s = strstr(s, "--"); } while (s && *(s += 2) && *s != '>');
- if (! s || (! *s && e != '>'))
- return ezxml_seterr(root, "unclosed <!--");
+ if (! (s = strstr(s + 3, "--")) || (*(s += 2) != '>' && *s) ||
+ (! *s && e != '>')) return ezxml_err(root, d, "unclosed <!--");
}
else if (! strncmp(s, "![CDATA[", 8)) { // cdata
if ((s = strstr(s, "]]>")))
- ezxml_char_content(root, d + 8, (s += 2) - d - 10, 0);
- else return ezxml_seterr(root, "unclosed <![CDATA[");
+ ezxml_char_content(root, d + 8, (s += 2) - d - 10, 'c');
+ else return ezxml_err(root, d, "unclosed <![CDATA[");
}
- else if (! strncmp(s, "!DOCTYPE", 8)) { // skip <!DOCTYPE declarations
+ else if (! strncmp(s, "!DOCTYPE", 8)) { // dtd
for (l = 0; *s && ((! l && *s != '>') || (l && (*s != ']' ||
- s[strspn(s + 1, EZXML_WS) + 1] != '>')));
+ *(s + strspn(s + 1, EZXML_WS) + 1) != '>')));
l = (*s == '[') ? 1 : l) s += strcspn(s + 1, "[]>") + 1;
- if (! *s && e != '>')
- return ezxml_seterr(root, "unclosed <!DOCTYPE");
+ if (! *s && e != '>')
+ return ezxml_err(root, d, "unclosed <!DOCTYPE");
+ d = (l) ? strchr(d, '[') + 1 : d;
+ if (l && ! ezxml_internal_dtd(root, d, s++ - d)) return &root->xml;
}
else if (*s == '?') { // <?...?> processing instructions
do { s = strchr(s, '?'); } while (s && *(++s) && *s != '>');
if (! s || (! *s && e != '>'))
- return ezxml_seterr(root, "unclosed <?");
+ return ezxml_err(root, d, "unclosed <?");
else ezxml_proc_inst(root, d + 1, s - d - 2);
}
- else return ezxml_seterr(root, "syntax error");
+ else return ezxml_err(root, d, "unexpected <");
if (! s || ! *s) break;
*s = '\0';
d = ++s;
if (*s && *s != '<') { // tag character content
while (*s && *s != '<') s++;
- if (*s) ezxml_char_content(root, d, s - d, 1);
+ if (*s) ezxml_char_content(root, d, s - d, '&');
else break;
}
else if (! *s) break;
}
-
- return (root->cur) ? ezxml_seterr(root, (root->cur->name) ? "unclosed tag" :
- "root tag missing") : (ezxml_t)root;
+
+ if (! root->cur) return &root->xml;
+ else if (! root->cur->name) return ezxml_err(root, d, "root tag missing");
+ else return ezxml_err(root, d, "unclosed tag <%s>", root->cur->name);
}
#ifdef CYGPKG_IO_FILEIO
// or ezxml_parse_fd()
ezxml_t ezxml_parse_fp(FILE *fp)
{
- ezxml_root_t ret;
- size_t l, len = 0, ps = (size_t)sysconf(_SC_PAGESIZE);
- void *s;
+ ezxml_root_t root;
+ size_t l, len = 0;
+ char *s;
- if (! (s = (char *)malloc(ps))) return NULL;
+ if (! (s = malloc(EZXML_BUFSIZE))) return NULL;
do {
- len += (l = fread((void *)((int)s + len), 1, ps, fp));
- if (l == ps) s = (char *)realloc((void *)s, len + ps);
- } while (s && l == ps);
+ len += (l = fread((s + len), 1, EZXML_BUFSIZE, fp));
+ if (l == EZXML_BUFSIZE) s = realloc(s, len + EZXML_BUFSIZE);
+ } while (s && l == EZXML_BUFSIZE);
if (! s) return NULL;
-
- ret = (ezxml_root_t)ezxml_parse_str(s, len);
- ret->len = -1; // so we know to free s in ezxml_free()
-
- return (ezxml_t)ret;
+ root = (ezxml_root_t)ezxml_parse_str(s, len);
+ root->len = -1; // so we know to free s in ezxml_free()
+ return &root->xml;
}
// A wrapper for ezxml_parse_str() that accepts a file descriptor. First
// Returns NULL on failure.
ezxml_t ezxml_parse_fd(int fd)
{
- ezxml_root_t ret;
- struct stat stat;
- size_t len, ps = (size_t)sysconf(_SC_PAGESIZE);
+ ezxml_root_t root;
+ struct stat st;
+ size_t l;
void *m;
if (fd < 0) return NULL;
+ fstat(fd, &st);
- fstat(fd, &stat);
- len = (stat.st_size + ps - 1) & ~(ps - 1); // round up to next page boundry
-#ifdef __ECOS__
- if (0) {
-#else
- if ((m = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0)) !=
+#ifndef EZXML_NOMMAP
+ l = (st.st_size + sysconf(_SC_PAGESIZE) - 1) & ~(sysconf(_SC_PAGESIZE) -1);
+ if ((m = mmap(NULL, l, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0)) !=
MAP_FAILED) {
- madvise(m, len, MADV_SEQUENTIAL); // optimize for sequential access
- ret = (ezxml_root_t)ezxml_parse_str((char *)m, stat.st_size);
- madvise(m, len, MADV_NORMAL); // put it back to normal
- ret->len = len;
-#endif
+ madvise(m, l, MADV_SEQUENTIAL); // optimize for sequential access
+ root = (ezxml_root_t)ezxml_parse_str(m, st.st_size);
+ madvise(m, root->len = l, MADV_NORMAL); // put it back to normal
}
else { // mmap failed, read file into memory
- if (! (m = malloc(stat.st_size))) return NULL;
- len = read(fd, m, stat.st_size);
- ret = (ezxml_root_t)ezxml_parse_str((char *)m, len);
- ret->len = -1;
+#endif // EZXML_NOMMAP
+ l = read(fd, m = malloc(st.st_size), st.st_size);
+ root = (ezxml_root_t)ezxml_parse_str(m, l);
+ root->len = -1; // so we know to free s in ezxml_free()
+#ifndef EZXML_NOMMAP
}
-
- return (ezxml_t)ret;
+#endif // EZXML_NOMMAP
+ return &root->xml;
}
// a wrapper for ezxml_parse_fd that accepts a file name
ezxml_t ezxml_parse_file(const char *file)
{
int fd = open(file, O_RDONLY, 0);
- ezxml_t ret = ezxml_parse_fd(fd);
+ ezxml_t xml = ezxml_parse_fd(fd);
if (fd >= 0) close(fd);
- return ret;
+ return xml;
}
-#endif
-// Encodes ampersand sequences appending the results to dst, reallocating dst
-// if it's length excedes max. Returns *dst.
+#endif // CYGPKG_IO_FILEIO
+
+// Encodes ampersand sequences appending the results to *dst, reallocating *dst
+// if length excedes max. a is non-zero for attribute encoding. Returns *dst
char *ezxml_ampencode(const char *s, size_t len, char **dst, size_t *dlen,
- size_t *max)
+ size_t *max, short a)
{
const char *e;
case '&': *dlen += sprintf(*dst + *dlen, "&"); break;
case '<': *dlen += sprintf(*dst + *dlen, "<"); break;
case '>': *dlen += sprintf(*dst + *dlen, ">"); break;
- case '"': *dlen += sprintf(*dst + *dlen, """); break;
- default:
- if (*s >= ' ' || *s == '\n' || *s == '\t') (*dst)[(*dlen)++] = *s;
- else *dlen += sprintf(*dst + *dlen, "&#%02d;", *s);
+ case '"': *dlen += sprintf(*dst + *dlen, (a) ? """ : "\""); break;
+ case '\n': *dlen += sprintf(*dst + *dlen, (a) ? "
" : "\n"); break;
+ case '\t': *dlen += sprintf(*dst + *dlen, (a) ? "	" : "\t"); break;
+ case '\r': *dlen += sprintf(*dst + *dlen, "
"); break;
+ default: (*dst)[(*dlen)++] = *s;
}
}
-
return *dst;
}
-// Recursively converts each tag to xml appending it to s. Reallocates s if it's
-// length excedes max. start is the location of the previous tag in the parent
-// tag's character content. Returns *s.
+// Recursively converts each tag to xml appending it to *s. Reallocates *s if
+// its length excedes max. start is the location of the previous tag in the
+// parent tag's character content. Returns *s.
char *ezxml_toxml_r(ezxml_t xml, char **s, size_t *len, size_t *max,
- size_t start)
+ size_t start, char ***attr)
{
- int i;
+ int i, j;
char *txt = (xml->parent) ? xml->parent->txt : "";
+ size_t off = 0;
// parent character content up to this tag
- ezxml_ampencode(txt + start, xml->off - start, s, len, max);
+ *s = ezxml_ampencode(txt + start, xml->off - start, s, len, max, 0);
while (*len + strlen(xml->name) + 4 > *max) // reallocate s
*s = realloc(*s, *max += EZXML_BUFSIZE);
*len += sprintf(*s + *len, "<%s", xml->name); // open tag
for (i = 0; xml->attr[i]; i += 2) { // tag attributes
+ if (ezxml_attr(xml, xml->attr[i]) != xml->attr[i + 1]) continue;
while (*len + strlen(xml->attr[i]) + 7 > *max) // reallocate s
*s = realloc(*s, *max += EZXML_BUFSIZE);
*len += sprintf(*s + *len, " %s=\"", xml->attr[i]);
- ezxml_ampencode(xml->attr[i + 1], -1, s, len, max);
+ ezxml_ampencode(xml->attr[i + 1], -1, s, len, max, 1);
*len += sprintf(*s + *len, "\"");
}
- if (xml->child || *(xml->txt)) { // tag content
- *len += sprintf(*s + *len, ">");
- if (xml->child) ezxml_toxml_r(xml->child, s, len, max, 0);
- else ezxml_ampencode(xml->txt, -1, s, len, max); // char content
-
- while (*len + strlen(xml->name) + 4 > *max) // reallocate s
+ for (i = 0; attr[i] && strcmp(attr[i][0], xml->name); i++);
+ for (j = 1; attr[i] && attr[i][j]; j += 3) { // default attributes
+ if (! attr[i][j + 1] || ezxml_attr(xml, attr[i][j]) != attr[i][j + 1])
+ continue; // skip duplicates and non-values
+ while (*len + strlen(attr[i][j]) + 7 > *max) // reallocate s
*s = realloc(*s, *max += EZXML_BUFSIZE);
- *len += sprintf(*s + *len, "</%s>", xml->name); // close tag
+ *len += sprintf(*s + *len, " %s=\"", attr[i][j]);
+ ezxml_ampencode(attr[i][j + 1], -1, s, len, max, 1);
+ *len += sprintf(*s + *len, "\"");
}
- else *len += sprintf(*s + *len, "/>"); // self closing tag
+ *len += sprintf(*s + *len, ">");
- if (xml->ordered) return ezxml_toxml_r(xml->ordered, s, len, max, xml->off);
- return ezxml_ampencode(txt + xml->off, -1, s, len, max);
+ *s = (xml->child) ? ezxml_toxml_r(xml->child, s, len, max, 0, attr) //child
+ : ezxml_ampencode(xml->txt, -1, s, len, max, 0); //data
+
+ while (*len + strlen(xml->name) + 4 > *max) // reallocate s
+ *s = realloc(*s, *max += EZXML_BUFSIZE);
+
+ *len += sprintf(*s + *len, "</%s>", xml->name); // close tag
+
+ while (txt[off] && off < xml->off) off++; // make sure off is within bounds
+ return (xml->ordered) ? ezxml_toxml_r(xml->ordered, s, len, max, off, attr)
+ : ezxml_ampencode(txt + off, -1, s, len, max, 0);
}
// converts an ezxml structure back to xml, returning it as a string that must
// be freed
char *ezxml_toxml(ezxml_t xml)
{
- ezxml_t p = xml->parent;
+ ezxml_t p = (xml) ? xml->parent : NULL, o = (xml) ? xml->ordered : NULL;
+ ezxml_root_t root = (ezxml_root_t)xml;
size_t len = 0, max = EZXML_BUFSIZE;
- char *s = strcpy((char *)malloc(max), "");
+ char *s = strcpy(malloc(max), ""), *t, *n;
+ int i, j, k;
if (! xml || ! xml->name) return realloc(s, len + 1);
+ while (root->xml.parent) root = (ezxml_root_t)root->xml.parent; // root tag
+
+ for (i = 0; ! p && root->pi[i]; i++) { // pre-root processing instructions
+ for (k = 2; root->pi[i][k - 1]; k++);
+ for (j = 1; (n = root->pi[i][j]); j++) {
+ if (root->pi[i][k][j - 1] == '>') continue; // not pre-root
+ while (len + strlen(t = root->pi[i][0]) + strlen(n) + 7 > max)
+ s = realloc(s, max += EZXML_BUFSIZE);
+ len += sprintf(s + len, "<?%s%s%s?>\n", t, *n ? " " : "", n);
+ }
+ }
- xml->parent = NULL;
- ezxml_toxml_r(xml, &s, &len, &max, 0);
+ xml->parent = xml->ordered = NULL;
+ s = ezxml_toxml_r(xml, &s, &len, &max, 0, root->attr);
xml->parent = p;
-
+ xml->ordered = o;
+
+ for (i = 0; ! p && root->pi[i]; i++) { // post-root processing instructions
+ for (k = 2; root->pi[i][k - 1]; k++);
+ for (j = 1; (n = root->pi[i][j]); j++) {
+ if (root->pi[i][k][j - 1] == '<') continue; // not post-root
+ while (len + strlen(t = root->pi[i][0]) + strlen(n) + 7 > max)
+ s = realloc(s, max += EZXML_BUFSIZE);
+ len += sprintf(s + len, "\n<?%s%s%s?>", t, *n ? " " : "", n);
+ }
+ }
return realloc(s, len + 1);
}
// free the memory allocated for the ezxml structure
void ezxml_free(ezxml_t xml)
{
- void *m = NULL; // assigned to null to avoid compiler warning
- size_t len = 0;
- int i;
+ ezxml_root_t root = (ezxml_root_t)xml;
+ int i, j;
+ char **a, *s;
if (! xml) return;
+ ezxml_free(xml->child);
+ ezxml_free(xml->ordered);
- if (! xml->parent) {
- m = ((ezxml_root_t)xml)->m;
- len = ((ezxml_root_t)xml)->len;
+ if (! xml->parent) { // free root tag allocations
+ for (i = 10; root->ent[i]; i += 2) // 0 - 9 are default entites (<>&"')
+ if ((s = root->ent[i + 1]) < root->s || s > root->e) free(s);
+ free(root->ent); // free list of general entities
- if (((ezxml_root_t)xml)->pi) {
- for (i = 0; ((ezxml_root_t)xml)->pi[i]; i++)
- free(((ezxml_root_t)xml)->pi[i]);
- free(((ezxml_root_t)xml)->pi);
+ for (i = 0; (a = root->attr[i]); i++) {
+ for (j = 1; a[j++]; j += 2) // free malloced attribute values
+ if (a[j] && (a[j] < root->s || a[j] > root->e)) free(a[j]);
+ free(a);
}
+ if (root->attr[0]) free(root->attr); // free default attribute list
+
+ for (i = 0; root->pi[i]; i++) {
+ for (j = 1; root->pi[i][j]; j++);
+ free(root->pi[i][j + 1]);
+ free(root->pi[i]);
+ }
+ if (root->pi[0]) free(root->pi); // free processing instructions
+
+ if (root->len == -1) free(root->m); // malloced xml data
+#ifndef EZXML_NOMMAP
+ else if (root->len) munmap(root->m, root->len); // mem mapped xml data
+#endif // EZXML_NOMMAP
+ if (root->u) free(root->u); // utf8 conversion
}
- ezxml_free(xml->child);
- ezxml_free(xml->ordered);
-
- if (xml->attr[0]) free((void *)xml->attr);
- if ((xml->flags & EZXML_TXTM)) free((void *)xml->txt);
- free((void *)xml);
-
- if (len == -1) free(m);
-#ifndef __ECOS__
- else if (len) munmap(m, len);
-#endif
+ ezxml_free_attr(xml->attr); // tag attributes
+ if ((xml->flags & EZXML_TXTM)) free(xml->txt); // character content
+ if ((xml->flags & EZXML_NAMEM)) free(xml->name); // tag name
+ free(xml);
}
// return parser error message or empty string if none
const char *ezxml_error(ezxml_t xml)
{
- while (xml->parent) xml = xml->parent;
- return ((ezxml_root_t)xml)->err;
+ while (xml && xml->parent) xml = xml->parent; // find root tag
+ return (xml) ? ((ezxml_root_t)xml)->err : "";
}
-#ifdef EZXMLTEST // test harness
+// returns a new empty ezxml structure with the given root tag name
+ezxml_t ezxml_new(const char *name)
+{
+ static char *ent[] = { "lt;", "<", "gt;", ">", "quot;", """,
+ "apos;", "'", "amp;", "&", NULL };
+ ezxml_root_t root = (ezxml_root_t)memset(malloc(sizeof(struct ezxml_root)),
+ '\0', sizeof(struct ezxml_root));
+ root->xml.name = (char *)name;
+ root->cur = &root->xml;
+ strcpy(root->err, root->xml.txt = "");
+ root->ent = memcpy(malloc(sizeof(ent)), ent, sizeof(ent));
+ root->attr = root->pi = (char ***)(root->xml.attr = EZXML_NIL);
+ return &root->xml;
+}
+
+// Adds a child tag. off is the offset of the child tag relative to the start
+// of the parent tag's character content. returns the child tag
+ezxml_t ezxml_add_child(ezxml_t xml, const char *name, size_t off)
+{
+ ezxml_t cur, head, child;
+
+ if (! xml) return NULL;
+ child = (ezxml_t)memset(malloc(sizeof(struct ezxml)), '\0',
+ sizeof(struct ezxml));
+ child->name = (char *)name;
+ child->attr = EZXML_NIL;
+ child->off = off;
+ child->parent = xml;
+ child->txt = "";
+
+ if ((head = xml->child)) { // already have sub tags
+ if (head->off <= off) { // not first subtag
+ for (cur = head; cur->ordered && cur->ordered->off <= off;
+ cur = cur->ordered);
+ child->ordered = cur->ordered;
+ cur->ordered = child;
+ }
+ else { // first subtag
+ child->ordered = head;
+ xml->child = child;
+ }
+
+ for (cur = head; cur->sibling && strcmp(cur->name, name);
+ cur = cur->sibling); // find tag type
+ if (! strcmp(cur->name, name) && cur->off <= off) { //not first of type
+ while (cur->next && cur->next->off <= off) cur = cur->next;
+ child->next = cur->next;
+ cur->next = child;
+ }
+ else { // first tag of this type
+ if (cur->off > off) child->next = cur; // not only tag of this type
+ for (cur = head; cur->sibling && cur->sibling->off <= off;
+ cur = cur->sibling);
+ child->sibling = cur->sibling;
+ cur->sibling = child;
+ }
+ }
+ else xml->child = child; // only sub tag
+
+ return child;
+}
+
+// sets the character content for the given tag and returns the tag
+ezxml_t ezxml_set_txt(ezxml_t xml, const char *txt)
+{
+ if (! xml) return NULL;
+ if (xml->flags & EZXML_TXTM) free(xml->txt); // existing txt was malloced
+ xml->flags &= ~EZXML_TXTM;
+ xml->txt = (char *)txt;
+ return xml;
+}
+
+// Sets the given tag attribute or adds a new attribute if not found. A value
+// of NULL will remove the specified attribute.
+void ezxml_set_attr(ezxml_t xml, const char *name, const char *value)
+{
+ int l = 0, c;
+ if (! xml) return;
+ while (xml->attr[l] && strcmp(xml->attr[l], name)) l += 2;
+ if (! xml->attr[l]) { // not found, add as new attribute
+ if (! value) return; // nothing to do
+ if (xml->attr == EZXML_NIL) { // first attribute
+ xml->attr = malloc(4 * sizeof(char *));
+ xml->attr[1] = strdup(""); // empty list of malloced names/vals
+ }
+ else xml->attr = realloc(xml->attr, (l + 4) * sizeof(char *));
+
+ xml->attr[l] = (char *)name; // set attribute name
+ xml->attr[l + 2] = NULL; // null terminate attribute list
+ xml->attr[l + 3] = realloc(xml->attr[l + 1],
+ (c = strlen(xml->attr[l + 1])) + 2);
+ strcpy(xml->attr[l + 3] + c, " "); // set name/value as not malloced
+ if (xml->flags & EZXML_DUP) xml->attr[l + 3][c] = EZXML_NAMEM;
+ }
+ else if (xml->flags & EZXML_DUP) free((char *)name); // name was strduped
+
+ for (c = l; xml->attr[c]; c += 2); // find end of attribute list
+ if (xml->attr[c + 1][l / 2] & EZXML_TXTM) free(xml->attr[l + 1]); //old val
+ if (xml->flags & EZXML_DUP) xml->attr[c + 1][l / 2] |= EZXML_TXTM;
+ else xml->attr[c + 1][l / 2] &= ~EZXML_TXTM;
+
+ if (value) xml->attr[l + 1] = (char *)value; // set attribute value
+ else { // remove attribute
+ if (xml->attr[c + 1][l / 2] & EZXML_NAMEM) free(xml->attr[l]);
+ memmove(xml->attr + l, xml->attr + l + 2, (c - l + 2) * sizeof(char*));
+ xml->attr = realloc(xml->attr, (c + 2) * sizeof(char *));
+ memmove(xml->attr[c + 1] + (l / 2), xml->attr[c + 1] + (l / 2) + 1,
+ (c / 2) - (l / 2)); // fix list of which name/vals are malloced
+ }
+ xml->flags &= ~EZXML_DUP; // clear strdup() flag
+}
+
+// sets a flag for the given tag and returns the tag
+ezxml_t ezxml_set_flag(ezxml_t xml, short flag)
+{
+ if (xml) xml->flags |= flag;
+ return xml;
+}
+
+// removes a tag along with all its subtags
+void ezxml_remove(ezxml_t xml)
+{
+ ezxml_t cur;
+
+ if (! xml) return; // nothing to do
+ if (xml->next) xml->next->sibling = xml->sibling; // patch sibling list
+
+ if (xml->parent) { // not root tag
+ cur = xml->parent->child; // find head of subtag list
+ if (cur == xml) xml->parent->child = xml->ordered; // first subtag
+ else { // not first subtag
+ while (cur->ordered != xml) cur = cur->ordered;
+ cur->ordered = cur->ordered->ordered; // patch ordered list
+
+ cur = xml->parent->child; // go back to head of subtag list
+ if (strcmp(cur->name, xml->name)) { // not in first sibling list
+ while (strcmp(cur->sibling->name, xml->name))
+ cur = cur->sibling;
+ if (cur->sibling == xml) { // first of a sibling list
+ cur->sibling = (xml->next) ? xml->next
+ : cur->sibling->sibling;
+ }
+ else cur = cur->sibling; // not first of a sibling list
+ }
+
+ while (cur->next && cur->next != xml) cur = cur->next;
+ if (cur->next) cur->next = cur->next->next; // patch next list
+ }
+ }
+ xml->ordered = NULL; // prevent ezxml_free() from clobbering ordered list
+ ezxml_free(xml);
+}
+
+#ifdef EZXML_TEST // test harness
int main(int argc, char **argv)
{
ezxml_t xml;
char *s;
+ int i;
if (argc != 2) return fprintf(stderr, "usage: %s xmlfile\n", argv[0]);
xml = ezxml_parse_file(argv[1]);
- printf("%s", (s = ezxml_toxml(xml)));
- fprintf(stderr, "%s", ezxml_error(xml));
+ printf("%s\n", (s = ezxml_toxml(xml)));
free(s);
+ i = fprintf(stderr, "%s", ezxml_error(xml));
ezxml_free(xml);
-
- return 0;
+ return (i) ? 1 : 0;
}
-
-#endif // EZXMLTEST
+#endif // EZXML_TEST
+2005-10-23 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * cdl/microwindows.cdl: gettimeofday now in POSIX
+ * src/ecos/ecos_app.c: removed gettimeofday implementation.
+
2004-06-08 Chris Garry <cgarry@sweeneydesign.co.uk>
* src/ecos/ecos_app.c: Remove 'strdup' definition.
cdl_package CYGPKG_MICROWINDOWS {
display "MicroWindows"
requires CYGPKG_POSIX
+ requires CYGPKG_POSIX_TIMERS
requires CYGPKG_ISOINFRA
requires CYGINT_ISO_C_TIME_TYPES
requires CYGINT_ISO_STRERROR
// MODIFICATION/HISTORY:
//
// $Log$
-// Revision 1.1 2008-11-03 11:52:52 lothar
-// Initial revision
+// Revision 1.1.9.1 2009-06-15 14:11:00 lothar
+// unified MX27, MX25, MX37 trees
//
// Revision 1.1.1.1 2001/06/21 06:32:41 greg
// Microwindows pre8 with patches
// MODIFICATION/HISTORY:
//
// $Log$
-// Revision 1.1 2008-11-03 11:52:52 lothar
-// Initial revision
+// Revision 1.1.9.1 2009-06-15 14:11:00 lothar
+// unified MX27, MX25, MX37 trees
//
// Revision 1.1.1.1 2001/06/21 06:32:41 greg
// Microwindows pre8 with patches
// MODIFICATION/HISTORY:
//
// $Log$
-// Revision 1.1 2008-11-03 11:52:55 lothar
-// Initial revision
+// Revision 1.1.9.1 2009-06-15 14:11:07 lothar
+// unified MX27, MX25, MX37 trees
//
// Revision 1.1.1.1 2001/06/21 06:32:41 greg
// Microwindows pre8 with patches
cyg_handle_t startup_thread;
cyg_thread startup_thread_obj;
-
-int
-gettimeofday(struct timeval *tv,
- struct timezone *tz)
-{
- tv->tv_usec = 0;
- tv->tv_sec = time(NULL);
- return(0);
-}
-
int
strcasecmp(const char *s1, const char *s2)
{
* MODIFICATION/HISTORY:
*
* $Log$
- * Revision 1.1 2008-11-03 11:53:23 lothar
- * Initial revision
+ * Revision 1.1.9.1 2009-06-15 14:12:31 lothar
+ * unified MX27, MX25, MX37 trees
*
* Revision 1.1.1.1 2001/06/21 06:32:42 greg
* Microwindows pre8 with patches
//
// MODIFICATION/HISTORY:
// $Log$
-// Revision 1.1 2008-11-03 11:53:23 lothar
-// Initial revision
+// Revision 1.1.9.1 2009-06-15 14:12:31 lothar
+// unified MX27, MX25, MX37 trees
//
// Revision 1.1.1.1 2001/06/21 06:32:42 greg
// Microwindows pre8 with patches
* MODIFICATION/HISTORY:
*
* $Log$
- * Revision 1.1 2008-11-03 11:53:23 lothar
- * Initial revision
+ * Revision 1.1.9.1 2009-06-15 14:12:31 lothar
+ * unified MX27, MX25, MX37 trees
*
* Revision 1.1.1.1 2001/06/21 06:32:42 greg
* Microwindows pre8 with patches
+2008-01-06 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * src/dlmalloc.cxx (MALLOC_COPY):
+ * cdl/memalloc.cdl: Use memmove instead of memcpy which can go
+ wrong in realloc() when the new and old block overlaps.
+ CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_USE_MEMCPY has been retained
+ instead of being renamed to ..._MEMMOVE to help backward
+ compatibility with older configurations. Thanks to Oyvind Harboe
+ and Dave Lawrence.
+
+2007-11-05 Oyvind Harboe <oyvind.harboe@zylin.com>
+
+ * cdl/memalloc.cdl: Added option CYGBLD_MEMALLOC_MALLOC_EXTERNAL_JOIN_H
+ to let applications implement a way to pick the pool to allocate memory
+ from based on an application specific heuristic.
+ * src/malloc.cxx: Use it.
+
+2007-10-24 Oyvind Harboe <oyvind.harboe@zylin.com>
+2007-10-24 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * src/malloc.cxx: Init priority for pool initialization is now
+ CYG_INIT_MEMALLOC instead of before CYG_INIT_LIBC
+ * src/heapgen.tcl: Ditto.
+
+2006-05-17 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * doc/memalloc.sgml: Fix parameters for calloc. Reported by
+ Andy Jackson.
+
+2005-09-30 Alexander Neundorf <neundorf@kde.org>
+
+ * doc/memalloc.sgml: two minor fixes
+
2005-07-30 Andrew Lunn <andrew.lunn@ascom.ch>
* tests/heaptest.c (test_pat): Casts to prevent compiler warnings.
}
cdl_option CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_USE_MEMCPY {
- display "Use system memcpy() and memset()"
+ display "Use system memmove() and memset()"
requires CYGPKG_ISOINFRA
default_value { 0 != CYGPKG_ISOINFRA }
description "
- This may be used to control whether memset() and memcpy()
+ This may be used to control whether memset() and memmove()
are used within the implementation. The alternative is
to use some macro equivalents, which some people report
are faster in some circumstances."
be set to a header which provides the equivalent
definitions to <pkgconf/heaps.hxx>."
}
+
+ cdl_component CYGBLD_MEMALLOC_MALLOC_EXTERNAL_JOIN_H {
+ display "Use external implementation of joining multiple heaps"
+ flavor booldata
+ default_value 0
+ description "The default implementation of joining multiple heaps
+ is fine for the case where there are multiple disjoint
+ memory regions of the same type. However, in a system
+ there might be e.g. a small amount of internal SRAM and
+ a large amount of external DRAM. The SRAM is faster and
+ the DRAM is slower. An application can implement some
+ heuristic to choose which pool to allocate from. This
+ heuristic can be highly application specific."
+ }
cdl_interface CYGINT_MEMALLOC_MALLOC_ALLOCATORS {
display "malloc() allocator implementations"
display "Additional compiler flags"
flavor data
no_define
- default_value { "" }
+ default_value { "-fno-rtti -Woverloaded-virtual" }
description "
This option modifies the set of compiler flags for
building this package. These flags are used in addition
display "Suppressed compiler flags"
flavor data
no_define
- default_value { "" }
+ default_value { "-Wno-pointer-sign" }
description "
This option modifies the set of compiler flags for
building this package. These flags are removed from
<paramdef>cyg_uint32 <parameter>size</parameter></paramdef>
<paramdef>cyg_uint32 <parameter>blocksize</parameter></paramdef>
<paramdef>cyg_handle_t* <parameter>fixpool</parameter></paramdef>
- <paramdef>cyg_mempool_var* <parameter>var</parameter></paramdef>
+ <paramdef>cyg_mempool_fix* <parameter>fix</parameter></paramdef>
</funcprototype>
<funcprototype>
<funcdef>void <function>cyg_mempool_fix_delete</function></funcdef>
</funcprototype>
<funcprototype>
<funcdef>void *<function>calloc</function></funcdef>
+ <paramdef>size_t <parameter>nmemb</parameter></paramdef>
<paramdef>size_t <parameter>size</parameter></paramdef>
</funcprototype>
<funcprototype>
: mypool( base, size, argthru ) {}
// Destructor
- ~Cyg_Mempool_dlmalloc() {}
+ //~Cyg_Mempool_dlmalloc() {}
// get some memory; wait if none available
// if we aren't configured to be thread-aware this is irrelevant
CYG_ADDRWORD /* argthru */ );
// Destructor
- ~Cyg_Mempool_dlmalloc_Implementation() {}
+ //~Cyg_Mempool_dlmalloc_Implementation() {}
// get some memory, return NULL if none available
cyg_uint8 *
#ifdef CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_USE_MEMCPY
-#include <string.h> // memcpy, memset
+#include <string.h> // memmove, memset
/* The following macros are only invoked with (2n+1)-multiples of
INTERNAL_SIZE_T units, with a positive integer n. This is exploited
*mcdst++ = *mcsrc++; \
*mcdst++ = *mcsrc++; \
*mcdst = *mcsrc ; \
- } else memcpy(dest, src, mcsz); \
+ } else memmove(dest, src, mcsz); \
} while(0)
#else /* !CYGIMP_MEMALLOC_ALLOCATOR_DLMALLOC_USE_MEMCPY */
foreach heap $heaps {
puts $cfile "#ifdef HAL_MEM_REAL_REGION_TOP\n"
- puts $cfile [ format "%s CYGBLD_ATTRIB_INIT_PRI(CYG_INIT_MEMALLOC) cygmem_pool_%s ( (cyg_uint8 *)CYGMEM_SECTION_%s ," \
+ puts $cfile [ format "%s CYGBLD_ATTRIB_INIT_BEFORE(CYG_INIT_MEMALLOC) cygmem_pool_%s ( (cyg_uint8 *)CYGMEM_SECTION_%s ," \
$malloc_impl_class $heap $heap ]
puts $cfile [ format " HAL_MEM_REAL_REGION_TOP( (cyg_uint8 *)CYGMEM_SECTION_%s + CYGMEM_SECTION_%s_SIZE ) - (cyg_uint8 *)CYGMEM_SECTION_%s ) " \
$heap $heap $heap ]
puts $cfile "#else\n"
- puts $cfile [ format "%s CYGBLD_ATTRIB_INIT_PRI(CYG_INIT_MEMALLOC) cygmem_pool_%s ( (cyg_uint8 *)CYGMEM_SECTION_%s , CYGMEM_SECTION_%s_SIZE ) ;\n" \
+ puts $cfile [ format "%s CYGBLD_ATTRIB_INIT_BEFORE(CYG_INIT_MEMALLOC) cygmem_pool_%s ( (cyg_uint8 *)CYGMEM_SECTION_%s , CYGMEM_SECTION_%s_SIZE ) ;\n" \
$malloc_impl_class $heap $heap $heap ]
puts $cfile "#endif"
// the memory pool object itself
CYGCLS_MEMALLOC_MALLOC_IMPL cyg_memalloc_mallocpool
- CYGBLD_ATTRIB_INIT_BEFORE( CYG_INIT_LIBC ) =
+ CYGBLD_ATTRIB_INIT_PRI( CYG_INIT_MEMALLOC ) =
CYGCLS_MEMALLOC_MALLOC_IMPL( cyg_memalloc_mallocpool_memory,
sizeof( cyg_memalloc_mallocpool_memory ) );
#else
// multiple heaps
-
+#ifdef CYGBLD_MEMALLOC_MALLOC_EXTERNAL_JOIN_H
+# include CYGBLD_MEMALLOC_MALLOC_EXTERNAL_JOIN_H
+#else
# include <cyg/memalloc/memjoin.hxx>
+#endif
Cyg_Mempool_Joined<CYGCLS_MEMALLOC_MALLOC_IMPL> cyg_memalloc_mallocpool
- CYGBLD_ATTRIB_INIT_BEFORE( CYG_INIT_LIBC ) =
+ CYGBLD_ATTRIB_INIT_PRI( CYG_INIT_MEMALLOC ) =
Cyg_Mempool_Joined<CYGCLS_MEMALLOC_MALLOC_IMPL>(
CYGMEM_HEAP_COUNT, cygmem_memalloc_heaps
);
+2006-06-27 Anthony Tonizzo <atonizzo@gmail.com>
+
+ * src/loader_fs.c : Minor cosmetic and formatting changes on all files.
+ Also got rid of some signed/unsigned comparison which did not show up using
+ the PPC toolchain but do when compiled with gcc under the synthetic target.
+ * src/objelf.c :
+ * src/objloader.c :
+ * src/relocate_i386.c :
+ * src/relocate_ppc.c :
+ * include/elf.h :
+ * include/loader_fs.h :
+ * include/objelf.h :
+ * include/relocate_i386.h :
+ * include/relocate_ppc.h :
+ * test/test_mods.c :
+ * test/library/hello.c :
+
2005-07-08 Andrew Lunn <andrew.lunn@ascom.ch>
- * include/objelf.h: Include hal_tables.h otherwise we get strange
- linker errors.
- * cdl/objloader.cdl: Rearranged the building of the test case.
- * include/relocate_i386.h (New):
- * src/relocate_i386.c (New): Added a relocator for i386.
- * src/objelf.c: Fixed various Elf_Rel vs Elf_Rela issues.
- * test/load_mods.c:
- * test/library/hello.c: Modified to make use of the eCos test
- infrastructure. Uses a romfs to hold the object file to be loaded.
-
-2005-05-10 Anthony Tonizzo <atonizzo@lycos.com>
+ * include/objelf.h: Include hal_tables.h otherwise we get strange
+ linker errors.
+ * cdl/objloader.cdl: Rearranged the building of the test case.
+ * include/relocate_i386.h (New):
+ * src/relocate_i386.c (New): Added a relocator for i386.
+ * src/objelf.c: Fixed various Elf_Rel vs Elf_Rela issues.
+ * test/load_mods.c:
+ * test/library/hello.c: Modified to make use of the eCos test
+ infrastructure. Uses a romfs to hold the object file to be loaded.
+
+2005-05-10 Anthony Tonizzo <atonizzo@gmail.com>
- * include/elf.h:
- * include/loader_fs.h:
- * include/objelf.h:
- * include/relocate_ppc.h:
- * src/loader_fs.c:
- * src/objelf.c:
- * src/objloader.c:
- * src/relocate_ppc.c:
- * doc/notes.txt:
- * cdl/objloader.cdl:
- * tests/test_mods.c:
- * tests/library/hello.c:
- Created OBJLDR package.
-
+ * include/elf.h:
+ * include/loader_fs.h:
+ * include/objelf.h:
+ * include/relocate_ppc.h:
+ * src/loader_fs.c:
+ * src/objelf.c:
+ * src/objloader.c:
+ * src/relocate_ppc.c:
+ * doc/notes.txt:
+ * cdl/objloader.cdl:
+ * tests/test_mods.c:
+ * tests/library/hello.c:
+ Created OBJLDR package.
+
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
# ====================================================================
######DESCRIPTIONBEGIN####
#
-# Author(s): atonizzo (atonizzo@lycos.com)
+# Author(s): Anthony Tonizzo (atonizzo@gmail.com)
# Contributors: Andrew Lunn
# Date: 2005-05-13
#
/* =================================================================
*
- * elf.f
+ * elf.h
*
* =================================================================
* ####ECOSGPLCOPYRIGHTBEGIN####
* =================================================================
* #####DESCRIPTIONBEGIN####
*
- * Author(s): atonizzo@lycos.com
+ * Author(s): Anthony Tonizzo (atonizzo@gmail.com)
* Date: 2005-05-13
* Purpose:
* Description:
/* =================================================================
*
- * loader_fs.c
+ * loader_fs.h
*
* =================================================================
* ####ECOSGPLCOPYRIGHTBEGIN####
* =================================================================
* #####DESCRIPTIONBEGIN####
*
- * Author(s): atonizzo@lycos.com
+ * Author(s): Anthony Tonizzo (atonizzo@gmail.com)
* Date: 2005-05-13
* Purpose:
* Description:
* =================================================================
*/
-size_t cyg_ldr_fs_read( PELF_OBJECT, size_t, size_t, void* );
-cyg_int32 cyg_ldr_fs_seek( PELF_OBJECT, cyg_uint32 );
-cyg_int32 cyg_ldr_fs_close( PELF_OBJECT );
+size_t cyg_ldr_fs_read(PELF_OBJECT, size_t, size_t, void*);
+cyg_int32 cyg_ldr_fs_seek(PELF_OBJECT, cyg_uint32);
+cyg_int32 cyg_ldr_fs_close(PELF_OBJECT);
+PELF_OBJECT cyg_ldr_open_library_fs(char *);
+void cyg_ldr_close_library_fs(PELF_OBJECT);
#endif // __LOADER_FS_H__
* =================================================================
* #####DESCRIPTIONBEGIN####
*
- * Author(s): atonizzo@lycos.com
+ * Author(s): Anthony Tonizzo (atonizzo@gmail.com)
* Contributors: nickg@ecoscentric.com
* Date: 2005-05-13
* Purpose:
//==============================================================================
-extern cyg_uint8 *cyg_ldr_last_error;
+extern char *cyg_ldr_last_error;
//==============================================================================
CYG_ADDRWORD ptr;
cyg_uint32 mode;
- size_t (*read)( struct ELF_OBJECT*, size_t, size_t, void* );
- cyg_int32 (*seek)( struct ELF_OBJECT*, cyg_uint32 );
- cyg_int32 (*close)( struct ELF_OBJECT* );
+ size_t (*read)(struct ELF_OBJECT*, size_t, size_t, void*);
+ cyg_int32 (*seek)(struct ELF_OBJECT*, cyg_uint32);
+ cyg_int32 (*close)(struct ELF_OBJECT*);
// This is the absolute address in memory where the library resides.
Elf32_Ehdr* p_elfhdr;
#endif
#if CYGPKG_SERVICES_OBJLOADER_DEBUG_LEVEL > 0
-void cyg_ldr_print_section_data( PELF_OBJECT );
-void cyg_ldr_print_symbol_names( PELF_OBJECT );
-void cyg_ldr_print_rel_names( PELF_OBJECT );
+void cyg_ldr_print_section_data(PELF_OBJECT);
+void cyg_ldr_print_symbol_names(PELF_OBJECT);
+void cyg_ldr_print_rel_names(PELF_OBJECT);
#endif
//==============================================================================
// Internal functions
-cyg_int32 *cyg_ldr_load_elf_section( PELF_OBJECT, cyg_uint32 );
-void cyg_ldr_delete_elf_section( PELF_OBJECT, cyg_uint32 );
-cyg_int32 *cyg_ldr_section_address( PELF_OBJECT, cyg_uint32 );
-void* cyg_ldr_scan_file( PELF_OBJECT );
-cyg_int32 cyg_ldr_relocate_section( PELF_OBJECT, cyg_uint32 );
-void* cyg_ldr_find_symbol( void*, cyg_uint8* );
-void* cyg_ldr_symbol_address( PELF_OBJECT, cyg_uint32 );
-void* cyg_ldr_external_address( PELF_OBJECT, cyg_uint32 );
+cyg_uint32 *cyg_ldr_load_elf_section(PELF_OBJECT, cyg_uint32);
+void cyg_ldr_delete_elf_section(PELF_OBJECT, cyg_uint32);
+cyg_uint32 *cyg_ldr_section_address(PELF_OBJECT, cyg_uint32);
+void* cyg_ldr_scan_file(PELF_OBJECT);
+cyg_int32 cyg_ldr_relocate_section(PELF_OBJECT, cyg_uint32);
+void* cyg_ldr_find_symbol(void*, char*);
+void* cyg_ldr_symbol_address(PELF_OBJECT, cyg_uint32);
+void* cyg_ldr_external_address(PELF_OBJECT, cyg_uint32);
//==============================================================================
// User interface.
-PELF_OBJECT cyg_ldr_open_library( CYG_ADDRWORD, cyg_int32 );
-void cyg_ldr_close_library( void* );
-cyg_uint8* cyg_ldr_error( void );
-void* cyg_ldr_get_symbol( void*, char* );
-
-PELF_OBJECT cyg_ldr_open_library_fs( cyg_uint8* );
-void cyg_ldr_close_library_fs( PELF_OBJECT );
+PELF_OBJECT cyg_ldr_open_library(CYG_ADDRWORD, cyg_int32);
+void cyg_ldr_close_library(void*);
+char* cyg_ldr_error(void);
+void* cyg_ldr_get_symbol(void*, char*);
//==============================================================================
-void *cyg_ldr_malloc( size_t ) CYGBLD_ATTRIB_WEAK;
-void cyg_ldr_free( void * ) CYGBLD_ATTRIB_WEAK;
+void *cyg_ldr_malloc(size_t) CYGBLD_ATTRIB_WEAK;
+void cyg_ldr_free(void *) CYGBLD_ATTRIB_WEAK;
//==============================================================================
typedef struct cyg_ldr_table_entry cyg_ldr_table_entry;
-#define CYG_LDR_TABLE_ENTRY( __name, __symbol_name, __handler ) \
- cyg_ldr_table_entry __name CYG_HAL_TABLE_ENTRY( ldr_table ) = \
+#define CYG_LDR_TABLE_ENTRY(__name, __symbol_name, __handler) \
+ cyg_ldr_table_entry __name CYG_HAL_TABLE_ENTRY(ldr_table) = \
{ __symbol_name, __handler }
//==============================================================================
-#define CYG_LDR_TABLE_KAPI_ALARM() \
-CYG_LDR_TABLE_ENTRY( cyg_alarm_create_entry, \
- "cyg_alarm_create", cyg_alarm_create ); \
-CYG_LDR_TABLE_ENTRY( cyg_alarm_delete_entry, \
- "cyg_alarm_delete", cyg_alarm_delete ); \
-CYG_LDR_TABLE_ENTRY( cyg_alarm_initialize_entry, \
- "cyg_alarm_initialize", cyg_alarm_initialize ); \
-CYG_LDR_TABLE_ENTRY( cyg_alarm_get_times_entry, \
- "cyg_alarm_get_times", cyg_alarm_get_times ); \
-CYG_LDR_TABLE_ENTRY( cyg_alarm_enable_entry, \
- "cyg_alarm_enable", cyg_alarm_enable ); \
-CYG_LDR_TABLE_ENTRY( cyg_alarm_disable_entry, \
- "cyg_alarm_disable", cyg_alarm_disable );
-
-#define CYG_LDR_TABLE_KAPI_CLOCK() \
-CYG_LDR_TABLE_ENTRY( cyg_clock_create_entry, \
- "cyg_clock_create", cyg_clock_create ); \
-CYG_LDR_TABLE_ENTRY( cyg_clock_delete_entry, \
- "cyg_clock_delete", cyg_clock_delete ); \
-CYG_LDR_TABLE_ENTRY( cyg_clock_to_counter_entry, \
- "cyg_clock_to_counter", cyg_clock_to_counter ); \
-CYG_LDR_TABLE_ENTRY( cyg_clock_set_resolution_entry, \
- "cyg_clock_set_resolution", cyg_clock_set_resolution ); \
-CYG_LDR_TABLE_ENTRY( cyg_clock_get_resolution_entry, \
- "cyg_clock_get_resolution",cyg_clock_get_resolution ); \
-CYG_LDR_TABLE_ENTRY( cyg_real_time_clock_entry, \
- "cyg_real_time_clock", cyg_real_time_clock ); \
-CYG_LDR_TABLE_ENTRY( cyg_current_time_entry, \
- "cyg_current_time", cyg_current_time );
-
-#define CYG_LDR_TABLE_KAPI_COND() \
-CYG_LDR_TABLE_ENTRY( cyg_cond_init_entry, \
- "cyg_cond_init", cyg_cond_init ); \
-CYG_LDR_TABLE_ENTRY( cyg_cond_destroy_entry, \
- "cyg_cond_destroy", cyg_cond_destroy ); \
-CYG_LDR_TABLE_ENTRY( cyg_cond_wait_entry, \
- "cyg_cond_wait", cyg_cond_wait ); \
-CYG_LDR_TABLE_ENTRY( cyg_cond_signal_entry, \
- "cyg_cond_signal", cyg_cond_signal ); \
-CYG_LDR_TABLE_ENTRY( cyg_cond_broadcast_entry, \
- "cyg_cond_broadcast", cyg_cond_broadcast ); \
-CYG_LDR_TABLE_ENTRY( cyg_cond_timed_wait_entry, \
- "cyg_cond_timed_wait", cyg_cond_timed_wait );
-
-#define CYG_LDR_TABLE_KAPI_COUNTER() \
-CYG_LDR_TABLE_ENTRY( cyg_counter_create_entry, \
- "cyg_counter_create", cyg_counter_create ); \
-CYG_LDR_TABLE_ENTRY( cyg_counter_delete_entry, \
- "cyg_counter_delete", cyg_counter_delete ); \
-CYG_LDR_TABLE_ENTRY( cyg_counter_current_value_entry, \
- "cyg_counter_current_value", cyg_counter_current_value ); \
-CYG_LDR_TABLE_ENTRY( cyg_counter_set_value_entry, \
- "cyg_counter_set_value", cyg_counter_set_value ); \
-CYG_LDR_TABLE_ENTRY( cyg_counter_tick_entry, \
- "cyg_counter_tick", cyg_counter_tick ); \
-CYG_LDR_TABLE_ENTRY( cyg_counter_multi_tick_entry, \
- "cyg_counter_multi_tick", cyg_counter_multi_tick );
-
-#define CYG_LDR_TABLE_KAPI_EXCEPTIONS() \
-CYG_LDR_TABLE_ENTRY( cyg_exception_set_handler_entry, \
- "cyg_exception_set_handler", cyg_exception_set_handler ); \
-CYG_LDR_TABLE_ENTRY( cyg_exception_clear_handler_entry, \
- "cyg_exception_clear_handler", \
- cyg_exception_clear_handler ); \
-CYG_LDR_TABLE_ENTRY( cyg_exception_call_handler_entry, \
- "cyg_exception_call_handler", \
- cyg_exception_call_handler );
-
-#define CYG_LDR_TABLE_KAPI_FLAG() \
-CYG_LDR_TABLE_ENTRY( cyg_flag_init_entry, \
- "cyg_flag_init", cyg_flag_init ); \
-CYG_LDR_TABLE_ENTRY( cyg_flag_destroy_entry, \
- "cyg_flag_destroy", cyg_flag_destroy ); \
-CYG_LDR_TABLE_ENTRY( cyg_flag_setbits_entry, \
- "cyg_flag_setbits", cyg_flag_setbits ); \
-CYG_LDR_TABLE_ENTRY( cyg_flag_maskbits_entry, \
- "cyg_flag_maskbits", cyg_flag_maskbits ); \
-CYG_LDR_TABLE_ENTRY( cyg_flag_wait_entry, \
- "cyg_flag_wait", cyg_flag_wait ); \
-CYG_LDR_TABLE_ENTRY( cyg_flag_timed_wait_entry, \
- "cyg_flag_timed_wait", cyg_flag_timed_wait ); \
-CYG_LDR_TABLE_ENTRY( cyg_flag_poll_entry, \
- "cyg_flag_poll", cyg_flag_poll ); \
-CYG_LDR_TABLE_ENTRY( cyg_flag_peek_entry, \
- "cyg_flag_peek", cyg_flag_peek ); \
-CYG_LDR_TABLE_ENTRY( cyg_flag_waiting_entry, \
- "cyg_flag_waiting", cyg_flag_waiting );
-
-#define CYG_LDR_TABLE_KAPI_INTERRUPTS() \
-CYG_LDR_TABLE_ENTRY( cyg_interrupt_create_entry, \
- "cyg_interrupt_create", cyg_interrupt_create ); \
-CYG_LDR_TABLE_ENTRY( cyg_interrupt_delete_entry, \
- "cyg_interrupt_delete", cyg_interrupt_delete ); \
-CYG_LDR_TABLE_ENTRY( cyg_interrupt_attach_entry, \
- "cyg_interrupt_attach", cyg_interrupt_attach ); \
-CYG_LDR_TABLE_ENTRY( cyg_interrupt_detach_entry, \
- "cyg_interrupt_detach", cyg_interrupt_detach ); \
-CYG_LDR_TABLE_ENTRY( cyg_interrupt_get_vsr_entry, \
- "cyg_interrupt_get_vsr", cyg_interrupt_get_vsr ); \
-CYG_LDR_TABLE_ENTRY( cyg_interrupt_set_vsr_entry, \
- "cyg_interrupt_set_vsr", cyg_interrupt_set_vsr ); \
-CYG_LDR_TABLE_ENTRY( cyg_interrupt_disable_entry, \
- "cyg_interrupt_disable", cyg_interrupt_disable ); \
-CYG_LDR_TABLE_ENTRY( cyg_interrupt_enable_entry, \
- "cyg_interrupt_enable", cyg_interrupt_enable ); \
-CYG_LDR_TABLE_ENTRY( cyg_interrupt_mask_entry, \
- "cyg_interrupt_mask", cyg_interrupt_mask ); \
-CYG_LDR_TABLE_ENTRY( cyg_interrupt_mask_intunsafe_entry, \
- "cyg_interrupt_mask_intunsafe", \
- cyg_interrupt_mask_intunsafe ); \
-CYG_LDR_TABLE_ENTRY( cyg_interrupt_unmask_entry, \
- "cyg_interrupt_unmask", cyg_interrupt_unmask ); \
-CYG_LDR_TABLE_ENTRY( cyg_interrupt_unmask_intunsafe_entry, \
- "cyg_interrupt_unmask_intunsafe", \
- cyg_interrupt_unmask_intunsafe ); \
-CYG_LDR_TABLE_ENTRY( cyg_interrupt_acknowledge_entry, \
- "cyg_interrupt_acknowledge", \
- cyg_interrupt_acknowledge ); \
-CYG_LDR_TABLE_ENTRY( cyg_interrupt_configure_entry, \
- "cyg_interrupt_configure", cyg_interrupt_configure ); \
-CYG_LDR_TABLE_ENTRY( cyg_interrupt_set_cpu_entry, \
- "cyg_interrupt_set_cpu", cyg_interrupt_set_cpu ); \
-CYG_LDR_TABLE_ENTRY( cyg_interrupt_get_cpu_entry, \
- "cyg_interrupt_get_cpu", cyg_interrupt_get_cpu );
-
-#define CYG_LDR_TABLE_KAPI_MBOX() \
-CYG_LDR_TABLE_ENTRY( cyg_mbox_create_entry, \
- "cyg_mbox_create", cyg_mbox_create ); \
-CYG_LDR_TABLE_ENTRY( cyg_mbox_delete_entry, \
- "cyg_mbox_delete", cyg_mbox_delete ); \
-CYG_LDR_TABLE_ENTRY( cyg_mbox_get_entry, \
- "cyg_mbox_get", cyg_mbox_get ); \
-CYG_LDR_TABLE_ENTRY( cyg_mbox_timed_get_entry, \
- "cyg_mbox_timed_get", cyg_mbox_timed_get ); \
-CYG_LDR_TABLE_ENTRY( cyg_mbox_tryget_entry, \
- "cyg_mbox_tryget", cyg_mbox_tryget ); \
-CYG_LDR_TABLE_ENTRY( cyg_mbox_peek_item_entry, \
- "cyg_mbox_peek_item", cyg_mbox_peek_item ); \
-CYG_LDR_TABLE_ENTRY( cyg_mbox_put_entry, \
- "cyg_mbox_put", cyg_mbox_put ); \
-CYG_LDR_TABLE_ENTRY( cyg_mbox_timed_put_entry, \
- "cyg_mbox_timed_put", cyg_mbox_timed_put ); \
-CYG_LDR_TABLE_ENTRY( cyg_mbox_tryput_entry, \
- "cyg_mbox_tryput", cyg_mbox_tryput ); \
-CYG_LDR_TABLE_ENTRY( cyg_mbox_peek_entry, \
- "cyg_mbox_peek", cyg_mbox_peek ); \
-CYG_LDR_TABLE_ENTRY( cyg_mbox_waiting_to_get_entry, \
- "cyg_mbox_waiting_to_get", \
- cyg_mbox_waiting_to_get ); \
-CYG_LDR_TABLE_ENTRY( cyg_mbox_waiting_to_put_entry, \
- "cyg_mbox_waiting_to_put", \
- cyg_mbox_waiting_to_put );
-
-#define CYG_LDR_TABLE_KAPI_MEMPOOL_FIX() \
-CYG_LDR_TABLE_ENTRY( cyg_mempool_fix_create_entry, \
- "cyg_mempool_fix_create", cyg_mempool_fix_create ); \
-CYG_LDR_TABLE_ENTRY( cyg_mempool_fix_delete_entry, \
- "cyg_mempool_fix_delete", cyg_mempool_fix_delete ); \
-CYG_LDR_TABLE_ENTRY( cyg_mempool_fix_alloc_entry, \
- "cyg_mempool_fix_alloc", cyg_mempool_fix_alloc ); \
-CYG_LDR_TABLE_ENTRY( cyg_mempool_fix_timed_alloc_entry, \
- "cyg_mempool_fix_timed_alloc", \
- cyg_mempool_fix_timed_alloc ); \
-CYG_LDR_TABLE_ENTRY( cyg_mempool_fix_try_alloc_entry, \
- "cyg_mempool_fix_try_alloc", \
- cyg_mempool_fix_try_alloc ); \
-CYG_LDR_TABLE_ENTRY( cyg_mempool_fix_free_entry, \
- "cyg_mempool_fix_free", cyg_mempool_fix_free ); \
-CYG_LDR_TABLE_ENTRY( cyg_mempool_fix_waiting_entry, \
- "cyg_mempool_fix_waiting", cyg_mempool_fix_waiting ); \
-CYG_LDR_TABLE_ENTRY( cyg_mempool_fix_get_info_entry, \
- "cyg_mempool_fix_get_info", cyg_mempool_fix_get_info );
-
-#define CYG_LDR_TABLE_KAPI_MEMPOOL_VAR() \
-CYG_LDR_TABLE_ENTRY( cyg_mempool_var_create_entry, \
- "cyg_mempool_var_create", cyg_mempool_var_create ); \
-CYG_LDR_TABLE_ENTRY( cyg_mempool_var_delete_entry, \
- "cyg_mempool_var_delete", cyg_mempool_var_delete ); \
-CYG_LDR_TABLE_ENTRY( cyg_mempool_var_alloc_entry, \
- "cyg_mempool_var_alloc", cyg_mempool_var_alloc ); \
-CYG_LDR_TABLE_ENTRY( cyg_mempool_var_timed_alloc_entry, \
- "cyg_mempool_var_timed_alloc", \
- cyg_mempool_var_timed_alloc ); \
-CYG_LDR_TABLE_ENTRY( cyg_mempool_var_try_alloc_entry, \
- "cyg_mempool_var_try_alloc", \
- cyg_mempool_var_try_alloc ); \
-CYG_LDR_TABLE_ENTRY( cyg_mempool_var_free_entry, \
- "cyg_mempool_var_free", cyg_mempool_var_free ); \
-CYG_LDR_TABLE_ENTRY( cyg_mempool_var_waiting_entry, \
- "cyg_mempool_var_waiting", cyg_mempool_var_waiting ); \
-CYG_LDR_TABLE_ENTRY( cyg_mempool_var_get_info_entry, \
- "cyg_mempool_var_get_info", cyg_mempool_var_get_info );
-
-#define CYG_LDR_TABLE_KAPI_MUTEX() \
-CYG_LDR_TABLE_ENTRY( cyg_mutex_init_entry, \
- "cyg_mutex_init", cyg_mutex_init ); \
-CYG_LDR_TABLE_ENTRY( cyg_mutex_destroy_entry, \
- "cyg_mutex_destroy", cyg_mutex_destroy ); \
-CYG_LDR_TABLE_ENTRY( cyg_mutex_trylock_entry, \
- "cyg_mutex_trylock", cyg_mutex_trylock ); \
-CYG_LDR_TABLE_ENTRY( cyg_mutex_unlock_entry, \
- "cyg_mutex_unlock", cyg_mutex_unlock ); \
-CYG_LDR_TABLE_ENTRY( cyg_mutex_release_entry, \
- "cyg_mutex_release", cyg_mutex_release ); \
-CYG_LDR_TABLE_ENTRY( cyg_mutex_set_ceiling_entry, \
- "cyg_mutex_set_ceiling", cyg_mutex_set_ceiling ); \
-CYG_LDR_TABLE_ENTRY( cyg_mutex_set_protocol_entry, \
- "cyg_mutex_set_protocol", cyg_mutex_set_protocol );
-
-#define CYG_LDR_TABLE_KAPI_SCHEDULER() \
-CYG_LDR_TABLE_ENTRY( cyg_scheduler_start_entry, \
- "cyg_scheduler_start", cyg_scheduler_start ); \
-CYG_LDR_TABLE_ENTRY( cyg_scheduler_lock_entry, \
- "cyg_scheduler_lock", cyg_scheduler_lock ); \
-CYG_LDR_TABLE_ENTRY( cyg_scheduler_safe_lock_entry, \
- "cyg_scheduler_safe_lock", cyg_scheduler_safe_lock ); \
-CYG_LDR_TABLE_ENTRY( cyg_scheduler_unlock_entry, \
- "cyg_scheduler_unlock", cyg_scheduler_unlock ); \
-CYG_LDR_TABLE_ENTRY( cyg_scheduler_read_lock_entry, \
- "cyg_scheduler_read_lock", cyg_scheduler_read_lock ); \
-
-#define CYG_LDR_TABLE_KAPI_SEMAPHORE() \
-CYG_LDR_TABLE_ENTRY( cyg_semaphore_init_entry, \
- "cyg_semaphore_init", cyg_semaphore_init ); \
-CYG_LDR_TABLE_ENTRY( cyg_semaphore_destroy_entry, \
- "cyg_semaphore_destroy", cyg_semaphore_destroy ); \
-CYG_LDR_TABLE_ENTRY( cyg_semaphore_wait_entry, \
- "cyg_semaphore_wait", cyg_semaphore_wait ); \
-CYG_LDR_TABLE_ENTRY( cyg_semaphore_timed_wait_entry, \
- "cyg_semaphore_timed_wait", cyg_semaphore_timed_wait ); \
-CYG_LDR_TABLE_ENTRY( cyg_semaphore_try_wait_entry, \
- "cyg_semaphore_trywait", cyg_semaphore_trywait ); \
-CYG_LDR_TABLE_ENTRY( cyg_semaphore_post_entry, \
- "cyg_semaphore_post", cyg_semaphore_post ); \
-CYG_LDR_TABLE_ENTRY( cyg_semaphore_peek_entry, \
- "cyg_semaphore_peek", cyg_semaphore_peek );
-
-#define CYG_LDR_TABLE_KAPI_THREAD() \
-CYG_LDR_TABLE_ENTRY( cyg_thread_create_entry, \
- "cyg_thread_create", cyg_thread_create ); \
-CYG_LDR_TABLE_ENTRY( cyg_thread_exit_entry, \
- "cyg_thread_exit", cyg_thread_exit ); \
-CYG_LDR_TABLE_ENTRY( cyg_thread_delete_entry, \
- "cyg_thread_delete", cyg_thread_delete ); \
-CYG_LDR_TABLE_ENTRY( cyg_thread_suspend_entry, \
- "cyg_thread_suspend", cyg_thread_suspend ); \
-CYG_LDR_TABLE_ENTRY( cyg_thread_resume_entry, \
- "cyg_thread_resume", cyg_thread_resume ); \
-CYG_LDR_TABLE_ENTRY( cyg_thread_kill_entry, \
- "cyg_thread_kill", cyg_thread_kill ); \
-CYG_LDR_TABLE_ENTRY( cyg_thread_release_entry, \
- "cyg_thread_release", cyg_thread_release ); \
-CYG_LDR_TABLE_ENTRY( cyg_thread_yield_entry, \
- "cyg_thread_yield", cyg_thread_yield ); \
-CYG_LDR_TABLE_ENTRY( cyg_thread_self_entry, \
- "cyg_thread_self", cyg_thread_self ); \
-CYG_LDR_TABLE_ENTRY( cyg_thread_idle_thread_entry, \
- "cyg_thread_idle_thread", cyg_thread_idle_thread ); \
-CYG_LDR_TABLE_ENTRY( cyg_thread_set_priority_entry, \
- "cyg_thread_set_priority", cyg_thread_set_priority ); \
-CYG_LDR_TABLE_ENTRY( cyg_thread_get_priority_entry, \
- "cyg_thread_get_priority", cyg_thread_get_priority ); \
-CYG_LDR_TABLE_ENTRY( cyg_thread_get_current_priority_entry, \
- "cyg_thread_get_current_priority", \
- cyg_thread_get_current_priority ); \
-CYG_LDR_TABLE_ENTRY( cyg_thread_delay_entry, \
- "cyg_thread_delay", cyg_thread_delay ); \
-CYG_LDR_TABLE_ENTRY( cyg_thread_get_stack_base_entry, \
- "cyg_thread_get_stack_base", cyg_thread_get_stack_base ); \
-CYG_LDR_TABLE_ENTRY( cyg_thread_get_stack_size_entry, \
- "cyg_thread_get_stack_size", cyg_thread_get_stack_size ); \
-CYG_LDR_TABLE_ENTRY( cyg_thread_new_data_index_entry, \
- "cyg_thread_new_data_index", cyg_thread_new_data_index ); \
-CYG_LDR_TABLE_ENTRY( cyg_thread_free_data_index_entry, \
- "cyg_thread_free_data_index", \
- cyg_thread_free_data_index ); \
-CYG_LDR_TABLE_ENTRY( cyg_thread_get_data_entry, \
- "cyg_thread_get_data", cyg_thread_get_data ); \
-CYG_LDR_TABLE_ENTRY( cyg_thread_get_data_ptr_entry, \
- "cyg_thread_get_data_ptr", cyg_thread_get_data_ptr ); \
-CYG_LDR_TABLE_ENTRY( cyg_thread_set_data_entry, \
- "cyg_thread_set_data", cyg_thread_set_data );
-
-#define CYG_LDR_TABLE_STRING() \
-CYG_LDR_TABLE_ENTRY( memchr_entry, "memchr", memchr ); \
-CYG_LDR_TABLE_ENTRY( memcmp_entry, "memcmp", memcmp ); \
-CYG_LDR_TABLE_ENTRY( memcpy_entry, "memcpy", memcpy ); \
-CYG_LDR_TABLE_ENTRY( memmove_entry, "memmove", memmove ); \
-CYG_LDR_TABLE_ENTRY( memset_entry, "memset", memset ); \
-CYG_LDR_TABLE_ENTRY( strcpy_entry, "strcpy", strcpy ); \
-CYG_LDR_TABLE_ENTRY( strncpy_entry, "strncpy", strncpy ); \
-CYG_LDR_TABLE_ENTRY( strcat_entry, "strcat", strcat ); \
-CYG_LDR_TABLE_ENTRY( strncat_entry, "strncat", strncat ); \
-CYG_LDR_TABLE_ENTRY( strchr_entry, "strchr", strchr ); \
-CYG_LDR_TABLE_ENTRY( strrchr_entry, "strrchr", strrchr ); \
-CYG_LDR_TABLE_ENTRY( strcoll_entry, "strcoll", strcoll ); \
-CYG_LDR_TABLE_ENTRY( strlen_entry, "strlen", strlen ); \
-CYG_LDR_TABLE_ENTRY( strcmp_entry, "strcmp", strcmp ); \
-CYG_LDR_TABLE_ENTRY( strncmp_entry, "strncmp", strncmp ); \
-CYG_LDR_TABLE_ENTRY( strcspn_entry, "strcspn", strcspn ); \
-CYG_LDR_TABLE_ENTRY( strerror_entry, "strerror", strerror ); \
-CYG_LDR_TABLE_ENTRY( strpbrk_entry, "strpbrk", strpbrk ); \
-CYG_LDR_TABLE_ENTRY( strspn_entry, "strspn", strspn ); \
-CYG_LDR_TABLE_ENTRY( strstr_entry, "strstr", strstr ); \
-CYG_LDR_TABLE_ENTRY( strtok_entry, "strtok", strtok ); \
-CYG_LDR_TABLE_ENTRY( strxfrm_entry, "strxfrm", strxfrm );
-
-#define CYG_LDR_TABLE_STDIO() \
-CYG_LDR_TABLE_ENTRY( clearerr_entry, "clearerr", clearerr ); \
-CYG_LDR_TABLE_ENTRY( fclose_entry, "fclose", fclose ); \
-CYG_LDR_TABLE_ENTRY( feof_entry, "feof", feof ); \
-CYG_LDR_TABLE_ENTRY( ferror_entry, "ferror", ferror ); \
-CYG_LDR_TABLE_ENTRY( fflush_entry, "fflush", fflush ); \
-CYG_LDR_TABLE_ENTRY( fgetc_entry, "fgetc", fgetc ); \
-CYG_LDR_TABLE_ENTRY( fgetpos_entry, "fgetpos", fgetpos ); \
-CYG_LDR_TABLE_ENTRY( fgets_entry, "fgets", fgets ); \
-CYG_LDR_TABLE_ENTRY( fopen_entry, "fopen", fopen ); \
-CYG_LDR_TABLE_ENTRY( fprintf_entry, "fprintf", fprintf ); \
-CYG_LDR_TABLE_ENTRY( fputc_entry, "fputc", fputc ); \
-CYG_LDR_TABLE_ENTRY( fputs_entry, "fputs", fputs ); \
-CYG_LDR_TABLE_ENTRY( fread_entry, "fread", fread ); \
-CYG_LDR_TABLE_ENTRY( freopen_entry, "freopen", freopen ); \
-CYG_LDR_TABLE_ENTRY( fscanf_entry, "fscanf", fscanf ); \
-CYG_LDR_TABLE_ENTRY( fseek_entry, "fseek", fseek ); \
-CYG_LDR_TABLE_ENTRY( fsetpos_entry, "fsetpos", fsetpos ); \
-CYG_LDR_TABLE_ENTRY( ftell_entry, "ftell", ftell ); \
-CYG_LDR_TABLE_ENTRY( fwrite_entry, "fwrite", fwrite ); \
-CYG_LDR_TABLE_ENTRY( perror_entry, "perror", perror ); \
-CYG_LDR_TABLE_ENTRY( printf_entry, "printf", printf ); \
-CYG_LDR_TABLE_ENTRY( putc_entry, "putc", putc ); \
-CYG_LDR_TABLE_ENTRY( putchar_entry, "putchar", putchar ); \
-CYG_LDR_TABLE_ENTRY( puts_entry, "puts", puts ); \
-CYG_LDR_TABLE_ENTRY( remove_entry, "remove", remove ); \
-CYG_LDR_TABLE_ENTRY( rename_entry, "rename", rename ); \
-CYG_LDR_TABLE_ENTRY( rewind_entry, "rewind", rewind ); \
-CYG_LDR_TABLE_ENTRY( scanf_entry, "scanf", scanf ); \
-CYG_LDR_TABLE_ENTRY( setbuf_entry, "setbuf", setbuf ); \
-CYG_LDR_TABLE_ENTRY( setvbuf_entry, "setvbuf", setvbuf ); \
-CYG_LDR_TABLE_ENTRY( sprintf_entry, "sprintf", sprintf ); \
-CYG_LDR_TABLE_ENTRY( sscanf_entry, "sscanf", sscanf ); \
-CYG_LDR_TABLE_ENTRY( tmpfile_entry, "tmpfile", tmpfile ); \
-CYG_LDR_TABLE_ENTRY( tmpnam_entry, "tmpnam", tmpnam ); \
-CYG_LDR_TABLE_ENTRY( ungetc_entry, "ungetc", ungetc );
-
-#define CYG_LDR_TABLE_INFRA_DIAG() \
-CYG_LDR_TABLE_ENTRY( diag_init_entry, "diag_init", diag_init ); \
-CYG_LDR_TABLE_ENTRY( diag_write_char_entry, \
- "diag_write_char", diag_write_char ); \
-CYG_LDR_TABLE_ENTRY( diag_write_string_entry, \
- "diag_write_string", diag_write_string ); \
-CYG_LDR_TABLE_ENTRY( diag_write_dec_entry, \
- "diag_write_dec", diag_write_dec ); \
-CYG_LDR_TABLE_ENTRY( diag_write_hex_entry, \
- "diag_write_hex", diag_write_hex ); \
-CYG_LDR_TABLE_ENTRY( diag_dump_buf_entry, \
- "diag_dump_buf", diag_dump_buf ); \
-CYG_LDR_TABLE_ENTRY( diag_dump_buf_32bit_entry, \
- "diag_dump_buf_32bit", diag_dump_buf_32bit ); \
-CYG_LDR_TABLE_ENTRY( diag_dump_buf_16bit_entry, \
- "diag_dump_buf_16bit", diag_dump_buf_16bit ); \
-CYG_LDR_TABLE_ENTRY( diag_vdump_buf_with_offset_entry, \
- "diag_vdump_buf_with_offset", \
- diag_vdump_buf_with_offset ); \
-CYG_LDR_TABLE_ENTRY( diag_dump_buf_with_offset_entry, \
- "diag_dump_buf_with_offset", \
- diag_dump_buf_with_offset ); \
-CYG_LDR_TABLE_ENTRY( diag_dump_buf_with_offset_32bit_entry, \
- "diag_dump_buf_with_offset_32bit", \
- diag_dump_buf_with_offset_32bit ); \
-CYG_LDR_TABLE_ENTRY( diag_dump_buf_with_offset_16bit_entry, \
- "diag_dump_buf_with_offset_16bit", \
- diag_dump_buf_with_offset_16bit ); \
-CYG_LDR_TABLE_ENTRY( diag_printf_entry, "diag_printf", diag_printf ); \
-CYG_LDR_TABLE_ENTRY( diag_init_putc_entry, "diag_init_putc", diag_init_putc ); \
-CYG_LDR_TABLE_ENTRY( diag_sprintf_entry, "diag_sprintf", diag_sprintf ); \
-CYG_LDR_TABLE_ENTRY( diag_snprintf_entry, "diag_snprintf", diag_snprintf ); \
-CYG_LDR_TABLE_ENTRY( diag_vsprintf_entry, "diag_vsprintf", diag_vsprintf ); \
-CYG_LDR_TABLE_ENTRY( diag_vprintf_entry, "diag_vprintf", diag_vprintf );
+#define CYG_LDR_TABLE_KAPI_ALARM() \
+CYG_LDR_TABLE_ENTRY(cyg_alarm_create_entry, \
+ "cyg_alarm_create", cyg_alarm_create); \
+CYG_LDR_TABLE_ENTRY(cyg_alarm_delete_entry, \
+ "cyg_alarm_delete", cyg_alarm_delete); \
+CYG_LDR_TABLE_ENTRY(cyg_alarm_initialize_entry, \
+ "cyg_alarm_initialize", cyg_alarm_initialize); \
+CYG_LDR_TABLE_ENTRY(cyg_alarm_get_times_entry, \
+ "cyg_alarm_get_times", cyg_alarm_get_times); \
+CYG_LDR_TABLE_ENTRY(cyg_alarm_enable_entry, \
+ "cyg_alarm_enable", cyg_alarm_enable); \
+CYG_LDR_TABLE_ENTRY(cyg_alarm_disable_entry, \
+ "cyg_alarm_disable", cyg_alarm_disable);
+
+#define CYG_LDR_TABLE_KAPI_CLOCK() \
+CYG_LDR_TABLE_ENTRY(cyg_clock_create_entry, \
+ "cyg_clock_create", cyg_clock_create); \
+CYG_LDR_TABLE_ENTRY(cyg_clock_delete_entry, \
+ "cyg_clock_delete", cyg_clock_delete); \
+CYG_LDR_TABLE_ENTRY(cyg_clock_to_counter_entry, \
+ "cyg_clock_to_counter", cyg_clock_to_counter); \
+CYG_LDR_TABLE_ENTRY(cyg_clock_set_resolution_entry, \
+ "cyg_clock_set_resolution", cyg_clock_set_resolution); \
+CYG_LDR_TABLE_ENTRY(cyg_clock_get_resolution_entry, \
+ "cyg_clock_get_resolution",cyg_clock_get_resolution); \
+CYG_LDR_TABLE_ENTRY(cyg_real_time_clock_entry, \
+ "cyg_real_time_clock", cyg_real_time_clock); \
+CYG_LDR_TABLE_ENTRY(cyg_current_time_entry, \
+ "cyg_current_time", cyg_current_time);
+
+#define CYG_LDR_TABLE_KAPI_COND() \
+CYG_LDR_TABLE_ENTRY(cyg_cond_init_entry, \
+ "cyg_cond_init", cyg_cond_init); \
+CYG_LDR_TABLE_ENTRY(cyg_cond_destroy_entry, \
+ "cyg_cond_destroy", cyg_cond_destroy); \
+CYG_LDR_TABLE_ENTRY(cyg_cond_wait_entry, \
+ "cyg_cond_wait", cyg_cond_wait); \
+CYG_LDR_TABLE_ENTRY(cyg_cond_signal_entry, \
+ "cyg_cond_signal", cyg_cond_signal); \
+CYG_LDR_TABLE_ENTRY(cyg_cond_broadcast_entry, \
+ "cyg_cond_broadcast", cyg_cond_broadcast); \
+CYG_LDR_TABLE_ENTRY(cyg_cond_timed_wait_entry, \
+ "cyg_cond_timed_wait", cyg_cond_timed_wait);
+
+#define CYG_LDR_TABLE_KAPI_COUNTER() \
+CYG_LDR_TABLE_ENTRY(cyg_counter_create_entry, \
+ "cyg_counter_create", cyg_counter_create); \
+CYG_LDR_TABLE_ENTRY(cyg_counter_delete_entry, \
+ "cyg_counter_delete", cyg_counter_delete); \
+CYG_LDR_TABLE_ENTRY(cyg_counter_current_value_entry, \
+ "cyg_counter_current_value", cyg_counter_current_value); \
+CYG_LDR_TABLE_ENTRY(cyg_counter_set_value_entry, \
+ "cyg_counter_set_value", cyg_counter_set_value); \
+CYG_LDR_TABLE_ENTRY(cyg_counter_tick_entry, \
+ "cyg_counter_tick", cyg_counter_tick); \
+CYG_LDR_TABLE_ENTRY(cyg_counter_multi_tick_entry, \
+ "cyg_counter_multi_tick", cyg_counter_multi_tick);
+
+#define CYG_LDR_TABLE_KAPI_EXCEPTIONS() \
+CYG_LDR_TABLE_ENTRY(cyg_exception_set_handler_entry, \
+ "cyg_exception_set_handler", cyg_exception_set_handler); \
+CYG_LDR_TABLE_ENTRY(cyg_exception_clear_handler_entry, \
+ "cyg_exception_clear_handler", \
+ cyg_exception_clear_handler); \
+CYG_LDR_TABLE_ENTRY(cyg_exception_call_handler_entry, \
+ "cyg_exception_call_handler", \
+ cyg_exception_call_handler);
+
+#define CYG_LDR_TABLE_KAPI_FLAG() \
+CYG_LDR_TABLE_ENTRY(cyg_flag_init_entry, \
+ "cyg_flag_init", cyg_flag_init); \
+CYG_LDR_TABLE_ENTRY(cyg_flag_destroy_entry, \
+ "cyg_flag_destroy", cyg_flag_destroy); \
+CYG_LDR_TABLE_ENTRY(cyg_flag_setbits_entry, \
+ "cyg_flag_setbits", cyg_flag_setbits); \
+CYG_LDR_TABLE_ENTRY(cyg_flag_maskbits_entry, \
+ "cyg_flag_maskbits", cyg_flag_maskbits); \
+CYG_LDR_TABLE_ENTRY(cyg_flag_wait_entry, \
+ "cyg_flag_wait", cyg_flag_wait); \
+CYG_LDR_TABLE_ENTRY(cyg_flag_timed_wait_entry, \
+ "cyg_flag_timed_wait", cyg_flag_timed_wait); \
+CYG_LDR_TABLE_ENTRY(cyg_flag_poll_entry, \
+ "cyg_flag_poll", cyg_flag_poll); \
+CYG_LDR_TABLE_ENTRY(cyg_flag_peek_entry, \
+ "cyg_flag_peek", cyg_flag_peek); \
+CYG_LDR_TABLE_ENTRY(cyg_flag_waiting_entry, \
+ "cyg_flag_waiting", cyg_flag_waiting);
+
+#define CYG_LDR_TABLE_KAPI_INTERRUPTS() \
+CYG_LDR_TABLE_ENTRY(cyg_interrupt_create_entry, \
+ "cyg_interrupt_create", cyg_interrupt_create); \
+CYG_LDR_TABLE_ENTRY(cyg_interrupt_delete_entry, \
+ "cyg_interrupt_delete", cyg_interrupt_delete); \
+CYG_LDR_TABLE_ENTRY(cyg_interrupt_attach_entry, \
+ "cyg_interrupt_attach", cyg_interrupt_attach); \
+CYG_LDR_TABLE_ENTRY(cyg_interrupt_detach_entry, \
+ "cyg_interrupt_detach", cyg_interrupt_detach); \
+CYG_LDR_TABLE_ENTRY(cyg_interrupt_get_vsr_entry, \
+ "cyg_interrupt_get_vsr", cyg_interrupt_get_vsr); \
+CYG_LDR_TABLE_ENTRY(cyg_interrupt_set_vsr_entry, \
+ "cyg_interrupt_set_vsr", cyg_interrupt_set_vsr); \
+CYG_LDR_TABLE_ENTRY(cyg_interrupt_disable_entry, \
+ "cyg_interrupt_disable", cyg_interrupt_disable); \
+CYG_LDR_TABLE_ENTRY(cyg_interrupt_enable_entry, \
+ "cyg_interrupt_enable", cyg_interrupt_enable); \
+CYG_LDR_TABLE_ENTRY(cyg_interrupt_mask_entry, \
+ "cyg_interrupt_mask", cyg_interrupt_mask); \
+CYG_LDR_TABLE_ENTRY(cyg_interrupt_mask_intunsafe_entry, \
+ "cyg_interrupt_mask_intunsafe", \
+ cyg_interrupt_mask_intunsafe); \
+CYG_LDR_TABLE_ENTRY(cyg_interrupt_unmask_entry, \
+ "cyg_interrupt_unmask", cyg_interrupt_unmask); \
+CYG_LDR_TABLE_ENTRY(cyg_interrupt_unmask_intunsafe_entry, \
+ "cyg_interrupt_unmask_intunsafe", \
+ cyg_interrupt_unmask_intunsafe); \
+CYG_LDR_TABLE_ENTRY(cyg_interrupt_acknowledge_entry, \
+ "cyg_interrupt_acknowledge", \
+ cyg_interrupt_acknowledge); \
+CYG_LDR_TABLE_ENTRY(cyg_interrupt_configure_entry, \
+ "cyg_interrupt_configure", cyg_interrupt_configure); \
+CYG_LDR_TABLE_ENTRY(cyg_interrupt_set_cpu_entry, \
+ "cyg_interrupt_set_cpu", cyg_interrupt_set_cpu); \
+CYG_LDR_TABLE_ENTRY(cyg_interrupt_get_cpu_entry, \
+ "cyg_interrupt_get_cpu", cyg_interrupt_get_cpu);
+
+#define CYG_LDR_TABLE_KAPI_MBOX() \
+CYG_LDR_TABLE_ENTRY(cyg_mbox_create_entry, \
+ "cyg_mbox_create", cyg_mbox_create); \
+CYG_LDR_TABLE_ENTRY(cyg_mbox_delete_entry, \
+ "cyg_mbox_delete", cyg_mbox_delete); \
+CYG_LDR_TABLE_ENTRY(cyg_mbox_get_entry, \
+ "cyg_mbox_get", cyg_mbox_get); \
+CYG_LDR_TABLE_ENTRY(cyg_mbox_timed_get_entry, \
+ "cyg_mbox_timed_get", cyg_mbox_timed_get); \
+CYG_LDR_TABLE_ENTRY(cyg_mbox_tryget_entry, \
+ "cyg_mbox_tryget", cyg_mbox_tryget); \
+CYG_LDR_TABLE_ENTRY(cyg_mbox_peek_item_entry, \
+ "cyg_mbox_peek_item", cyg_mbox_peek_item); \
+CYG_LDR_TABLE_ENTRY(cyg_mbox_put_entry, \
+ "cyg_mbox_put", cyg_mbox_put); \
+CYG_LDR_TABLE_ENTRY(cyg_mbox_timed_put_entry, \
+ "cyg_mbox_timed_put", cyg_mbox_timed_put); \
+CYG_LDR_TABLE_ENTRY(cyg_mbox_tryput_entry, \
+ "cyg_mbox_tryput", cyg_mbox_tryput); \
+CYG_LDR_TABLE_ENTRY(cyg_mbox_peek_entry, \
+ "cyg_mbox_peek", cyg_mbox_peek); \
+CYG_LDR_TABLE_ENTRY(cyg_mbox_waiting_to_get_entry, \
+ "cyg_mbox_waiting_to_get", \
+ cyg_mbox_waiting_to_get); \
+CYG_LDR_TABLE_ENTRY(cyg_mbox_waiting_to_put_entry, \
+ "cyg_mbox_waiting_to_put", \
+ cyg_mbox_waiting_to_put);
+
+#define CYG_LDR_TABLE_KAPI_MEMPOOL_FIX() \
+CYG_LDR_TABLE_ENTRY(cyg_mempool_fix_create_entry, \
+ "cyg_mempool_fix_create", cyg_mempool_fix_create); \
+CYG_LDR_TABLE_ENTRY(cyg_mempool_fix_delete_entry, \
+ "cyg_mempool_fix_delete", cyg_mempool_fix_delete); \
+CYG_LDR_TABLE_ENTRY(cyg_mempool_fix_alloc_entry, \
+ "cyg_mempool_fix_alloc", cyg_mempool_fix_alloc); \
+CYG_LDR_TABLE_ENTRY(cyg_mempool_fix_timed_alloc_entry, \
+ "cyg_mempool_fix_timed_alloc", \
+ cyg_mempool_fix_timed_alloc); \
+CYG_LDR_TABLE_ENTRY(cyg_mempool_fix_try_alloc_entry, \
+ "cyg_mempool_fix_try_alloc", \
+ cyg_mempool_fix_try_alloc); \
+CYG_LDR_TABLE_ENTRY(cyg_mempool_fix_free_entry, \
+ "cyg_mempool_fix_free", cyg_mempool_fix_free); \
+CYG_LDR_TABLE_ENTRY(cyg_mempool_fix_waiting_entry, \
+ "cyg_mempool_fix_waiting", cyg_mempool_fix_waiting); \
+CYG_LDR_TABLE_ENTRY(cyg_mempool_fix_get_info_entry, \
+ "cyg_mempool_fix_get_info", cyg_mempool_fix_get_info);
+
+#define CYG_LDR_TABLE_KAPI_MEMPOOL_VAR() \
+CYG_LDR_TABLE_ENTRY(cyg_mempool_var_create_entry, \
+ "cyg_mempool_var_create", cyg_mempool_var_create); \
+CYG_LDR_TABLE_ENTRY(cyg_mempool_var_delete_entry, \
+ "cyg_mempool_var_delete", cyg_mempool_var_delete); \
+CYG_LDR_TABLE_ENTRY(cyg_mempool_var_alloc_entry, \
+ "cyg_mempool_var_alloc", cyg_mempool_var_alloc); \
+CYG_LDR_TABLE_ENTRY(cyg_mempool_var_timed_alloc_entry, \
+ "cyg_mempool_var_timed_alloc", \
+ cyg_mempool_var_timed_alloc); \
+CYG_LDR_TABLE_ENTRY(cyg_mempool_var_try_alloc_entry, \
+ "cyg_mempool_var_try_alloc", \
+ cyg_mempool_var_try_alloc); \
+CYG_LDR_TABLE_ENTRY(cyg_mempool_var_free_entry, \
+ "cyg_mempool_var_free", cyg_mempool_var_free); \
+CYG_LDR_TABLE_ENTRY(cyg_mempool_var_waiting_entry, \
+ "cyg_mempool_var_waiting", cyg_mempool_var_waiting); \
+CYG_LDR_TABLE_ENTRY(cyg_mempool_var_get_info_entry, \
+ "cyg_mempool_var_get_info", cyg_mempool_var_get_info);
+
+#define CYG_LDR_TABLE_KAPI_MUTEX() \
+CYG_LDR_TABLE_ENTRY(cyg_mutex_init_entry, \
+ "cyg_mutex_init", cyg_mutex_init); \
+CYG_LDR_TABLE_ENTRY(cyg_mutex_destroy_entry, \
+ "cyg_mutex_destroy", cyg_mutex_destroy); \
+CYG_LDR_TABLE_ENTRY(cyg_mutex_trylock_entry, \
+ "cyg_mutex_trylock", cyg_mutex_trylock); \
+CYG_LDR_TABLE_ENTRY(cyg_mutex_unlock_entry, \
+ "cyg_mutex_unlock", cyg_mutex_unlock); \
+CYG_LDR_TABLE_ENTRY(cyg_mutex_release_entry, \
+ "cyg_mutex_release", cyg_mutex_release); \
+CYG_LDR_TABLE_ENTRY(cyg_mutex_set_ceiling_entry, \
+ "cyg_mutex_set_ceiling", cyg_mutex_set_ceiling); \
+CYG_LDR_TABLE_ENTRY(cyg_mutex_set_protocol_entry, \
+ "cyg_mutex_set_protocol", cyg_mutex_set_protocol);
+
+#define CYG_LDR_TABLE_KAPI_SCHEDULER() \
+CYG_LDR_TABLE_ENTRY(cyg_scheduler_start_entry, \
+ "cyg_scheduler_start", cyg_scheduler_start); \
+CYG_LDR_TABLE_ENTRY(cyg_scheduler_lock_entry, \
+ "cyg_scheduler_lock", cyg_scheduler_lock); \
+CYG_LDR_TABLE_ENTRY(cyg_scheduler_safe_lock_entry, \
+ "cyg_scheduler_safe_lock", cyg_scheduler_safe_lock); \
+CYG_LDR_TABLE_ENTRY(cyg_scheduler_unlock_entry, \
+ "cyg_scheduler_unlock", cyg_scheduler_unlock); \
+CYG_LDR_TABLE_ENTRY(cyg_scheduler_read_lock_entry, \
+ "cyg_scheduler_read_lock", cyg_scheduler_read_lock); \
+
+#define CYG_LDR_TABLE_KAPI_SEMAPHORE() \
+CYG_LDR_TABLE_ENTRY(cyg_semaphore_init_entry, \
+ "cyg_semaphore_init", cyg_semaphore_init); \
+CYG_LDR_TABLE_ENTRY(cyg_semaphore_destroy_entry, \
+ "cyg_semaphore_destroy", cyg_semaphore_destroy); \
+CYG_LDR_TABLE_ENTRY(cyg_semaphore_wait_entry, \
+ "cyg_semaphore_wait", cyg_semaphore_wait); \
+CYG_LDR_TABLE_ENTRY(cyg_semaphore_timed_wait_entry, \
+ "cyg_semaphore_timed_wait", cyg_semaphore_timed_wait); \
+CYG_LDR_TABLE_ENTRY(cyg_semaphore_try_wait_entry, \
+ "cyg_semaphore_trywait", cyg_semaphore_trywait); \
+CYG_LDR_TABLE_ENTRY(cyg_semaphore_post_entry, \
+ "cyg_semaphore_post", cyg_semaphore_post); \
+CYG_LDR_TABLE_ENTRY(cyg_semaphore_peek_entry, \
+ "cyg_semaphore_peek", cyg_semaphore_peek);
+
+#define CYG_LDR_TABLE_KAPI_THREAD() \
+CYG_LDR_TABLE_ENTRY(cyg_thread_create_entry, \
+ "cyg_thread_create", cyg_thread_create); \
+CYG_LDR_TABLE_ENTRY(cyg_thread_exit_entry, \
+ "cyg_thread_exit", cyg_thread_exit); \
+CYG_LDR_TABLE_ENTRY(cyg_thread_delete_entry, \
+ "cyg_thread_delete", cyg_thread_delete); \
+CYG_LDR_TABLE_ENTRY(cyg_thread_suspend_entry, \
+ "cyg_thread_suspend", cyg_thread_suspend); \
+CYG_LDR_TABLE_ENTRY(cyg_thread_resume_entry, \
+ "cyg_thread_resume", cyg_thread_resume); \
+CYG_LDR_TABLE_ENTRY(cyg_thread_kill_entry, \
+ "cyg_thread_kill", cyg_thread_kill); \
+CYG_LDR_TABLE_ENTRY(cyg_thread_release_entry, \
+ "cyg_thread_release", cyg_thread_release); \
+CYG_LDR_TABLE_ENTRY(cyg_thread_yield_entry, \
+ "cyg_thread_yield", cyg_thread_yield); \
+CYG_LDR_TABLE_ENTRY(cyg_thread_self_entry, \
+ "cyg_thread_self", cyg_thread_self); \
+CYG_LDR_TABLE_ENTRY(cyg_thread_idle_thread_entry, \
+ "cyg_thread_idle_thread", cyg_thread_idle_thread); \
+CYG_LDR_TABLE_ENTRY(cyg_thread_set_priority_entry, \
+ "cyg_thread_set_priority", cyg_thread_set_priority); \
+CYG_LDR_TABLE_ENTRY(cyg_thread_get_priority_entry, \
+ "cyg_thread_get_priority", cyg_thread_get_priority); \
+CYG_LDR_TABLE_ENTRY(cyg_thread_get_current_priority_entry, \
+ "cyg_thread_get_current_priority", \
+ cyg_thread_get_current_priority); \
+CYG_LDR_TABLE_ENTRY(cyg_thread_delay_entry, \
+ "cyg_thread_delay", cyg_thread_delay); \
+CYG_LDR_TABLE_ENTRY(cyg_thread_get_stack_base_entry, \
+ "cyg_thread_get_stack_base", cyg_thread_get_stack_base); \
+CYG_LDR_TABLE_ENTRY(cyg_thread_get_stack_size_entry, \
+ "cyg_thread_get_stack_size", cyg_thread_get_stack_size); \
+CYG_LDR_TABLE_ENTRY(cyg_thread_new_data_index_entry, \
+ "cyg_thread_new_data_index", cyg_thread_new_data_index); \
+CYG_LDR_TABLE_ENTRY(cyg_thread_free_data_index_entry, \
+ "cyg_thread_free_data_index", \
+ cyg_thread_free_data_index); \
+CYG_LDR_TABLE_ENTRY(cyg_thread_get_data_entry, \
+ "cyg_thread_get_data", cyg_thread_get_data); \
+CYG_LDR_TABLE_ENTRY(cyg_thread_get_data_ptr_entry, \
+ "cyg_thread_get_data_ptr", cyg_thread_get_data_ptr); \
+CYG_LDR_TABLE_ENTRY(cyg_thread_set_data_entry, \
+ "cyg_thread_set_data", cyg_thread_set_data);
+
+#define CYG_LDR_TABLE_STRING() \
+CYG_LDR_TABLE_ENTRY(memchr_entry, "memchr", memchr); \
+CYG_LDR_TABLE_ENTRY(memcmp_entry, "memcmp", memcmp); \
+CYG_LDR_TABLE_ENTRY(memcpy_entry, "memcpy", memcpy); \
+CYG_LDR_TABLE_ENTRY(memmove_entry, "memmove", memmove); \
+CYG_LDR_TABLE_ENTRY(memset_entry, "memset", memset); \
+CYG_LDR_TABLE_ENTRY(strcpy_entry, "strcpy", strcpy); \
+CYG_LDR_TABLE_ENTRY(strncpy_entry, "strncpy", strncpy); \
+CYG_LDR_TABLE_ENTRY(strcat_entry, "strcat", strcat); \
+CYG_LDR_TABLE_ENTRY(strncat_entry, "strncat", strncat); \
+CYG_LDR_TABLE_ENTRY(strchr_entry, "strchr", strchr); \
+CYG_LDR_TABLE_ENTRY(strrchr_entry, "strrchr", strrchr); \
+CYG_LDR_TABLE_ENTRY(strcoll_entry, "strcoll", strcoll); \
+CYG_LDR_TABLE_ENTRY(strlen_entry, "strlen", strlen); \
+CYG_LDR_TABLE_ENTRY(strcmp_entry, "strcmp", strcmp); \
+CYG_LDR_TABLE_ENTRY(strncmp_entry, "strncmp", strncmp); \
+CYG_LDR_TABLE_ENTRY(strcspn_entry, "strcspn", strcspn); \
+CYG_LDR_TABLE_ENTRY(strerror_entry, "strerror", strerror); \
+CYG_LDR_TABLE_ENTRY(strpbrk_entry, "strpbrk", strpbrk); \
+CYG_LDR_TABLE_ENTRY(strspn_entry, "strspn", strspn); \
+CYG_LDR_TABLE_ENTRY(strstr_entry, "strstr", strstr); \
+CYG_LDR_TABLE_ENTRY(strtok_entry, "strtok", strtok); \
+CYG_LDR_TABLE_ENTRY(strxfrm_entry, "strxfrm", strxfrm);
+
+#define CYG_LDR_TABLE_STDIO() \
+CYG_LDR_TABLE_ENTRY(clearerr_entry, "clearerr", clearerr); \
+CYG_LDR_TABLE_ENTRY(fclose_entry, "fclose", fclose); \
+CYG_LDR_TABLE_ENTRY(feof_entry, "feof", feof); \
+CYG_LDR_TABLE_ENTRY(ferror_entry, "ferror", ferror); \
+CYG_LDR_TABLE_ENTRY(fflush_entry, "fflush", fflush); \
+CYG_LDR_TABLE_ENTRY(fgetc_entry, "fgetc", fgetc); \
+CYG_LDR_TABLE_ENTRY(fgetpos_entry, "fgetpos", fgetpos); \
+CYG_LDR_TABLE_ENTRY(fgets_entry, "fgets", fgets); \
+CYG_LDR_TABLE_ENTRY(fopen_entry, "fopen", fopen); \
+CYG_LDR_TABLE_ENTRY(fprintf_entry, "fprintf", fprintf); \
+CYG_LDR_TABLE_ENTRY(fputc_entry, "fputc", fputc); \
+CYG_LDR_TABLE_ENTRY(fputs_entry, "fputs", fputs); \
+CYG_LDR_TABLE_ENTRY(fread_entry, "fread", fread); \
+CYG_LDR_TABLE_ENTRY(freopen_entry, "freopen", freopen); \
+CYG_LDR_TABLE_ENTRY(fscanf_entry, "fscanf", fscanf); \
+CYG_LDR_TABLE_ENTRY(fseek_entry, "fseek", fseek); \
+CYG_LDR_TABLE_ENTRY(fsetpos_entry, "fsetpos", fsetpos); \
+CYG_LDR_TABLE_ENTRY(ftell_entry, "ftell", ftell); \
+CYG_LDR_TABLE_ENTRY(fwrite_entry, "fwrite", fwrite); \
+CYG_LDR_TABLE_ENTRY(perror_entry, "perror", perror); \
+CYG_LDR_TABLE_ENTRY(printf_entry, "printf", printf); \
+CYG_LDR_TABLE_ENTRY(putc_entry, "putc", putc); \
+CYG_LDR_TABLE_ENTRY(putchar_entry, "putchar", putchar); \
+CYG_LDR_TABLE_ENTRY(puts_entry, "puts", puts); \
+CYG_LDR_TABLE_ENTRY(remove_entry, "remove", remove); \
+CYG_LDR_TABLE_ENTRY(rename_entry, "rename", rename); \
+CYG_LDR_TABLE_ENTRY(rewind_entry, "rewind", rewind); \
+CYG_LDR_TABLE_ENTRY(scanf_entry, "scanf", scanf); \
+CYG_LDR_TABLE_ENTRY(setbuf_entry, "setbuf", setbuf); \
+CYG_LDR_TABLE_ENTRY(setvbuf_entry, "setvbuf", setvbuf); \
+CYG_LDR_TABLE_ENTRY(sprintf_entry, "sprintf", sprintf); \
+CYG_LDR_TABLE_ENTRY(sscanf_entry, "sscanf", sscanf); \
+CYG_LDR_TABLE_ENTRY(tmpfile_entry, "tmpfile", tmpfile); \
+CYG_LDR_TABLE_ENTRY(tmpnam_entry, "tmpnam", tmpnam); \
+CYG_LDR_TABLE_ENTRY(ungetc_entry, "ungetc", ungetc);
+
+#define CYG_LDR_TABLE_INFRA_DIAG() \
+CYG_LDR_TABLE_ENTRY(diag_init_entry, "diag_init", diag_init); \
+CYG_LDR_TABLE_ENTRY(diag_write_char_entry, \
+ "diag_write_char", diag_write_char); \
+CYG_LDR_TABLE_ENTRY(diag_write_string_entry, \
+ "diag_write_string", diag_write_string); \
+CYG_LDR_TABLE_ENTRY(diag_write_dec_entry, \
+ "diag_write_dec", diag_write_dec); \
+CYG_LDR_TABLE_ENTRY(diag_write_hex_entry, \
+ "diag_write_hex", diag_write_hex); \
+CYG_LDR_TABLE_ENTRY(diag_dump_buf_entry, \
+ "diag_dump_buf", diag_dump_buf); \
+CYG_LDR_TABLE_ENTRY(diag_dump_buf_32bit_entry, \
+ "diag_dump_buf_32bit", diag_dump_buf_32bit); \
+CYG_LDR_TABLE_ENTRY(diag_dump_buf_16bit_entry, \
+ "diag_dump_buf_16bit", diag_dump_buf_16bit); \
+CYG_LDR_TABLE_ENTRY(diag_vdump_buf_with_offset_entry, \
+ "diag_vdump_buf_with_offset", \
+ diag_vdump_buf_with_offset); \
+CYG_LDR_TABLE_ENTRY(diag_dump_buf_with_offset_entry, \
+ "diag_dump_buf_with_offset", \
+ diag_dump_buf_with_offset); \
+CYG_LDR_TABLE_ENTRY(diag_dump_buf_with_offset_32bit_entry, \
+ "diag_dump_buf_with_offset_32bit", \
+ diag_dump_buf_with_offset_32bit); \
+CYG_LDR_TABLE_ENTRY(diag_dump_buf_with_offset_16bit_entry, \
+ "diag_dump_buf_with_offset_16bit", \
+ diag_dump_buf_with_offset_16bit); \
+CYG_LDR_TABLE_ENTRY(diag_printf_entry, "diag_printf", diag_printf); \
+CYG_LDR_TABLE_ENTRY(diag_init_putc_entry, "diag_init_putc", diag_init_putc); \
+CYG_LDR_TABLE_ENTRY(diag_sprintf_entry, "diag_sprintf", diag_sprintf); \
+CYG_LDR_TABLE_ENTRY(diag_snprintf_entry, "diag_snprintf", diag_snprintf); \
+CYG_LDR_TABLE_ENTRY(diag_vsprintf_entry, "diag_vsprintf", diag_vsprintf); \
+CYG_LDR_TABLE_ENTRY(diag_vprintf_entry, "diag_vprintf", diag_vprintf);
//==============================================================================
#endif
#define ELF_ARCH_ENDIANNESS ELFDATA2LSB
#define ELF_ARCH_RELTYPE Elf_Rel
-#define R_386_32 1
-#define R_386_PC32 2
+#define R_386_32 1
+#define R_386_PC32 2
-void cyg_ldr_flush_cache( void );
-cyg_int32 cyg_ldr_relocate( cyg_int32, cyg_uint32, cyg_int32 );
+void cyg_ldr_flush_cache(void);
+cyg_int32 cyg_ldr_relocate(cyg_int32, cyg_uint32, cyg_int32);
#endif //__RELOCATE_I386_H__
* =================================================================
* #####DESCRIPTIONBEGIN####
*
- * Author(s): atonizzo@lycos.com
+ * Author(s): Anthony Tonizzo (atonizzo@gmail.com)
* Date: 2005-05-13
* Purpose:
* Description:
* =================================================================
* #####DESCRIPTIONBEGIN####
*
- * Author(s): atonizzo@lycos.com
+ * Author(s): Anthony Tonizzo (atonizzo@gmail.com)
* Contributors: nickg@ecoscentric.com
* Date: 2005-05-13
* Purpose:
#include <cyg/objloader/loader_fs.h>
size_t
-cyg_ldr_fs_read( PELF_OBJECT p, size_t s, size_t n, void *mem )
+cyg_ldr_fs_read(PELF_OBJECT p, size_t s, size_t n, void *mem)
{
- return fread( mem, s, n, (FILE*)p->ptr );
+ return fread(mem, s, n, (FILE*)p->ptr);
}
cyg_int32
-cyg_ldr_fs_seek( PELF_OBJECT p, cyg_uint32 offs )
+cyg_ldr_fs_seek(PELF_OBJECT p, cyg_uint32 offs)
{
- return fseek( (FILE*)p->ptr, offs, SEEK_SET );
+ return fseek((FILE*)p->ptr, offs, SEEK_SET);
}
cyg_int32
-cyg_ldr_fs_close( PELF_OBJECT p )
+cyg_ldr_fs_close(PELF_OBJECT p)
{
- return fclose( (FILE*)p->ptr );
+ return fclose((FILE*)p->ptr);
}
PELF_OBJECT
-cyg_ldr_open_library_fs( cyg_uint8 *ptr )
+cyg_ldr_open_library_fs(char *ptr)
{
- PELF_OBJECT e_obj;
- FILE *fp;
-
- fp = fopen( ptr, "rb" );
- if ( fp == 0 )
+ FILE *fp = fopen(ptr, "rb");
+ if (fp == NULL)
{
cyg_ldr_last_error = "FILE NOT FOUND";
return (void*)0;
}
// Create a file object to keep track of this library.
- e_obj = (PELF_OBJECT)malloc( sizeof( ELF_OBJECT ) );
- CYG_ASSERT( e_obj != 0, "Cannot malloc() e_obj" );
- if ( e_obj == 0 )
+ PELF_OBJECT e_obj = (PELF_OBJECT)malloc(sizeof(ELF_OBJECT));
+ CYG_ASSERT(e_obj != 0, "Cannot malloc() e_obj");
+ if (e_obj == 0)
{
cyg_ldr_last_error = "ERROR IN MALLOC";
- fclose( fp );
+ fclose(fp);
return (void*)0;
}
- memset( e_obj, 0, sizeof( ELF_OBJECT ) );
+ memset(e_obj, 0, sizeof(ELF_OBJECT));
e_obj->ptr = (CYG_ADDRWORD)fp;
e_obj->mode = CYG_LDR_MODE_FILESYSTEM;
}
void
-cyg_ldr_close_library_fs( PELF_OBJECT p )
+cyg_ldr_close_library_fs(PELF_OBJECT p)
{
}
* =================================================================
* #####DESCRIPTIONBEGIN####
*
- * Author(s): atonizzo@lycos.com
+ * Author(s): Anthony Tonizzo (atonizzo@gmail.com)
* Contributors: nickg@ecoscentric.com
* Date: 2005-05-13
* Purpose:
#include <cyg/objloader/elf.h>
#include <cyg/objloader/objelf.h>
-CYG_HAL_TABLE_BEGIN( cyg_ldr_table, ldr_table );
-CYG_HAL_TABLE_END( cyg_ldr_table_end, ldr_table );
+CYG_HAL_TABLE_BEGIN(cyg_ldr_table, ldr_table);
+CYG_HAL_TABLE_END(cyg_ldr_table_end, ldr_table);
__externC cyg_ldr_table_entry cyg_ldr_table[];
__externC cyg_ldr_table_entry cyg_ldr_table_end[];
#if CYGPKG_SERVICES_OBJLOADER_DEBUG_LEVEL > 0
void
-cyg_ldr_print_section_data( PELF_OBJECT p )
+cyg_ldr_print_section_data(PELF_OBJECT p)
{
- cyg_int32 i;
- cyg_uint8 strname[32];
- cyg_uint8 *p_strtab = (cyg_uint8*)p->sections[p->p_elfhdr->e_shstrndx];
+ int i;
+ char strname[32];
+ char *p_strtab = (char*)p->sections[p->p_elfhdr->e_shstrndx];
- diag_printf( "\n\nSection Headers:\n" );
- diag_printf( "[Nr] Name Addr Offset Size Info\n" );
- for ( i = 0; i < p->p_elfhdr->e_shnum; i++ )
+ diag_printf("\n\nSection Headers:\n");
+ diag_printf("[Nr] Name Addr Offset Size Info\n");
+ for (i = 0; i < p->p_elfhdr->e_shnum; i++)
{
- sprintf( strname, "%s", p_strtab + p->p_sechdr[i].sh_name );
- while ( strlen( strname ) < 20 )
- strcat( strname, " " );
- diag_printf( "[%02d] %s %08X %08X %08X %08X\n",
+ sprintf(strname, "%s", p_strtab + p->p_sechdr[i].sh_name);
+ while (strlen(strname) < 20)
+ strcat(strname, " ");
+ diag_printf("[%02d] %s %08X %08X %08X %08X\n",
i,
strname,
p->p_sechdr[i].sh_addr,
p->p_sechdr[i].sh_offset,
p->p_sechdr[i].sh_size,
- p->p_sechdr[i].sh_info );
+ p->p_sechdr[i].sh_info);
}
- diag_printf( "\n" );
+ diag_printf("\n");
}
void
-cyg_ldr_print_symbol_names( PELF_OBJECT p )
+cyg_ldr_print_symbol_names(PELF_OBJECT p)
{
- cyg_int32 i, symtab_entries;
+ int i;
Elf32_Sym *p_symtab = (Elf32_Sym*)p->sections[p->hdrndx_symtab];
- cyg_uint8 *p_strtab = (cyg_uint8*)p->sections[p->hdrndx_strtab];
- cyg_uint8 strname[32];
+ char *p_strtab = (char*)p->sections[p->hdrndx_strtab];
+ char strname[32];
// Total number of entries in the symbol table.
- symtab_entries = p->p_sechdr[p->hdrndx_symtab].sh_size /
+ int symtab_entries = p->p_sechdr[p->hdrndx_symtab].sh_size /
p->p_sechdr[p->hdrndx_symtab].sh_entsize;
- diag_printf( "Num Value Size Ndx Name\n" );
- for ( i = 1; i < symtab_entries; i++ )
+ diag_printf("Num Value Size Ndx Name\n");
+ for (i = 1; i < symtab_entries; i++)
{
- sprintf( strname, "%d", i );
- while ( strlen( strname ) < 5 )
- strcat( strname, " " );
- diag_printf( strname );
+ sprintf(strname, "%d", i);
+ while (strlen(strname) < 5)
+ strcat(strname, " ");
+ diag_printf(strname);
- sprintf( strname,
+ sprintf(strname,
"%08X %d",
p_symtab[i].st_value,
- p_symtab[i].st_size );
- while ( strlen( strname ) < 15 )
- strcat( strname, " " );
- diag_printf( strname );
+ p_symtab[i].st_size);
+ while (strlen(strname) < 15)
+ strcat(strname, " ");
+ diag_printf(strname);
- sprintf( strname, "%d", p_symtab[i].st_shndx );
- while ( strlen( strname ) < 6 )
- strcat( strname, " " );
- diag_printf( strname );
+ sprintf(strname, "%d", p_symtab[i].st_shndx);
+ while (strlen(strname) < 6)
+ strcat(strname, " ");
+ diag_printf(strname);
- strncpy( strname,
+ strncpy(strname,
p_strtab + p_symtab[i].st_name,
- sizeof( strname ) - 1 );
- strname[strlen( p_strtab + p_symtab[i].st_name )] = '\0';
- diag_printf( strname );
- diag_printf( "\n" );
+ sizeof(strname) - 1);
+ strname[strlen(p_strtab + p_symtab[i].st_name)] = '\0';
+ diag_printf(strname);
+ diag_printf("\n");
}
}
void
-cyg_ldr_print_rel_names( PELF_OBJECT p )
+cyg_ldr_print_rel_names(PELF_OBJECT p)
{
- cyg_int32 i, j, r_entries, sym_index;
+ int i, j, r_entries, sym_index;
Elf32_Sym *p_symtab = (Elf32_Sym*)p->sections[p->hdrndx_symtab];
- cyg_uint8 *p_strtab = (cyg_uint8*)p->sections[p->hdrndx_strtab];
- cyg_uint8 *p_shstrtab = (cyg_uint8*)p->sections[p->p_elfhdr->e_shstrndx];
+ char *p_strtab = (char*)p->sections[p->hdrndx_strtab];
+ char *p_shstrtab = (char*)p->sections[p->p_elfhdr->e_shstrndx];
#if ELF_ARCH_RELTYPE == Elf_Rela
Elf32_Rela* p_rela;
#else
Elf32_Rel* p_rel;
#endif
- cyg_uint8 strname[32];
+ char strname[32];
- for ( i = 1; i < p->p_elfhdr->e_shnum; i++ )
+ for (i = 1; i < p->p_elfhdr->e_shnum; i++)
{
- if ( ( p->p_sechdr[i].sh_type == SHT_REL ) ||
- ( p->p_sechdr[i].sh_type == SHT_RELA ) )
+ if ((p->p_sechdr[i].sh_type == SHT_REL) ||
+ (p->p_sechdr[i].sh_type == SHT_RELA))
{
// Calculate the total number of entries in the .rela section.
r_entries = p->p_sechdr[i].sh_size / p->p_sechdr[i].sh_entsize;
- diag_printf( "\n\nSymbols at: %s\n\n",
- p_shstrtab + p->p_sechdr[i].sh_name );
+ diag_printf("\n\nSymbols at: %s\n\n",
+ p_shstrtab + p->p_sechdr[i].sh_name);
#if ELF_ARCH_RELTYPE == Elf_Rela
- p_rela = (Elf32_Rela*)cyg_ldr_load_elf_section( p, i );
- printf( "Offset Info Name [+ Addend]\n" );
+ p_rela = (Elf32_Rela*)cyg_ldr_load_elf_section(p, i);
+ printf("Offset Info Name [+ Addend]\n");
#else
- p_rel = (Elf32_Rel*)cyg_ldr_load_elf_section( p, i );
- printf( "Offset Info Name\n" );
+ p_rel = (Elf32_Rel*)cyg_ldr_load_elf_section(p, i);
+ printf("Offset Info Name\n");
#endif
- for ( j = 0; j < r_entries; j++ )
+ for (j = 0; j < r_entries; j++)
{
- sprintf( strname,
+ sprintf(strname,
"%08X %08X ",
#if ELF_ARCH_RELTYPE == Elf_Rela
- p_rela[j].r_offset,
- p_rela[j].r_info
+ p_rela[j].r_offset,
+ p_rela[j].r_info
#else
- p_rel[j].r_offset,
- p_rel[j].r_info
+ p_rel[j].r_offset,
+ p_rel[j].r_info
#endif
- );
+ );
- diag_printf( strname );
+ diag_printf(strname);
#if ELF_ARCH_RELTYPE == Elf_Rela
- cyg_uint8 sym_type = ELF32_R_SYM( p_rela[j].r_info );
+ cyg_uint8 sym_type = ELF32_R_SYM(p_rela[j].r_info);
#else
- cyg_uint8 sym_type = ELF32_R_SYM( p_rel[j].r_info );
+ cyg_uint8 sym_type = ELF32_R_SYM(p_rel[j].r_info);
#endif
- if ( strlen ( p_strtab + p_symtab[sym_type].st_name ) > 0 )
- diag_printf( p_strtab + p_symtab[sym_type].st_name );
+ if (strlen (p_strtab + p_symtab[sym_type].st_name) > 0)
+ diag_printf(p_strtab + p_symtab[sym_type].st_name);
else
{
// If the symbol name is not available, then print
// the name of the section.
sym_index = p_symtab[sym_type].st_shndx;
- diag_printf( p_shstrtab + p->p_sechdr[sym_index].sh_name );
+ diag_printf(p_shstrtab + p->p_sechdr[sym_index].sh_name);
}
#if ELF_ARCH_RELTYPE == Elf_Rela
- if ( p_rela[j].r_addend != 0 )
- diag_printf( " + %08X", p_rela[j].r_addend );
+ if (p_rela[j].r_addend != 0)
+ diag_printf(" + %08X", p_rela[j].r_addend);
#endif
- diag_printf( "\n" );
+ diag_printf("\n");
}
// After all the printing is done, the relocation table can
// be dumped.
- cyg_ldr_delete_elf_section( p, i );
+ cyg_ldr_delete_elf_section(p, i);
}
}
}
#endif // DEBUG_PRINT
static void
-*cyg_ldr_local_address( PELF_OBJECT p, cyg_uint32 sym_index )
+*cyg_ldr_local_address(PELF_OBJECT p, cyg_uint32 sym_index)
{
cyg_uint32 data_sec, addr;
Elf32_Sym *p_symtab;
- p_symtab = (Elf32_Sym*)cyg_ldr_section_address( p, p->hdrndx_symtab );
+ p_symtab = (Elf32_Sym*)cyg_ldr_section_address(p, p->hdrndx_symtab);
// Find out the section number in which the data for this symbol is
// located.
// From the section number we get the start of the memory area in
// memory.
- addr = (cyg_uint32)cyg_ldr_section_address( p, data_sec );
+ addr = (cyg_uint32)cyg_ldr_section_address(p, data_sec);
// And now return the address of the data.
- return (void*)( addr + p_symtab[sym_index].st_value);
+ return (void*)(addr + p_symtab[sym_index].st_value);
}
void
-*cyg_ldr_external_address( PELF_OBJECT p, cyg_uint32 sym_index )
+*cyg_ldr_external_address(PELF_OBJECT p, cyg_uint32 sym_index)
{
cyg_uint8* tmp2;
Elf32_Sym *p_symtab;
cyg_ldr_table_entry *entry = cyg_ldr_table;
- p_symtab = (Elf32_Sym*)cyg_ldr_section_address( p, p->hdrndx_symtab );
- p_strtab = (cyg_uint8*)cyg_ldr_section_address( p, p->hdrndx_strtab );
+ p_symtab = (Elf32_Sym*)cyg_ldr_section_address(p, p->hdrndx_symtab);
+ p_strtab = (cyg_uint8*)cyg_ldr_section_address(p, p->hdrndx_strtab);
// This is the name of the external reference to search.
tmp2 = p_strtab + p_symtab[sym_index].st_name;
- while ( entry != cyg_ldr_table_end )
+ while (entry != cyg_ldr_table_end)
{
- if ( !strcmp( (const char*)tmp2, entry->symbol_name ) )
+ if (!strcmp((const char*)tmp2, entry->symbol_name ))
return entry->handler;
entry++;
}
// 0 : Symbol not found
// Other : Address of the symbol in absolute memory.
void
-*cyg_ldr_symbol_address( PELF_OBJECT p, cyg_uint32 sym_index )
+*cyg_ldr_symbol_address(PELF_OBJECT p, cyg_uint32 sym_index)
{
cyg_uint32 addr;
- cyg_uint8 sym_info;
- Elf32_Sym *p_symtab;
-
- p_symtab = (Elf32_Sym*)cyg_ldr_section_address( p, p->hdrndx_symtab );
- sym_info = p_symtab[sym_index].st_info;
-
- switch ( ELF32_ST_TYPE( sym_info ) )
+ Elf32_Sym *p_symtab = (Elf32_Sym*)cyg_ldr_section_address(p,
+ p->hdrndx_symtab);
+ cyg_uint8 sym_info = p_symtab[sym_index].st_info;
+ switch (ELF32_ST_TYPE(sym_info))
{
case STT_NOTYPE:
case STT_FUNC:
case STT_OBJECT:
- switch ( ELF32_ST_BIND( sym_info ) )
+ switch (ELF32_ST_BIND(sym_info))
{
case STB_LOCAL:
case STB_GLOBAL:
- if ( p_symtab[sym_index].st_shndx == SHN_UNDEF )
- return cyg_ldr_external_address( p, sym_index );
+ if (p_symtab[sym_index].st_shndx == SHN_UNDEF)
+ return cyg_ldr_external_address(p, sym_index);
else
- return cyg_ldr_local_address( p, sym_index );
+ return cyg_ldr_local_address(p, sym_index);
case STB_WEAK:
- addr = (cyg_uint32)cyg_ldr_external_address( p, sym_index );
- if ( addr != 0 )
+ addr = (cyg_uint32)cyg_ldr_external_address(p, sym_index);
+ if (addr != 0)
return (void*)addr;
else
- return cyg_ldr_local_address( p, sym_index );
+ return cyg_ldr_local_address(p, sym_index);
default:
return 0;
}
break;
case STT_SECTION:
// Return the starting address of a section, given its index.
- return (void*)cyg_ldr_section_address( p,
- p_symtab[sym_index].st_shndx );
+ return (void*)cyg_ldr_section_address(p, p_symtab[sym_index].st_shndx);
default:
return 0;
}
// Loads the relocation information, relocates, and dumps the relocation
// information once the process is complete.
cyg_int32
-cyg_ldr_relocate_section( PELF_OBJECT p, cyg_uint32 r_shndx )
+cyg_ldr_relocate_section(PELF_OBJECT p, cyg_uint32 r_shndx)
{
- cyg_int32 i, rc;
- cyg_uint32 r_entries, r_target_shndx, r_target_addr;
- cyg_uint32 sym_value, sym_index;
- Elf32_Addr r_offset;
- Elf32_Word r_type;
- Elf32_Sword r_addend;
+ int i, rc;
#if ELF_ARCH_RELTYPE == Elf_Rela
- Elf32_Rela* p_rela = (Elf32_Rela*)cyg_ldr_load_elf_section( p, r_shndx );
+ Elf32_Rela* p_rela = (Elf32_Rela*)cyg_ldr_load_elf_section(p, r_shndx);
#else
- Elf32_Rel* p_rel = (Elf32_Rel*)cyg_ldr_load_elf_section( p, r_shndx );
+ Elf32_Rel* p_rel = (Elf32_Rel*)cyg_ldr_load_elf_section(p, r_shndx);
#endif
#if CYGPKG_SERVICES_OBJLOADER_DEBUG_LEVEL > 0
- Elf32_Sym *p_symtab = (Elf32_Sym*)cyg_ldr_section_address( p,
- p->hdrndx_symtab );
- cyg_uint8 *p_strtab = (cyg_uint8*)cyg_ldr_section_address( p,
- p->hdrndx_strtab );
- cyg_uint8 *p_shstrtab = (cyg_uint8*)cyg_ldr_section_address( p,
- p->p_elfhdr->e_shstrndx );
+ Elf32_Sym *p_symtab = (Elf32_Sym*)cyg_ldr_section_address(p,
+ p->hdrndx_symtab);
+ char *p_strtab = (char*)cyg_ldr_section_address(p, p->hdrndx_strtab);
+ char *p_shstrtab = (char*)cyg_ldr_section_address(p,
+ p->p_elfhdr->e_shstrndx);
#endif
// Now we can get the address of the contents of the section to modify.
- r_target_shndx = p->p_sechdr[r_shndx].sh_info;
- r_target_addr = (cyg_uint32)cyg_ldr_section_address( p, r_target_shndx );
+ cyg_uint32 r_target_shndx = p->p_sechdr[r_shndx].sh_info;
+ cyg_uint32 r_target_addr = (cyg_uint32)cyg_ldr_section_address(p,
+ r_target_shndx);
#if CYGPKG_SERVICES_OBJLOADER_DEBUG_LEVEL > 0
- diag_printf( "Relocating section \"%s\"\n",
- p_shstrtab + p->p_sechdr[r_target_shndx].sh_name );
+ diag_printf("Relocating section \"%s\"\n",
+ p_shstrtab + p->p_sechdr[r_target_shndx].sh_name);
#if CYGPKG_SERVICES_OBJLOADER_DEBUG_LEVEL > 1
- diag_printf( "Ndx Type Offset Name\"\n" );
+ diag_printf("Ndx Type Offset Name\"\n");
#endif
#endif
// Perform relocatation for each of the members of this table.
- r_entries = p->p_sechdr[r_shndx].sh_size / p->p_sechdr[r_shndx].sh_entsize;
- for ( i = 0; i < r_entries; i++ )
+ cyg_uint32 r_entries = p->p_sechdr[r_shndx].sh_size /
+ p->p_sechdr[r_shndx].sh_entsize;
+ for (i = 0; i < r_entries; i++)
{
#if ELF_ARCH_RELTYPE == Elf_Rela
- r_offset = p_rela[i].r_offset;
- r_type = ELF32_R_TYPE( p_rela[i].r_info );
- sym_index = ELF32_R_SYM( p_rela[i].r_info );
- r_addend = p_rela[i].r_addend;
+ Elf32_Addr r_offset = p_rela[i].r_offset;
+ Elf32_Word r_type = ELF32_R_TYPE(p_rela[i].r_info);
+ cyg_uint32 sym_index = ELF32_R_SYM(p_rela[i].r_info);
+ Elf32_Sword r_addend = p_rela[i].r_addend;
#else
- r_offset = p_rel[i].r_offset;
- r_type = ELF32_R_TYPE( p_rel[i].r_info );
- sym_index = ELF32_R_SYM( p_rel[i].r_info );
- r_addend = 0;
+ Elf32_Addr r_offset = p_rel[i].r_offset;
+ Elf32_Word r_type = ELF32_R_TYPE(p_rel[i].r_info);
+ cyg_uint32 sym_index = ELF32_R_SYM(p_rel[i].r_info);
+ Elf32_Sword r_addend = 0;
#endif
- sym_value = (cyg_uint32)cyg_ldr_symbol_address( p, sym_index );
- if ( sym_value == 0 )
+ cyg_uint32 sym_value = (cyg_uint32)cyg_ldr_symbol_address(p, sym_index);
+ if (sym_value == 0)
{
#if CYGPKG_SERVICES_OBJLOADER_DEBUG_LEVEL > 0
- diag_printf( "Unknown symbol value: %s Index: %d\n",
+ diag_printf("Unknown symbol value: %s Index: %d\n",
p_strtab + p_symtab[sym_index].st_name,
- sym_index );
+ sym_index);
#endif
return -1;
}
// This is architecture dependent, and deals with whether we have
// '.rel' or '.rela' sections.
#if CYGPKG_SERVICES_OBJLOADER_DEBUG_LEVEL > 1
- diag_printf( "%04X %04X %08X ",
+ diag_printf("%04X %04X %08X ",
sym_index,
r_type,
- r_offset );
- if ( strlen ( p_strtab + p_symtab[sym_index].st_name ) > 0 )
- diag_printf( p_strtab + p_symtab[sym_index].st_name );
+ r_offset);
+ if (strlen(p_strtab + p_symtab[sym_index].st_name) > 0)
+ diag_printf(p_strtab + p_symtab[sym_index].st_name);
else
{
// If the symbol name is not available, then print
// the name of the section.
cyg_uint32 sec_ndx = p_symtab[sym_index].st_shndx;
- diag_printf( p_shstrtab + p->p_sechdr[sec_ndx].sh_name );
+ diag_printf(p_shstrtab + p->p_sechdr[sec_ndx].sh_name);
}
- diag_printf( "\n" );
+ diag_printf("\n");
#endif
- rc = cyg_ldr_relocate( r_type,
+ rc = cyg_ldr_relocate(r_type,
r_target_addr + r_offset,
- sym_value + r_addend );
- if ( rc != 0 )
+ sym_value + r_addend);
+ if (rc != 0)
{
#if CYGPKG_SERVICES_OBJLOADER_DEBUG_LEVEL > 0
- diag_printf( "Relocation error: Cannot find symbol: %s\n",
- p_strtab + p_symtab[sym_index].st_name );
+ diag_printf("Relocation error: Cannot find symbol: %s\n",
+ p_strtab + p_symtab[sym_index].st_name);
#endif
return -1;
}
}
// After the relocation is done, the relocation table can be dumped.
- cyg_ldr_delete_elf_section( p, r_shndx );
+ cyg_ldr_delete_elf_section(p, r_shndx);
return 0;
}
* =================================================================
* #####DESCRIPTIONBEGIN####
*
- * Author(s): atonizzo@lycos.com
+ * Author(s): Anthony Tonizzo (atonizzo@gmail.com)
* Contributors: nickg@ecoscentric.com
* Date: 2005-05-13
* Purpose:
#include <cyg/objloader/objelf.h>
#include <cyg/objloader/loader_fs.h>
-cyg_uint8 *cyg_ldr_last_error;
+char *cyg_ldr_last_error;
-void *cyg_ldr_malloc( size_t ) CYGBLD_ATTRIB_WEAK;
+void *cyg_ldr_malloc(size_t) CYGBLD_ATTRIB_WEAK;
void
-*cyg_ldr_malloc( size_t s )
+*cyg_ldr_malloc(size_t s)
{
- return malloc( s );
+ return malloc(s);
}
-void cyg_ldr_free( void * ) CYGBLD_ATTRIB_WEAK;
+void cyg_ldr_free(void *) CYGBLD_ATTRIB_WEAK;
void
-cyg_ldr_free( void *s )
+cyg_ldr_free(void *s)
{
- free( s );
+ free(s);
}
void
-cyg_ldr_delete_elf_section( PELF_OBJECT p, cyg_uint32 idx )
+cyg_ldr_delete_elf_section(PELF_OBJECT p, cyg_uint32 idx)
{
- cyg_ldr_free( p->sections[idx] );
+ cyg_ldr_free(p->sections[idx]);
p->sections[idx] = 0;
}
// the close() function to close files or sockets, and finally frees up
// the ELF object altogether.
static void
-cyg_ldr_free_elf_object( PELF_OBJECT p )
+cyg_ldr_free_elf_object(PELF_OBJECT p)
{
cyg_int32 i;
- for ( i = 0; i < p->p_elfhdr->e_shnum + 1; i++ )
- if ( p->sections[i] )
- cyg_ldr_delete_elf_section( p, i );
+ for (i = 0; i < p->p_elfhdr->e_shnum + 1; i++)
+ if (p->sections[i])
+ cyg_ldr_delete_elf_section(p, i);
- if ( p->sections != 0 )
- cyg_ldr_free( p->sections );
+ if (p->sections != 0)
+ cyg_ldr_free(p->sections);
- if ( p->p_sechdr != 0 )
- cyg_ldr_free( p->p_sechdr );
+ if (p->p_sechdr != 0)
+ cyg_ldr_free(p->p_sechdr);
- if ( p->p_elfhdr != 0 )
- cyg_ldr_free( p->p_elfhdr );
+ if (p->p_elfhdr != 0)
+ cyg_ldr_free(p->p_elfhdr);
- p->close( p );
- cyg_ldr_free( p );
+ p->close(p);
+ cyg_ldr_free(p);
}
static cyg_uint32
-cyg_ldr_find_common_size( PELF_OBJECT p )
+cyg_ldr_find_common_size(PELF_OBJECT p)
{
- cyg_int32 i, symtab_entries, common_size = 0;
+ cyg_int32 i, common_size = 0;
Elf32_Sym *p_symtab = (Elf32_Sym*)p->sections[p->hdrndx_symtab];
// Total number of entries in the symbol table.
- symtab_entries = p->p_sechdr[p->hdrndx_symtab].sh_size /
+ int symtab_entries = p->p_sechdr[p->hdrndx_symtab].sh_size /
p->p_sechdr[p->hdrndx_symtab].sh_entsize;
- for ( i = 1; i < symtab_entries; i++ )
- if ( p_symtab[i].st_shndx == SHN_COMMON )
+ for (i = 1; i < symtab_entries; i++)
+ if (p_symtab[i].st_shndx == SHN_COMMON)
{
// In the case of an SHN_COMMON symbol the st_value field holds
// alignment constraints.
cyg_uint32 boundary = p_symtab[i].st_value - 1;
// Calculate the next byte boundary.
- common_size = ( common_size + boundary ) & ~boundary;
+ common_size = (common_size + boundary) & ~boundary;
common_size += p_symtab[i].st_size;
}
#if CYGPKG_SERVICES_OBJLOADER_DEBUG_LEVEL > 0
- diag_printf( "common_size = %d\n", common_size );
+ diag_printf("common_size = %d\n", common_size);
#endif
return common_size;
}
// Allocates memory and loads the contents of a specific ELF section.
// Returns the address of the newly allocated memory, of 0 for any error.
-cyg_int32
-*cyg_ldr_load_elf_section( PELF_OBJECT p, cyg_uint32 idx )
+cyg_uint32
+*cyg_ldr_load_elf_section(PELF_OBJECT p, cyg_uint32 idx)
{
- cyg_uint32 *addr;
-
- addr = cyg_ldr_malloc( p->p_sechdr[idx].sh_size );
- CYG_ASSERT( addr != 0, "Cannot malloc() section" );
- if ( addr == 0 )
+ cyg_uint32 *addr = (cyg_uint32 *)cyg_ldr_malloc(p->p_sechdr[idx].sh_size);
+ CYG_ASSERT(addr != 0, "Cannot malloc() section");
+ if (addr == 0)
{
cyg_ldr_last_error = "ERROR IN MALLOC";
return (void*)0;
}
- p->seek( p, p->p_sechdr[idx].sh_offset );
- p->read( p, sizeof( char ), p->p_sechdr[idx].sh_size, addr );
+ p->seek(p, p->p_sechdr[idx].sh_offset);
+ p->read(p, sizeof(char), p->p_sechdr[idx].sh_size, addr);
return addr;
}
// Returns the starting address of a section. If the section is not already
// loaded in memory, area for it will be allocated and the section will be
// loaded.
-cyg_int32
-*cyg_ldr_section_address( PELF_OBJECT p, cyg_uint32 idx )
+cyg_uint32
+*cyg_ldr_section_address(PELF_OBJECT p, cyg_uint32 idx)
{
- if ( p->sections[idx] == 0 )
- p->sections[idx] = cyg_ldr_load_elf_section( p, idx );
+ if (p->sections[idx] == 0)
+ p->sections[idx] = cyg_ldr_load_elf_section(p, idx);
return p->sections[idx];
}
void
-*cyg_ldr_find_symbol( void* handle, cyg_uint8* sym_name )
+*cyg_ldr_find_symbol(void* handle, char* sym_name)
{
PELF_OBJECT p = (PELF_OBJECT)handle;
- cyg_uint8* tmp2;
- cyg_int32 i, symtab_entries;
- cyg_uint8 *p_strtab = (cyg_uint8*)p->sections[p->hdrndx_strtab];
+ int i;
+ char *p_strtab = (char*)p->sections[p->hdrndx_strtab];
Elf32_Sym *p_symtab = (Elf32_Sym*)p->sections[p->hdrndx_symtab];
-
- symtab_entries = p->p_sechdr[p->hdrndx_symtab].sh_size /
+
+ int symtab_entries = p->p_sechdr[p->hdrndx_symtab].sh_size /
p->p_sechdr[p->hdrndx_symtab].sh_entsize;
- for ( i = 0; i < symtab_entries; i++ )
+ for (i = 0; i < symtab_entries; i++)
{
- tmp2 = p_strtab + p_symtab[i].st_name;
- if ( !strcmp( tmp2, sym_name ) )
- return cyg_ldr_symbol_address( p, i );
+ char* tmp2 = p_strtab + p_symtab[i].st_name;
+ if (!strcmp(tmp2, sym_name))
+ return cyg_ldr_symbol_address(p, i);
}
// Symbol not found.
return 0;
}
-static cyg_uint8
-*cyg_ldr_sanity_check( PELF_OBJECT p )
+static char
+*cyg_ldr_sanity_check(PELF_OBJECT p)
{
- if ( ( p->p_elfhdr->e_ident[EI_MAG0] != ELFMAG0 ) ||
- ( p->p_elfhdr->e_ident[EI_MAG1] != ELFMAG1 ) ||
- ( p->p_elfhdr->e_ident[EI_MAG2] != ELFMAG2 ) ||
- ( p->p_elfhdr->e_ident[EI_MAG3] != ELFMAG3 ) ||
- ( p->p_elfhdr->e_ident[EI_CLASS] != ELFCLASS32 ) )
+ if ((p->p_elfhdr->e_ident[EI_MAG0] != ELFMAG0) ||
+ (p->p_elfhdr->e_ident[EI_MAG1] != ELFMAG1) ||
+ (p->p_elfhdr->e_ident[EI_MAG2] != ELFMAG2 ) ||
+ (p->p_elfhdr->e_ident[EI_MAG3] != ELFMAG3) ||
+ (p->p_elfhdr->e_ident[EI_CLASS] != ELFCLASS32))
return "INVALID ELF HEADER";
// We only work with relocatable files. No dynamic linking.
- if ( p->p_elfhdr->e_type != ET_REL )
+ if (p->p_elfhdr->e_type != ET_REL)
return "NOT RELOCATABLE";
// These #defines are sitting in the hal.
- if ( p->p_elfhdr->e_machine != ELF_ARCH_MACHINE_TYPE )
+ if (p->p_elfhdr->e_machine != ELF_ARCH_MACHINE_TYPE)
return "INVALID ARCHITECTURE";
- if ( p->p_elfhdr->e_ident[EI_DATA] != ELF_ARCH_ENDIANNESS )
+ if (p->p_elfhdr->e_ident[EI_DATA] != ELF_ARCH_ENDIANNESS)
return "INVALID ENDIAN";
return 0; }
// will be loaded on demand when needed during the relocation process and,
// when possible, dumped after use.
static cyg_int32
-cyg_ldr_load_sections( PELF_OBJECT p )
+cyg_ldr_load_sections(PELF_OBJECT p)
{
- cyg_uint8 *error_string;
+ char *error_string;
cyg_int32 idx;
// Load the ELF header.
- p->p_elfhdr = (Elf32_Ehdr*)cyg_ldr_malloc( sizeof( Elf32_Ehdr ) );
- CYG_ASSERT( p->p_elfhdr != 0, "Cannot malloc() p->p_elfhdr" );
- if ( p->p_elfhdr == 0 )
+ p->p_elfhdr = (Elf32_Ehdr*)cyg_ldr_malloc(sizeof(Elf32_Ehdr));
+ CYG_ASSERT(p->p_elfhdr != 0, "Cannot malloc() p->p_elfhdr");
+ if (p->p_elfhdr == 0)
return -1;
- p->seek( p, 0 );
- p->read( p, sizeof( char ), sizeof( Elf32_Ehdr ), p->p_elfhdr );
- error_string = cyg_ldr_sanity_check( p );
- if ( error_string != 0 )
+ p->seek(p, 0);
+ p->read(p, sizeof(char), sizeof(Elf32_Ehdr), p->p_elfhdr );
+ error_string = cyg_ldr_sanity_check(p);
+ if (error_string != 0)
{
cyg_ldr_last_error = "ERROR IN ELF HEADER";
return -1;
// library. This is not strictly optimal, since some sections do not
// need to be loaded all the time. Allocate an extra pointer for the
// COMMON area.
- p->sections = cyg_ldr_malloc( ( p->p_elfhdr->e_shnum + 1 ) *
- sizeof( cyg_uint32 ) );
- CYG_ASSERT( p->sections != 0, "Cannot malloc() p->sections" );
- if ( p->sections == 0 )
+ p->sections = cyg_ldr_malloc((p->p_elfhdr->e_shnum + 1) *
+ sizeof(cyg_uint32));
+ CYG_ASSERT(p->sections != 0, "Cannot malloc() p->sections");
+ if (p->sections == 0)
{
cyg_ldr_last_error = "ERROR IN MALLOC";
return -1;
}
- memset( p->sections, 0, ( p->p_elfhdr->e_shnum + 1 ) *
- sizeof( cyg_uint32 ) );
+ memset(p->sections, 0, (p->p_elfhdr->e_shnum + 1) *
+ sizeof(cyg_uint32));
// Now that the header is loaded, load the sections header.
- p->p_sechdr = (Elf32_Shdr*)cyg_ldr_malloc(
- p->p_elfhdr->e_shnum * p->p_elfhdr->e_shentsize );
- CYG_ASSERT( p->p_sechdr != 0, "Cannot malloc() p->p_sechdr" );
- if ( p->p_sechdr == 0 )
+ p->p_sechdr = (Elf32_Shdr*)cyg_ldr_malloc(
+ p->p_elfhdr->e_shnum * p->p_elfhdr->e_shentsize);
+ CYG_ASSERT(p->p_sechdr != 0, "Cannot malloc() p->p_sechdr");
+ if (p->p_sechdr == 0)
{
cyg_ldr_last_error = "ERROR IN MALLOC";
return -1;
}
- p->seek( p, p->p_elfhdr->e_shoff );
- p->read( p, p->p_elfhdr->e_shentsize, p->p_elfhdr->e_shnum, p->p_sechdr );
+ p->seek(p, p->p_elfhdr->e_shoff);
+ p->read(p, p->p_elfhdr->e_shentsize, p->p_elfhdr->e_shnum, p->p_sechdr);
// Load the section header string table. This is a byte oriented table,
// so alignment is not an issue.
idx = p->p_elfhdr->e_shstrndx;
- p->sections[idx] = cyg_ldr_load_elf_section( p, idx );
+ p->sections[idx] = cyg_ldr_load_elf_section(p, idx);
return 0;
}
PELF_OBJECT
-cyg_ldr_open_library( CYG_ADDRWORD ptr, cyg_int32 mode )
+cyg_ldr_open_library(CYG_ADDRWORD ptr, cyg_int32 mode)
{
- Elf32_Sym *p_symtab;
- cyg_uint8 *p_shstrtab;
- PELF_OBJECT e_obj;
int (*fn)(void);
- cyg_int32 i, rc, symtab_entries;
- cyg_uint32 common_size;
+ int i;
// In the future there might be a switch() (against 'mode') that calls an
// open function other than cyg_ldr_open_library_fs(). These function
// fetch and open a library using ftp, http or libraries that are already
// in ROM.
- e_obj = cyg_ldr_open_library_fs( (cyg_uint8*)ptr );
- if ( e_obj == 0 )
+ PELF_OBJECT e_obj = cyg_ldr_open_library_fs((char*)ptr);
+ if (e_obj == 0)
return 0;
- rc = cyg_ldr_load_sections( e_obj );
- if ( rc != 0 )
+ int rc = cyg_ldr_load_sections(e_obj);
+ if (rc != 0)
{
- cyg_ldr_free_elf_object( e_obj );
+ cyg_ldr_free_elf_object(e_obj);
return 0;
}
// Find the section index for the .shstrtab section. The names of the
// sections are held here, and are the only way to identify them.
- p_shstrtab = (cyg_uint8*)cyg_ldr_section_address( e_obj,
- e_obj->p_elfhdr->e_shstrndx );
- if ( p_shstrtab == 0 )
+ char *p_shstrtab = (char*)cyg_ldr_section_address(e_obj,
+ e_obj->p_elfhdr->e_shstrndx);
+ if (p_shstrtab == 0)
{
- cyg_ldr_free_elf_object( e_obj );
+ cyg_ldr_free_elf_object(e_obj);
return 0;
}
// .symtab section and .strtab. We have to go through the section names
// to find where they are.
- for ( i = 1; i < e_obj->p_elfhdr->e_shnum; i++ )
+ for (i = 1; i < e_obj->p_elfhdr->e_shnum; i++)
{
// Now look for the index of .symtab. These are the symbols needed for
// the symbol retrieval as well as relocation.
- if ( !strcmp( p_shstrtab + e_obj->p_sechdr[i].sh_name,
- ELF_STRING_symtab ) )
+ if (!strcmp(p_shstrtab + e_obj->p_sechdr[i].sh_name, ELF_STRING_symtab))
{
e_obj->hdrndx_symtab = i;
- e_obj->sections[i] = cyg_ldr_load_elf_section( e_obj, i );
- if ( e_obj->sections[i] == 0 )
+ e_obj->sections[i] = cyg_ldr_load_elf_section(e_obj, i);
+ if (e_obj->sections[i] == 0)
{
- cyg_ldr_free_elf_object( e_obj );
+ cyg_ldr_free_elf_object(e_obj);
return 0;
}
}
// Load the table with the names of all the symbols. We need this
// to compare the name of external references symbols against the
// names in the in the CYG_HAL_TABLE provided by the user.
- if ( !strcmp( p_shstrtab + e_obj->p_sechdr[i].sh_name,
- ELF_STRING_strtab ) )
+ if (!strcmp(p_shstrtab + e_obj->p_sechdr[i].sh_name, ELF_STRING_strtab))
{
e_obj->hdrndx_strtab = i;
- e_obj->sections[i] = cyg_ldr_load_elf_section( e_obj, i );
- if ( e_obj->sections[i] == 0 )
+ e_obj->sections[i] = cyg_ldr_load_elf_section(e_obj, i);
+ if (e_obj->sections[i] == 0)
{
- cyg_ldr_free_elf_object( e_obj );
+ cyg_ldr_free_elf_object(e_obj);
return 0;
}
}
}
- CYG_ASSERT( e_obj->hdrndx_symtab != 0, "No symtab index found" );
- CYG_ASSERT( e_obj->hdrndx_strtab != 0, "No strtab index found" );
+ CYG_ASSERT(e_obj->hdrndx_symtab != 0, "No symtab index found");
+ CYG_ASSERT(e_obj->hdrndx_strtab != 0, "No strtab index found");
// Now look for symbols in the COMMON area. The COMMON symbols are a
// special case, because the area they reside in must be sized up
// the sections header and can be read out of the library itself.
// Extra room in the 'sections' array has already been allocated to hold
// the pointer to the commons area.
- common_size = cyg_ldr_find_common_size( e_obj );
- if ( common_size != 0 )
+ cyg_uint32 common_size = cyg_ldr_find_common_size(e_obj);
+ if (common_size != 0)
{
cyg_uint32 com_shndx = e_obj->p_elfhdr->e_shnum;
cyg_int32 com_offset = 0;
- e_obj->sections[com_shndx] = (cyg_uint32*)cyg_ldr_malloc( common_size );
- CYG_ASSERT( e_obj->sections[com_shndx] != 0,
- "Cannot malloc() the COMMONS" );
+ e_obj->sections[com_shndx] = (cyg_uint32*)cyg_ldr_malloc(common_size);
+ CYG_ASSERT(e_obj->sections[com_shndx] != 0,
+ "Cannot malloc() the COMMONS");
- if ( e_obj->sections[com_shndx] == 0 )
+ if (e_obj->sections[com_shndx] == 0)
{
- cyg_ldr_free_elf_object( e_obj );
+ cyg_ldr_free_elf_object(e_obj);
return 0;
}
// Now find all the symbols in the SHN_COMMON area and make
// them point to the newly allocated COM area.
- symtab_entries = e_obj->p_sechdr[e_obj->hdrndx_symtab].sh_size /
+ int symtab_entries = e_obj->p_sechdr[e_obj->hdrndx_symtab].sh_size /
e_obj->p_sechdr[e_obj->hdrndx_symtab].sh_entsize;
- p_symtab = (Elf32_Sym*)e_obj->sections[e_obj->hdrndx_symtab];
+ Elf32_Sym *p_symtab = (Elf32_Sym*)e_obj->sections[e_obj->hdrndx_symtab];
#if CYGPKG_SERVICES_OBJLOADER_DEBUG_LEVEL > 1
- diag_printf( "Num Value Size Ndx Name\n" );
+ diag_printf("Num Value Size Ndx Name\n");
#endif
- for ( i = 1; i < symtab_entries; i++ )
+ for (i = 1; i < symtab_entries; i++)
{
#if CYGPKG_SERVICES_OBJLOADER_DEBUG_LEVEL > 1
- cyg_uint8 *p_strtab = (cyg_uint8*)cyg_ldr_section_address( e_obj,
- e_obj->hdrndx_strtab );
+ cyg_uint8 *p_strtab = (cyg_uint8*)cyg_ldr_section_address(e_obj,
+ e_obj->hdrndx_strtab);
#endif
- if ( p_symtab[i].st_shndx == SHN_COMMON )
+ if (p_symtab[i].st_shndx == SHN_COMMON)
{
cyg_uint32 boundary = p_symtab[i].st_value - 1;
// Calculate the next byte boundary.
- com_offset = ( com_offset + boundary ) & ~boundary;
+ com_offset = (com_offset + boundary) & ~boundary;
p_symtab[i].st_shndx = com_shndx;
p_symtab[i].st_value = com_offset;
com_offset += p_symtab[i].st_size;
}
#if CYGPKG_SERVICES_OBJLOADER_DEBUG_LEVEL > 1
- diag_printf( "%03d %08X %04X %03d %s\n",
+ diag_printf("%03d %08X %04X %03d %s\n",
i,
p_symtab[i].st_value,
p_symtab[i].st_size,
p_symtab[i].st_shndx,
- p_strtab + p_symtab[i].st_name );
+ p_strtab + p_symtab[i].st_name);
#endif
}
}
#if CYGPKG_SERVICES_OBJLOADER_DEBUG_LEVEL > 0
- cyg_ldr_print_section_data( e_obj );
+ cyg_ldr_print_section_data(e_obj);
#if CYGPKG_SERVICES_OBJLOADER_DEBUG_LEVEL > 1
- cyg_ldr_print_symbol_names( e_obj );
+ cyg_ldr_print_symbol_names(e_obj);
#endif
#endif
- for ( i = 1; i < e_obj->p_elfhdr->e_shnum; i++ )
+ for (i = 1; i < e_obj->p_elfhdr->e_shnum; i++)
{
// Find all the '.rel' or '.rela' sections and relocate them.
- if ( ( e_obj->p_sechdr[i].sh_type == SHT_REL ) ||
- ( e_obj->p_sechdr[i].sh_type == SHT_RELA ) )
+ if ((e_obj->p_sechdr[i].sh_type == SHT_REL) ||
+ (e_obj->p_sechdr[i].sh_type == SHT_RELA))
{
// Load and relocate the section.
- rc = cyg_ldr_relocate_section( e_obj, i );
- if ( rc < 0 )
+ rc = cyg_ldr_relocate_section(e_obj, i);
+ if (rc < 0)
{
#if CYGPKG_SERVICES_OBJLOADER_DEBUG_LEVEL > 0
- ELFDEBUG( "Relocation unsuccessful\n" );
+ ELFDEBUG("Relocation unsuccessful\n");
#endif
- cyg_ldr_free_elf_object( e_obj );
+ cyg_ldr_free_elf_object(e_obj);
return 0;
}
}
cyg_ldr_flush_cache();
// Run the library initialization code.
- fn = cyg_ldr_find_symbol( e_obj, "library_open" );
- if ( fn != 0 )
+ fn = cyg_ldr_find_symbol(e_obj, "library_open");
+ if (fn != 0)
fn();
return ((void*)e_obj);
}
-cyg_uint8
-*cyg_ldr_error( void )
+char
+*cyg_ldr_error(void)
{
- cyg_uint8* p = cyg_ldr_last_error;
+ char* p = cyg_ldr_last_error;
cyg_ldr_last_error = NULL;
return p;
}
-void cyg_ldr_close_library( void* handle )
+void cyg_ldr_close_library(void* handle)
{
void (*fn)(void);
PELF_OBJECT p = (PELF_OBJECT)handle;
- fn = cyg_ldr_find_symbol( p, "library_close" );
- if ( fn != 0 )
+ fn = cyg_ldr_find_symbol(p, "library_close");
+ if (fn != 0)
fn();
- cyg_ldr_free_elf_object( p );
+ cyg_ldr_free_elf_object(p);
p = 0;
}
* =================================================================
* #####DESCRIPTIONBEGIN####
*
- * Author(s): atonizzo@lycos.com, andrew.lunn@ascom.ch
+ * Author(s): Anthony Tonizzo (atonizzo@gmail.com), andrew.lunn@ascom.ch
* Date: 2005-07-07
* Purpose:
* Description:
#if defined(CYGPKG_HAL_I386) || defined(CYGPKG_HAL_SYNTH_I386)
void
-cyg_ldr_flush_cache( void )
+cyg_ldr_flush_cache(void)
{
HAL_DCACHE_SYNC();
HAL_ICACHE_SYNC();
// mem Address in memory to modify (relocate).
// sym_value
cyg_int32
-cyg_ldr_relocate( cyg_int32 sym_type, cyg_uint32 mem, cyg_int32 sym_value )
+cyg_ldr_relocate(cyg_int32 sym_type, cyg_uint32 mem, cyg_int32 sym_value)
{
cyg_int32 i;
// PPC uses rela, so we have to add the addend.
- switch( sym_type )
+ switch(sym_type)
{
case R_386_32:
- HAL_READ_UINT32( mem , i );
- HAL_WRITE_UINT32( mem, i + sym_value );
+ HAL_READ_UINT32(mem , i);
+ HAL_WRITE_UINT32(mem, i + sym_value );
return 0;
case R_386_PC32:
- HAL_READ_UINT32( mem , i );
- HAL_WRITE_UINT32( mem, i + sym_value - mem );
+ HAL_READ_UINT32(mem , i);
+ HAL_WRITE_UINT32(mem, i + sym_value - mem);
return 0;
default:
- ELFDEBUG( "FIXME: Unknown relocation value!!!\n" );
+ ELFDEBUG("FIXME: Unknown relocation value!!!\n");
return -1;
}
}
* =================================================================
* #####DESCRIPTIONBEGIN####
*
- * Author(s): atonizzo@lycos.com
+ * Author(s): Anthony Tonizzo (atonizzo@gmail.com)
* Date: 2005-05-13
* Purpose:
* Description:
#ifdef CYGPKG_HAL_POWERPC
void
-cyg_ldr_flush_cache( void )
+cyg_ldr_flush_cache(void)
{
HAL_DCACHE_SYNC();
HAL_ICACHE_SYNC();
// mem Address in memory to modify (relocate).
// sym_value
cyg_int32
-cyg_ldr_relocate( cyg_int32 sym_type, cyg_uint32 mem, cyg_int32 sym_value )
+cyg_ldr_relocate(cyg_int32 sym_type, cyg_uint32 mem, cyg_int32 sym_value)
{
cyg_int32 rel_offset, i;
// PPC uses rela, so we have to add the addend.
- switch( sym_type )
+ switch(sym_type)
{
case R_PPC_ADDR16_HA:
- HAL_WRITE_UINT16( mem, _ha_( sym_value ) );
+ HAL_WRITE_UINT16(mem, _ha_(sym_value));
return 0;
case R_PPC_ADDR16_HI:
- HAL_WRITE_UINT16( mem, _hi_( sym_value ) );
+ HAL_WRITE_UINT16(mem, _hi_(sym_value));
return 0;
case R_PPC_ADDR16_LO:
- HAL_WRITE_UINT16( mem, _lo_( sym_value ) );
+ HAL_WRITE_UINT16(mem, _lo_(sym_value));
return 0;
case R_PPC_REL24:
// Now it is time to seek the destination address of the call.
// We need to do something in case the user jumps more than 16MB.
- rel_offset = ( sym_value - mem ) & 0x03FFFFFC;
- HAL_READ_UINT32( mem, i );
+ rel_offset = (sym_value - mem) & 0x03FFFFFC;
+ HAL_READ_UINT32(mem, i);
i &= 0xFC000003;
- HAL_WRITE_UINT32( mem, rel_offset | i );
+ HAL_WRITE_UINT32(mem, rel_offset | i);
return 0;
case R_PPC_REL32:
- HAL_WRITE_UINT32( mem, ( sym_value - mem ) );
+ HAL_WRITE_UINT32(mem, (sym_value - mem));
return 0;
case R_PPC_ADDR32:
- HAL_WRITE_UINT32( mem, sym_value );
+ HAL_WRITE_UINT32(mem, sym_value);
return 0;
default:
- ELFDEBUG( "FIXME: Unknown relocation value!!!\n" );
+ ELFDEBUG("FIXME: Unknown relocation value!!!\n");
return -1;
}
}
* =================================================================
* #####DESCRIPTIONBEGIN####
*
- * Author(s): atonizzo@lycos.com
+ * Author(s): Anthony Tonizzo (atonizzo@gmail.com)
* Date: 2005-05-13
* Purpose:
* Description:
extern int weak_fn_called;
-void weak_function( void ) CYGBLD_ATTRIB_WEAK;
-void weak_function( void )
+void weak_function(void) CYGBLD_ATTRIB_WEAK;
+void weak_function(void)
{
// Store the data value passed in for this thread.
- diag_printf( "INFO:< This is the library weak function>" );
- CYG_TEST_FAIL ( "Libraries weak function called when apps should be called" );
+ diag_printf("INFO:< This is the library weak function>");
+ CYG_TEST_FAIL ("Libraries weak function called when apps should be called");
}
-void library_open( void )
+void library_open(void)
{
// Initialize the count for thread a.
thread_a_count = 0;
// Initialize the semaphore with a count of zero,
// prior to creating the threads.
- cyg_semaphore_init( &sem_signal_thread, 0 );
- CYG_TEST_INFO( "Library initialized" );
+ cyg_semaphore_init(&sem_signal_thread, 0);
+ CYG_TEST_INFO("Library initialized");
}
-void library_close( void )
+void library_close(void)
{
- CYG_TEST_INFO( "Library closed" );
+ CYG_TEST_INFO("Library closed");
}
-void print_message( void )
+void print_message(void)
{
- diag_printf( "INFO:<Printing a silly message...>\n" );
+ diag_printf("INFO:<Printing a silly message...>\n");
}
// Thread A - signals thread B via semaphore.
-void thread_a( cyg_addrword_t data )
+void thread_a(cyg_addrword_t data)
{
// Store the data value passed in for this thread.
int msg = (int)data;
weak_function ();
- while( thread_a_count < 5 )
+ while(thread_a_count < 5)
{
// Increment the thread a count.
thread_a_count++;
// Send out a message to the diagnostic port.
- diag_printf( "INFO:<Thread A, count: %d message: %d>\n", thread_a_count, msg );
+ diag_printf("INFO:<Thread A, count: %d message: %d>\n", thread_a_count, msg);
// Delay for 1 second.
- cyg_thread_delay( 100 );
+ cyg_thread_delay(100);
// Signal thread B using the semaphore.
- cyg_semaphore_post( &sem_signal_thread );
+ cyg_semaphore_post(&sem_signal_thread);
}
- CYG_TEST_CHECK( weak_fn_called == 2 , "Application week function not called" );
- CYG_TEST_FINISH( "Object loader test finished" );
+ CYG_TEST_CHECK(weak_fn_called == 2 , "Application week function not called");
+ CYG_TEST_FINISH("Object loader test finished");
}
// Thread B - waits for semaphore signal from thread A.
-void thread_b( cyg_addrword_t data )
+void thread_b(cyg_addrword_t data)
{
// Store the data value passed in for this thread.
int msg = (int)data;
- while( 1 )
+ while(1)
{
// Signal thread B using the semaphore.
- cyg_semaphore_wait( &sem_signal_thread );
+ cyg_semaphore_wait(&sem_signal_thread);
// Send out a message to the diagnostic port.
- diag_printf( "INFO:< Thread B, message: %d>\n", msg );
+ diag_printf("INFO:< Thread B, message: %d>\n", msg);
}
}
* =================================================================
* #####DESCRIPTIONBEGIN####
*
- * Author(s): atonizzo@lycos.com
+ * Author(s): Anthony Tonizzo (atonizzo@gmail.com)
* Date: 2005-05-13
* Purpose:
* Description:
//==========================================================================
-MTAB_ENTRY( romfs_mte1,
+MTAB_ENTRY(romfs_mte1,
"/",
"romfs",
"",
- (CYG_ADDRWORD) &filedata[0] );
+ (CYG_ADDRWORD) &filedata[0]);
//==========================================================================
cyg_handle_t thread_a_hdl;
cyg_handle_t thread_b_hdl;
-#define SHOW_RESULT( _fn, _res ) \
+#define SHOW_RESULT(_fn, _res) \
diag_printf("<FAIL>: " #_fn "() returned %d %s\n", _res, _res<0?strerror(errno):"");
int weak_fn_called = 0;
-void weak_function( void )
+void weak_function(void)
{
- CYG_TEST_PASS( "Applications weak function called" );
+ CYG_TEST_PASS("Applications weak function called");
weak_fn_called++;
}
-void (*thread_a)( cyg_addrword_t );
-void (*thread_b)( cyg_addrword_t );
+void (*thread_a)(cyg_addrword_t);
+void (*thread_b)(cyg_addrword_t);
// This is the main starting point for our example application.
-void cyg_user_start( void )
+void cyg_user_start(void)
{
int err;
void* lib_handle;
- void (*fn)( void );
+ void (*fn)(void);
CYG_TEST_INIT();
- CYG_TEST_INFO( "Object loader module test started" );
+ CYG_TEST_INFO("Object loader module test started");
- err = chdir( "/" );
+ err = chdir("/");
- if( err < 0 )
- SHOW_RESULT( chdir, err );
+ if(err < 0)
+ SHOW_RESULT(chdir, err);
- lib_handle = cyg_ldr_open_library( (CYG_ADDRWORD)"/hello.o", 0 );
- CYG_TEST_CHECK( lib_handle , "Unable to load object file to load" );
+ lib_handle = cyg_ldr_open_library((CYG_ADDRWORD)"/hello.o", 0);
+ CYG_TEST_CHECK(lib_handle , "Unable to load object file to load");
- fn = cyg_ldr_find_symbol( lib_handle, "print_message" );
- CYG_TEST_CHECK( fn , "Unable to find print_message function" );
+ fn = cyg_ldr_find_symbol(lib_handle, "print_message");
+ CYG_TEST_CHECK(fn , "Unable to find print_message function");
fn();
- fn = cyg_ldr_find_symbol( lib_handle, "weak_function" );
- CYG_TEST_CHECK( fn , "Unable to find weak_function" );
+ fn = cyg_ldr_find_symbol(lib_handle, "weak_function");
+ CYG_TEST_CHECK(fn , "Unable to find weak_function");
fn();
- fn = cyg_ldr_find_symbol ( lib_handle, "unresolvable_symbol" );
- CYG_TEST_CHECK( !fn , "Found none existing symbol!" );
+ fn = cyg_ldr_find_symbol (lib_handle, "unresolvable_symbol");
+ CYG_TEST_CHECK(!fn , "Found none existing symbol!");
- thread_a = cyg_ldr_find_symbol( lib_handle, "thread_a" );
- thread_b = cyg_ldr_find_symbol( lib_handle, "thread_b" );
- CYG_TEST_CHECK( thread_a && thread_b , "Unable to find thread functions" );
+ thread_a = cyg_ldr_find_symbol(lib_handle, "thread_a");
+ thread_b = cyg_ldr_find_symbol(lib_handle, "thread_b");
+ CYG_TEST_CHECK(thread_a && thread_b , "Unable to find thread functions");
// Create our two threads.
- cyg_thread_create( THREAD_PRIORITY,
+ cyg_thread_create(THREAD_PRIORITY,
thread_a,
(cyg_addrword_t) 75,
"Thread A",
(void *)thread_a_stack,
THREAD_STACK_SIZE,
&thread_a_hdl,
- &thread_a_obj );
+ &thread_a_obj);
- cyg_thread_create( THREAD_PRIORITY + 1,
+ cyg_thread_create(THREAD_PRIORITY + 1,
thread_b,
(cyg_addrword_t) 68,
"Thread B",
(void *)thread_b_stack,
THREAD_STACK_SIZE,
&thread_b_hdl,
- &thread_b_obj );
+ &thread_b_obj);
// Resume the threads so they start when the scheduler begins.
- cyg_thread_resume( thread_a_hdl );
- cyg_thread_resume( thread_b_hdl );
+ cyg_thread_resume(thread_a_hdl);
+ cyg_thread_resume(thread_b_hdl);
cyg_scheduler_start();
}
CYG_LDR_TABLE_INFRA_DIAG()
// Test case infrastructure function
-CYG_LDR_TABLE_ENTRY( cyg_test_output_entry, "cyg_test_output", cyg_test_output );
-CYG_LDR_TABLE_ENTRY( cyg_test_exit_entry, "cyg_test_exit", cyg_test_exit );
+CYG_LDR_TABLE_ENTRY(cyg_test_output_entry, "cyg_test_output", cyg_test_output);
+CYG_LDR_TABLE_ENTRY(cyg_test_exit_entry, "cyg_test_exit", cyg_test_exit);
// Test function
-CYG_LDR_TABLE_ENTRY( weak_function_entry, "weak_function", weak_function );
+CYG_LDR_TABLE_ENTRY(weak_function_entry, "weak_function", weak_function);
// Test Variable
-CYG_LDR_TABLE_ENTRY( weak_fn_called_entry, "weak_fn_called", &weak_fn_called );
+CYG_LDR_TABLE_ENTRY(weak_fn_called_entry, "weak_fn_called", &weak_fn_called);
+2007-12-14 Oyvind Harboe <oyvind.harboe@zylin.com>
+2007-12-21 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * include/profile.h: Declare profile_off.
+ * src/profile.c: Added support for invoking profile_on() multiple
+ times. It now stops profiling and sets up a fresh profiling range
+ on every invocation using new profile_off() function.
+ * doc/profile.sgml: Document it.
+
2005-05-13 Peter Korsgaard <jacmet@sunsite.dk>
* doc/profile.sgml: Fixed typo in HAL support section.
</varlistentry>
</variablelist>
<para>
+<function>profile_on</function> can be invoked multiple times, and
+on subsequent invocations, it will delete profiling data
+and allocate a fresh profiling range.
+ </para>
+ <para>
+Profiling can be turned off using the function
+<function>profile_off</function>:
+<programlisting>
+void profile_off(void);
+</programlisting>
+This will also reset any existing profile data.
+ </para>
+ <para>
If the eCos configuration includes a TCP/IP stack and if a tftp daemon
will be used to <link linkend="gprof-extract">extract</link> the data
from the target then the call to <function>profile_on</function>
__externC void profile_on(void *start_addr, void *end_addr,
int bucket_size, int sample_resolution);
+// Disable and reset profiling
+__externC void profile_off(void);
+
// Callback used by timer routine
__externC void __profile_hit(CYG_ADDRWORD pc);
};
#endif
+// ----------------------------------------------------------------------------
+// stop profiling
+void
+profile_off(void)
+{
+ // suspend currently running profiling
+ profile_enabled = 0;
+ // Clear all pre-existing profile data
+ profile_reset();
+ if (profile_hist_data) {
+ free(profile_hist_data);
+ profile_hist_data = NULL;
+ }
+#ifdef CYGPKG_PROFILE_CALLGRAPH
+ if (profile_arc_hashtable) {
+ free(profile_arc_hashtable);
+ profile_arc_hashtable=NULL;
+ }
+ if (profile_arc_records) {
+ free(profile_arc_records);
+ profile_arc_records=NULL;
+ }
+#endif
+}
+
+
// ----------------------------------------------------------------------------
// profile_on() has to be called by application code to start profiling.
// Application code will determine the start and end addresses, usually
// but requires more memory. The resolution is used to initialize the
// profiling timer: more frequent interrupts means more accurate results
// but increases the risk of an overflow.
+//
+// profile_on() can be invoked multiple times. If invoked a second time
+// it will stop the current profiling run and create a new profiling
+// range.
+
+
void
profile_on(void *_start, void *_end, int _bucket_size, int resolution)
cyg_uint32 version = GMON_VERSION;
CYG_ADDRWORD text_size = (CYG_ADDRWORD)_end - (CYG_ADDRWORD)_start;
+ if (profile_enabled)
+ {
+ // invoking profile_on a second time
+ profile_off();
+ }
+
+
// Initialize statics. This also ensures that they won't be
// garbage collected by the linker so a gdb script can safely
// reference them.
#ifdef CYGPKG_PROFILE_TFTP
// Create a TFTP server to provide the data
+ // invoking this a second time is harmless
(void) tftpd_start(CYGNUM_PROFILE_TFTP_PORT, &profile_tftp_fileops);
#endif
}
+2008-04-08 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * current.ect: Add libc_string which memalloc needs.
+
2000-07-24 Jonathan Larmour <jlarmour@redhat.co.uk>
* current.ect: Fix up after isoinfra and memalloc additions
package CYGPKG_KERNEL current ;
package CYGPKG_ERROR current ;
package CYGPKG_MEMALLOC current ;
+ package CYGPKG_LIBC_STRING current ;
package CYGPKG_ISOINFRA current ;
};
cdl_option CYGBLD_ISO_STRERROR_HEADER {
inferred_value 1 <cyg/error/strerror.h>
};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+2008-04-08 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * current.cdl: Add LIBC_STRING which MEMALLOC now needs.
+
2004-05-04 Jani Monoses <jani@iv.ro>
* current.ect: Create new configuration for lwIP/ethernet
package CYGPKG_INFRA current ;
package CYGPKG_KERNEL current ;
package CYGPKG_MEMALLOC current ;
+ package CYGPKG_LIBC_STRING current ;
package CYGPKG_ERROR current ;
package CYGPKG_ISOINFRA current ;
package CYGPKG_NET_LWIP current ;
inferred_value 1 <cyg/error/strerror.h>
};
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+2008-04-08 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * current.cdl: Add LIBC_STRING which MEMALLOC now needs.
+
+2006-03-22 Uwe Kindler <uwe_kindler@web.de>
+
+ * current.ect: Fixed configuration options to match new names of
+ configuration options in lwip_net.cdl
+
2004-05-04 Jani Monoses <jani@iv.ro>
* current.ect: Create new configuration for lwIP/PPP
inferred_value 1 <cyg/error/strerror.h>
};
-cdl_option CYGPKG_LWIP_SERV_ADDR {
+cdl_option CYGDAT_LWIP_SERV_ADDR {
user_value 192,168,0,3
};
-cdl_option CYGPKG_LWIP_MY_ADDR {
+cdl_option CYGDAT_LWIP_MY_ADDR {
user_value 192,168,0,4
};
user_value 1
}
-cdl_option CYGPKG_LWIP_PPP_DEV {
+cdl_option CYGDAT_LWIP_PPP_DEV {
user_value "\"/dev/ser1\""
};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
dnl Now we know what the user is after.
if test "${GCC}" = "yes" ; then
ecos_CFLAGS="${ecos_CFLAGS} -pipe -Wall -Wpointer-arith -Wbad-function-cast -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes -Wnested-externs"
- ecos_CXXFLAGS="${ecos_CXXFLAGS} -pipe -Wall -Wpointer-arith -Wbad-function-cast -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes -Wnested-externs -Woverloaded-virtual"
+ ecos_CXXFLAGS="${ecos_CXXFLAGS} -pipe -Wall -Wpointer-arith -Wcast-qual -Woverloaded-virtual"
elif test "${MSVC}" = "yes" ; then
ecos_CFLAGS="${ecos_CFLAGS} -nologo -W3"
ecos_CXXFLAGS="${ecos_CXXFLAGS} -nologo -W3 -GR -GX"
fi
fi
- cd $ac_popdir
+ cd "$ac_popdir"
done
fi
fi
fi
-for ac_declaration in \
- ''\
- '#include <stdlib.h>' \
- 'extern "C" void std::exit (int) throw (); using std::exit;' \
- 'extern "C" void std::exit (int); using std::exit;' \
- 'extern "C" void exit (int) throw ();' \
- 'extern "C" void exit (int);' \
- 'void exit (int);'
-do
- cat > conftest.$ac_ext <<EOF
-#line 1231 "configure"
-#include "confdefs.h"
-#include <stdlib.h>
-$ac_declaration
-int main() {
-exit (42);
-; return 0; }
-EOF
-if { (eval echo configure:1239: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
- :
-else
- echo "configure: failed program was:" >&5
- cat conftest.$ac_ext >&5
- rm -rf conftest*
- continue
-fi
-rm -f conftest*
- cat > conftest.$ac_ext <<EOF
-#line 1249 "configure"
-#include "confdefs.h"
-$ac_declaration
-int main() {
-exit (42);
-; return 0; }
-EOF
-if { (eval echo configure:1256: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
- rm -rf conftest*
- break
-else
- echo "configure: failed program was:" >&5
- cat conftest.$ac_ext >&5
-fi
-rm -f conftest*
-done
-if test -n "$ac_declaration"; then
- echo '#ifdef __cplusplus' >>confdefs.h
- echo $ac_declaration >>confdefs.h
- echo '#endif' >>confdefs.h
-fi
-
-
# Extract the first word of "ranlib", so it can be a program name with args.
set dummy ranlib; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1275: checking for $ac_word" >&5
+echo "configure:1224: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
fi
echo $ac_n "checking for object suffix""... $ac_c" 1>&6
-echo "configure:1303: checking for object suffix" >&5
+echo "configure:1252: checking for object suffix" >&5
if eval "test \"`echo '$''{'ac_cv_objext'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
rm -f conftest*
echo 'int i = 1;' > conftest.$ac_ext
-if { (eval echo configure:1309: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:1258: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
for ac_file in conftest.*; do
case $ac_file in
*.c) ;;
ac_objext=$ac_cv_objext
echo $ac_n "checking for Cygwin environment""... $ac_c" 1>&6
-echo "configure:1327: checking for Cygwin environment" >&5
+echo "configure:1276: checking for Cygwin environment" >&5
if eval "test \"`echo '$''{'ac_cv_cygwin'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 1332 "configure"
+#line 1281 "configure"
#include "confdefs.h"
int main() {
return __CYGWIN__;
; return 0; }
EOF
-if { (eval echo configure:1343: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:1292: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest*
ac_cv_cygwin=yes
else
CYGWIN=
test "$ac_cv_cygwin" = yes && CYGWIN=yes
echo $ac_n "checking for mingw32 environment""... $ac_c" 1>&6
-echo "configure:1360: checking for mingw32 environment" >&5
+echo "configure:1309: checking for mingw32 environment" >&5
if eval "test \"`echo '$''{'ac_cv_mingw32'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 1365 "configure"
+#line 1314 "configure"
#include "confdefs.h"
int main() {
return __MINGW32__;
; return 0; }
EOF
-if { (eval echo configure:1372: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:1321: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest*
ac_cv_mingw32=yes
else
echo $ac_n "checking for executable suffix""... $ac_c" 1>&6
-echo "configure:1391: checking for executable suffix" >&5
+echo "configure:1340: checking for executable suffix" >&5
if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
rm -f conftest*
echo 'int main () { return 0; }' > conftest.$ac_ext
ac_cv_exeext=
- if { (eval echo configure:1401: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
+ if { (eval echo configure:1350: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
for file in conftest.*; do
case $file in
- *.c | *.o | *.obj) ;;
+ *.$ac_ext | *.c | *.o | *.obj) ;;
*) ac_cv_exeext=`echo $file | sed -e s/conftest//` ;;
esac
done
echo $ac_n "checking "for Visual C++"""... $ac_c" 1>&6
-echo "configure:1439: checking "for Visual C++"" >&5
+echo "configure:1388: checking "for Visual C++"" >&5
MSVC="no";
if test "${CC}" = "cl" ; then
MSVC="yes"
echo $ac_n "checking "the default compiler flags"""... $ac_c" 1>&6
-echo "configure:1479: checking "the default compiler flags"" >&5
+echo "configure:1428: checking "the default compiler flags"" >&5
ecosflags_enable_debug="no"
# Check whether --enable-debug or --disable-debug was given.
if test "${GCC}" = "yes" ; then
ecos_CFLAGS="${ecos_CFLAGS} -pipe -Wall -Wpointer-arith -Wbad-function-cast -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes -Wnested-externs"
- ecos_CXXFLAGS="${ecos_CXXFLAGS} -pipe -Wall -Wpointer-arith -Wbad-function-cast -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes -Wnested-externs -Woverloaded-virtual"
+ ecos_CXXFLAGS="${ecos_CXXFLAGS} -pipe -Wall -Wpointer-arith -Wcast-qual -Woverloaded-virtual"
elif test "${MSVC}" = "yes" ; then
ecos_CFLAGS="${ecos_CFLAGS} -nologo -W3"
ecos_CXXFLAGS="${ecos_CXXFLAGS} -nologo -W3 -GR -GX"
echo $ac_n "checking whether byte ordering is bigendian""... $ac_c" 1>&6
-echo "configure:1540: checking whether byte ordering is bigendian" >&5
+echo "configure:1489: checking whether byte ordering is bigendian" >&5
if eval "test \"`echo '$''{'ac_cv_c_bigendian'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
ac_cv_c_bigendian=unknown
# See if sys/param.h defines the BYTE_ORDER macro.
cat > conftest.$ac_ext <<EOF
-#line 1547 "configure"
+#line 1496 "configure"
#include "confdefs.h"
#include <sys/types.h>
#include <sys/param.h>
#endif
; return 0; }
EOF
-if { (eval echo configure:1558: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:1507: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest*
# It does; now see whether it defined to BIG_ENDIAN or not.
cat > conftest.$ac_ext <<EOF
-#line 1562 "configure"
+#line 1511 "configure"
#include "confdefs.h"
#include <sys/types.h>
#include <sys/param.h>
#endif
; return 0; }
EOF
-if { (eval echo configure:1573: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:1522: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest*
ac_cv_c_bigendian=yes
else
{ echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; }
else
cat > conftest.$ac_ext <<EOF
-#line 1593 "configure"
+#line 1542 "configure"
#include "confdefs.h"
main () {
/* Are we little or big endian? From Harbison&Steele. */
exit (u.c[sizeof (long) - 1] == 1);
}
EOF
-if { (eval echo configure:1606: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+if { (eval echo configure:1555: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
then
ac_cv_c_bigendian=no
else
echo $ac_n "checking "for a 64 bit data type"""... $ac_c" 1>&6
-echo "configure:1635: checking "for a 64 bit data type"" >&5
+echo "configure:1584: checking "for a 64 bit data type"" >&5
if eval "test \"`echo '$''{'ecos_cv_type_64bit'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
ctype_64bit="long long"
else
cat > conftest.$ac_ext <<EOF
-#line 1653 "configure"
+#line 1602 "configure"
#include "confdefs.h"
main() {
}
EOF
-if { (eval echo configure:1661: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+if { (eval echo configure:1610: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
then
ctype_64bit=$type
else
cxxtype_64bit="long long"
else
cat > conftest.$ac_ext <<EOF
-#line 1684 "configure"
+#line 1633 "configure"
#include "confdefs.h"
+#ifdef __cplusplus
+extern "C" void exit(int);
+#endif
int main(int argc, char ** argv) {
return 8 != sizeof($type);
}
EOF
-if { (eval echo configure:1692: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+if { (eval echo configure:1644: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
then
cxxtype_64bit=$type
else
echo $ac_n "checking size of int *""... $ac_c" 1>&6
-echo "configure:1737: checking size of int *" >&5
+echo "configure:1689: checking size of int *" >&5
if eval "test \"`echo '$''{'ac_cv_sizeof_int_p'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
{ echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; }
else
cat > conftest.$ac_ext <<EOF
-#line 1745 "configure"
+#line 1697 "configure"
#include "confdefs.h"
#include <stdio.h>
-int main()
+#include <sys/types.h>
+main()
{
FILE *f=fopen("conftestval", "w");
- if (!f) return(1);
+ if (!f) exit(1);
fprintf(f, "%d\n", sizeof(int *));
- return(0);
+ exit(0);
}
EOF
-if { (eval echo configure:1756: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+if { (eval echo configure:1709: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
then
ac_cv_sizeof_int_p=`cat conftestval`
else
echo $ac_n "checking size of long""... $ac_c" 1>&6
-echo "configure:1776: checking size of long" >&5
+echo "configure:1729: checking size of long" >&5
if eval "test \"`echo '$''{'ac_cv_sizeof_long'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
{ echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; }
else
cat > conftest.$ac_ext <<EOF
-#line 1784 "configure"
+#line 1737 "configure"
#include "confdefs.h"
#include <stdio.h>
-int main()
+#include <sys/types.h>
+main()
{
FILE *f=fopen("conftestval", "w");
- if (!f) return(1);
+ if (!f) exit(1);
fprintf(f, "%d\n", sizeof(long));
- return(0);
+ exit(0);
}
EOF
-if { (eval echo configure:1795: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+if { (eval echo configure:1749: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
then
ac_cv_sizeof_long=`cat conftestval`
else
echo $ac_n "checking "for __PRETTY_FUNCTION__ support"""... $ac_c" 1>&6
-echo "configure:1820: checking "for __PRETTY_FUNCTION__ support"" >&5
+echo "configure:1774: checking "for __PRETTY_FUNCTION__ support"" >&5
if eval "test \"`echo '$''{'ecos_cv_c_pretty_function'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cross_compiling=$ac_cv_prog_cc_cross
cat > conftest.$ac_ext <<EOF
-#line 1834 "configure"
+#line 1788 "configure"
#include "confdefs.h"
#include <stdio.h>
int main() {
puts(__PRETTY_FUNCTION__);
; return 0; }
EOF
-if { (eval echo configure:1841: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:1795: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
c_ok="yes"
else
cross_compiling=$ac_cv_prog_cxx_cross
cat > conftest.$ac_ext <<EOF
-#line 1860 "configure"
+#line 1814 "configure"
#include "confdefs.h"
#include <cstdio>
int main() {
puts(__PRETTY_FUNCTION__);
; return 0; }
EOF
-if { (eval echo configure:1867: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:1821: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
cxx_ok="yes"
else
for ac_func in mkstemp
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:1903: checking for $ac_func" >&5
+echo "configure:1857: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 1908 "configure"
+#line 1862 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
; return 0; }
EOF
-if { (eval echo configure:1931: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:1885: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
-2003-05-01 Jonathan Larmour <jifl@eCosCentric.com>
-
- * doc/package.sgml: Use PNGs instead of GIFs.
- * doc/jadetex.cfg: Add this to configure PDF output nicely with index
- and coloured links.
-
2003-02-12 Bart Veer <bartv@ecoscentric.com>
* Makefile.in, configure, testsuite/Makefile.in:
fi
fi
-for ac_declaration in \
- ''\
- '#include <stdlib.h>' \
- 'extern "C" void std::exit (int) throw (); using std::exit;' \
- 'extern "C" void std::exit (int); using std::exit;' \
- 'extern "C" void exit (int) throw ();' \
- 'extern "C" void exit (int);' \
- 'void exit (int);'
-do
- cat > conftest.$ac_ext <<EOF
-#line 1262 "configure"
-#include "confdefs.h"
-#include <stdlib.h>
-$ac_declaration
-int main() {
-exit (42);
-; return 0; }
-EOF
-if { (eval echo configure:1270: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
- :
-else
- echo "configure: failed program was:" >&5
- cat conftest.$ac_ext >&5
- rm -rf conftest*
- continue
-fi
-rm -f conftest*
- cat > conftest.$ac_ext <<EOF
-#line 1280 "configure"
-#include "confdefs.h"
-$ac_declaration
-int main() {
-exit (42);
-; return 0; }
-EOF
-if { (eval echo configure:1287: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
- rm -rf conftest*
- break
-else
- echo "configure: failed program was:" >&5
- cat conftest.$ac_ext >&5
-fi
-rm -f conftest*
-done
-if test -n "$ac_declaration"; then
- echo '#ifdef __cplusplus' >>confdefs.h
- echo $ac_declaration >>confdefs.h
- echo '#endif' >>confdefs.h
-fi
-
-
# Extract the first word of "ranlib", so it can be a program name with args.
set dummy ranlib; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1306: checking for $ac_word" >&5
+echo "configure:1255: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
fi
echo $ac_n "checking for object suffix""... $ac_c" 1>&6
-echo "configure:1334: checking for object suffix" >&5
+echo "configure:1283: checking for object suffix" >&5
if eval "test \"`echo '$''{'ac_cv_objext'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
rm -f conftest*
echo 'int i = 1;' > conftest.$ac_ext
-if { (eval echo configure:1340: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:1289: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
for ac_file in conftest.*; do
case $ac_file in
*.c) ;;
ac_objext=$ac_cv_objext
echo $ac_n "checking for Cygwin environment""... $ac_c" 1>&6
-echo "configure:1358: checking for Cygwin environment" >&5
+echo "configure:1307: checking for Cygwin environment" >&5
if eval "test \"`echo '$''{'ac_cv_cygwin'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 1363 "configure"
+#line 1312 "configure"
#include "confdefs.h"
int main() {
return __CYGWIN__;
; return 0; }
EOF
-if { (eval echo configure:1374: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:1323: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest*
ac_cv_cygwin=yes
else
CYGWIN=
test "$ac_cv_cygwin" = yes && CYGWIN=yes
echo $ac_n "checking for mingw32 environment""... $ac_c" 1>&6
-echo "configure:1391: checking for mingw32 environment" >&5
+echo "configure:1340: checking for mingw32 environment" >&5
if eval "test \"`echo '$''{'ac_cv_mingw32'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 1396 "configure"
+#line 1345 "configure"
#include "confdefs.h"
int main() {
return __MINGW32__;
; return 0; }
EOF
-if { (eval echo configure:1403: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:1352: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest*
ac_cv_mingw32=yes
else
echo $ac_n "checking for executable suffix""... $ac_c" 1>&6
-echo "configure:1422: checking for executable suffix" >&5
+echo "configure:1371: checking for executable suffix" >&5
if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
rm -f conftest*
echo 'int main () { return 0; }' > conftest.$ac_ext
ac_cv_exeext=
- if { (eval echo configure:1432: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
+ if { (eval echo configure:1381: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
for file in conftest.*; do
case $file in
- *.c | *.o | *.obj) ;;
+ *.$ac_ext | *.c | *.o | *.obj) ;;
*) ac_cv_exeext=`echo $file | sed -e s/conftest//` ;;
esac
done
echo $ac_n "checking "for Visual C++"""... $ac_c" 1>&6
-echo "configure:1470: checking "for Visual C++"" >&5
+echo "configure:1419: checking "for Visual C++"" >&5
MSVC="no";
if test "${CC}" = "cl" ; then
MSVC="yes"
echo $ac_n "checking "the default compiler flags"""... $ac_c" 1>&6
-echo "configure:1510: checking "the default compiler flags"" >&5
+echo "configure:1459: checking "the default compiler flags"" >&5
ecosflags_enable_debug="no"
# Check whether --enable-debug or --disable-debug was given.
if test "${GCC}" = "yes" ; then
ecos_CFLAGS="${ecos_CFLAGS} -pipe -Wall -Wpointer-arith -Wbad-function-cast -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes -Wnested-externs"
- ecos_CXXFLAGS="${ecos_CXXFLAGS} -pipe -Wall -Wpointer-arith -Wbad-function-cast -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes -Wnested-externs -Woverloaded-virtual"
+ ecos_CXXFLAGS="${ecos_CXXFLAGS} -pipe -Wall -Wpointer-arith -Wcast-qual -Woverloaded-virtual"
elif test "${MSVC}" = "yes" ; then
ecos_CFLAGS="${ecos_CFLAGS} -nologo -W3"
ecos_CXXFLAGS="${ecos_CXXFLAGS} -nologo -W3 -GR -GX"
echo $ac_n "checking for eCos host-side infrastructure""... $ac_c" 1>&6
-echo "configure:1712: checking for eCos host-side infrastructure" >&5
+echo "configure:1661: checking for eCos host-side infrastructure" >&5
infra_builddir=""
possibles=".. ../.. ../../.. ../../../.. ../../../../.."
ecos_tk_libdir=""
echo $ac_n "checking for Tcl installation""... $ac_c" 1>&6
-echo "configure:1826: checking for Tcl installation" >&5
+echo "configure:1775: checking for Tcl installation" >&5
# Check whether --with-tcl or --without-tcl was given.
if test "${with_tcl+set}" = set; then
withval="$with_tcl"
<informalfigure PgWide=1>
<mediaobject>
<imageobject>
-<imagedata fileref="repo.png" Scalefit=1 Align="Center">
+<imagedata fileref="repo.eps" format="eps" Scalefit=1 Align="Center">
+</imageobject>
+<imageobject>
+<imagedata fileref="repo.gif" format="gif" Align="Center">
</imageobject>
</mediaobject>
</informalfigure>
<informalfigure PgWide=1>
<mediaobject>
<imageobject>
-<imagedata fileref="version.png" Scalefit=1 Align="Center">
+<imagedata fileref="version.eps" format="eps" Scalefit=1 Align="Center">
+</imageobject>
+<imageobject>
+<imagedata fileref="version.gif" format="gif" Align="Center">
</imageobject>
</mediaobject>
</informalfigure>
<informalfigure PgWide=1>
<mediaobject>
<imageobject>
-<imagedata fileref="package.png" Scalefit=1 Align="Center">
+<imagedata fileref="package.eps" format="eps" Scalefit=1 Align="Center">
+</imageobject>
+<imageobject>
+<imagedata fileref="package.gif" format="gif" Align="Center">
</imageobject>
</mediaobject>
</informalfigure>
<!-- }}} -->
-</chapter>
+</chapter>
\ No newline at end of file
-2003-04-30 John Dallaway <jld@ecoscentric.com>
-
- * common/eCosStd.h: Update version string to "2.0".
- Use WSAEWOULDBLOCK under Cygwin.
-
2003-02-12 Bart Veer <bartv@ecoscentric.com>
* common/configure, common/Makefile.in:
fi
fi
-for ac_declaration in \
- ''\
- '#include <stdlib.h>' \
- 'extern "C" void std::exit (int) throw (); using std::exit;' \
- 'extern "C" void std::exit (int); using std::exit;' \
- 'extern "C" void exit (int) throw ();' \
- 'extern "C" void exit (int);' \
- 'void exit (int);'
-do
- cat > conftest.$ac_ext <<EOF
-#line 1240 "configure"
-#include "confdefs.h"
-#include <stdlib.h>
-$ac_declaration
-int main() {
-exit (42);
-; return 0; }
-EOF
-if { (eval echo configure:1248: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
- :
-else
- echo "configure: failed program was:" >&5
- cat conftest.$ac_ext >&5
- rm -rf conftest*
- continue
-fi
-rm -f conftest*
- cat > conftest.$ac_ext <<EOF
-#line 1258 "configure"
-#include "confdefs.h"
-$ac_declaration
-int main() {
-exit (42);
-; return 0; }
-EOF
-if { (eval echo configure:1265: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
- rm -rf conftest*
- break
-else
- echo "configure: failed program was:" >&5
- cat conftest.$ac_ext >&5
-fi
-rm -f conftest*
-done
-if test -n "$ac_declaration"; then
- echo '#ifdef __cplusplus' >>confdefs.h
- echo $ac_declaration >>confdefs.h
- echo '#endif' >>confdefs.h
-fi
-
-
# Extract the first word of "ranlib", so it can be a program name with args.
set dummy ranlib; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1284: checking for $ac_word" >&5
+echo "configure:1233: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
fi
echo $ac_n "checking for object suffix""... $ac_c" 1>&6
-echo "configure:1312: checking for object suffix" >&5
+echo "configure:1261: checking for object suffix" >&5
if eval "test \"`echo '$''{'ac_cv_objext'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
rm -f conftest*
echo 'int i = 1;' > conftest.$ac_ext
-if { (eval echo configure:1318: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:1267: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
for ac_file in conftest.*; do
case $ac_file in
*.c) ;;
ac_objext=$ac_cv_objext
echo $ac_n "checking for Cygwin environment""... $ac_c" 1>&6
-echo "configure:1336: checking for Cygwin environment" >&5
+echo "configure:1285: checking for Cygwin environment" >&5
if eval "test \"`echo '$''{'ac_cv_cygwin'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 1341 "configure"
+#line 1290 "configure"
#include "confdefs.h"
int main() {
return __CYGWIN__;
; return 0; }
EOF
-if { (eval echo configure:1352: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:1301: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest*
ac_cv_cygwin=yes
else
CYGWIN=
test "$ac_cv_cygwin" = yes && CYGWIN=yes
echo $ac_n "checking for mingw32 environment""... $ac_c" 1>&6
-echo "configure:1369: checking for mingw32 environment" >&5
+echo "configure:1318: checking for mingw32 environment" >&5
if eval "test \"`echo '$''{'ac_cv_mingw32'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 1374 "configure"
+#line 1323 "configure"
#include "confdefs.h"
int main() {
return __MINGW32__;
; return 0; }
EOF
-if { (eval echo configure:1381: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:1330: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest*
ac_cv_mingw32=yes
else
echo $ac_n "checking for executable suffix""... $ac_c" 1>&6
-echo "configure:1400: checking for executable suffix" >&5
+echo "configure:1349: checking for executable suffix" >&5
if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
rm -f conftest*
echo 'int main () { return 0; }' > conftest.$ac_ext
ac_cv_exeext=
- if { (eval echo configure:1410: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
+ if { (eval echo configure:1359: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
for file in conftest.*; do
case $file in
- *.c | *.o | *.obj) ;;
+ *.$ac_ext | *.c | *.o | *.obj) ;;
*) ac_cv_exeext=`echo $file | sed -e s/conftest//` ;;
esac
done
echo $ac_n "checking "for Visual C++"""... $ac_c" 1>&6
-echo "configure:1448: checking "for Visual C++"" >&5
+echo "configure:1397: checking "for Visual C++"" >&5
MSVC="no";
if test "${CC}" = "cl" ; then
MSVC="yes"
echo $ac_n "checking "the default compiler flags"""... $ac_c" 1>&6
-echo "configure:1488: checking "the default compiler flags"" >&5
+echo "configure:1437: checking "the default compiler flags"" >&5
ecosflags_enable_debug="no"
# Check whether --enable-debug or --disable-debug was given.
if test "${GCC}" = "yes" ; then
ecos_CFLAGS="${ecos_CFLAGS} -pipe -Wall -Wpointer-arith -Wbad-function-cast -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes -Wnested-externs"
- ecos_CXXFLAGS="${ecos_CXXFLAGS} -pipe -Wall -Wpointer-arith -Wbad-function-cast -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes -Wnested-externs -Woverloaded-virtual"
+ ecos_CXXFLAGS="${ecos_CXXFLAGS} -pipe -Wall -Wpointer-arith -Wcast-qual -Woverloaded-virtual"
elif test "${MSVC}" = "yes" ; then
ecos_CFLAGS="${ecos_CFLAGS} -nologo -W3"
ecos_CXXFLAGS="${ecos_CXXFLAGS} -nologo -W3 -GR -GX"
#include <malloc.h> // malloc
#include <stdlib.h> // atoi
#include <errno.h>
- #define WOULDBLOCK WSAEWOULDBLOCK
+ #define WOULDBLOCK EWOULDBLOCK
#include "wcharunix.h"
#include <sys/time.h>
#define MODE_TEXT
#endif
-#define ECOS_VERSION "2.0"
+#define ECOS_VERSION "1.3.2"
typedef int Duration;
-2003-05-02 John Dallaway <jld@ecoscentric.com>
-
- * standalone/wxwin/appsettings.cpp: Don't use "." in the PATH to
- look for build tools and user tools.
-
-2003-05-01 John Dallaway <jld@ecoscentric.com>
-
- * standalone/common/cdl_exec.cxx: Generate Cygwin text-mode mounts
- explicitly since text-mode is no longer the default.
-
- * standalone/wxwin/runtestsdlg.cpp: Use the rich edit control under
- Windows to eliminate a 64k limit on the length of text in the test
- output window and make the window read-only.
-
-2003-04-25 John Dallaway <jld@ecoscentric.com>
-
- * standalone/wxwin/docsystem.cpp: Accommodate the latest HTML doc
- structure.
-
-2003-04-24 John Dallaway <jld@ecoscentric.com>
-
- * standalone/wxwin/mainwin.cpp: Fix behaviour of user tools warning
- message box.
-
- * standalone/wxwin/makefile.gnu: Deduce OS type using uname tool.
-
-2003-04-17 John Dallaway <jld@ecoscentric.com>
-
- * standalone/wxwin/appsettings.cpp, standalone/wxwin/mainwin.cpp:
- Rationalise the treatment of the build tools directory during startup
- and when using the build tools dialog.
-
- * standalone/wxwin/configtool.cpp: Wait for the installation of platform
- definitions to complete on Linux.
-
-2003-04-16 John Dallaway <jld@ecoscentric.com>
-
- * standalone/wxwin/configtool.cpp: Install default platform definitions
- on initial invocation. Generate Cygwin text-mode mounts explicitly since
- text-mode is no longer the default mount type.
-
-2003-04-11 John Dallaway <jld@ecoscentric.com>
-
- * standalone/wxwin/ecutils.cpp, standalone/wxwin/ecutils.h: Create
- wxString wrappers for cygwin_conv_to_*_path().
-
- * standalone/wxwin/appsettings.cpp: Accommodate POSIX-style values of
- the ECOS_REPOSITORY environment variable.
-
-2003-04-10 John Dallaway <jld@ecoscentric.com>
-
- * standalone/wxwin/docsystem.cpp: Eliminate pop-up warning when
- attempting to create a directory under $HOME/.eCosDocs/ which already
- exists.
-
-2003-04-07 John Dallaway <jld@ecoscentric.com>
-
- * standalone/wxwin/appsettings.cpp,
- standalone/wxwin/appsettings.h: Look for user tools and build
- tools relative to the configtool executable file.
-
-2003-04-05 John Dallaway <jld@ecoscentric.com>
-
- * standalone/wxwin/makefile.gnu: Build Cygwin hosted configtool with
- "--subsystem windows" to eliminate the console window.
-
- * standalone/wxwin/admindlg.cpp: Strip CR characters from the license
- text on Linux.
-
-2003-03-28 John Dallaway <jld@ecoscentric.com>
-
- * standalone/wxwin/packagesdlg.cpp: Fix population of package lists
- to ensure the last package is seen. [ Bugzilla 87520 ]
-
-2003-03-26 John Dallaway <jld@ecoscentric.com>
-
- * standalone/wxwin/makefile.gnu: Tidy up.
-
- * standalone/wxwin/splittree.cpp: Fix wxRemotelyScrolledTreeCtrl for
- wxWindows 2.4.0 on Linux/GTK. Patch contributed by Julian Smart.
-
-2003-03-25 John Dallaway <jld@ecoscentric.com>
-
- * standalone/wxwin/symbols.h,
- standalone/wxwin/aboutdlg.cpp,
- standalone/wxwin/configtool.cpp,
- standalone/wxwin/mainwin.cpp: Use a character string to represent
- the configtool version number.
-
- * standalone/wxwin/runtestsdlg.cpp: Remove CR characters in test
- output. [ Bugzilla 85163 ]
-
-2003-03-19 John Dallaway <jld@ecoscentric.com>
-
- * standalone/wxwin/appsettings.cpp,
- standalone/wxwin/configtooldoc.cpp,
- standalone/wxwin/ecpch.h,
- standalone/wxwin/filename.cpp,
- standalone/wxwin/configtool.rc,
- standalone/wxwin/makefile.gnu: Allow configtool to build against
- wxWindows 2.4.0 using Cygwin GCC.
-
-2003-03-18 John Dallaway <jld@ecoscentric.com>
-
- * standalone/wxwin/appsettings.cpp,
- standalone/wxwin/configtool.cpp: Look for a default repository
- at ../../packages relative to the configtool location as a last
- resort.
-
- * standalone/wxwin/configtool.cpp: Eliminate scroll bar jitter in
- the output pane during eCos builds.
-
- * standalone/wxwin/configtool.cpp (HasInput),
- standalone/wxwin/mainwin.cpp,
- standalone/wxwin/configtool.rc,
- standalone/wxwin/makefile.gnu: Allow configtool to build and run
- against wxWindows 2.4.0.
-
2003-03-07 John Dallaway <jld@ecoscentric.com>
* standalone/wxwin/appsettings.cpp: Look in the right place for the
//
// ----------------------------------------------------------------------------
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-// Copyright (C) 2003 John Dallaway
//
// This program is part of the eCos host tools.
//
status = true;
#ifdef __CYGWIN__
char buf[100];
- strcpy(buf, "mount.exe -f -t -u x: /ecos-x");
+ strcpy(buf, "mount.exe -f x: /ecos-x");
//printf("Cwd_win32: %s\n", cwd_win32);
if ( cwd_win32[1] == ':' )
{
- buf[19] = tolower(cwd_win32[0]);
- buf[28] = tolower(cwd_win32[0]);
+ buf[13] = cwd_win32[0];
+ buf[22] = cwd_win32[0];
system(buf);
}
if ( repository[1] == ':' )
{
- buf[19] = tolower(repository[0]);
- buf[28] = tolower(repository[0]);
+ buf[13] = repository[0];
+ buf[22] = repository[0];
system(buf);
}
if ( !install_prefix.empty() )
//printf("Install prefix: %s\n", install_prefix.c_str());
if ( install_prefix[1] == ':' )
{
- buf[19] = tolower(install_prefix[0]);
- buf[28] = tolower(install_prefix[0]);
+ buf[13] = install_prefix[0];
+ buf[22] = install_prefix[0];
system(buf);
}
}
fi
fi
-for ac_declaration in \
- ''\
- '#include <stdlib.h>' \
- 'extern "C" void std::exit (int) throw (); using std::exit;' \
- 'extern "C" void std::exit (int); using std::exit;' \
- 'extern "C" void exit (int) throw ();' \
- 'extern "C" void exit (int);' \
- 'void exit (int);'
-do
- cat > conftest.$ac_ext <<EOF
-#line 1260 "configure"
-#include "confdefs.h"
-#include <stdlib.h>
-$ac_declaration
-int main() {
-exit (42);
-; return 0; }
-EOF
-if { (eval echo configure:1268: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
- :
-else
- echo "configure: failed program was:" >&5
- cat conftest.$ac_ext >&5
- rm -rf conftest*
- continue
-fi
-rm -f conftest*
- cat > conftest.$ac_ext <<EOF
-#line 1278 "configure"
-#include "confdefs.h"
-$ac_declaration
-int main() {
-exit (42);
-; return 0; }
-EOF
-if { (eval echo configure:1285: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
- rm -rf conftest*
- break
-else
- echo "configure: failed program was:" >&5
- cat conftest.$ac_ext >&5
-fi
-rm -f conftest*
-done
-if test -n "$ac_declaration"; then
- echo '#ifdef __cplusplus' >>confdefs.h
- echo $ac_declaration >>confdefs.h
- echo '#endif' >>confdefs.h
-fi
-
-
echo $ac_n "checking for object suffix""... $ac_c" 1>&6
-echo "configure:1302: checking for object suffix" >&5
+echo "configure:1251: checking for object suffix" >&5
if eval "test \"`echo '$''{'ac_cv_objext'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
rm -f conftest*
echo 'int i = 1;' > conftest.$ac_ext
-if { (eval echo configure:1308: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:1257: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
for ac_file in conftest.*; do
case $ac_file in
*.c) ;;
ac_objext=$ac_cv_objext
echo $ac_n "checking for Cygwin environment""... $ac_c" 1>&6
-echo "configure:1326: checking for Cygwin environment" >&5
+echo "configure:1275: checking for Cygwin environment" >&5
if eval "test \"`echo '$''{'ac_cv_cygwin'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 1331 "configure"
+#line 1280 "configure"
#include "confdefs.h"
int main() {
return __CYGWIN__;
; return 0; }
EOF
-if { (eval echo configure:1342: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:1291: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest*
ac_cv_cygwin=yes
else
CYGWIN=
test "$ac_cv_cygwin" = yes && CYGWIN=yes
echo $ac_n "checking for mingw32 environment""... $ac_c" 1>&6
-echo "configure:1359: checking for mingw32 environment" >&5
+echo "configure:1308: checking for mingw32 environment" >&5
if eval "test \"`echo '$''{'ac_cv_mingw32'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 1364 "configure"
+#line 1313 "configure"
#include "confdefs.h"
int main() {
return __MINGW32__;
; return 0; }
EOF
-if { (eval echo configure:1371: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:1320: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest*
ac_cv_mingw32=yes
else
echo $ac_n "checking for executable suffix""... $ac_c" 1>&6
-echo "configure:1390: checking for executable suffix" >&5
+echo "configure:1339: checking for executable suffix" >&5
if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
rm -f conftest*
echo 'int main () { return 0; }' > conftest.$ac_ext
ac_cv_exeext=
- if { (eval echo configure:1400: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
+ if { (eval echo configure:1349: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
for file in conftest.*; do
case $file in
- *.c | *.o | *.obj) ;;
+ *.$ac_ext | *.c | *.o | *.obj) ;;
*) ac_cv_exeext=`echo $file | sed -e s/conftest//` ;;
esac
done
echo $ac_n "checking "for Visual C++"""... $ac_c" 1>&6
-echo "configure:1438: checking "for Visual C++"" >&5
+echo "configure:1387: checking "for Visual C++"" >&5
MSVC="no";
if test "${CC}" = "cl" ; then
MSVC="yes"
echo $ac_n "checking "the default compiler flags"""... $ac_c" 1>&6
-echo "configure:1478: checking "the default compiler flags"" >&5
+echo "configure:1427: checking "the default compiler flags"" >&5
ecosflags_enable_debug="no"
# Check whether --enable-debug or --disable-debug was given.
if test "${GCC}" = "yes" ; then
ecos_CFLAGS="${ecos_CFLAGS} -pipe -Wall -Wpointer-arith -Wbad-function-cast -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes -Wnested-externs"
- ecos_CXXFLAGS="${ecos_CXXFLAGS} -pipe -Wall -Wpointer-arith -Wbad-function-cast -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes -Wnested-externs -Woverloaded-virtual"
+ ecos_CXXFLAGS="${ecos_CXXFLAGS} -pipe -Wall -Wpointer-arith -Wcast-qual -Woverloaded-virtual"
elif test "${MSVC}" = "yes" ; then
ecos_CFLAGS="${ecos_CFLAGS} -nologo -W3"
ecos_CXXFLAGS="${ecos_CXXFLAGS} -nologo -W3 -GR -GX"
echo $ac_n "checking for libcdl""... $ac_c" 1>&6
-echo "configure:1681: checking for libcdl" >&5
+echo "configure:1630: checking for libcdl" >&5
libcdl_srcdir=""
possibles="${srcdir}/.. ${srcdir}/../.. ${srcdir}/../../.. ${srcdir}/../../../.. ${srcdir}/../../../../.."
echo $ac_n "checking for eCos host-side infrastructure""... $ac_c" 1>&6
-echo "configure:1817: checking for eCos host-side infrastructure" >&5
+echo "configure:1766: checking for eCos host-side infrastructure" >&5
infra_builddir=""
possibles=".. ../.. ../../.. ../../../.. ../../../../.."
ecos_tk_libdir=""
echo $ac_n "checking for Tcl installation""... $ac_c" 1>&6
-echo "configure:1931: checking for Tcl installation" >&5
+echo "configure:1880: checking for Tcl installation" >&5
# Check whether --with-tcl or --without-tcl was given.
if test "${with_tcl+set}" = set; then
withval="$with_tcl"
#include "cdl_exec.hxx"
#include "ecosconfig.hxx"
-#define TOOL_VERSION "2.0"
+#define TOOL_VERSION "2.0b1"
#define TOOL_COPYRIGHT "Copyright (c) 2002 Red Hat, Inc."
#define DEFAULT_SAVE_FILE "ecos.ecc"
static char* tool = "ecosconfig";
}
// Customize the HTML
- htmlText.Replace(wxT("$VERSION$"), ecCONFIGURATION_TOOL_VERSION);
+ wxString verString;
+ verString.Printf("%.2f", ecCONFIGURATION_TOOL_VERSION);
+ htmlText.Replace(wxT("$VERSION$"), verString);
htmlText.Replace(wxT("$DATE$"), __DATE__);
wxSize htmlSize(420, 390);
#ifdef __WXMSW__
if (-1 == strLicenseText.Find (wxT("\r\n"))) // if the file has LF line endings...
strLicenseText.Replace (_T("\n"), _T("\r\n")); // ... replace with CRLF line endings
-#else
- strLicenseText.Replace (_T("\r"), wxEmptyString); // remove CR characters
-#endif
+#endif
// display the license text
-
+
ecLicenseDialog dlgLicense (strLicenseText, this, ecID_LICENSE_DIALOG, strPathName + _(" - Add Packages"));
if (wxID_OK != dlgLicense.ShowModal ()) // if license not accepted by user
continue; // try the next file
#ifdef __WXMSW__
#include <windows.h>
#include "wx/msw/winundef.h"
-#ifdef GetTempPath
+#if defined(GetTempPath) && !defined(__CYGWIN__)
#undef GetTempPath
#endif
#endif
// Only to be used if we fail to find the information installed
// with the Configuration Tool.
config.Read(_("/Paths/BuildToolsDir"), & m_buildToolsDir);
- if (m_buildToolsDir.IsEmpty()) // first invocation by this user
- {
- // we have no clues as to the location of the build tools so
- // test for ../../../gnutools relative to the configtool location
- wxFileName gnutools = wxFileName (wxGetApp().GetAppDir(), wxEmptyString);
- gnutools.Normalize(); // remove trailing "./" if present
- if (2 < gnutools.GetDirCount())
- {
- gnutools.RemoveDir (gnutools.GetDirCount()-1);
- gnutools.RemoveDir (gnutools.GetDirCount()-1);
- gnutools.RemoveDir (gnutools.GetDirCount()-1);
- gnutools.AppendDir (wxT("gnutools"));
- if (gnutools.DirExists()) // we've found the gnutools
- m_buildToolsDir = gnutools.GetFullPath();
- }
- }
-
- // look for *objcopy in and under the build tools directory
- if (! m_buildToolsDir.IsEmpty())
- {
- wxArrayString objcopyFiles;
- wxString objcopyFileSpec(wxT("objcopy"));
-#ifdef __WXMSW__
- objcopyFileSpec += wxT(".exe");
-#endif
- size_t objcopyCount = wxDir::GetAllFiles(m_buildToolsDir, &objcopyFiles, wxT("*") + objcopyFileSpec, wxDIR_FILES | wxDIR_DIRS);
- for (int count=0; count < objcopyCount; count++)
- {
- wxFileName file (objcopyFiles [count]);
- wxString new_prefix (file.GetFullName().Left (file.GetFullName().Find(objcopyFileSpec)));
- if ((! new_prefix.IsEmpty()) && ('-' == new_prefix.Last()))
- new_prefix = new_prefix.Left (new_prefix.Len() - 1); // strip off trailing hyphen
- m_arstrBinDirs.Set(new_prefix, file.GetPath(wxPATH_GET_VOLUME));
- }
- }
-
+
if (!config.Read(_("/Build/Make Options"), & m_strMakeOptions))
{
#ifdef __WXMSW__
wxArrayString arstrPath;
ecUtils::Chop(strPath, arstrPath, wxT(':'));
-
+
for (int i = arstrPath.GetCount()-1;i >= 0; --i)
{ // Reverse order is important to treat path correctly
- if (wxT(".") != arstrPath[i] && !arstrPath[i].IsEmpty())
+ wxLogNull log;
+ wxDir finder(arstrPath[i]);
+ wxString filename;
+
+ if (finder.IsOpened())
{
- wxLogNull log;
- wxDir finder(arstrPath[i]);
- wxString filename;
-
- if (finder.IsOpened())
+ bool bMore = finder.GetFirst(& filename, gccExe);
+ while (bMore)
{
- bool bMore = finder.GetFirst(& filename, gccExe);
- while (bMore)
- {
- wxString targetName = filename.Left(filename.Find(wxT("-gcc")));
- m_arstrBinDirs.Set(targetName, arstrPath[i]);
-
- bMore = finder.GetNext(& filename);
- }
+ wxString targetName = filename.Left(filename.Find(wxT("-gcc")));
+ m_arstrBinDirs.Set(targetName, arstrPath[i]);
+
+ bMore = finder.GetNext(& filename);
}
}
}
// Read toolchain paths (local machine again)
#ifdef __WXMSW__
wxArrayString arstrToolChainPaths;
-
+
// Use eCos just as a test.
//GetRepositoryRegistryClues(arstrToolChainPaths,_T("eCos"));
GetRepositoryRegistryClues(arstrToolChainPaths,_T("GNUPro eCos"));
for (int i = arstrPath.GetCount()-1;i >= 0; --i)
{ // Reverse order is important to treat path correctly
-
+
const ecFileName &strFolder = arstrPath[i];
- if (wxT(".") != strFolder && !strFolder.IsEmpty())
+ ecFileName strFile(strFolder);
+ strFile += wxT("ls.exe");
+ if ( strFile.Exists() )
{
- ecFileName strFile(strFolder);
- strFile += wxT("ls.exe");
- if ( strFile.Exists() )
+ if (!wxArrayStringIsMember(m_userToolPaths, strFolder))
{
- if (!wxArrayStringIsMember(m_userToolPaths, strFolder))
- {
- m_userToolPaths.Add(strFolder);
- }
-
- if ( m_userToolsDir.IsEmpty() )
- {
- m_userToolsDir = strFolder;
- }
+ m_userToolPaths.Add(strFolder);
+ }
+
+ if ( m_userToolsDir.IsEmpty() )
+ {
+ m_userToolsDir = strFolder;
}
}
}
// Note that ECOS_REPOSITORY has the packages (or ecc) folder in the name.
// In order to be in the form that is compatible with configtool operation,
// it needs to have that stripped off.
- envVarValue = ecUtils::PosixToNativePath(envVarValue); // accommodate posix-style ECOS_REPOSITORY value under Cygwin
wxString packagesName = wxFileNameFromPath(envVarValue);
if (packagesName == wxT("ecc") || packagesName == wxT("packages"))
envVarValue = wxPathOnly(envVarValue);
}
}
-#ifdef __WXMSW__
- if (m_userToolsDir.IsEmpty())
- m_userToolsDir = GetCygwinInstallPath() + wxT("\\bin");
-#else
+#ifdef __WXGTK__
if (m_userToolsDir.IsEmpty())
m_userToolsDir = wxT("/bin");
#endif
return TRUE;
}
-#ifdef __WXMSW__
-wxString ecSettings::GetCygwinInstallPath()
-{
- HKEY hKey = 0;
- DWORD type;
- BYTE value[256];
- DWORD sz = sizeof(value);
- wxString strCygwinInstallPath;
-
- // look for the "/" mount point in the system registry settings
- if (ERROR_SUCCESS == RegOpenKeyEx(HKEY_LOCAL_MACHINE, "Software\\Cygnus Solutions\\Cygwin\\mounts v2\\/", 0, KEY_READ, &hKey)) {
- if (ERROR_SUCCESS == RegQueryValueEx(hKey, "native", NULL, & type, value, & sz)) {
- strCygwinInstallPath = (const char*) value;
- }
- RegCloseKey(hKey);
- }
-
- // if not yet found, look for the "/" mount point in the user's registry settings
- hKey = 0;
- sz = sizeof(value);
- if (strCygwinInstallPath.IsEmpty() && (ERROR_SUCCESS == RegOpenKeyEx(HKEY_CURRENT_USER, "Software\\Cygnus Solutions\\Cygwin\\mounts v2\\/", 0, KEY_READ, &hKey))) {
- if (ERROR_SUCCESS == RegQueryValueEx(hKey, "native", NULL, & type, value, & sz)) {
- strCygwinInstallPath = (const char*) value;
- }
- RegCloseKey(hKey);
- }
-
- return strCygwinInstallPath;
-}
-#endif
-
// Save config info
bool ecSettings::SaveConfig()
{
cont = dir.GetNext(& filename);
}
}
-// if (latestDir.IsEmpty())
-// latestDir = wxGetCwd();
+ if (latestDir.IsEmpty())
+ latestDir = wxGetCwd();
return latestDir;
#else
wxMessageBox(wxT("FindLatestVersion() is only implemented for Unix."));
//
// ----------------------------------------------------------------------------
// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
-// Copyright (C) 2003 John Dallaway
//
// This program is part of the eCos host tools.
//
//===========================================================================
//#####DESCRIPTIONBEGIN####
//
-// Author(s): julians, jld
+// Author(s): julians
// Contact(s): julians
// Date: 2000/08/29
// Version: $Id$
// Find the subkey of the latest installed eCos, e.g. "1.4.9"
wxString GetInstallVersionKey ();
-
-#ifdef __WXMSW__
- // Find the location of the Cygwin installation
- wxString GetCygwinInstallPath ();
-#endif
//// Accessors
{
wxLog::SetTimestamp(NULL);
+ CeCosSocket::Init();
+ CeCosTestPlatform::Load();
+
wxHelpProvider::Set(new wxSimpleHelpProvider);
//wxHelpProvider::Set(new wxHelpControllerHelpProvider(& m_helpController));
m_appDir = wxPathOnly(m_appDir);
#endif
-// Install default platform definitions if no platforms defined
-#ifdef __WXMSW__
- wxConfig config (wxGetApp().GetSettings().GetConfigAppName());
- if (! config.Exists (wxT("Platforms")))
- {
- wxFileName platforms (m_appDir, wxT("platforms.reg"));
- platforms.Normalize();
- if (platforms.FileExists())
- wxExecute (wxT("regedit /s \"") + platforms.GetFullPath() + wxT("\""), wxEXEC_SYNC);
- }
-#endif
-#ifdef __WXGTK__
- wxFileName config (wxFileName::GetHomeDir(), wxEmptyString);
- config.AppendDir(wxT(".eCosPlatforms"));
- if (! config.DirExists())
- {
- wxFileName platforms (m_appDir, wxT("platforms.tar"));
- platforms.Normalize();
- if (platforms.FileExists())
- wxExecute (wxT("tar -C ") + wxFileName::GetHomeDir() + wxT(" -xf ") + platforms.GetFullPath(), wxEXEC_SYNC);
- }
-#endif
-
- CeCosSocket::Init();
- CeCosTestPlatform::Load();
-
// Load resources from binary resources archive, or failing that, from
// Windows resources or plain files
LoadResources();
wxLog::SetActiveTarget(new wxLogStderr);
#endif
wxString msg;
- msg.Printf(wxT("eCos Configuration Tool (c) Red Hat, 2001 Version %s, %s"), ecCONFIGURATION_TOOL_VERSION, __DATE__);
+ msg.Printf(wxT("eCos Configuration Tool (c) Red Hat, 2001 Version %.2f, %s"), ecCONFIGURATION_TOOL_VERSION, __DATE__);
wxLogMessage(msg);
return FALSE;
}
wxString msg;
msg.Printf(wxT("Sorry, there was a problem compiling the help index."));
wxMessageBox(msg, wxGetApp().GetSettings().GetAppName(), wxICON_EXCLAMATION|wxOK);
- return FALSE;
+ return FALSE;
}
}
else
wxString msg;
msg.Printf(wxT("Sorry, there was no current document when compiling the help index."));
wxMessageBox(msg, wxGetApp().GetSettings().GetAppName(), wxICON_EXCLAMATION|wxOK);
- return FALSE;
+ return FALSE;
}
// Return FALSE in order to quit the application
}
else
{
- if (GetSettings().m_strRepository.IsEmpty()) // first invocation by this user
- {
- // we have no clues as to the location of the repository so
- // test for ../../packages relative to the configtool location
- wxFileName repository = wxFileName (m_appDir, wxEmptyString);
- repository.Normalize(); // remove trailing "./" if present
- repository.RemoveDir (repository.GetDirCount()-1);
- repository.RemoveDir (repository.GetDirCount()-1);
- repository.AppendDir (wxT("packages"));
- if (repository.DirExists()) // we've found a repository
- {
- repository.RemoveDir (repository.GetDirCount()-1);
- GetSettings().m_strRepository = repository.GetFullPath();
- }
- }
m_docManager->CreateDocument(wxString(""), wxDOC_NEW);
}
// Bottom left of area to start drawing at
wxString verString;
- verString.Printf("%s", ecCONFIGURATION_TOOL_VERSION);
+ verString.Printf("%.2f", ecCONFIGURATION_TOOL_VERSION);
int x = 339; int y = 231;
#ifdef __WXMSW__
if ((msg == wxEmptyString) || (msg.Last() != wxT('\n')))
frame->GetOutputWindow()->AppendText(wxT("\n"));
-// frame->GetOutputWindow()->ShowPosition(frame->GetOutputWindow()->GetLastPosition());
+ frame->GetOutputWindow()->ShowPosition(frame->GetOutputWindow()->GetLastPosition());
}
}
wxString strCmd;
String strOutput;
- strCmd.Printf(wxT("mount -t -u %c: /ecos-%c"),c,c);
+ strCmd.Printf(wxT("mount %c: /ecos-%c"),c,c);
CSubprocess sub;
sub.Run(strOutput,strCmd);
}
bool hasInput = FALSE;
wxInputStream& is = *GetInputStream();
- if ( IsInputAvailable() )
+ if ( !is.Eof() )
{
wxTextInputStream tis(is);
}
wxInputStream& es = *GetErrorStream();
- if ( IsErrorAvailable() )
+ if ( !es.Eof() )
{
wxTextInputStream tis(es);
text_dis ICON "bitmaps/text_dis.ico"
#include "wx/msw/wx.rc"
+#include "wx/html/msw/wxhtml.rc"
#include <shlobj.h>
#endif
#include "wx/msw/winundef.h"
-#ifdef CreateDirectory
+#if defined(CreateDirectory) && !defined(__CYGWIN__)
#undef CreateDirectory
#endif
#endif
//
// ----------------------------------------------------------------------------
// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
-// Copyright (C) 2003 John Dallaway
//
// This program is part of the eCos host tools.
//
//===========================================================================
//#####DESCRIPTIONBEGIN####
//
-// Author(s): julians, jld
+// Author(s): julians
// Contact(s): julians
// Date: 2001/04/04
// Version: $Id$
// packaged version doesn't
if (wxDirExists(docDir + sep + wxT("html")))
docDir = docDir + sep + wxString(wxT("html"));
-
+
wxString projectDir = FindIndexFilesDir(reposDir);
projectFile = projectDir + sep + wxT("eCos.hhp");
node = node->Next();
}
-// CreateHHCPackagesSection(wxT("Packages"), wxEmptyString, stream, docDir);
+ CreateHHCPackagesSection(wxT("Packages"), wxEmptyString, stream, docDir);
CreateHHCWriteFooter(stream);
}
wxString name(ecMakeNameFromPath(reposDir));
wxString ecosVerDir = ecosDir + sep + name;
- if (!wxDirExists(ecosVerDir))
+ if (!wxFileExists(ecosVerDir))
{
wxMkdir(ecosVerDir);
}
wxArrayString tutorials;
wxString sep(wxFILE_SEP_PATH);
-
+
wxString docDir(reposDir + sep + wxString(wxT("doc"))) ;
-
+
// The CVS repository has an HTML subdirectory, but the
// packaged version doesn't
if (wxDirExists(docDir + sep + wxT("html")))
wxLogNull log;
wxDir dir(docDir);
-
+
if (dir.IsOpened())
{
wxString filename;
{
if (filename != wxT(".") && filename != wxT(".."))
tutorials.Add(filename);
-
+
cont = dir.GetNext(& filename);
}
}
-// AddStartSection(wxT("Getting Started with eCos"), wxT(""));
+ AddStartSection(wxT("Getting Started with eCos"), wxT(""));
size_t i;
for (i = 0; i < tutorials.GetCount(); i++)
{
// Use a more friendly name than just the directory if it's available
AddIndexByList(TranslateTutorialDirectory(tutorial), tutorialRelativePath, tutorialRelativePath);
}
-// AddEndSection();
+ AddEndSection();
- AddIndexByList(wxT("User Guide"), wxT("user-guide/ecos-user-guide.html"), wxT("user-guide/ecos-user-guide.html"));
-// AddIndexByList(wxT("RedBoot User's Guide"), wxT("redboot/redboot.html"), wxT("redboot/redboot.html"));
-#ifdef __WXGTK__
- // FIXME: wxHtmlParser (version 2.4.0) doesn't like the eCos Reference HTML on Linux so just index the initial page for now
- AddIndexItem(wxT("eCos Reference"), wxT("ref/ecos-ref.html"));
-#else
- AddIndexByList(wxT("eCos Reference"), wxT("ref/ecos-ref.html"), wxT("ref/ecos-ref.html"));
-#endif
- AddIndexByList(wxT("Component Writer's Guide"), wxT("cdl-guide/cdl-guide.html"), wxT("cdl-guide/cdl-guide.html"));
-// AddIndexByList(wxT("eCos-EL/IX Compatibility Guide"), wxT("ecos-elix/elix-compatibility.html"), wxT("ecos-elix/elix-compatibility.html"));
+ AddIndexByList(wxT("eCos User's Guide"), wxT("guides/ecos-user-guide.html"), wxT("guides/ecos-user-guide.html"));
+ AddIndexByList(wxT("RedBoot User's Guide"), wxT("redboot/redboot.html"), wxT("redboot/redboot.html"));
+ AddIndexByList(wxT("eCos Component Writer's Guide"), wxT("cdl/cdl-guide.html"), wxT("cdl/cdl-guide.html"));
+ AddIndexByList(wxT("eCos Reference Manual"), wxT("ref/ecos-reference-manual.html"), wxT("ref/ecos-reference-manual.html"));
+ AddIndexByList(wxT("eCos-EL/IX Compatibility Guide"), wxT("ecos-elix/elix-compatibility.html"), wxT("ecos-elix/elix-compatibility.html"));
//// TOOLCHAIN REFERENCE MANUALS
-// AddStartSection(wxT("GNUPro Toolkit Reference Manual"));
+ AddStartSection(wxT("GNUPro Toolkit Reference Manual"));
// Start at indent 1 to avoid a spurious level
-// AddIndexByClass(wxT("ARM"), wxT("ref/gnupro-ref/arm/ARM_COMBO_front.html"), wxT("ref/gnupro-ref/arm/ARM_COMBOTOC.html"), 1);
-// AddIndexByClass(wxT("Fujitsu SPARClite"), wxT("ref/gnupro-ref/sparclite/index.html"), wxT("ref/gnupro-ref/sparclite/index.html"), 1);
-// AddIndexByClass(wxT("Matsushita MN10300"), wxT("ref/gnupro-ref/mn10300/am33_front.html"), wxT("ref/gnupro-ref/mn10300/am33toc.html"), 1);
-// AddIndexByClass(wxT("PowerPC"), wxT("ref/gnupro-ref/powerpc/index.html"), wxT("ref/gnupro-ref/powerpc/index.html"));
-// AddIndexByClass(wxT("Toshiba MIPS TX39"), wxT("/gnupro-ref/tx39/index.html"), wxT("/gnupro-ref/tx39/index.html"));
-
+ AddIndexByClass(wxT("ARM"), wxT("ref/gnupro-ref/arm/ARM_COMBO_front.html"), wxT("ref/gnupro-ref/arm/ARM_COMBOTOC.html"), 1);
+ AddIndexByClass(wxT("Fujitsu SPARClite"), wxT("ref/gnupro-ref/sparclite/index.html"), wxT("ref/gnupro-ref/sparclite/index.html"), 1);
+ AddIndexByClass(wxT("Matsushita MN10300"), wxT("ref/gnupro-ref/mn10300/am33_front.html"), wxT("ref/gnupro-ref/mn10300/am33toc.html"), 1);
+ AddIndexByClass(wxT("PowerPC"), wxT("ref/gnupro-ref/powerpc/index.html"), wxT("ref/gnupro-ref/powerpc/index.html"));
+ AddIndexByClass(wxT("Toshiba MIPS TX39"), wxT("/gnupro-ref/tx39/index.html"), wxT("/gnupro-ref/tx39/index.html"));
+
// Don't parse HTML, just add this item, if the page exists.
// Presumably the HTML can't be parsed for some reason.
-// AddIndexItem(wxT("Toshiba MIPS TX49"), wxT("ref/gnupro-ref/tx49/tx49_ref.html"));
-
-// AddIndexByClass(wxT("Hitachi SuperH"), wxT("ref/gnupro-ref/sh/SH_front.html"), wxT("ref/gnupro-ref/sh/SHTOC.html"), 1);
-
-// AddIndexItem(wxT("NEC V850"), wxT("ref/gnupro-ref/v850/v850_ref_3.html"));
-// AddIndexByClass(wxT("NEC VR4300"), wxT("ref/gnupro-ref/vr4300/Vr43REF_front.html"), wxT("ref/gnupro-ref/vr4300/Vr43REFTOC.html"), 1);
-// AddEndSection();
+ AddIndexItem(wxT("Toshiba MIPS TX49"), wxT("ref/gnupro-ref/tx49/tx49_ref.html"));
+
+ AddIndexByClass(wxT("Hitachi SuperH"), wxT("ref/gnupro-ref/sh/SH_front.html"), wxT("ref/gnupro-ref/sh/SHTOC.html"), 1);
+
+ AddIndexItem(wxT("NEC V850"), wxT("ref/gnupro-ref/v850/v850_ref_3.html"));
+ AddIndexByClass(wxT("NEC VR4300"), wxT("ref/gnupro-ref/vr4300/Vr43REF_front.html"), wxT("ref/gnupro-ref/vr4300/Vr43REFTOC.html"), 1);
+ AddEndSection();
}
DoIndexDocs(reposDir, projectFile, force);
-
+
return TRUE;
}
#endif
// include winsock2.h early to eliminate fd_set warning
-// FIXME: including winsock2.h early causes build failures
-// relating to the CreateDialog macro defined in the w32api.
-// Need to find a better point to #include <winsock2.h>
-//#ifdef __CYGWIN__
-//#include <winsock2.h>
-//#endif
+#ifdef __CYGWIN__
+#include <winsock2.h>
+#endif
#include "wx/wx.h"
#include "wx/splitter.h"
//
// ----------------------------------------------------------------------------
// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
-// Copyright (C) 2003 John Dallaway
//
// This program is part of the eCos host tools.
//
//===========================================================================
//#####DESCRIPTIONBEGIN####
//
-// Author(s): sdf, jld
+// Author(s): sdf
// Contact(s): sdf
// Date: 1998/08/11
// Version: 0.01
#include <tlhelp32.h>
#endif
-#ifdef __CYGWIN__
-#include <sys/cygwin.h> /* for cygwin_conv_to_*_path() */
-#endif
-
#if 0
#define INCLUDEFILE <string>
}
#endif
-const wxString ecUtils::NativeToPosixPath(const wxString & native)
-{
-#ifdef __CYGWIN__
- if (native.IsEmpty())
- return native;
- else
- {
- wxString posix;
- cygwin_conv_to_posix_path(native.c_str(), posix.GetWriteBuf(MAXPATHLEN + 1));
- posix.UngetWriteBuf();
- return posix;
- }
-#else
- return native;
-#endif
-}
-
-const wxString ecUtils::PosixToNativePath(const wxString & posix)
-{
-#ifdef __CYGWIN__
- if (posix.IsEmpty())
- return posix;
- else
- {
- wxString native;
- cygwin_conv_to_win32_path(posix.c_str(), native.GetWriteBuf(MAXPATHLEN + 1));
- native.UngetWriteBuf();
- return native;
- }
-#else
- return posix;
-#endif
-}
-
bool ecUtils::AddToPath(const ecFileName & strFolder, bool bAtFront)
{
wxString strPath,strOldPath;
//
// ----------------------------------------------------------------------------
// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
-// Copyright (C) 2003 John Dallaway
//
// This program is part of the eCos host tools.
//
//===========================================================================
//#####DESCRIPTIONBEGIN####
//
-// Author(s): sdf, jld
+// Author(s): sdf
// Contact(s): sdf
// Date: 1998/08/11
// Version: 0.01
static wxString GetLastErrorMessageString ();
#endif
- static const wxString PosixToNativePath(const wxString & posix);
- static const wxString NativeToPosixPath(const wxString & native);
static bool AddToPath (const ecFileName &strFolder, bool bAtFront=true);
#if 0
#include <shlwapi.h>
#include "wx/msw/winundef.h"
+#ifndef __CYGWIN__
#ifdef CreateDirectory
#undef CreateDirectory
#endif
#ifdef GetTempPath
#undef GetTempPath
#endif
+#endif
#else
#include "folderdlg.h"
#include "reposdlg.h"
#include "docsystem.h"
-#include "symbols.h"
#ifdef __WXMSW__
#include "wx/msw/winundef.h"
{
// ecAboutDialog dialog(this, ecID_ABOUT_DIALOG, _("About eCos Configuration Tool"));
// dialog.ShowModal();
- wxString msg;
- msg.Printf("eCos Configuration Tool %s (%s %s)\n\nCopyright (c) Red Hat, Inc. 1998-2002\nCopyright (c) John Dallaway 2003", ecCONFIGURATION_TOOL_VERSION, __DATE__, __TIME__);
- wxMessageBox(msg, _("About eCos Configuration Tool"), wxICON_INFORMATION | wxOK);
+ wxMessageBox(_("eCos Configuration Tool 2.12.net (eCos 2.0b1)\n\nCopyright (c) Red Hat, Inc. 1998-2002\nCopyright (c) John Dallaway 2003"), _("About eCos Configuration Tool"), wxICON_INFORMATION | wxOK);
}
void ecMainFrame::OnSize(wxSizeEvent& WXUNUSED(event))
if (!doc)
return;
- // add the current build tools dir to the drop-down list box
+ // Add all the paths from the bin dirs to the path array,
+ // making the default path the appropriate target prefix
+ wxString defaultPath;
+ const wxString strPrefix(doc->GetCurrentTargetPrefix());
wxArrayString arstrPaths;
- if (!wxGetApp().GetSettings().m_buildToolsDir.IsEmpty())
- arstrPaths.Add(wxGetApp().GetSettings().m_buildToolsDir);
- // also add the sub-directory containing tools for the current command prefix
- wxString value;
wxStringToStringMap& map = wxGetApp().GetSettings().GetBinDirs();
- const wxString strPrefix(doc->GetCurrentTargetPrefix());
- if (map.Find(strPrefix, value) && (wxNOT_FOUND == arstrPaths.Index(value)))
+ map.BeginFind();
+ wxString key, value;
+ bool hasDefaultDir = FALSE;
+ while (map.Next(key, value))
+ {
arstrPaths.Add(value);
-
+ if (key == strPrefix)
+ defaultPath = value;
+ if (value == wxGetApp().GetSettings().m_buildToolsDir)
+ hasDefaultDir = TRUE;
+ }
+ if (!wxGetApp().GetSettings().m_buildToolsDir.IsEmpty() && !hasDefaultDir)
+ {
+ arstrPaths.Add(wxGetApp().GetSettings().m_buildToolsDir);
+ }
+
wxString msg;
msg.Printf(_("Enter the location of the %s build tools\n"
- "folder. You can type in a path or use the\n"
- "Browse button to navigate to a folder."),
- (const wxChar*) (strPrefix.IsEmpty() ? wxString(wxT("native")) : strPrefix));
+ "folder, which should contain %sgcc. You can\n"
+ "type in a path or use the Browse button to\n"
+ "navigate to a folder."),
+ (const wxChar*) (strPrefix.IsEmpty() ? wxString(wxT("native")) : strPrefix),
+ (const wxChar*) (strPrefix.IsEmpty() ? wxString(wxT("")) : strPrefix + wxT("-"))
+ );
wxString caption(_("Build Tools Path"));
- ecFolderDialog dialog(wxGetApp().GetSettings().m_buildToolsDir, arstrPaths, msg, this, ecID_BUILD_TOOLS_DIALOG, caption);
+ ecFolderDialog dialog(defaultPath, arstrPaths, msg, this, ecID_BUILD_TOOLS_DIALOG, caption);
if (dialog.ShowModal() == wxID_OK)
{
- wxString path (dialog.GetPath());
+ ecFileName strExe;
- // look for *objcopy under the user-specified build tools directory
- wxArrayString objcopyFiles;
- wxString objcopyFileSpec(wxT("objcopy"));
#ifdef __WXMSW__
- objcopyFileSpec += wxT(".exe");
+ wxString exeSuffix(wxT(".exe"));
+#else
+ wxString exeSuffix(wxEmptyString);
#endif
- size_t objcopyCount = wxDir::GetAllFiles(path, &objcopyFiles, wxT("*") + objcopyFileSpec, wxDIR_FILES | wxDIR_DIRS);
- bool bPrefixFound = false;
- for (int count=0; count < objcopyCount; count++)
- {
- wxFileName file (objcopyFiles [count]);
- wxString new_prefix (file.GetFullName().Left (file.GetFullName().Find(objcopyFileSpec)));
- if ((! new_prefix.IsEmpty()) && ('-' == new_prefix.Last()))
- new_prefix = new_prefix.Left (new_prefix.Len() - 1); // strip off trailing hyphen
- if (new_prefix == strPrefix)
- bPrefixFound = true;
- }
+ wxString path(dialog.GetPath());
+ strExe.Printf(wxT("%s%c%s%sgcc%s"), (const wxChar*) path, wxFILE_SEP_PATH, (const wxChar*) strPrefix,
+ (const wxChar*) strPrefix.IsEmpty() ? wxT("") : wxT("-"), (const wxChar*) exeSuffix);
wxString msg;
msg.Printf(wxT("%s does not appear to contain the build tools - use this folder anyway?"), (const wxChar*) path);
- if(bPrefixFound ||
- (wxYES == wxMessageBox(msg, wxGetApp().GetSettings().GetAppName(), wxICON_QUESTION|wxYES_NO)))
+ if(strExe.Exists() ||
+ (wxID_YES == wxMessageBox(msg, wxGetApp().GetSettings().GetAppName(), wxICON_QUESTION|wxYES_NO)))
{
- for (int count=0; count < objcopyCount; count++)
- {
- wxFileName file (objcopyFiles [count]);
- wxString new_prefix (file.GetFullName().Left (file.GetFullName().Find(objcopyFileSpec)));
- if ((! new_prefix.IsEmpty()) && ('-' == new_prefix.Last()))
- new_prefix = new_prefix.Left (new_prefix.Len() - 1); // strip off trailing hyphen
- map.Set(new_prefix, file.GetPath(wxPATH_GET_VOLUME));
- }
- wxGetApp().GetSettings().m_buildToolsDir = path;
+ map.Set(strPrefix, path);
+ if (!hasDefaultDir)
+ wxGetApp().GetSettings().m_buildToolsDir = path;
}
}
}
msg.Printf(wxT("%s does not appear to contain the user tools - use this folder anyway?"), (const wxChar*) path);
if(strFile.Exists() ||
- (wxYES == wxMessageBox(msg, wxGetApp().GetSettings().GetAppName(), wxICON_QUESTION|wxYES_NO)))
+ (wxID_YES == wxMessageBox(msg, wxGetApp().GetSettings().GetAppName(), wxICON_QUESTION|wxYES_NO)))
{
wxGetApp().GetSettings().m_userToolsDir = path;
}
if (& event == s_lastEvent)
return FALSE;
- if (event.IsCommandEvent() && !event.IsKindOf(CLASSINFO(wxChildFocusEvent)))
+ if (event.IsCommandEvent())
{
s_lastEvent = & event;
# Usage:
# cd emptydir
-# make -f /path/to/this/makefile WXDIR=/path/to/wx/installation INSTALLDIR=/path/to/ecos/tools [ ECOSSRCDIR=/path/to/ecos/tools/src ] [ TCLDIR=/path/to/tcl/installation ] [ DEBUG=1 ]
+# make -f /path/to/this/makefile WXDIR=/path/to/wx/installation ECOSSRCDIR=/path/to/ecos/tools/src OSTYPE=$OSTYPE
-INSTALLDIR=INSTALLDIR_not_defined
+TCLDIR=TCLDIR_not_defined
WXDIR=WXDIR_not_defined
+ECOSSRCDIR=ECOSSRCDIR_not_defined
CTBUILDDIR=$(shell pwd)
-ECOSSRCDIR=$(INSTALLDIR)/src
CTDIR=$(ECOSSRCDIR)/tools/configtool/standalone/wxwin
-TCLDIR=TCLDIR_use_system
+INSTALLDIR=$(ECOSSRCDIR)/..
+LEVEL=release
USEEXPERIMENTALCODE=1
EXTRACPPFLAGS=\
-DecUSE_EXPERIMENTAL_CODE=$(USEEXPERIMENTALCODE)
EXTRALDFLAGS=-L$(TCLDIR)/lib -L$(INSTALLDIR)/lib -lcdl -lcyginfra -ltcl
-ifneq (,$(findstring CYGWIN, $(shell uname)))
+ifeq "$(OSTYPE)" "cygwin"
PROGRAM=configtool.exe
- CPPFLAGS=`$(WXDIR)/bin/wx-config --cppflags` -D_WIN32 -D__WIN32__ -DSTRICT
- LDFLAGS=`$(WXDIR)/bin/wx-config --libs` -lshlwapi -Wl,--subsystem,windows
+ CPPFLAGS=-I$(WXDIR)/include -I$(WXDIR)/lib/wx/include -DSTRICT -DWINVER=0x0400 -D_WIN32 -D__GNUWIN32__ -D__WIN95__ -D__WIN32__ -D_X86_=1 -DWIN32
+ LDFLAGS=-L$(WXDIR)/lib -lwx -lstdc++ -lwinspool -lwinmm -lshell32 -lcomctl32 -lctl3d32 -ladvapi32 -lwsock32 -lglu32 -lgdi32 -lcomdlg32 -lole32 -luuid -lshlwapi -lpng -lzlib
EXTRAOBJECTS=$(CTBUILDDIR)/configtoolres.o
else
PROGRAM=configtool
- CPPFLAGS=`$(WXDIR)/bin/wx-config --cppflags`
- LDFLAGS=`$(WXDIR)/bin/wx-config --libs`
+ CPPFLAGS=-I$(WXDIR)/include -I$(WXDIR)/lib/wx/include -DGTK_NO_CHECK_CASTS -D__WXGTK__ -D__USE_WXCONFIG__
+ LDFLAGS=-L$(WXDIR)/lib -L/usr/X11R6/lib -lwx_gtk -lgtk -lgdk -rdynamic -lgmodule -lgthread -lglib -lpthread -ldl -lXi -lXext -lX11 -lm
EXTRAOBJECTS=
endif
-ifeq "$(DEBUG)" ""
+ifneq "$(LEVEL)" "debug"
CPPDEBUGOPTIONS=-O2
else
- CPPDEBUGOPTIONS=-ggdb
+ CPPDEBUGOPTIONS=-D__WXDEBUG__ -ggdb
endif
OBJECTS = \
$(CC) $(CPPDEBUGOPTIONS) -c $(EXTRACPPFLAGS) $(CPPFLAGS) -o $@ $<
$(CTBUILDDIR)/configtoolres.o: $(CTDIR)/configtool.rc
- $(RESCOMP) -i $< -o $@ --preprocessor "$(CC) -c -E -xc-header -DRC_INVOKED" --include-dir $(WXDIR)/include --include-dir $(CTDIR) --define __GNUWIN32__
+ $(RESCOMP) -i $< -o $@ --preprocessor "$(CC) -c -E -xc-header -DRC_INVOKED" --include-dir $(WXDIR)/include --include-dir $(CTDIR) --define __WIN32__ --define __WIN95__ --define __GNUWIN32__
clean:
rm -f $(CTBUILDDIR)/$(PROGRAM) $(CTBUILDDIR)/*.o
//
// ----------------------------------------------------------------------------
// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
-// Copyright (C) 2003 John Dallaway
//
// This program is part of the eCos host tools.
//
//===========================================================================
//#####DESCRIPTIONBEGIN####
//
-// Author(s): julians, jld
+// Author(s): julians
// Contact(s): julians
// Date: 2000/09/28
// Version: $Id$
wxSizer *item1 = new wxBoxSizer( wxHORIZONTAL );
wxSizer *item2 = new wxBoxSizer( wxVERTICAL );
-
+
wxStaticText *item3 = new wxStaticText( parent, wxID_STATIC, _("Available &packages:"), wxDefaultPosition, wxDefaultSize, 0 );
item2->Add( item3, 0, wxALIGN_CENTER_VERTICAL|wxALL, 5 );
wxButton *item7 = new wxButton( parent, ecID_PACKAGES_DIALOG_REMOVE, _("<< &Remove"), wxDefaultPosition, wxDefaultSize, 0 );
item5->Add( item7, 0, wxALIGN_CENTRE|wxALL, 5 );
-
+
item1->Add( item5, 0, wxALIGN_CENTRE|wxALL, 0 );
wxSizer *item8 = new wxBoxSizer( wxVERTICAL );
wxButton *item20 = new wxButton( parent, wxID_OK, _("&OK"), wxDefaultPosition, wxDefaultSize, 0 );
item20->SetDefault();
item18->Add( item20, 0, wxALIGN_CENTRE|wxALL, 5 );
-
+
wxButton *item21 = new wxButton( parent, wxID_CANCEL, _("&Cancel"), wxDefaultPosition, wxDefaultSize, 0 );
item18->Add( item21, 0, wxALIGN_CENTRE|wxALL, 5 );
}
// Initialize the controls
- for (i = 0; i < GetCount(); i++)
+ for (i = 0; i < GetCount()-1; i++)
{
const wxString& str = m_items[i];
wxListBox* lb = m_arnItems[i] ? useList : availableList;
ecRunTestsDialog* pWnd = (ecRunTestsDialog*)pParam;
if (ecRunTestsDialog::m_runTestsDialog)
{
- // FIXME: test output should not contain CR characters on non-Windows
- // platforms so need to find the root of this problem
-#ifndef __WXMSW__
- wxString output(psz);
- output.Replace(wxT("\r"), wxEmptyString); // remove CR characters
- pWnd->OutputToBuffer(output);
-#else
- // FIXME ends
pWnd->OutputToBuffer(psz);
-#endif
}
}
{
wxSizer *item0 = new wxBoxSizer( wxVERTICAL );
- wxTextCtrl *item1 = new wxTextCtrl( parent, ecID_RUN_TESTS_OUTPUT_TEXT, "", wxDefaultPosition, wxSize(80,40), wxTE_MULTILINE|wxTE_READONLY|wxTE_RICH|wxCLIP_CHILDREN );
+ wxTextCtrl *item1 = new wxTextCtrl( parent, ecID_RUN_TESTS_OUTPUT_TEXT, "", wxDefaultPosition, wxSize(80,40), wxTE_MULTILINE );
item0->Add( item1, 1, wxGROW|wxALIGN_CENTER_VERTICAL|wxALL, 5 );
// Add context-sensitive help
wxRemotelyScrolledTreeCtrl::wxRemotelyScrolledTreeCtrl(wxWindow* parent, wxWindowID id, const wxPoint& pt,
const wxSize& sz, long style):
wxTreeCtrl(parent, id, pt, sz, style
-#if wxVERSION_NUMBER > 2301
+#if wxVERSON_NUMBER > 2301
& ~wxTR_ROW_LINES
-#endif
+#endif
)
{
m_companionWindow = NULL;
if (IsKindOf(CLASSINFO(wxGenericTreeCtrl)))
{
wxGenericTreeCtrl* win = (wxGenericTreeCtrl*) this;
- // Pass TRUE for noRefresh so that it doesn't
- // draw part of the tree as if the scroll view is
- // at zero vertically.
- win->wxGenericTreeCtrl::SetScrollbars(pixelsPerUnitX, pixelsPerUnitY, noUnitsX, 0, xPos, 0, /* noRefresh */ TRUE);
+ win->wxGenericTreeCtrl::SetScrollbars(pixelsPerUnitX, 0, noUnitsX, 0, xPos, 0, noRefresh);
ecScrolledWindow* scrolledWindow = GetScrolledWindow();
if (scrolledWindow)
//
// ----------------------------------------------------------------------------
// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
-// Copyright (C) 2003 John Dallaway
//
// This program is part of the eCos host tools.
//
//
//===========================================================================
-#define ecCONFIGURATION_TOOL_VERSION "2.0"
+#define ecCONFIGURATION_TOOL_VERSION 2.12
// Use /ecos-x notation for drive specification
#define ecUSE_ECOS_X_NOTATION 1
-2003-04-11 John Dallaway <jld@ecoscentric.com>
-
- * common/eCosTestPlatform.cpp (CeCosTestPlatform::Load): Return
- true since it's not a problem if there are no platforms defined.
-
- * unix/Makefile: Allow ser_filter to build under Cygwin.
-
2003-02-21 John Dallaway <jld@ecoscentric.com>
* common/eCosTestPlatform.cpp (CeCosTestPlatform::Load): Allow an
const String strDir(CeCosTestUtils::HomeFile(_T(".eCosPlatforms")));
#ifdef _WIN32
if(!CeCosTestUtils::Exists(strDir)){
- return true;
+ return rc;
}
#endif
LoadFromDir(strDir);
CXX=g++
-ifneq (,$(findstring CYGWIN, $(shell uname)))
-LIBS := -lwsock32
-endif
-
-ifneq (, $(findstring SunOS, $(shell uname)))
-LIBS := -lpthread -lsocket -lxnet -lstdc++ -lposix4
-endif
-
-ifneq (, $(findstring Linux, $(shell uname)))
-LIBS := -lpthread -efence -lstdc++
+ifeq ($(shell uname), SunOS)
+# SunOS
+LIBS := -lpthread -lsocket -lxnet -lstdc++ -lposix4
+else
+# Linux
+LIBS := -lpthread -efence -lstdc++
endif
# Look in these directories for source/make files
all: $(programs)
ser_filter: $(common_objects) ser_filter.o
- $(CXX) -o $@ $(CXXFLAGS) $^ $(LIBPATH) $(LIBS)
+ $(CXX) -o $@ $(CXXFLAGS) $(LIBPATH) $(LIBS) $^
.PHONY: clean
projects / karo-tx-redboot.git / commitdiff