*/
#include <common.h>
+#include <div64.h>
+#include <ipu.h>
+#include <fuse.h>
+#include <thermal.h>
+#include <asm/armv7.h>
+#include <asm/bootm.h>
+#include <asm/pl310.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
+#include <asm/arch/regs-ocotp.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/dma.h>
#include <stdbool.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
+#include <dm.h>
+#include <imx_thermal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define __data __attribute__((section(".data")))
+
+#ifdef CONFIG_MX6_TEMPERATURE_MIN
+#define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
+#else
+#define TEMPERATURE_MIN (-40)
+#endif
+#ifdef CONFIG_MX6_TEMPERATURE_HOT
+#define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
+#else
+#define TEMPERATURE_HOT 80
+#endif
+#ifdef CONFIG_MX6_TEMPERATURE_MAX
+#define TEMPERATURE_MAX CONFIG_MX6_TEMPERATURE_MAX
+#else
+#define TEMPERATURE_MAX 125
+#endif
+#define TEMP_AVG_COUNT 5
+#define TEMP_WARN_THRESHOLD 5
enum ldo_reg {
LDO_ARM,
u32 fpga_rev;
};
+#if defined(CONFIG_IMX6_THERMAL)
+static const struct imx_thermal_plat imx6_thermal_plat = {
+ .regs = (void *)ANATOP_BASE_ADDR,
+ .fuse_bank = 1,
+ .fuse_word = 6,
+};
+
+U_BOOT_DEVICE(imx6_thermal) = {
+ .name = "imx_thermal",
+ .platdata = &imx6_thermal_plat,
+};
+#endif
+
+u32 get_nr_cpus(void)
+{
+ struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+ return readl(&scu->config) & 3;
+}
+
u32 get_cpu_rev(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
u32 reg = readl(&anatop->digprog_sololite);
u32 type = ((reg >> 16) & 0xff);
+ u32 major, cfg = 0;
if (type != MXC_CPU_MX6SL) {
reg = readl(&anatop->digprog);
+ struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+ cfg = readl(&scu->config) & 3;
type = ((reg >> 16) & 0xff);
if (type == MXC_CPU_MX6DL) {
- struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
- u32 cfg = readl(&scu->config) & 3;
-
if (!cfg)
type = MXC_CPU_MX6SOLO;
}
+
+ if (type == MXC_CPU_MX6Q) {
+ if (cfg == 1)
+ type = MXC_CPU_MX6D;
+ }
+
+ }
+ major = ((reg >> 8) & 0xff);
+ if ((major >= 1) &&
+ ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
+ major--;
+ type = MXC_CPU_MX6QP;
+ if (cfg == 1)
+ type = MXC_CPU_MX6DP;
}
reg &= 0xff; /* mx6 silicon revision */
- return (type << 12) | (reg + 0x10);
+ if (type == MXC_CPU_MX6Q) {
+ switch (reg) {
+ case 0x02:
+ break;
+ case 0x05:
+ reg = 0x03;
+ break;
+ case 0x06:
+ reg = 0x06;
+ break;
+ default:
+ printf("Unknown CPU Rev.: 0x%02x\n", reg);
+ }
+ }
+ return (type << 12) | (reg + (0x10 * (major + 1)));
+}
+
+/*
+ * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
+ * defines a 2-bit SPEED_GRADING
+ */
+#define OCOTP_CFG3_SPEED_SHIFT 16
+#define OCOTP_CFG3_SPEED_800MHZ 0
+#define OCOTP_CFG3_SPEED_850MHZ 1
+#define OCOTP_CFG3_SPEED_1GHZ 2
+#define OCOTP_CFG3_SPEED_1P2GHZ 3
+
+u32 get_cpu_speed_grade_hz(void)
+{
+ uint32_t val;
+
+ if (fuse_read(0, 3, &val)) {
+ printf("Failed to read speed_grade fuse\n");
+ return 0;
+ }
+ val >>= OCOTP_CFG3_SPEED_SHIFT;
+ val &= 0x3;
+
+ switch (val) {
+ /* Valid for IMX6DQ */
+ case OCOTP_CFG3_SPEED_1P2GHZ:
+ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ return 1200000000;
+ /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
+ case OCOTP_CFG3_SPEED_1GHZ:
+ return 996000000;
+ /* Valid for IMX6DQ */
+ case OCOTP_CFG3_SPEED_850MHZ:
+ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ return 852000000;
+ /* Valid for IMX6SX/IMX6SDL/IMX6DQ/IMX6ULL */
+ case OCOTP_CFG3_SPEED_800MHZ:
+ return 792000000;
+ }
+ return 0;
+}
+
+/*
+ * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
+ * defines a 2-bit Temperature Grade
+ *
+ * return temperature grade and min/max temperature in celcius
+ */
+#define OCOTP_MEM0_TEMP_SHIFT 6
+
+u32 get_cpu_temp_grade(int *minc, int *maxc)
+{
+ uint32_t val;
+
+ if (fuse_read(1, 0, &val)) {
+ printf("Failed to read temp_grade fuse\n");
+ val = 0;
+ }
+ val >>= OCOTP_MEM0_TEMP_SHIFT;
+ val &= 0x3;
+
+ if (minc && maxc) {
+ if (val == TEMP_AUTOMOTIVE) {
+ *minc = -40;
+ *maxc = 125;
+ } else if (val == TEMP_INDUSTRIAL) {
+ *minc = -40;
+ *maxc = 105;
+ } else if (val == TEMP_EXTCOMMERCIAL) {
+ *minc = -20;
+ *maxc = 105;
+ } else {
+ *minc = 0;
+ *maxc = 95;
+ }
+ }
+ return val;
}
#ifdef CONFIG_REVISION_TAG
if (type == MXC_CPU_MX6SOLO)
cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
+ if (type == MXC_CPU_MX6D)
+ cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
+
return cpurev;
}
#endif
void init_aips(void)
{
struct aipstz_regs *aips1, *aips2;
-
+#ifdef AIPS3_CONFIG_BASE_ADDR
+ struct aipstz_regs *aips3;
+#endif
aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
+#ifdef AIPS3_CONFIG_BASE_ADDR
+ aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
+#endif
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
writel(0x00000000, &aips2->opacr2);
writel(0x00000000, &aips2->opacr3);
writel(0x00000000, &aips2->opacr4);
+
+#ifdef AIPS3_CONFIG_BASE_ADDR
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ writel(0x77777777, &aips3->mprot0);
+ writel(0x77777777, &aips3->mprot1);
+
+ /*
+ * Set all OPACRx to be non-bufferable, not require
+ * supervisor privilege level for access,allow for
+ * write access and untrusted master access.
+ */
+ writel(0x00000000, &aips3->opacr0);
+ writel(0x00000000, &aips3->opacr1);
+ writel(0x00000000, &aips3->opacr2);
+ writel(0x00000000, &aips3->opacr3);
+ writel(0x00000000, &aips3->opacr4);
+#endif
}
static void clear_ldo_ramp(void)
}
/*
- * Set the VDDSOC
+ * Set the PMU_REG_CORE register
*
- * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
- * them to the specified millivolt level.
+ * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
* Possible values are from 0.725V to 1.450V in steps of
* 0.025V (25mV).
*/
return 0;
}
+int check_cpu_temperature(int boot)
+{
+ int ret;
+ static int __data max_temp;
+ int boot_limit = getenv_ulong("max_boot_temp", 10, TEMPERATURE_HOT);
+ int tmp;
+ struct udevice *dev;
+ bool first = true;
+
+ if (uclass_get_device_by_name(UCLASS_THERMAL, "imx_thermal", &dev)) {
+ if (first) {
+ printf("No thermal device found; cannot read CPU temperature\n");
+ first = false;
+ }
+ return 0;
+ }
+
+ ret = thermal_get_temp(dev, &tmp);
+ if (ret) {
+ printf("Failed to read temperature: %d\n", ret);
+ return TEMPERATURE_MAX;
+ }
+ if (tmp < TEMPERATURE_MIN || tmp > TEMPERATURE_MAX) {
+ printf("Temperature: can't get valid data!\n");
+ return tmp;
+ }
+
+ if (!boot) {
+ if (tmp > boot_limit) {
+ printf("CPU is %d C; too hot, resetting...\n", tmp);
+ udelay(100000);
+ reset_cpu(0);
+ }
+ if (tmp > max_temp) {
+ if (tmp > boot_limit - TEMP_WARN_THRESHOLD)
+ printf("WARNING: CPU temperature %d C\n", tmp);
+ max_temp = tmp;
+ }
+ } else {
+ while (tmp >= boot_limit) {
+ if (first) {
+ printf("CPU is %d C; too hot to boot, waiting...\n",
+ tmp);
+ first = false;
+ }
+ if (ctrlc())
+ break;
+ udelay(50000);
+ ret = thermal_get_temp(dev, &tmp);
+ if (ret < 0) {
+ printf("Failed to read temperature: %d\n", ret);
+ return TEMPERATURE_MAX;
+ }
+ if (tmp > boot_limit - TEMP_WARN_THRESHOLD && tmp != max_temp)
+ printf("WARNING: CPU temperature %d C\n", tmp);
+ max_temp = tmp;
+ }
+ }
+ return tmp;
+}
+
static void imx_set_wdog_powerdown(bool enable)
{
struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
+ struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
+
+ if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
+ is_cpu_type(MXC_CPU_MX6ULL))
+ writew(enable, &wdog3->wmcr);
/* Write to the PDE (Power Down Enable) bit */
writew(enable, &wdog1->wmcr);
(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
}
+static void clear_mmdc_ch_mask(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ u32 reg;
+ reg = readl(&mxc_ccm->ccdr);
+
+ /* Clear MMDC channel mask */
+ reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+ writel(reg, &mxc_ccm->ccdr);
+}
+
+static void init_bandgap(void)
+{
+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ /*
+ * Ensure the bandgap has stabilized.
+ */
+ while (!(readl(&anatop->ana_misc0) & 0x80))
+ ;
+ /*
+ * For best noise performance of the analog blocks using the
+ * outputs of the bandgap, the reftop_selfbiasoff bit should
+ * be set.
+ */
+ writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
+}
+
+#ifdef CONFIG_SOC_MX6SL
+static void set_preclk_from_osc(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ u32 reg;
+
+ reg = readl(&mxc_ccm->cscmr1);
+ reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
+ writel(reg, &mxc_ccm->cscmr1);
+}
+#endif
+
+#define SRC_SCR_WARM_RESET_ENABLE 0
+
+static void init_src(void)
+{
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ u32 val;
+
+ /*
+ * force warm reset sources to generate cold reset
+ * for a more reliable restart
+ */
+ val = readl(&src_regs->scr);
+ val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
+ writel(val, &src_regs->scr);
+}
+
int arch_cpu_init(void)
{
init_aips();
+ /* Need to clear MMDC_CHx_MASK to make warm reset work. */
+ clear_mmdc_ch_mask();
+
+ /*
+ * Disable self-bias circuit in the analog bandap.
+ * The self-bias circuit is used by the bandgap during startup.
+ * This bit should be set after the bandgap has initialized.
+ */
+ init_bandgap();
+
/*
* When low freq boot is enabled, ROM will not set AHB
* freq, so we need to ensure AHB freq is 132MHz in such
if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
set_ahb_rate(132000000);
+ /* Set perclk to source from OSC 24MHz */
+#if defined(CONFIG_SOC_MX6SL)
+ set_preclk_from_osc();
+#endif
+
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
-#ifdef CONFIG_APBH_DMA
- /* Start APBH DMA */
+#ifdef CONFIG_VIDEO_IPUV3
+ gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3H;
+#endif
+#ifdef CONFIG_APBH_DMA
+ /* Timer is required for Initializing APBH DMA */
+ timer_init();
mxs_dma_init();
#endif
+ init_src();
+
return 0;
}
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+ enum dcache_option option = DCACHE_WRITETHROUGH;
+#else
+ enum dcache_option option = DCACHE_WRITEBACK;
+#endif
+
/* Avoid random hang when download by usb */
invalidate_dcache_all();
+
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
+
+ /* Enable caching on OCRAM and ROM */
+ mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
+ ROMCP_ARB_END_ADDR,
+ option);
+ mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
+ IRAM_SIZE,
+ option);
}
#endif
#if defined(CONFIG_FEC_MXC)
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+__weak void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- struct fuse_bank *bank = &ocotp->bank[4];
- struct fuse_bank4_regs *fuse =
- (struct fuse_bank4_regs *)bank->fuse_regs;
-
- u32 value = readl(&fuse->mac_addr_high);
- mac[0] = (value >> 8);
- mac[1] = value ;
+ unsigned int mac0, mac1;
- value = readl(&fuse->mac_addr_low);
- mac[2] = value >> 24 ;
- mac[3] = value >> 16 ;
- mac[4] = value >> 8 ;
- mac[5] = value ;
+ memset(mac, 0, 6);
+ if (dev_id < 0 || dev_id > 2)
+ return;
+ if (fuse_read(4, 2, &mac0)) {
+ printf("Failed to read MAC0 fuse\n");
+ return;
+ }
+ if (fuse_read(4, 3, &mac1)) {
+ printf("Failed to read MAC1 fuse\n");
+ return;
+ }
+ mac[0] = mac1 >> 8;
+ mac[1] = mac1;
+ mac[2] = mac0 >> 24;
+ mac[3] = mac0 >> 16;
+ if (dev_id == 0) {
+ mac[4] = mac0 >> 8;
+ mac[5] = mac0;
+ } else {
+ mac[4] = mac1 >> 24;
+ mac[5] = mac1 >> 16;
+ }
}
#endif
/*
* cfg_val will be used for
* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
- * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
- * to SBMR1, which will determine the boot device.
+ * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
+ * instead of SBMR1 to determine the boot device.
*/
const struct boot_mode soc_boot_modes[] = {
{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
/* reserved value should start rom usb */
{"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
{"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
- {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
- {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
- {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
- {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
+ {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
+ {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
+ {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
+ {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
/* 4 bit bus width */
{"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
{"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
void s_init(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- int is_6q = is_cpu_type(MXC_CPU_MX6Q);
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
u32 mask480;
u32 mask528;
+ u32 reg, periph1, periph2;
+
+ if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
+ is_cpu_type(MXC_CPU_MX6ULL))
+ return;
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
* to make sure PFD is working right, otherwise, PFDs may
ANATOP_PFD_CLKGATE_MASK(1) |
ANATOP_PFD_CLKGATE_MASK(2) |
ANATOP_PFD_CLKGATE_MASK(3);
- mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
- ANATOP_PFD_CLKGATE_MASK(1) |
+ mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
ANATOP_PFD_CLKGATE_MASK(3);
- /*
- * Don't reset PFD2 on DL/S
- */
- if (is_6q)
+ reg = readl(&ccm->cbcmr);
+ periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
+ >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
+ periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
+ >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
+
+ /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
+ if ((periph2 != 0x2) && (periph1 != 0x2))
+ mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
+
+ if ((periph2 != 0x1) && (periph1 != 0x1) &&
+ (periph2 != 0x3) && (periph1 != 0x3))
mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
+
writel(mask480, &anatop->pfd_480_set);
writel(mask528, &anatop->pfd_528_set);
writel(mask480, &anatop->pfd_480_clr);
writel(reg, &mxc_ccm->chsccdr);
}
#endif
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
+void v7_outer_cache_enable(void)
+{
+ struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+ unsigned int val;
+
+
+ /*
+ * Set bit 22 in the auxiliary control register. If this bit
+ * is cleared, PL310 treats Normal Shared Non-cacheable
+ * accesses as Cacheable no-allocate.
+ */
+ setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+#if defined CONFIG_SOC_MX6SL
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ val = readl(&iomux->gpr[11]);
+ if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
+ /* L2 cache configured as OCRAM, reset it */
+ val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
+ writel(val, &iomux->gpr[11]);
+ }
+#endif
+
+ /* Must disable the L2 before changing the latency parameters */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
+ writel(0x132, &pl310->pl310_tag_latency_ctrl);
+ writel(0x132, &pl310->pl310_data_latency_ctrl);
+
+ val = readl(&pl310->pl310_prefetch_ctrl);
+
+ /* Turn on the L2 I/D prefetch */
+ val |= 0x30000000;
+
+ /*
+ * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
+ * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
+ * But according to ARM PL310 errata: 752271
+ * ID: 752271: Double linefill feature can cause data corruption
+ * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
+ * Workaround: The only workaround to this erratum is to disable the
+ * double linefill feature. This is the default behavior.
+ */
+
+#ifndef CONFIG_SOC_MX6Q
+ val |= 0x40800000;
+#endif
+ writel(val, &pl310->pl310_prefetch_ctrl);
+
+ val = readl(&pl310->pl310_power_ctrl);
+ val |= L2X0_DYNAMIC_CLK_GATING_EN;
+ val |= L2X0_STNDBY_MODE_EN;
+ writel(val, &pl310->pl310_power_ctrl);
+
+ setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+void v7_outer_cache_disable(void)
+{
+ struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+#endif /* !CONFIG_SYS_L2CACHE_OFF */