am33xx: Re-enable SW levelling for DDR2

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / omap-common / clocks-common.c

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index fa04bbedf9ea780841f7b96fc37d79f2351581ee..c94a807819310fb2a3b00e7a79d45ce3074a3eb0 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -372,6 +372,7 @@ static void setup_dplls(void)
 {
        u32 temp;
        const struct dpll_params *params;
+       struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
 
        debug("setup_dplls\n");
 
@@ -382,7 +383,8 @@ static void setup_dplls(void)
         * Core DPLL will be locked after setting up EMIF
         * using the FREQ_UPDATE method(freq_update_core())
         */
-       if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
+       if (emif_sdram_type(readl(&emif->emif_sdram_config)) ==
+           EMIF_SDRAM_TYPE_LPDDR2)
                do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
                                                        DPLL_NO_LOCK, "core");
        else