ARM: DRA7: Enable clocks for USB OTGSS2 and USB PHY2

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / omap5 / hw_data.c

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index a2d9cc8e646ecf9d2d1b2a8f5ebd0558d30b28e3..e0ee23f3d1fa3f8d5801ba0eb7a3896e7373c08b 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -463,6 +463,9 @@ void enable_basic_clocks(void)
 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
                (*prcm)->cm_l3init_ocp2scp1_clkctrl,
                (*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+               (*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
+#endif
 #endif
                0
        };
@@ -503,6 +506,19 @@ void enable_basic_clocks(void)
        /* Enable 32 KHz clock for dwc3 */
        setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
                     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+       /* Enable 960 MHz clock for dwc3 */
+       setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
+                    OPTFCLKEN_REFCLK960M);
+
+       /* Enable 32 KHz clock for dwc3 */
+       setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
+                    USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+       /* Enable 60 MHz clock for USB2PHY2 */
+       setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
+                    L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
+#endif
 #endif
 
        /* Set the correct clock dividers for mmc */