karo: merge with Ka-Ro specific tree for secure boot support

[karo-tx-uboot.git] / arch / arm / include / asm / arch-mx5 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index b38a40caefd76b8715104b1148ff521c7b3b9fbd..091055f8f07fb723f9fbb07a3acc802bcd008059 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -12,7 +12,6 @@
 #if defined(CONFIG_MX51)
 #define IRAM_BASE_ADDR         0x1FFE0000      /* internal ram */
 #define IPU_SOC_BASE_ADDR      0x40000000
-#define IPU_SOC_OFFSET         0x1E000000
 #define SPBA0_BASE_ADDR                0x70000000
 #define AIPS1_BASE_ADDR                0x73F00000
 #define AIPS2_BASE_ADDR                0x83F00000
@@ -21,8 +20,7 @@
 #define NFC_BASE_ADDR_AXI      0xCFFF0000
 #define CS1_BASE_ADDR          0xB8000000
 #elif defined(CONFIG_MX53)
-#define IPU_SOC_BASE_ADDR      0x18000000
-#define IPU_SOC_OFFSET         0x06000000
+#define IPU_SOC_BASE_ADDR      0x00000000
 #define SPBA0_BASE_ADDR                0x50000000
 #define AIPS1_BASE_ADDR                0x53F00000
 #define AIPS2_BASE_ADDR                0x63F00000
@@ -202,21 +200,6 @@
  */
 #define WBED           1
 
-/*
- * WEIM WCR
- */
-#define BCM            1
-#define GBCD(x)                (((x) & 0x3) << 1)
-#define INTEN          (1 << 4)
-#define INTPOL         (1 << 5)
-#define WDOG_EN                (1 << 8)
-#define WDOG_LIMIT(x)  (((x) & 0x3) << 9)
-
-#define CS0_128                                        0
-#define CS0_64M_CS1_64M                                1
-#define CS0_64M_CS1_32M_CS2_32M                        2
-#define CS0_32M_CS1_32M_CS2_32M_CS3_32M                3
-
 /*
  * CSPI register definitions
  */
@@ -240,9 +223,10 @@
 #define MXC_CSPICTRL_CHAN      18
 
 /* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_POL                4
-#define MXC_CSPICON_PHA                0
-#define MXC_CSPICON_SSPOL      12
+#define MXC_CSPICON_PHA                0  /* SCLK phase control */
+#define MXC_CSPICON_POL                4  /* SCLK polarity */
+#define MXC_CSPICON_SSPOL      12 /* SS polarity */
+#define MXC_CSPICON_CTL                20 /* inactive state of SCLK */
 #define MXC_SPI_BASE_ADDRESSES \
        CSPI1_BASE_ADDR, \
        CSPI2_BASE_ADDR, \
@@ -435,8 +419,7 @@ struct weim {
 
 #if defined(CONFIG_MX51)
 struct iomuxc {
-       u32     gpr0;
-       u32     gpr1;
+       u32     gpr[2];
        u32     omux0;
        u32     omux1;
        u32     omux2;
@@ -445,9 +428,7 @@ struct iomuxc {
 };
 #elif defined(CONFIG_MX53)
 struct iomuxc {
-       u32     gpr0;
-       u32     gpr1;
-       u32     gpr2;
+       u32     gpr[3];
        u32     omux0;
        u32     omux1;
        u32     omux2;