*/
#define WBED 1
-/*
- * WEIM WCR
- */
-#define BCM 1
-#define GBCD(x) (((x) & 0x3) << 1)
-#define INTEN (1 << 4)
-#define INTPOL (1 << 5)
-#define WDOG_EN (1 << 8)
-#define WDOG_LIMIT(x) (((x) & 0x3) << 9)
-
-#define CS0_128 0
-#define CS0_64M_CS1_64M 1
-#define CS0_64M_CS1_32M_CS2_32M 2
-#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
-
/*
* CSPI register definitions
*/
#define MXC_CSPICTRL_CHAN 18
/* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_POL 4
-#define MXC_CSPICON_PHA 0
-#define MXC_CSPICON_SSPOL 12
+#define MXC_CSPICON_PHA 0 /* SCLK phase control */
+#define MXC_CSPICON_POL 4 /* SCLK polarity */
+#define MXC_CSPICON_SSPOL 12 /* SS polarity */
+#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
#define MXC_SPI_BASE_ADDRESSES \
CSPI1_BASE_ADDR, \
CSPI2_BASE_ADDR, \
#if defined(CONFIG_MX51)
struct iomuxc {
- u32 gpr0;
- u32 gpr1;
+ u32 gpr[2];
u32 omux0;
u32 omux1;
u32 omux2;
};
#elif defined(CONFIG_MX53)
struct iomuxc {
- u32 gpr0;
- u32 gpr1;
- u32 gpr2;
+ u32 gpr[3];
u32 omux0;
u32 omux1;
u32 omux2;