-#define BM_ANADIG_USB2_PLL_480_CTRL_LOCK (1 << 31)
-#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS (1 << 16)
-#define BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC 14
-#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC)
-#define BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
- (((v) << BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC) & \
- BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC)
-#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(0)
-#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(1)
-#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(2)
-#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__XOR BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(3)
-#define BM_ANADIG_USB2_PLL_480_CTRL_ENABLE (1 << 13)
-#define BM_ANADIG_USB2_PLL_480_CTRL_POWER (1 << 12)
-#define BM_ANADIG_USB2_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
-#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_CP (1 << 10)
-#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_CP (1 << 9)
-#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_LF (1 << 8)
-#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_LF (1 << 7)
-#define BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
-#define BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0 2
-#define BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0)
-#define BF_ANADIG_USB2_PLL_480_CTRL_CONTROL0(v) \
- (((v) << BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0) & \
- BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0)
-#define BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT 0
-#define BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT)
-#define BF_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT(v) \
- (((v) << BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT) & \
- BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT)
-
-#define BM_ANADIG_PLL_SYS_LOCK (1 << 31)
-#define BM_ANADIG_PLL_SYS_PLL_SEL (1 << 19)
-#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL (1 << 18)
-#define BM_ANADIG_PLL_SYS_LVDS_SEL (1 << 17)
-#define BM_ANADIG_PLL_SYS_BYPASS (1 << 16)
-#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
-#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
-#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
- (((v) << BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_PLL_SYS_ENABLE (1 << 13)
-#define BM_ANADIG_PLL_SYS_POWERDOWN (1 << 12)
-#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF (1 << 11)
-#define BM_ANADIG_PLL_SYS_DOUBLE_CP (1 << 10)
-#define BM_ANADIG_PLL_SYS_HALF_CP (1 << 9)
-#define BM_ANADIG_PLL_SYS_DOUBLE_LF (1 << 8)
-#define BM_ANADIG_PLL_SYS_HALF_LF (1 << 7)
-#define BP_ANADIG_PLL_SYS_DIV_SELECT 0
-#define BM_ANADIG_PLL_SYS_DIV_SELECT (0x7F << BP_ANADIG_PLL_SYS_DIV_SELECT)
-#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
- (((v) << BP_ANADIG_PLL_SYS_DIV_SELECT) & BM_ANADIG_PLL_SYS_DIV_SELECT)
-
-#define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31)
-#define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21)
-#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
-#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
-#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
- (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
-#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18)
-#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17)
-#define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16)
-#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
-#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
-#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
- (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_PLL_AUDIO_ENABLE (1 << 13)
-#define BM_ANADIG_PLL_AUDIO_POWERDOWN (1 << 12)
-#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF (1 << 11)
-#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP (1 << 10)
-#define BM_ANADIG_PLL_AUDIO_HALF_CP (1 << 9)
-#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF (1 << 8)
-#define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7)
-#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
-#define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
-#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
- (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
-
-#define BP_ANADIG_PLL_AUDIO_NUM_A 0
-#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
-#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
- (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & BM_ANADIG_PLL_AUDIO_NUM_A)
-
-#define BP_ANADIG_PLL_AUDIO_DENOM_B 0
-#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
-#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
- (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & BM_ANADIG_PLL_AUDIO_DENOM_B)
-
-#define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31)
-#define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21)
-#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
-#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
-#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
- (((v) << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
-#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18)
-#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17)
-#define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16)
-#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
-#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
-#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
- (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_PLL_VIDEO_ENABLE (1 << 13)
-#define BM_ANADIG_PLL_VIDEO_POWERDOWN (1 << 12)
-#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF (1 << 11)
-#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP (1 << 10)
-#define BM_ANADIG_PLL_VIDEO_HALF_CP (1 << 9)
-#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF (1 << 8)
-#define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7)
-#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
-#define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
-#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
- (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
-
-#define BP_ANADIG_PLL_VIDEO_NUM_A 0
-#define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
-#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
- (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & BM_ANADIG_PLL_VIDEO_NUM_A)
-
-#define BP_ANADIG_PLL_VIDEO_DENOM_B 0
-#define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
-#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
- (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & BM_ANADIG_PLL_VIDEO_DENOM_B)
-
-#define BM_ANADIG_PLL_MLB_LOCK (1 << 31)
-#define BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG 26
-#define BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
-#define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v) \
- (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
-#define BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG 23
-#define BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
-#define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v) \
- (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
-#define BP_ANADIG_PLL_MLB_VDDD_DLY_CFG 20
-#define BM_ANADIG_PLL_MLB_VDDD_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG)
-#define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v) \
- (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & BM_ANADIG_PLL_MLB_VDDD_DLY_CFG)
-#define BP_ANADIG_PLL_MLB_VDDA_DLY_CFG 17
-#define BM_ANADIG_PLL_MLB_VDDA_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG)
-#define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v) \
- (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & BM_ANADIG_PLL_MLB_VDDA_DLY_CFG)
-#define BM_ANADIG_PLL_MLB_BYPASS (1 << 16)
-#define BP_ANADIG_PLL_MLB_PHASE_SEL 12
-#define BM_ANADIG_PLL_MLB_PHASE_SEL (0x7 << BP_ANADIG_PLL_MLB_PHASE_SEL)
-#define BF_ANADIG_PLL_MLB_PHASE_SEL(v) \
- (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & BM_ANADIG_PLL_MLB_PHASE_SEL)
-#define BM_ANADIG_PLL_MLB_HOLD_RING_OFF (1 << 11)
-
-#define BM_ANADIG_PLL_ENET_LOCK (1 << 31)
-#define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20)
-#define BM_ANADIG_PLL_ENET_ENABLE_PCIE (1 << 19)
-#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN (1 << 18)
-#define BM_ANADIG_PLL_ENET_DITHER_ENABLE (1 << 17)
-#define BM_ANADIG_PLL_ENET_BYPASS (1 << 16)
-#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
-#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
-#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
- (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_PLL_ENET_ENABLE (1 << 13)
-#define BM_ANADIG_PLL_ENET_POWERDOWN (1 << 12)
-#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF (1 << 11)
-#define BM_ANADIG_PLL_ENET_DOUBLE_CP (1 << 10)
-#define BM_ANADIG_PLL_ENET_HALF_CP (1 << 9)
-#define BM_ANADIG_PLL_ENET_DOUBLE_LF (1 << 8)
-#define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7)
-#define BP_ANADIG_PLL_ENET_DIV_SELECT 0
-#define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
-#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
- (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & BM_ANADIG_PLL_ENET_DIV_SELECT)
-
-#define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31)
-#define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30)
-#define BP_ANADIG_PFD_480_PFD3_FRAC 24
-#define BM_ANADIG_PFD_480_PFD3_FRAC (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)
+#define BM_ANADIG_PLL_528_LOCK (1 << 31)
+#define BM_ANADIG_PLL_528_PLL_SEL (1 << 19)
+#define BM_ANADIG_PLL_528_LVDS_24MHZ_SEL (1 << 18)
+#define BM_ANADIG_PLL_528_LVDS_SEL (1 << 17)
+#define BM_ANADIG_PLL_528_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_528_BYPASS_CLK_SRC)
+#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_PLL_528_BYPASS_CLK_SRC) & \
+ BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_528_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_528_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_528_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_528_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_528_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_528_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_528_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_528_DIV_SELECT 0
+#define BM_ANADIG_PLL_528_DIV_SELECT (0x7F << BP_ANADIG_PLL_528_DIV_SELECT)
+#define BF_ANADIG_PLL_528_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_528_DIV_SELECT) & \
+ BM_ANADIG_PLL_528_DIV_SELECT)
+
+#define BP_ANADIG_PLL_528_SS_STOP 16
+#define BM_ANADIG_PLL_528_SS_STOP (0xFFFF << BP_ANADIG_PLL_528_SS_STOP)
+#define BF_ANADIG_PLL_528_SS_STOP(v) \
+ (((v) << BP_ANADIG_PLL_528_SS_STOP) & \
+ BM_ANADIG_PLL_528_SS_STOP)
+#define BM_ANADIG_PLL_528_SS_ENABLE (1 << 15)
+#define BP_ANADIG_PLL_528_SS_STEP 0
+#define BM_ANADIG_PLL_528_SS_STEP (0x7FFF << BP_ANADIG_PLL_528_SS_STEP)
+#define BF_ANADIG_PLL_528_SS_STEP(v) \
+ (((v) << BP_ANADIG_PLL_528_SS_STEP) & \
+ BM_ANADIG_PLL_528_SS_STEP)
+
+#define BP_ANADIG_PLL_528_NUM_A 0
+#define BM_ANADIG_PLL_528_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_528_NUM_A)
+#define BF_ANADIG_PLL_528_NUM_A(v) \
+ (((v) << BP_ANADIG_PLL_528_NUM_A) & \
+ BM_ANADIG_PLL_528_NUM_A)
+
+#define BP_ANADIG_PLL_528_DENOM_B 0
+#define BM_ANADIG_PLL_528_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_528_DENOM_B)
+#define BF_ANADIG_PLL_528_DENOM_B(v) \
+ (((v) << BP_ANADIG_PLL_528_DENOM_B) & \
+ BM_ANADIG_PLL_528_DENOM_B)
+
+#define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31)
+#define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21)
+#define BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT 19
+#define BM_ANADIG_PLL_AUDIO_POST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT)
+#define BF_ANADIG_PLL_AUDIO_POST_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT) & \
+ BM_ANADIG_PLL_AUDIO_POST_DIV_SELECT)
+#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18)
+#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17)
+#define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
+#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & \
+ BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_AUDIO_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_AUDIO_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_AUDIO_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
+#define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
+#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & \
+ BM_ANADIG_PLL_AUDIO_DIV_SELECT)
+
+#define BP_ANADIG_PLL_AUDIO_NUM_A 0
+#define BM_ANADIG_PLL_AUDIO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_NUM_A)
+#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & \
+ BM_ANADIG_PLL_AUDIO_NUM_A)
+
+#define BP_ANADIG_PLL_AUDIO_DENOM_B 0
+#define BM_ANADIG_PLL_AUDIO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_DENOM_B)
+#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & \
+ BM_ANADIG_PLL_AUDIO_DENOM_B)
+
+#define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31)
+#define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21)
+#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
+#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
+#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT) & \
+ BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
+#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18)
+#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17)
+#define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
+#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & \
+ BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_VIDEO_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_VIDEO_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_VIDEO_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
+#define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
+#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & \
+ BM_ANADIG_PLL_VIDEO_DIV_SELECT)
+
+#define BP_ANADIG_PLL_VIDEO_NUM_A 0
+#define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
+#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
+ (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & \
+ BM_ANADIG_PLL_VIDEO_NUM_A)
+
+#define BP_ANADIG_PLL_VIDEO_DENOM_B 0
+#define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
+#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
+ (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \
+ BM_ANADIG_PLL_VIDEO_DENOM_B)
+
+#define BM_ANADIG_PLL_MLB_LOCK (1 << 31)
+#define BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG 26
+#define BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
+#define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v) \
+ (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & \
+ BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
+#define BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG 23
+#define BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
+#define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v) \
+ (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & \
+ BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
+#define BP_ANADIG_PLL_MLB_VDDD_DLY_CFG 20
+#define BM_ANADIG_PLL_MLB_VDDD_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG)
+#define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v) \
+ (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & \
+ BM_ANADIG_PLL_MLB_VDDD_DLY_CFG)
+#define BP_ANADIG_PLL_MLB_VDDA_DLY_CFG 17
+#define BM_ANADIG_PLL_MLB_VDDA_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG)
+#define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v) \
+ (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & \
+ BM_ANADIG_PLL_MLB_VDDA_DLY_CFG)
+#define BM_ANADIG_PLL_MLB_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_MLB_PHASE_SEL 12
+#define BM_ANADIG_PLL_MLB_PHASE_SEL (0x7 << BP_ANADIG_PLL_MLB_PHASE_SEL)
+#define BF_ANADIG_PLL_MLB_PHASE_SEL(v) \
+ (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & \
+ BM_ANADIG_PLL_MLB_PHASE_SEL)
+#define BM_ANADIG_PLL_MLB_HOLD_RING_OFF (1 << 11)
+
+#define BM_ANADIG_PLL_ENET_LOCK (1 << 31)
+#define BM_ANADIG_PLL_ENET_REF_25M_ENABLE (1 << 21)
+#define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20)
+#define BM_ANADIG_PLL_ENET_ENABLE_PCIE (1 << 19)
+#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN (1 << 18)
+#define BM_ANADIG_PLL_ENET_DITHER_ENABLE (1 << 17)
+#define BM_ANADIG_PLL_ENET_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
+#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & \
+ BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_ENET_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_ENET_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_ENET_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_ENET_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_ENET_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_ENET_DIV_SELECT 0
+#define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
+#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & \
+ BM_ANADIG_PLL_ENET_DIV_SELECT)
+
+#define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31)
+#define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30)
+#define BP_ANADIG_PFD_480_PFD3_FRAC 24
+#define BM_ANADIG_PFD_480_PFD3_FRAC (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)