* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __REGS_APBH_H__
#define __REGS_APBH_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
-struct apbh_regs {
- mxs_reg_32(hw_apbh_ctrl0)
- mxs_reg_32(hw_apbh_ctrl1)
- mxs_reg_32(hw_apbh_ctrl2)
- mxs_reg_32(hw_apbh_channel_ctrl)
- mxs_reg_32(hw_apbh_devsel)
- mxs_reg_32(hw_apbh_dma_burst_size)
- mxs_reg_32(hw_apbh_debug)
- uint32_t reserved[36];
+#if defined(CONFIG_MX23)
+struct mxs_apbh_regs {
+ mxs_reg_32(hw_apbh_ctrl0);
+ mxs_reg_32(hw_apbh_ctrl1);
+ mxs_reg_32(hw_apbh_ctrl2);
+ mxs_reg_32(hw_apbh_channel_ctrl);
+
+ union {
+ struct {
+ mxs_reg_32(hw_apbh_ch_curcmdar);
+ mxs_reg_32(hw_apbh_ch_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch_cmd);
+ mxs_reg_32(hw_apbh_ch_bar);
+ mxs_reg_32(hw_apbh_ch_sema);
+ mxs_reg_32(hw_apbh_ch_debug1);
+ mxs_reg_32(hw_apbh_ch_debug2);
+ } ch[8];
+ struct {
+ mxs_reg_32(hw_apbh_ch0_curcmdar);
+ mxs_reg_32(hw_apbh_ch0_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch0_cmd);
+ mxs_reg_32(hw_apbh_ch0_bar);
+ mxs_reg_32(hw_apbh_ch0_sema);
+ mxs_reg_32(hw_apbh_ch0_debug1);
+ mxs_reg_32(hw_apbh_ch0_debug2);
+ mxs_reg_32(hw_apbh_ch1_curcmdar);
+ mxs_reg_32(hw_apbh_ch1_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch1_cmd);
+ mxs_reg_32(hw_apbh_ch1_bar);
+ mxs_reg_32(hw_apbh_ch1_sema);
+ mxs_reg_32(hw_apbh_ch1_debug1);
+ mxs_reg_32(hw_apbh_ch1_debug2);
+ mxs_reg_32(hw_apbh_ch2_curcmdar);
+ mxs_reg_32(hw_apbh_ch2_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch2_cmd);
+ mxs_reg_32(hw_apbh_ch2_bar);
+ mxs_reg_32(hw_apbh_ch2_sema);
+ mxs_reg_32(hw_apbh_ch2_debug1);
+ mxs_reg_32(hw_apbh_ch2_debug2);
+ mxs_reg_32(hw_apbh_ch3_curcmdar);
+ mxs_reg_32(hw_apbh_ch3_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch3_cmd);
+ mxs_reg_32(hw_apbh_ch3_bar);
+ mxs_reg_32(hw_apbh_ch3_sema);
+ mxs_reg_32(hw_apbh_ch3_debug1);
+ mxs_reg_32(hw_apbh_ch3_debug2);
+ mxs_reg_32(hw_apbh_ch4_curcmdar);
+ mxs_reg_32(hw_apbh_ch4_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch4_cmd);
+ mxs_reg_32(hw_apbh_ch4_bar);
+ mxs_reg_32(hw_apbh_ch4_sema);
+ mxs_reg_32(hw_apbh_ch4_debug1);
+ mxs_reg_32(hw_apbh_ch4_debug2);
+ mxs_reg_32(hw_apbh_ch5_curcmdar);
+ mxs_reg_32(hw_apbh_ch5_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch5_cmd);
+ mxs_reg_32(hw_apbh_ch5_bar);
+ mxs_reg_32(hw_apbh_ch5_sema);
+ mxs_reg_32(hw_apbh_ch5_debug1);
+ mxs_reg_32(hw_apbh_ch5_debug2);
+ mxs_reg_32(hw_apbh_ch6_curcmdar);
+ mxs_reg_32(hw_apbh_ch6_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch6_cmd);
+ mxs_reg_32(hw_apbh_ch6_bar);
+ mxs_reg_32(hw_apbh_ch6_sema);
+ mxs_reg_32(hw_apbh_ch6_debug1);
+ mxs_reg_32(hw_apbh_ch6_debug2);
+ mxs_reg_32(hw_apbh_ch7_curcmdar);
+ mxs_reg_32(hw_apbh_ch7_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch7_cmd);
+ mxs_reg_32(hw_apbh_ch7_bar);
+ mxs_reg_32(hw_apbh_ch7_sema);
+ mxs_reg_32(hw_apbh_ch7_debug1);
+ mxs_reg_32(hw_apbh_ch7_debug2);
+ };
+ };
+ mxs_reg_32(hw_apbh_version);
+};
+
+#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
+struct mxs_apbh_regs {
+ mxs_reg_32(hw_apbh_ctrl0); /* 0x000 */
+ mxs_reg_32(hw_apbh_ctrl1); /* 0x010 */
+ mxs_reg_32(hw_apbh_ctrl2); /* 0x020 */
+ mxs_reg_32(hw_apbh_channel_ctrl); /* 0x030 */
+ mxs_reg_32(hw_apbh_devsel); /* 0x040 */
+ mxs_reg_32(hw_apbh_dma_burst_size); /* 0x050 */
+ mxs_reg_32(hw_apbh_debug); /* 0x060 */
+
+ reg_32(reserved[9]); /* 0x064-0x0fc */
union {
struct {
- mxs_reg_32(hw_apbh_ch_curcmdar)
- mxs_reg_32(hw_apbh_ch_nxtcmdar)
- mxs_reg_32(hw_apbh_ch_cmd)
- mxs_reg_32(hw_apbh_ch_bar)
- mxs_reg_32(hw_apbh_ch_sema)
- mxs_reg_32(hw_apbh_ch_debug1)
- mxs_reg_32(hw_apbh_ch_debug2)
+ mxs_reg_32(hw_apbh_ch_curcmdar);
+ mxs_reg_32(hw_apbh_ch_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch_cmd);
+ mxs_reg_32(hw_apbh_ch_bar);
+ mxs_reg_32(hw_apbh_ch_sema);
+ mxs_reg_32(hw_apbh_ch_debug1);
+ mxs_reg_32(hw_apbh_ch_debug2);
} ch[16];
struct {
- mxs_reg_32(hw_apbh_ch0_curcmdar)
- mxs_reg_32(hw_apbh_ch0_nxtcmdar)
- mxs_reg_32(hw_apbh_ch0_cmd)
- mxs_reg_32(hw_apbh_ch0_bar)
- mxs_reg_32(hw_apbh_ch0_sema)
- mxs_reg_32(hw_apbh_ch0_debug1)
- mxs_reg_32(hw_apbh_ch0_debug2)
- mxs_reg_32(hw_apbh_ch1_curcmdar)
- mxs_reg_32(hw_apbh_ch1_nxtcmdar)
- mxs_reg_32(hw_apbh_ch1_cmd)
- mxs_reg_32(hw_apbh_ch1_bar)
- mxs_reg_32(hw_apbh_ch1_sema)
- mxs_reg_32(hw_apbh_ch1_debug1)
- mxs_reg_32(hw_apbh_ch1_debug2)
- mxs_reg_32(hw_apbh_ch2_curcmdar)
- mxs_reg_32(hw_apbh_ch2_nxtcmdar)
- mxs_reg_32(hw_apbh_ch2_cmd)
- mxs_reg_32(hw_apbh_ch2_bar)
- mxs_reg_32(hw_apbh_ch2_sema)
- mxs_reg_32(hw_apbh_ch2_debug1)
- mxs_reg_32(hw_apbh_ch2_debug2)
- mxs_reg_32(hw_apbh_ch3_curcmdar)
- mxs_reg_32(hw_apbh_ch3_nxtcmdar)
- mxs_reg_32(hw_apbh_ch3_cmd)
- mxs_reg_32(hw_apbh_ch3_bar)
- mxs_reg_32(hw_apbh_ch3_sema)
- mxs_reg_32(hw_apbh_ch3_debug1)
- mxs_reg_32(hw_apbh_ch3_debug2)
- mxs_reg_32(hw_apbh_ch4_curcmdar)
- mxs_reg_32(hw_apbh_ch4_nxtcmdar)
- mxs_reg_32(hw_apbh_ch4_cmd)
- mxs_reg_32(hw_apbh_ch4_bar)
- mxs_reg_32(hw_apbh_ch4_sema)
- mxs_reg_32(hw_apbh_ch4_debug1)
- mxs_reg_32(hw_apbh_ch4_debug2)
- mxs_reg_32(hw_apbh_ch5_curcmdar)
- mxs_reg_32(hw_apbh_ch5_nxtcmdar)
- mxs_reg_32(hw_apbh_ch5_cmd)
- mxs_reg_32(hw_apbh_ch5_bar)
- mxs_reg_32(hw_apbh_ch5_sema)
- mxs_reg_32(hw_apbh_ch5_debug1)
- mxs_reg_32(hw_apbh_ch5_debug2)
- mxs_reg_32(hw_apbh_ch6_curcmdar)
- mxs_reg_32(hw_apbh_ch6_nxtcmdar)
- mxs_reg_32(hw_apbh_ch6_cmd)
- mxs_reg_32(hw_apbh_ch6_bar)
- mxs_reg_32(hw_apbh_ch6_sema)
- mxs_reg_32(hw_apbh_ch6_debug1)
- mxs_reg_32(hw_apbh_ch6_debug2)
- mxs_reg_32(hw_apbh_ch7_curcmdar)
- mxs_reg_32(hw_apbh_ch7_nxtcmdar)
- mxs_reg_32(hw_apbh_ch7_cmd)
- mxs_reg_32(hw_apbh_ch7_bar)
- mxs_reg_32(hw_apbh_ch7_sema)
- mxs_reg_32(hw_apbh_ch7_debug1)
- mxs_reg_32(hw_apbh_ch7_debug2)
- mxs_reg_32(hw_apbh_ch8_curcmdar)
- mxs_reg_32(hw_apbh_ch8_nxtcmdar)
- mxs_reg_32(hw_apbh_ch8_cmd)
- mxs_reg_32(hw_apbh_ch8_bar)
- mxs_reg_32(hw_apbh_ch8_sema)
- mxs_reg_32(hw_apbh_ch8_debug1)
- mxs_reg_32(hw_apbh_ch8_debug2)
- mxs_reg_32(hw_apbh_ch9_curcmdar)
- mxs_reg_32(hw_apbh_ch9_nxtcmdar)
- mxs_reg_32(hw_apbh_ch9_cmd)
- mxs_reg_32(hw_apbh_ch9_bar)
- mxs_reg_32(hw_apbh_ch9_sema)
- mxs_reg_32(hw_apbh_ch9_debug1)
- mxs_reg_32(hw_apbh_ch9_debug2)
- mxs_reg_32(hw_apbh_ch10_curcmdar)
- mxs_reg_32(hw_apbh_ch10_nxtcmdar)
- mxs_reg_32(hw_apbh_ch10_cmd)
- mxs_reg_32(hw_apbh_ch10_bar)
- mxs_reg_32(hw_apbh_ch10_sema)
- mxs_reg_32(hw_apbh_ch10_debug1)
- mxs_reg_32(hw_apbh_ch10_debug2)
- mxs_reg_32(hw_apbh_ch11_curcmdar)
- mxs_reg_32(hw_apbh_ch11_nxtcmdar)
- mxs_reg_32(hw_apbh_ch11_cmd)
- mxs_reg_32(hw_apbh_ch11_bar)
- mxs_reg_32(hw_apbh_ch11_sema)
- mxs_reg_32(hw_apbh_ch11_debug1)
- mxs_reg_32(hw_apbh_ch11_debug2)
- mxs_reg_32(hw_apbh_ch12_curcmdar)
- mxs_reg_32(hw_apbh_ch12_nxtcmdar)
- mxs_reg_32(hw_apbh_ch12_cmd)
- mxs_reg_32(hw_apbh_ch12_bar)
- mxs_reg_32(hw_apbh_ch12_sema)
- mxs_reg_32(hw_apbh_ch12_debug1)
- mxs_reg_32(hw_apbh_ch12_debug2)
- mxs_reg_32(hw_apbh_ch13_curcmdar)
- mxs_reg_32(hw_apbh_ch13_nxtcmdar)
- mxs_reg_32(hw_apbh_ch13_cmd)
- mxs_reg_32(hw_apbh_ch13_bar)
- mxs_reg_32(hw_apbh_ch13_sema)
- mxs_reg_32(hw_apbh_ch13_debug1)
- mxs_reg_32(hw_apbh_ch13_debug2)
- mxs_reg_32(hw_apbh_ch14_curcmdar)
- mxs_reg_32(hw_apbh_ch14_nxtcmdar)
- mxs_reg_32(hw_apbh_ch14_cmd)
- mxs_reg_32(hw_apbh_ch14_bar)
- mxs_reg_32(hw_apbh_ch14_sema)
- mxs_reg_32(hw_apbh_ch14_debug1)
- mxs_reg_32(hw_apbh_ch14_debug2)
- mxs_reg_32(hw_apbh_ch15_curcmdar)
- mxs_reg_32(hw_apbh_ch15_nxtcmdar)
- mxs_reg_32(hw_apbh_ch15_cmd)
- mxs_reg_32(hw_apbh_ch15_bar)
- mxs_reg_32(hw_apbh_ch15_sema)
- mxs_reg_32(hw_apbh_ch15_debug1)
- mxs_reg_32(hw_apbh_ch15_debug2)
+ mxs_reg_32(hw_apbh_ch0_curcmdar);
+ mxs_reg_32(hw_apbh_ch0_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch0_cmd);
+ mxs_reg_32(hw_apbh_ch0_bar);
+ mxs_reg_32(hw_apbh_ch0_sema);
+ mxs_reg_32(hw_apbh_ch0_debug1);
+ mxs_reg_32(hw_apbh_ch0_debug2);
+ mxs_reg_32(hw_apbh_ch1_curcmdar);
+ mxs_reg_32(hw_apbh_ch1_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch1_cmd);
+ mxs_reg_32(hw_apbh_ch1_bar);
+ mxs_reg_32(hw_apbh_ch1_sema);
+ mxs_reg_32(hw_apbh_ch1_debug1);
+ mxs_reg_32(hw_apbh_ch1_debug2);
+ mxs_reg_32(hw_apbh_ch2_curcmdar);
+ mxs_reg_32(hw_apbh_ch2_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch2_cmd);
+ mxs_reg_32(hw_apbh_ch2_bar);
+ mxs_reg_32(hw_apbh_ch2_sema);
+ mxs_reg_32(hw_apbh_ch2_debug1);
+ mxs_reg_32(hw_apbh_ch2_debug2);
+ mxs_reg_32(hw_apbh_ch3_curcmdar);
+ mxs_reg_32(hw_apbh_ch3_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch3_cmd);
+ mxs_reg_32(hw_apbh_ch3_bar);
+ mxs_reg_32(hw_apbh_ch3_sema);
+ mxs_reg_32(hw_apbh_ch3_debug1);
+ mxs_reg_32(hw_apbh_ch3_debug2);
+ mxs_reg_32(hw_apbh_ch4_curcmdar);
+ mxs_reg_32(hw_apbh_ch4_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch4_cmd);
+ mxs_reg_32(hw_apbh_ch4_bar);
+ mxs_reg_32(hw_apbh_ch4_sema);
+ mxs_reg_32(hw_apbh_ch4_debug1);
+ mxs_reg_32(hw_apbh_ch4_debug2);
+ mxs_reg_32(hw_apbh_ch5_curcmdar);
+ mxs_reg_32(hw_apbh_ch5_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch5_cmd);
+ mxs_reg_32(hw_apbh_ch5_bar);
+ mxs_reg_32(hw_apbh_ch5_sema);
+ mxs_reg_32(hw_apbh_ch5_debug1);
+ mxs_reg_32(hw_apbh_ch5_debug2);
+ mxs_reg_32(hw_apbh_ch6_curcmdar);
+ mxs_reg_32(hw_apbh_ch6_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch6_cmd);
+ mxs_reg_32(hw_apbh_ch6_bar);
+ mxs_reg_32(hw_apbh_ch6_sema);
+ mxs_reg_32(hw_apbh_ch6_debug1);
+ mxs_reg_32(hw_apbh_ch6_debug2);
+ mxs_reg_32(hw_apbh_ch7_curcmdar);
+ mxs_reg_32(hw_apbh_ch7_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch7_cmd);
+ mxs_reg_32(hw_apbh_ch7_bar);
+ mxs_reg_32(hw_apbh_ch7_sema);
+ mxs_reg_32(hw_apbh_ch7_debug1);
+ mxs_reg_32(hw_apbh_ch7_debug2);
+ mxs_reg_32(hw_apbh_ch8_curcmdar);
+ mxs_reg_32(hw_apbh_ch8_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch8_cmd);
+ mxs_reg_32(hw_apbh_ch8_bar);
+ mxs_reg_32(hw_apbh_ch8_sema);
+ mxs_reg_32(hw_apbh_ch8_debug1);
+ mxs_reg_32(hw_apbh_ch8_debug2);
+ mxs_reg_32(hw_apbh_ch9_curcmdar);
+ mxs_reg_32(hw_apbh_ch9_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch9_cmd);
+ mxs_reg_32(hw_apbh_ch9_bar);
+ mxs_reg_32(hw_apbh_ch9_sema);
+ mxs_reg_32(hw_apbh_ch9_debug1);
+ mxs_reg_32(hw_apbh_ch9_debug2);
+ mxs_reg_32(hw_apbh_ch10_curcmdar);
+ mxs_reg_32(hw_apbh_ch10_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch10_cmd);
+ mxs_reg_32(hw_apbh_ch10_bar);
+ mxs_reg_32(hw_apbh_ch10_sema);
+ mxs_reg_32(hw_apbh_ch10_debug1);
+ mxs_reg_32(hw_apbh_ch10_debug2);
+ mxs_reg_32(hw_apbh_ch11_curcmdar);
+ mxs_reg_32(hw_apbh_ch11_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch11_cmd);
+ mxs_reg_32(hw_apbh_ch11_bar);
+ mxs_reg_32(hw_apbh_ch11_sema);
+ mxs_reg_32(hw_apbh_ch11_debug1);
+ mxs_reg_32(hw_apbh_ch11_debug2);
+ mxs_reg_32(hw_apbh_ch12_curcmdar);
+ mxs_reg_32(hw_apbh_ch12_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch12_cmd);
+ mxs_reg_32(hw_apbh_ch12_bar);
+ mxs_reg_32(hw_apbh_ch12_sema);
+ mxs_reg_32(hw_apbh_ch12_debug1);
+ mxs_reg_32(hw_apbh_ch12_debug2);
+ mxs_reg_32(hw_apbh_ch13_curcmdar);
+ mxs_reg_32(hw_apbh_ch13_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch13_cmd);
+ mxs_reg_32(hw_apbh_ch13_bar);
+ mxs_reg_32(hw_apbh_ch13_sema);
+ mxs_reg_32(hw_apbh_ch13_debug1);
+ mxs_reg_32(hw_apbh_ch13_debug2);
+ mxs_reg_32(hw_apbh_ch14_curcmdar);
+ mxs_reg_32(hw_apbh_ch14_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch14_cmd);
+ mxs_reg_32(hw_apbh_ch14_bar);
+ mxs_reg_32(hw_apbh_ch14_sema);
+ mxs_reg_32(hw_apbh_ch14_debug1);
+ mxs_reg_32(hw_apbh_ch14_debug2);
+ mxs_reg_32(hw_apbh_ch15_curcmdar);
+ mxs_reg_32(hw_apbh_ch15_nxtcmdar);
+ mxs_reg_32(hw_apbh_ch15_cmd);
+ mxs_reg_32(hw_apbh_ch15_bar);
+ mxs_reg_32(hw_apbh_ch15_sema);
+ mxs_reg_32(hw_apbh_ch15_debug1);
+ mxs_reg_32(hw_apbh_ch15_debug2);
};
};
- mxs_reg_32(hw_apbh_version)
+ mxs_reg_32(hw_apbh_version);
};
#endif
+#endif
+
#define APBH_CTRL0_SFTRST (1 << 31)
#define APBH_CTRL0_CLKGATE (1 << 30)
#define APBH_CTRL0_AHB_BURST8_EN (1 << 29)
#define APBH_CTRL0_APB_BURST_EN (1 << 28)
+#if defined(CONFIG_MX23)
+#define APBH_CTRL0_RSVD0_MASK (0xf << 24)
+#define APBH_CTRL0_RSVD0_OFFSET 24
+#define APBH_CTRL0_RESET_CHANNEL_MASK (0xff << 16)
+#define APBH_CTRL0_RESET_CHANNEL_OFFSET 16
+#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xff << 8)
+#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 8
+#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x02
+#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x04
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x10
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x20
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x40
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x80
+#elif defined(CONFIG_MX28)
#define APBH_CTRL0_RSVD0_MASK (0xfff << 16)
#define APBH_CTRL0_RSVD0_OFFSET 16
#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
+#elif defined(CONFIG_MX6)
+#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0004
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0008
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0010
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0020
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0040
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0080
+#define APBH_CTRL0_CLKGATE_CHANNEL_SSP 0x0100
+#endif
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31)
#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30)
#define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1)
#define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0)
+#if defined(CONFIG_MX28)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16)
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
+#endif
+#if defined(CONFIG_MX6)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
+#endif
+
+#if defined(CONFIG_MX23)
+#define APBH_DEVSEL_CH7_MASK (0xf << 28)
+#define APBH_DEVSEL_CH7_OFFSET 28
+#define APBH_DEVSEL_CH6_MASK (0xf << 24)
+#define APBH_DEVSEL_CH6_OFFSET 24
+#define APBH_DEVSEL_CH5_MASK (0xf << 20)
+#define APBH_DEVSEL_CH5_OFFSET 20
+#define APBH_DEVSEL_CH4_MASK (0xf << 16)
+#define APBH_DEVSEL_CH4_OFFSET 16
+#define APBH_DEVSEL_CH3_MASK (0xf << 12)
+#define APBH_DEVSEL_CH3_OFFSET 12
+#define APBH_DEVSEL_CH2_MASK (0xf << 8)
+#define APBH_DEVSEL_CH2_OFFSET 8
+#define APBH_DEVSEL_CH1_MASK (0xf << 4)
+#define APBH_DEVSEL_CH1_OFFSET 4
+#define APBH_DEVSEL_CH0_MASK (0xf << 0)
+#define APBH_DEVSEL_CH0_OFFSET 0
+#elif defined(CONFIG_MX28)
#define APBH_DEVSEL_CH15_MASK (0x3 << 30)
#define APBH_DEVSEL_CH15_OFFSET 30
#define APBH_DEVSEL_CH14_MASK (0x3 << 28)
#define APBH_DEVSEL_CH1_OFFSET 2
#define APBH_DEVSEL_CH0_MASK (0x3 << 0)
#define APBH_DEVSEL_CH0_OFFSET 0
+#endif
+#if defined(CONFIG_MX28)
#define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30)
#define APBH_DMA_BURST_SIZE_CH15_OFFSET 30
#define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28)
#define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2
#define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0)
+#endif
#define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff
#define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0
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