karo: merge with Ka-Ro specific tree for secure boot support

[karo-tx-uboot.git] / arch / arm / lib / cache-cp15.c

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 2155fe818717163caaa59428dbd842e0ffd926db..751abe4e3c83f50f5fb5ad121c91f4603bd5051c 100644 (file)
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -22,16 +22,6 @@ __weak void arm_init_domains(void)
 {
 }
 
-static void cp_delay (void)
-{
-       volatile int i;
-
-       /* copro seems to need some delay between reading and writing */
-       for (i = 0; i < 100; i++)
-               nop();
-       asm volatile("" : : : "memory");
-}
-
 void set_section_dcache(int section, enum dcache_option option)
 {
        u32 *page_table = (u32 *)gd->arch.tlb_addr;
@@ -47,15 +37,15 @@ __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
        debug("%s: Warning: not implemented\n", __func__);
 }
 
-void mmu_set_region_dcache_behaviour(u32 start, int size,
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
                                     enum dcache_option option)
 {
        u32 *page_table = (u32 *)gd->arch.tlb_addr;
-       u32 upto, end;
+       unsigned long upto, end;
 
        end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
        start = start >> MMU_SECTION_SHIFT;
-       debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size,
+       debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
              option);
        for (upto = start; upto < end; upto++)
                set_section_dcache(upto, option);
@@ -96,18 +86,20 @@ static inline void mmu_setup(void)
                dram_bank_mmu_setup(i);
        }
 
-       /* Copy the page table address to cp15 */
-       asm volatile("mcr p15, 0, %0, c2, c0, 0"
-                    : : "r" (gd->arch.tlb_addr) : "memory");
-       /* Set the access control to all-supervisor */
-       asm volatile("mcr p15, 0, %0, c3, c0, 0"
-                    : : "r" (~0));
+       asm volatile(
+               /* Copy the page table address to cp15 */
+               "mcr p15, 0, %0, c2, c0, 0\n"
+               /* Set the access control to all-supervisor */
+               "mcr p15, 0, %1, c3, c0, 0\n"
+               :
+               : "r"(gd->arch.tlb_addr), "r"(~0)
+               : "memory"
+               );
 
        arm_init_domains();
 
        /* and enable the mmu */
        reg = get_cr(); /* get control reg. */
-       cp_delay();
        set_cr(reg | CR_M);
 }
 
@@ -125,7 +117,6 @@ static void cache_enable(uint32_t cache_bit)
        if ((cache_bit == CR_C) && !mmu_enabled())
                mmu_setup();
        reg = get_cr(); /* get control reg. */
-       cp_delay();
        set_cr(reg | cache_bit);
 }
 
@@ -135,7 +126,6 @@ static void cache_disable(uint32_t cache_bit)
        uint32_t reg;
 
        reg = get_cr();
-       cp_delay();
 
        if (cache_bit == CR_C) {
                /* if cache isn;t enabled no need to disable */
@@ -145,7 +135,6 @@ static void cache_disable(uint32_t cache_bit)
                cache_bit |= CR_M;
        }
        reg = get_cr();
-       cp_delay();
        if (cache_bit == (CR_C | CR_M))
                flush_dcache_all();
        set_cr(reg & ~cache_bit);