cpu_str = "Q";
else if (is_cpu_type(MXC_CPU_MX6UL))
cpu_str = "UL";
+ else if (is_cpu_type(MXC_CPU_MX6ULL))
+ cpu_str = "ULL";
printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
cpu_str,
static inline u8 tx6ul_mem_suffix(void)
{
-#ifdef CONFIG_TX6UL_NAND
- return '0';
-#else
- return '1';
-#endif
+ return '0' + CONFIG_SYS_SDRAM_CHIP_SIZE / 1024 * 2 +
+ IS_ENABLED(CONFIG_TX6_EMMC);
}
#ifdef CONFIG_RN5T567
#define VDD_CORE_VAL_LP rn5t_mV_to_regval(900)
#define VDD_DDR_VAL rn5t_mV_to_regval(1350) /* DCDC3 */
#define VDD_DDR_VAL_LP rn5t_mV_to_regval(1350)
-#define VDD_HIGH_VAL rn5t_mV_to_regval(3300) /* DCDC4 */
-#define VDD_HIGH_VAL_LP rn5t_mV_to_regval(3300)
-#define VDD_CSI_VAL rn5t_mV_to_regval2(3300) /* LDO4 */
-#define VDD_CSI_VAL_LP rn5t_mV_to_regval2(3300)
+#define VDD_IO_EXT_VAL rn5t_mV_to_regval(3300) /* DCDC4 */
+#define VDD_IO_EXT_VAL_LP rn5t_mV_to_regval(3300)
+#define VDD_IO_INT_VAL rn5t_mV_to_regval2(3300) /* LDO1 */
+#define VDD_IO_INT_VAL_LP rn5t_mV_to_regval2(3300)
+#define VDD_ADC_VAL rn5t_mV_to_regval2(3300) /* LDO2 */
+#define VDD_ADC_VAL_LP rn5t_mV_to_regval2(3300)
+#define VDD_PMIC_VAL rn5t_mV_to_regval2(2500) /* LDO3 */
+#define VDD_PMIC_VAL_LP rn5t_mV_to_regval2(2500)
+#define VDD_CSI_VAL rn5t_mV_to_regval2(1800) /* LDO4 */
+#define VDD_CSI_VAL_LP rn5t_mV_to_regval2(1800)
static struct pmic_regs rn5t567_regs[] = {
{ RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
- { RN5T567_DC2CTL, DC2_DC2DIS, },
{ RN5T567_DC1DAC, VDD_CORE_VAL, },
{ RN5T567_DC3DAC, VDD_DDR_VAL, },
- { RN5T567_DC4DAC, VDD_HIGH_VAL, },
+ { RN5T567_DC4DAC, VDD_IO_EXT_VAL, },
{ RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
{ RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
- { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
- { RN5T567_LDOEN1, 0x01f, ~0x1f, },
- { RN5T567_LDOEN2, 0x10, ~0x30, },
- { RN5T567_LDODIS, 0x00, },
- { RN5T567_LDO4DAC, VDD_CSI_VAL, },
+ { RN5T567_DC4DAC_SLP, VDD_IO_EXT_VAL_LP, },
+ { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
+ { RN5T567_DC2CTL, DCnCTL_DCnDIS, },
+ { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
+ { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
{ RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
{ RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
+ { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
+ { RN5T567_LDO2DAC, VDD_ADC_VAL, },
+ { RN5T567_LDO3DAC, VDD_PMIC_VAL, },
+ { RN5T567_LDO4DAC, VDD_CSI_VAL, },
+ { RN5T567_LDOEN1, 0x0f, ~0x1f, },
+ { RN5T567_LDOEN2, 0x10, ~0x30, },
+ { RN5T567_LDODIS, 0x10, ~0x1f, },
+ { RN5T567_INTPOL, 0, },
+ { RN5T567_INTEN, 0x3, },
+ { RN5T567_IREN, 0xf, },
+ { RN5T567_EN_GPIR, 0, },
};
-static int pmic_addr __maybe_unused = 0x33;
+static int pmic_addr = 0x33;
#endif
int board_init(void)
{
int ret;
u32 cpurev = get_cpu_rev();
+ char f = '?';
- debug("%s@%d: \n", __func__, __LINE__);
+ if (is_cpu_type(MXC_CPU_MX6UL))
+ f = ((cpurev & 0xf0) > 0x10) ? '5' : '0';
+ else if (is_cpu_type(MXC_CPU_MX6ULL))
+ f = '8';
+
+ debug("%s@%d: cpurev=%08x\n", __func__, __LINE__, cpurev);
- printf("Board: Ka-Ro TXUL-%c01%c\n",
- ((cpurev &0xff) > 0x10) ? '5' : '0',
- tx6ul_mem_suffix());
+ printf("Board: Ka-Ro TXUL-%c01%c\n", f, tx6ul_mem_suffix());
get_hab_status();
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
+ PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
return 0;
}
printf("Failed to request stk5_gpios: %d\n", ret);
return;
}
+
imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
if (getenv_yesno("jtag_enable") != 0) {
/* true if unset or set to one of: 'yYtT1' */
imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads));
}
+
debug("%s@%d: \n", __func__, __LINE__);
}
karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
karo_fdt_fixup_flexcan(blob, stk5_v5);
- karo_fdt_update_fb_mode(blob, video_mode);
+ karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel");
return 0;
}