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ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3
authorMarek Vasut <marex@denx.de>
Tue, 21 Jul 2015 03:29:05 +0000 (05:29 +0200)
committerMarek Vasut <marex@denx.de>
Sat, 8 Aug 2015 12:14:23 +0000 (14:14 +0200)
commitc65408720670819a9a7174a6b0ed59968cd8ffb7
tree85fdd58e6897b3c4399007bdeb2ddbf82ca38ec9tree | snapshot
parentc8570afa04b6d5db236b2426922f78fc26f647b5commit | diff
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3

Zap the useless addr variable.

Signed-off-by: Marek Vasut <marex@denx.de>
drivers/ddr/altera/sequencer.c diff | blob | history
UBoot for KaRo TX COM modules