*
*/
+#define RN5T567_SLPCNT 0x0e
+#define RN5T567_REPCNT 0x0f
+#define RN5T567_PWRONTIMSET 0x10
#define RN5T567_NOETIMSET 0x11
+#define RN5T567_PWRIRSEL 0x15
+#define RN5T567_DC1_SLOT 0x16
+#define RN5T567_DC2_SLOT 0x17
+#define RN5T567_DC3_SLOT 0x18
+#define RN5T567_DC4_SLOT 0x19
+#define RN5T567_LDO1_SLOT 0x1b
+#define RN5T567_LDO2_SLOT 0x1c
+#define RN5T567_LDO3_SLOT 0x1d
+#define RN5T567_LDO4_SLOT 0x1e
+#define RN5T567_LDO5_SLOT 0x1f
+#define RN5T567_PSO0_SLOT 0x25
+#define RN5T567_PSO1_SLOT 0x26
+#define RN5T567_PSO2_SLOT 0x27
+#define RN5T567_PSO3_SLOT 0x28
#define RN5T567_LDORTC1_SLOT 0x2a
#define RN5T567_DC1CTL 0x2c
#define RN5T567_DC1CTL2 0x2d
#define RN5T567_DC2DAC_SLP 0x3c
#define RN5T567_DC3DAC_SLP 0x3d
#define RN5T567_DC4DAC_SLP 0x3e
-#define RN5T567_IREN 0x40
+#define RN5T567_DCIREN 0x40
+#define RN5T567_DCIRQ 0x41
+#define RN5T567_DCIRMON 0x42
#define RN5T567_LDOEN1 0x44
#define RN5T567_LDOEN2 0x45
#define RN5T567_LDODIS 0x46
#define RN5T567_LDO4DAC 0x4f
#define RN5T567_LDO5DAC 0x50
#define RN5T567_LDORTC1DAC 0x56 /* VBACKUP */
+#define RN5T567_LDORTC2DAC 0x57
#define RN5T567_LDO1DAC_SLP 0x58
#define RN5T567_LDO2DAC_SLP 0x59
#define RN5T567_LDO3DAC_SLP 0x5a
#define NOETIMSET_DIS_OFF_NOE_TIM (1 << 3)
-#define DCnCTL_DCnEN (1 << 0)
-#define DCnCTL_DCnDIS (1 << 1)
+#define DCnCTL_EN (1 << 0)
+#define DCnCTL_DIS (1 << 1)
#define DCnMODE(m) (((m) & 0x3) << 4)
#define DCnMODE_SLP(m) (((m) & 0x3) << 6)
-#define DCnMODE_AUTO 0
-#define DCnMODE_PWM 1
-#define DCnMODE_PSM 2
+#define MODE_AUTO 0
+#define MODE_PWM 1
+#define MODE_PSM 2
+
+#define DCnCTL2_LIMSDEN (1 << 0)
+#define DCnCTL2_LIM_NONE (0 << 1)
+#define DCnCTL2_LIM_LOW (1 << 1)
+#define DCnCTL2_LIM_MED (2 << 1)
+#define DCnCTL2_LIM_HIGH (3 << 1)
+#define DCnCTL2_SR_LOW (2 << 4)
+#define DCnCTL2_SR_MED (1 << 4)
+#define DCnCTL2_SR_HIGH (0 << 4)
+#define DCnCTL2_OSC_LOW (0 << 6)
+#define DCnCTL2_OSC_MED (1 << 6)
+#define DCnCTL2_OSC_HIGH (2 << 6)
/* calculate voltages in 10mV */
#define rn5t_v2r(v,n,m) DIV_ROUND(((((v) * 10 < (n)) ? (n) : (v) * 10) - (n)), m)
{ RN5T567_DC2DAC_SLP, VDD_SOC_VAL_LP, },
{ RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
{ RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
- { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
- { RN5T567_DC2CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
- { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
- { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
+ { RN5T567_DC1CTL, DCnCTL_EN | DCnMODE_SLP(MODE_PSM), },
+ { RN5T567_DC2CTL, DCnCTL_EN | DCnMODE_SLP(MODE_PSM), },
+ { RN5T567_DC3CTL, DCnCTL_EN | DCnMODE_SLP(MODE_PSM), },
+ { RN5T567_DC4CTL, DCnCTL_EN | DCnMODE_SLP(MODE_PSM), },
{ RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
{ RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
{ RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
{ RN5T567_LDODIS, 0x1c, ~0x1f, },
{ RN5T567_INTPOL, 0, },
{ RN5T567_INTEN, 0x3, },
- { RN5T567_IREN, 0xf, },
+ { RN5T567_DCIREN, 0xf, },
{ RN5T567_EN_GPIR, 0, },
};
#endif
#define VDD_RTC_VAL rn5t_mV_to_regval_rtc(3000)
#define VDD_CORE_VAL rn5t_mV_to_regval(1300) /* DCDC1 */
#define VDD_CORE_VAL_LP rn5t_mV_to_regval(900)
-#define VDD_DDR_VAL rn5t_mV_to_regval(1350) /* DCDC3 */
+#define VDD_DDR_VAL rn5t_mV_to_regval(1350) /* DCDC3 SDRAM 1.35V */
#define VDD_DDR_VAL_LP rn5t_mV_to_regval(1350)
-#define VDD_IO_EXT_VAL rn5t_mV_to_regval(3300) /* DCDC4 */
+#define VDD_IO_EXT_VAL rn5t_mV_to_regval(3300) /* DCDC4 eMMC/NAND,VDDIO_EXT 3.0V */
#define VDD_IO_EXT_VAL_LP rn5t_mV_to_regval(3300)
-#define VDD_IO_INT_VAL rn5t_mV_to_regval2(3300) /* LDO1 */
+#define VDD_IO_INT_VAL rn5t_mV_to_regval2(3300) /* LDO1 ENET,GPIO,LCD,SD1,UART,3.3V */
#define VDD_IO_INT_VAL_LP rn5t_mV_to_regval2(3300)
-#define VDD_ADC_VAL rn5t_mV_to_regval2(3300) /* LDO2 */
+#define VDD_ADC_VAL rn5t_mV_to_regval2(3300) /* LDO2 ADC */
#define VDD_ADC_VAL_LP rn5t_mV_to_regval2(3300)
-#define VDD_PMIC_VAL rn5t_mV_to_regval2(2500) /* LDO3 */
+#define VDD_PMIC_VAL rn5t_mV_to_regval2(2500) /* LDO3 PMIC */
#define VDD_PMIC_VAL_LP rn5t_mV_to_regval2(2500)
-#define VDD_CSI_VAL rn5t_mV_to_regval2(3300) /* LDO4 */
+#define VDD_CSI_VAL rn5t_mV_to_regval2(3300) /* LDO4 CSI */
#define VDD_CSI_VAL_LP rn5t_mV_to_regval2(3300)
+#define VDD_LDO5_VAL rn5t_mV_to_regval2(1200) /* LDO5 1.2V */
+#define LDOEN1_LDO1EN (1 << 0)
+#define LDOEN1_LDO2EN (1 << 1)
+#define LDOEN1_LDO3EN (1 << 2)
+#define LDOEN1_LDO4EN (1 << 3)
+#define LDOEN1_LDO5EN (1 << 4)
+#define LDOEN1_VAL (LDOEN1_LDO1EN | LDOEN1_LDO2EN | LDOEN1_LDO3EN | LDOEN1_LDO4EN)
+#define LDOEN1_MASK 0x1f
+#define LDOEN2_LDORTC1EN (1 << 4)
+#define LDOEN2_LDORTC2EN (1 << 5)
+#define LDOEN2_VAL LDOEN2_LDORTC1EN
+#define LDOEN2_MASK 0x30
static struct pmic_regs rn5t567_regs[] = {
{ RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
+ { RN5T567_SLPCNT, 0, },
+ { RN5T567_REPCNT, (3 << 4) | (0 << 1), },
{ RN5T567_DC1DAC, VDD_CORE_VAL, },
{ RN5T567_DC3DAC, VDD_DDR_VAL, },
{ RN5T567_DC4DAC, VDD_IO_EXT_VAL, },
{ RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
{ RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
{ RN5T567_DC4DAC_SLP, VDD_IO_EXT_VAL_LP, },
- { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
- { RN5T567_DC2CTL, DCnCTL_DCnDIS, },
- { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
- { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
+ { RN5T567_DC1CTL, DCnCTL_EN | DCnCTL_DIS | DCnMODE_SLP(MODE_PSM), },
+ { RN5T567_DC2CTL, DCnCTL_DIS, },
+ { RN5T567_DC3CTL, DCnCTL_EN | DCnCTL_DIS | DCnMODE_SLP(MODE_PSM), },
+ { RN5T567_DC4CTL, DCnCTL_EN | DCnCTL_DIS | DCnMODE_SLP(MODE_PSM), },
+ { RN5T567_DC1CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, },
+ { RN5T567_DC2CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, },
+ { RN5T567_DC3CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, },
+ { RN5T567_DC4CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, },
{ RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
{ RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
{ RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
{ RN5T567_LDO2DAC_SLP, VDD_ADC_VAL_LP, },
{ RN5T567_LDO3DAC_SLP, VDD_PMIC_VAL_LP, },
{ RN5T567_LDO4DAC_SLP, VDD_CSI_VAL_LP, },
- { RN5T567_LDOEN1, 0x0f, ~0x1f, },
- { RN5T567_LDOEN2, 0x10, ~0x30, },
- { RN5T567_LDODIS, 0x10, ~0x1f, },
+ { RN5T567_LDO5DAC, VDD_LDO5_VAL, },
+ { RN5T567_LDO1DAC_SLP, VDD_IO_INT_VAL_LP, },
+ { RN5T567_LDO2DAC_SLP, VDD_ADC_VAL_LP, },
+ { RN5T567_LDO3DAC_SLP, VDD_PMIC_VAL_LP, },
+ { RN5T567_LDO4DAC_SLP, VDD_CSI_VAL_LP, },
+ { RN5T567_LDOEN1, LDOEN1_VAL, ~LDOEN1_MASK, },
+ { RN5T567_LDOEN2, LDOEN2_VAL, ~LDOEN2_MASK, },
+ { RN5T567_LDODIS, 0x1f, ~0x1f, },
{ RN5T567_INTPOL, 0, },
{ RN5T567_INTEN, 0x3, },
- { RN5T567_IREN, 0xf, },
+ { RN5T567_DCIREN, 0xf, },
{ RN5T567_EN_GPIR, 0, },
};