Merge branch 'master' into tk71

[mv-sheeva.git] / arch / arm / mach-msm / board-msm8x60.c

diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
new file mode 100644 (file)
index 0000000..9b5eb2b
--- /dev/null
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -0,0 +1,97 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+
+#include <mach/board.h>
+#include <mach/msm_iomap.h>
+
+unsigned long clk_get_max_axi_khz(void)
+{
+       return 0;
+}
+
+static void __init msm8x60_map_io(void)
+{
+       msm_map_msm8x60_io();
+}
+
+static void __init msm8x60_init_irq(void)
+{
+       unsigned int i;
+
+       gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
+                (void *)MSM_QGIC_CPU_BASE);
+
+       /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
+       writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
+
+       /* RUMI does not adhere to GIC spec by enabling STIs by default.
+        * Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
+        */
+       if (!machine_is_msm8x60_sim())
+               writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
+
+       /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
+        * as they are configured as level, which does not play nice with
+        * handle_percpu_irq.
+        */
+       for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
+               if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
+                       set_irq_handler(i, handle_percpu_irq);
+       }
+}
+
+static void __init msm8x60_init(void)
+{
+}
+
+MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
+       .map_io = msm8x60_map_io,
+       .init_irq = msm8x60_init_irq,
+       .init_machine = msm8x60_init,
+       .timer = &msm_timer,
+MACHINE_END
+
+MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
+       .map_io = msm8x60_map_io,
+       .init_irq = msm8x60_init_irq,
+       .init_machine = msm8x60_init,
+       .timer = &msm_timer,
+MACHINE_END
+
+MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
+       .map_io = msm8x60_map_io,
+       .init_irq = msm8x60_init_irq,
+       .init_machine = msm8x60_init,
+       .timer = &msm_timer,
+MACHINE_END
+
+MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
+       .map_io = msm8x60_map_io,
+       .init_irq = msm8x60_init_irq,
+       .init_machine = msm8x60_init,
+       .timer = &msm_timer,
+MACHINE_END