Merge tag 'v2.6.38' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6

[mv-sheeva.git] / arch / arm / plat-mxc / ehci.c

diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index 9915607683de39e08d1145b115bd289fec360da2..8772ce346a584771764e605dc9331d7f47e0c212 100644 (file)
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -49,6 +49,7 @@
 
 #define MXC_OTG_OFFSET         0
 #define MXC_H1_OFFSET          0x200
+#define MXC_H2_OFFSET          0x400
 
 /* USB_CTRL */
 #define MXC_OTG_UCTRL_OWIE_BIT         (1 << 27)       /* OTG wakeup intr enable */
@@ -61,6 +62,11 @@
 #define MXC_OTG_PHYCTRL_OC_DIS_BIT     (1 << 8)        /* OTG Disable Overcurrent Event */
 #define MXC_H1_OC_DIS_BIT                      (1 << 5)        /* UH1 Disable Overcurrent Event */
 
+/* USBH2CTRL */
+#define MXC_H2_UCTRL_H2UIE_BIT         (1 << 8)
+#define MXC_H2_UCTRL_H2WIE_BIT         (1 << 7)
+#define MXC_H2_UCTRL_H2PM_BIT          (1 << 4)
+
 #define MXC_USBCMD_OFFSET                      0x140
 
 /* USBCMD */
@@ -69,9 +75,9 @@
 int mxc_initialize_usb_hw(int port, unsigned int flags)
 {
        unsigned int v;
-#if defined(CONFIG_ARCH_MX25)
+#if defined(CONFIG_SOC_IMX25)
        if (cpu_is_mx25()) {
-               v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR +
+               v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
                                     USBCTRL_OTGBASE_OFFSET));
 
                switch (port) {
@@ -108,14 +114,14 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
                        return -EINVAL;
                }
 
-               writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR +
+               writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
                                     USBCTRL_OTGBASE_OFFSET));
                return 0;
        }
-#endif /* CONFIG_ARCH_MX25 */
+#endif /* if defined(CONFIG_SOC_IMX25) */
 #if defined(CONFIG_ARCH_MX3)
        if (cpu_is_mx31()) {
-               v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
+               v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
                                     USBCTRL_OTGBASE_OFFSET));
 
                switch (port) {
@@ -153,13 +159,13 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
                        return -EINVAL;
                }
 
-               writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
+               writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
                                     USBCTRL_OTGBASE_OFFSET));
                return 0;
        }
 
        if (cpu_is_mx35()) {
-               v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR +
+               v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
                                     USBCTRL_OTGBASE_OFFSET));
 
                switch (port) {
@@ -196,7 +202,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
                        return -EINVAL;
                }
 
-               writel(v, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR +
+               writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
                                     USBCTRL_OTGBASE_OFFSET));
                return 0;
        }
@@ -206,7 +212,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
                /* On i.MX27 we can use the i.MX31 USBCTRL bits, they
                 * are identical
                 */
-               v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR +
+               v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
                                     USBCTRL_OTGBASE_OFFSET));
                switch (port) {
                case 0: /* OTG port */
@@ -241,12 +247,12 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
                default:
                        return -EINVAL;
                }
-               writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR +
+               writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
                                     USBCTRL_OTGBASE_OFFSET));
                return 0;
        }
 #endif /* CONFIG_MACH_MX27 */
-#ifdef CONFIG_ARCH_MX51
+#ifdef CONFIG_SOC_IMX51
        if (cpu_is_mx51()) {
                void __iomem *usb_base;
                void __iomem *usbotg_base;
@@ -254,6 +260,10 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
                int ret = 0;
 
                usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+               if (!usb_base) {
+                       printk(KERN_ERR "%s(): ioremap failed\n", __func__);
+                       return -ENOMEM;
+               }
 
                switch (port) {
                case 0: /* OTG port */
@@ -262,6 +272,9 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
                case 1: /* Host 1 port */
                        usbotg_base = usb_base + MXC_H1_OFFSET;
                        break;
+               case 2: /* Host 2 port */
+                       usbotg_base = usb_base + MXC_H2_OFFSET;
+                       break;
                default:
                        printk(KERN_ERR"%s no such port %d\n", __func__, port);
                        ret = -ENOENT;
@@ -274,10 +287,13 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
                        if (flags & MXC_EHCI_INTERNAL_PHY) {
                                v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
 
-                               if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                                       v |= (MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is not used */
-                               else
-                                       v &= ~(MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is used */
+                               if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
+                                       /* OC/USBPWR is not used */
+                                       v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
+                               } else {
+                                       /* OC/USBPWR is used */
+                                       v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
+                               }
                                __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
 
                                v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
@@ -285,16 +301,23 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
                                        v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
                                else
                                        v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
+                               if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                                       v |= MXC_OTG_UCTRL_OPM_BIT;
+                               else
+                                       v &= ~MXC_OTG_UCTRL_OPM_BIT;
                                __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
                        }
                        break;
                case 1: /* Host 1 */
                        /*Host ULPI */
                        v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
-                       if (flags & MXC_EHCI_WAKEUP_ENABLED)
-                               v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */
-                       else
-                               v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */
+                       if (flags & MXC_EHCI_WAKEUP_ENABLED) {
+                               /* HOST1 wakeup/ULPI intr enable */
+                               v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
+                       } else {
+                               /* HOST1 wakeup/ULPI intr disable */
+                               v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
+                       }
 
                        if (flags & MXC_EHCI_POWER_PINS_ENABLED)
                                v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
@@ -315,6 +338,22 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
                                v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
                        __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
                        break;
+               case 2: /* Host 2 ULPI */
+                       v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
+                       if (flags & MXC_EHCI_WAKEUP_ENABLED) {
+                               /* HOST1 wakeup/ULPI intr enable */
+                               v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
+                       } else {
+                               /* HOST1 wakeup/ULPI intr disable */
+                               v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
+                       }
+
+                       if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                               v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
+                       else
+                               v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
+                       __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
+                       break;
                }
 
 error: