Merge branch 'master' into tk71

[mv-sheeva.git] / arch / arm / plat-s5p / include / plat / irqs.h

diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h
index 3fb3a3a1746505fc376e20a13cdfe153842db8cb..ba9121c60a2a7ba919fdb1c1653c29f818ca0d9a 100644 (file)
--- a/arch/arm/plat-s5p/include/plat/irqs.h
+++ b/arch/arm/plat-s5p/include/plat/irqs.h
@@ -94,4 +94,22 @@
                                                ((irq) - S5P_EINT_BASE1) : \
                                                ((irq) + 16 - S5P_EINT_BASE2))
 
+#define IRQ_EINT_BIT(x)                EINT_OFFSET(x)
+
+/* Typically only a few gpio chips require gpio interrupt support.
+   To avoid memory waste irq descriptors are allocated only for
+   S5P_GPIOINT_GROUP_COUNT chips, each with total number of
+   S5P_GPIOINT_GROUP_SIZE pins/irqs. Each GPIOINT group can be assiged
+   to any gpio chip with the s5p_register_gpio_interrupt() function */
+#define S5P_GPIOINT_GROUP_COUNT 4
+#define S5P_GPIOINT_GROUP_SIZE 8
+#define S5P_GPIOINT_COUNT      (S5P_GPIOINT_GROUP_COUNT * S5P_GPIOINT_GROUP_SIZE)
+
+/* IRQ types common for all s5p platforms */
+#define S5P_IRQ_TYPE_LEVEL_LOW         (0x00)
+#define S5P_IRQ_TYPE_LEVEL_HIGH                (0x01)
+#define S5P_IRQ_TYPE_EDGE_FALLING      (0x02)
+#define S5P_IRQ_TYPE_EDGE_RISING       (0x03)
+#define S5P_IRQ_TYPE_EDGE_BOTH         (0x04)
+
 #endif /* __ASM_PLAT_S5P_IRQS_H */