Merge tag 'v2.6.38' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6

[mv-sheeva.git] / arch / arm / plat-s5p / include / plat / regs-srom.h

diff --git a/arch/arm/plat-s5p/include/plat/regs-srom.h b/arch/arm/plat-s5p/include/plat/regs-srom.h
new file mode 100644 (file)
index 0000000..f121ab5
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/regs-srom.h
@@ -0,0 +1,54 @@
+/* linux/arch/arm/plat-s5p/include/plat/regs-srom.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * S5P SROMC register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_S5P_REGS_SROM_H
+#define __ASM_PLAT_S5P_REGS_SROM_H __FILE__
+
+#include <mach/map.h>
+
+#define S5P_SROMREG(x)         (S5P_VA_SROMC + (x))
+
+#define S5P_SROM_BW            S5P_SROMREG(0x0)
+#define S5P_SROM_BC0           S5P_SROMREG(0x4)
+#define S5P_SROM_BC1           S5P_SROMREG(0x8)
+#define S5P_SROM_BC2           S5P_SROMREG(0xc)
+#define S5P_SROM_BC3           S5P_SROMREG(0x10)
+#define S5P_SROM_BC4           S5P_SROMREG(0x14)
+#define S5P_SROM_BC5           S5P_SROMREG(0x18)
+
+/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
+
+#define S5P_SROM_BW__DATAWIDTH__SHIFT          0
+#define S5P_SROM_BW__ADDRMODE__SHIFT           1
+#define S5P_SROM_BW__WAITENABLE__SHIFT         2
+#define S5P_SROM_BW__BYTEENABLE__SHIFT         3
+
+#define S5P_SROM_BW__CS_MASK                   0xf
+
+#define S5P_SROM_BW__NCS0__SHIFT               0
+#define S5P_SROM_BW__NCS1__SHIFT               4
+#define S5P_SROM_BW__NCS2__SHIFT               8
+#define S5P_SROM_BW__NCS3__SHIFT               12
+#define S5P_SROM_BW__NCS4__SHIFT               16
+#define S5P_SROM_BW__NCS5__SHIFT               20
+
+/* applies to same to BCS0 - BCS3 */
+
+#define S5P_SROM_BCX__PMC__SHIFT               0
+#define S5P_SROM_BCX__TACP__SHIFT              4
+#define S5P_SROM_BCX__TCAH__SHIFT              8
+#define S5P_SROM_BCX__TCOH__SHIFT              12
+#define S5P_SROM_BCX__TACC__SHIFT              16
+#define S5P_SROM_BCX__TCOS__SHIFT              24
+#define S5P_SROM_BCX__TACS__SHIFT              28
+
+#endif /* __ASM_PLAT_S5P_REGS_SROM_H */