m32r: Cleanup direct irq_desc access

[mv-sheeva.git] / arch / m32r / platforms / oaks32r / setup.c

diff --git a/arch/m32r/platforms/oaks32r/setup.c b/arch/m32r/platforms/oaks32r/setup.c
index d11d93bf74f52bd4b14baea3e6fc3da16d83b271..43bf5a0c95151be1acb15998c0cf78900f809196 100644 (file)
--- a/arch/m32r/platforms/oaks32r/setup.c
+++ b/arch/m32r/platforms/oaks32r/setup.c
@@ -83,52 +83,34 @@ void __init init_IRQ(void)
 
 #ifdef CONFIG_NE2000
        /* INT3 : LAN controller (RTL8019AS) */
-       irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
-       irq_desc[M32R_IRQ_INT3].chip = &oaks32r_irq_type;
-       irq_desc[M32R_IRQ_INT3].action = 0;
-       irq_desc[M32R_IRQ_INT3].depth = 1;
+       set_irq_chip(M32R_IRQ_INT3, &oaks32r_irq_type);
        icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
        disable_oaks32r_irq(M32R_IRQ_INT3);
 #endif /* CONFIG_M32R_NE2000 */
 
        /* MFT2 : system timer */
-       irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
-       irq_desc[M32R_IRQ_MFT2].chip = &oaks32r_irq_type;
-       irq_desc[M32R_IRQ_MFT2].action = 0;
-       irq_desc[M32R_IRQ_MFT2].depth = 1;
+       set_irq_chip(M32R_IRQ_MFT2, &oaks32r_irq_type);
        icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
        disable_oaks32r_irq(M32R_IRQ_MFT2);
 
 #ifdef CONFIG_SERIAL_M32R_SIO
        /* SIO0_R : uart receive data */
-       irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
-       irq_desc[M32R_IRQ_SIO0_R].chip = &oaks32r_irq_type;
-       irq_desc[M32R_IRQ_SIO0_R].action = 0;
-       irq_desc[M32R_IRQ_SIO0_R].depth = 1;
+       set_irq_chip(M32R_IRQ_SIO0_R, &oaks32r_irq_type);
        icu_data[M32R_IRQ_SIO0_R].icucr = 0;
        disable_oaks32r_irq(M32R_IRQ_SIO0_R);
 
        /* SIO0_S : uart send data */
-       irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
-       irq_desc[M32R_IRQ_SIO0_S].chip = &oaks32r_irq_type;
-       irq_desc[M32R_IRQ_SIO0_S].action = 0;
-       irq_desc[M32R_IRQ_SIO0_S].depth = 1;
+       set_irq_chip(M32R_IRQ_SIO0_S, &oaks32r_irq_type);
        icu_data[M32R_IRQ_SIO0_S].icucr = 0;
        disable_oaks32r_irq(M32R_IRQ_SIO0_S);
 
        /* SIO1_R : uart receive data */
-       irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
-       irq_desc[M32R_IRQ_SIO1_R].chip = &oaks32r_irq_type;
-       irq_desc[M32R_IRQ_SIO1_R].action = 0;
-       irq_desc[M32R_IRQ_SIO1_R].depth = 1;
+       set_irq_chip(M32R_IRQ_SIO1_R, &oaks32r_irq_type);
        icu_data[M32R_IRQ_SIO1_R].icucr = 0;
        disable_oaks32r_irq(M32R_IRQ_SIO1_R);
 
        /* SIO1_S : uart send data */
-       irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
-       irq_desc[M32R_IRQ_SIO1_S].chip = &oaks32r_irq_type;
-       irq_desc[M32R_IRQ_SIO1_S].action = 0;
-       irq_desc[M32R_IRQ_SIO1_S].depth = 1;
+       set_irq_chip(M32R_IRQ_SIO1_S, &oaks32r_irq_type);
        icu_data[M32R_IRQ_SIO1_S].icucr = 0;
        disable_oaks32r_irq(M32R_IRQ_SIO1_S);
 #endif /* CONFIG_SERIAL_M32R_SIO */