MIPS, Perf-events: Work with the new PMU interface

[mv-sheeva.git] / arch / mips / kernel / perf_event_mipsxx.c

diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 183e0d226669193700c72f405f1e4e43303612a4..d9a7db78ed62bd1b38bf9401eacdb3c7332ae6f2 100644 (file)
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -696,7 +696,7 @@ static int mipsxx_pmu_handle_shared_irq(void)
         * interrupt, not NMI.
         */
        if (handled == IRQ_HANDLED)
-               perf_event_do_pending();
+               irq_work_run();
 
 #ifdef CONFIG_MIPS_MT_SMP
        read_unlock(&pmuint_rwlock);
@@ -1045,6 +1045,8 @@ init_hw_perf_events(void)
                        "CPU, irq %d%s\n", mipspmu->name, counters, irq,
                        irq < 0 ? " (share with timer interrupt)" : "");
 
+       perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
+
        return 0;
 }
 early_initcall(init_hw_perf_events);