Merge tag 'v2.6.38' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6

[mv-sheeva.git] / arch / x86 / kernel / aperture_64.c

diff --git a/arch/x86/kernel/aperture_64.c b/arch/x86/kernel/aperture_64.c
index b3a16e8f0703d47f50a354223bfe8c6e9382126e..5955a7800a96637d2336b1a568f2f9882ad8689b 100644 (file)
--- a/arch/x86/kernel/aperture_64.c
+++ b/arch/x86/kernel/aperture_64.c
@@ -39,18 +39,6 @@ int fallback_aper_force __initdata;
 
 int fix_aperture __initdata = 1;
 
-struct bus_dev_range {
-       int bus;
-       int dev_base;
-       int dev_limit;
-};
-
-static struct bus_dev_range bus_dev_ranges[] __initdata = {
-       { 0x00, 0x18, 0x20},
-       { 0xff, 0x00, 0x20},
-       { 0xfe, 0x00, 0x20}
-};
-
 static struct resource gart_resource = {
        .name   = "GART",
        .flags  = IORESOURCE_MEM,
@@ -206,7 +194,7 @@ static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)
  * Do an PCI bus scan by hand because we're running before the PCI
  * subsystem.
  *
- * All K8 AGP bridges are AGPv3 compliant, so we can do this scan
+ * All AMD AGP bridges are AGPv3 compliant, so we can do this scan
  * generically. It's probably overkill to always scan all slots because
  * the AGP bridges should be always an own bus on the HT hierarchy,
  * but do it here for future safety.
@@ -294,16 +282,16 @@ void __init early_gart_iommu_check(void)
        search_agp_bridge(&agp_aper_order, &valid_agp);
 
        fix = 0;
-       for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
+       for (i = 0; amd_nb_bus_dev_ranges[i].dev_limit; i++) {
                int bus;
                int dev_base, dev_limit;
 
-               bus = bus_dev_ranges[i].bus;
-               dev_base = bus_dev_ranges[i].dev_base;
-               dev_limit = bus_dev_ranges[i].dev_limit;
+               bus = amd_nb_bus_dev_ranges[i].bus;
+               dev_base = amd_nb_bus_dev_ranges[i].dev_base;
+               dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
 
                for (slot = dev_base; slot < dev_limit; slot++) {
-                       if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
+                       if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
                                continue;
 
                        ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
@@ -349,16 +337,16 @@ void __init early_gart_iommu_check(void)
                return;
 
        /* disable them all at first */
-       for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
+       for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
                int bus;
                int dev_base, dev_limit;
 
-               bus = bus_dev_ranges[i].bus;
-               dev_base = bus_dev_ranges[i].dev_base;
-               dev_limit = bus_dev_ranges[i].dev_limit;
+               bus = amd_nb_bus_dev_ranges[i].bus;
+               dev_base = amd_nb_bus_dev_ranges[i].dev_base;
+               dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
 
                for (slot = dev_base; slot < dev_limit; slot++) {
-                       if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
+                       if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
                                continue;
 
                        ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
@@ -390,17 +378,17 @@ int __init gart_iommu_hole_init(void)
 
        fix = 0;
        node = 0;
-       for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
+       for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
                int bus;
                int dev_base, dev_limit;
                u32 ctl;
 
-               bus = bus_dev_ranges[i].bus;
-               dev_base = bus_dev_ranges[i].dev_base;
-               dev_limit = bus_dev_ranges[i].dev_limit;
+               bus = amd_nb_bus_dev_ranges[i].bus;
+               dev_base = amd_nb_bus_dev_ranges[i].dev_base;
+               dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
 
                for (slot = dev_base; slot < dev_limit; slot++) {
-                       if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
+                       if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
                                continue;
 
                        iommu_detected = 1;
@@ -505,7 +493,7 @@ out:
        }
 
        /* Fix up the north bridges */
-       for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
+       for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
                int bus, dev_base, dev_limit;
 
                /*
@@ -514,11 +502,11 @@ out:
                 */
                u32 ctl = DISTLBWALKPRB | aper_order << 1;
 
-               bus = bus_dev_ranges[i].bus;
-               dev_base = bus_dev_ranges[i].dev_base;
-               dev_limit = bus_dev_ranges[i].dev_limit;
+               bus = amd_nb_bus_dev_ranges[i].bus;
+               dev_base = amd_nb_bus_dev_ranges[i].dev_base;
+               dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
                for (slot = dev_base; slot < dev_limit; slot++) {
-                       if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
+                       if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
                                continue;
 
                        write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);