Merge branch 'drm-intel-fixes' into drm-intel-next

[mv-sheeva.git] / drivers / gpu / drm / i915 / intel_display.c

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bee24b1a58e86b5dc1d1c038f8f1a653848bec97..3fa5aaa941d2dd9b54c4441d5180885672b5f6c2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1461,7 +1461,7 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
                BUG();
        }
 
-       ret = i915_gem_object_pin(obj, alignment);
+       ret = i915_gem_object_pin(obj, alignment, true);
        if (ret)
                return ret;
 
@@ -1474,8 +1474,7 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
         * framebuffer compression.  For simplicity, we always install
         * a fence as the cost is not that onerous.
         */
-       if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
-           obj_priv->tiling_mode != I915_TILING_NONE) {
+       if (obj_priv->tiling_mode != I915_TILING_NONE) {
                ret = i915_gem_object_get_fence_reg(obj, false);
                if (ret)
                        goto err_unpin;
@@ -1996,17 +1995,17 @@ static void intel_flush_display_plane(struct drm_device *dev,
 static void intel_clear_scanline_wait(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
+       struct intel_ring_buffer *ring;
        u32 tmp;
 
        if (IS_GEN2(dev))
                /* Can't break the hang on i8xx */
                return;
 
-       tmp = I915_READ(PRB0_CTL);
-       if (tmp & RING_WAIT) {
-               I915_WRITE(PRB0_CTL, tmp);
-               POSTING_READ(PRB0_CTL);
-       }
+       ring = &dev_priv->render_ring;
+       tmp = I915_READ_CTL(ring);
+       if (tmp & RING_WAIT)
+               I915_WRITE_CTL(ring, tmp);
 }
 
 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
@@ -4378,7 +4377,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
        /* we only need to pin inside GTT if cursor is non-phy */
        mutex_lock(&dev->struct_mutex);
        if (!dev_priv->info->cursor_needs_physical) {
-               ret = i915_gem_object_pin(bo, PAGE_SIZE);
+               ret = i915_gem_object_pin(bo, PAGE_SIZE, true);
                if (ret) {
                        DRM_ERROR("failed to pin cursor bo\n");
                        goto fail_locked;
@@ -5115,22 +5114,16 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
        if (ret)
                goto cleanup_objs;
 
-       /* Block clients from rendering to the new back buffer until
-        * the flip occurs and the object is no longer visible.
-        */
-       atomic_add(1 << intel_crtc->plane,
-                  &to_intel_bo(work->old_fb_obj)->pending_flip);
-
-       work->pending_flip_obj = obj;
-       obj_priv = to_intel_bo(obj);
-
        if (IS_GEN3(dev) || IS_GEN2(dev)) {
                u32 flip_mask;
 
                /* Can't queue multiple flips, so wait for the previous
                 * one to finish before executing the next.
                 */
-               BEGIN_LP_RING(2);
+               ret = BEGIN_LP_RING(2);
+               if (ret)
+                       goto cleanup_objs;
+
                if (intel_crtc->plane)
                        flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
                else
@@ -5140,13 +5133,25 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
                ADVANCE_LP_RING();
        }
 
+       work->pending_flip_obj = obj;
+       obj_priv = to_intel_bo(obj);
+
        work->enable_stall_check = true;
 
        /* Offset into the new buffer for cases of shared fbs between CRTCs */
        offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
 
-       BEGIN_LP_RING(4);
-       switch(INTEL_INFO(dev)->gen) {
+       ret = BEGIN_LP_RING(4);
+       if (ret)
+               goto cleanup_objs;
+
+       /* Block clients from rendering to the new back buffer until
+        * the flip occurs and the object is no longer visible.
+        */
+       atomic_add(1 << intel_crtc->plane,
+                  &to_intel_bo(work->old_fb_obj)->pending_flip);
+
+       switch (INTEL_INFO(dev)->gen) {
        case 2:
                OUT_RING(MI_DISPLAY_FLIP |
                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
@@ -5536,7 +5541,7 @@ intel_alloc_context_page(struct drm_device *dev)
        }
 
        mutex_lock(&dev->struct_mutex);
-       ret = i915_gem_object_pin(ctx, 4096);
+       ret = i915_gem_object_pin(ctx, 4096, true);
        if (ret) {
                DRM_ERROR("failed to pin power context: %d\n", ret);
                goto err_unref;
@@ -5824,6 +5829,16 @@ void intel_init_clock_gating(struct drm_device *dev)
                                   ILK_DPFC_DIS2 |
                                   ILK_CLK_FBC);
                }
+
+               I915_WRITE(ILK_DISPLAY_CHICKEN2,
+                          I915_READ(ILK_DISPLAY_CHICKEN2) |
+                          ILK_ELPIN_409_SELECT);
+
+               if (IS_GEN5(dev)) {
+                       I915_WRITE(_3D_CHICKEN2,
+                                  _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
+                                  _3D_CHICKEN2_WM_READ_PIPELINED);
+               }
                return;
        } else if (IS_G4X(dev)) {
                uint32_t dspclk_gate;
@@ -5874,16 +5889,17 @@ void intel_init_clock_gating(struct drm_device *dev)
                        struct drm_i915_gem_object *obj_priv;
                        obj_priv = to_intel_bo(dev_priv->renderctx);
                        if (obj_priv) {
-                               BEGIN_LP_RING(4);
-                               OUT_RING(MI_SET_CONTEXT);
-                               OUT_RING(obj_priv->gtt_offset |
-                                               MI_MM_SPACE_GTT |
-                                               MI_SAVE_EXT_STATE_EN |
-                                               MI_RESTORE_EXT_STATE_EN |
-                                               MI_RESTORE_INHIBIT);
-                               OUT_RING(MI_NOOP);
-                               OUT_RING(MI_FLUSH);
-                               ADVANCE_LP_RING();
+                               if (BEGIN_LP_RING(4) == 0) {
+                                       OUT_RING(MI_SET_CONTEXT);
+                                       OUT_RING(obj_priv->gtt_offset |
+                                                MI_MM_SPACE_GTT |
+                                                MI_SAVE_EXT_STATE_EN |
+                                                MI_RESTORE_EXT_STATE_EN |
+                                                MI_RESTORE_INHIBIT);
+                                       OUT_RING(MI_NOOP);
+                                       OUT_RING(MI_FLUSH);
+                                       ADVANCE_LP_RING();
+                               }
                        }
                } else
                        DRM_DEBUG_KMS("Failed to allocate render context."