Merge branch 'master' into tk71

[mv-sheeva.git] / drivers / gpu / drm / nouveau / nv40_fb.c

diff --git a/drivers/gpu/drm/nouveau/nv40_fb.c b/drivers/gpu/drm/nouveau/nv40_fb.c
index 3cd07d8d5bd7a93c27f118dc5923991954a35d23..f3d9c0505f7bbc38f52d43937a1f366eab5b8839 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv40_fb.c
+++ b/drivers/gpu/drm/nouveau/nv40_fb.c
@@ -4,26 +4,22 @@
 #include "nouveau_drm.h"
 
 void
-nv40_fb_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
-                         uint32_t size, uint32_t pitch)
+nv40_fb_set_tile_region(struct drm_device *dev, int i)
 {
        struct drm_nouveau_private *dev_priv = dev->dev_private;
-       uint32_t limit = max(1u, addr + size) - 1;
-
-       if (pitch)
-               addr |= 1;
+       struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
 
        switch (dev_priv->chipset) {
        case 0x40:
-               nv_wr32(dev, NV10_PFB_TLIMIT(i), limit);
-               nv_wr32(dev, NV10_PFB_TSIZE(i), pitch);
-               nv_wr32(dev, NV10_PFB_TILE(i), addr);
+               nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit);
+               nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch);
+               nv_wr32(dev, NV10_PFB_TILE(i), tile->addr);
                break;
 
        default:
-               nv_wr32(dev, NV40_PFB_TLIMIT(i), limit);
-               nv_wr32(dev, NV40_PFB_TSIZE(i), pitch);
-               nv_wr32(dev, NV40_PFB_TILE(i), addr);
+               nv_wr32(dev, NV40_PFB_TLIMIT(i), tile->limit);
+               nv_wr32(dev, NV40_PFB_TSIZE(i), tile->pitch);
+               nv_wr32(dev, NV40_PFB_TILE(i), tile->addr);
                break;
        }
 }
@@ -64,7 +60,7 @@ nv40_fb_init(struct drm_device *dev)
 
        /* Turn all the tiling regions off. */
        for (i = 0; i < pfb->num_tiles; i++)
-               pfb->set_region_tiling(dev, i, 0, 0, 0);
+               pfb->set_tile_region(dev, i);
 
        return 0;
 }