drm/radeon: fix page flipping hangs on r300/r400

[mv-sheeva.git] / drivers / gpu / drm / radeon / r100.c

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 56deae5bf02e9dbff8066136d961a9f4ba52bf8f..79de991e1ea397a0e2459dac747796904369bf86 100644 (file)
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -70,23 +70,6 @@ MODULE_FIRMWARE(FIRMWARE_R520);
 
 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
 {
-       struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
-       u32 tmp;
-
-       /* make sure flip is at vb rather than hb */
-       tmp = RREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset);
-       tmp &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
-       /* make sure pending bit is asserted */
-       tmp |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
-       WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, tmp);
-
-       /* set pageflip to happen as late as possible in the vblank interval.
-        * same field for crtc1/2
-        */
-       tmp = RREG32(RADEON_CRTC_GEN_CNTL);
-       tmp &= ~RADEON_CRTC_VSTAT_MODE_MASK;
-       WREG32(RADEON_CRTC_GEN_CNTL, tmp);
-
        /* enable the pflip int */
        radeon_irq_kms_pflip_irq_get(rdev, crtc);
 }
@@ -3490,7 +3473,7 @@ void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track
                track->num_texture = 16;
                track->maxy = 4096;
                track->separate_cube = 0;
-               track->aaresolve = true;
+               track->aaresolve = false;
                track->aa.robj = NULL;
        }
 
@@ -3801,8 +3784,6 @@ static int r100_startup(struct radeon_device *rdev)
        r100_mc_program(rdev);
        /* Resume clock */
        r100_clock_startup(rdev);
-       /* Initialize GPU configuration (# pipes, ...) */
-//     r100_gpu_init(rdev);
        /* Initialize GART (initialize after TTM so we can allocate
         * memory through TTM but finalize after TTM) */
        r100_enable_bm(rdev);