Merge tag 'v2.6.38' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6

[mv-sheeva.git] / drivers / staging / spectra / lld_nand.c

diff --git a/drivers/staging/spectra/lld_nand.c b/drivers/staging/spectra/lld_nand.c
index 0d647a8fd2b6a6fa2283976dc7d57a51367f526c..2263d3ea5456e3522e79c979c439a33d2dfa77b3 100644 (file)
--- a/drivers/staging/spectra/lld_nand.c
+++ b/drivers/staging/spectra/lld_nand.c
@@ -2395,14 +2395,94 @@ static int nand_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
        unsigned long csr_base;
        unsigned long csr_len;
        struct mrst_nand_info *pndev = &info;
+       u32 int_mask;
 
        nand_dbg_print(NAND_DBG_WARN, "%s, Line %d, Function: %s\n",
                       __FILE__, __LINE__, __func__);
 
+       FlashReg = ioremap_nocache(GLOB_HWCTL_REG_BASE,
+                       GLOB_HWCTL_REG_SIZE);
+       if (!FlashReg) {
+               printk(KERN_ERR "Spectra: ioremap_nocache failed!");
+               return -ENOMEM;
+       }
+       nand_dbg_print(NAND_DBG_WARN,
+               "Spectra: Remapped reg base address: "
+               "0x%p, len: %d\n",
+               FlashReg, GLOB_HWCTL_REG_SIZE);
+
+       FlashMem = ioremap_nocache(GLOB_HWCTL_MEM_BASE,
+                       GLOB_HWCTL_MEM_SIZE);
+       if (!FlashMem) {
+               printk(KERN_ERR "Spectra: ioremap_nocache failed!");
+               iounmap(FlashReg);
+               return -ENOMEM;
+       }
+       nand_dbg_print(NAND_DBG_WARN,
+               "Spectra: Remapped flash base address: "
+               "0x%p, len: %d\n",
+               (void *)FlashMem, GLOB_HWCTL_MEM_SIZE);
+
+       nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:"
+                       "acc_clks: %d, re_2_we: %d, we_2_re: %d,"
+                       "addr_2_data: %d, rdwr_en_lo_cnt: %d, "
+                       "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
+                       ioread32(FlashReg + ACC_CLKS),
+                       ioread32(FlashReg + RE_2_WE),
+                       ioread32(FlashReg + WE_2_RE),
+                       ioread32(FlashReg + ADDR_2_DATA),
+                       ioread32(FlashReg + RDWR_EN_LO_CNT),
+                       ioread32(FlashReg + RDWR_EN_HI_CNT),
+                       ioread32(FlashReg + CS_SETUP_CNT));
+
+       NAND_Flash_Reset();
+
+       iowrite32(0, FlashReg + GLOBAL_INT_ENABLE);
+
+#if CMD_DMA
+       info.pcmds_num = 0;
+       info.flash_bank = 0;
+       info.cdma_num = 0;
+       int_mask = (DMA_INTR__DESC_COMP_CHANNEL0 |
+               DMA_INTR__DESC_COMP_CHANNEL1 |
+               DMA_INTR__DESC_COMP_CHANNEL2 |
+               DMA_INTR__DESC_COMP_CHANNEL3 |
+               DMA_INTR__MEMCOPY_DESC_COMP);
+       iowrite32(int_mask, FlashReg + DMA_INTR_EN);
+       iowrite32(0xFFFF, FlashReg + DMA_INTR);
+
+       int_mask = (INTR_STATUS0__ECC_ERR |
+               INTR_STATUS0__PROGRAM_FAIL |
+               INTR_STATUS0__ERASE_FAIL);
+#else
+       int_mask = INTR_STATUS0__DMA_CMD_COMP |
+               INTR_STATUS0__ECC_TRANSACTION_DONE |
+               INTR_STATUS0__ECC_ERR |
+               INTR_STATUS0__PROGRAM_FAIL |
+               INTR_STATUS0__ERASE_FAIL;
+#endif
+       iowrite32(int_mask, FlashReg + INTR_EN0);
+       iowrite32(int_mask, FlashReg + INTR_EN1);
+       iowrite32(int_mask, FlashReg + INTR_EN2);
+       iowrite32(int_mask, FlashReg + INTR_EN3);
+
+       /* Clear all status bits */
+       iowrite32(0xFFFF, FlashReg + INTR_STATUS0);
+       iowrite32(0xFFFF, FlashReg + INTR_STATUS1);
+       iowrite32(0xFFFF, FlashReg + INTR_STATUS2);
+       iowrite32(0xFFFF, FlashReg + INTR_STATUS3);
+
+       iowrite32(0x0F, FlashReg + RB_PIN_ENABLED);
+       iowrite32(CHIP_EN_DONT_CARE__FLAG, FlashReg + CHIP_ENABLE_DONT_CARE);
+
+       /* Should set value for these registers when init */
+       iowrite32(0, FlashReg + TWO_ROW_ADDR_CYCLES);
+       iowrite32(1, FlashReg + ECC_ENABLE);
+       enable_ecc = 1;
        ret = pci_enable_device(dev);
        if (ret) {
                printk(KERN_ERR "Spectra: pci_enable_device failed.\n");
-               return ret;
+               goto failed_req_csr;
        }
 
        pci_set_master(dev);
@@ -2461,12 +2541,26 @@ static int nand_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 
        pci_set_drvdata(dev, pndev);
 
+       ret = GLOB_LLD_Read_Device_ID();
+       if (ret) {
+               iounmap(pndev->ioaddr);
+               goto failed_remap_csr;
+       }
+
+       ret = register_spectra_ftl();
+       if (ret) {
+               iounmap(pndev->ioaddr);
+               goto failed_remap_csr;
+       }
+
        return 0;
 
 failed_remap_csr:
        pci_release_regions(dev);
 failed_req_csr:
        pci_disable_device(dev);
+       iounmap(FlashMem);
+       iounmap(FlashReg);
 
        return ret;
 }
@@ -2498,91 +2592,10 @@ static struct pci_driver nand_pci_driver = {
 int NAND_Flash_Init(void)
 {
        int retval;
-       u32 int_mask;
 
        nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
                       __FILE__, __LINE__, __func__);
 
-       FlashReg = ioremap_nocache(GLOB_HWCTL_REG_BASE,
-                       GLOB_HWCTL_REG_SIZE);
-       if (!FlashReg) {
-               printk(KERN_ERR "Spectra: ioremap_nocache failed!");
-               return -ENOMEM;
-       }
-       nand_dbg_print(NAND_DBG_WARN,
-               "Spectra: Remapped reg base address: "
-               "0x%p, len: %d\n",
-               FlashReg, GLOB_HWCTL_REG_SIZE);
-
-       FlashMem = ioremap_nocache(GLOB_HWCTL_MEM_BASE,
-                       GLOB_HWCTL_MEM_SIZE);
-       if (!FlashMem) {
-               printk(KERN_ERR "Spectra: ioremap_nocache failed!");
-               iounmap(FlashReg);
-               return -ENOMEM;
-       }
-       nand_dbg_print(NAND_DBG_WARN,
-               "Spectra: Remapped flash base address: "
-               "0x%p, len: %d\n",
-               (void *)FlashMem, GLOB_HWCTL_MEM_SIZE);
-
-       nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:"
-                       "acc_clks: %d, re_2_we: %d, we_2_re: %d,"
-                       "addr_2_data: %d, rdwr_en_lo_cnt: %d, "
-                       "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
-                       ioread32(FlashReg + ACC_CLKS),
-                       ioread32(FlashReg + RE_2_WE),
-                       ioread32(FlashReg + WE_2_RE),
-                       ioread32(FlashReg + ADDR_2_DATA),
-                       ioread32(FlashReg + RDWR_EN_LO_CNT),
-                       ioread32(FlashReg + RDWR_EN_HI_CNT),
-                       ioread32(FlashReg + CS_SETUP_CNT));
-
-       NAND_Flash_Reset();
-
-       iowrite32(0, FlashReg + GLOBAL_INT_ENABLE);
-
-#if CMD_DMA
-       info.pcmds_num = 0;
-       info.flash_bank = 0;
-       info.cdma_num = 0;
-       int_mask = (DMA_INTR__DESC_COMP_CHANNEL0 |
-               DMA_INTR__DESC_COMP_CHANNEL1 |
-               DMA_INTR__DESC_COMP_CHANNEL2 |
-               DMA_INTR__DESC_COMP_CHANNEL3 |
-               DMA_INTR__MEMCOPY_DESC_COMP);
-       iowrite32(int_mask, FlashReg + DMA_INTR_EN);
-       iowrite32(0xFFFF, FlashReg + DMA_INTR);
-
-       int_mask = (INTR_STATUS0__ECC_ERR |
-               INTR_STATUS0__PROGRAM_FAIL |
-               INTR_STATUS0__ERASE_FAIL);
-#else
-       int_mask = INTR_STATUS0__DMA_CMD_COMP |
-               INTR_STATUS0__ECC_TRANSACTION_DONE |
-               INTR_STATUS0__ECC_ERR |
-               INTR_STATUS0__PROGRAM_FAIL |
-               INTR_STATUS0__ERASE_FAIL;
-#endif
-       iowrite32(int_mask, FlashReg + INTR_EN0);
-       iowrite32(int_mask, FlashReg + INTR_EN1);
-       iowrite32(int_mask, FlashReg + INTR_EN2);
-       iowrite32(int_mask, FlashReg + INTR_EN3);
-
-       /* Clear all status bits */
-       iowrite32(0xFFFF, FlashReg + INTR_STATUS0);
-       iowrite32(0xFFFF, FlashReg + INTR_STATUS1);
-       iowrite32(0xFFFF, FlashReg + INTR_STATUS2);
-       iowrite32(0xFFFF, FlashReg + INTR_STATUS3);
-
-       iowrite32(0x0F, FlashReg + RB_PIN_ENABLED);
-       iowrite32(CHIP_EN_DONT_CARE__FLAG, FlashReg + CHIP_ENABLE_DONT_CARE);
-
-       /* Should set value for these registers when init */
-       iowrite32(0, FlashReg + TWO_ROW_ADDR_CYCLES);
-       iowrite32(1, FlashReg + ECC_ENABLE);
-       enable_ecc = 1;
-
        retval = pci_register_driver(&nand_pci_driver);
        if (retval)
                return -ENOMEM;