static char driver_name[] = "vme_tsi148";
-static const struct pci_device_id tsi148_ids[] = {
+static DEFINE_PCI_DEVICE_TABLE(tsi148_ids) = {
{ PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) },
{ },
};
u32 serviced = 0;
if (channel_mask & TSI148_LCSR_INTS_DMA0S) {
- wake_up(&(bridge->dma_queue[0]));
+ wake_up(&bridge->dma_queue[0]);
serviced |= TSI148_LCSR_INTC_DMA0C;
}
if (channel_mask & TSI148_LCSR_INTS_DMA1S) {
- wake_up(&(bridge->dma_queue[1]));
+ wake_up(&bridge->dma_queue[1]);
serviced |= TSI148_LCSR_INTC_DMA1C;
}
if (error) {
error->address = error_addr;
error->attributes = error_attrib;
- list_add_tail(&(error->list), &(tsi148_bridge->vme_errors));
+ list_add_tail(&error->list, &tsi148_bridge->vme_errors);
} else {
dev_err(tsi148_bridge->parent, "Unable to alloc memory for "
"VMEbus Error reporting\n");
*/
static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge)
{
- wake_up(&(bridge->iack_queue));
+ wake_up(&bridge->iack_queue);
return TSI148_LCSR_INTC_IACKC;
}
bridge = tsi148_bridge->driver_priv;
/* Initialise list for VME bus errors */
- INIT_LIST_HEAD(&(tsi148_bridge->vme_errors));
+ INIT_LIST_HEAD(&tsi148_bridge->vme_errors);
- mutex_init(&(tsi148_bridge->irq_mtx));
+ mutex_init(&tsi148_bridge->irq_mtx);
result = request_irq(pdev->irq,
tsi148_irqhandler,
return 0;
}
-static void tsi148_irq_exit(struct tsi148_driver *bridge, struct pci_dev *pdev)
+static void tsi148_irq_exit(struct vme_bridge *tsi148_bridge,
+ struct pci_dev *pdev)
{
+ struct tsi148_driver *bridge = tsi148_bridge->driver_priv;
+
/* Turn off interrupts */
iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);
iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);
iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);
/* Detach interrupt handler */
- free_irq(pdev->irq, pdev);
+ free_irq(pdev->irq, tsi148_bridge);
}
/*
* Check to see if an IACk has been received, return true (1) or false (0).
*/
-int tsi148_iack_received(struct tsi148_driver *bridge)
+static int tsi148_iack_received(struct tsi148_driver *bridge)
{
u32 tmp;
/*
* Configure VME interrupt
*/
-void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level,
+static void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level,
int state, int sync)
{
struct pci_dev *pdev;
* Generate a VME bus interrupt at the requested level & vector. Wait for
* interrupt to be acked.
*/
-int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level, int statid)
+static int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level,
+ int statid)
{
u32 tmp;
struct tsi148_driver *bridge;
bridge = tsi148_bridge->driver_priv;
- mutex_lock(&(bridge->vme_int));
+ mutex_lock(&bridge->vme_int);
/* Read VICR register */
tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
wait_event_interruptible(bridge->iack_queue,
tsi148_iack_received(bridge));
- mutex_unlock(&(bridge->vme_int));
+ mutex_unlock(&bridge->vme_int);
return 0;
}
*/
err_pos = NULL;
/* Iterate through errors */
- list_for_each(err_pos, &(tsi148_bridge->vme_errors)) {
+ list_for_each(err_pos, &tsi148_bridge->vme_errors) {
vme_err = list_entry(err_pos, struct vme_bus_error, list);
if ((vme_err->address >= address) &&
(vme_err->address < bound)) {
*/
err_pos = NULL;
/* Iterate through errors */
- list_for_each_safe(err_pos, temp, &(tsi148_bridge->vme_errors)) {
+ list_for_each_safe(err_pos, temp, &tsi148_bridge->vme_errors) {
vme_err = list_entry(err_pos, struct vme_bus_error, list);
if ((vme_err->address >= address) &&
/*
* Initialize a slave window with the requested attributes.
*/
-int tsi148_slave_set(struct vme_slave_resource *image, int enabled,
+static int tsi148_slave_set(struct vme_slave_resource *image, int enabled,
unsigned long long vme_base, unsigned long long size,
dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle)
{
/*
* Get slave window configuration.
*/
-int tsi148_slave_get(struct vme_slave_resource *image, int *enabled,
+static int tsi148_slave_get(struct vme_slave_resource *image, int *enabled,
unsigned long long *vme_base, unsigned long long *size,
dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle)
{
image->kern_base = NULL;
if (image->bus_resource.name != NULL)
kfree(image->bus_resource.name);
- release_resource(&(image->bus_resource));
- memset(&(image->bus_resource), 0, sizeof(struct resource));
+ release_resource(&image->bus_resource);
+ memset(&image->bus_resource, 0, sizeof(struct resource));
}
/* Exit here if size is zero */
image->bus_resource.flags = IORESOURCE_MEM;
retval = pci_bus_alloc_resource(pdev->bus,
- &(image->bus_resource), size, size, PCIBIOS_MIN_MEM,
+ &image->bus_resource, size, size, PCIBIOS_MIN_MEM,
0, NULL, NULL);
if (retval) {
dev_err(tsi148_bridge->parent, "Failed to allocate mem "
iounmap(image->kern_base);
image->kern_base = NULL;
err_remap:
- release_resource(&(image->bus_resource));
+ release_resource(&image->bus_resource);
err_resource:
kfree(image->bus_resource.name);
- memset(&(image->bus_resource), 0, sizeof(struct resource));
+ memset(&image->bus_resource, 0, sizeof(struct resource));
err_name:
return retval;
}
{
iounmap(image->kern_base);
image->kern_base = NULL;
- release_resource(&(image->bus_resource));
+ release_resource(&image->bus_resource);
kfree(image->bus_resource.name);
- memset(&(image->bus_resource), 0, sizeof(struct resource));
+ memset(&image->bus_resource, 0, sizeof(struct resource));
}
/*
* Set the attributes of an outbound window.
*/
-int tsi148_master_set(struct vme_master_resource *image, int enabled,
+static int tsi148_master_set(struct vme_master_resource *image, int enabled,
unsigned long long vme_base, unsigned long long size,
vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
{
goto err_window;
}
- spin_lock(&(image->lock));
+ spin_lock(&image->lock);
/* Let's allocate the resource here rather than further up the stack as
* it avoids pushing loads of bus dependant stuff up the stack. If size
*/
retval = tsi148_alloc_resource(image, size);
if (retval) {
- spin_unlock(&(image->lock));
+ spin_unlock(&image->lock);
dev_err(tsi148_bridge->parent, "Unable to allocate memory for "
"resource\n");
goto err_res;
reg_split(vme_offset, &vme_offset_high, &vme_offset_low);
if (pci_base_low & 0xFFFF) {
- spin_unlock(&(image->lock));
+ spin_unlock(&image->lock);
dev_err(tsi148_bridge->parent, "Invalid PCI base alignment\n");
retval = -EINVAL;
goto err_gran;
}
if (pci_bound_low & 0xFFFF) {
- spin_unlock(&(image->lock));
+ spin_unlock(&image->lock);
dev_err(tsi148_bridge->parent, "Invalid PCI bound alignment\n");
retval = -EINVAL;
goto err_gran;
}
if (vme_offset_low & 0xFFFF) {
- spin_unlock(&(image->lock));
+ spin_unlock(&image->lock);
dev_err(tsi148_bridge->parent, "Invalid VME Offset "
"alignment\n");
retval = -EINVAL;
temp_ctl |= TSI148_LCSR_OTAT_DBW_32;
break;
default:
- spin_unlock(&(image->lock));
+ spin_unlock(&image->lock);
dev_err(tsi148_bridge->parent, "Invalid data width\n");
retval = -EINVAL;
goto err_dwidth;
temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;
break;
default:
- spin_unlock(&(image->lock));
+ spin_unlock(&image->lock);
dev_err(tsi148_bridge->parent, "Invalid address space\n");
retval = -EINVAL;
goto err_aspace;
iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
TSI148_LCSR_OFFSET_OTAT);
- spin_unlock(&(image->lock));
+ spin_unlock(&image->lock);
return 0;
err_aspace:
*
* XXX Not parsing prefetch information.
*/
-int __tsi148_master_get(struct vme_master_resource *image, int *enabled,
+static int __tsi148_master_get(struct vme_master_resource *image, int *enabled,
unsigned long long *vme_base, unsigned long long *size,
vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
{
}
-int tsi148_master_get(struct vme_master_resource *image, int *enabled,
+static int tsi148_master_get(struct vme_master_resource *image, int *enabled,
unsigned long long *vme_base, unsigned long long *size,
vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
{
int retval;
- spin_lock(&(image->lock));
+ spin_lock(&image->lock);
retval = __tsi148_master_get(image, enabled, vme_base, size, aspace,
cycle, dwidth);
- spin_unlock(&(image->lock));
+ spin_unlock(&image->lock);
return retval;
}
-ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf,
+static ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf,
size_t count, loff_t offset)
{
int retval, enabled;
tsi148_bridge = image->parent;
- spin_lock(&(image->lock));
+ spin_lock(&image->lock);
memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count);
retval = count;
}
skip_chk:
- spin_unlock(&(image->lock));
+ spin_unlock(&image->lock);
return retval;
}
-ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
+static ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
size_t count, loff_t offset)
{
int retval = 0, enabled;
bridge = tsi148_bridge->driver_priv;
- spin_lock(&(image->lock));
+ spin_lock(&image->lock);
memcpy_toio(image->kern_base + offset, buf, (unsigned int)count);
retval = count;
}
skip_chk:
- spin_unlock(&(image->lock));
+ spin_unlock(&image->lock);
return retval;
}
*
* Requires a previously configured master window, returns final value.
*/
-unsigned int tsi148_master_rmw(struct vme_master_resource *image,
+static unsigned int tsi148_master_rmw(struct vme_master_resource *image,
unsigned int mask, unsigned int compare, unsigned int swap,
loff_t offset)
{
i = image->number;
/* Locking as we can only do one of these at a time */
- mutex_lock(&(bridge->vme_rmw));
+ mutex_lock(&bridge->vme_rmw);
/* Lock image */
- spin_lock(&(image->lock));
+ spin_lock(&image->lock);
pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
TSI148_LCSR_OFFSET_OTSAU);
tmp &= ~TSI148_LCSR_VMCTRL_RMWEN;
iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
- spin_unlock(&(image->lock));
+ spin_unlock(&image->lock);
- mutex_unlock(&(bridge->vme_rmw));
+ mutex_unlock(&bridge->vme_rmw);
return result;
}
/*
* Add a link list descriptor to the list
*/
-int tsi148_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src,
- struct vme_dma_attr *dest, size_t count)
+static int tsi148_dma_list_add(struct vme_dma_list *list,
+ struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count)
{
struct tsi148_dma_entry *entry, *prev;
u32 address_high, address_low;
}
/* Test descriptor alignment */
- if ((unsigned long)&(entry->descriptor) & 0x7) {
+ if ((unsigned long)&entry->descriptor & 0x7) {
dev_err(tsi148_bridge->parent, "Descriptor not aligned to 8 "
"byte boundary as required: %p\n",
- &(entry->descriptor));
+ &entry->descriptor);
retval = -EINVAL;
goto err_align;
}
/* Given we are going to fill out the structure, we probably don't
* need to zero it, but better safe than sorry for now.
*/
- memset(&(entry->descriptor), 0, sizeof(struct tsi148_dma_descriptor));
+ memset(&entry->descriptor, 0, sizeof(struct tsi148_dma_descriptor));
/* Fill out source part */
switch (src->type) {
entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_VME;
retval = tsi148_dma_set_vme_src_attributes(
- tsi148_bridge->parent, &(entry->descriptor.dsat),
+ tsi148_bridge->parent, &entry->descriptor.dsat,
vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
if (retval < 0)
goto err_source;
entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_VME;
retval = tsi148_dma_set_vme_dest_attributes(
- tsi148_bridge->parent, &(entry->descriptor.ddat),
+ tsi148_bridge->parent, &entry->descriptor.ddat,
vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
if (retval < 0)
goto err_dest;
entry->descriptor.dcnt = (u32)count;
/* Add to list */
- list_add_tail(&(entry->list), &(list->entries));
+ list_add_tail(&entry->list, &list->entries);
/* Fill out previous descriptors "Next Address" */
- if (entry->list.prev != &(list->entries)) {
+ if (entry->list.prev != &list->entries) {
prev = list_entry(entry->list.prev, struct tsi148_dma_entry,
list);
/* We need the bus address for the pointer */
- desc_ptr = virt_to_bus(&(entry->descriptor));
- reg_split(desc_ptr, &(prev->descriptor.dnlau),
- &(prev->descriptor.dnlal));
+ desc_ptr = virt_to_bus(&entry->descriptor);
+ reg_split(desc_ptr, &prev->descriptor.dnlau,
+ &prev->descriptor.dnlal);
}
return 0;
*
* XXX Need to provide control register configuration.
*/
-int tsi148_dma_list_exec(struct vme_dma_list *list)
+static int tsi148_dma_list_exec(struct vme_dma_list *list)
{
struct vme_dma_resource *ctrlr;
int channel, retval = 0;
bridge = tsi148_bridge->driver_priv;
- mutex_lock(&(ctrlr->mtx));
+ mutex_lock(&ctrlr->mtx);
channel = ctrlr->number;
- if (!list_empty(&(ctrlr->running))) {
+ if (!list_empty(&ctrlr->running)) {
/*
* XXX We have an active DMA transfer and currently haven't
* sorted out the mechanism for "pending" DMA transfers.
* Return busy.
*/
/* Need to add to pending here */
- mutex_unlock(&(ctrlr->mtx));
+ mutex_unlock(&ctrlr->mtx);
return -EBUSY;
} else {
- list_add(&(list->list), &(ctrlr->running));
+ list_add(&list->list, &ctrlr->running);
}
/* Get first bus address and write into registers */
- entry = list_first_entry(&(list->entries), struct tsi148_dma_entry,
+ entry = list_first_entry(&list->entries, struct tsi148_dma_entry,
list);
- bus_addr = virt_to_bus(&(entry->descriptor));
+ bus_addr = virt_to_bus(&entry->descriptor);
- mutex_unlock(&(ctrlr->mtx));
+ mutex_unlock(&ctrlr->mtx);
reg_split(bus_addr, &bus_addr_high, &bus_addr_low);
}
/* Remove list from running list */
- mutex_lock(&(ctrlr->mtx));
- list_del(&(list->list));
- mutex_unlock(&(ctrlr->mtx));
+ mutex_lock(&ctrlr->mtx);
+ list_del(&list->list);
+ mutex_unlock(&ctrlr->mtx);
return retval;
}
*
* We have a separate function, don't assume that the chain can't be reused.
*/
-int tsi148_dma_list_empty(struct vme_dma_list *list)
+static int tsi148_dma_list_empty(struct vme_dma_list *list)
{
struct list_head *pos, *temp;
struct tsi148_dma_entry *entry;
/* detach and free each entry */
- list_for_each_safe(pos, temp, &(list->entries)) {
+ list_for_each_safe(pos, temp, &list->entries) {
list_del(pos);
entry = list_entry(pos, struct tsi148_dma_entry, list);
kfree(entry);
* This does not enable the LM monitor - that should be done when the first
* callback is attached and disabled when the last callback is removed.
*/
-int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
+static int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
vme_address_t aspace, vme_cycle_t cycle)
{
u32 lm_base_high, lm_base_low, lm_ctl = 0;
bridge = tsi148_bridge->driver_priv;
- mutex_lock(&(lm->mtx));
+ mutex_lock(&lm->mtx);
/* If we already have a callback attached, we can't move it! */
for (i = 0; i < lm->monitors; i++) {
if (bridge->lm_callback[i] != NULL) {
- mutex_unlock(&(lm->mtx));
+ mutex_unlock(&lm->mtx);
dev_err(tsi148_bridge->parent, "Location monitor "
"callback attached, can't reset\n");
return -EBUSY;
lm_ctl |= TSI148_LCSR_LMAT_AS_A64;
break;
default:
- mutex_unlock(&(lm->mtx));
+ mutex_unlock(&lm->mtx);
dev_err(tsi148_bridge->parent, "Invalid address space\n");
return -EINVAL;
break;
iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL);
iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
- mutex_unlock(&(lm->mtx));
+ mutex_unlock(&lm->mtx);
return 0;
}
/* Get configuration of the callback monitor and return whether it is enabled
* or disabled.
*/
-int tsi148_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base,
- vme_address_t *aspace, vme_cycle_t *cycle)
+static int tsi148_lm_get(struct vme_lm_resource *lm,
+ unsigned long long *lm_base, vme_address_t *aspace, vme_cycle_t *cycle)
{
u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0;
struct tsi148_driver *bridge;
bridge = lm->parent->driver_priv;
- mutex_lock(&(lm->mtx));
+ mutex_lock(&lm->mtx);
lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);
lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);
if (lm_ctl & TSI148_LCSR_LMAT_DATA)
*cycle |= VME_DATA;
- mutex_unlock(&(lm->mtx));
+ mutex_unlock(&lm->mtx);
return enabled;
}
*
* Callback will be passed the monitor triggered.
*/
-int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor,
+static int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor,
void (*callback)(int))
{
u32 lm_ctl, tmp;
bridge = tsi148_bridge->driver_priv;
- mutex_lock(&(lm->mtx));
+ mutex_lock(&lm->mtx);
/* Ensure that the location monitor is configured - need PGM or DATA */
lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) {
- mutex_unlock(&(lm->mtx));
+ mutex_unlock(&lm->mtx);
dev_err(tsi148_bridge->parent, "Location monitor not properly "
"configured\n");
return -EINVAL;
/* Check that a callback isn't already attached */
if (bridge->lm_callback[monitor] != NULL) {
- mutex_unlock(&(lm->mtx));
+ mutex_unlock(&lm->mtx);
dev_err(tsi148_bridge->parent, "Existing callback attached\n");
return -EBUSY;
}
iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
}
- mutex_unlock(&(lm->mtx));
+ mutex_unlock(&lm->mtx);
return 0;
}
/*
* Detach a callback function forn a specific location monitor.
*/
-int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor)
+static int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor)
{
u32 lm_en, tmp;
struct tsi148_driver *bridge;
bridge = lm->parent->driver_priv;
- mutex_lock(&(lm->mtx));
+ mutex_lock(&lm->mtx);
/* Disable Location Monitor and ensure previous interrupts are clear */
lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);
iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT);
}
- mutex_unlock(&(lm->mtx));
+ mutex_unlock(&lm->mtx);
return 0;
}
/*
* Determine Geographical Addressing
*/
-int tsi148_slot_get(struct vme_bridge *tsi148_bridge)
+static int tsi148_slot_get(struct vme_bridge *tsi148_bridge)
{
u32 slot = 0;
struct tsi148_driver *bridge;
/* Allocate mem for CR/CSR image */
bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
- &(bridge->crcsr_bus));
+ &bridge->crcsr_bus);
if (bridge->crcsr_kernel == NULL) {
dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
"CR/CSR image\n");
}
/* Initialize wait queues & mutual exclusion flags */
- init_waitqueue_head(&(tsi148_device->dma_queue[0]));
- init_waitqueue_head(&(tsi148_device->dma_queue[1]));
- init_waitqueue_head(&(tsi148_device->iack_queue));
- mutex_init(&(tsi148_device->vme_int));
- mutex_init(&(tsi148_device->vme_rmw));
+ init_waitqueue_head(&tsi148_device->dma_queue[0]);
+ init_waitqueue_head(&tsi148_device->dma_queue[1]);
+ init_waitqueue_head(&tsi148_device->iack_queue);
+ mutex_init(&tsi148_device->vme_int);
+ mutex_init(&tsi148_device->vme_rmw);
- tsi148_bridge->parent = &(pdev->dev);
+ tsi148_bridge->parent = &pdev->dev;
strcpy(tsi148_bridge->name, driver_name);
/* Setup IRQ */
goto err_master;
}
tsi148_device->flush_image->parent = tsi148_bridge;
- spin_lock_init(&(tsi148_device->flush_image->lock));
+ spin_lock_init(&tsi148_device->flush_image->lock);
tsi148_device->flush_image->locked = 1;
tsi148_device->flush_image->number = master_num;
tsi148_device->flush_image->address_attr = VME_A16 | VME_A24 |
VME_2eSST160 | VME_2eSST267 | VME_2eSST320 | VME_SUPER |
VME_USER | VME_PROG | VME_DATA;
tsi148_device->flush_image->width_attr = VME_D16 | VME_D32;
- memset(&(tsi148_device->flush_image->bus_resource), 0,
+ memset(&tsi148_device->flush_image->bus_resource, 0,
sizeof(struct resource));
tsi148_device->flush_image->kern_base = NULL;
}
/* Add master windows to list */
- INIT_LIST_HEAD(&(tsi148_bridge->master_resources));
+ INIT_LIST_HEAD(&tsi148_bridge->master_resources);
for (i = 0; i < master_num; i++) {
master_image = kmalloc(sizeof(struct vme_master_resource),
GFP_KERNEL);
goto err_master;
}
master_image->parent = tsi148_bridge;
- spin_lock_init(&(master_image->lock));
+ spin_lock_init(&master_image->lock);
master_image->locked = 0;
master_image->number = i;
master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
VME_PROG | VME_DATA;
master_image->width_attr = VME_D16 | VME_D32;
- memset(&(master_image->bus_resource), 0,
+ memset(&master_image->bus_resource, 0,
sizeof(struct resource));
master_image->kern_base = NULL;
- list_add_tail(&(master_image->list),
- &(tsi148_bridge->master_resources));
+ list_add_tail(&master_image->list,
+ &tsi148_bridge->master_resources);
}
/* Add slave windows to list */
- INIT_LIST_HEAD(&(tsi148_bridge->slave_resources));
+ INIT_LIST_HEAD(&tsi148_bridge->slave_resources);
for (i = 0; i < TSI148_MAX_SLAVE; i++) {
slave_image = kmalloc(sizeof(struct vme_slave_resource),
GFP_KERNEL);
goto err_slave;
}
slave_image->parent = tsi148_bridge;
- mutex_init(&(slave_image->mtx));
+ mutex_init(&slave_image->mtx);
slave_image->locked = 0;
slave_image->number = i;
slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
VME_PROG | VME_DATA;
- list_add_tail(&(slave_image->list),
- &(tsi148_bridge->slave_resources));
+ list_add_tail(&slave_image->list,
+ &tsi148_bridge->slave_resources);
}
/* Add dma engines to list */
- INIT_LIST_HEAD(&(tsi148_bridge->dma_resources));
+ INIT_LIST_HEAD(&tsi148_bridge->dma_resources);
for (i = 0; i < TSI148_MAX_DMA; i++) {
dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
GFP_KERNEL);
goto err_dma;
}
dma_ctrlr->parent = tsi148_bridge;
- mutex_init(&(dma_ctrlr->mtx));
+ mutex_init(&dma_ctrlr->mtx);
dma_ctrlr->locked = 0;
dma_ctrlr->number = i;
dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
VME_DMA_MEM_TO_VME | VME_DMA_VME_TO_VME |
VME_DMA_MEM_TO_MEM | VME_DMA_PATTERN_TO_VME |
VME_DMA_PATTERN_TO_MEM;
- INIT_LIST_HEAD(&(dma_ctrlr->pending));
- INIT_LIST_HEAD(&(dma_ctrlr->running));
- list_add_tail(&(dma_ctrlr->list),
- &(tsi148_bridge->dma_resources));
+ INIT_LIST_HEAD(&dma_ctrlr->pending);
+ INIT_LIST_HEAD(&dma_ctrlr->running);
+ list_add_tail(&dma_ctrlr->list,
+ &tsi148_bridge->dma_resources);
}
/* Add location monitor to list */
- INIT_LIST_HEAD(&(tsi148_bridge->lm_resources));
+ INIT_LIST_HEAD(&tsi148_bridge->lm_resources);
lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
if (lm == NULL) {
dev_err(&pdev->dev, "Failed to allocate memory for "
goto err_lm;
}
lm->parent = tsi148_bridge;
- mutex_init(&(lm->mtx));
+ mutex_init(&lm->mtx);
lm->locked = 0;
lm->number = 1;
lm->monitors = 4;
- list_add_tail(&(lm->list), &(tsi148_bridge->lm_resources));
+ list_add_tail(&lm->list, &tsi148_bridge->lm_resources);
tsi148_bridge->slave_get = tsi148_slave_get;
tsi148_bridge->slave_set = tsi148_slave_set;
return 0;
- vme_unregister_bridge(tsi148_bridge);
err_reg:
tsi148_crcsr_exit(tsi148_bridge, pdev);
err_crcsr:
err_lm:
/* resources are stored in link list */
- list_for_each(pos, &(tsi148_bridge->lm_resources)) {
+ list_for_each(pos, &tsi148_bridge->lm_resources) {
lm = list_entry(pos, struct vme_lm_resource, list);
list_del(pos);
kfree(lm);
}
err_dma:
/* resources are stored in link list */
- list_for_each(pos, &(tsi148_bridge->dma_resources)) {
+ list_for_each(pos, &tsi148_bridge->dma_resources) {
dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
list_del(pos);
kfree(dma_ctrlr);
}
err_slave:
/* resources are stored in link list */
- list_for_each(pos, &(tsi148_bridge->slave_resources)) {
+ list_for_each(pos, &tsi148_bridge->slave_resources) {
slave_image = list_entry(pos, struct vme_slave_resource, list);
list_del(pos);
kfree(slave_image);
}
err_master:
/* resources are stored in link list */
- list_for_each(pos, &(tsi148_bridge->master_resources)) {
+ list_for_each(pos, &tsi148_bridge->master_resources) {
master_image = list_entry(pos, struct vme_master_resource,
list);
list_del(pos);
kfree(master_image);
}
- tsi148_irq_exit(tsi148_device, pdev);
+ tsi148_irq_exit(tsi148_bridge, pdev);
err_irq:
err_test:
iounmap(tsi148_device->base);
static void tsi148_remove(struct pci_dev *pdev)
{
struct list_head *pos = NULL;
+ struct list_head *tmplist;
struct vme_master_resource *master_image;
struct vme_slave_resource *slave_image;
struct vme_dma_resource *dma_ctrlr;
iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1);
iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2);
- tsi148_irq_exit(bridge, pdev);
+ tsi148_irq_exit(tsi148_bridge, pdev);
vme_unregister_bridge(tsi148_bridge);
tsi148_crcsr_exit(tsi148_bridge, pdev);
/* resources are stored in link list */
- list_for_each(pos, &(tsi148_bridge->dma_resources)) {
+ list_for_each_safe(pos, tmplist, &tsi148_bridge->dma_resources) {
dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
list_del(pos);
kfree(dma_ctrlr);
}
/* resources are stored in link list */
- list_for_each(pos, &(tsi148_bridge->slave_resources)) {
+ list_for_each_safe(pos, tmplist, &tsi148_bridge->slave_resources) {
slave_image = list_entry(pos, struct vme_slave_resource, list);
list_del(pos);
kfree(slave_image);
}
/* resources are stored in link list */
- list_for_each(pos, &(tsi148_bridge->master_resources)) {
+ list_for_each_safe(pos, tmplist, &tsi148_bridge->master_resources) {
master_image = list_entry(pos, struct vme_master_resource,
list);
list_del(pos);
kfree(master_image);
}
- tsi148_irq_exit(bridge, pdev);
-
iounmap(bridge->base);
pci_release_regions(pdev);
projects / mv-sheeva.git / blobdiff