if(!(ivideo->vbflags2 & VB2_VIDEOBRIDGE))
return false;
- inSISIDXREG(SISPART1,0x00,P1_00);
+ P1_00 = SiS_GetReg(SISPART1, 0x00);
if( ((ivideo->sisvga_engine == SIS_300_VGA) && (P1_00 & 0xa0) == 0x20) ||
((ivideo->sisvga_engine == SIS_315_VGA) && (P1_00 & 0x50) == 0x10) ) {
return true;
{
u8 temp;
- inSISIDXREG(SISCR,0x17,temp);
+ temp = SiS_GetReg(SISCR, 0x17);
if(!(temp & 0x80))
return false;
- inSISIDXREG(SISSR,0x1f,temp);
+ temp = SiS_GetReg(SISSR, 0x1f);
if(temp & 0xc0)
return false;
if(!sisfballowretracecrt1(ivideo))
return false;
- if(inSISREG(SISINPSTAT) & 0x08)
+ if (SiS_GetRegByte(SISINPSTAT) & 0x08)
return true;
else
return false;
return;
watchdog = 65536;
- while((!(inSISREG(SISINPSTAT) & 0x08)) && --watchdog);
+ while ((!(SiS_GetRegByte(SISINPSTAT) & 0x08)) && --watchdog);
watchdog = 65536;
- while((inSISREG(SISINPSTAT) & 0x08) && --watchdog);
+ while ((SiS_GetRegByte(SISINPSTAT) & 0x08) && --watchdog);
}
static bool
default: return false;
}
- inSISIDXREG(SISPART1, reg, temp);
+ temp = SiS_GetReg(SISPART1, reg);
if(temp & 0x02)
return true;
else
default:
case SIS_315_VGA: idx = 0x30; break;
}
- inSISIDXREG(SISPART1,(idx+0),reg1); /* 30 */
- inSISIDXREG(SISPART1,(idx+1),reg2); /* 31 */
- inSISIDXREG(SISPART1,(idx+2),reg3); /* 32 */
- inSISIDXREG(SISPART1,(idx+3),reg4); /* 33 */
+ reg1 = SiS_GetReg(SISPART1, (idx+0)); /* 30 */
+ reg2 = SiS_GetReg(SISPART1, (idx+1)); /* 31 */
+ reg3 = SiS_GetReg(SISPART1, (idx+2)); /* 32 */
+ reg4 = SiS_GetReg(SISPART1, (idx+3)); /* 33 */
if(reg1 & 0x01) ret |= FB_VBLANK_VBLANKING;
if(reg1 & 0x02) ret |= FB_VBLANK_VSYNCING;
if(reg4 & 0x80) ret |= FB_VBLANK_HBLANKING;
FB_VBLANK_HAVE_VBLANK |
FB_VBLANK_HAVE_VCOUNT |
FB_VBLANK_HAVE_HCOUNT);
- reg1 = inSISREG(SISINPSTAT);
+ reg1 = SiS_GetRegByte(SISINPSTAT);
if(reg1 & 0x08) ret |= FB_VBLANK_VSYNCING;
if(reg1 & 0x01) ret |= FB_VBLANK_VBLANKING;
- inSISIDXREG(SISCR,0x20,reg1);
- inSISIDXREG(SISCR,0x1b,reg1);
- inSISIDXREG(SISCR,0x1c,reg2);
- inSISIDXREG(SISCR,0x1d,reg3);
+ reg1 = SiS_GetReg(SISCR, 0x20);
+ reg1 = SiS_GetReg(SISCR, 0x1b);
+ reg2 = SiS_GetReg(SISCR, 0x1c);
+ reg3 = SiS_GetReg(SISCR, 0x1d);
(*vcount) = reg2 | ((reg3 & 0x07) << 8);
(*hcount) = (reg1 | ((reg3 & 0x10) << 4)) << 3;
}
(ivideo->sisfb_thismonitor.feature & 0xe0))) {
if(ivideo->sisvga_engine == SIS_315_VGA) {
- setSISIDXREG(SISCR, ivideo->SiS_Pr.SiS_MyCR63, 0xbf, cr63);
+ SiS_SetRegANDOR(SISCR, ivideo->SiS_Pr.SiS_MyCR63, 0xbf, cr63);
}
if(!(sisfb_bridgeisslave(ivideo))) {
- setSISIDXREG(SISSR, 0x01, ~0x20, sr01);
- setSISIDXREG(SISSR, 0x1f, 0x3f, sr1f);
+ SiS_SetRegANDOR(SISSR, 0x01, ~0x20, sr01);
+ SiS_SetRegANDOR(SISSR, 0x1f, 0x3f, sr1f);
}
}
(ivideo->vbflags2 & (VB2_301|VB2_30xBDH|VB2_LVDS))) ||
((ivideo->sisvga_engine == SIS_315_VGA) &&
((ivideo->vbflags2 & (VB2_LVDS | VB2_CHRONTEL)) == VB2_LVDS))) {
- setSISIDXREG(SISSR, 0x11, ~0x0c, sr11);
+ SiS_SetRegANDOR(SISSR, 0x11, ~0x0c, sr11);
}
if(ivideo->sisvga_engine == SIS_300_VGA) {
if((ivideo->vbflags2 & VB2_30xB) &&
(!(ivideo->vbflags2 & VB2_30xBDH))) {
- setSISIDXREG(SISPART1, 0x13, 0x3f, p1_13);
+ SiS_SetRegANDOR(SISPART1, 0x13, 0x3f, p1_13);
}
} else if(ivideo->sisvga_engine == SIS_315_VGA) {
if((ivideo->vbflags2 & VB2_30xB) &&
(!(ivideo->vbflags2 & VB2_30xBDH))) {
- setSISIDXREG(SISPART2, 0x00, 0x1f, p2_0);
+ SiS_SetRegANDOR(SISPART2, 0x00, 0x1f, p2_0);
}
}
} else if(ivideo->currentvbflags & CRT2_VGA) {
if(ivideo->vbflags2 & VB2_30xB) {
- setSISIDXREG(SISPART2, 0x00, 0x1f, p2_0);
+ SiS_SetRegANDOR(SISPART2, 0x00, 0x1f, p2_0);
}
}
/* We need to set pitch for CRT1 if bridge is in slave mode, too */
if((ivideo->currentvbflags & VB_DISPTYPE_DISP1) || (isslavemode)) {
- outSISIDXREG(SISCR,0x13,(HDisplay1 & 0xFF));
- setSISIDXREG(SISSR,0x0E,0xF0,(HDisplay1 >> 8));
+ SiS_SetReg(SISCR, 0x13, (HDisplay1 & 0xFF));
+ SiS_SetRegANDOR(SISSR, 0x0E, 0xF0, (HDisplay1 >> 8));
}
/* We must not set the pitch for CRT2 if bridge is in slave mode */
if((ivideo->currentvbflags & VB_DISPTYPE_DISP2) && (!isslavemode)) {
- orSISIDXREG(SISPART1,ivideo->CRT2_write_enable,0x01);
- outSISIDXREG(SISPART1,0x07,(HDisplay2 & 0xFF));
- setSISIDXREG(SISPART1,0x09,0xF0,(HDisplay2 >> 8));
+ SiS_SetRegOR(SISPART1, ivideo->CRT2_write_enable, 0x01);
+ SiS_SetReg(SISPART1, 0x07, (HDisplay2 & 0xFF));
+ SiS_SetRegANDOR(SISPART1, 0x09, 0xF0, (HDisplay2 >> 8));
}
}
/* >=2.6.12's fbcon clears the screen anyway */
modeno |= 0x80;
- outSISIDXREG(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
+ SiS_SetReg(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
sisfb_pre_setmode(ivideo);
return -EINVAL;
}
- outSISIDXREG(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
+ SiS_SetReg(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
sisfb_post_setmode(ivideo);
static void
sisfb_set_base_CRT1(struct sis_video_info *ivideo, unsigned int base)
{
- outSISIDXREG(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
+ SiS_SetReg(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
- outSISIDXREG(SISCR, 0x0D, base & 0xFF);
- outSISIDXREG(SISCR, 0x0C, (base >> 8) & 0xFF);
- outSISIDXREG(SISSR, 0x0D, (base >> 16) & 0xFF);
+ SiS_SetReg(SISCR, 0x0D, base & 0xFF);
+ SiS_SetReg(SISCR, 0x0C, (base >> 8) & 0xFF);
+ SiS_SetReg(SISSR, 0x0D, (base >> 16) & 0xFF);
if(ivideo->sisvga_engine == SIS_315_VGA) {
- setSISIDXREG(SISSR, 0x37, 0xFE, (base >> 24) & 0x01);
+ SiS_SetRegANDOR(SISSR, 0x37, 0xFE, (base >> 24) & 0x01);
}
}
sisfb_set_base_CRT2(struct sis_video_info *ivideo, unsigned int base)
{
if(ivideo->currentvbflags & VB_DISPTYPE_DISP2) {
- orSISIDXREG(SISPART1, ivideo->CRT2_write_enable, 0x01);
- outSISIDXREG(SISPART1, 0x06, (base & 0xFF));
- outSISIDXREG(SISPART1, 0x05, ((base >> 8) & 0xFF));
- outSISIDXREG(SISPART1, 0x04, ((base >> 16) & 0xFF));
+ SiS_SetRegOR(SISPART1, ivideo->CRT2_write_enable, 0x01);
+ SiS_SetReg(SISPART1, 0x06, (base & 0xFF));
+ SiS_SetReg(SISPART1, 0x05, ((base >> 8) & 0xFF));
+ SiS_SetReg(SISPART1, 0x04, ((base >> 16) & 0xFF));
if(ivideo->sisvga_engine == SIS_315_VGA) {
- setSISIDXREG(SISPART1, 0x02, 0x7F, ((base >> 24) & 0x01) << 7);
+ SiS_SetRegANDOR(SISPART1, 0x02, 0x7F, ((base >> 24) & 0x01) << 7);
}
}
}
switch(info->var.bits_per_pixel) {
case 8:
- outSISREG(SISDACA, regno);
- outSISREG(SISDACD, (red >> 10));
- outSISREG(SISDACD, (green >> 10));
- outSISREG(SISDACD, (blue >> 10));
+ SiS_SetRegByte(SISDACA, regno);
+ SiS_SetRegByte(SISDACD, (red >> 10));
+ SiS_SetRegByte(SISDACD, (green >> 10));
+ SiS_SetRegByte(SISDACD, (blue >> 10));
if(ivideo->currentvbflags & VB_DISPTYPE_DISP2) {
- outSISREG(SISDAC2A, regno);
- outSISREG(SISDAC2D, (red >> 8));
- outSISREG(SISDAC2D, (green >> 8));
- outSISREG(SISDAC2D, (blue >> 8));
+ SiS_SetRegByte(SISDAC2A, regno);
+ SiS_SetRegByte(SISDAC2D, (red >> 8));
+ SiS_SetRegByte(SISDAC2D, (green >> 8));
+ SiS_SetRegByte(SISDAC2D, (blue >> 8));
}
break;
case 16:
switch(ivideo->chip) {
#ifdef CONFIG_FB_SIS_300
case SIS_300:
- inSISIDXREG(SISSR, 0x14, reg);
+ reg = SiS_GetReg(SISSR, 0x14);
ivideo->video_size = ((reg & 0x3F) + 1) << 20;
break;
case SIS_540:
case SIS_315H:
case SIS_315PRO:
case SIS_315:
- inSISIDXREG(SISSR, 0x14, reg);
+ reg = SiS_GetReg(SISSR, 0x14);
ivideo->video_size = (1 << ((reg & 0xf0) >> 4)) << 20;
switch((reg >> 2) & 0x03) {
case 0x01:
}
break;
case SIS_330:
- inSISIDXREG(SISSR, 0x14, reg);
+ reg = SiS_GetReg(SISSR, 0x14);
ivideo->video_size = (1 << ((reg & 0xf0) >> 4)) << 20;
if(reg & 0x0c) ivideo->video_size <<= 1;
break;
case SIS_550:
case SIS_650:
case SIS_740:
- inSISIDXREG(SISSR, 0x14, reg);
+ reg = SiS_GetReg(SISSR, 0x14);
ivideo->video_size = (((reg & 0x3f) + 1) << 2) << 20;
break;
case SIS_661:
case SIS_741:
- inSISIDXREG(SISCR, 0x79, reg);
+ reg = SiS_GetReg(SISCR, 0x79);
ivideo->video_size = (1 << ((reg & 0xf0) >> 4)) << 20;
break;
case SIS_660:
case SIS_760:
case SIS_761:
- inSISIDXREG(SISCR, 0x79, reg);
+ reg = SiS_GetReg(SISCR, 0x79);
reg = (reg & 0xf0) >> 4;
if(reg) {
ivideo->video_size = (1 << reg) << 20;
ivideo->UMAsize = ivideo->video_size;
}
- inSISIDXREG(SISCR, 0x78, reg);
+ reg = SiS_GetReg(SISCR, 0x78);
reg &= 0x30;
if(reg) {
if(reg == 0x10) {
case SIS_340:
case XGI_20:
case XGI_40:
- inSISIDXREG(SISSR, 0x14, reg);
+ reg = SiS_GetReg(SISSR, 0x14);
ivideo->video_size = (1 << ((reg & 0xf0) >> 4)) << 20;
if(ivideo->chip != XGI_20) {
reg = (reg & 0x0c) >> 2;
#ifdef CONFIG_FB_SIS_300
if(ivideo->sisvga_engine == SIS_300_VGA) {
- inSISIDXREG(SISSR, 0x17, temp);
+ temp = SiS_GetReg(SISSR, 0x17);
if((temp & 0x0F) && (ivideo->chip != SIS_300)) {
/* PAL/NTSC is stored on SR16 on such machines */
if(!(ivideo->vbflags & (TV_PAL | TV_NTSC | TV_PALM | TV_PALN))) {
- inSISIDXREG(SISSR, 0x16, temp);
+ temp = SiS_GetReg(SISSR, 0x16);
if(temp & 0x20)
ivideo->vbflags |= TV_PAL;
else
}
#endif
- inSISIDXREG(SISCR, 0x32, cr32);
+ cr32 = SiS_GetReg(SISCR, 0x32);
if(cr32 & SIS_CRT1) {
ivideo->sisfb_crt1off = 0;
}
if(!(ivideo->vbflags & (TV_PAL | TV_NTSC | TV_PALM | TV_PALN | TV_NTSCJ))) {
if(ivideo->sisvga_engine == SIS_300_VGA) {
- inSISIDXREG(SISSR, 0x38, temp);
+ temp = SiS_GetReg(SISSR, 0x38);
if(temp & 0x01) ivideo->vbflags |= TV_PAL;
else ivideo->vbflags |= TV_NTSC;
} else if((ivideo->chip <= SIS_315PRO) || (ivideo->chip >= SIS_330)) {
- inSISIDXREG(SISSR, 0x38, temp);
+ temp = SiS_GetReg(SISSR, 0x38);
if(temp & 0x01) ivideo->vbflags |= TV_PAL;
else ivideo->vbflags |= TV_NTSC;
} else {
- inSISIDXREG(SISCR, 0x79, temp);
+ temp = SiS_GetReg(SISCR, 0x79);
if(temp & 0x20) ivideo->vbflags |= TV_PAL;
else ivideo->vbflags |= TV_NTSC;
}
u16 temp = 0xffff;
int i;
- inSISIDXREG(SISSR,0x1F,sr1F);
- orSISIDXREG(SISSR,0x1F,0x04);
- andSISIDXREG(SISSR,0x1F,0x3F);
+ sr1F = SiS_GetReg(SISSR, 0x1F);
+ SiS_SetRegOR(SISSR, 0x1F, 0x04);
+ SiS_SetRegAND(SISSR, 0x1F, 0x3F);
if(sr1F & 0xc0) mustwait = true;
#ifdef CONFIG_FB_SIS_315
if(ivideo->sisvga_engine == SIS_315_VGA) {
- inSISIDXREG(SISCR,ivideo->SiS_Pr.SiS_MyCR63,cr63);
+ cr63 = SiS_GetReg(SISCR, ivideo->SiS_Pr.SiS_MyCR63);
cr63 &= 0x40;
- andSISIDXREG(SISCR,ivideo->SiS_Pr.SiS_MyCR63,0xBF);
+ SiS_SetRegAND(SISCR, ivideo->SiS_Pr.SiS_MyCR63, 0xBF);
}
#endif
- inSISIDXREG(SISCR,0x17,cr17);
+ cr17 = SiS_GetReg(SISCR, 0x17);
cr17 &= 0x80;
if(!cr17) {
- orSISIDXREG(SISCR,0x17,0x80);
+ SiS_SetRegOR(SISCR, 0x17, 0x80);
mustwait = true;
- outSISIDXREG(SISSR, 0x00, 0x01);
- outSISIDXREG(SISSR, 0x00, 0x03);
+ SiS_SetReg(SISSR, 0x00, 0x01);
+ SiS_SetReg(SISSR, 0x00, 0x03);
}
if(mustwait) {
#ifdef CONFIG_FB_SIS_315
if(ivideo->chip >= SIS_330) {
- andSISIDXREG(SISCR,0x32,~0x20);
+ SiS_SetRegAND(SISCR, 0x32, ~0x20);
if(ivideo->chip >= SIS_340) {
- outSISIDXREG(SISCR, 0x57, 0x4a);
+ SiS_SetReg(SISCR, 0x57, 0x4a);
} else {
- outSISIDXREG(SISCR, 0x57, 0x5f);
+ SiS_SetReg(SISCR, 0x57, 0x5f);
}
- orSISIDXREG(SISCR, 0x53, 0x02);
- while((inSISREG(SISINPSTAT)) & 0x01) break;
- while(!((inSISREG(SISINPSTAT)) & 0x01)) break;
- if((inSISREG(SISMISCW)) & 0x10) temp = 1;
- andSISIDXREG(SISCR, 0x53, 0xfd);
- andSISIDXREG(SISCR, 0x57, 0x00);
+ SiS_SetRegOR(SISCR, 0x53, 0x02);
+ while ((SiS_GetRegByte(SISINPSTAT)) & 0x01) break;
+ while (!((SiS_GetRegByte(SISINPSTAT)) & 0x01)) break;
+ if ((SiS_GetRegByte(SISMISCW)) & 0x10) temp = 1;
+ SiS_SetRegAND(SISCR, 0x53, 0xfd);
+ SiS_SetRegAND(SISCR, 0x57, 0x00);
}
#endif
}
if((temp) && (temp != 0xffff)) {
- orSISIDXREG(SISCR,0x32,0x20);
+ SiS_SetRegOR(SISCR, 0x32, 0x20);
}
#ifdef CONFIG_FB_SIS_315
if(ivideo->sisvga_engine == SIS_315_VGA) {
- setSISIDXREG(SISCR,ivideo->SiS_Pr.SiS_MyCR63,0xBF,cr63);
+ SiS_SetRegANDOR(SISCR, ivideo->SiS_Pr.SiS_MyCR63, 0xBF, cr63);
}
#endif
- setSISIDXREG(SISCR,0x17,0x7F,cr17);
+ SiS_SetRegANDOR(SISCR, 0x17, 0x7F, cr17);
- outSISIDXREG(SISSR,0x1F,sr1F);
+ SiS_SetReg(SISSR, 0x1F, sr1F);
}
/* Determine and detect attached devices on SiS30x */
return;
/* If LCD already set up by BIOS, skip it */
- inSISIDXREG(SISCR, 0x32, reg);
+ reg = SiS_GetReg(SISCR, 0x32);
if(reg & 0x08)
return;
else
cr37 |= 0xc0;
- outSISIDXREG(SISCR, 0x36, paneltype);
+ SiS_SetReg(SISCR, 0x36, paneltype);
cr37 &= 0xf1;
- setSISIDXREG(SISCR, 0x37, 0x0c, cr37);
- orSISIDXREG(SISCR, 0x32, 0x08);
+ SiS_SetRegANDOR(SISCR, 0x37, 0x0c, cr37);
+ SiS_SetRegOR(SISCR, 0x32, 0x08);
ivideo->SiS_Pr.PanelSelfDetected = true;
}
result = 0;
for(i = 0; i < 3; i++) {
mytest = test;
- outSISIDXREG(SISPART4,0x11,(type & 0x00ff));
+ SiS_SetReg(SISPART4, 0x11, (type & 0x00ff));
temp = (type >> 8) | (mytest & 0x00ff);
- setSISIDXREG(SISPART4,0x10,0xe0,temp);
+ SiS_SetRegANDOR(SISPART4, 0x10, 0xe0, temp);
SiS_DDC2Delay(&ivideo->SiS_Pr, 0x1500);
mytest >>= 8;
mytest &= 0x7f;
- inSISIDXREG(SISPART4,0x03,temp);
+ temp = SiS_GetReg(SISPART4, 0x03);
temp ^= 0x0e;
temp &= mytest;
if(temp == mytest) result++;
#if 1
- outSISIDXREG(SISPART4,0x11,0x00);
- andSISIDXREG(SISPART4,0x10,0xe0);
+ SiS_SetReg(SISPART4, 0x11, 0x00);
+ SiS_SetRegAND(SISPART4, 0x10, 0xe0);
SiS_DDC2Delay(&ivideo->SiS_Pr, 0x1000);
#endif
}
if(ivideo->vbflags2 & VB2_301) {
svhs = 0x00b9; cvbs = 0x00b3; vga2 = 0x00d1;
- inSISIDXREG(SISPART4,0x01,myflag);
+ myflag = SiS_GetReg(SISPART4, 0x01);
if(myflag & 0x04) {
svhs = 0x00dd; cvbs = 0x00ee; vga2 = 0x00fd;
}
}
if(ivideo->chip == SIS_300) {
- inSISIDXREG(SISSR,0x3b,myflag);
+ myflag = SiS_GetReg(SISSR, 0x3b);
if(!(myflag & 0x01)) vga2 = vga2_c = 0;
}
vga2 = vga2_c = 0;
}
- inSISIDXREG(SISSR,0x1e,backupSR_1e);
- orSISIDXREG(SISSR,0x1e,0x20);
+ backupSR_1e = SiS_GetReg(SISSR, 0x1e);
+ SiS_SetRegOR(SISSR, 0x1e, 0x20);
- inSISIDXREG(SISPART4,0x0d,backupP4_0d);
+ backupP4_0d = SiS_GetReg(SISPART4, 0x0d);
if(ivideo->vbflags2 & VB2_30xC) {
- setSISIDXREG(SISPART4,0x0d,~0x07,0x01);
+ SiS_SetRegANDOR(SISPART4, 0x0d, ~0x07, 0x01);
} else {
- orSISIDXREG(SISPART4,0x0d,0x04);
+ SiS_SetRegOR(SISPART4, 0x0d, 0x04);
}
SiS_DDC2Delay(&ivideo->SiS_Pr, 0x2000);
- inSISIDXREG(SISPART2,0x00,backupP2_00);
- outSISIDXREG(SISPART2,0x00,((backupP2_00 | 0x1c) & 0xfc));
+ backupP2_00 = SiS_GetReg(SISPART2, 0x00);
+ SiS_SetReg(SISPART2, 0x00, ((backupP2_00 | 0x1c) & 0xfc));
- inSISIDXREG(SISPART2,0x4d,backupP2_4d);
+ backupP2_4d = SiS_GetReg(SISPART2, 0x4d);
if(ivideo->vbflags2 & VB2_SISYPBPRBRIDGE) {
- outSISIDXREG(SISPART2,0x4d,(backupP2_4d & ~0x10));
+ SiS_SetReg(SISPART2, 0x4d, (backupP2_4d & ~0x10));
}
if(!(ivideo->vbflags2 & VB2_30xCLV)) {
SISDoSense(ivideo, 0, 0);
}
- andSISIDXREG(SISCR, 0x32, ~0x14);
+ SiS_SetRegAND(SISCR, 0x32, ~0x14);
if(vga2_c || vga2) {
if(SISDoSense(ivideo, vga2, vga2_c)) {
if(biosflag & 0x01) {
printk(KERN_INFO "%s %s SCART output\n", stdstr, tvstr);
- orSISIDXREG(SISCR, 0x32, 0x04);
+ SiS_SetRegOR(SISCR, 0x32, 0x04);
} else {
printk(KERN_INFO "%s secondary VGA connection\n", stdstr);
- orSISIDXREG(SISCR, 0x32, 0x10);
+ SiS_SetRegOR(SISCR, 0x32, 0x10);
}
}
}
- andSISIDXREG(SISCR, 0x32, 0x3f);
+ SiS_SetRegAND(SISCR, 0x32, 0x3f);
if(ivideo->vbflags2 & VB2_30xCLV) {
- orSISIDXREG(SISPART4,0x0d,0x04);
+ SiS_SetRegOR(SISPART4, 0x0d, 0x04);
}
if((ivideo->sisvga_engine == SIS_315_VGA) && (ivideo->vbflags2 & VB2_SISYPBPRBRIDGE)) {
- outSISIDXREG(SISPART2,0x4d,(backupP2_4d | 0x10));
+ SiS_SetReg(SISPART2, 0x4d, (backupP2_4d | 0x10));
SiS_DDC2Delay(&ivideo->SiS_Pr, 0x2000);
if((result = SISDoSense(ivideo, svhs, 0x0604))) {
if((result = SISDoSense(ivideo, cvbs, 0x0804))) {
printk(KERN_INFO "%s %s YPbPr component output\n", stdstr, tvstr);
- orSISIDXREG(SISCR,0x32,0x80);
+ SiS_SetRegOR(SISCR, 0x32, 0x80);
}
}
- outSISIDXREG(SISPART2,0x4d,backupP2_4d);
+ SiS_SetReg(SISPART2, 0x4d, backupP2_4d);
}
- andSISIDXREG(SISCR, 0x32, ~0x03);
+ SiS_SetRegAND(SISCR, 0x32, ~0x03);
if(!(ivideo->vbflags & TV_YPBPR)) {
if((result = SISDoSense(ivideo, svhs, svhs_c))) {
printk(KERN_INFO "%s %s SVIDEO output\n", stdstr, tvstr);
- orSISIDXREG(SISCR, 0x32, 0x02);
+ SiS_SetRegOR(SISCR, 0x32, 0x02);
}
if((biosflag & 0x02) || (!result)) {
if(SISDoSense(ivideo, cvbs, cvbs_c)) {
printk(KERN_INFO "%s %s COMPOSITE output\n", stdstr, tvstr);
- orSISIDXREG(SISCR, 0x32, 0x01);
+ SiS_SetRegOR(SISCR, 0x32, 0x01);
}
}
}
SISDoSense(ivideo, 0, 0);
- outSISIDXREG(SISPART2,0x00,backupP2_00);
- outSISIDXREG(SISPART4,0x0d,backupP4_0d);
- outSISIDXREG(SISSR,0x1e,backupSR_1e);
+ SiS_SetReg(SISPART2, 0x00, backupP2_00);
+ SiS_SetReg(SISPART4, 0x0d, backupP4_0d);
+ SiS_SetReg(SISSR, 0x1e, backupSR_1e);
if(ivideo->vbflags2 & VB2_30xCLV) {
- inSISIDXREG(SISPART2,0x00,biosflag);
+ biosflag = SiS_GetReg(SISPART2, 0x00);
if(biosflag & 0x20) {
for(myflag = 2; myflag > 0; myflag--) {
biosflag ^= 0x20;
- outSISIDXREG(SISPART2,0x00,biosflag);
+ SiS_SetReg(SISPART2, 0x00, biosflag);
}
}
}
- outSISIDXREG(SISPART2,0x00,backupP2_00);
+ SiS_SetReg(SISPART2, 0x00, backupP2_00);
}
/* Determine and detect attached TV's on Chrontel */
if(temp1 == 0x02) {
printk(KERN_INFO "%s SVIDEO output\n", stdstr);
ivideo->vbflags |= TV_SVIDEO;
- orSISIDXREG(SISCR, 0x32, 0x02);
- andSISIDXREG(SISCR, 0x32, ~0x05);
+ SiS_SetRegOR(SISCR, 0x32, 0x02);
+ SiS_SetRegAND(SISCR, 0x32, ~0x05);
} else if (temp1 == 0x01) {
printk(KERN_INFO "%s CVBS output\n", stdstr);
ivideo->vbflags |= TV_AVIDEO;
- orSISIDXREG(SISCR, 0x32, 0x01);
- andSISIDXREG(SISCR, 0x32, ~0x06);
+ SiS_SetRegOR(SISCR, 0x32, 0x01);
+ SiS_SetRegAND(SISCR, 0x32, ~0x06);
} else {
SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x0e, 0x01, 0xF8);
- andSISIDXREG(SISCR, 0x32, ~0x07);
+ SiS_SetRegAND(SISCR, 0x32, ~0x07);
}
} else if(temp1 == 0) {
SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x0e, 0x01, 0xF8);
- andSISIDXREG(SISCR, 0x32, ~0x07);
+ SiS_SetRegAND(SISCR, 0x32, ~0x07);
}
/* Set general purpose IO for Chrontel communication */
SiS_SetChrontelGPIO(&ivideo->SiS_Pr, 0x00);
case 0x01:
printk(KERN_INFO "%s CVBS output\n", stdstr);
ivideo->vbflags |= TV_AVIDEO;
- orSISIDXREG(SISCR, 0x32, 0x01);
- andSISIDXREG(SISCR, 0x32, ~0x06);
+ SiS_SetRegOR(SISCR, 0x32, 0x01);
+ SiS_SetRegAND(SISCR, 0x32, ~0x06);
break;
case 0x02:
printk(KERN_INFO "%s SVIDEO output\n", stdstr);
ivideo->vbflags |= TV_SVIDEO;
- orSISIDXREG(SISCR, 0x32, 0x02);
- andSISIDXREG(SISCR, 0x32, ~0x05);
+ SiS_SetRegOR(SISCR, 0x32, 0x02);
+ SiS_SetRegAND(SISCR, 0x32, ~0x05);
break;
case 0x04:
printk(KERN_INFO "%s SCART output\n", stdstr);
- orSISIDXREG(SISCR, 0x32, 0x04);
- andSISIDXREG(SISCR, 0x32, ~0x03);
+ SiS_SetRegOR(SISCR, 0x32, 0x04);
+ SiS_SetRegAND(SISCR, 0x32, ~0x03);
break;
default:
- andSISIDXREG(SISCR, 0x32, ~0x07);
+ SiS_SetRegAND(SISCR, 0x32, ~0x07);
}
#endif
}
if(ivideo->chip == XGI_20)
return;
- inSISIDXREG(SISPART4, 0x00, vb_chipid);
+ vb_chipid = SiS_GetReg(SISPART4, 0x00);
switch(vb_chipid) {
case 0x01:
- inSISIDXREG(SISPART4, 0x01, reg);
+ reg = SiS_GetReg(SISPART4, 0x01);
if(reg < 0xb0) {
ivideo->vbflags |= VB_301; /* Deprecated */
ivideo->vbflags2 |= VB2_301;
} else if(reg < 0xc0) {
ivideo->vbflags |= VB_301B; /* Deprecated */
ivideo->vbflags2 |= VB2_301B;
- inSISIDXREG(SISPART4,0x23,reg);
+ reg = SiS_GetReg(SISPART4, 0x23);
if(!(reg & 0x02)) {
ivideo->vbflags |= VB_30xBDH; /* Deprecated */
ivideo->vbflags2 |= VB2_30xBDH;
ivideo->vbflags2 |= VB2_301LV;
printk(KERN_INFO "%s SiS301LV %s\n", stdstr, bridgestr);
} else if(reg <= 0xe1) {
- inSISIDXREG(SISPART4,0x39,reg);
+ reg = SiS_GetReg(SISPART4, 0x39);
if(reg == 0xff) {
ivideo->vbflags |= VB_302LV; /* Deprecated */
ivideo->vbflags2 |= VB2_302LV;
}
if((!(ivideo->vbflags2 & VB2_VIDEOBRIDGE)) && (ivideo->chip != SIS_300)) {
- inSISIDXREG(SISCR, 0x37, reg);
+ reg = SiS_GetReg(SISCR, 0x37);
reg &= SIS_EXTERNAL_CHIP_MASK;
reg >>= 1;
if(ivideo->sisvga_engine == SIS_300_VGA) {
#endif
} else if(ivideo->chip >= SIS_661) {
#ifdef CONFIG_FB_SIS_315
- inSISIDXREG(SISCR, 0x38, reg);
+ reg = SiS_GetReg(SISCR, 0x38);
reg >>= 5;
switch(reg) {
case 0x02:
tqueue_pos = (ivideo->video_size - ivideo->cmdQueueSize) / (64 * 1024);
- inSISIDXREG(SISSR, IND_SIS_TURBOQUEUE_SET, tq_state);
+ tq_state = SiS_GetReg(SISSR, IND_SIS_TURBOQUEUE_SET);
tq_state |= 0xf0;
tq_state &= 0xfc;
tq_state |= (u8)(tqueue_pos >> 8);
- outSISIDXREG(SISSR, IND_SIS_TURBOQUEUE_SET, tq_state);
+ SiS_SetReg(SISSR, IND_SIS_TURBOQUEUE_SET, tq_state);
- outSISIDXREG(SISSR, IND_SIS_TURBOQUEUE_ADR, (u8)(tqueue_pos & 0xff));
+ SiS_SetReg(SISSR, IND_SIS_TURBOQUEUE_ADR, (u8)(tqueue_pos & 0xff));
ivideo->caps |= TURBO_QUEUE_CAP;
}
}
}
- outSISIDXREG(SISSR, IND_SIS_CMDQUEUE_THRESHOLD, COMMAND_QUEUE_THRESHOLD);
- outSISIDXREG(SISSR, IND_SIS_CMDQUEUE_SET, SIS_CMD_QUEUE_RESET);
+ SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_THRESHOLD, COMMAND_QUEUE_THRESHOLD);
+ SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_SET, SIS_CMD_QUEUE_RESET);
if((ivideo->chip >= XGI_40) && ivideo->modechanged) {
/* Must disable dual pipe on XGI_40. Can't do
MMIO_OUT32(ivideo->mmio_vbase, Q_WRITE_PTR, 0);
- outSISIDXREG(SISSR, IND_SIS_CMDQUEUE_SET, (temp | SIS_VRAM_CMDQUEUE_ENABLE));
+ SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_SET, (temp | SIS_VRAM_CMDQUEUE_ENABLE));
tempq = MMIO_IN32(ivideo->mmio_vbase, Q_READ_PTR);
MMIO_OUT32(ivideo->mmio_vbase, Q_WRITE_PTR, tempq);
sisfb_syncaccel(ivideo);
- outSISIDXREG(SISSR, IND_SIS_CMDQUEUE_SET, SIS_CMD_QUEUE_RESET);
+ SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_SET, SIS_CMD_QUEUE_RESET);
}
}
MMIO_OUT32(ivideo->mmio_vbase, MMIO_QUEUE_WRITEPORT, tempq);
temp |= (SIS_MMIO_CMD_ENABLE | SIS_CMD_AUTO_CORR);
- outSISIDXREG(SISSR, IND_SIS_CMDQUEUE_SET, temp);
+ SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_SET, temp);
tempq = (u32)(ivideo->video_size - ivideo->cmdQueueSize);
MMIO_OUT32(ivideo->mmio_vbase, MMIO_QUEUE_PHYBASE, tempq);
u8 reg;
int i;
- inSISIDXREG(SISCR, 0x36, reg);
+ reg = SiS_GetReg(SISCR, 0x36);
reg &= 0x0f;
if(ivideo->sisvga_engine == SIS_300_VGA) {
ivideo->CRT2LCDType = sis300paneltype[reg];
if(ivideo->CRT2LCDType == LCD_UNKNOWN) {
/* For broken BIOSes: Assume 1024x768, RGB18 */
ivideo->CRT2LCDType = LCD_1024x768;
- setSISIDXREG(SISCR,0x36,0xf0,0x02);
- setSISIDXREG(SISCR,0x37,0xee,0x01);
+ SiS_SetRegANDOR(SISCR, 0x36, 0xf0, 0x02);
+ SiS_SetRegANDOR(SISCR, 0x37, 0xee, 0x01);
printk(KERN_DEBUG "sisfb: Invalid panel ID (%02x), assuming 1024x768, RGB18\n", reg);
}
if(ivideo->sisvga_engine == SIS_300_VGA) {
if(ivideo->vbflags2 & (VB2_LVDS | VB2_30xBDH)) {
int tmp;
- inSISIDXREG(SISCR,0x30,tmp);
+ tmp = SiS_GetReg(SISCR, 0x30);
if(tmp & 0x20) {
/* Currently on LCD? If yes, read current pdc */
- inSISIDXREG(SISPART1,0x13,ivideo->detectedpdc);
+ ivideo->detectedpdc = SiS_GetReg(SISPART1, 0x13);
ivideo->detectedpdc &= 0x3c;
if(ivideo->SiS_Pr.PDC == -1) {
/* Let option override detection */
/* Try to find about LCDA */
if(ivideo->vbflags2 & VB2_SISLCDABRIDGE) {
int tmp;
- inSISIDXREG(SISPART1,0x13,tmp);
+ tmp = SiS_GetReg(SISPART1, 0x13);
if(tmp & 0x04) {
ivideo->SiS_Pr.SiS_UseLCDA = true;
ivideo->detectedlcda = 0x03;
/* Save PDC */
if(ivideo->vbflags2 & VB2_SISLVDSBRIDGE) {
int tmp;
- inSISIDXREG(SISCR,0x30,tmp);
+ tmp = SiS_GetReg(SISCR, 0x30);
if((tmp & 0x20) || (ivideo->detectedlcda != 0xff)) {
/* Currently on LCD? If yes, read current pdc */
u8 pdc;
- inSISIDXREG(SISPART1,0x2D,pdc);
+ pdc = SiS_GetReg(SISPART1, 0x2D);
ivideo->detectedpdc = (pdc & 0x0f) << 1;
ivideo->detectedpdca = (pdc & 0xf0) >> 3;
- inSISIDXREG(SISPART1,0x35,pdc);
+ pdc = SiS_GetReg(SISPART1, 0x35);
ivideo->detectedpdc |= ((pdc >> 7) & 0x01);
- inSISIDXREG(SISPART1,0x20,pdc);
+ pdc = SiS_GetReg(SISPART1, 0x20);
ivideo->detectedpdca |= ((pdc >> 6) & 0x01);
if(ivideo->newrom) {
/* New ROM invalidates other PDC resp. */
/* Save EMI */
if(ivideo->vbflags2 & VB2_SISEMIBRIDGE) {
- inSISIDXREG(SISPART4,0x30,ivideo->SiS_Pr.EMI_30);
- inSISIDXREG(SISPART4,0x31,ivideo->SiS_Pr.EMI_31);
- inSISIDXREG(SISPART4,0x32,ivideo->SiS_Pr.EMI_32);
- inSISIDXREG(SISPART4,0x33,ivideo->SiS_Pr.EMI_33);
+ ivideo->SiS_Pr.EMI_30 = SiS_GetReg(SISPART4, 0x30);
+ ivideo->SiS_Pr.EMI_31 = SiS_GetReg(SISPART4, 0x31);
+ ivideo->SiS_Pr.EMI_32 = SiS_GetReg(SISPART4, 0x32);
+ ivideo->SiS_Pr.EMI_33 = SiS_GetReg(SISPART4, 0x33);
ivideo->SiS_Pr.HaveEMI = true;
if((tmp & 0x20) || (ivideo->detectedlcda != 0xff)) {
ivideo->SiS_Pr.HaveEMILCD = true;
* ivideo->accel here, as this might have
* been changed before this is called.
*/
- inSISIDXREG(SISSR, IND_SIS_PCI_ADDRESS_SET, cr30);
- inSISIDXREG(SISSR, IND_SIS_MODULE_ENABLE, cr31);
+ cr30 = SiS_GetReg(SISSR, IND_SIS_PCI_ADDRESS_SET);
+ cr31 = SiS_GetReg(SISSR, IND_SIS_MODULE_ENABLE);
/* MMIO and 2D/3D engine enabled? */
if((cr30 & SIS_MEM_MAP_IO_ENABLE) && (cr31 & 0x42)) {
#ifdef CONFIG_FB_SIS_300
* enabled, and that the queue
* is not in the state of "reset"
*/
- inSISIDXREG(SISSR, 0x26, cr30);
+ cr30 = SiS_GetReg(SISSR, 0x26);
if((cr30 & 0xe0) && (!(cr30 & 0x01))) {
sisfb_syncaccel(ivideo);
}
ivideo->currentvbflags &= (VB_VIDEOBRIDGE | VB_DISPTYPE_DISP2);
- outSISIDXREG(SISSR, 0x05, 0x86);
+ SiS_SetReg(SISSR, 0x05, 0x86);
- inSISIDXREG(SISCR, 0x31, cr31);
+ cr31 = SiS_GetReg(SISCR, 0x31);
cr31 &= ~0x60;
cr31 |= 0x04;
#ifdef CONFIG_FB_SIS_315
if(ivideo->sisvga_engine == SIS_315_VGA) {
if(ivideo->chip >= SIS_661) {
- inSISIDXREG(SISCR, 0x38, cr38);
+ cr38 = SiS_GetReg(SISCR, 0x38);
cr38 &= ~0x07; /* Clear LCDA/DualEdge and YPbPr bits */
} else {
tvregnum = 0x38;
- inSISIDXREG(SISCR, tvregnum, cr38);
+ cr38 = SiS_GetReg(SISCR, tvregnum);
cr38 &= ~0x3b; /* Clear LCDA/DualEdge and YPbPr bits */
}
}
#ifdef CONFIG_FB_SIS_300
if(ivideo->sisvga_engine == SIS_300_VGA) {
tvregnum = 0x35;
- inSISIDXREG(SISCR, tvregnum, cr38);
+ cr38 = SiS_GetReg(SISCR, tvregnum);
}
#endif
cr31 |= (SIS_DRIVER_MODE | SIS_VB_OUTPUT_DISABLE);
}
- outSISIDXREG(SISCR, 0x30, cr30);
- outSISIDXREG(SISCR, 0x33, cr33);
+ SiS_SetReg(SISCR, 0x30, cr30);
+ SiS_SetReg(SISCR, 0x33, cr33);
if(ivideo->chip >= SIS_661) {
#ifdef CONFIG_FB_SIS_315
cr31 &= ~0x01; /* Clear PAL flag (now in CR35) */
- setSISIDXREG(SISCR, 0x35, ~0x10, cr35); /* Leave overscan bit alone */
+ SiS_SetRegANDOR(SISCR, 0x35, ~0x10, cr35); /* Leave overscan bit alone */
cr38 &= 0x07; /* Use only LCDA and HiVision/YPbPr bits */
- setSISIDXREG(SISCR, 0x38, 0xf8, cr38);
+ SiS_SetRegANDOR(SISCR, 0x38, 0xf8, cr38);
#endif
} else if(ivideo->chip != SIS_300) {
- outSISIDXREG(SISCR, tvregnum, cr38);
+ SiS_SetReg(SISCR, tvregnum, cr38);
}
- outSISIDXREG(SISCR, 0x31, cr31);
+ SiS_SetReg(SISCR, 0x31, cr31);
ivideo->SiS_Pr.SiS_UseOEM = ivideo->sisfb_useoem;
u8 tmpreg;
if(ivideo->chip >= SIS_661) {
- inSISIDXREG(SISSR,0x11,tmpreg);
+ tmpreg = SiS_GetReg(SISSR, 0x11);
if(tmpreg & 0x20) {
- inSISIDXREG(SISSR,0x3e,tmpreg);
+ tmpreg = SiS_GetReg(SISSR, 0x3e);
tmpreg = (tmpreg + 1) & 0xff;
- outSISIDXREG(SISSR,0x3e,tmpreg);
- inSISIDXREG(SISSR,0x11,tmpreg);
+ SiS_SetReg(SISSR, 0x3e, tmpreg);
+ tmpreg = SiS_GetReg(SISSR, 0x11);
}
if(tmpreg & 0xf0) {
- andSISIDXREG(SISSR,0x11,0x0f);
+ SiS_SetRegAND(SISSR, 0x11, 0x0f);
}
}
}
case 1:
x += val;
if(x < 0) x = 0;
- outSISIDXREG(SISSR,0x05,0x86);
+ SiS_SetReg(SISSR, 0x05, 0x86);
SiS_SetCH700x(&ivideo->SiS_Pr, 0x0a, (x & 0xff));
SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x08, ((x & 0x0100) >> 7), 0xFD);
break;
temp += (val * 2);
p2_43 = temp & 0xff;
p2_42 = (temp & 0xf00) >> 4;
- outSISIDXREG(SISPART2,0x1f,p2_1f);
- setSISIDXREG(SISPART2,0x20,0x0F,p2_20);
- setSISIDXREG(SISPART2,0x2b,0xF0,p2_2b);
- setSISIDXREG(SISPART2,0x42,0x0F,p2_42);
- outSISIDXREG(SISPART2,0x43,p2_43);
+ SiS_SetReg(SISPART2, 0x1f, p2_1f);
+ SiS_SetRegANDOR(SISPART2, 0x20, 0x0F, p2_20);
+ SiS_SetRegANDOR(SISPART2, 0x2b, 0xF0, p2_2b);
+ SiS_SetRegANDOR(SISPART2, 0x42, 0x0F, p2_42);
+ SiS_SetReg(SISPART2, 0x43, p2_43);
}
}
}
case 1:
y -= val;
if(y < 0) y = 0;
- outSISIDXREG(SISSR,0x05,0x86);
+ SiS_SetReg(SISSR, 0x05, 0x86);
SiS_SetCH700x(&ivideo->SiS_Pr, 0x0b, (y & 0xff));
SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x08, ((y & 0x0100) >> 8), 0xFE);
break;
p2_02 += 2;
}
}
- outSISIDXREG(SISPART2,0x01,p2_01);
- outSISIDXREG(SISPART2,0x02,p2_02);
+ SiS_SetReg(SISPART2, 0x01, p2_01);
+ SiS_SetReg(SISPART2, 0x02, p2_02);
}
}
}
u8 reg1;
#endif
- outSISIDXREG(SISSR, 0x05, 0x86);
+ SiS_SetReg(SISSR, 0x05, 0x86);
#ifdef CONFIG_FB_SIS_315
sisfb_fixup_SR11(ivideo);
crt1isoff = false;
reg = 0x80;
}
- setSISIDXREG(SISCR, 0x17, 0x7f, reg);
+ SiS_SetRegANDOR(SISCR, 0x17, 0x7f, reg);
}
#endif
#ifdef CONFIG_FB_SIS_315
reg = 0x00;
reg1 = 0x00;
}
- setSISIDXREG(SISCR, ivideo->SiS_Pr.SiS_MyCR63, ~0x40, reg);
- setSISIDXREG(SISSR, 0x1f, ~0xc0, reg1);
+ SiS_SetRegANDOR(SISCR, ivideo->SiS_Pr.SiS_MyCR63, ~0x40, reg);
+ SiS_SetRegANDOR(SISSR, 0x1f, 0x3f, reg1);
}
#endif
}
}
- andSISIDXREG(SISSR, IND_SIS_RAMDAC_CONTROL, ~0x04);
+ SiS_SetRegAND(SISSR, IND_SIS_RAMDAC_CONTROL, ~0x04);
if(ivideo->currentvbflags & CRT2_TV) {
if(ivideo->vbflags2 & VB2_SISBRIDGE) {
- inSISIDXREG(SISPART2,0x1f,ivideo->p2_1f);
- inSISIDXREG(SISPART2,0x20,ivideo->p2_20);
- inSISIDXREG(SISPART2,0x2b,ivideo->p2_2b);
- inSISIDXREG(SISPART2,0x42,ivideo->p2_42);
- inSISIDXREG(SISPART2,0x43,ivideo->p2_43);
- inSISIDXREG(SISPART2,0x01,ivideo->p2_01);
- inSISIDXREG(SISPART2,0x02,ivideo->p2_02);
+ ivideo->p2_1f = SiS_GetReg(SISPART2, 0x1f);
+ ivideo->p2_20 = SiS_GetReg(SISPART2, 0x20);
+ ivideo->p2_2b = SiS_GetReg(SISPART2, 0x2b);
+ ivideo->p2_42 = SiS_GetReg(SISPART2, 0x42);
+ ivideo->p2_43 = SiS_GetReg(SISPART2, 0x43);
+ ivideo->p2_01 = SiS_GetReg(SISPART2, 0x01);
+ ivideo->p2_02 = SiS_GetReg(SISPART2, 0x02);
} else if(ivideo->vbflags2 & VB2_CHRONTEL) {
if(ivideo->chronteltype == 1) {
ivideo->tvx = SiS_GetCH700x(&ivideo->SiS_Pr, 0x0a);
struct sis_video_info *ivideo = pci_get_drvdata(pdev);
void __iomem *rom_base;
unsigned char *myrombase = NULL;
- u32 temp;
size_t romsize;
/* First, try the official pci ROM functions (except
/* Otherwise do it the conventional way. */
#if defined(__i386__) || defined(__x86_64__)
+ {
+ u32 temp;
- for(temp = 0x000c0000; temp < 0x000f0000; temp += 0x00001000) {
+ for (temp = 0x000c0000; temp < 0x000f0000; temp += 0x00001000) {
- rom_base = ioremap(temp, 65536);
- if(!rom_base)
- continue;
+ rom_base = ioremap(temp, 65536);
+ if (!rom_base)
+ continue;
- if(!sisfb_check_rom(rom_base, ivideo)) {
- iounmap(rom_base);
- continue;
- }
+ if (!sisfb_check_rom(rom_base, ivideo)) {
+ iounmap(rom_base);
+ continue;
+ }
- if((myrombase = vmalloc(65536)))
- memcpy_fromio(myrombase, rom_base, 65536);
+ if ((myrombase = vmalloc(65536)))
+ memcpy_fromio(myrombase, rom_base, 65536);
- iounmap(rom_base);
- break;
+ iounmap(rom_base);
+ break;
- }
+ }
+ }
#endif
return myrombase;
unsigned char reg;
int i, j;
- andSISIDXREG(SISSR, 0x15, 0xFB);
- orSISIDXREG(SISSR, 0x15, 0x04);
- outSISIDXREG(SISSR, 0x13, 0x00);
- outSISIDXREG(SISSR, 0x14, 0xBF);
+ SiS_SetRegAND(SISSR, 0x15, 0xFB);
+ SiS_SetRegOR(SISSR, 0x15, 0x04);
+ SiS_SetReg(SISSR, 0x13, 0x00);
+ SiS_SetReg(SISSR, 0x14, 0xBF);
for(i = 0; i < 2; i++) {
temp = 0x1234;
writew(temp, FBAddress);
if(readw(FBAddress) == temp)
break;
- orSISIDXREG(SISSR, 0x3c, 0x01);
- inSISIDXREG(SISSR, 0x05, reg);
- inSISIDXREG(SISSR, 0x05, reg);
- andSISIDXREG(SISSR, 0x3c, 0xfe);
- inSISIDXREG(SISSR, 0x05, reg);
- inSISIDXREG(SISSR, 0x05, reg);
+ SiS_SetRegOR(SISSR, 0x3c, 0x01);
+ reg = SiS_GetReg(SISSR, 0x05);
+ reg = SiS_GetReg(SISSR, 0x05);
+ SiS_SetRegAND(SISSR, 0x3c, 0xfe);
+ reg = SiS_GetReg(SISSR, 0x05);
+ reg = SiS_GetReg(SISSR, 0x05);
temp++;
}
}
writel(0x89ABCDEFL, (FBAddress + 8));
writel(0xCDEF0123L, (FBAddress + 12));
- inSISIDXREG(SISSR, 0x3b, reg);
+ reg = SiS_GetReg(SISSR, 0x3b);
if(reg & 0x01) {
if(readl((FBAddress + 12)) == 0xCDEF0123L)
return 4; /* Channel A 128bit */
PhysicalAdrHalfPage = (PageCapacity / 2 + PhysicalAdrHigh) % PageCapacity;
PhysicalAdrOtherPage = PageCapacity * SiS_DRAMType[k][2] + PhysicalAdrHigh;
- andSISIDXREG(SISSR, 0x15, 0xFB); /* Test */
- orSISIDXREG(SISSR, 0x15, 0x04); /* Test */
+ SiS_SetRegAND(SISSR, 0x15, 0xFB); /* Test */
+ SiS_SetRegOR(SISSR, 0x15, 0x04); /* Test */
sr14 = (SiS_DRAMType[k][3] * buswidth) - 1;
if(buswidth == 4) sr14 |= 0x80;
else if(buswidth == 2) sr14 |= 0x40;
- outSISIDXREG(SISSR, 0x13, SiS_DRAMType[k][4]);
- outSISIDXREG(SISSR, 0x14, sr14);
+ SiS_SetReg(SISSR, 0x13, SiS_DRAMType[k][4]);
+ SiS_SetReg(SISSR, 0x14, sr14);
BankNumHigh <<= 16;
BankNumMid <<= 16;
if(!ivideo->SiS_Pr.UseROM)
bios = NULL;
- outSISIDXREG(SISSR, 0x05, 0x86);
+ SiS_SetReg(SISSR, 0x05, 0x86);
if(bios) {
if(bios[0x52] & 0x80) {
memtype = bios[0x52];
} else {
- inSISIDXREG(SISSR, 0x3a, memtype);
+ memtype = SiS_GetReg(SISSR, 0x3a);
}
memtype &= 0x07;
}
v6 = bios[rindex++];
}
}
- outSISIDXREG(SISSR, 0x28, v1);
- outSISIDXREG(SISSR, 0x29, v2);
- outSISIDXREG(SISSR, 0x2a, v3);
- outSISIDXREG(SISSR, 0x2e, v4);
- outSISIDXREG(SISSR, 0x2f, v5);
- outSISIDXREG(SISSR, 0x30, v6);
+ SiS_SetReg(SISSR, 0x28, v1);
+ SiS_SetReg(SISSR, 0x29, v2);
+ SiS_SetReg(SISSR, 0x2a, v3);
+ SiS_SetReg(SISSR, 0x2e, v4);
+ SiS_SetReg(SISSR, 0x2f, v5);
+ SiS_SetReg(SISSR, 0x30, v6);
v1 = 0x10;
if(bios)
v1 = bios[0xa4];
- outSISIDXREG(SISSR, 0x07, v1); /* DAC speed */
+ SiS_SetReg(SISSR, 0x07, v1); /* DAC speed */
- outSISIDXREG(SISSR, 0x11, 0x0f); /* DDC, power save */
+ SiS_SetReg(SISSR, 0x11, 0x0f); /* DDC, power save */
v1 = 0x01; v2 = 0x43; v3 = 0x1e; v4 = 0x2a;
v5 = 0x06; v6 = 0x00; v7 = 0x00; v8 = 0x00;
}
if(ivideo->revision_id >= 0x80)
v3 &= 0xfd;
- outSISIDXREG(SISSR, 0x15, v1); /* Ram type (assuming 0, BIOS 0xa5 step 8) */
- outSISIDXREG(SISSR, 0x16, v2);
- outSISIDXREG(SISSR, 0x17, v3);
- outSISIDXREG(SISSR, 0x18, v4);
- outSISIDXREG(SISSR, 0x19, v5);
- outSISIDXREG(SISSR, 0x1a, v6);
- outSISIDXREG(SISSR, 0x1b, v7);
- outSISIDXREG(SISSR, 0x1c, v8); /* ---- */
- andSISIDXREG(SISSR, 0x15 ,0xfb);
- orSISIDXREG(SISSR, 0x15, 0x04);
+ SiS_SetReg(SISSR, 0x15, v1); /* Ram type (assuming 0, BIOS 0xa5 step 8) */
+ SiS_SetReg(SISSR, 0x16, v2);
+ SiS_SetReg(SISSR, 0x17, v3);
+ SiS_SetReg(SISSR, 0x18, v4);
+ SiS_SetReg(SISSR, 0x19, v5);
+ SiS_SetReg(SISSR, 0x1a, v6);
+ SiS_SetReg(SISSR, 0x1b, v7);
+ SiS_SetReg(SISSR, 0x1c, v8); /* ---- */
+ SiS_SetRegAND(SISSR, 0x15, 0xfb);
+ SiS_SetRegOR(SISSR, 0x15, 0x04);
if(bios) {
if(bios[0x53] & 0x02) {
- orSISIDXREG(SISSR, 0x19, 0x20);
+ SiS_SetRegOR(SISSR, 0x19, 0x20);
}
}
v1 = 0x04; /* DAC pedestal (BIOS 0xe5) */
if(ivideo->revision_id >= 0x80)
v1 |= 0x01;
- outSISIDXREG(SISSR, 0x1f, v1);
- outSISIDXREG(SISSR, 0x20, 0xa4); /* linear & relocated io & disable a0000 */
+ SiS_SetReg(SISSR, 0x1f, v1);
+ SiS_SetReg(SISSR, 0x20, 0xa4); /* linear & relocated io & disable a0000 */
v1 = 0xf6; v2 = 0x0d; v3 = 0x00;
if(bios) {
v1 = bios[0xe8];
v2 = bios[0xe9];
v3 = bios[0xea];
}
- outSISIDXREG(SISSR, 0x23, v1);
- outSISIDXREG(SISSR, 0x24, v2);
- outSISIDXREG(SISSR, 0x25, v3);
- outSISIDXREG(SISSR, 0x21, 0x84);
- outSISIDXREG(SISSR, 0x22, 0x00);
- outSISIDXREG(SISCR, 0x37, 0x00);
- orSISIDXREG(SISPART1, 0x24, 0x01); /* unlock crt2 */
- outSISIDXREG(SISPART1, 0x00, 0x00);
+ SiS_SetReg(SISSR, 0x23, v1);
+ SiS_SetReg(SISSR, 0x24, v2);
+ SiS_SetReg(SISSR, 0x25, v3);
+ SiS_SetReg(SISSR, 0x21, 0x84);
+ SiS_SetReg(SISSR, 0x22, 0x00);
+ SiS_SetReg(SISCR, 0x37, 0x00);
+ SiS_SetRegOR(SISPART1, 0x24, 0x01); /* unlock crt2 */
+ SiS_SetReg(SISPART1, 0x00, 0x00);
v1 = 0x40; v2 = 0x11;
if(bios) {
v1 = bios[0xec];
v2 = bios[0xeb];
}
- outSISIDXREG(SISPART1, 0x02, v1);
+ SiS_SetReg(SISPART1, 0x02, v1);
if(ivideo->revision_id >= 0x80)
v2 &= ~0x01;
- inSISIDXREG(SISPART4, 0x00, reg);
+ reg = SiS_GetReg(SISPART4, 0x00);
if((reg == 1) || (reg == 2)) {
- outSISIDXREG(SISCR, 0x37, 0x02);
- outSISIDXREG(SISPART2, 0x00, 0x1c);
+ SiS_SetReg(SISCR, 0x37, 0x02);
+ SiS_SetReg(SISPART2, 0x00, 0x1c);
v4 = 0x00; v5 = 0x00; v6 = 0x10;
if(ivideo->SiS_Pr.UseROM) {
v4 = bios[0xf5];
v5 = bios[0xf6];
v6 = bios[0xf7];
}
- outSISIDXREG(SISPART4, 0x0d, v4);
- outSISIDXREG(SISPART4, 0x0e, v5);
- outSISIDXREG(SISPART4, 0x10, v6);
- outSISIDXREG(SISPART4, 0x0f, 0x3f);
- inSISIDXREG(SISPART4, 0x01, reg);
+ SiS_SetReg(SISPART4, 0x0d, v4);
+ SiS_SetReg(SISPART4, 0x0e, v5);
+ SiS_SetReg(SISPART4, 0x10, v6);
+ SiS_SetReg(SISPART4, 0x0f, 0x3f);
+ reg = SiS_GetReg(SISPART4, 0x01);
if(reg >= 0xb0) {
- inSISIDXREG(SISPART4, 0x23, reg);
+ reg = SiS_GetReg(SISPART4, 0x23);
reg &= 0x20;
reg <<= 1;
- outSISIDXREG(SISPART4, 0x23, reg);
+ SiS_SetReg(SISPART4, 0x23, reg);
}
} else {
v2 &= ~0x10;
}
- outSISIDXREG(SISSR, 0x32, v2);
+ SiS_SetReg(SISSR, 0x32, v2);
- andSISIDXREG(SISPART1, 0x24, 0xfe); /* Lock CRT2 */
+ SiS_SetRegAND(SISPART1, 0x24, 0xfe); /* Lock CRT2 */
- inSISIDXREG(SISSR, 0x16, reg);
+ reg = SiS_GetReg(SISSR, 0x16);
reg &= 0xc3;
- outSISIDXREG(SISCR, 0x35, reg);
- outSISIDXREG(SISCR, 0x83, 0x00);
+ SiS_SetReg(SISCR, 0x35, reg);
+ SiS_SetReg(SISCR, 0x83, 0x00);
#if !defined(__i386__) && !defined(__x86_64__)
if(sisfb_videoram) {
- outSISIDXREG(SISSR, 0x13, 0x28); /* ? */
+ SiS_SetReg(SISSR, 0x13, 0x28); /* ? */
reg = ((sisfb_videoram >> 10) - 1) | 0x40;
- outSISIDXREG(SISSR, 0x14, reg);
+ SiS_SetReg(SISSR, 0x14, reg);
} else {
#endif
/* Need to map max FB size for finding out about RAM size */
} else {
printk(KERN_DEBUG
"sisfb: Failed to map memory for size detection, assuming 8MB\n");
- outSISIDXREG(SISSR, 0x13, 0x28); /* ? */
- outSISIDXREG(SISSR, 0x14, 0x47); /* 8MB, 64bit default */
+ SiS_SetReg(SISSR, 0x13, 0x28); /* ? */
+ SiS_SetReg(SISSR, 0x14, 0x47); /* 8MB, 64bit default */
}
#if !defined(__i386__) && !defined(__x86_64__)
}
v1 = bios[0xe6];
v2 = bios[0xe7];
} else {
- inSISIDXREG(SISSR, 0x3a, reg);
+ reg = SiS_GetReg(SISSR, 0x3a);
if((reg & 0x30) == 0x30) {
v1 = 0x04; /* PCI */
v2 = 0x92;
v2 = 0xb2;
}
}
- outSISIDXREG(SISSR, 0x21, v1);
- outSISIDXREG(SISSR, 0x22, v2);
+ SiS_SetReg(SISSR, 0x21, v1);
+ SiS_SetReg(SISSR, 0x22, v2);
/* Sense CRT1 */
sisfb_sense_crt1(ivideo);
ivideo->SiS_Pr.VideoMemorySize = 8 << 20;
SiSSetMode(&ivideo->SiS_Pr, 0x2e | 0x80);
- outSISIDXREG(SISSR, 0x05, 0x86);
+ SiS_SetReg(SISSR, 0x05, 0x86);
/* Display off */
- orSISIDXREG(SISSR, 0x01, 0x20);
+ SiS_SetRegOR(SISSR, 0x01, 0x20);
/* Save mode number in CR34 */
- outSISIDXREG(SISCR, 0x34, 0x2e);
+ SiS_SetReg(SISCR, 0x34, 0x2e);
/* Let everyone know what the current mode is */
ivideo->modeprechange = 0x2e;
u8 reg;
for(i = 0; i <= (delay * 10 * 36); i++) {
- inSISIDXREG(SISSR, 0x05, reg);
+ reg = SiS_GetReg(SISSR, 0x05);
reg++;
}
}
* - if running on non-x86, there usually is no VGA window
* at a0000.
*/
- orSISIDXREG(SISSR, 0x20, (0x80 | 0x04));
+ SiS_SetRegOR(SISSR, 0x20, (0x80 | 0x04));
/* Need to map max FB size for finding out about RAM size */
mapsize = ivideo->video_size;
if(!ivideo->video_vbase) {
printk(KERN_ERR "sisfb: Unable to detect RAM size. Setting default.\n");
- outSISIDXREG(SISSR, 0x13, 0x35);
- outSISIDXREG(SISSR, 0x14, 0x41);
+ SiS_SetReg(SISSR, 0x13, 0x35);
+ SiS_SetReg(SISSR, 0x14, 0x41);
/* TODO */
return;
}
/* Non-interleaving */
- outSISIDXREG(SISSR, 0x15, 0x00);
+ SiS_SetReg(SISSR, 0x15, 0x00);
/* No tiling */
- outSISIDXREG(SISSR, 0x1c, 0x00);
+ SiS_SetReg(SISSR, 0x1c, 0x00);
if(ivideo->chip == XGI_20) {
channelab = 1;
- inSISIDXREG(SISCR, 0x97, reg);
+ reg = SiS_GetReg(SISCR, 0x97);
if(!(reg & 0x01)) { /* Single 32/16 */
buswidth = 32;
- outSISIDXREG(SISSR, 0x13, 0xb1);
- outSISIDXREG(SISSR, 0x14, 0x52);
+ SiS_SetReg(SISSR, 0x13, 0xb1);
+ SiS_SetReg(SISSR, 0x14, 0x52);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x02;
if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize))
goto bail_out;
- outSISIDXREG(SISSR, 0x13, 0x31);
- outSISIDXREG(SISSR, 0x14, 0x42);
+ SiS_SetReg(SISSR, 0x13, 0x31);
+ SiS_SetReg(SISSR, 0x14, 0x42);
sisfb_post_xgi_delay(ivideo, 1);
if(sisfb_post_xgi_rwtest(ivideo, 23, 23, mapsize))
goto bail_out;
buswidth = 16;
- outSISIDXREG(SISSR, 0x13, 0xb1);
- outSISIDXREG(SISSR, 0x14, 0x41);
+ SiS_SetReg(SISSR, 0x13, 0xb1);
+ SiS_SetReg(SISSR, 0x14, 0x41);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x01;
if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize))
goto bail_out;
else
- outSISIDXREG(SISSR, 0x13, 0x31);
+ SiS_SetReg(SISSR, 0x13, 0x31);
} else { /* Dual 16/8 */
buswidth = 16;
- outSISIDXREG(SISSR, 0x13, 0xb1);
- outSISIDXREG(SISSR, 0x14, 0x41);
+ SiS_SetReg(SISSR, 0x13, 0xb1);
+ SiS_SetReg(SISSR, 0x14, 0x41);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x01;
if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize))
goto bail_out;
- outSISIDXREG(SISSR, 0x13, 0x31);
- outSISIDXREG(SISSR, 0x14, 0x31);
+ SiS_SetReg(SISSR, 0x13, 0x31);
+ SiS_SetReg(SISSR, 0x14, 0x31);
sisfb_post_xgi_delay(ivideo, 1);
if(sisfb_post_xgi_rwtest(ivideo, 22, 22, mapsize))
goto bail_out;
buswidth = 8;
- outSISIDXREG(SISSR, 0x13, 0xb1);
- outSISIDXREG(SISSR, 0x14, 0x30);
+ SiS_SetReg(SISSR, 0x13, 0xb1);
+ SiS_SetReg(SISSR, 0x14, 0x30);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x00;
if(sisfb_post_xgi_rwtest(ivideo, 21, 22, mapsize))
goto bail_out;
else
- outSISIDXREG(SISSR, 0x13, 0x31);
+ SiS_SetReg(SISSR, 0x13, 0x31);
}
} else { /* XGI_40 */
- inSISIDXREG(SISCR, 0x97, reg);
+ reg = SiS_GetReg(SISCR, 0x97);
if(!(reg & 0x10)) {
- inSISIDXREG(SISSR, 0x39, reg);
+ reg = SiS_GetReg(SISSR, 0x39);
reg >>= 1;
}
buswidth = 32;
if(ivideo->revision_id == 2) {
channelab = 2;
- outSISIDXREG(SISSR, 0x13, 0xa1);
- outSISIDXREG(SISSR, 0x14, 0x44);
+ SiS_SetReg(SISSR, 0x13, 0xa1);
+ SiS_SetReg(SISSR, 0x14, 0x44);
sr14 = 0x04;
sisfb_post_xgi_delay(ivideo, 1);
if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize))
goto bail_out;
- outSISIDXREG(SISSR, 0x13, 0x21);
- outSISIDXREG(SISSR, 0x14, 0x34);
+ SiS_SetReg(SISSR, 0x13, 0x21);
+ SiS_SetReg(SISSR, 0x14, 0x34);
if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize))
goto bail_out;
channelab = 1;
- outSISIDXREG(SISSR, 0x13, 0xa1);
- outSISIDXREG(SISSR, 0x14, 0x40);
+ SiS_SetReg(SISSR, 0x13, 0xa1);
+ SiS_SetReg(SISSR, 0x14, 0x40);
sr14 = 0x00;
if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize))
goto bail_out;
- outSISIDXREG(SISSR, 0x13, 0x21);
- outSISIDXREG(SISSR, 0x14, 0x30);
+ SiS_SetReg(SISSR, 0x13, 0x21);
+ SiS_SetReg(SISSR, 0x14, 0x30);
} else {
channelab = 3;
- outSISIDXREG(SISSR, 0x13, 0xa1);
- outSISIDXREG(SISSR, 0x14, 0x4c);
+ SiS_SetReg(SISSR, 0x13, 0xa1);
+ SiS_SetReg(SISSR, 0x14, 0x4c);
sr14 = 0x0c;
sisfb_post_xgi_delay(ivideo, 1);
if(sisfb_post_xgi_rwtest(ivideo, 23, 25, mapsize))
goto bail_out;
channelab = 2;
- outSISIDXREG(SISSR, 0x14, 0x48);
+ SiS_SetReg(SISSR, 0x14, 0x48);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x08;
if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize))
goto bail_out;
- outSISIDXREG(SISSR, 0x13, 0x21);
- outSISIDXREG(SISSR, 0x14, 0x3c);
+ SiS_SetReg(SISSR, 0x13, 0x21);
+ SiS_SetReg(SISSR, 0x14, 0x3c);
sr14 = 0x0c;
if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize)) {
channelab = 3;
} else {
channelab = 2;
- outSISIDXREG(SISSR, 0x14, 0x38);
+ SiS_SetReg(SISSR, 0x14, 0x38);
sr14 = 0x08;
}
}
buswidth = 64;
if(ivideo->revision_id == 2) {
channelab = 1;
- outSISIDXREG(SISSR, 0x13, 0xa1);
- outSISIDXREG(SISSR, 0x14, 0x52);
+ SiS_SetReg(SISSR, 0x13, 0xa1);
+ SiS_SetReg(SISSR, 0x14, 0x52);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x02;
if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize))
goto bail_out;
- outSISIDXREG(SISSR, 0x13, 0x21);
- outSISIDXREG(SISSR, 0x14, 0x42);
+ SiS_SetReg(SISSR, 0x13, 0x21);
+ SiS_SetReg(SISSR, 0x14, 0x42);
} else {
channelab = 2;
- outSISIDXREG(SISSR, 0x13, 0xa1);
- outSISIDXREG(SISSR, 0x14, 0x5a);
+ SiS_SetReg(SISSR, 0x13, 0xa1);
+ SiS_SetReg(SISSR, 0x14, 0x5a);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x0a;
if(sisfb_post_xgi_rwtest(ivideo, 24, 25, mapsize))
goto bail_out;
- outSISIDXREG(SISSR, 0x13, 0x21);
- outSISIDXREG(SISSR, 0x14, 0x4a);
+ SiS_SetReg(SISSR, 0x13, 0x21);
+ SiS_SetReg(SISSR, 0x14, 0x4a);
}
sisfb_post_xgi_delay(ivideo, 1);
}
bail_out:
- setSISIDXREG(SISSR, 0x14, 0xf0, sr14);
+ SiS_SetRegANDOR(SISSR, 0x14, 0xf0, sr14);
sisfb_post_xgi_delay(ivideo, 1);
j = (ivideo->chip == XGI_20) ? 5 : 9;
reg = (ivideo->chip == XGI_20) ?
dramsr13[(i * 5) + 4] : dramsr13_4[(i * 5) + 4];
- setSISIDXREG(SISSR, 0x13, 0x80, reg);
+ SiS_SetRegANDOR(SISSR, 0x13, 0x80, reg);
sisfb_post_xgi_delay(ivideo, 50);
ranksize = (ivideo->chip == XGI_20) ?
dramsr13[(i * 5) + 3] : dramsr13_4[(i * 5) + 3];
- inSISIDXREG(SISSR, 0x13, reg);
+ reg = SiS_GetReg(SISSR, 0x13);
if(reg & 0x80) ranksize <<= 1;
if(ivideo->chip == XGI_20) {
if(!reg) continue;
- setSISIDXREG(SISSR, 0x14, 0x0f, (reg & 0xf0));
+ SiS_SetRegANDOR(SISSR, 0x14, 0x0f, (reg & 0xf0));
sisfb_post_xgi_delay(ivideo, 1);
if(sisfb_post_xgi_rwtest(ivideo, j, ((reg >> 4) + channelab - 2 + 20), mapsize))
v2 = ivideo->bios_abase[0x90 + index + 1];
v3 = ivideo->bios_abase[0x90 + index + 2];
}
- outSISIDXREG(SISSR, 0x28, v1);
- outSISIDXREG(SISSR, 0x29, v2);
- outSISIDXREG(SISSR, 0x2a, v3);
+ SiS_SetReg(SISSR, 0x28, v1);
+ SiS_SetReg(SISSR, 0x29, v2);
+ SiS_SetReg(SISSR, 0x2a, v3);
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
v2 = ivideo->bios_abase[0xb8 + index + 1];
v3 = ivideo->bios_abase[0xb8 + index + 2];
}
- outSISIDXREG(SISSR, 0x2e, v1);
- outSISIDXREG(SISSR, 0x2f, v2);
- outSISIDXREG(SISSR, 0x30, v3);
+ SiS_SetReg(SISSR, 0x2e, v1);
+ SiS_SetReg(SISSR, 0x2f, v2);
+ SiS_SetReg(SISSR, 0x30, v3);
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
};
/* VGA enable */
- reg = inSISREG(SISVGAENABLE) | 0x01;
- outSISREG(SISVGAENABLE, reg);
+ reg = SiS_GetRegByte(SISVGAENABLE) | 0x01;
+ SiS_SetRegByte(SISVGAENABLE, reg);
/* Misc */
- reg = inSISREG(SISMISCR) | 0x01;
- outSISREG(SISMISCW, reg);
+ reg = SiS_GetRegByte(SISMISCR) | 0x01;
+ SiS_SetRegByte(SISMISCW, reg);
/* Unlock SR */
- outSISIDXREG(SISSR, 0x05, 0x86);
- inSISIDXREG(SISSR, 0x05, reg);
+ SiS_SetReg(SISSR, 0x05, 0x86);
+ reg = SiS_GetReg(SISSR, 0x05);
if(reg != 0xa1)
return 0;
/* Clear some regs */
for(i = 0; i < 0x22; i++) {
if(0x06 + i == 0x20) continue;
- outSISIDXREG(SISSR, 0x06 + i, 0x00);
+ SiS_SetReg(SISSR, 0x06 + i, 0x00);
}
for(i = 0; i < 0x0b; i++) {
- outSISIDXREG(SISSR, 0x31 + i, 0x00);
+ SiS_SetReg(SISSR, 0x31 + i, 0x00);
}
for(i = 0; i < 0x10; i++) {
- outSISIDXREG(SISCR, 0x30 + i, 0x00);
+ SiS_SetReg(SISCR, 0x30 + i, 0x00);
}
ptr = cs78;
ptr = (const u8 *)&bios[0x78];
}
for(i = 0; i < 3; i++) {
- outSISIDXREG(SISSR, 0x23 + i, ptr[i]);
+ SiS_SetReg(SISSR, 0x23 + i, ptr[i]);
}
ptr = cs76;
ptr = (const u8 *)&bios[0x76];
}
for(i = 0; i < 2; i++) {
- outSISIDXREG(SISSR, 0x21 + i, ptr[i]);
+ SiS_SetReg(SISSR, 0x21 + i, ptr[i]);
}
v1 = 0x18; v2 = 0x00;
v1 = bios[0x74];
v2 = bios[0x75];
}
- outSISIDXREG(SISSR, 0x07, v1);
- outSISIDXREG(SISSR, 0x11, 0x0f);
- outSISIDXREG(SISSR, 0x1f, v2);
+ SiS_SetReg(SISSR, 0x07, v1);
+ SiS_SetReg(SISSR, 0x11, 0x0f);
+ SiS_SetReg(SISSR, 0x1f, v2);
/* PCI linear mode, RelIO enabled, A0000 decoding disabled */
- outSISIDXREG(SISSR, 0x20, 0x80 | 0x20 | 0x04);
- outSISIDXREG(SISSR, 0x27, 0x74);
+ SiS_SetReg(SISSR, 0x20, 0x80 | 0x20 | 0x04);
+ SiS_SetReg(SISSR, 0x27, 0x74);
ptr = cs7b;
if(ivideo->haveXGIROM) {
ptr = (const u8 *)&bios[0x7b];
}
for(i = 0; i < 3; i++) {
- outSISIDXREG(SISSR, 0x31 + i, ptr[i]);
+ SiS_SetReg(SISSR, 0x31 + i, ptr[i]);
}
if(ivideo->chip == XGI_40) {
if(ivideo->revision_id == 2) {
- setSISIDXREG(SISSR, 0x3b, 0x3f, 0xc0);
+ SiS_SetRegANDOR(SISSR, 0x3b, 0x3f, 0xc0);
}
- outSISIDXREG(SISCR, 0x7d, 0xfe);
- outSISIDXREG(SISCR, 0x7e, 0x0f);
+ SiS_SetReg(SISCR, 0x7d, 0xfe);
+ SiS_SetReg(SISCR, 0x7e, 0x0f);
}
if(ivideo->revision_id == 0) { /* 40 *and* 20? */
- andSISIDXREG(SISCR, 0x58, 0xd7);
- inSISIDXREG(SISCR, 0xcb, reg);
+ SiS_SetRegAND(SISCR, 0x58, 0xd7);
+ reg = SiS_GetReg(SISCR, 0xcb);
if(reg & 0x20) {
- setSISIDXREG(SISCR, 0x58, 0xd7, (reg & 0x10) ? 0x08 : 0x20); /* =0x28 Z7 ? */
+ SiS_SetRegANDOR(SISCR, 0x58, 0xd7, (reg & 0x10) ? 0x08 : 0x20); /* =0x28 Z7 ? */
}
}
reg = (ivideo->chip == XGI_40) ? 0x20 : 0x00;
- setSISIDXREG(SISCR, 0x38, 0x1f, reg);
+ SiS_SetRegANDOR(SISCR, 0x38, 0x1f, reg);
if(ivideo->chip == XGI_20) {
- outSISIDXREG(SISSR, 0x36, 0x70);
+ SiS_SetReg(SISSR, 0x36, 0x70);
} else {
- outSISIDXREG(SISVID, 0x00, 0x86);
- outSISIDXREG(SISVID, 0x32, 0x00);
- outSISIDXREG(SISVID, 0x30, 0x00);
- outSISIDXREG(SISVID, 0x32, 0x01);
- outSISIDXREG(SISVID, 0x30, 0x00);
- andSISIDXREG(SISVID, 0x2f, 0xdf);
- andSISIDXREG(SISCAP, 0x00, 0x3f);
-
- outSISIDXREG(SISPART1, 0x2f, 0x01);
- outSISIDXREG(SISPART1, 0x00, 0x00);
- outSISIDXREG(SISPART1, 0x02, bios[0x7e]);
- outSISIDXREG(SISPART1, 0x2e, 0x08);
- andSISIDXREG(SISPART1, 0x35, 0x7f);
- andSISIDXREG(SISPART1, 0x50, 0xfe);
-
- inSISIDXREG(SISPART4, 0x00, reg);
+ SiS_SetReg(SISVID, 0x00, 0x86);
+ SiS_SetReg(SISVID, 0x32, 0x00);
+ SiS_SetReg(SISVID, 0x30, 0x00);
+ SiS_SetReg(SISVID, 0x32, 0x01);
+ SiS_SetReg(SISVID, 0x30, 0x00);
+ SiS_SetRegAND(SISVID, 0x2f, 0xdf);
+ SiS_SetRegAND(SISCAP, 0x00, 0x3f);
+
+ SiS_SetReg(SISPART1, 0x2f, 0x01);
+ SiS_SetReg(SISPART1, 0x00, 0x00);
+ SiS_SetReg(SISPART1, 0x02, bios[0x7e]);
+ SiS_SetReg(SISPART1, 0x2e, 0x08);
+ SiS_SetRegAND(SISPART1, 0x35, 0x7f);
+ SiS_SetRegAND(SISPART1, 0x50, 0xfe);
+
+ reg = SiS_GetReg(SISPART4, 0x00);
if(reg == 1 || reg == 2) {
- outSISIDXREG(SISPART2, 0x00, 0x1c);
- outSISIDXREG(SISPART4, 0x0d, bios[0x7f]);
- outSISIDXREG(SISPART4, 0x0e, bios[0x80]);
- outSISIDXREG(SISPART4, 0x10, bios[0x81]);
- andSISIDXREG(SISPART4, 0x0f, 0x3f);
+ SiS_SetReg(SISPART2, 0x00, 0x1c);
+ SiS_SetReg(SISPART4, 0x0d, bios[0x7f]);
+ SiS_SetReg(SISPART4, 0x0e, bios[0x80]);
+ SiS_SetReg(SISPART4, 0x10, bios[0x81]);
+ SiS_SetRegAND(SISPART4, 0x0f, 0x3f);
- inSISIDXREG(SISPART4, 0x01, reg);
+ reg = SiS_GetReg(SISPART4, 0x01);
if((reg & 0xf0) >= 0xb0) {
- inSISIDXREG(SISPART4, 0x23, reg);
+ reg = SiS_GetReg(SISPART4, 0x23);
if(reg & 0x20) reg |= 0x40;
- outSISIDXREG(SISPART4, 0x23, reg);
+ SiS_SetReg(SISPART4, 0x23, reg);
reg = (reg & 0x20) ? 0x02 : 0x00;
- setSISIDXREG(SISPART1, 0x1e, 0xfd, reg);
+ SiS_SetRegANDOR(SISPART1, 0x1e, 0xfd, reg);
}
}
v1 = bios[0x77];
- inSISIDXREG(SISSR, 0x3b, reg);
+ reg = SiS_GetReg(SISSR, 0x3b);
if(reg & 0x02) {
- inSISIDXREG(SISSR, 0x3a, reg);
+ reg = SiS_GetReg(SISSR, 0x3a);
v2 = (reg & 0x30) >> 3;
if(!(v2 & 0x04)) v2 ^= 0x02;
- inSISIDXREG(SISSR, 0x39, reg);
+ reg = SiS_GetReg(SISSR, 0x39);
if(reg & 0x80) v2 |= 0x80;
v2 |= 0x01;
v2 |= 0x08;
}
}
- setSISIDXREG(SISCR, 0x5f, 0xf0, v2);
+ SiS_SetRegANDOR(SISCR, 0x5f, 0xf0, v2);
}
- outSISIDXREG(SISSR, 0x22, v1);
+ SiS_SetReg(SISSR, 0x22, v1);
if(ivideo->revision_id == 2) {
- inSISIDXREG(SISSR, 0x3b, v1);
- inSISIDXREG(SISSR, 0x3a, v2);
+ v1 = SiS_GetReg(SISSR, 0x3b);
+ v2 = SiS_GetReg(SISSR, 0x3a);
regd = bios[0x90 + 3] | (bios[0x90 + 4] << 8);
if( (!(v1 & 0x02)) && (v2 & 0x30) && (regd < 0xcf) )
- setSISIDXREG(SISCR, 0x5f, 0xf1, 0x01);
+ SiS_SetRegANDOR(SISCR, 0x5f, 0xf1, 0x01);
if((mypdev = pci_get_device(0x10de, 0x01e0, NULL))) {
/* TODO: set CR5f &0xf1 | 0x01 for version 6570
* of nforce 2 ROM
*/
if(0)
- setSISIDXREG(SISCR, 0x5f, 0xf1, 0x01);
+ SiS_SetRegANDOR(SISCR, 0x5f, 0xf1, 0x01);
pci_dev_put(mypdev);
}
}
v1 = 0x30;
- inSISIDXREG(SISSR, 0x3b, reg);
- inSISIDXREG(SISCR, 0x5f, v2);
+ reg = SiS_GetReg(SISSR, 0x3b);
+ v2 = SiS_GetReg(SISCR, 0x5f);
if((!(reg & 0x02)) && (v2 & 0x0e))
v1 |= 0x08;
- outSISIDXREG(SISSR, 0x27, v1);
+ SiS_SetReg(SISSR, 0x27, v1);
if(bios[0x64] & 0x01) {
- setSISIDXREG(SISCR, 0x5f, 0xf0, bios[0x64]);
+ SiS_SetRegANDOR(SISCR, 0x5f, 0xf0, bios[0x64]);
}
v1 = bios[0x4f7];
regd = (regd >> 20) & 0x0f;
if(regd == 1) {
v1 &= 0xfc;
- orSISIDXREG(SISCR, 0x5f, 0x08);
- }
- outSISIDXREG(SISCR, 0x48, v1);
-
- setSISIDXREG(SISCR, 0x47, 0x04, bios[0x4f6] & 0xfb);
- setSISIDXREG(SISCR, 0x49, 0xf0, bios[0x4f8] & 0x0f);
- setSISIDXREG(SISCR, 0x4a, 0x60, bios[0x4f9] & 0x9f);
- setSISIDXREG(SISCR, 0x4b, 0x08, bios[0x4fa] & 0xf7);
- setSISIDXREG(SISCR, 0x4c, 0x80, bios[0x4fb] & 0x7f);
- outSISIDXREG(SISCR, 0x70, bios[0x4fc]);
- setSISIDXREG(SISCR, 0x71, 0xf0, bios[0x4fd] & 0x0f);
- outSISIDXREG(SISCR, 0x74, 0xd0);
- setSISIDXREG(SISCR, 0x74, 0xcf, bios[0x4fe] & 0x30);
- setSISIDXREG(SISCR, 0x75, 0xe0, bios[0x4ff] & 0x1f);
- setSISIDXREG(SISCR, 0x76, 0xe0, bios[0x500] & 0x1f);
+ SiS_SetRegOR(SISCR, 0x5f, 0x08);
+ }
+ SiS_SetReg(SISCR, 0x48, v1);
+
+ SiS_SetRegANDOR(SISCR, 0x47, 0x04, bios[0x4f6] & 0xfb);
+ SiS_SetRegANDOR(SISCR, 0x49, 0xf0, bios[0x4f8] & 0x0f);
+ SiS_SetRegANDOR(SISCR, 0x4a, 0x60, bios[0x4f9] & 0x9f);
+ SiS_SetRegANDOR(SISCR, 0x4b, 0x08, bios[0x4fa] & 0xf7);
+ SiS_SetRegANDOR(SISCR, 0x4c, 0x80, bios[0x4fb] & 0x7f);
+ SiS_SetReg(SISCR, 0x70, bios[0x4fc]);
+ SiS_SetRegANDOR(SISCR, 0x71, 0xf0, bios[0x4fd] & 0x0f);
+ SiS_SetReg(SISCR, 0x74, 0xd0);
+ SiS_SetRegANDOR(SISCR, 0x74, 0xcf, bios[0x4fe] & 0x30);
+ SiS_SetRegANDOR(SISCR, 0x75, 0xe0, bios[0x4ff] & 0x1f);
+ SiS_SetRegANDOR(SISCR, 0x76, 0xe0, bios[0x500] & 0x1f);
v1 = bios[0x501];
if((mypdev = pci_get_device(0x8086, 0x2530, NULL))) {
v1 = 0xf0;
pci_dev_put(mypdev);
}
- outSISIDXREG(SISCR, 0x77, v1);
+ SiS_SetReg(SISCR, 0x77, v1);
}
/* RAM type */
if(ivideo->haveXGIROM) {
v1 = bios[0x140 + regb];
}
- outSISIDXREG(SISCR, 0x6d, v1);
+ SiS_SetReg(SISCR, 0x6d, v1);
ptr = cs128;
if(ivideo->haveXGIROM) {
ptr = (const u8 *)&bios[0x128];
}
for(i = 0, j = 0; i < 3; i++, j += 8) {
- outSISIDXREG(SISCR, 0x68 + i, ptr[j + regb]);
+ SiS_SetReg(SISCR, 0x68 + i, ptr[j + regb]);
}
ptr = cs31a;
if(regd & 0x01) reg |= 0x04;
if(regd & 0x02) reg |= 0x08;
regd >>= 2;
- outSISIDXREG(SISCR, rega, reg);
- inSISIDXREG(SISCR, rega, reg);
- inSISIDXREG(SISCR, rega, reg);
+ SiS_SetReg(SISCR, rega, reg);
+ reg = SiS_GetReg(SISCR, rega);
+ reg = SiS_GetReg(SISCR, rega);
reg += 0x10;
}
}
- andSISIDXREG(SISCR, 0x6e, 0xfc);
+ SiS_SetRegAND(SISCR, 0x6e, 0xfc);
ptr = NULL;
if(ivideo->haveXGIROM) {
ptr = (const u8 *)&bios[index];
}
for(i = 0; i < 4; i++) {
- setSISIDXREG(SISCR, 0x6e, 0xfc, i);
+ SiS_SetRegANDOR(SISCR, 0x6e, 0xfc, i);
reg = 0x00;
for(j = 0; j < 2; j++) {
regd = 0;
if(regd & 0x01) reg |= 0x01;
if(regd & 0x02) reg |= 0x02;
regd >>= 2;
- outSISIDXREG(SISCR, 0x6f, reg);
- inSISIDXREG(SISCR, 0x6f, reg);
- inSISIDXREG(SISCR, 0x6f, reg);
+ SiS_SetReg(SISCR, 0x6f, reg);
+ reg = SiS_GetReg(SISCR, 0x6f);
+ reg = SiS_GetReg(SISCR, 0x6f);
reg += 0x08;
}
}
ptr = (const u8 *)&bios[0x148];
}
for(i = 0, j = 0; i < 2; i++, j += 8) {
- outSISIDXREG(SISCR, 0x80 + i, ptr[j + regb]);
+ SiS_SetReg(SISCR, 0x80 + i, ptr[j + regb]);
}
- andSISIDXREG(SISCR, 0x89, 0x8f);
+ SiS_SetRegAND(SISCR, 0x89, 0x8f);
ptr = cs45a;
if(ivideo->haveXGIROM) {
if(regd & 0x01) reg |= 0x01;
if(regd & 0x02) reg |= 0x02;
regd >>= 2;
- outSISIDXREG(SISCR, 0x89, reg);
- inSISIDXREG(SISCR, 0x89, reg);
- inSISIDXREG(SISCR, 0x89, reg);
+ SiS_SetReg(SISCR, 0x89, reg);
+ reg = SiS_GetReg(SISCR, 0x89);
+ reg = SiS_GetReg(SISCR, 0x89);
reg += 0x10;
}
v3 = bios[0x120 + regb];
v4 = bios[0x1ca];
}
- outSISIDXREG(SISCR, 0x45, v1 & 0x0f);
- outSISIDXREG(SISCR, 0x99, (v1 >> 4) & 0x07);
- orSISIDXREG(SISCR, 0x40, v1 & 0x80);
- outSISIDXREG(SISCR, 0x41, v2);
+ SiS_SetReg(SISCR, 0x45, v1 & 0x0f);
+ SiS_SetReg(SISCR, 0x99, (v1 >> 4) & 0x07);
+ SiS_SetRegOR(SISCR, 0x40, v1 & 0x80);
+ SiS_SetReg(SISCR, 0x41, v2);
ptr = cs170;
if(ivideo->haveXGIROM) {
ptr = (const u8 *)&bios[0x170];
}
for(i = 0, j = 0; i < 7; i++, j += 8) {
- outSISIDXREG(SISCR, 0x90 + i, ptr[j + regb]);
+ SiS_SetReg(SISCR, 0x90 + i, ptr[j + regb]);
}
- outSISIDXREG(SISCR, 0x59, v3);
+ SiS_SetReg(SISCR, 0x59, v3);
ptr = cs1a8;
if(ivideo->haveXGIROM) {
ptr = (const u8 *)&bios[0x1a8];
}
for(i = 0, j = 0; i < 3; i++, j += 8) {
- outSISIDXREG(SISCR, 0xc3 + i, ptr[j + regb]);
+ SiS_SetReg(SISCR, 0xc3 + i, ptr[j + regb]);
}
ptr = cs100;
ptr = (const u8 *)&bios[0x100];
}
for(i = 0, j = 0; i < 2; i++, j += 8) {
- outSISIDXREG(SISCR, 0x8a + i, ptr[j + regb]);
+ SiS_SetReg(SISCR, 0x8a + i, ptr[j + regb]);
}
- outSISIDXREG(SISCR, 0xcf, v4);
+ SiS_SetReg(SISCR, 0xcf, v4);
- outSISIDXREG(SISCR, 0x83, 0x09);
- outSISIDXREG(SISCR, 0x87, 0x00);
+ SiS_SetReg(SISCR, 0x83, 0x09);
+ SiS_SetReg(SISCR, 0x87, 0x00);
if(ivideo->chip == XGI_40) {
if( (ivideo->revision_id == 1) ||
(ivideo->revision_id == 2) ) {
- outSISIDXREG(SISCR, 0x8c, 0x87);
+ SiS_SetReg(SISCR, 0x8c, 0x87);
}
}
- outSISIDXREG(SISSR, 0x17, 0x00);
- outSISIDXREG(SISSR, 0x1a, 0x87);
+ SiS_SetReg(SISSR, 0x17, 0x00);
+ SiS_SetReg(SISSR, 0x1a, 0x87);
if(ivideo->chip == XGI_20) {
- outSISIDXREG(SISSR, 0x15, 0x00);
- outSISIDXREG(SISSR, 0x1c, 0x00);
+ SiS_SetReg(SISSR, 0x15, 0x00);
+ SiS_SetReg(SISSR, 0x1c, 0x00);
}
ramtype = 0x00; v1 = 0x10;
}
if(!(ramtype & 0x80)) {
if(ivideo->chip == XGI_20) {
- outSISIDXREG(SISCR, 0x97, v1);
- inSISIDXREG(SISCR, 0x97, reg);
+ SiS_SetReg(SISCR, 0x97, v1);
+ reg = SiS_GetReg(SISCR, 0x97);
if(reg & 0x10) {
ramtype = (reg & 0x01) << 1;
}
} else {
- inSISIDXREG(SISSR, 0x39, reg);
+ reg = SiS_GetReg(SISSR, 0x39);
ramtype = reg & 0x02;
if(!(ramtype)) {
- inSISIDXREG(SISSR, 0x3a, reg);
+ reg = SiS_GetReg(SISSR, 0x3a);
ramtype = (reg >> 1) & 0x01;
}
}
v2 = bios[regb + 0x160];
v3 = bios[regb + 0x168];
}
- outSISIDXREG(SISCR, 0x82, v1);
- outSISIDXREG(SISCR, 0x85, v2);
- outSISIDXREG(SISCR, 0x86, v3);
+ SiS_SetReg(SISCR, 0x82, v1);
+ SiS_SetReg(SISCR, 0x85, v2);
+ SiS_SetReg(SISCR, 0x86, v3);
} else {
- outSISIDXREG(SISCR, 0x82, 0x88);
- outSISIDXREG(SISCR, 0x86, 0x00);
- inSISIDXREG(SISCR, 0x86, reg);
- outSISIDXREG(SISCR, 0x86, 0x88);
- inSISIDXREG(SISCR, 0x86, reg);
- outSISIDXREG(SISCR, 0x86, bios[regb + 0x168]);
- outSISIDXREG(SISCR, 0x82, 0x77);
- outSISIDXREG(SISCR, 0x85, 0x00);
- inSISIDXREG(SISCR, 0x85, reg);
- outSISIDXREG(SISCR, 0x85, 0x88);
- inSISIDXREG(SISCR, 0x85, reg);
- outSISIDXREG(SISCR, 0x85, bios[regb + 0x160]);
- outSISIDXREG(SISCR, 0x82, bios[regb + 0x158]);
+ SiS_SetReg(SISCR, 0x82, 0x88);
+ SiS_SetReg(SISCR, 0x86, 0x00);
+ reg = SiS_GetReg(SISCR, 0x86);
+ SiS_SetReg(SISCR, 0x86, 0x88);
+ reg = SiS_GetReg(SISCR, 0x86);
+ SiS_SetReg(SISCR, 0x86, bios[regb + 0x168]);
+ SiS_SetReg(SISCR, 0x82, 0x77);
+ SiS_SetReg(SISCR, 0x85, 0x00);
+ reg = SiS_GetReg(SISCR, 0x85);
+ SiS_SetReg(SISCR, 0x85, 0x88);
+ reg = SiS_GetReg(SISCR, 0x85);
+ SiS_SetReg(SISCR, 0x85, bios[regb + 0x160]);
+ SiS_SetReg(SISCR, 0x82, bios[regb + 0x158]);
}
if(ivideo->chip == XGI_40) {
- outSISIDXREG(SISCR, 0x97, 0x00);
+ SiS_SetReg(SISCR, 0x97, 0x00);
}
- outSISIDXREG(SISCR, 0x98, 0x01);
- outSISIDXREG(SISCR, 0x9a, 0x02);
+ SiS_SetReg(SISCR, 0x98, 0x01);
+ SiS_SetReg(SISCR, 0x9a, 0x02);
- outSISIDXREG(SISSR, 0x18, 0x01);
+ SiS_SetReg(SISSR, 0x18, 0x01);
if((ivideo->chip == XGI_20) ||
(ivideo->revision_id == 2)) {
- outSISIDXREG(SISSR, 0x19, 0x40);
+ SiS_SetReg(SISSR, 0x19, 0x40);
} else {
- outSISIDXREG(SISSR, 0x19, 0x20);
+ SiS_SetReg(SISSR, 0x19, 0x20);
}
- outSISIDXREG(SISSR, 0x16, 0x00);
- outSISIDXREG(SISSR, 0x16, 0x80);
+ SiS_SetReg(SISSR, 0x16, 0x00);
+ SiS_SetReg(SISSR, 0x16, 0x80);
if((ivideo->chip == XGI_20) || (bios[0x1cb] != 0x0c)) {
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
- outSISIDXREG(SISSR, 0x18, 0x00);
+ SiS_SetReg(SISSR, 0x18, 0x00);
if((ivideo->chip == XGI_20) ||
(ivideo->revision_id == 2)) {
- outSISIDXREG(SISSR, 0x19, 0x40);
+ SiS_SetReg(SISSR, 0x19, 0x40);
} else {
- outSISIDXREG(SISSR, 0x19, 0x20);
+ SiS_SetReg(SISSR, 0x19, 0x20);
}
} else if((ivideo->chip == XGI_40) && (bios[0x1cb] == 0x0c)) {
- /* outSISIDXREG(SISSR, 0x16, 0x0c); */ /* ? */
+ /* SiS_SetReg(SISSR, 0x16, 0x0c); */ /* ? */
}
- outSISIDXREG(SISSR, 0x16, 0x00);
- outSISIDXREG(SISSR, 0x16, 0x80);
+ SiS_SetReg(SISSR, 0x16, 0x00);
+ SiS_SetReg(SISSR, 0x16, 0x80);
sisfb_post_xgi_delay(ivideo, 4);
v1 = 0x31; v2 = 0x03; v3 = 0x83; v4 = 0x03; v5 = 0x83;
if(ivideo->haveXGIROM) {
v4 = bios[index + 2];
v5 = bios[index + 3];
}
- outSISIDXREG(SISSR, 0x18, v1);
- outSISIDXREG(SISSR, 0x19, ((ivideo->chip == XGI_20) ? 0x02 : 0x01));
- outSISIDXREG(SISSR, 0x16, v2);
- outSISIDXREG(SISSR, 0x16, v3);
+ SiS_SetReg(SISSR, 0x18, v1);
+ SiS_SetReg(SISSR, 0x19, ((ivideo->chip == XGI_20) ? 0x02 : 0x01));
+ SiS_SetReg(SISSR, 0x16, v2);
+ SiS_SetReg(SISSR, 0x16, v3);
sisfb_post_xgi_delay(ivideo, 0x43);
- outSISIDXREG(SISSR, 0x1b, 0x03);
+ SiS_SetReg(SISSR, 0x1b, 0x03);
sisfb_post_xgi_delay(ivideo, 0x22);
- outSISIDXREG(SISSR, 0x18, v1);
- outSISIDXREG(SISSR, 0x19, 0x00);
- outSISIDXREG(SISSR, 0x16, v4);
- outSISIDXREG(SISSR, 0x16, v5);
- outSISIDXREG(SISSR, 0x1b, 0x00);
+ SiS_SetReg(SISSR, 0x18, v1);
+ SiS_SetReg(SISSR, 0x19, 0x00);
+ SiS_SetReg(SISSR, 0x16, v4);
+ SiS_SetReg(SISSR, 0x16, v5);
+ SiS_SetReg(SISSR, 0x1b, 0x00);
break;
case 1:
- outSISIDXREG(SISCR, 0x82, 0x77);
- outSISIDXREG(SISCR, 0x86, 0x00);
- inSISIDXREG(SISCR, 0x86, reg);
- outSISIDXREG(SISCR, 0x86, 0x88);
- inSISIDXREG(SISCR, 0x86, reg);
+ SiS_SetReg(SISCR, 0x82, 0x77);
+ SiS_SetReg(SISCR, 0x86, 0x00);
+ reg = SiS_GetReg(SISCR, 0x86);
+ SiS_SetReg(SISCR, 0x86, 0x88);
+ reg = SiS_GetReg(SISCR, 0x86);
v1 = cs168[regb]; v2 = cs160[regb]; v3 = cs158[regb];
if(ivideo->haveXGIROM) {
v1 = bios[regb + 0x168];
v2 = bios[regb + 0x160];
v3 = bios[regb + 0x158];
}
- outSISIDXREG(SISCR, 0x86, v1);
- outSISIDXREG(SISCR, 0x82, 0x77);
- outSISIDXREG(SISCR, 0x85, 0x00);
- inSISIDXREG(SISCR, 0x85, reg);
- outSISIDXREG(SISCR, 0x85, 0x88);
- inSISIDXREG(SISCR, 0x85, reg);
- outSISIDXREG(SISCR, 0x85, v2);
- outSISIDXREG(SISCR, 0x82, v3);
- outSISIDXREG(SISCR, 0x98, 0x01);
- outSISIDXREG(SISCR, 0x9a, 0x02);
-
- outSISIDXREG(SISSR, 0x28, 0x64);
- outSISIDXREG(SISSR, 0x29, 0x63);
+ SiS_SetReg(SISCR, 0x86, v1);
+ SiS_SetReg(SISCR, 0x82, 0x77);
+ SiS_SetReg(SISCR, 0x85, 0x00);
+ reg = SiS_GetReg(SISCR, 0x85);
+ SiS_SetReg(SISCR, 0x85, 0x88);
+ reg = SiS_GetReg(SISCR, 0x85);
+ SiS_SetReg(SISCR, 0x85, v2);
+ SiS_SetReg(SISCR, 0x82, v3);
+ SiS_SetReg(SISCR, 0x98, 0x01);
+ SiS_SetReg(SISCR, 0x9a, 0x02);
+
+ SiS_SetReg(SISSR, 0x28, 0x64);
+ SiS_SetReg(SISSR, 0x29, 0x63);
sisfb_post_xgi_delay(ivideo, 15);
- outSISIDXREG(SISSR, 0x18, 0x00);
- outSISIDXREG(SISSR, 0x19, 0x20);
- outSISIDXREG(SISSR, 0x16, 0x00);
- outSISIDXREG(SISSR, 0x16, 0x80);
- outSISIDXREG(SISSR, 0x18, 0xc5);
- outSISIDXREG(SISSR, 0x19, 0x23);
- outSISIDXREG(SISSR, 0x16, 0x00);
- outSISIDXREG(SISSR, 0x16, 0x80);
+ SiS_SetReg(SISSR, 0x18, 0x00);
+ SiS_SetReg(SISSR, 0x19, 0x20);
+ SiS_SetReg(SISSR, 0x16, 0x00);
+ SiS_SetReg(SISSR, 0x16, 0x80);
+ SiS_SetReg(SISSR, 0x18, 0xc5);
+ SiS_SetReg(SISSR, 0x19, 0x23);
+ SiS_SetReg(SISSR, 0x16, 0x00);
+ SiS_SetReg(SISSR, 0x16, 0x80);
sisfb_post_xgi_delay(ivideo, 1);
- outSISIDXREG(SISCR, 0x97,0x11);
+ SiS_SetReg(SISCR, 0x97, 0x11);
sisfb_post_xgi_setclocks(ivideo, regb);
sisfb_post_xgi_delay(ivideo, 0x46);
- outSISIDXREG(SISSR, 0x18, 0xc5);
- outSISIDXREG(SISSR, 0x19, 0x23);
- outSISIDXREG(SISSR, 0x16, 0x00);
- outSISIDXREG(SISSR, 0x16, 0x80);
+ SiS_SetReg(SISSR, 0x18, 0xc5);
+ SiS_SetReg(SISSR, 0x19, 0x23);
+ SiS_SetReg(SISSR, 0x16, 0x00);
+ SiS_SetReg(SISSR, 0x16, 0x80);
sisfb_post_xgi_delay(ivideo, 1);
- outSISIDXREG(SISSR, 0x1b, 0x04);
+ SiS_SetReg(SISSR, 0x1b, 0x04);
sisfb_post_xgi_delay(ivideo, 1);
- outSISIDXREG(SISSR, 0x1b, 0x00);
+ SiS_SetReg(SISSR, 0x1b, 0x00);
sisfb_post_xgi_delay(ivideo, 1);
v1 = 0x31;
if(ivideo->haveXGIROM) {
v1 = bios[0xf0];
}
- outSISIDXREG(SISSR, 0x18, v1);
- outSISIDXREG(SISSR, 0x19, 0x06);
- outSISIDXREG(SISSR, 0x16, 0x04);
- outSISIDXREG(SISSR, 0x16, 0x84);
+ SiS_SetReg(SISSR, 0x18, v1);
+ SiS_SetReg(SISSR, 0x19, 0x06);
+ SiS_SetReg(SISSR, 0x16, 0x04);
+ SiS_SetReg(SISSR, 0x16, 0x84);
sisfb_post_xgi_delay(ivideo, 1);
break;
default:
if((ivideo->chip == XGI_40) &&
((ivideo->revision_id == 1) ||
(ivideo->revision_id == 2))) {
- outSISIDXREG(SISCR, 0x82, bios[regb + 0x158]);
- outSISIDXREG(SISCR, 0x85, bios[regb + 0x160]);
- outSISIDXREG(SISCR, 0x86, bios[regb + 0x168]);
+ SiS_SetReg(SISCR, 0x82, bios[regb + 0x158]);
+ SiS_SetReg(SISCR, 0x85, bios[regb + 0x160]);
+ SiS_SetReg(SISCR, 0x86, bios[regb + 0x168]);
} else {
- outSISIDXREG(SISCR, 0x82, 0x88);
- outSISIDXREG(SISCR, 0x86, 0x00);
- inSISIDXREG(SISCR, 0x86, reg);
- outSISIDXREG(SISCR, 0x86, 0x88);
- outSISIDXREG(SISCR, 0x82, 0x77);
- outSISIDXREG(SISCR, 0x85, 0x00);
- inSISIDXREG(SISCR, 0x85, reg);
- outSISIDXREG(SISCR, 0x85, 0x88);
- inSISIDXREG(SISCR, 0x85, reg);
+ SiS_SetReg(SISCR, 0x82, 0x88);
+ SiS_SetReg(SISCR, 0x86, 0x00);
+ reg = SiS_GetReg(SISCR, 0x86);
+ SiS_SetReg(SISCR, 0x86, 0x88);
+ SiS_SetReg(SISCR, 0x82, 0x77);
+ SiS_SetReg(SISCR, 0x85, 0x00);
+ reg = SiS_GetReg(SISCR, 0x85);
+ SiS_SetReg(SISCR, 0x85, 0x88);
+ reg = SiS_GetReg(SISCR, 0x85);
v1 = cs160[regb]; v2 = cs158[regb];
if(ivideo->haveXGIROM) {
v1 = bios[regb + 0x160];
v2 = bios[regb + 0x158];
}
- outSISIDXREG(SISCR, 0x85, v1);
- outSISIDXREG(SISCR, 0x82, v2);
+ SiS_SetReg(SISCR, 0x85, v1);
+ SiS_SetReg(SISCR, 0x82, v2);
}
if(ivideo->chip == XGI_40) {
- outSISIDXREG(SISCR, 0x97, 0x11);
+ SiS_SetReg(SISCR, 0x97, 0x11);
}
if((ivideo->chip == XGI_40) && (ivideo->revision_id == 2)) {
- outSISIDXREG(SISCR, 0x98, 0x01);
+ SiS_SetReg(SISCR, 0x98, 0x01);
} else {
- outSISIDXREG(SISCR, 0x98, 0x03);
+ SiS_SetReg(SISCR, 0x98, 0x03);
}
- outSISIDXREG(SISCR, 0x9a, 0x02);
+ SiS_SetReg(SISCR, 0x9a, 0x02);
if(ivideo->chip == XGI_40) {
- outSISIDXREG(SISSR, 0x18, 0x01);
+ SiS_SetReg(SISSR, 0x18, 0x01);
} else {
- outSISIDXREG(SISSR, 0x18, 0x00);
+ SiS_SetReg(SISSR, 0x18, 0x00);
}
- outSISIDXREG(SISSR, 0x19, 0x40);
- outSISIDXREG(SISSR, 0x16, 0x00);
- outSISIDXREG(SISSR, 0x16, 0x80);
+ SiS_SetReg(SISSR, 0x19, 0x40);
+ SiS_SetReg(SISSR, 0x16, 0x00);
+ SiS_SetReg(SISSR, 0x16, 0x80);
if((ivideo->chip == XGI_40) && (bios[0x1cb] != 0x0c)) {
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
- outSISIDXREG(SISSR, 0x18, 0x00);
- outSISIDXREG(SISSR, 0x19, 0x40);
- outSISIDXREG(SISSR, 0x16, 0x00);
- outSISIDXREG(SISSR, 0x16, 0x80);
+ SiS_SetReg(SISSR, 0x18, 0x00);
+ SiS_SetReg(SISSR, 0x19, 0x40);
+ SiS_SetReg(SISSR, 0x16, 0x00);
+ SiS_SetReg(SISSR, 0x16, 0x80);
}
sisfb_post_xgi_delay(ivideo, 4);
v1 = 0x31;
if(ivideo->haveXGIROM) {
v1 = bios[0xf0];
}
- outSISIDXREG(SISSR, 0x18, v1);
- outSISIDXREG(SISSR, 0x19, 0x01);
+ SiS_SetReg(SISSR, 0x18, v1);
+ SiS_SetReg(SISSR, 0x19, 0x01);
if(ivideo->chip == XGI_40) {
- outSISIDXREG(SISSR, 0x16, bios[0x53e]);
- outSISIDXREG(SISSR, 0x16, bios[0x53f]);
+ SiS_SetReg(SISSR, 0x16, bios[0x53e]);
+ SiS_SetReg(SISSR, 0x16, bios[0x53f]);
} else {
- outSISIDXREG(SISSR, 0x16, 0x05);
- outSISIDXREG(SISSR, 0x16, 0x85);
+ SiS_SetReg(SISSR, 0x16, 0x05);
+ SiS_SetReg(SISSR, 0x16, 0x85);
}
sisfb_post_xgi_delay(ivideo, 0x43);
if(ivideo->chip == XGI_40) {
- outSISIDXREG(SISSR, 0x1b, 0x01);
+ SiS_SetReg(SISSR, 0x1b, 0x01);
} else {
- outSISIDXREG(SISSR, 0x1b, 0x03);
+ SiS_SetReg(SISSR, 0x1b, 0x03);
}
sisfb_post_xgi_delay(ivideo, 0x22);
- outSISIDXREG(SISSR, 0x18, v1);
- outSISIDXREG(SISSR, 0x19, 0x00);
+ SiS_SetReg(SISSR, 0x18, v1);
+ SiS_SetReg(SISSR, 0x19, 0x00);
if(ivideo->chip == XGI_40) {
- outSISIDXREG(SISSR, 0x16, bios[0x540]);
- outSISIDXREG(SISSR, 0x16, bios[0x541]);
+ SiS_SetReg(SISSR, 0x16, bios[0x540]);
+ SiS_SetReg(SISSR, 0x16, bios[0x541]);
} else {
- outSISIDXREG(SISSR, 0x16, 0x05);
- outSISIDXREG(SISSR, 0x16, 0x85);
+ SiS_SetReg(SISSR, 0x16, 0x05);
+ SiS_SetReg(SISSR, 0x16, 0x85);
}
- outSISIDXREG(SISSR, 0x1b, 0x00);
+ SiS_SetReg(SISSR, 0x1b, 0x00);
}
regb = 0; /* ! */
if(ivideo->haveXGIROM) {
v1 = bios[0x110 + regb];
}
- outSISIDXREG(SISSR, 0x1b, v1);
+ SiS_SetReg(SISSR, 0x1b, v1);
/* RAM size */
v1 = 0x00; v2 = 0x00;
regd = 1 << regb;
if((v1 & 0x40) && (v2 & regd) && ivideo->haveXGIROM) {
- outSISIDXREG(SISSR, 0x13, bios[regb + 0xe0]);
- outSISIDXREG(SISSR, 0x14, bios[regb + 0xe0 + 8]);
+ SiS_SetReg(SISSR, 0x13, bios[regb + 0xe0]);
+ SiS_SetReg(SISSR, 0x14, bios[regb + 0xe0 + 8]);
} else {
ivideo->SiS_Pr.VideoMemorySize = 8 << 20;
SiSSetMode(&ivideo->SiS_Pr, 0x2e | 0x80);
- outSISIDXREG(SISSR, 0x05, 0x86);
+ SiS_SetReg(SISSR, 0x05, 0x86);
/* Disable read-cache */
- andSISIDXREG(SISSR, 0x21, 0xdf);
+ SiS_SetRegAND(SISSR, 0x21, 0xdf);
sisfb_post_xgi_ramsize(ivideo);
/* Enable read-cache */
- orSISIDXREG(SISSR, 0x21, 0x20);
+ SiS_SetRegOR(SISSR, 0x21, 0x20);
}
#if 0
printk(KERN_DEBUG "-----------------\n");
for(i = 0; i < 0xff; i++) {
- inSISIDXREG(SISCR, i, reg);
+ reg = SiS_GetReg(SISCR, i);
printk(KERN_DEBUG "CR%02x(%x) = 0x%02x\n", i, SISCR, reg);
}
for(i = 0; i < 0x40; i++) {
- inSISIDXREG(SISSR, i, reg);
+ reg = SiS_GetReg(SISSR, i);
printk(KERN_DEBUG "SR%02x(%x) = 0x%02x\n", i, SISSR, reg);
}
printk(KERN_DEBUG "-----------------\n");
/* Sense CRT1 */
if(ivideo->chip == XGI_20) {
- orSISIDXREG(SISCR, 0x32, 0x20);
+ SiS_SetRegOR(SISCR, 0x32, 0x20);
} else {
- inSISIDXREG(SISPART4, 0x00, reg);
+ reg = SiS_GetReg(SISPART4, 0x00);
if((reg == 1) || (reg == 2)) {
sisfb_sense_crt1(ivideo);
} else {
- orSISIDXREG(SISCR, 0x32, 0x20);
+ SiS_SetRegOR(SISCR, 0x32, 0x20);
}
}
ivideo->curFSTN = ivideo->curDSTN = 0;
SiSSetMode(&ivideo->SiS_Pr, 0x2e | 0x80);
- outSISIDXREG(SISSR, 0x05, 0x86);
+ SiS_SetReg(SISSR, 0x05, 0x86);
/* Display off */
- orSISIDXREG(SISSR, 0x01, 0x20);
+ SiS_SetRegOR(SISSR, 0x01, 0x20);
/* Save mode number in CR34 */
- outSISIDXREG(SISCR, 0x34, 0x2e);
+ SiS_SetReg(SISCR, 0x34, 0x2e);
/* Let everyone know what the current mode is */
ivideo->modeprechange = 0x2e;
if(ivideo->chip == XGI_40) {
- inSISIDXREG(SISCR, 0xca, reg);
- inSISIDXREG(SISCR, 0xcc, v1);
+ reg = SiS_GetReg(SISCR, 0xca);
+ v1 = SiS_GetReg(SISCR, 0xcc);
if((reg & 0x10) && (!(v1 & 0x04))) {
printk(KERN_ERR
"sisfb: Please connect power to the card.\n");
}
#endif
- outSISIDXREG(SISSR, 0x05, 0x86);
+ SiS_SetReg(SISSR, 0x05, 0x86);
if( (!ivideo->sisvga_enabled)
#if !defined(__i386__) && !defined(__x86_64__)
#endif
) {
for(i = 0x30; i <= 0x3f; i++) {
- outSISIDXREG(SISCR, i, 0x00);
+ SiS_SetReg(SISCR, i, 0x00);
}
}
/* Find out about current video mode */
ivideo->modeprechange = 0x03;
- inSISIDXREG(SISCR, 0x34, reg);
+ reg = SiS_GetReg(SISCR, 0x34);
if(reg & 0x7f) {
ivideo->modeprechange = reg & 0x7f;
} else if(ivideo->sisvga_enabled) {
if((ivideo->sisfb_mode_idx < 0) ||
((sisbios_mode[ivideo->sisfb_mode_idx].mode_no[ivideo->mni]) != 0xFF)) {
/* Enable PCI_LINEAR_ADDRESSING and MMIO_ENABLE */
- orSISIDXREG(SISSR, IND_SIS_PCI_ADDRESS_SET, (SIS_PCI_ADDR_ENABLE | SIS_MEM_MAP_IO_ENABLE));
+ SiS_SetRegOR(SISSR, IND_SIS_PCI_ADDRESS_SET, (SIS_PCI_ADDR_ENABLE | SIS_MEM_MAP_IO_ENABLE));
/* Enable 2D accelerator engine */
- orSISIDXREG(SISSR, IND_SIS_MODULE_ENABLE, SIS_ENABLE_2D);
+ SiS_SetRegOR(SISSR, IND_SIS_MODULE_ENABLE, SIS_ENABLE_2D);
}
if(sisfb_pdc != 0xff) {
projects / mv-sheeva.git / blobdiff