]> git.karo-electronics.de Git - mv-sheeva.git/commit
drm/radeon/r600: fix tiling issues in CS checker.
authorDave Airlie <airlied@redhat.com>
Thu, 21 Oct 2010 03:55:40 +0000 (13:55 +1000)
committerDave Airlie <airlied@redhat.com>
Tue, 26 Oct 2010 00:26:35 +0000 (10:26 +1000)
commitf30df2fad0c901e74ac9a52a488a54c69a373a41
tree8f7ab96e9cbc373b20833e764a07f78091b41fb6
parente3ce8a0b277438591844847ac7c89a980b4cfa6d
drm/radeon/r600: fix tiling issues in CS checker.

The CS checker had some incorrect alignment requirements for 2D surfaces,
this made rendering to mipmap levels that were 2D broken.

Also the CB height was being worked out from the BO size, this doesn't work
at all when rendering mipmap levels, instead we work out what height userspace
wanted from slice max and use that to check it fits inside the BO, however
the DDX send the wrong slice max for an unaligned buffer so we have to workaround
for that even though its a userspace bug.

Reviewed-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/radeon/r600_cs.c
drivers/gpu/drm/radeon/radeon_drv.c