From 291b7c3a02a7eafbb8ea89a2c0e93676d6972926 Mon Sep 17 00:00:00 2001 From: Nils Faerber Date: Fri, 7 Jan 2011 10:46:21 +0100 Subject: [PATCH] - add Cogent CSB1725 board support (along with RDStor, will be split later) - add definitions for several MV78x00 SOC components --- arch/arm/mach-mv78xx0/Kconfig | 6 + arch/arm/mach-mv78xx0/Makefile | 1 + arch/arm/mach-mv78xx0/addr-map.c | 20 + arch/arm/mach-mv78xx0/common.c | 198 ++++++++++ arch/arm/mach-mv78xx0/common.h | 6 +- .../mach-mv78xx0/include/mach/bridge-regs.h | 2 + arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | 17 + arch/arm/mach-mv78xx0/mpp.c | 20 +- arch/arm/mach-mv78xx0/pcie.c | 2 +- arch/arm/mach-mv78xx0/rdstor-setup.c | 369 ++++++++++++++++++ drivers/i2c/busses/i2c-mv64xxx.c | 2 +- drivers/net/mv643xx_eth.c | 6 +- drivers/watchdog/Kconfig | 2 +- 13 files changed, 641 insertions(+), 10 deletions(-) create mode 100644 arch/arm/mach-mv78xx0/rdstor-setup.c diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig index f2d309d0619..d3e9cb84dd0 100644 --- a/arch/arm/mach-mv78xx0/Kconfig +++ b/arch/arm/mach-mv78xx0/Kconfig @@ -20,6 +20,12 @@ config MACH_TERASTATION_WXL Say 'Y' here if you want your kernel to support the Buffalo WXL Nas. +config MACH_RDSTOR + bool "BDT RDStor based on Cogent CSB1725" + help + Say 'Y' here if you want your kernel to support the + BDT RDStor board. + endmenu endif diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile index 67a13f9bfe6..1b6b68f0a74 100644 --- a/arch/arm/mach-mv78xx0/Makefile +++ b/arch/arm/mach-mv78xx0/Makefile @@ -2,3 +2,4 @@ obj-y += common.o addr-map.o mpp.o irq.o pcie.o obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o obj-$(CONFIG_MACH_TERASTATION_WXL) += buffalo-wxl-setup.o +obj-$(CONFIG_MACH_RDSTOR) += rdstor-setup.o diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c index 311d5b0e9bc..a2d6fb59858 100644 --- a/arch/arm/mach-mv78xx0/addr-map.c +++ b/arch/arm/mach-mv78xx0/addr-map.c @@ -22,6 +22,7 @@ #define TARGET_PCIE0 4 #define TARGET_PCIE1 8 #define TARGET_PCIE(i) ((i) ? TARGET_PCIE1 : TARGET_PCIE0) +#define TARGET_SRAM 9 #define ATTR_DEV_SPI_ROM 0x1f #define ATTR_DEV_BOOT 0x2f #define ATTR_DEV_CS3 0x37 @@ -30,6 +31,7 @@ #define ATTR_DEV_CS0 0x3e #define ATTR_PCIE_IO(l) (0xf0 & ~(0x10 << (l))) #define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l))) +#define ATTR_SRAM 0x01 /* * Helpers to get DDR bank info @@ -139,6 +141,24 @@ void __init mv78xx0_setup_cpu_mbus(void) } } mv78xx0_mbus_dram_info.num_cs = cs; + + /* + * Setup window for SRAM. + */ + setup_cpu_win(11, MV78XX0_SRAM_PHYS_BASE, MV78XX0_SRAM_SIZE, + TARGET_SRAM, ATTR_SRAM, -1); + + /* + * Setup window for NAND controller. + */ + setup_cpu_win(12, MV78XX0_NAND_MEM_PHYS_BASE, MV78XX0_NAND_MEM_SIZE, + TARGET_DEV_BUS, ATTR_DEV_CS2, -1); + + /* + * Setup Window for physmap NOR - boot device + */ + setup_cpu_win(13, MV78XX0_BOOTCS_MEM_PHY_BASE /*0xfc000000*/, SZ_64M, + TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); } void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 08465eb6a2c..5155d5cd3e9 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -21,9 +21,12 @@ #include #include #include +#include #include #include +#include #include +#include #include #include "common.h" @@ -532,6 +535,35 @@ void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) platform_device_register(&mv78xx0_ge11); } +/***************************************************************************** + * SPI + ****************************************************************************/ +static struct orion_spi_info mv78x00_spi_plat_data = { +}; + +static struct resource mv78x00_spi_resources[] = { + { + .start = SPI_PHYS_BASE, + .end = SPI_PHYS_BASE + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device mv78x00_spi = { + .name = "orion_spi", + .id = 0, + .resource = mv78x00_spi_resources, + .dev = { + .platform_data = &mv78x00_spi_plat_data, + }, + .num_resources = ARRAY_SIZE(mv78x00_spi_resources), +}; + +void __init mv78x00_spi_init() +{ + platform_device_register(&mv78x00_spi); +} + /***************************************************************************** * I2C bus 0 ****************************************************************************/ @@ -814,6 +846,171 @@ void __init mv78xx0_uart3_init(void) platform_device_register(&mv78xx0_uart3); } +/***************************************************************************** + * Cryptographic Engines and Security Accelerator (CESA) + ****************************************************************************/ + +static struct resource mv78xx0_crypto_res[] = { + { + .name = "regs", + .start = CRYPTO_PHYS_BASE, + .end = CRYPTO_PHYS_BASE + 0xffff, + .flags = IORESOURCE_MEM, + }, { + .name = "sram", + .start = MV78XX0_SRAM_PHYS_BASE, + .end = MV78XX0_SRAM_PHYS_BASE + MV78XX0_SRAM_SIZE - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "crypto interrupt", + .start = IRQ_MV78XX0_CRYPTO, + .end = IRQ_MV78XX0_CRYPTO, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mv78xx0_crypto_device = { + .name = "mv_crypto", + .id = -1, + .num_resources = ARRAY_SIZE(mv78xx0_crypto_res), + .resource = mv78xx0_crypto_res, +}; + +void __init mv78xx0_crypto_init(void) +{ + platform_device_register(&mv78xx0_crypto_device); +} + +/***************************************************************************** + * XOR + ****************************************************************************/ +static struct mv_xor_platform_shared_data mv78xx0_xor_shared_data = { + .dram = &mv78xx0_mbus_dram_info, +}; + +static u64 mv78xx0_xor_dmamask = DMA_BIT_MASK(32); + + +/***************************************************************************** + * XOR0 + ****************************************************************************/ +static struct resource mv78xx0_xor0_shared_resources[] = { + { + .name = "xor 0 low", + .start = XOR0_PHYS_BASE, + .end = XOR0_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .name = "xor 0 high", + .start = XOR0_HIGH_PHYS_BASE, + .end = XOR0_HIGH_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device mv78xx0_xor0_shared = { + .name = MV_XOR_SHARED_NAME, + .id = 0, + .dev = { + .platform_data = &mv78xx0_xor_shared_data, + }, + .num_resources = ARRAY_SIZE(mv78xx0_xor0_shared_resources), + .resource = mv78xx0_xor0_shared_resources, +}; + +static struct resource mv78xx0_xor00_resources[] = { + [0] = { + .start = IRQ_MV78XX0_XOR_0, + .end = IRQ_MV78XX0_XOR_0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data mv78xx0_xor00_data = { + .shared = &mv78xx0_xor0_shared, + .hw_id = 0, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device mv78xx0_xor00_channel = { + .name = MV_XOR_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(mv78xx0_xor00_resources), + .resource = mv78xx0_xor00_resources, + .dev = { + .dma_mask = &mv78xx0_xor_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = &mv78xx0_xor00_data, + }, +}; + +static struct resource mv78xx0_xor01_resources[] = { + [0] = { + .start = IRQ_MV78XX0_XOR_1, + .end = IRQ_MV78XX0_XOR_1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data mv78xx0_xor01_data = { + .shared = &mv78xx0_xor0_shared, + .hw_id = 1, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device mv78xx0_xor01_channel = { + .name = MV_XOR_NAME, + .id = 1, + .num_resources = ARRAY_SIZE(mv78xx0_xor01_resources), + .resource = mv78xx0_xor01_resources, + .dev = { + .dma_mask = &mv78xx0_xor_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = &mv78xx0_xor01_data, + }, +}; + +void __init mv78xx0_xor0_init(void) +{ + platform_device_register(&mv78xx0_xor0_shared); + + /* + * two engines can't do memset simultaneously, this limitation + * satisfied by removing memset support from one of the engines. + */ + dma_cap_set(DMA_MEMCPY, mv78xx0_xor00_data.cap_mask); + dma_cap_set(DMA_XOR, mv78xx0_xor00_data.cap_mask); + platform_device_register(&mv78xx0_xor00_channel); + + dma_cap_set(DMA_MEMCPY, mv78xx0_xor01_data.cap_mask); + dma_cap_set(DMA_MEMSET, mv78xx0_xor01_data.cap_mask); + dma_cap_set(DMA_XOR, mv78xx0_xor01_data.cap_mask); + platform_device_register(&mv78xx0_xor01_channel); +} + + +/***************************************************************************** + * Watchdog + ****************************************************************************/ +static struct orion_wdt_platform_data mv78xx0_wdt_data = { + .tclk = 0, +}; + +static struct platform_device mv78xx0_wdt_device = { + .name = "orion_wdt", + .id = -1, + .dev = { + .platform_data = &mv78xx0_wdt_data, + }, + .num_resources = 0, +}; + +void __init mv78xx0_wdt_init(void) +{ + mv78xx0_wdt_data.tclk = get_tclk(); + platform_device_register(&mv78xx0_wdt_device); +} + /***************************************************************************** * Time handling @@ -898,4 +1095,5 @@ void __init mv78xx0_init(void) mv78xx0_uart1_data[0].uartclk = tclk; mv78xx0_uart2_data[0].uartclk = tclk; mv78xx0_uart3_data[0].uartclk = tclk; + mv78x00_spi_plat_data.tclk = tclk; } diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h index befc2247546..4605e5e0b8b 100644 --- a/arch/arm/mach-mv78xx0/common.h +++ b/arch/arm/mach-mv78xx0/common.h @@ -44,9 +44,13 @@ void mv78xx0_uart0_init(void); void mv78xx0_uart1_init(void); void mv78xx0_uart2_init(void); void mv78xx0_uart3_init(void); +void mv78x00_spi_init(void); void mv78xx0_i2c_init(void); +void mv78xx0_crypto_init(void); +void mv78xx0_xor0_init(void); +void mv78xx0_wdt_init(void); extern struct sys_timer mv78xx0_timer; - +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) #endif diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h index 2d14c4fe294..19a57629ebc 100644 --- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h +++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h @@ -15,6 +15,7 @@ #define L2_WRITETHROUGH 0x00020000 #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) +#define WDT_RESET_OUT_EN 0x00000002 #define SOFT_RESET_OUT_EN 0x00000004 #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) @@ -25,6 +26,7 @@ #define BRIDGE_INT_TIMER0 0x0002 #define BRIDGE_INT_TIMER1 0x0004 #define BRIDGE_INT_TIMER1_CLR (~0x0004) +#define WDT_INT_REQ 0x0008 #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) #define IRQ_CAUSE_ERR_OFF 0x0000 diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index 788bdace130..8bb402f7f8e 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h @@ -52,9 +52,18 @@ #define MV78XX0_REGS_VIRT_BASE 0xfef00000 #define MV78XX0_REGS_SIZE SZ_1M +#define MV78XX0_SRAM_PHYS_BASE 0xf4000000 +#define MV78XX0_SRAM_SIZE SZ_2K + #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 #define MV78XX0_PCIE_MEM_SIZE 0x30000000 +#define MV78XX0_NAND_MEM_PHYS_BASE 0xfa000000 +#define MV78XX0_NAND_MEM_SIZE SZ_1K + +#define MV78XX0_BOOTCS_MEM_PHY_BASE 0xfc000000 +#define MV78XX0_BOOTCS_MEM_SIZE SZ_64M + /* * Core-specific peripheral registers. */ @@ -71,6 +80,7 @@ #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) #define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) #define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) +#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600) #define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) #define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100) #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) @@ -94,6 +104,11 @@ #define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000) #define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000) +#define XOR0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x60900) +#define XOR0_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x60900) +#define XOR0_HIGH_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x60B00) +#define XOR0_HIGH_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x60B00) + #define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000) #define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000) @@ -102,6 +117,8 @@ #define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000) #define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000) +#define CRYPTO_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x90000) + #define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) /* diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c index 354ac514eb8..2b517224772 100644 --- a/arch/arm/mach-mv78xx0/mpp.c +++ b/arch/arm/mach-mv78xx0/mpp.c @@ -34,6 +34,13 @@ static unsigned int __init mv78xx0_variant(void) #define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4) #define MPP_NR_REGS (1 + MPP_MAX/8) +static unsigned char hgpio[] = { + 0, 1, 2, 3, 4, 5, 6, 7, /* GPIO[0..7] on AD[24..31] */ + 17, 18, 19, 20, 21, 22, 23, /* GPIO[17..23] on AD[9..15] */ + 16, /* GPIO[16] on WEn[1] */ + 8, 9 /* GPIO[8..9] on WEn[2..3] */ +}; + void __init mv78xx0_mpp_conf(unsigned int *mpp_list) { u32 mpp_ctrl[MPP_NR_REGS]; @@ -45,7 +52,7 @@ void __init mv78xx0_mpp_conf(unsigned int *mpp_list) return; /* Initialize gpiolib. */ - orion_gpio_init(); + // orion_gpio_init(); /* already been done in irq.c */ printk(KERN_DEBUG "initial MPP regs:"); for (i = 0; i < MPP_NR_REGS; i++) { @@ -80,9 +87,14 @@ void __init mv78xx0_mpp_conf(unsigned int *mpp_list) gpio_mode |= GPIO_INPUT_OK; if (*mpp_list & MPP_OUTPUT_MASK) gpio_mode |= GPIO_OUTPUT_OK; - if (sel != 0) - gpio_mode = 0; - orion_gpio_set_valid(num, gpio_mode); + if (num > 31 && sel == 0x01) { + /* printk(KERN_ERR "high GPIO %d -> %d\n", num, hgpio[num-32]); */ + orion_gpio_set_valid(hgpio[num-32], gpio_mode); + } else { + if (sel != 0) + gpio_mode = 0; + orion_gpio_set_valid(num, gpio_mode); + } mpp_list++; } diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index a560439dcc3..fbf1362deda 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c @@ -124,7 +124,7 @@ static void __init mv78xx0_pcie_preinit(void) panic("can't allocate PCIe MEM sub-space"); } - win = 0; + win = 0; /* first three are NOR, NAND and SRAM */ for (i = 0; i < num_pcie_ports; i++) { struct pcie_port *pp = pcie_port + i; diff --git a/arch/arm/mach-mv78xx0/rdstor-setup.c b/arch/arm/mach-mv78xx0/rdstor-setup.c new file mode 100644 index 00000000000..79ba032b9b0 --- /dev/null +++ b/arch/arm/mach-mv78xx0/rdstor-setup.c @@ -0,0 +1,369 @@ +/* + * arch/arm/mach-mv78xx0/db78x00-bp-setup.c + * + * Marvell DB-78x00-BP Development Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" +#include "mpp.h" + + +static unsigned int rdstor_mpp_config[] __initdata = { + /* GPIO8 - n.a. */ + /* GPIO9 - n.a. */ + /* GPI10 - n.a. */ + /* GPI11 - n.a. */ + MPP12_GPIO, /* parallel LCD */ + MPP13_GPIO, /* parallel LCD */ + MPP14_GPIO, /* parallel LCD */ + MPP15_GPIO, /* parallel LCD */ + MPP16_UNUSED, /* GPIO16 - n.a. */ + MPP17_UNUSED, /* GPIO17 */ + MPP18_GPIO, /* parallel LCD A0 */ + MPP19_GPIO, /* parallel LCD R/W */ + MPP20_GPIO, /* parallel LCD LCD_EN */ + MPP21_GPIO, /* parallel LCD CSn */ + MPP22_GPIO, /* GPIO22 WAKE0 PCI Express 0 Wake Input (on pin MPP22) */ + MPP23_GPIO, /* GPIO23 WAKE0 PCI Express 0 Wake Input (on pin MPP23) */ + MPP24_UA2_TXD, + MPP25_UA2_RXD, + MPP26_GPIO, /* LCD module RESETn */ + MPP27_GPIO, /* LCD module switch */ + MPP28_GPIO, /* parallel LCD */ + MPP29_GPIO, /* parallel LCD */ + MPP30_GPIO, /* parallel LCD */ + MPP31_GPIO, /* parallel LCD */ + MPP32_GPIO, /* GPIO0 I2C0_INT I2C IRQ */ + MPP33_GPIO, /* GPIO1 T_CRIT LM86 thermal IRQ */ + MPP34_GPIO, /* GPIO2 MII_INT PHY Interrupt for off module MII Bus */ + MPP35_GPIO, /* GPIO3 PHY_INT 88E1121R Dual PHY Interrupt */ + MPP36_GPIO, /* PS1 PF input, GPIO4 INTA MXM Interrupt A */ + MPP37_GPIO, /* PWR SWITCH CSB, GPIO5 INTB MXM Interrupt B */ + MPP38_GPIO, /* GPIO6 INTC MXM Interrupt C */ + MPP39_GPIO, /* GPIO7 INTD MXM Interrupt D */ + MPP47_GPIO, /* GPIO16 N_RDY NAND ready/busy */ + MPP48_SATA1_ACTn, + MPP49_SATA0_ACTn, + 0, +}; + + +/* + * GigE + */ +static struct mv643xx_eth_platform_data db78x00_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(0 /*8*/), +}; + +static struct mv643xx_eth_platform_data db78x00_ge01_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(1 /*9*/), +}; + + +/* + * SATA + */ +static struct mv_sata_platform_data db78x00_sata_data = { + .n_ports = 2, +}; + + +/* + * GPIO + */ +static struct pca953x_platform_data rdstor_gpio_ext_pdata = { + .gpio_base = 128, +}; + + +/* + * I2C + */ +static struct i2c_board_info __initdata rdstor_i2c_bus0[] = { + { + I2C_BOARD_INFO("pca9555", 0x27), + .platform_data = &rdstor_gpio_ext_pdata, + }, +}; + +static struct i2c_board_info __initdata rdstor_i2c_bus1[] = { + { + I2C_BOARD_INFO("lm86", 0x4c) + }, { + I2C_BOARD_INFO("24aa00", 0x50) + }, { + I2C_BOARD_INFO("ds1338", 0x68) + } +}; + + +/* + * NAND flash + */ +static struct mtd_partition rdstor_nand_parts[] = { + { + .name = "nand-kernel", + .offset = 0, + .size = SZ_4M, + // .mask_flags = MTD_WRITEABLE + }, + { + .name = "nand-kernel-fallback", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + // .mask_flags = MTD_WRITEABLE + }, + { + .name = "nand-rootfs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + // .mask_flags = MTD_WRITEABLE + } +}; + +static struct resource mv78xx0_nand_resource = { + .flags = IORESOURCE_MEM, + .start = MV78XX0_NAND_MEM_PHYS_BASE, + .end = MV78XX0_NAND_MEM_PHYS_BASE + + MV78XX0_NAND_MEM_SIZE - 1, +}; + +static struct orion_nand_data mv78xx0_nand_data = { + .cle = 0, + .ale = 1, + .width = 8, +}; + +static struct platform_device mv78xx0_nand_flash = { + .name = "orion_nand", + .id = -1, + .dev = { + .platform_data = &mv78xx0_nand_data, + }, + .resource = &mv78xx0_nand_resource, + .num_resources = 1, +}; + + +static int rdstor_nand_dev_ready(struct mtd_info *mtd) +{ + return gpio_get_value(16); +} + +void __init mv78xx0_nand_init_rb(struct mtd_partition *parts, int nr_parts) +{ + mv78xx0_nand_data.parts = parts; + mv78xx0_nand_data.nr_parts = nr_parts; + mv78xx0_nand_data.dev_ready = rdstor_nand_dev_ready; + + platform_device_register(&mv78xx0_nand_flash); +} + + +void __init mv78xx0_nand_init(struct mtd_partition *parts, int nr_parts, + int chip_delay) +{ + mv78xx0_nand_data.parts = parts; + mv78xx0_nand_data.nr_parts = nr_parts; + mv78xx0_nand_data.chip_delay = chip_delay; + + platform_device_register(&mv78xx0_nand_flash); +} + +/* + * NOR flash + */ +static struct resource rdstor_mtd_resource = { + /* NOR Flash 64MB */ + .start = MV78XX0_BOOTCS_MEM_PHY_BASE /*0xfc000000*/, + .end = MV78XX0_BOOTCS_MEM_PHY_BASE + MV78XX0_BOOTCS_MEM_SIZE /*0xfc000000 + SZ_64M*/ - 1, + .flags = IORESOURCE_MEM, +}; + +static struct mtd_partition rdstor_nor_parts[] = { + { + .name = "nor-user", + .offset = 0, + .size = 0x3f60000, + //.mask_flags = MTD_WRITEABLE + }, + { + .name = "nor-uboot-env", + .offset = MTDPART_OFS_APPEND, + .size = 0x20000, + // .mask_flags = MTD_WRITEABLE + }, + { + .name = "nor-uboot", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = MTD_WRITEABLE + } +}; + +static struct physmap_flash_data rdstor_flash_data[] = { + { + .width = 2, + .parts = rdstor_nor_parts, + .nr_parts = 3, + } +}; + +static struct platform_device rdstor_mtd_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &rdstor_flash_data, + }, + .resource = &rdstor_mtd_resource, + .num_resources = 1, +}; + +/* SPI flash */ +static struct mtd_partition rdstor_dataflash_partitions[] = { + { + .name = "dataflash", + .offset = 0, + .size = MTDPART_SIZ_FULL, + // .mask_flags = MTD_WRITEABLE + } +}; + +static struct flash_platform_data rdstor_spi_slave_data = { + // .type = "m25p64", + .nr_parts = ARRAY_SIZE(rdstor_dataflash_partitions), + .parts = rdstor_dataflash_partitions, +}; + +static struct spi_board_info rdstor_spi_devices[] = { + { /* DataFlash card */ + .modalias = "m25p64", + .irq = NO_IRQ, + .chip_select = 0, + .max_speed_hz = 20000000, + .bus_num = 0, + .platform_data = &rdstor_spi_slave_data, + }, +}; + +static void __init db78x00_init(void) +{ + /* + * Basic MV78xx0 setup. Needs to be called early. + */ + mv78xx0_init(); + + /* setup MMPs */ + mv78xx0_mpp_conf(rdstor_mpp_config); + + /* + * Partition on-chip peripherals between the two CPU cores. + * On the RDstor we also have the single core option so for now + * all peripherals are assigned to core #0. + */ + if (mv78xx0_core_index() == 0) { + mv78xx0_uart0_init(); + mv78xx0_uart1_init(); + mv78xx0_uart2_init(); + //mv78xx0_uart3_init(); + + mv78xx0_i2c_init(); + + mv78xx0_ge00_init(&db78x00_ge00_data); + mv78xx0_ge01_init(&db78x00_ge01_data); + + mv78xx0_sata_init(&db78x00_sata_data); + + /*mv78xx0_ehci0_init();*/ /* somewhere? */ + mv78xx0_ehci1_init(); /* ext USB */ + /* USB2 is device mode */ + + i2c_register_board_info(0, ARRAY_AND_SIZE(rdstor_i2c_bus0)); + i2c_register_board_info(1, ARRAY_AND_SIZE(rdstor_i2c_bus1)); + + /* NOR flash */ + platform_device_register(&rdstor_mtd_device); + + /* NAND flash */ + #if 1 + printk(KERN_ERR "NAND read params: 0x%08x\n", readl(MV78XX0_REGS_VIRT_BASE | 0x10418)); + printk(KERN_ERR "NAND write params: 0x%08x\n", readl(MV78XX0_REGS_VIRT_BASE | 0x1041C)); + printk(KERN_ERR "NAND control: 0x%08x\n", readl(MV78XX0_REGS_VIRT_BASE | 0x10470)); + #endif + writel(0xfff40 /*0x07d940*/, MV78XX0_REGS_VIRT_BASE | 0x10470); + printk(KERN_ERR "NAND control: 0x%08x\n", readl(MV78XX0_REGS_VIRT_BASE | 0x10470)); + + if (/*1 ||*/ gpio_request(16, "NAND READY") != 0 || + gpio_direction_input(16) != 0) { + printk(KERN_ERR "nand_init: failed to request GPIO16 for NAND_READY, falling back to udelay\n"); + mv78xx0_nand_init(ARRAY_AND_SIZE(rdstor_nand_parts), 30); + } else + mv78xx0_nand_init_rb(ARRAY_AND_SIZE(rdstor_nand_parts)); + + spi_register_board_info(rdstor_spi_devices, ARRAY_SIZE(rdstor_spi_devices)); + mv78x00_spi_init(); + + mv78xx0_crypto_init(); + + mv78xx0_xor0_init(); + + mv78xx0_wdt_init(); + } else { + } +} + +static int __init db78x00_pci_init(void) +{ + if (1 /*machine_is_db78x00_bp()*/ /*machine_is_rdstor()*/) { + /* + * Assign the x16 PCIe slot on the board to CPU core + * #0, and let CPU core #1 have the four x1 slots. + */ + if (mv78xx0_core_index() == 0) { + printk(KERN_ERR "pcie_init core#0\n"); + mv78xx0_pcie_init(1, 1); + } else { + mv78xx0_pcie_init(1, 0); + printk(KERN_ERR "pcie_init other core\n"); + } + } else + printk(KERN_ERR "pcie_init machine mismatch\n"); + + return 0; +} +subsys_initcall(db78x00_pci_init); + +MACHINE_START(DB78X00_BP /*RDSTOR*/, "BDT RDStor, with CSB1725 module") + /* Maintainer: Nils Faerber */ + .phys_io = MV78XX0_REGS_PHYS_BASE, + .io_pg_offst = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = db78x00_init, + .map_io = mv78xx0_map_io, + .init_irq = mv78xx0_init_irq, + .timer = &mv78xx0_timer, +MACHINE_END diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c index 16242063144..6a456e72e5c 100644 --- a/drivers/i2c/busses/i2c-mv64xxx.c +++ b/drivers/i2c/busses/i2c-mv64xxx.c @@ -497,7 +497,7 @@ mv64xxx_i2c_probe(struct platform_device *pd) struct mv64xxx_i2c_pdata *pdata = pd->dev.platform_data; int rc; - if ((pd->id != 0) || !pdata) + if (/*(pd->id != 0) ||*/ !pdata) return -ENODEV; drv_data = kzalloc(sizeof(struct mv64xxx_i2c_data), GFP_KERNEL); diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c index 2d488abcf62..44c2fd9838b 100644 --- a/drivers/net/mv643xx_eth.c +++ b/drivers/net/mv643xx_eth.c @@ -2792,11 +2792,13 @@ static struct phy_device *phy_scan(struct mv643xx_eth_private *mp, if (phydev == NULL) { phydev = bus->phy_map[addr]; - if (phydev != NULL) + if (phydev != NULL) { phy_addr_set(mp, addr); + printk(KERN_INFO "mv643xx_eth: found PHY @ %d ID %08x\n", phydev->addr, phydev->phy_id); + } else + printk(KERN_ERR "mv643xx_eth: PHY @ %d not found!\n", addr); } } - return phydev; } diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 24efd8ea41b..9ee0b248f9a 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -253,7 +253,7 @@ config DAVINCI_WATCHDOG config ORION_WATCHDOG tristate "Orion watchdog" - depends on ARCH_ORION5X || ARCH_KIRKWOOD + depends on ARCH_ORION5X || ARCH_KIRKWOOD || ARCH_MV78XX0 help Say Y here if to include support for the watchdog timer in the Marvell Orion5x and Kirkwood ARM SoCs. -- 2.39.2