+#else
+ // Startup LFXT1 32 kHz crystal
+ while (LFXT_Start_Timeout(XT1DRIVE_0, 50000) == UCS_STATUS_ERROR)
+ nop();
+
+ // select the sources for the FLL reference and ACLK
+ SELECT_ACLK(SELA__XT1CLK);
+ SELECT_FLLREF(SELREF__XT1CLK);
+
+ // 512 * 32768 = 16777216 / 1024
+ Init_FLL_Settle(configCPU_CLOCK_HZ/configTICK_RATE_HZ, ACLK_MULTIPLIER);
+
+ // Disable FLL loop control
+// __bis_SR_register(SCG0);
+#endif
+ // setup for quick wake up from interrupt and
+ // minimal power consumption in sleep mode
+ DISABLE_SVSL(); // SVS Low side is turned off
+ DISABLE_SVSL_RESET();
+
+ DISABLE_SVML(); // Monitor low side is turned off
+ DISABLE_SVML_INTERRUPT();
+
+ DISABLE_SVMH(); // Monitor high side is turned off
+ DISABLE_SVMH_INTERRUPT();
+
+ ENABLE_SVSH(); // SVS High side is turned on
+ ENABLE_SVSH_RESET(); // Enable POR on SVS Event
+
+ SVSH_ENABLED_IN_LPM_FULL_PERF(); // SVS high side Full perf mode,
+ // stays on in LPM3,enhanced protect
+ SVSL_ENABLED_IN_LPM_FAST_WAKE();
+
+ // Wait until high side, low side settled
+ while ((PMMIFG & SVSMLDLYIFG) == 0 && (PMMIFG & SVSMHDLYIFG) == 0)
+ nop();
+ CLEAR_PMM_IFGS();
+
+ while (PMM15Check());
+
+ // Errata PMM17
+ if (DetermineErrata()) {
+ *(unsigned int*)(0x0110) = 0x9602;
+ *(unsigned int*)(0x0112) |= 0x0800;
+ }