4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_STRNCPY_FROM_USER
19 select GENERIC_STRNLEN_USER
20 select HARDIRQS_SW_RESEND
22 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
24 select HAVE_ARCH_SECCOMP_FILTER
25 select HAVE_ARCH_TRACEHOOK
27 select HAVE_C_RECORDMCOUNT
28 select HAVE_DEBUG_KMEMLEAK
29 select HAVE_DMA_API_DEBUG
31 select HAVE_DMA_CONTIGUOUS if MMU
32 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
33 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
34 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
35 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
36 select HAVE_GENERIC_DMA_COHERENT
37 select HAVE_GENERIC_HARDIRQS
38 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
39 select HAVE_IDE if PCI || ISA || PCMCIA
40 select HAVE_KERNEL_GZIP
41 select HAVE_KERNEL_LZMA
42 select HAVE_KERNEL_LZO
44 select HAVE_KPROBES if !XIP_KERNEL
45 select HAVE_KRETPROBES if (HAVE_KPROBES)
47 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
48 select HAVE_PERF_EVENTS
49 select HAVE_REGS_AND_STACK_ACCESS_API
50 select HAVE_SYSCALL_TRACEPOINTS
52 select HAVE_VIRT_TO_BUS
54 select PERF_USE_VMALLOC
56 select SYS_SUPPORTS_APM_EMULATION
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select MODULES_USE_ELF_REL
59 select CLONE_BACKWARDS
60 select OLD_SIGSUSPEND3
63 The ARM series is a line of low-power-consumption RISC chip designs
64 licensed by ARM Ltd and targeted at embedded applications and
65 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
66 manufactured, but legacy ARM-based PC hardware remains popular in
67 Europe. There is an ARM Linux project with a web page at
68 <http://www.arm.linux.org.uk/>.
70 config ARM_HAS_SG_CHAIN
73 config NEED_SG_DMA_LENGTH
76 config ARM_DMA_USE_IOMMU
78 select ARM_HAS_SG_CHAIN
79 select NEED_SG_DMA_LENGTH
83 config ARM_DMA_IOMMU_ALIGNMENT
84 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
88 DMA mapping framework by default aligns all buffers to the smallest
89 PAGE_SIZE order which is greater than or equal to the requested buffer
90 size. This works well for buffers up to a few hundreds kilobytes, but
91 for larger buffers it just a waste of address space. Drivers which has
92 relatively small addressing window (like 64Mib) might run out of
93 virtual space with just a few allocations.
95 With this parameter you can specify the maximum PAGE_SIZE order for
96 DMA IOMMU buffers. Larger buffers will be aligned only to this
97 specified order. The order is expressed as a power of two multiplied
105 config MIGHT_HAVE_PCI
108 config SYS_SUPPORTS_APM_EMULATION
116 select GENERIC_ALLOCATOR
127 The Extended Industry Standard Architecture (EISA) bus was
128 developed as an open alternative to the IBM MicroChannel bus.
130 The EISA bus provided some of the features of the IBM MicroChannel
131 bus while maintaining backward compatibility with cards made for
132 the older ISA bus. The EISA bus saw limited use between 1988 and
133 1995 when it was made obsolete by the PCI bus.
135 Say Y here if you are building a kernel for an EISA-based machine.
142 config STACKTRACE_SUPPORT
146 config HAVE_LATENCYTOP_SUPPORT
151 config LOCKDEP_SUPPORT
155 config TRACE_IRQFLAGS_SUPPORT
159 config RWSEM_GENERIC_SPINLOCK
163 config RWSEM_XCHGADD_ALGORITHM
166 config ARCH_HAS_ILOG2_U32
169 config ARCH_HAS_ILOG2_U64
172 config ARCH_HAS_CPUFREQ
175 Internal node to signify that the ARCH has CPUFREQ support
176 and that the relevant menu configurations are displayed for
179 config GENERIC_HWEIGHT
183 config GENERIC_CALIBRATE_DELAY
187 config ARCH_MAY_HAVE_PC_FDC
193 config NEED_DMA_MAP_STATE
196 config ARCH_HAS_DMA_SET_COHERENT_MASK
199 config GENERIC_ISA_DMA
205 config NEED_RET_TO_USER
213 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
214 default DRAM_BASE if REMAP_VECTORS_TO_RAM
217 The base address of exception vectors.
219 config ARM_PATCH_PHYS_VIRT
220 bool "Patch physical to virtual translations at runtime" if EMBEDDED
222 depends on !XIP_KERNEL && MMU
223 depends on !ARCH_REALVIEW || !SPARSEMEM
225 Patch phys-to-virt and virt-to-phys translation functions at
226 boot and module load time according to the position of the
227 kernel in system memory.
229 This can only be used with non-XIP MMU kernels where the base
230 of physical memory is at a 16MB boundary.
232 Only disable this option if you know that you do not require
233 this feature (eg, building a kernel for a single machine) and
234 you need to shrink the kernel to the minimal size.
236 config NEED_MACH_GPIO_H
239 Select this when mach/gpio.h is required to provide special
240 definitions for this platform. The need for mach/gpio.h should
241 be avoided when possible.
243 config NEED_MACH_IO_H
246 Select this when mach/io.h is required to provide special
247 definitions for this platform. The need for mach/io.h should
248 be avoided when possible.
250 config NEED_MACH_MEMORY_H
253 Select this when mach/memory.h is required to provide special
254 definitions for this platform. The need for mach/memory.h should
255 be avoided when possible.
258 hex "Physical address of main memory" if MMU
259 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
260 default DRAM_BASE if !MMU
262 Please provide the physical address corresponding to the
263 location of main memory in your system.
269 source "init/Kconfig"
271 source "kernel/Kconfig.freezer"
276 bool "MMU-based Paged Memory Management Support"
279 Select if you want MMU-based virtualised addressing space
280 support by paged memory management. If unsure, say 'Y'.
283 # The "ARM system type" choice list is ordered alphabetically by option
284 # text. Please add new entries in the option alphabetic order.
287 prompt "ARM system type"
288 default ARCH_VERSATILE if !MMU
289 default ARCH_MULTIPLATFORM if MMU
291 config ARCH_MULTIPLATFORM
292 bool "Allow multiple platforms to be selected"
294 select ARM_PATCH_PHYS_VIRT
297 select MULTI_IRQ_HANDLER
301 config ARCH_INTEGRATOR
302 bool "ARM Ltd. Integrator family"
303 select ARCH_HAS_CPUFREQ
306 select COMMON_CLK_VERSATILE
307 select GENERIC_CLOCKEVENTS
310 select MULTI_IRQ_HANDLER
311 select NEED_MACH_MEMORY_H
312 select PLAT_VERSATILE
314 select VERSATILE_FPGA_IRQ
316 Support for ARM's Integrator platform.
319 bool "ARM Ltd. RealView family"
320 select ARCH_WANT_OPTIONAL_GPIOLIB
322 select ARM_TIMER_SP804
324 select COMMON_CLK_VERSATILE
325 select GENERIC_CLOCKEVENTS
326 select GPIO_PL061 if GPIOLIB
328 select NEED_MACH_MEMORY_H
329 select PLAT_VERSATILE
330 select PLAT_VERSATILE_CLCD
332 This enables support for ARM Ltd RealView boards.
334 config ARCH_VERSATILE
335 bool "ARM Ltd. Versatile family"
336 select ARCH_WANT_OPTIONAL_GPIOLIB
338 select ARM_TIMER_SP804
341 select GENERIC_CLOCKEVENTS
342 select HAVE_MACH_CLKDEV
344 select PLAT_VERSATILE
345 select PLAT_VERSATILE_CLCD
346 select PLAT_VERSATILE_CLOCK
347 select VERSATILE_FPGA_IRQ
349 This enables support for ARM Ltd Versatile board.
353 select ARCH_REQUIRE_GPIOLIB
357 select NEED_MACH_GPIO_H
358 select NEED_MACH_IO_H if PCCARD
360 select PINCTRL_AT91 if USE_OF
362 This enables support for systems based on Atmel
363 AT91RM9200 and AT91SAM9* processors.
366 bool "Broadcom BCM2835 family"
367 select ARCH_REQUIRE_GPIOLIB
369 select ARM_ERRATA_411920
370 select ARM_TIMER_SP804
375 select GENERIC_CLOCKEVENTS
376 select MULTI_IRQ_HANDLER
378 select PINCTRL_BCM2835
382 This enables support for the Broadcom BCM2835 SoC. This SoC is
383 use in the Raspberry Pi, and Roku 2 devices.
386 bool "Cavium Networks CNS3XXX family"
389 select GENERIC_CLOCKEVENTS
390 select MIGHT_HAVE_CACHE_L2X0
391 select MIGHT_HAVE_PCI
392 select PCI_DOMAINS if PCI
394 Support for Cavium Networks CNS3XXX platform.
397 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
398 select ARCH_REQUIRE_GPIOLIB
403 select GENERIC_CLOCKEVENTS
404 select MULTI_IRQ_HANDLER
405 select NEED_MACH_MEMORY_H
408 Support for Cirrus Logic 711x/721x/731x based boards.
411 bool "Cortina Systems Gemini"
412 select ARCH_REQUIRE_GPIOLIB
413 select ARCH_USES_GETTIMEOFFSET
414 select NEED_MACH_GPIO_H
417 Support for the Cortina Systems Gemini family SoCs
421 select ARCH_REQUIRE_GPIOLIB
424 select GENERIC_CLOCKEVENTS
425 select GENERIC_IRQ_CHIP
426 select MIGHT_HAVE_CACHE_L2X0
432 Support for CSR SiRFprimaII/Marco/Polo platforms
436 select ARCH_USES_GETTIMEOFFSET
439 select NEED_MACH_IO_H
440 select NEED_MACH_MEMORY_H
443 This is an evaluation board for the StrongARM processor available
444 from Digital. It has limited hardware on-board, including an
445 Ethernet interface, two PCMCIA sockets, two serial ports and a
450 select ARCH_HAS_HOLES_MEMORYMODEL
451 select ARCH_REQUIRE_GPIOLIB
452 select ARCH_USES_GETTIMEOFFSET
457 select NEED_MACH_MEMORY_H
459 This enables support for the Cirrus EP93xx series of CPUs.
461 config ARCH_FOOTBRIDGE
465 select GENERIC_CLOCKEVENTS
467 select NEED_MACH_IO_H if !MMU
468 select NEED_MACH_MEMORY_H
470 Support for systems based on the DC21285 companion chip
471 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
474 bool "Freescale MXS-based"
475 select ARCH_REQUIRE_GPIOLIB
479 select GENERIC_CLOCKEVENTS
480 select HAVE_CLK_PREPARE
481 select MULTI_IRQ_HANDLER
486 Support for Freescale MXS-based family of processors
489 bool "Hilscher NetX based"
493 select GENERIC_CLOCKEVENTS
495 This enables support for systems based on the Hilscher NetX Soc
500 select ARCH_SUPPORTS_MSI
502 select NEED_MACH_MEMORY_H
503 select NEED_RET_TO_USER
508 Support for Intel's IOP13XX (XScale) family of processors.
513 select ARCH_REQUIRE_GPIOLIB
515 select NEED_MACH_GPIO_H
516 select NEED_RET_TO_USER
520 Support for Intel's 80219 and IOP32X (XScale) family of
526 select ARCH_REQUIRE_GPIOLIB
528 select NEED_MACH_GPIO_H
529 select NEED_RET_TO_USER
533 Support for Intel's IOP33X (XScale) family of processors.
538 select ARCH_HAS_DMA_SET_COHERENT_MASK
539 select ARCH_REQUIRE_GPIOLIB
542 select DMABOUNCE if PCI
543 select GENERIC_CLOCKEVENTS
544 select MIGHT_HAVE_PCI
545 select NEED_MACH_IO_H
547 Support for Intel's IXP4XX (XScale) family of processors.
551 select ARCH_REQUIRE_GPIOLIB
552 select COMMON_CLK_DOVE
554 select GENERIC_CLOCKEVENTS
555 select MIGHT_HAVE_PCI
558 select PLAT_ORION_LEGACY
559 select USB_ARCH_HAS_EHCI
561 Support for the Marvell Dove SoC 88AP510
564 bool "Marvell Kirkwood"
565 select ARCH_REQUIRE_GPIOLIB
567 select GENERIC_CLOCKEVENTS
571 select PINCTRL_KIRKWOOD
572 select PLAT_ORION_LEGACY
574 Support for the following Marvell Kirkwood series SoCs:
575 88F6180, 88F6192 and 88F6281.
578 bool "Marvell MV78xx0"
579 select ARCH_REQUIRE_GPIOLIB
581 select GENERIC_CLOCKEVENTS
583 select PLAT_ORION_LEGACY
585 Support for the following Marvell MV78xx0 series SoCs:
591 select ARCH_REQUIRE_GPIOLIB
593 select GENERIC_CLOCKEVENTS
595 select PLAT_ORION_LEGACY
597 Support for the following Marvell Orion 5x series SoCs:
598 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
599 Orion-2 (5281), Orion-1-90 (6183).
602 bool "Marvell PXA168/910/MMP2"
604 select ARCH_REQUIRE_GPIOLIB
606 select GENERIC_ALLOCATOR
607 select GENERIC_CLOCKEVENTS
610 select NEED_MACH_GPIO_H
615 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
618 bool "Micrel/Kendin KS8695"
619 select ARCH_REQUIRE_GPIOLIB
622 select GENERIC_CLOCKEVENTS
623 select NEED_MACH_MEMORY_H
625 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
626 System-on-Chip devices.
629 bool "Nuvoton W90X900 CPU"
630 select ARCH_REQUIRE_GPIOLIB
634 select GENERIC_CLOCKEVENTS
636 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
637 At present, the w90x900 has been renamed nuc900, regarding
638 the ARM series product line, you can login the following
639 link address to know more.
641 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
642 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
646 select ARCH_REQUIRE_GPIOLIB
651 select GENERIC_CLOCKEVENTS
654 select USB_ARCH_HAS_OHCI
657 Support for the NXP LPC32XX family of processors
661 select ARCH_HAS_CPUFREQ
662 select ARCH_REQUIRE_GPIOLIB
667 select GENERIC_CLOCKEVENTS
670 select MIGHT_HAVE_CACHE_L2X0
674 This enables support for NVIDIA Tegra based systems (Tegra APX,
675 Tegra 6xx and Tegra 2 series).
678 bool "PXA2xx/PXA3xx-based"
680 select ARCH_HAS_CPUFREQ
682 select ARCH_REQUIRE_GPIOLIB
683 select ARM_CPU_SUSPEND if PM
687 select GENERIC_CLOCKEVENTS
690 select MULTI_IRQ_HANDLER
691 select NEED_MACH_GPIO_H
695 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
699 select ARCH_REQUIRE_GPIOLIB
701 select GENERIC_CLOCKEVENTS
704 Support for Qualcomm MSM/QSD based systems. This runs on the
705 apps processor of the MSM/QSD and depends on a shared memory
706 interface to the modem processor which runs the baseband
707 stack and controls some vital subsystems
708 (clock and power control, etc).
711 bool "Renesas SH-Mobile / R-Mobile"
713 select GENERIC_CLOCKEVENTS
715 select HAVE_MACH_CLKDEV
717 select MIGHT_HAVE_CACHE_L2X0
718 select MULTI_IRQ_HANDLER
719 select NEED_MACH_MEMORY_H
722 select PM_GENERIC_DOMAINS if PM
725 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
730 select ARCH_MAY_HAVE_PC_FDC
731 select ARCH_SPARSEMEM_ENABLE
732 select ARCH_USES_GETTIMEOFFSET
735 select HAVE_PATA_PLATFORM
737 select NEED_MACH_IO_H
738 select NEED_MACH_MEMORY_H
741 On the Acorn Risc-PC, Linux can support the internal IDE disk and
742 CD-ROM interface, serial and parallel port, and the floppy drive.
746 select ARCH_HAS_CPUFREQ
748 select ARCH_REQUIRE_GPIOLIB
749 select ARCH_SPARSEMEM_ENABLE
754 select GENERIC_CLOCKEVENTS
757 select NEED_MACH_GPIO_H
758 select NEED_MACH_MEMORY_H
761 Support for StrongARM 11x0 based boards.
764 bool "Samsung S3C24XX SoCs"
765 select ARCH_HAS_CPUFREQ
766 select ARCH_USES_GETTIMEOFFSET
769 select HAVE_S3C2410_I2C if I2C
770 select HAVE_S3C2410_WATCHDOG if WATCHDOG
771 select HAVE_S3C_RTC if RTC_CLASS
772 select NEED_MACH_GPIO_H
773 select NEED_MACH_IO_H
775 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
776 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
777 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
778 Samsung SMDK2410 development board (and derivatives).
781 bool "Samsung S3C64XX"
782 select ARCH_HAS_CPUFREQ
783 select ARCH_REQUIRE_GPIOLIB
784 select ARCH_USES_GETTIMEOFFSET
789 select HAVE_S3C2410_I2C if I2C
790 select HAVE_S3C2410_WATCHDOG if WATCHDOG
792 select NEED_MACH_GPIO_H
796 select S3C_GPIO_TRACK
797 select SAMSUNG_CLKSRC
798 select SAMSUNG_GPIOLIB_4BIT
799 select SAMSUNG_IRQ_VIC_TIMER
800 select USB_ARCH_HAS_OHCI
802 Samsung S3C64XX series based systems
805 bool "Samsung S5P6440 S5P6450"
809 select GENERIC_CLOCKEVENTS
811 select HAVE_S3C2410_I2C if I2C
812 select HAVE_S3C2410_WATCHDOG if WATCHDOG
813 select HAVE_S3C_RTC if RTC_CLASS
814 select NEED_MACH_GPIO_H
816 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
820 bool "Samsung S5PC100"
821 select ARCH_USES_GETTIMEOFFSET
825 select HAVE_S3C2410_I2C if I2C
826 select HAVE_S3C2410_WATCHDOG if WATCHDOG
827 select HAVE_S3C_RTC if RTC_CLASS
828 select NEED_MACH_GPIO_H
830 Samsung S5PC100 series based systems
833 bool "Samsung S5PV210/S5PC110"
834 select ARCH_HAS_CPUFREQ
835 select ARCH_HAS_HOLES_MEMORYMODEL
836 select ARCH_SPARSEMEM_ENABLE
840 select GENERIC_CLOCKEVENTS
842 select HAVE_S3C2410_I2C if I2C
843 select HAVE_S3C2410_WATCHDOG if WATCHDOG
844 select HAVE_S3C_RTC if RTC_CLASS
845 select NEED_MACH_GPIO_H
846 select NEED_MACH_MEMORY_H
848 Samsung S5PV210/S5PC110 series based systems
851 bool "Samsung EXYNOS"
852 select ARCH_HAS_CPUFREQ
853 select ARCH_HAS_HOLES_MEMORYMODEL
854 select ARCH_SPARSEMEM_ENABLE
857 select GENERIC_CLOCKEVENTS
859 select HAVE_S3C2410_I2C if I2C
860 select HAVE_S3C2410_WATCHDOG if WATCHDOG
861 select HAVE_S3C_RTC if RTC_CLASS
862 select NEED_MACH_GPIO_H
863 select NEED_MACH_MEMORY_H
865 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
869 select ARCH_USES_GETTIMEOFFSET
873 select NEED_MACH_MEMORY_H
877 Support for the StrongARM based Digital DNARD machine, also known
878 as "Shark" (<http://www.shark-linux.de/shark.html>).
881 bool "ST-Ericsson U300 Series"
883 select ARCH_REQUIRE_GPIOLIB
885 select ARM_PATCH_PHYS_VIRT
891 select GENERIC_CLOCKEVENTS
895 Support for ST-Ericsson U300 series mobile platforms.
898 bool "ST-Ericsson U8500 Series"
900 select ARCH_HAS_CPUFREQ
901 select ARCH_REQUIRE_GPIOLIB
905 select GENERIC_CLOCKEVENTS
907 select MIGHT_HAVE_CACHE_L2X0
910 Support for ST-Ericsson's Ux500 architecture
913 bool "STMicroelectronics Nomadik"
914 select ARCH_REQUIRE_GPIOLIB
917 select CLKSRC_NOMADIK_MTU
920 select GENERIC_CLOCKEVENTS
921 select MIGHT_HAVE_CACHE_L2X0
924 select PINCTRL_STN8815
927 Support for the Nomadik platform by ST-Ericsson
931 select ARCH_HAS_CPUFREQ
932 select ARCH_REQUIRE_GPIOLIB
937 select GENERIC_CLOCKEVENTS
940 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
944 select ARCH_HAS_HOLES_MEMORYMODEL
945 select ARCH_REQUIRE_GPIOLIB
947 select GENERIC_ALLOCATOR
948 select GENERIC_CLOCKEVENTS
949 select GENERIC_IRQ_CHIP
951 select NEED_MACH_GPIO_H
955 Support for TI's DaVinci platform.
960 select ARCH_HAS_CPUFREQ
961 select ARCH_HAS_HOLES_MEMORYMODEL
963 select ARCH_REQUIRE_GPIOLIB
966 select GENERIC_CLOCKEVENTS
967 select GENERIC_IRQ_CHIP
971 select NEED_MACH_IO_H if PCCARD
972 select NEED_MACH_MEMORY_H
974 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
978 menu "Multiple platform selection"
979 depends on ARCH_MULTIPLATFORM
981 comment "CPU Core family selection"
984 bool "ARMv4 based platforms (FA526, StrongARM)"
985 depends on !ARCH_MULTI_V6_V7
986 select ARCH_MULTI_V4_V5
988 config ARCH_MULTI_V4T
989 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
990 depends on !ARCH_MULTI_V6_V7
991 select ARCH_MULTI_V4_V5
994 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
995 depends on !ARCH_MULTI_V6_V7
996 select ARCH_MULTI_V4_V5
998 config ARCH_MULTI_V4_V5
1001 config ARCH_MULTI_V6
1002 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
1003 select ARCH_MULTI_V6_V7
1006 config ARCH_MULTI_V7
1007 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1009 select ARCH_MULTI_V6_V7
1010 select ARCH_VEXPRESS
1013 config ARCH_MULTI_V6_V7
1016 config ARCH_MULTI_CPU_AUTO
1017 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1018 select ARCH_MULTI_V5
1023 # This is sorted alphabetically by mach-* pathname. However, plat-*
1024 # Kconfigs may be included either alphabetically (according to the
1025 # plat- suffix) or along side the corresponding mach-* source.
1027 source "arch/arm/mach-mvebu/Kconfig"
1029 source "arch/arm/mach-at91/Kconfig"
1031 source "arch/arm/mach-bcm/Kconfig"
1033 source "arch/arm/mach-clps711x/Kconfig"
1035 source "arch/arm/mach-cns3xxx/Kconfig"
1037 source "arch/arm/mach-davinci/Kconfig"
1039 source "arch/arm/mach-dove/Kconfig"
1041 source "arch/arm/mach-ep93xx/Kconfig"
1043 source "arch/arm/mach-footbridge/Kconfig"
1045 source "arch/arm/mach-gemini/Kconfig"
1047 source "arch/arm/mach-highbank/Kconfig"
1049 source "arch/arm/mach-integrator/Kconfig"
1051 source "arch/arm/mach-iop32x/Kconfig"
1053 source "arch/arm/mach-iop33x/Kconfig"
1055 source "arch/arm/mach-iop13xx/Kconfig"
1057 source "arch/arm/mach-ixp4xx/Kconfig"
1059 source "arch/arm/mach-kirkwood/Kconfig"
1061 source "arch/arm/mach-ks8695/Kconfig"
1063 source "arch/arm/mach-msm/Kconfig"
1065 source "arch/arm/mach-mv78xx0/Kconfig"
1067 source "arch/arm/mach-imx/Kconfig"
1069 source "arch/arm/mach-mxs/Kconfig"
1071 source "arch/arm/mach-netx/Kconfig"
1073 source "arch/arm/mach-nomadik/Kconfig"
1075 source "arch/arm/plat-omap/Kconfig"
1077 source "arch/arm/mach-omap1/Kconfig"
1079 source "arch/arm/mach-omap2/Kconfig"
1081 source "arch/arm/mach-orion5x/Kconfig"
1083 source "arch/arm/mach-picoxcell/Kconfig"
1085 source "arch/arm/mach-pxa/Kconfig"
1086 source "arch/arm/plat-pxa/Kconfig"
1088 source "arch/arm/mach-mmp/Kconfig"
1090 source "arch/arm/mach-realview/Kconfig"
1092 source "arch/arm/mach-sa1100/Kconfig"
1094 source "arch/arm/plat-samsung/Kconfig"
1096 source "arch/arm/mach-socfpga/Kconfig"
1098 source "arch/arm/plat-spear/Kconfig"
1100 source "arch/arm/mach-s3c24xx/Kconfig"
1103 source "arch/arm/mach-s3c64xx/Kconfig"
1106 source "arch/arm/mach-s5p64x0/Kconfig"
1108 source "arch/arm/mach-s5pc100/Kconfig"
1110 source "arch/arm/mach-s5pv210/Kconfig"
1112 source "arch/arm/mach-exynos/Kconfig"
1114 source "arch/arm/mach-shmobile/Kconfig"
1116 source "arch/arm/mach-sunxi/Kconfig"
1118 source "arch/arm/mach-prima2/Kconfig"
1120 source "arch/arm/mach-tegra/Kconfig"
1122 source "arch/arm/mach-u300/Kconfig"
1124 source "arch/arm/mach-ux500/Kconfig"
1126 source "arch/arm/mach-versatile/Kconfig"
1128 source "arch/arm/mach-vexpress/Kconfig"
1129 source "arch/arm/plat-versatile/Kconfig"
1131 source "arch/arm/mach-virt/Kconfig"
1133 source "arch/arm/mach-vt8500/Kconfig"
1135 source "arch/arm/mach-w90x900/Kconfig"
1137 source "arch/arm/mach-zynq/Kconfig"
1139 # Definitions to make life easier
1145 select GENERIC_CLOCKEVENTS
1151 select GENERIC_IRQ_CHIP
1154 config PLAT_ORION_LEGACY
1161 config PLAT_VERSATILE
1164 config ARM_TIMER_SP804
1167 select HAVE_SCHED_CLOCK
1169 source arch/arm/mm/Kconfig
1173 default 16 if ARCH_EP93XX
1177 bool "Enable iWMMXt support"
1178 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1179 default y if PXA27x || PXA3xx || ARCH_MMP
1181 Enable support for iWMMXt context switching at run time if
1182 running on a CPU that supports it.
1186 depends on CPU_XSCALE
1189 config MULTI_IRQ_HANDLER
1192 Allow each machine to specify it's own IRQ handler at run time.
1195 source "arch/arm/Kconfig-nommu"
1198 config ARM_ERRATA_326103
1199 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1202 Executing a SWP instruction to read-only memory does not set bit 11
1203 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1204 treat the access as a read, preventing a COW from occurring and
1205 causing the faulting task to livelock.
1207 config ARM_ERRATA_411920
1208 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1209 depends on CPU_V6 || CPU_V6K
1211 Invalidation of the Instruction Cache operation can
1212 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1213 It does not affect the MPCore. This option enables the ARM Ltd.
1214 recommended workaround.
1216 config ARM_ERRATA_430973
1217 bool "ARM errata: Stale prediction on replaced interworking branch"
1220 This option enables the workaround for the 430973 Cortex-A8
1221 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1222 interworking branch is replaced with another code sequence at the
1223 same virtual address, whether due to self-modifying code or virtual
1224 to physical address re-mapping, Cortex-A8 does not recover from the
1225 stale interworking branch prediction. This results in Cortex-A8
1226 executing the new code sequence in the incorrect ARM or Thumb state.
1227 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1228 and also flushes the branch target cache at every context switch.
1229 Note that setting specific bits in the ACTLR register may not be
1230 available in non-secure mode.
1232 config ARM_ERRATA_458693
1233 bool "ARM errata: Processor deadlock when a false hazard is created"
1235 depends on !ARCH_MULTIPLATFORM
1237 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1238 erratum. For very specific sequences of memory operations, it is
1239 possible for a hazard condition intended for a cache line to instead
1240 be incorrectly associated with a different cache line. This false
1241 hazard might then cause a processor deadlock. The workaround enables
1242 the L1 caching of the NEON accesses and disables the PLD instruction
1243 in the ACTLR register. Note that setting specific bits in the ACTLR
1244 register may not be available in non-secure mode.
1246 config ARM_ERRATA_460075
1247 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1249 depends on !ARCH_MULTIPLATFORM
1251 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1252 erratum. Any asynchronous access to the L2 cache may encounter a
1253 situation in which recent store transactions to the L2 cache are lost
1254 and overwritten with stale memory contents from external memory. The
1255 workaround disables the write-allocate mode for the L2 cache via the
1256 ACTLR register. Note that setting specific bits in the ACTLR register
1257 may not be available in non-secure mode.
1259 config ARM_ERRATA_742230
1260 bool "ARM errata: DMB operation may be faulty"
1261 depends on CPU_V7 && SMP
1262 depends on !ARCH_MULTIPLATFORM
1264 This option enables the workaround for the 742230 Cortex-A9
1265 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1266 between two write operations may not ensure the correct visibility
1267 ordering of the two writes. This workaround sets a specific bit in
1268 the diagnostic register of the Cortex-A9 which causes the DMB
1269 instruction to behave as a DSB, ensuring the correct behaviour of
1272 config ARM_ERRATA_742231
1273 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1274 depends on CPU_V7 && SMP
1275 depends on !ARCH_MULTIPLATFORM
1277 This option enables the workaround for the 742231 Cortex-A9
1278 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1279 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1280 accessing some data located in the same cache line, may get corrupted
1281 data due to bad handling of the address hazard when the line gets
1282 replaced from one of the CPUs at the same time as another CPU is
1283 accessing it. This workaround sets specific bits in the diagnostic
1284 register of the Cortex-A9 which reduces the linefill issuing
1285 capabilities of the processor.
1287 config PL310_ERRATA_588369
1288 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1289 depends on CACHE_L2X0
1291 The PL310 L2 cache controller implements three types of Clean &
1292 Invalidate maintenance operations: by Physical Address
1293 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1294 They are architecturally defined to behave as the execution of a
1295 clean operation followed immediately by an invalidate operation,
1296 both performing to the same memory location. This functionality
1297 is not correctly implemented in PL310 as clean lines are not
1298 invalidated as a result of these operations.
1300 config ARM_ERRATA_720789
1301 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1304 This option enables the workaround for the 720789 Cortex-A9 (prior to
1305 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1306 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1307 As a consequence of this erratum, some TLB entries which should be
1308 invalidated are not, resulting in an incoherency in the system page
1309 tables. The workaround changes the TLB flushing routines to invalidate
1310 entries regardless of the ASID.
1312 config PL310_ERRATA_727915
1313 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1314 depends on CACHE_L2X0
1316 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1317 operation (offset 0x7FC). This operation runs in background so that
1318 PL310 can handle normal accesses while it is in progress. Under very
1319 rare circumstances, due to this erratum, write data can be lost when
1320 PL310 treats a cacheable write transaction during a Clean &
1321 Invalidate by Way operation.
1323 config ARM_ERRATA_743622
1324 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1326 depends on !ARCH_MULTIPLATFORM
1328 This option enables the workaround for the 743622 Cortex-A9
1329 (r2p*) erratum. Under very rare conditions, a faulty
1330 optimisation in the Cortex-A9 Store Buffer may lead to data
1331 corruption. This workaround sets a specific bit in the diagnostic
1332 register of the Cortex-A9 which disables the Store Buffer
1333 optimisation, preventing the defect from occurring. This has no
1334 visible impact on the overall performance or power consumption of the
1337 config ARM_ERRATA_751472
1338 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1340 depends on !ARCH_MULTIPLATFORM
1342 This option enables the workaround for the 751472 Cortex-A9 (prior
1343 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1344 completion of a following broadcasted operation if the second
1345 operation is received by a CPU before the ICIALLUIS has completed,
1346 potentially leading to corrupted entries in the cache or TLB.
1348 config PL310_ERRATA_753970
1349 bool "PL310 errata: cache sync operation may be faulty"
1350 depends on CACHE_PL310
1352 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1354 Under some condition the effect of cache sync operation on
1355 the store buffer still remains when the operation completes.
1356 This means that the store buffer is always asked to drain and
1357 this prevents it from merging any further writes. The workaround
1358 is to replace the normal offset of cache sync operation (0x730)
1359 by another offset targeting an unmapped PL310 register 0x740.
1360 This has the same effect as the cache sync operation: store buffer
1361 drain and waiting for all buffers empty.
1363 config ARM_ERRATA_754322
1364 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1367 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1368 r3p*) erratum. A speculative memory access may cause a page table walk
1369 which starts prior to an ASID switch but completes afterwards. This
1370 can populate the micro-TLB with a stale entry which may be hit with
1371 the new ASID. This workaround places two dsb instructions in the mm
1372 switching code so that no page table walks can cross the ASID switch.
1374 config ARM_ERRATA_754327
1375 bool "ARM errata: no automatic Store Buffer drain"
1376 depends on CPU_V7 && SMP
1378 This option enables the workaround for the 754327 Cortex-A9 (prior to
1379 r2p0) erratum. The Store Buffer does not have any automatic draining
1380 mechanism and therefore a livelock may occur if an external agent
1381 continuously polls a memory location waiting to observe an update.
1382 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1383 written polling loops from denying visibility of updates to memory.
1385 config ARM_ERRATA_364296
1386 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1387 depends on CPU_V6 && !SMP
1389 This options enables the workaround for the 364296 ARM1136
1390 r0p2 erratum (possible cache data corruption with
1391 hit-under-miss enabled). It sets the undocumented bit 31 in
1392 the auxiliary control register and the FI bit in the control
1393 register, thus disabling hit-under-miss without putting the
1394 processor into full low interrupt latency mode. ARM11MPCore
1397 config ARM_ERRATA_764369
1398 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1399 depends on CPU_V7 && SMP
1401 This option enables the workaround for erratum 764369
1402 affecting Cortex-A9 MPCore with two or more processors (all
1403 current revisions). Under certain timing circumstances, a data
1404 cache line maintenance operation by MVA targeting an Inner
1405 Shareable memory region may fail to proceed up to either the
1406 Point of Coherency or to the Point of Unification of the
1407 system. This workaround adds a DSB instruction before the
1408 relevant cache maintenance functions and sets a specific bit
1409 in the diagnostic control register of the SCU.
1411 config PL310_ERRATA_769419
1412 bool "PL310 errata: no automatic Store Buffer drain"
1413 depends on CACHE_L2X0
1415 On revisions of the PL310 prior to r3p2, the Store Buffer does
1416 not automatically drain. This can cause normal, non-cacheable
1417 writes to be retained when the memory system is idle, leading
1418 to suboptimal I/O performance for drivers using coherent DMA.
1419 This option adds a write barrier to the cpu_idle loop so that,
1420 on systems with an outer cache, the store buffer is drained
1423 config ARM_ERRATA_775420
1424 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1427 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1428 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1429 operation aborts with MMU exception, it might cause the processor
1430 to deadlock. This workaround puts DSB before executing ISB if
1431 an abort may occur on cache maintenance.
1435 source "arch/arm/common/Kconfig"
1445 Find out whether you have ISA slots on your motherboard. ISA is the
1446 name of a bus system, i.e. the way the CPU talks to the other stuff
1447 inside your box. Other bus systems are PCI, EISA, MicroChannel
1448 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1449 newer boards don't support it. If you have ISA, say Y, otherwise N.
1451 # Select ISA DMA controller support
1456 config ARCH_NO_VIRT_TO_BUS
1458 depends on !ARCH_RPC && !ARCH_NETWINDER && !ARCH_SHARK
1460 # Select ISA DMA interface
1465 bool "PCI support" if MIGHT_HAVE_PCI
1467 Find out whether you have a PCI motherboard. PCI is the name of a
1468 bus system, i.e. the way the CPU talks to the other stuff inside
1469 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1470 VESA. If you have PCI, say Y, otherwise N.
1476 config PCI_NANOENGINE
1477 bool "BSE nanoEngine PCI support"
1478 depends on SA1100_NANOENGINE
1480 Enable PCI on the BSE nanoEngine board.
1485 # Select the host bridge type
1486 config PCI_HOST_VIA82C505
1488 depends on PCI && ARCH_SHARK
1491 config PCI_HOST_ITE8152
1493 depends on PCI && MACH_ARMCORE
1497 source "drivers/pci/Kconfig"
1499 source "drivers/pcmcia/Kconfig"
1503 menu "Kernel Features"
1508 This option should be selected by machines which have an SMP-
1511 The only effect of this option is to make the SMP-related
1512 options available to the user for configuration.
1515 bool "Symmetric Multi-Processing"
1516 depends on CPU_V6K || CPU_V7
1517 depends on GENERIC_CLOCKEVENTS
1520 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1521 select USE_GENERIC_SMP_HELPERS
1523 This enables support for systems with more than one CPU. If you have
1524 a system with only one CPU, like most personal computers, say N. If
1525 you have a system with more than one CPU, say Y.
1527 If you say N here, the kernel will run on single and multiprocessor
1528 machines, but will use only one CPU of a multiprocessor machine. If
1529 you say Y here, the kernel will run on many, but not all, single
1530 processor machines. On a single processor machine, the kernel will
1531 run faster if you say N here.
1533 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1534 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1535 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1537 If you don't know what to do here, say N.
1540 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1541 depends on SMP && !XIP_KERNEL
1544 SMP kernels contain instructions which fail on non-SMP processors.
1545 Enabling this option allows the kernel to modify itself to make
1546 these instructions safe. Disabling it allows about 1K of space
1549 If you don't know what to do here, say Y.
1551 config ARM_CPU_TOPOLOGY
1552 bool "Support cpu topology definition"
1553 depends on SMP && CPU_V7
1556 Support ARM cpu topology definition. The MPIDR register defines
1557 affinity between processors which is then used to describe the cpu
1558 topology of an ARM System.
1561 bool "Multi-core scheduler support"
1562 depends on ARM_CPU_TOPOLOGY
1564 Multi-core scheduler support improves the CPU scheduler's decision
1565 making when dealing with multi-core CPU chips at a cost of slightly
1566 increased overhead in some places. If unsure say N here.
1569 bool "SMT scheduler support"
1570 depends on ARM_CPU_TOPOLOGY
1572 Improves the CPU scheduler's decision making when dealing with
1573 MultiThreading at a cost of slightly increased overhead in some
1574 places. If unsure say N here.
1579 This option enables support for the ARM system coherency unit
1581 config HAVE_ARM_ARCH_TIMER
1582 bool "Architected timer support"
1584 select ARM_ARCH_TIMER
1586 This option enables support for the ARM architected timer
1592 This options enables support for the ARM timer and watchdog unit
1595 prompt "Memory split"
1598 Select the desired split between kernel and user memory.
1600 If you are not absolutely sure what you are doing, leave this
1604 bool "3G/1G user/kernel split"
1606 bool "2G/2G user/kernel split"
1608 bool "1G/3G user/kernel split"
1613 default 0x40000000 if VMSPLIT_1G
1614 default 0x80000000 if VMSPLIT_2G
1618 int "Maximum number of CPUs (2-32)"
1624 bool "Support for hot-pluggable CPUs"
1625 depends on SMP && HOTPLUG
1627 Say Y here to experiment with turning CPUs off and on. CPUs
1628 can be controlled through /sys/devices/system/cpu.
1631 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1634 Say Y here if you want Linux to communicate with system firmware
1635 implementing the PSCI specification for CPU-centric power
1636 management operations described in ARM document number ARM DEN
1637 0022A ("Power State Coordination Interface System Software on
1641 bool "Use local timer interrupts"
1644 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1646 Enable support for local timers on SMP platforms, rather then the
1647 legacy IPI broadcast method. Local timers allows the system
1648 accounting to be spread across the timer interval, preventing a
1649 "thundering herd" at every timer tick.
1653 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1654 default 355 if ARCH_U8500
1655 default 264 if MACH_H4700
1656 default 512 if SOC_OMAP5
1657 default 288 if ARCH_VT8500 || ARCH_SUNXI
1660 Maximum number of GPIOs in the system.
1662 If unsure, leave the default value.
1664 source kernel/Kconfig.preempt
1668 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1669 ARCH_S5PV210 || ARCH_EXYNOS4
1670 default AT91_TIMER_HZ if ARCH_AT91
1671 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1675 def_bool HIGH_RES_TIMERS
1677 config THUMB2_KERNEL
1678 bool "Compile the kernel in Thumb-2 mode"
1679 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1681 select ARM_ASM_UNIFIED
1684 By enabling this option, the kernel will be compiled in
1685 Thumb-2 mode. A compiler/assembler that understand the unified
1686 ARM-Thumb syntax is needed.
1690 config THUMB2_AVOID_R_ARM_THM_JUMP11
1691 bool "Work around buggy Thumb-2 short branch relocations in gas"
1692 depends on THUMB2_KERNEL && MODULES
1695 Various binutils versions can resolve Thumb-2 branches to
1696 locally-defined, preemptible global symbols as short-range "b.n"
1697 branch instructions.
1699 This is a problem, because there's no guarantee the final
1700 destination of the symbol, or any candidate locations for a
1701 trampoline, are within range of the branch. For this reason, the
1702 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1703 relocation in modules at all, and it makes little sense to add
1706 The symptom is that the kernel fails with an "unsupported
1707 relocation" error when loading some modules.
1709 Until fixed tools are available, passing
1710 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1711 code which hits this problem, at the cost of a bit of extra runtime
1712 stack usage in some cases.
1714 The problem is described in more detail at:
1715 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1717 Only Thumb-2 kernels are affected.
1719 Unless you are sure your tools don't have this problem, say Y.
1721 config ARM_ASM_UNIFIED
1725 bool "Use the ARM EABI to compile the kernel"
1727 This option allows for the kernel to be compiled using the latest
1728 ARM ABI (aka EABI). This is only useful if you are using a user
1729 space environment that is also compiled with EABI.
1731 Since there are major incompatibilities between the legacy ABI and
1732 EABI, especially with regard to structure member alignment, this
1733 option also changes the kernel syscall calling convention to
1734 disambiguate both ABIs and allow for backward compatibility support
1735 (selected with CONFIG_OABI_COMPAT).
1737 To use this you need GCC version 4.0.0 or later.
1740 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1741 depends on AEABI && !THUMB2_KERNEL
1744 This option preserves the old syscall interface along with the
1745 new (ARM EABI) one. It also provides a compatibility layer to
1746 intercept syscalls that have structure arguments which layout
1747 in memory differs between the legacy ABI and the new ARM EABI
1748 (only for non "thumb" binaries). This option adds a tiny
1749 overhead to all syscalls and produces a slightly larger kernel.
1750 If you know you'll be using only pure EABI user space then you
1751 can say N here. If this option is not selected and you attempt
1752 to execute a legacy ABI binary then the result will be
1753 UNPREDICTABLE (in fact it can be predicted that it won't work
1754 at all). If in doubt say Y.
1756 config ARCH_HAS_HOLES_MEMORYMODEL
1759 config ARCH_SPARSEMEM_ENABLE
1762 config ARCH_SPARSEMEM_DEFAULT
1763 def_bool ARCH_SPARSEMEM_ENABLE
1765 config ARCH_SELECT_MEMORY_MODEL
1766 def_bool ARCH_SPARSEMEM_ENABLE
1768 config HAVE_ARCH_PFN_VALID
1769 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1772 bool "High Memory Support"
1775 The address space of ARM processors is only 4 Gigabytes large
1776 and it has to accommodate user address space, kernel address
1777 space as well as some memory mapped IO. That means that, if you
1778 have a large amount of physical memory and/or IO, not all of the
1779 memory can be "permanently mapped" by the kernel. The physical
1780 memory that is not permanently mapped is called "high memory".
1782 Depending on the selected kernel/user memory split, minimum
1783 vmalloc space and actual amount of RAM, you may not need this
1784 option which should result in a slightly faster kernel.
1789 bool "Allocate 2nd-level pagetables from highmem"
1792 config HW_PERF_EVENTS
1793 bool "Enable hardware performance counter support for perf events"
1794 depends on PERF_EVENTS
1797 Enable hardware performance counter support for perf events. If
1798 disabled, perf events will use software events only.
1802 config FORCE_MAX_ZONEORDER
1803 int "Maximum zone order" if ARCH_SHMOBILE
1804 range 11 64 if ARCH_SHMOBILE
1805 default "12" if SOC_AM33XX
1806 default "9" if SA1111
1809 The kernel memory allocator divides physically contiguous memory
1810 blocks into "zones", where each zone is a power of two number of
1811 pages. This option selects the largest power of two that the kernel
1812 keeps in the memory allocator. If you need to allocate very large
1813 blocks of physically contiguous memory, then you may need to
1814 increase this value.
1816 This config option is actually maximum order plus one. For example,
1817 a value of 11 means that the largest free memory block is 2^10 pages.
1819 config ALIGNMENT_TRAP
1821 depends on CPU_CP15_MMU
1822 default y if !ARCH_EBSA110
1823 select HAVE_PROC_CPU if PROC_FS
1825 ARM processors cannot fetch/store information which is not
1826 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1827 address divisible by 4. On 32-bit ARM processors, these non-aligned
1828 fetch/store instructions will be emulated in software if you say
1829 here, which has a severe performance impact. This is necessary for
1830 correct operation of some network protocols. With an IP-only
1831 configuration it is safe to say N, otherwise say Y.
1833 config UACCESS_WITH_MEMCPY
1834 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1836 default y if CPU_FEROCEON
1838 Implement faster copy_to_user and clear_user methods for CPU
1839 cores where a 8-word STM instruction give significantly higher
1840 memory write throughput than a sequence of individual 32bit stores.
1842 A possible side effect is a slight increase in scheduling latency
1843 between threads sharing the same address space if they invoke
1844 such copy operations with large buffers.
1846 However, if the CPU data cache is using a write-allocate mode,
1847 this option is unlikely to provide any performance gain.
1851 prompt "Enable seccomp to safely compute untrusted bytecode"
1853 This kernel feature is useful for number crunching applications
1854 that may need to compute untrusted bytecode during their
1855 execution. By using pipes or other transports made available to
1856 the process as file descriptors supporting the read/write
1857 syscalls, it's possible to isolate those applications in
1858 their own address space using seccomp. Once seccomp is
1859 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1860 and the task is only allowed to execute a few safe syscalls
1861 defined by each seccomp mode.
1863 config CC_STACKPROTECTOR
1864 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1866 This option turns on the -fstack-protector GCC feature. This
1867 feature puts, at the beginning of functions, a canary value on
1868 the stack just before the return address, and validates
1869 the value just before actually returning. Stack based buffer
1870 overflows (that need to overwrite this return address) now also
1871 overwrite the canary, which gets detected and the attack is then
1872 neutralized via a kernel panic.
1873 This feature requires gcc version 4.2 or above.
1880 bool "Xen guest support on ARM (EXPERIMENTAL)"
1881 depends on ARM && OF
1882 depends on CPU_V7 && !CPU_V6
1884 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1891 bool "Flattened Device Tree support"
1894 select OF_EARLY_FLATTREE
1896 Include support for flattened device tree machine descriptions.
1899 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1902 This is the traditional way of passing data to the kernel at boot
1903 time. If you are solely relying on the flattened device tree (or
1904 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1905 to remove ATAGS support from your kernel binary. If unsure,
1908 config DEPRECATED_PARAM_STRUCT
1909 bool "Provide old way to pass kernel parameters"
1912 This was deprecated in 2001 and announced to live on for 5 years.
1913 Some old boot loaders still use this way.
1915 # Compressed boot loader in ROM. Yes, we really want to ask about
1916 # TEXT and BSS so we preserve their values in the config files.
1917 config ZBOOT_ROM_TEXT
1918 hex "Compressed ROM boot loader base address"
1921 The physical address at which the ROM-able zImage is to be
1922 placed in the target. Platforms which normally make use of
1923 ROM-able zImage formats normally set this to a suitable
1924 value in their defconfig file.
1926 If ZBOOT_ROM is not enabled, this has no effect.
1928 config ZBOOT_ROM_BSS
1929 hex "Compressed ROM boot loader BSS address"
1932 The base address of an area of read/write memory in the target
1933 for the ROM-able zImage which must be available while the
1934 decompressor is running. It must be large enough to hold the
1935 entire decompressed kernel plus an additional 128 KiB.
1936 Platforms which normally make use of ROM-able zImage formats
1937 normally set this to a suitable value in their defconfig file.
1939 If ZBOOT_ROM is not enabled, this has no effect.
1942 bool "Compressed boot loader in ROM/flash"
1943 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1945 Say Y here if you intend to execute your compressed kernel image
1946 (zImage) directly from ROM or flash. If unsure, say N.
1949 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1950 depends on ZBOOT_ROM && ARCH_SH7372
1951 default ZBOOT_ROM_NONE
1953 Include experimental SD/MMC loading code in the ROM-able zImage.
1954 With this enabled it is possible to write the ROM-able zImage
1955 kernel image to an MMC or SD card and boot the kernel straight
1956 from the reset vector. At reset the processor Mask ROM will load
1957 the first part of the ROM-able zImage which in turn loads the
1958 rest the kernel image to RAM.
1960 config ZBOOT_ROM_NONE
1961 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1963 Do not load image from SD or MMC
1965 config ZBOOT_ROM_MMCIF
1966 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1968 Load image from MMCIF hardware block.
1970 config ZBOOT_ROM_SH_MOBILE_SDHI
1971 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1973 Load image from SDHI hardware block
1977 config ARM_APPENDED_DTB
1978 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1979 depends on OF && !ZBOOT_ROM
1981 With this option, the boot code will look for a device tree binary
1982 (DTB) appended to zImage
1983 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1985 This is meant as a backward compatibility convenience for those
1986 systems with a bootloader that can't be upgraded to accommodate
1987 the documented boot protocol using a device tree.
1989 Beware that there is very little in terms of protection against
1990 this option being confused by leftover garbage in memory that might
1991 look like a DTB header after a reboot if no actual DTB is appended
1992 to zImage. Do not leave this option active in a production kernel
1993 if you don't intend to always append a DTB. Proper passing of the
1994 location into r2 of a bootloader provided DTB is always preferable
1997 config ARM_ATAG_DTB_COMPAT
1998 bool "Supplement the appended DTB with traditional ATAG information"
1999 depends on ARM_APPENDED_DTB
2001 Some old bootloaders can't be updated to a DTB capable one, yet
2002 they provide ATAGs with memory configuration, the ramdisk address,
2003 the kernel cmdline string, etc. Such information is dynamically
2004 provided by the bootloader and can't always be stored in a static
2005 DTB. To allow a device tree enabled kernel to be used with such
2006 bootloaders, this option allows zImage to extract the information
2007 from the ATAG list and store it at run time into the appended DTB.
2010 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2011 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2013 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2014 bool "Use bootloader kernel arguments if available"
2016 Uses the command-line options passed by the boot loader instead of
2017 the device tree bootargs property. If the boot loader doesn't provide
2018 any, the device tree bootargs property will be used.
2020 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2021 bool "Extend with bootloader kernel arguments"
2023 The command-line arguments provided by the boot loader will be
2024 appended to the the device tree bootargs property.
2029 string "Default kernel command string"
2032 On some architectures (EBSA110 and CATS), there is currently no way
2033 for the boot loader to pass arguments to the kernel. For these
2034 architectures, you should supply some command-line options at build
2035 time by entering them here. As a minimum, you should specify the
2036 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2039 prompt "Kernel command line type" if CMDLINE != ""
2040 default CMDLINE_FROM_BOOTLOADER
2043 config CMDLINE_FROM_BOOTLOADER
2044 bool "Use bootloader kernel arguments if available"
2046 Uses the command-line options passed by the boot loader. If
2047 the boot loader doesn't provide any, the default kernel command
2048 string provided in CMDLINE will be used.
2050 config CMDLINE_EXTEND
2051 bool "Extend bootloader kernel arguments"
2053 The command-line arguments provided by the boot loader will be
2054 appended to the default kernel command string.
2056 config CMDLINE_FORCE
2057 bool "Always use the default kernel command string"
2059 Always use the default kernel command string, even if the boot
2060 loader passes other arguments to the kernel.
2061 This is useful if you cannot or don't want to change the
2062 command-line options your boot loader passes to the kernel.
2066 bool "Kernel Execute-In-Place from ROM"
2067 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2069 Execute-In-Place allows the kernel to run from non-volatile storage
2070 directly addressable by the CPU, such as NOR flash. This saves RAM
2071 space since the text section of the kernel is not loaded from flash
2072 to RAM. Read-write sections, such as the data section and stack,
2073 are still copied to RAM. The XIP kernel is not compressed since
2074 it has to run directly from flash, so it will take more space to
2075 store it. The flash address used to link the kernel object files,
2076 and for storing it, is configuration dependent. Therefore, if you
2077 say Y here, you must know the proper physical address where to
2078 store the kernel image depending on your own flash memory usage.
2080 Also note that the make target becomes "make xipImage" rather than
2081 "make zImage" or "make Image". The final kernel binary to put in
2082 ROM memory will be arch/arm/boot/xipImage.
2086 config XIP_PHYS_ADDR
2087 hex "XIP Kernel Physical Location"
2088 depends on XIP_KERNEL
2089 default "0x00080000"
2091 This is the physical address in your flash memory the kernel will
2092 be linked for and stored to. This address is dependent on your
2096 bool "Kexec system call (EXPERIMENTAL)"
2097 depends on (!SMP || HOTPLUG_CPU)
2099 kexec is a system call that implements the ability to shutdown your
2100 current kernel, and to start another kernel. It is like a reboot
2101 but it is independent of the system firmware. And like a reboot
2102 you can start any kernel with it, not just Linux.
2104 It is an ongoing process to be certain the hardware in a machine
2105 is properly shutdown, so do not be surprised if this code does not
2106 initially work for you. It may help to enable device hotplugging
2110 bool "Export atags in procfs"
2111 depends on ATAGS && KEXEC
2114 Should the atags used to boot the kernel be exported in an "atags"
2115 file in procfs. Useful with kexec.
2118 bool "Build kdump crash kernel (EXPERIMENTAL)"
2120 Generate crash dump after being started by kexec. This should
2121 be normally only set in special crash dump kernels which are
2122 loaded in the main kernel with kexec-tools into a specially
2123 reserved region and then later executed after a crash by
2124 kdump/kexec. The crash dump kernel must be compiled to a
2125 memory address not used by the main kernel
2127 For more details see Documentation/kdump/kdump.txt
2129 config AUTO_ZRELADDR
2130 bool "Auto calculation of the decompressed kernel image address"
2131 depends on !ZBOOT_ROM && !ARCH_U300
2133 ZRELADDR is the physical address where the decompressed kernel
2134 image will be placed. If AUTO_ZRELADDR is selected, the address
2135 will be determined at run-time by masking the current IP with
2136 0xf8000000. This assumes the zImage being placed in the first 128MB
2137 from start of memory.
2141 menu "CPU Power Management"
2145 source "drivers/cpufreq/Kconfig"
2148 tristate "CPUfreq driver for i.MX CPUs"
2149 depends on ARCH_MXC && CPU_FREQ
2150 select CPU_FREQ_TABLE
2152 This enables the CPUfreq driver for i.MX CPUs.
2154 config CPU_FREQ_SA1100
2157 config CPU_FREQ_SA1110
2160 config CPU_FREQ_INTEGRATOR
2161 tristate "CPUfreq driver for ARM Integrator CPUs"
2162 depends on ARCH_INTEGRATOR && CPU_FREQ
2165 This enables the CPUfreq driver for ARM Integrator CPUs.
2167 For details, take a look at <file:Documentation/cpu-freq>.
2173 depends on CPU_FREQ && ARCH_PXA && PXA25x
2175 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2176 select CPU_FREQ_TABLE
2181 Internal configuration node for common cpufreq on Samsung SoC
2183 config CPU_FREQ_S3C24XX
2184 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2185 depends on ARCH_S3C24XX && CPU_FREQ
2188 This enables the CPUfreq driver for the Samsung S3C24XX family
2191 For details, take a look at <file:Documentation/cpu-freq>.
2195 config CPU_FREQ_S3C24XX_PLL
2196 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2197 depends on CPU_FREQ_S3C24XX
2199 Compile in support for changing the PLL frequency from the
2200 S3C24XX series CPUfreq driver. The PLL takes time to settle
2201 after a frequency change, so by default it is not enabled.
2203 This also means that the PLL tables for the selected CPU(s) will
2204 be built which may increase the size of the kernel image.
2206 config CPU_FREQ_S3C24XX_DEBUG
2207 bool "Debug CPUfreq Samsung driver core"
2208 depends on CPU_FREQ_S3C24XX
2210 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2212 config CPU_FREQ_S3C24XX_IODEBUG
2213 bool "Debug CPUfreq Samsung driver IO timing"
2214 depends on CPU_FREQ_S3C24XX
2216 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2218 config CPU_FREQ_S3C24XX_DEBUGFS
2219 bool "Export debugfs for CPUFreq"
2220 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2222 Export status information via debugfs.
2226 source "drivers/cpuidle/Kconfig"
2230 menu "Floating point emulation"
2232 comment "At least one emulation must be selected"
2235 bool "NWFPE math emulation"
2236 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2238 Say Y to include the NWFPE floating point emulator in the kernel.
2239 This is necessary to run most binaries. Linux does not currently
2240 support floating point hardware so you need to say Y here even if
2241 your machine has an FPA or floating point co-processor podule.
2243 You may say N here if you are going to load the Acorn FPEmulator
2244 early in the bootup.
2247 bool "Support extended precision"
2248 depends on FPE_NWFPE
2250 Say Y to include 80-bit support in the kernel floating-point
2251 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2252 Note that gcc does not generate 80-bit operations by default,
2253 so in most cases this option only enlarges the size of the
2254 floating point emulator without any good reason.
2256 You almost surely want to say N here.
2259 bool "FastFPE math emulation (EXPERIMENTAL)"
2260 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2262 Say Y here to include the FAST floating point emulator in the kernel.
2263 This is an experimental much faster emulator which now also has full
2264 precision for the mantissa. It does not support any exceptions.
2265 It is very simple, and approximately 3-6 times faster than NWFPE.
2267 It should be sufficient for most programs. It may be not suitable
2268 for scientific calculations, but you have to check this for yourself.
2269 If you do not feel you need a faster FP emulation you should better
2273 bool "VFP-format floating point maths"
2274 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2276 Say Y to include VFP support code in the kernel. This is needed
2277 if your hardware includes a VFP unit.
2279 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2280 release notes and additional status information.
2282 Say N if your target does not have VFP hardware.
2290 bool "Advanced SIMD (NEON) Extension support"
2291 depends on VFPv3 && CPU_V7
2293 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2298 menu "Userspace binary formats"
2300 source "fs/Kconfig.binfmt"
2303 tristate "RISC OS personality"
2306 Say Y here to include the kernel code necessary if you want to run
2307 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2308 experimental; if this sounds frightening, say N and sleep in peace.
2309 You can also say M here to compile this support as a module (which
2310 will be called arthur).
2314 menu "Power management options"
2316 source "kernel/power/Kconfig"
2318 config ARCH_SUSPEND_POSSIBLE
2319 depends on !ARCH_S5PC100
2320 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2321 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2324 config ARM_CPU_SUSPEND
2329 source "net/Kconfig"
2331 source "drivers/Kconfig"
2335 source "arch/arm/Kconfig.debug"
2337 source "security/Kconfig"
2339 source "crypto/Kconfig"
2341 source "lib/Kconfig"
2343 source "arch/arm/kvm/Kconfig"