arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/irqchip.h>
  16 #include <linux/io.h>
  17 #include <linux/device.h>
  18 #include <linux/gpio.h>
  19 #include <linux/sched.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/of.h>
  22 #include <linux/of_fdt.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/export.h>
  25 #include <linux/irqdomain.h>
  26 #include <linux/irqchip.h>
  27 #include <linux/of_address.h>
  28 #include <linux/irqchip/arm-gic.h>
  29
  30 #include <asm/proc-fns.h>
  31 #include <asm/exception.h>
  32 #include <asm/hardware/cache-l2x0.h>
  33 #include <asm/mach/map.h>
  34 #include <asm/mach/irq.h>
  35 #include <asm/cacheflush.h>
  36
  37 #include <mach/regs-irq.h>
  38 #include <mach/regs-pmu.h>
  39 #include <mach/regs-gpio.h>
  40
  41 #include <plat/cpu.h>
  42 #include <plat/clock.h>
  43 #include <plat/devs.h>
  44 #include <plat/pm.h>
  45 #include <plat/sdhci.h>
  46 #include <plat/gpio-cfg.h>
  47 #include <plat/adc-core.h>
  48 #include <plat/fb-core.h>
  49 #include <plat/fimc-core.h>
  50 #include <plat/iic-core.h>
  51 #include <plat/tv-core.h>
  52 #include <plat/spi-core.h>
  53 #include <plat/regs-serial.h>
  54
  55 #include "common.h"
  56 #define L2_AUX_VAL 0x7C470001
  57 #define L2_AUX_MASK 0xC200ffff
  58
  59 static const char name_exynos4210[] = "EXYNOS4210";
  60 static const char name_exynos4212[] = "EXYNOS4212";
  61 static const char name_exynos4412[] = "EXYNOS4412";
  62 static const char name_exynos5250[] = "EXYNOS5250";
  63 static const char name_exynos5440[] = "EXYNOS5440";
  64
  65 static void exynos4_map_io(void);
  66 static void exynos5_map_io(void);
  67 static void exynos5440_map_io(void);
  68 static void exynos4_init_clocks(int xtal);
  69 static void exynos5_init_clocks(int xtal);
  70 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  71 static int exynos_init(void);
  72
  73 static struct cpu_table cpu_ids[] __initdata = {
  74         {
  75                 .idcode         = EXYNOS4210_CPU_ID,
  76                 .idmask         = EXYNOS4_CPU_MASK,
  77                 .map_io         = exynos4_map_io,
  78                 .init_clocks    = exynos4_init_clocks,
  79                 .init_uarts     = exynos4_init_uarts,
  80                 .init           = exynos_init,
  81                 .name           = name_exynos4210,
  82         }, {
  83                 .idcode         = EXYNOS4212_CPU_ID,
  84                 .idmask         = EXYNOS4_CPU_MASK,
  85                 .map_io         = exynos4_map_io,
  86                 .init_clocks    = exynos4_init_clocks,
  87                 .init_uarts     = exynos4_init_uarts,
  88                 .init           = exynos_init,
  89                 .name           = name_exynos4212,
  90         }, {
  91                 .idcode         = EXYNOS4412_CPU_ID,
  92                 .idmask         = EXYNOS4_CPU_MASK,
  93                 .map_io         = exynos4_map_io,
  94                 .init_clocks    = exynos4_init_clocks,
  95                 .init_uarts     = exynos4_init_uarts,
  96                 .init           = exynos_init,
  97                 .name           = name_exynos4412,
  98         }, {
  99                 .idcode         = EXYNOS5250_SOC_ID,
 100                 .idmask         = EXYNOS5_SOC_MASK,
 101                 .map_io         = exynos5_map_io,
 102                 .init_clocks    = exynos5_init_clocks,
 103                 .init           = exynos_init,
 104                 .name           = name_exynos5250,
 105         }, {
 106                 .idcode         = EXYNOS5440_SOC_ID,
 107                 .idmask         = EXYNOS5_SOC_MASK,
 108                 .map_io         = exynos5440_map_io,
 109                 .init           = exynos_init,
 110                 .name           = name_exynos5440,
 111         },
 112 };
 113
 114 /* Initial IO mappings */
 115
 116 static struct map_desc exynos_iodesc[] __initdata = {
 117         {
 118                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 119                 .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
 120                 .length         = SZ_4K,
 121                 .type           = MT_DEVICE,
 122         },
 123 };
 124
 125 #ifdef CONFIG_ARCH_EXYNOS5
 126 static struct map_desc exynos5440_iodesc[] __initdata = {
 127         {
 128                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 129                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
 130                 .length         = SZ_4K,
 131                 .type           = MT_DEVICE,
 132         },
 133 };
 134 #endif
 135
 136 static struct map_desc exynos4_iodesc[] __initdata = {
 137         {
 138                 .virtual        = (unsigned long)S3C_VA_SYS,
 139                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 140                 .length         = SZ_64K,
 141                 .type           = MT_DEVICE,
 142         }, {
 143                 .virtual        = (unsigned long)S3C_VA_TIMER,
 144                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 145                 .length         = SZ_16K,
 146                 .type           = MT_DEVICE,
 147         }, {
 148                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 149                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 150                 .length         = SZ_4K,
 151                 .type           = MT_DEVICE,
 152         }, {
 153                 .virtual        = (unsigned long)S5P_VA_SROMC,
 154                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 155                 .length         = SZ_4K,
 156                 .type           = MT_DEVICE,
 157         }, {
 158                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 159                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 160                 .length         = SZ_4K,
 161                 .type           = MT_DEVICE,
 162         }, {
 163                 .virtual        = (unsigned long)S5P_VA_PMU,
 164                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 165                 .length         = SZ_64K,
 166                 .type           = MT_DEVICE,
 167         }, {
 168                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 169                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 170                 .length         = SZ_4K,
 171                 .type           = MT_DEVICE,
 172         }, {
 173                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 174                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 175                 .length         = SZ_64K,
 176                 .type           = MT_DEVICE,
 177         }, {
 178                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 179                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 180                 .length         = SZ_64K,
 181                 .type           = MT_DEVICE,
 182         }, {
 183                 .virtual        = (unsigned long)S3C_VA_UART,
 184                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 185                 .length         = SZ_512K,
 186                 .type           = MT_DEVICE,
 187         }, {
 188                 .virtual        = (unsigned long)S5P_VA_CMU,
 189                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 190                 .length         = SZ_128K,
 191                 .type           = MT_DEVICE,
 192         }, {
 193                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 194                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 195                 .length         = SZ_8K,
 196                 .type           = MT_DEVICE,
 197         }, {
 198                 .virtual        = (unsigned long)S5P_VA_L2CC,
 199                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 200                 .length         = SZ_4K,
 201                 .type           = MT_DEVICE,
 202         }, {
 203                 .virtual        = (unsigned long)S5P_VA_DMC0,
 204                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 205                 .length         = SZ_64K,
 206                 .type           = MT_DEVICE,
 207         }, {
 208                 .virtual        = (unsigned long)S5P_VA_DMC1,
 209                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 210                 .length         = SZ_64K,
 211                 .type           = MT_DEVICE,
 212         }, {
 213                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 214                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 215                 .length         = SZ_4K,
 216                 .type           = MT_DEVICE,
 217         },
 218 };
 219
 220 static struct map_desc exynos4_iodesc0[] __initdata = {
 221         {
 222                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 223                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 224                 .length         = SZ_4K,
 225                 .type           = MT_DEVICE,
 226         },
 227 };
 228
 229 static struct map_desc exynos4_iodesc1[] __initdata = {
 230         {
 231                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 232                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 233                 .length         = SZ_4K,
 234                 .type           = MT_DEVICE,
 235         },
 236 };
 237
 238 static struct map_desc exynos5_iodesc[] __initdata = {
 239         {
 240                 .virtual        = (unsigned long)S3C_VA_SYS,
 241                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 242                 .length         = SZ_64K,
 243                 .type           = MT_DEVICE,
 244         }, {
 245                 .virtual        = (unsigned long)S3C_VA_TIMER,
 246                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 247                 .length         = SZ_16K,
 248                 .type           = MT_DEVICE,
 249         }, {
 250                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 251                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 252                 .length         = SZ_4K,
 253                 .type           = MT_DEVICE,
 254         }, {
 255                 .virtual        = (unsigned long)S5P_VA_SROMC,
 256                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 257                 .length         = SZ_4K,
 258                 .type           = MT_DEVICE,
 259         }, {
 260                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 261                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
 262                 .length         = SZ_4K,
 263                 .type           = MT_DEVICE,
 264         }, {
 265                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 266                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 267                 .length         = SZ_4K,
 268                 .type           = MT_DEVICE,
 269         }, {
 270                 .virtual        = (unsigned long)S5P_VA_CMU,
 271                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 272                 .length         = 144 * SZ_1K,
 273                 .type           = MT_DEVICE,
 274         }, {
 275                 .virtual        = (unsigned long)S5P_VA_PMU,
 276                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 277                 .length         = SZ_64K,
 278                 .type           = MT_DEVICE,
 279         }, {
 280                 .virtual        = (unsigned long)S3C_VA_UART,
 281                 .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
 282                 .length         = SZ_512K,
 283                 .type           = MT_DEVICE,
 284         },
 285 };
 286
 287 static struct map_desc exynos5440_iodesc0[] __initdata = {
 288         {
 289                 .virtual        = (unsigned long)S3C_VA_UART,
 290                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_UART0),
 291                 .length         = SZ_512K,
 292                 .type           = MT_DEVICE,
 293         },
 294 };
 295
 296 void exynos4_restart(char mode, const char *cmd)
 297 {
 298         __raw_writel(0x1, S5P_SWRESET);
 299 }
 300
 301 void exynos5_restart(char mode, const char *cmd)
 302 {
 303         struct device_node *np;
 304         u32 val;
 305         void __iomem *addr;
 306
 307         if (of_machine_is_compatible("samsung,exynos5250")) {
 308                 val = 0x1;
 309                 addr = EXYNOS_SWRESET;
 310         } else if (of_machine_is_compatible("samsung,exynos5440")) {
 311                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
 312                 addr = of_iomap(np, 0) + 0xcc;
 313                 val = (0xfff << 20) | (0x1 << 16);
 314         } else {
 315                 pr_err("%s: cannot support non-DT\n", __func__);
 316                 return;
 317         }
 318
 319         __raw_writel(val, addr);
 320 }
 321
 322 void __init exynos_init_late(void)
 323 {
 324         if (of_machine_is_compatible("samsung,exynos5440"))
 325                 /* to be supported later */
 326                 return;
 327
 328         exynos_pm_late_initcall();
 329 }
 330
 331 /*
 332  * exynos_map_io
 333  *
 334  * register the standard cpu IO areas
 335  */
 336
 337 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 338 {
 339         struct map_desc *iodesc = exynos_iodesc;
 340         int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
 341 #if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
 342         unsigned long root = of_get_flat_dt_root();
 343
 344         /* initialize the io descriptors we need for initialization */
 345         if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
 346                 iodesc = exynos5440_iodesc;
 347                 iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
 348         }
 349 #endif
 350
 351         iotable_init(iodesc, iodesc_sz);
 352
 353         if (mach_desc)
 354                 iotable_init(mach_desc, size);
 355
 356         /* detect cpu id and rev. */
 357         s5p_init_cpu(S5P_VA_CHIPID);
 358
 359         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 360 }
 361
 362 static void __init exynos4_map_io(void)
 363 {
 364         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 365
 366         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 367                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 368         else
 369                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 370
 371         /* initialize device information early */
 372         exynos4_default_sdhci0();
 373         exynos4_default_sdhci1();
 374         exynos4_default_sdhci2();
 375         exynos4_default_sdhci3();
 376
 377         s3c_adc_setname("samsung-adc-v3");
 378
 379         s3c_fimc_setname(0, "exynos4-fimc");
 380         s3c_fimc_setname(1, "exynos4-fimc");
 381         s3c_fimc_setname(2, "exynos4-fimc");
 382         s3c_fimc_setname(3, "exynos4-fimc");
 383
 384         s3c_sdhci_setname(0, "exynos4-sdhci");
 385         s3c_sdhci_setname(1, "exynos4-sdhci");
 386         s3c_sdhci_setname(2, "exynos4-sdhci");
 387         s3c_sdhci_setname(3, "exynos4-sdhci");
 388
 389         /* The I2C bus controllers are directly compatible with s3c2440 */
 390         s3c_i2c0_setname("s3c2440-i2c");
 391         s3c_i2c1_setname("s3c2440-i2c");
 392         s3c_i2c2_setname("s3c2440-i2c");
 393
 394         s5p_fb_setname(0, "exynos4-fb");
 395         s5p_hdmi_setname("exynos4-hdmi");
 396
 397         s3c64xx_spi_setname("exynos4210-spi");
 398 }
 399
 400 static void __init exynos5_map_io(void)
 401 {
 402         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 403 }
 404
 405 static void __init exynos4_init_clocks(int xtal)
 406 {
 407         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 408
 409         s3c24xx_register_baseclocks(xtal);
 410         s5p_register_clocks(xtal);
 411
 412         if (soc_is_exynos4210())
 413                 exynos4210_register_clocks();
 414         else if (soc_is_exynos4212() || soc_is_exynos4412())
 415                 exynos4212_register_clocks();
 416
 417         exynos4_register_clocks();
 418         exynos4_setup_clocks();
 419 }
 420
 421 static void __init exynos5440_map_io(void)
 422 {
 423         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 424 }
 425
 426 static void __init exynos5_init_clocks(int xtal)
 427 {
 428         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 429
 430         /* EXYNOS5440 can support only common clock framework */
 431
 432         if (soc_is_exynos5440())
 433                 return;
 434
 435 #ifdef CONFIG_SOC_EXYNOS5250
 436         s3c24xx_register_baseclocks(xtal);
 437         s5p_register_clocks(xtal);
 438
 439         exynos5_register_clocks();
 440         exynos5_setup_clocks();
 441 #endif
 442 }
 443
 444 void __init exynos4_init_irq(void)
 445 {
 446         unsigned int gic_bank_offset;
 447
 448         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 449
 450         if (!of_have_populated_dt())
 451                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 452 #ifdef CONFIG_OF
 453         else
 454                 irqchip_init();
 455 #endif
 456
 457         if (!of_have_populated_dt())
 458                 combiner_init(S5P_VA_COMBINER_BASE, NULL);
 459
 460         /*
 461          * The parameters of s5p_init_irq() are for VIC init.
 462          * Theses parameters should be NULL and 0 because EXYNOS4
 463          * uses GIC instead of VIC.
 464          */
 465         s5p_init_irq(NULL, 0);
 466 }
 467
 468 void __init exynos5_init_irq(void)
 469 {
 470 #ifdef CONFIG_OF
 471         irqchip_init();
 472 #endif
 473         /*
 474          * The parameters of s5p_init_irq() are for VIC init.
 475          * Theses parameters should be NULL and 0 because EXYNOS4
 476          * uses GIC instead of VIC.
 477          */
 478         if (!of_machine_is_compatible("samsung,exynos5440"))
 479                 s5p_init_irq(NULL, 0);
 480
 481         gic_arch_extn.irq_set_wake = s3c_irq_wake;
 482 }
 483
 484 struct bus_type exynos_subsys = {
 485         .name           = "exynos-core",
 486         .dev_name       = "exynos-core",
 487 };
 488
 489 static struct device exynos4_dev = {
 490         .bus    = &exynos_subsys,
 491 };
 492
 493 static int __init exynos_core_init(void)
 494 {
 495         return subsys_system_register(&exynos_subsys, NULL);
 496 }
 497 core_initcall(exynos_core_init);
 498
 499 #ifdef CONFIG_CACHE_L2X0
 500 static int __init exynos4_l2x0_cache_init(void)
 501 {
 502         int ret;
 503
 504         if (soc_is_exynos5250() || soc_is_exynos5440())
 505                 return 0;
 506
 507         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 508         if (!ret) {
 509                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 510                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 511                 return 0;
 512         }
 513
 514         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
 515                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
 516                 /* TAG, Data Latency Control: 2 cycles */
 517                 l2x0_saved_regs.tag_latency = 0x110;
 518
 519                 if (soc_is_exynos4212() || soc_is_exynos4412())
 520                         l2x0_saved_regs.data_latency = 0x120;
 521                 else
 522                         l2x0_saved_regs.data_latency = 0x110;
 523
 524                 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
 525                 l2x0_saved_regs.pwr_ctrl =
 526                         (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
 527
 528                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 529
 530                 __raw_writel(l2x0_saved_regs.tag_latency,
 531                                 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 532                 __raw_writel(l2x0_saved_regs.data_latency,
 533                                 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 534
 535                 /* L2X0 Prefetch Control */
 536                 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
 537                                 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 538
 539                 /* L2X0 Power Control */
 540                 __raw_writel(l2x0_saved_regs.pwr_ctrl,
 541                                 S5P_VA_L2CC + L2X0_POWER_CTRL);
 542
 543                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 544                 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 545         }
 546
 547         l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
 548         return 0;
 549 }
 550 early_initcall(exynos4_l2x0_cache_init);
 551 #endif
 552
 553 static int __init exynos_init(void)
 554 {
 555         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 556
 557         return device_register(&exynos4_dev);
 558 }
 559
 560 /* uart registration process */
 561
 562 static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 563 {
 564         struct s3c2410_uartcfg *tcfg = cfg;
 565         u32 ucnt;
 566
 567         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 568                 tcfg->has_fracval = 1;
 569
 570         s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 571 }
 572
 573 static void __iomem *exynos_eint_base;
 574
 575 static DEFINE_SPINLOCK(eint_lock);
 576
 577 static unsigned int eint0_15_data[16];
 578
 579 static inline int exynos4_irq_to_gpio(unsigned int irq)
 580 {
 581         if (irq < IRQ_EINT(0))
 582                 return -EINVAL;
 583
 584         irq -= IRQ_EINT(0);
 585         if (irq < 8)
 586                 return EXYNOS4_GPX0(irq);
 587
 588         irq -= 8;
 589         if (irq < 8)
 590                 return EXYNOS4_GPX1(irq);
 591
 592         irq -= 8;
 593         if (irq < 8)
 594                 return EXYNOS4_GPX2(irq);
 595
 596         irq -= 8;
 597         if (irq < 8)
 598                 return EXYNOS4_GPX3(irq);
 599
 600         return -EINVAL;
 601 }
 602
 603 static inline int exynos5_irq_to_gpio(unsigned int irq)
 604 {
 605         if (irq < IRQ_EINT(0))
 606                 return -EINVAL;
 607
 608         irq -= IRQ_EINT(0);
 609         if (irq < 8)
 610                 return EXYNOS5_GPX0(irq);
 611
 612         irq -= 8;
 613         if (irq < 8)
 614                 return EXYNOS5_GPX1(irq);
 615
 616         irq -= 8;
 617         if (irq < 8)
 618                 return EXYNOS5_GPX2(irq);
 619
 620         irq -= 8;
 621         if (irq < 8)
 622                 return EXYNOS5_GPX3(irq);
 623
 624         return -EINVAL;
 625 }
 626
 627 static unsigned int exynos4_eint0_15_src_int[16] = {
 628         EXYNOS4_IRQ_EINT0,
 629         EXYNOS4_IRQ_EINT1,
 630         EXYNOS4_IRQ_EINT2,
 631         EXYNOS4_IRQ_EINT3,
 632         EXYNOS4_IRQ_EINT4,
 633         EXYNOS4_IRQ_EINT5,
 634         EXYNOS4_IRQ_EINT6,
 635         EXYNOS4_IRQ_EINT7,
 636         EXYNOS4_IRQ_EINT8,
 637         EXYNOS4_IRQ_EINT9,
 638         EXYNOS4_IRQ_EINT10,
 639         EXYNOS4_IRQ_EINT11,
 640         EXYNOS4_IRQ_EINT12,
 641         EXYNOS4_IRQ_EINT13,
 642         EXYNOS4_IRQ_EINT14,
 643         EXYNOS4_IRQ_EINT15,
 644 };
 645
 646 static unsigned int exynos5_eint0_15_src_int[16] = {
 647         EXYNOS5_IRQ_EINT0,
 648         EXYNOS5_IRQ_EINT1,
 649         EXYNOS5_IRQ_EINT2,
 650         EXYNOS5_IRQ_EINT3,
 651         EXYNOS5_IRQ_EINT4,
 652         EXYNOS5_IRQ_EINT5,
 653         EXYNOS5_IRQ_EINT6,
 654         EXYNOS5_IRQ_EINT7,
 655         EXYNOS5_IRQ_EINT8,
 656         EXYNOS5_IRQ_EINT9,
 657         EXYNOS5_IRQ_EINT10,
 658         EXYNOS5_IRQ_EINT11,
 659         EXYNOS5_IRQ_EINT12,
 660         EXYNOS5_IRQ_EINT13,
 661         EXYNOS5_IRQ_EINT14,
 662         EXYNOS5_IRQ_EINT15,
 663 };
 664 static inline void exynos_irq_eint_mask(struct irq_data *data)
 665 {
 666         u32 mask;
 667
 668         spin_lock(&eint_lock);
 669         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 670         mask |= EINT_OFFSET_BIT(data->irq);
 671         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 672         spin_unlock(&eint_lock);
 673 }
 674
 675 static void exynos_irq_eint_unmask(struct irq_data *data)
 676 {
 677         u32 mask;
 678
 679         spin_lock(&eint_lock);
 680         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 681         mask &= ~(EINT_OFFSET_BIT(data->irq));
 682         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 683         spin_unlock(&eint_lock);
 684 }
 685
 686 static inline void exynos_irq_eint_ack(struct irq_data *data)
 687 {
 688         __raw_writel(EINT_OFFSET_BIT(data->irq),
 689                      EINT_PEND(exynos_eint_base, data->irq));
 690 }
 691
 692 static void exynos_irq_eint_maskack(struct irq_data *data)
 693 {
 694         exynos_irq_eint_mask(data);
 695         exynos_irq_eint_ack(data);
 696 }
 697
 698 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 699 {
 700         int offs = EINT_OFFSET(data->irq);
 701         int shift;
 702         u32 ctrl, mask;
 703         u32 newvalue = 0;
 704
 705         switch (type) {
 706         case IRQ_TYPE_EDGE_RISING:
 707                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 708                 break;
 709
 710         case IRQ_TYPE_EDGE_FALLING:
 711                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 712                 break;
 713
 714         case IRQ_TYPE_EDGE_BOTH:
 715                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 716                 break;
 717
 718         case IRQ_TYPE_LEVEL_LOW:
 719                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 720                 break;
 721
 722         case IRQ_TYPE_LEVEL_HIGH:
 723                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 724                 break;
 725
 726         default:
 727                 printk(KERN_ERR "No such irq type %d", type);
 728                 return -EINVAL;
 729         }
 730
 731         shift = (offs & 0x7) * 4;
 732         mask = 0x7 << shift;
 733
 734         spin_lock(&eint_lock);
 735         ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
 736         ctrl &= ~mask;
 737         ctrl |= newvalue << shift;
 738         __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
 739         spin_unlock(&eint_lock);
 740
 741         if (soc_is_exynos5250())
 742                 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 743         else
 744                 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 745
 746         return 0;
 747 }
 748
 749 static struct irq_chip exynos_irq_eint = {
 750         .name           = "exynos-eint",
 751         .irq_mask       = exynos_irq_eint_mask,
 752         .irq_unmask     = exynos_irq_eint_unmask,
 753         .irq_mask_ack   = exynos_irq_eint_maskack,
 754         .irq_ack        = exynos_irq_eint_ack,
 755         .irq_set_type   = exynos_irq_eint_set_type,
 756 #ifdef CONFIG_PM
 757         .irq_set_wake   = s3c_irqext_wake,
 758 #endif
 759 };
 760
 761 /*
 762  * exynos4_irq_demux_eint
 763  *
 764  * This function demuxes the IRQ from from EINTs 16 to 31.
 765  * It is designed to be inlined into the specific handler
 766  * s5p_irq_demux_eintX_Y.
 767  *
 768  * Each EINT pend/mask registers handle eight of them.
 769  */
 770 static inline void exynos_irq_demux_eint(unsigned int start)
 771 {
 772         unsigned int irq;
 773
 774         u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
 775         u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 776
 777         status &= ~mask;
 778         status &= 0xff;
 779
 780         while (status) {
 781                 irq = fls(status) - 1;
 782                 generic_handle_irq(irq + start);
 783                 status &= ~(1 << irq);
 784         }
 785 }
 786
 787 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 788 {
 789         struct irq_chip *chip = irq_get_chip(irq);
 790         chained_irq_enter(chip, desc);
 791         exynos_irq_demux_eint(IRQ_EINT(16));
 792         exynos_irq_demux_eint(IRQ_EINT(24));
 793         chained_irq_exit(chip, desc);
 794 }
 795
 796 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 797 {
 798         u32 *irq_data = irq_get_handler_data(irq);
 799         struct irq_chip *chip = irq_get_chip(irq);
 800
 801         chained_irq_enter(chip, desc);
 802         generic_handle_irq(*irq_data);
 803         chained_irq_exit(chip, desc);
 804 }
 805
 806 static int __init exynos_init_irq_eint(void)
 807 {
 808         int irq;
 809
 810 #ifdef CONFIG_PINCTRL_SAMSUNG
 811         /*
 812          * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
 813          * functionality along with support for external gpio and wakeup
 814          * interrupts. If the samsung pinctrl driver is enabled and includes
 815          * the wakeup interrupt support, then the setting up external wakeup
 816          * interrupts here can be skipped. This check here is temporary to
 817          * allow exynos4 platforms that do not use Samsung pinctrl driver to
 818          * co-exist with platforms that do. When all of the Samsung Exynos4
 819          * platforms switch over to using the pinctrl driver, the wakeup
 820          * interrupt support code here can be completely removed.
 821          */
 822         static const struct of_device_id exynos_pinctrl_ids[] = {
 823                 { .compatible = "samsung,exynos4210-pinctrl", },
 824                 { .compatible = "samsung,exynos4x12-pinctrl", },
 825         };
 826         struct device_node *pctrl_np, *wkup_np;
 827         const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
 828
 829         for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
 830                 if (of_device_is_available(pctrl_np)) {
 831                         wkup_np = of_find_compatible_node(pctrl_np, NULL,
 832                                                         wkup_compat);
 833                         if (wkup_np)
 834                                 return -ENODEV;
 835                 }
 836         }
 837 #endif
 838         if (soc_is_exynos5440())
 839                 return 0;
 840
 841         if (soc_is_exynos5250())
 842                 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
 843         else
 844                 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
 845
 846         if (exynos_eint_base == NULL) {
 847                 pr_err("unable to ioremap for EINT base address\n");
 848                 return -ENOMEM;
 849         }
 850
 851         for (irq = 0 ; irq <= 31 ; irq++) {
 852                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
 853                                          handle_level_irq);
 854                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 855         }
 856
 857         irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 858
 859         for (irq = 0 ; irq <= 15 ; irq++) {
 860                 eint0_15_data[irq] = IRQ_EINT(irq);
 861
 862                 if (soc_is_exynos5250()) {
 863                         irq_set_handler_data(exynos5_eint0_15_src_int[irq],
 864                                              &eint0_15_data[irq]);
 865                         irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
 866                                                 exynos_irq_eint0_15);
 867                 } else {
 868                         irq_set_handler_data(exynos4_eint0_15_src_int[irq],
 869                                              &eint0_15_data[irq]);
 870                         irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
 871                                                 exynos_irq_eint0_15);
 872                 }
 873         }
 874
 875         return 0;
 876 }
 877 arch_initcall(exynos_init_irq_eint);