drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include "drm_crtc_helper.h"
  34 #include "drm_edid.h"
  35
  36 static int radeon_ddc_dump(struct drm_connector *connector);
  37
  38 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  39 {
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         struct drm_device *dev = crtc->dev;
  42         struct radeon_device *rdev = dev->dev_private;
  43         int i;
  44
  45         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  46         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  47
  48         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  49         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  50         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  51
  52         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  53         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  54         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  55
  56         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  57         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  58         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  59
  60         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  61         for (i = 0; i < 256; i++) {
  62                 WREG32(AVIVO_DC_LUT_30_COLOR,
  63                              (radeon_crtc->lut_r[i] << 20) |
  64                              (radeon_crtc->lut_g[i] << 10) |
  65                              (radeon_crtc->lut_b[i] << 0));
  66         }
  67
  68         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
  69 }
  70
  71 static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
  72 {
  73         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  74         struct drm_device *dev = crtc->dev;
  75         struct radeon_device *rdev = dev->dev_private;
  76         int i;
  77
  78         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  79         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  80
  81         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  82         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  83         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  84
  85         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  86         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  87         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  88
  89         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  90         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  91
  92         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  93         for (i = 0; i < 256; i++) {
  94                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  95                        (radeon_crtc->lut_r[i] << 20) |
  96                        (radeon_crtc->lut_g[i] << 10) |
  97                        (radeon_crtc->lut_b[i] << 0));
  98         }
  99 }
 100
 101 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 102 {
 103         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 104         struct drm_device *dev = crtc->dev;
 105         struct radeon_device *rdev = dev->dev_private;
 106         int i;
 107         uint32_t dac2_cntl;
 108
 109         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 110         if (radeon_crtc->crtc_id == 0)
 111                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 112         else
 113                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 114         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 115
 116         WREG8(RADEON_PALETTE_INDEX, 0);
 117         for (i = 0; i < 256; i++) {
 118                 WREG32(RADEON_PALETTE_30_DATA,
 119                              (radeon_crtc->lut_r[i] << 20) |
 120                              (radeon_crtc->lut_g[i] << 10) |
 121                              (radeon_crtc->lut_b[i] << 0));
 122         }
 123 }
 124
 125 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 126 {
 127         struct drm_device *dev = crtc->dev;
 128         struct radeon_device *rdev = dev->dev_private;
 129
 130         if (!crtc->enabled)
 131                 return;
 132
 133         if (ASIC_IS_DCE4(rdev))
 134                 evergreen_crtc_load_lut(crtc);
 135         else if (ASIC_IS_AVIVO(rdev))
 136                 avivo_crtc_load_lut(crtc);
 137         else
 138                 legacy_crtc_load_lut(crtc);
 139 }
 140
 141 void radeon_crtc_save_lut(struct drm_crtc *crtc)
 142 {
 143         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 144         int i;
 145
 146         if (!crtc->enabled)
 147                 return;
 148
 149         for (i = 0; i < 256; i++) {
 150                 radeon_crtc->lut_r_copy[i] = radeon_crtc->lut_r[i];
 151                 radeon_crtc->lut_g_copy[i] = radeon_crtc->lut_g[i];
 152                 radeon_crtc->lut_b_copy[i] = radeon_crtc->lut_b[i];
 153         }
 154 }
 155
 156 void radeon_crtc_restore_lut(struct drm_crtc *crtc)
 157 {
 158         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 159         int i;
 160
 161         if (!crtc->enabled)
 162                 return;
 163
 164         for (i = 0; i < 256; i++) {
 165                 radeon_crtc->lut_r[i] = radeon_crtc->lut_r_copy[i];
 166                 radeon_crtc->lut_g[i] = radeon_crtc->lut_g_copy[i];
 167                 radeon_crtc->lut_b[i] = radeon_crtc->lut_b_copy[i];
 168         }
 169
 170         radeon_crtc_load_lut(crtc);
 171 }
 172
 173 /** Sets the color ramps on behalf of fbcon */
 174 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 175                               u16 blue, int regno)
 176 {
 177         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 178
 179         radeon_crtc->lut_r[regno] = red >> 6;
 180         radeon_crtc->lut_g[regno] = green >> 6;
 181         radeon_crtc->lut_b[regno] = blue >> 6;
 182 }
 183
 184 /** Gets the color ramps on behalf of fbcon */
 185 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 186                               u16 *blue, int regno)
 187 {
 188         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 189
 190         *red = radeon_crtc->lut_r[regno] << 6;
 191         *green = radeon_crtc->lut_g[regno] << 6;
 192         *blue = radeon_crtc->lut_b[regno] << 6;
 193 }
 194
 195 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 196                                   u16 *blue, uint32_t start, uint32_t size)
 197 {
 198         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 199         int end = (start + size > 256) ? 256 : start + size, i;
 200
 201         /* userspace palettes are always correct as is */
 202         for (i = start; i < end; i++) {
 203                 radeon_crtc->lut_r[i] = red[i] >> 6;
 204                 radeon_crtc->lut_g[i] = green[i] >> 6;
 205                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 206         }
 207         radeon_crtc_load_lut(crtc);
 208 }
 209
 210 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 211 {
 212         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 213
 214         drm_crtc_cleanup(crtc);
 215         kfree(radeon_crtc);
 216 }
 217
 218 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 219         .cursor_set = radeon_crtc_cursor_set,
 220         .cursor_move = radeon_crtc_cursor_move,
 221         .gamma_set = radeon_crtc_gamma_set,
 222         .set_config = drm_crtc_helper_set_config,
 223         .destroy = radeon_crtc_destroy,
 224 };
 225
 226 static void radeon_crtc_init(struct drm_device *dev, int index)
 227 {
 228         struct radeon_device *rdev = dev->dev_private;
 229         struct radeon_crtc *radeon_crtc;
 230         int i;
 231
 232         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 233         if (radeon_crtc == NULL)
 234                 return;
 235
 236         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 237
 238         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 239         radeon_crtc->crtc_id = index;
 240         rdev->mode_info.crtcs[index] = radeon_crtc;
 241
 242 #if 0
 243         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 244         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 245         radeon_crtc->mode_set.num_connectors = 0;
 246 #endif
 247
 248         for (i = 0; i < 256; i++) {
 249                 radeon_crtc->lut_r[i] = i << 2;
 250                 radeon_crtc->lut_g[i] = i << 2;
 251                 radeon_crtc->lut_b[i] = i << 2;
 252         }
 253
 254         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 255                 radeon_atombios_init_crtc(dev, radeon_crtc);
 256         else
 257                 radeon_legacy_init_crtc(dev, radeon_crtc);
 258 }
 259
 260 static const char *encoder_names[34] = {
 261         "NONE",
 262         "INTERNAL_LVDS",
 263         "INTERNAL_TMDS1",
 264         "INTERNAL_TMDS2",
 265         "INTERNAL_DAC1",
 266         "INTERNAL_DAC2",
 267         "INTERNAL_SDVOA",
 268         "INTERNAL_SDVOB",
 269         "SI170B",
 270         "CH7303",
 271         "CH7301",
 272         "INTERNAL_DVO1",
 273         "EXTERNAL_SDVOA",
 274         "EXTERNAL_SDVOB",
 275         "TITFP513",
 276         "INTERNAL_LVTM1",
 277         "VT1623",
 278         "HDMI_SI1930",
 279         "HDMI_INTERNAL",
 280         "INTERNAL_KLDSCP_TMDS1",
 281         "INTERNAL_KLDSCP_DVO1",
 282         "INTERNAL_KLDSCP_DAC1",
 283         "INTERNAL_KLDSCP_DAC2",
 284         "SI178",
 285         "MVPU_FPGA",
 286         "INTERNAL_DDI",
 287         "VT1625",
 288         "HDMI_SI1932",
 289         "DP_AN9801",
 290         "DP_DP501",
 291         "INTERNAL_UNIPHY",
 292         "INTERNAL_KLDSCP_LVTMA",
 293         "INTERNAL_UNIPHY1",
 294         "INTERNAL_UNIPHY2",
 295 };
 296
 297 static const char *connector_names[15] = {
 298         "Unknown",
 299         "VGA",
 300         "DVI-I",
 301         "DVI-D",
 302         "DVI-A",
 303         "Composite",
 304         "S-video",
 305         "LVDS",
 306         "Component",
 307         "DIN",
 308         "DisplayPort",
 309         "HDMI-A",
 310         "HDMI-B",
 311         "TV",
 312         "eDP",
 313 };
 314
 315 static const char *hpd_names[6] = {
 316         "HPD1",
 317         "HPD2",
 318         "HPD3",
 319         "HPD4",
 320         "HPD5",
 321         "HPD6",
 322 };
 323
 324 static void radeon_print_display_setup(struct drm_device *dev)
 325 {
 326         struct drm_connector *connector;
 327         struct radeon_connector *radeon_connector;
 328         struct drm_encoder *encoder;
 329         struct radeon_encoder *radeon_encoder;
 330         uint32_t devices;
 331         int i = 0;
 332
 333         DRM_INFO("Radeon Display Connectors\n");
 334         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 335                 radeon_connector = to_radeon_connector(connector);
 336                 DRM_INFO("Connector %d:\n", i);
 337                 DRM_INFO("  %s\n", connector_names[connector->connector_type]);
 338                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 339                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 340                 if (radeon_connector->ddc_bus) {
 341                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 342                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 343                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 344                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 345                                  radeon_connector->ddc_bus->rec.a_data_reg,
 346                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 347                                  radeon_connector->ddc_bus->rec.en_data_reg,
 348                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 349                                  radeon_connector->ddc_bus->rec.y_data_reg);
 350                         if (radeon_connector->router_bus)
 351                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 352                                          radeon_connector->router.mux_control_pin,
 353                                          radeon_connector->router.mux_state);
 354                 } else {
 355                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 356                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 357                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 358                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 359                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 360                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 361                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 362                 }
 363                 DRM_INFO("  Encoders:\n");
 364                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 365                         radeon_encoder = to_radeon_encoder(encoder);
 366                         devices = radeon_encoder->devices & radeon_connector->devices;
 367                         if (devices) {
 368                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 369                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 370                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 371                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 372                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 373                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 374                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 375                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 376                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 377                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 378                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 379                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 380                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 381                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 382                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 383                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 384                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 385                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 386                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 387                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 388                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 389                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 390                         }
 391                 }
 392                 i++;
 393         }
 394 }
 395
 396 static bool radeon_setup_enc_conn(struct drm_device *dev)
 397 {
 398         struct radeon_device *rdev = dev->dev_private;
 399         struct drm_connector *drm_connector;
 400         bool ret = false;
 401
 402         if (rdev->bios) {
 403                 if (rdev->is_atom_bios) {
 404                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 405                         if (ret == false)
 406                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 407                 } else {
 408                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 409                         if (ret == false)
 410                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 411                 }
 412         } else {
 413                 if (!ASIC_IS_AVIVO(rdev))
 414                         ret = radeon_get_legacy_connector_info_from_table(dev);
 415         }
 416         if (ret) {
 417                 radeon_setup_encoder_clones(dev);
 418                 radeon_print_display_setup(dev);
 419                 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
 420                         radeon_ddc_dump(drm_connector);
 421         }
 422
 423         return ret;
 424 }
 425
 426 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 427 {
 428         struct drm_device *dev = radeon_connector->base.dev;
 429         struct radeon_device *rdev = dev->dev_private;
 430         int ret = 0;
 431
 432         /* on hw with routers, select right port */
 433         if (radeon_connector->router.valid)
 434                 radeon_router_select_port(radeon_connector);
 435
 436         if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 437             (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
 438                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 439                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 440                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
 441                         radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
 442         }
 443         if (!radeon_connector->ddc_bus)
 444                 return -1;
 445         if (!radeon_connector->edid) {
 446                 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
 447         }
 448         /* some servers provide a hardcoded edid in rom for KVMs */
 449         if (!radeon_connector->edid)
 450                 radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev);
 451         if (radeon_connector->edid) {
 452                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 453                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 454                 return ret;
 455         }
 456         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 457         return 0;
 458 }
 459
 460 static int radeon_ddc_dump(struct drm_connector *connector)
 461 {
 462         struct edid *edid;
 463         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 464         int ret = 0;
 465
 466         /* on hw with routers, select right port */
 467         if (radeon_connector->router.valid)
 468                 radeon_router_select_port(radeon_connector);
 469
 470         if (!radeon_connector->ddc_bus)
 471                 return -1;
 472         edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
 473         if (edid) {
 474                 kfree(edid);
 475         }
 476         return ret;
 477 }
 478
 479 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
 480 {
 481         uint64_t mod;
 482
 483         n += d / 2;
 484
 485         mod = do_div(n, d);
 486         return n;
 487 }
 488
 489 void radeon_compute_pll(struct radeon_pll *pll,
 490                         uint64_t freq,
 491                         uint32_t *dot_clock_p,
 492                         uint32_t *fb_div_p,
 493                         uint32_t *frac_fb_div_p,
 494                         uint32_t *ref_div_p,
 495                         uint32_t *post_div_p)
 496 {
 497         uint32_t min_ref_div = pll->min_ref_div;
 498         uint32_t max_ref_div = pll->max_ref_div;
 499         uint32_t min_post_div = pll->min_post_div;
 500         uint32_t max_post_div = pll->max_post_div;
 501         uint32_t min_fractional_feed_div = 0;
 502         uint32_t max_fractional_feed_div = 0;
 503         uint32_t best_vco = pll->best_vco;
 504         uint32_t best_post_div = 1;
 505         uint32_t best_ref_div = 1;
 506         uint32_t best_feedback_div = 1;
 507         uint32_t best_frac_feedback_div = 0;
 508         uint32_t best_freq = -1;
 509         uint32_t best_error = 0xffffffff;
 510         uint32_t best_vco_diff = 1;
 511         uint32_t post_div;
 512         u32 pll_out_min, pll_out_max;
 513
 514         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
 515         freq = freq * 1000;
 516
 517         if (pll->flags & RADEON_PLL_IS_LCD) {
 518                 pll_out_min = pll->lcd_pll_out_min;
 519                 pll_out_max = pll->lcd_pll_out_max;
 520         } else {
 521                 pll_out_min = pll->pll_out_min;
 522                 pll_out_max = pll->pll_out_max;
 523         }
 524
 525         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 526                 min_ref_div = max_ref_div = pll->reference_div;
 527         else {
 528                 while (min_ref_div < max_ref_div-1) {
 529                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
 530                         uint32_t pll_in = pll->reference_freq / mid;
 531                         if (pll_in < pll->pll_in_min)
 532                                 max_ref_div = mid;
 533                         else if (pll_in > pll->pll_in_max)
 534                                 min_ref_div = mid;
 535                         else
 536                                 break;
 537                 }
 538         }
 539
 540         if (pll->flags & RADEON_PLL_USE_POST_DIV)
 541                 min_post_div = max_post_div = pll->post_div;
 542
 543         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 544                 min_fractional_feed_div = pll->min_frac_feedback_div;
 545                 max_fractional_feed_div = pll->max_frac_feedback_div;
 546         }
 547
 548         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
 549                 uint32_t ref_div;
 550
 551                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
 552                         continue;
 553
 554                 /* legacy radeons only have a few post_divs */
 555                 if (pll->flags & RADEON_PLL_LEGACY) {
 556                         if ((post_div == 5) ||
 557                             (post_div == 7) ||
 558                             (post_div == 9) ||
 559                             (post_div == 10) ||
 560                             (post_div == 11) ||
 561                             (post_div == 13) ||
 562                             (post_div == 14) ||
 563                             (post_div == 15))
 564                                 continue;
 565                 }
 566
 567                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
 568                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
 569                         uint32_t pll_in = pll->reference_freq / ref_div;
 570                         uint32_t min_feed_div = pll->min_feedback_div;
 571                         uint32_t max_feed_div = pll->max_feedback_div + 1;
 572
 573                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
 574                                 continue;
 575
 576                         while (min_feed_div < max_feed_div) {
 577                                 uint32_t vco;
 578                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
 579                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
 580                                 uint32_t frac_feedback_div;
 581                                 uint64_t tmp;
 582
 583                                 feedback_div = (min_feed_div + max_feed_div) / 2;
 584
 585                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
 586                                 vco = radeon_div(tmp, ref_div);
 587
 588                                 if (vco < pll_out_min) {
 589                                         min_feed_div = feedback_div + 1;
 590                                         continue;
 591                                 } else if (vco > pll_out_max) {
 592                                         max_feed_div = feedback_div;
 593                                         continue;
 594                                 }
 595
 596                                 while (min_frac_feed_div < max_frac_feed_div) {
 597                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
 598                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
 599                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
 600                                         current_freq = radeon_div(tmp, ref_div * post_div);
 601
 602                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
 603                                                 if (freq < current_freq)
 604                                                         error = 0xffffffff;
 605                                                 else
 606                                                         error = freq - current_freq;
 607                                         } else
 608                                                 error = abs(current_freq - freq);
 609                                         vco_diff = abs(vco - best_vco);
 610
 611                                         if ((best_vco == 0 && error < best_error) ||
 612                                             (best_vco != 0 &&
 613                                              ((best_error > 100 && error < best_error - 100) ||
 614                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
 615                                                 best_post_div = post_div;
 616                                                 best_ref_div = ref_div;
 617                                                 best_feedback_div = feedback_div;
 618                                                 best_frac_feedback_div = frac_feedback_div;
 619                                                 best_freq = current_freq;
 620                                                 best_error = error;
 621                                                 best_vco_diff = vco_diff;
 622                                         } else if (current_freq == freq) {
 623                                                 if (best_freq == -1) {
 624                                                         best_post_div = post_div;
 625                                                         best_ref_div = ref_div;
 626                                                         best_feedback_div = feedback_div;
 627                                                         best_frac_feedback_div = frac_feedback_div;
 628                                                         best_freq = current_freq;
 629                                                         best_error = error;
 630                                                         best_vco_diff = vco_diff;
 631                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
 632                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
 633                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
 634                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
 635                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
 636                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
 637                                                         best_post_div = post_div;
 638                                                         best_ref_div = ref_div;
 639                                                         best_feedback_div = feedback_div;
 640                                                         best_frac_feedback_div = frac_feedback_div;
 641                                                         best_freq = current_freq;
 642                                                         best_error = error;
 643                                                         best_vco_diff = vco_diff;
 644                                                 }
 645                                         }
 646                                         if (current_freq < freq)
 647                                                 min_frac_feed_div = frac_feedback_div + 1;
 648                                         else
 649                                                 max_frac_feed_div = frac_feedback_div;
 650                                 }
 651                                 if (current_freq < freq)
 652                                         min_feed_div = feedback_div + 1;
 653                                 else
 654                                         max_feed_div = feedback_div;
 655                         }
 656                 }
 657         }
 658
 659         *dot_clock_p = best_freq / 10000;
 660         *fb_div_p = best_feedback_div;
 661         *frac_fb_div_p = best_frac_feedback_div;
 662         *ref_div_p = best_ref_div;
 663         *post_div_p = best_post_div;
 664 }
 665
 666 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
 667 {
 668         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
 669
 670         if (radeon_fb->obj) {
 671                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
 672         }
 673         drm_framebuffer_cleanup(fb);
 674         kfree(radeon_fb);
 675 }
 676
 677 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
 678                                                   struct drm_file *file_priv,
 679                                                   unsigned int *handle)
 680 {
 681         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
 682
 683         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
 684 }
 685
 686 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
 687         .destroy = radeon_user_framebuffer_destroy,
 688         .create_handle = radeon_user_framebuffer_create_handle,
 689 };
 690
 691 void
 692 radeon_framebuffer_init(struct drm_device *dev,
 693                         struct radeon_framebuffer *rfb,
 694                         struct drm_mode_fb_cmd *mode_cmd,
 695                         struct drm_gem_object *obj)
 696 {
 697         rfb->obj = obj;
 698         drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
 699         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
 700 }
 701
 702 static struct drm_framebuffer *
 703 radeon_user_framebuffer_create(struct drm_device *dev,
 704                                struct drm_file *file_priv,
 705                                struct drm_mode_fb_cmd *mode_cmd)
 706 {
 707         struct drm_gem_object *obj;
 708         struct radeon_framebuffer *radeon_fb;
 709
 710         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
 711         if (obj ==  NULL) {
 712                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
 713                         "can't create framebuffer\n", mode_cmd->handle);
 714                 return ERR_PTR(-ENOENT);
 715         }
 716
 717         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
 718         if (radeon_fb == NULL)
 719                 return ERR_PTR(-ENOMEM);
 720
 721         radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
 722
 723         return &radeon_fb->base;
 724 }
 725
 726 static void radeon_output_poll_changed(struct drm_device *dev)
 727 {
 728         struct radeon_device *rdev = dev->dev_private;
 729         radeon_fb_output_poll_changed(rdev);
 730 }
 731
 732 static const struct drm_mode_config_funcs radeon_mode_funcs = {
 733         .fb_create = radeon_user_framebuffer_create,
 734         .output_poll_changed = radeon_output_poll_changed
 735 };
 736
 737 struct drm_prop_enum_list {
 738         int type;
 739         char *name;
 740 };
 741
 742 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
 743 {       { 0, "driver" },
 744         { 1, "bios" },
 745 };
 746
 747 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
 748 {       { TV_STD_NTSC, "ntsc" },
 749         { TV_STD_PAL, "pal" },
 750         { TV_STD_PAL_M, "pal-m" },
 751         { TV_STD_PAL_60, "pal-60" },
 752         { TV_STD_NTSC_J, "ntsc-j" },
 753         { TV_STD_SCART_PAL, "scart-pal" },
 754         { TV_STD_PAL_CN, "pal-cn" },
 755         { TV_STD_SECAM, "secam" },
 756 };
 757
 758 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
 759 {       { UNDERSCAN_OFF, "off" },
 760         { UNDERSCAN_ON, "on" },
 761         { UNDERSCAN_AUTO, "auto" },
 762 };
 763
 764 static int radeon_modeset_create_props(struct radeon_device *rdev)
 765 {
 766         int i, sz;
 767
 768         if (rdev->is_atom_bios) {
 769                 rdev->mode_info.coherent_mode_property =
 770                         drm_property_create(rdev->ddev,
 771                                             DRM_MODE_PROP_RANGE,
 772                                             "coherent", 2);
 773                 if (!rdev->mode_info.coherent_mode_property)
 774                         return -ENOMEM;
 775
 776                 rdev->mode_info.coherent_mode_property->values[0] = 0;
 777                 rdev->mode_info.coherent_mode_property->values[1] = 1;
 778         }
 779
 780         if (!ASIC_IS_AVIVO(rdev)) {
 781                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
 782                 rdev->mode_info.tmds_pll_property =
 783                         drm_property_create(rdev->ddev,
 784                                             DRM_MODE_PROP_ENUM,
 785                                             "tmds_pll", sz);
 786                 for (i = 0; i < sz; i++) {
 787                         drm_property_add_enum(rdev->mode_info.tmds_pll_property,
 788                                               i,
 789                                               radeon_tmds_pll_enum_list[i].type,
 790                                               radeon_tmds_pll_enum_list[i].name);
 791                 }
 792         }
 793
 794         rdev->mode_info.load_detect_property =
 795                 drm_property_create(rdev->ddev,
 796                                     DRM_MODE_PROP_RANGE,
 797                                     "load detection", 2);
 798         if (!rdev->mode_info.load_detect_property)
 799                 return -ENOMEM;
 800         rdev->mode_info.load_detect_property->values[0] = 0;
 801         rdev->mode_info.load_detect_property->values[1] = 1;
 802
 803         drm_mode_create_scaling_mode_property(rdev->ddev);
 804
 805         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
 806         rdev->mode_info.tv_std_property =
 807                 drm_property_create(rdev->ddev,
 808                                     DRM_MODE_PROP_ENUM,
 809                                     "tv standard", sz);
 810         for (i = 0; i < sz; i++) {
 811                 drm_property_add_enum(rdev->mode_info.tv_std_property,
 812                                       i,
 813                                       radeon_tv_std_enum_list[i].type,
 814                                       radeon_tv_std_enum_list[i].name);
 815         }
 816
 817         sz = ARRAY_SIZE(radeon_underscan_enum_list);
 818         rdev->mode_info.underscan_property =
 819                 drm_property_create(rdev->ddev,
 820                                     DRM_MODE_PROP_ENUM,
 821                                     "underscan", sz);
 822         for (i = 0; i < sz; i++) {
 823                 drm_property_add_enum(rdev->mode_info.underscan_property,
 824                                       i,
 825                                       radeon_underscan_enum_list[i].type,
 826                                       radeon_underscan_enum_list[i].name);
 827         }
 828
 829         rdev->mode_info.underscan_hborder_property =
 830                 drm_property_create(rdev->ddev,
 831                                         DRM_MODE_PROP_RANGE,
 832                                         "underscan hborder", 2);
 833         if (!rdev->mode_info.underscan_hborder_property)
 834                 return -ENOMEM;
 835         rdev->mode_info.underscan_hborder_property->values[0] = 0;
 836         rdev->mode_info.underscan_hborder_property->values[1] = 128;
 837
 838         rdev->mode_info.underscan_vborder_property =
 839                 drm_property_create(rdev->ddev,
 840                                         DRM_MODE_PROP_RANGE,
 841                                         "underscan vborder", 2);
 842         if (!rdev->mode_info.underscan_vborder_property)
 843                 return -ENOMEM;
 844         rdev->mode_info.underscan_vborder_property->values[0] = 0;
 845         rdev->mode_info.underscan_vborder_property->values[1] = 128;
 846
 847         return 0;
 848 }
 849
 850 void radeon_update_display_priority(struct radeon_device *rdev)
 851 {
 852         /* adjustment options for the display watermarks */
 853         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
 854                 /* set display priority to high for r3xx, rv515 chips
 855                  * this avoids flickering due to underflow to the
 856                  * display controllers during heavy acceleration.
 857                  * Don't force high on rs4xx igp chips as it seems to
 858                  * affect the sound card.  See kernel bug 15982.
 859                  */
 860                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
 861                     !(rdev->flags & RADEON_IS_IGP))
 862                         rdev->disp_priority = 2;
 863                 else
 864                         rdev->disp_priority = 0;
 865         } else
 866                 rdev->disp_priority = radeon_disp_priority;
 867
 868 }
 869
 870 int radeon_modeset_init(struct radeon_device *rdev)
 871 {
 872         int i;
 873         int ret;
 874
 875         drm_mode_config_init(rdev->ddev);
 876         rdev->mode_info.mode_config_initialized = true;
 877
 878         rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
 879
 880         if (ASIC_IS_AVIVO(rdev)) {
 881                 rdev->ddev->mode_config.max_width = 8192;
 882                 rdev->ddev->mode_config.max_height = 8192;
 883         } else {
 884                 rdev->ddev->mode_config.max_width = 4096;
 885                 rdev->ddev->mode_config.max_height = 4096;
 886         }
 887
 888         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
 889
 890         ret = radeon_modeset_create_props(rdev);
 891         if (ret) {
 892                 return ret;
 893         }
 894
 895         /* init i2c buses */
 896         radeon_i2c_init(rdev);
 897
 898         /* check combios for a valid hardcoded EDID - Sun servers */
 899         if (!rdev->is_atom_bios) {
 900                 /* check for hardcoded EDID in BIOS */
 901                 radeon_combios_check_hardcoded_edid(rdev);
 902         }
 903
 904         /* allocate crtcs */
 905         for (i = 0; i < rdev->num_crtc; i++) {
 906                 radeon_crtc_init(rdev->ddev, i);
 907         }
 908
 909         /* okay we should have all the bios connectors */
 910         ret = radeon_setup_enc_conn(rdev->ddev);
 911         if (!ret) {
 912                 return ret;
 913         }
 914         /* initialize hpd */
 915         radeon_hpd_init(rdev);
 916
 917         /* Initialize power management */
 918         radeon_pm_init(rdev);
 919
 920         radeon_fbdev_init(rdev);
 921         drm_kms_helper_poll_init(rdev->ddev);
 922
 923         return 0;
 924 }
 925
 926 void radeon_modeset_fini(struct radeon_device *rdev)
 927 {
 928         radeon_fbdev_fini(rdev);
 929         kfree(rdev->mode_info.bios_hardcoded_edid);
 930         radeon_pm_fini(rdev);
 931
 932         if (rdev->mode_info.mode_config_initialized) {
 933                 drm_kms_helper_poll_fini(rdev->ddev);
 934                 radeon_hpd_fini(rdev);
 935                 drm_mode_config_cleanup(rdev->ddev);
 936                 rdev->mode_info.mode_config_initialized = false;
 937         }
 938         /* free i2c buses */
 939         radeon_i2c_fini(rdev);
 940 }
 941
 942 static bool is_hdtv_mode(struct drm_display_mode *mode)
 943 {
 944         /* try and guess if this is a tv or a monitor */
 945         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
 946             (mode->vdisplay == 576) || /* 576p */
 947             (mode->vdisplay == 720) || /* 720p */
 948             (mode->vdisplay == 1080)) /* 1080p */
 949                 return true;
 950         else
 951                 return false;
 952 }
 953
 954 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
 955                                 struct drm_display_mode *mode,
 956                                 struct drm_display_mode *adjusted_mode)
 957 {
 958         struct drm_device *dev = crtc->dev;
 959         struct radeon_device *rdev = dev->dev_private;
 960         struct drm_encoder *encoder;
 961         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 962         struct radeon_encoder *radeon_encoder;
 963         struct drm_connector *connector;
 964         struct radeon_connector *radeon_connector;
 965         bool first = true;
 966         u32 src_v = 1, dst_v = 1;
 967         u32 src_h = 1, dst_h = 1;
 968
 969         radeon_crtc->h_border = 0;
 970         radeon_crtc->v_border = 0;
 971
 972         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 973                 if (encoder->crtc != crtc)
 974                         continue;
 975                 radeon_encoder = to_radeon_encoder(encoder);
 976                 connector = radeon_get_connector_for_encoder(encoder);
 977                 radeon_connector = to_radeon_connector(connector);
 978
 979                 if (first) {
 980                         /* set scaling */
 981                         if (radeon_encoder->rmx_type == RMX_OFF)
 982                                 radeon_crtc->rmx_type = RMX_OFF;
 983                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
 984                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
 985                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
 986                         else
 987                                 radeon_crtc->rmx_type = RMX_OFF;
 988                         /* copy native mode */
 989                         memcpy(&radeon_crtc->native_mode,
 990                                &radeon_encoder->native_mode,
 991                                 sizeof(struct drm_display_mode));
 992                         src_v = crtc->mode.vdisplay;
 993                         dst_v = radeon_crtc->native_mode.vdisplay;
 994                         src_h = crtc->mode.hdisplay;
 995                         dst_h = radeon_crtc->native_mode.hdisplay;
 996
 997                         /* fix up for overscan on hdmi */
 998                         if (ASIC_IS_AVIVO(rdev) &&
 999                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1000                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1001                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1002                               drm_detect_hdmi_monitor(radeon_connector->edid) &&
1003                               is_hdtv_mode(mode)))) {
1004                                 if (radeon_encoder->underscan_hborder != 0)
1005                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1006                                 else
1007                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1008                                 if (radeon_encoder->underscan_vborder != 0)
1009                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1010                                 else
1011                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1012                                 radeon_crtc->rmx_type = RMX_FULL;
1013                                 src_v = crtc->mode.vdisplay;
1014                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1015                                 src_h = crtc->mode.hdisplay;
1016                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1017                         }
1018                         first = false;
1019                 } else {
1020                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1021                                 /* WARNING: Right now this can't happen but
1022                                  * in the future we need to check that scaling
1023                                  * are consistent across different encoder
1024                                  * (ie all encoder can work with the same
1025                                  *  scaling).
1026                                  */
1027                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1028                                 return false;
1029                         }
1030                 }
1031         }
1032         if (radeon_crtc->rmx_type != RMX_OFF) {
1033                 fixed20_12 a, b;
1034                 a.full = dfixed_const(src_v);
1035                 b.full = dfixed_const(dst_v);
1036                 radeon_crtc->vsc.full = dfixed_div(a, b);
1037                 a.full = dfixed_const(src_h);
1038                 b.full = dfixed_const(dst_h);
1039                 radeon_crtc->hsc.full = dfixed_div(a, b);
1040         } else {
1041                 radeon_crtc->vsc.full = dfixed_const(1);
1042                 radeon_crtc->hsc.full = dfixed_const(1);
1043         }
1044         return true;
1045 }
1046
1047 /*
1048  * Retrieve current video scanout position of crtc on a given gpu.
1049  *
1050  * \param rdev Device to query.
1051  * \param crtc Crtc to query.
1052  * \param *vpos Location where vertical scanout position should be stored.
1053  * \param *hpos Location where horizontal scanout position should go.
1054  *
1055  * Returns vpos as a positive number while in active scanout area.
1056  * Returns vpos as a negative number inside vblank, counting the number
1057  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1058  * until start of active scanout / end of vblank."
1059  *
1060  * \return Flags, or'ed together as follows:
1061  *
1062  * RADEON_SCANOUTPOS_VALID = Query successfull.
1063  * RADEON_SCANOUTPOS_INVBL = Inside vblank.
1064  * RADEON_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1065  * this flag means that returned position may be offset by a constant but
1066  * unknown small number of scanlines wrt. real scanout position.
1067  *
1068  */
1069 int radeon_get_crtc_scanoutpos(struct radeon_device *rdev, int crtc, int *vpos, int *hpos)
1070 {
1071         u32 stat_crtc = 0, vbl = 0, position = 0;
1072         int vbl_start, vbl_end, vtotal, ret = 0;
1073         bool in_vbl = true;
1074
1075         if (ASIC_IS_DCE4(rdev)) {
1076                 if (crtc == 0) {
1077                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1078                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1079                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1080                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1081                         ret |= RADEON_SCANOUTPOS_VALID;
1082                 }
1083                 if (crtc == 1) {
1084                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1085                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1086                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1087                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1088                         ret |= RADEON_SCANOUTPOS_VALID;
1089                 }
1090                 if (crtc == 2) {
1091                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1092                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1093                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1094                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1095                         ret |= RADEON_SCANOUTPOS_VALID;
1096                 }
1097                 if (crtc == 3) {
1098                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1099                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1100                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1101                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1102                         ret |= RADEON_SCANOUTPOS_VALID;
1103                 }
1104                 if (crtc == 4) {
1105                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1106                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1107                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1108                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1109                         ret |= RADEON_SCANOUTPOS_VALID;
1110                 }
1111                 if (crtc == 5) {
1112                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1113                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1114                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1115                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1116                         ret |= RADEON_SCANOUTPOS_VALID;
1117                 }
1118         } else if (ASIC_IS_AVIVO(rdev)) {
1119                 if (crtc == 0) {
1120                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1121                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1122                         ret |= RADEON_SCANOUTPOS_VALID;
1123                 }
1124                 if (crtc == 1) {
1125                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1126                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1127                         ret |= RADEON_SCANOUTPOS_VALID;
1128                 }
1129         } else {
1130                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1131                 if (crtc == 0) {
1132                         /* Assume vbl_end == 0, get vbl_start from
1133                          * upper 16 bits.
1134                          */
1135                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1136                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1137                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1138                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1139                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1140                         if (!(stat_crtc & 1))
1141                                 in_vbl = false;
1142
1143                         ret |= RADEON_SCANOUTPOS_VALID;
1144                 }
1145                 if (crtc == 1) {
1146                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1147                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1148                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1149                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1150                         if (!(stat_crtc & 1))
1151                                 in_vbl = false;
1152
1153                         ret |= RADEON_SCANOUTPOS_VALID;
1154                 }
1155         }
1156
1157         /* Decode into vertical and horizontal scanout position. */
1158         *vpos = position & 0x1fff;
1159         *hpos = (position >> 16) & 0x1fff;
1160
1161         /* Valid vblank area boundaries from gpu retrieved? */
1162         if (vbl > 0) {
1163                 /* Yes: Decode. */
1164                 ret |= RADEON_SCANOUTPOS_ACCURATE;
1165                 vbl_start = vbl & 0x1fff;
1166                 vbl_end = (vbl >> 16) & 0x1fff;
1167         }
1168         else {
1169                 /* No: Fake something reasonable which gives at least ok results. */
1170                 vbl_start = rdev->mode_info.crtcs[crtc]->base.mode.crtc_vdisplay;
1171                 vbl_end = 0;
1172         }
1173
1174         /* Test scanout position against vblank region. */
1175         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1176                 in_vbl = false;
1177
1178         /* Check if inside vblank area and apply corrective offsets:
1179          * vpos will then be >=0 in video scanout area, but negative
1180          * within vblank area, counting down the number of lines until
1181          * start of scanout.
1182          */
1183
1184         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1185         if (in_vbl && (*vpos >= vbl_start)) {
1186                 vtotal = rdev->mode_info.crtcs[crtc]->base.mode.crtc_vtotal;
1187                 *vpos = *vpos - vtotal;
1188         }
1189
1190         /* Correct for shifted end of vbl at vbl_end. */
1191         *vpos = *vpos - vbl_end;
1192
1193         /* In vblank? */
1194         if (in_vbl)
1195                 ret |= RADEON_SCANOUTPOS_INVBL;
1196
1197         return ret;
1198 }