]> git.karo-electronics.de Git - mv-sheeva.git/commitdiff
Revert "drm/radeon/kms: remove some pll algo flags"
authorDave Airlie <airlied@redhat.com>
Tue, 19 Oct 2010 00:36:47 +0000 (10:36 +1000)
committerDave Airlie <airlied@redhat.com>
Tue, 19 Oct 2010 04:12:22 +0000 (14:12 +1000)
This reverts commit f28488c282d8916b9b6190cc41714815bbaf97d5.

On my rv610 test machine the monitor failed to light up after this.

Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/radeon/atombios_crtc.c
drivers/gpu/drm/radeon/radeon_display.c
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
drivers/gpu/drm/radeon/radeon_mode.h

index 037e3260cb7c786cd9891866932e65679ba30d5e..176f424975ac291f296b871a970e803e82171fc1 100644 (file)
@@ -501,9 +501,21 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                    (rdev->family == CHIP_RS740))
                        pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
                                       RADEON_PLL_PREFER_CLOSEST_LOWER);
-       } else
+
+               if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
+                       pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
+               else
+                       pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
+       } else {
                pll->flags |= RADEON_PLL_LEGACY;
 
+               if (mode->clock > 200000)       /* range limits??? */
+                       pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
+               else
+                       pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
+
+       }
+
        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
                if (encoder->crtc == crtc) {
                        radeon_encoder = to_radeon_encoder(encoder);
index 6c6846cdaa3020cf95f33cb48d666917947b9404..9151ded9c1cda626a340ebe67cba757b74b6694a 100644 (file)
@@ -611,8 +611,7 @@ void radeon_compute_pll(struct radeon_pll *pll,
                                        if ((best_vco == 0 && error < best_error) ||
                                            (best_vco != 0 &&
                                             ((best_error > 100 && error < best_error - 100) ||
-                                             (abs(error - best_error) < 100 &&
-                                              vco_diff < best_vco_diff)))) {
+                                             (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
                                                best_post_div = post_div;
                                                best_ref_div = ref_div;
                                                best_feedback_div = feedback_div;
@@ -620,6 +619,29 @@ void radeon_compute_pll(struct radeon_pll *pll,
                                                best_freq = current_freq;
                                                best_error = error;
                                                best_vco_diff = vco_diff;
+                                       } else if (current_freq == freq) {
+                                               if (best_freq == -1) {
+                                                       best_post_div = post_div;
+                                                       best_ref_div = ref_div;
+                                                       best_feedback_div = feedback_div;
+                                                       best_frac_feedback_div = frac_feedback_div;
+                                                       best_freq = current_freq;
+                                                       best_error = error;
+                                                       best_vco_diff = vco_diff;
+                                               } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
+                                                          ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
+                                                          ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
+                                                          ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
+                                                          ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
+                                                          ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
+                                                       best_post_div = post_div;
+                                                       best_ref_div = ref_div;
+                                                       best_feedback_div = feedback_div;
+                                                       best_frac_feedback_div = frac_feedback_div;
+                                                       best_freq = current_freq;
+                                                       best_error = error;
+                                                       best_vco_diff = vco_diff;
+                                               }
                                        }
                                        if (current_freq < freq)
                                                min_frac_feed_div = frac_feedback_div + 1;
index c0bf8b7cc56c97d92808243ff176b88ac573d9b0..f8dae717acc8e53ee09042fe43e1500ed4272dbb 100644 (file)
@@ -745,6 +745,11 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 
        pll->flags = RADEON_PLL_LEGACY;
 
+       if (mode->clock > 200000) /* range limits??? */
+               pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
+       else
+               pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
+
        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
                if (encoder->crtc == crtc) {
                        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
index 3cda63e37b28d0c18b76c6b3bb866755943310a3..d58b003e9a041196fe82aa5d0fb94fb9927907a2 100644 (file)
@@ -139,10 +139,16 @@ struct radeon_tmds_pll {
 #define RADEON_PLL_NO_ODD_POST_DIV      (1 << 1)
 #define RADEON_PLL_USE_REF_DIV          (1 << 2)
 #define RADEON_PLL_LEGACY               (1 << 3)
-#define RADEON_PLL_USE_FRAC_FB_DIV      (1 << 4)
-#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 5)
-#define RADEON_PLL_USE_POST_DIV         (1 << 6)
-#define RADEON_PLL_IS_LCD               (1 << 7)
+#define RADEON_PLL_PREFER_LOW_REF_DIV   (1 << 4)
+#define RADEON_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
+#define RADEON_PLL_PREFER_LOW_FB_DIV    (1 << 6)
+#define RADEON_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
+#define RADEON_PLL_PREFER_LOW_POST_DIV  (1 << 8)
+#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
+#define RADEON_PLL_USE_FRAC_FB_DIV      (1 << 10)
+#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
+#define RADEON_PLL_USE_POST_DIV         (1 << 12)
+#define RADEON_PLL_IS_LCD               (1 << 13)
 
 struct radeon_pll {
        /* reference frequency */