drivers/gpu/drm/radeon/radeon_legacy_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include <drm/drm_fixed.h>
  30 #include "radeon.h"
  31 #include "atom.h"
  32
  33 static void radeon_overscan_setup(struct drm_crtc *crtc,
  34                                   struct drm_display_mode *mode)
  35 {
  36         struct drm_device *dev = crtc->dev;
  37         struct radeon_device *rdev = dev->dev_private;
  38         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  39
  40         WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
  41         WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
  42         WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
  43 }
  44
  45 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
  46                                        struct drm_display_mode *mode)
  47 {
  48         struct drm_device *dev = crtc->dev;
  49         struct radeon_device *rdev = dev->dev_private;
  50         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  51         int xres = mode->hdisplay;
  52         int yres = mode->vdisplay;
  53         bool hscale = true, vscale = true;
  54         int hsync_wid;
  55         int vsync_wid;
  56         int hsync_start;
  57         int blank_width;
  58         u32 scale, inc, crtc_more_cntl;
  59         u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
  60         u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
  61         u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
  62         struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
  63
  64         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
  65                 (RADEON_VERT_STRETCH_RESERVED |
  66                  RADEON_VERT_AUTO_RATIO_INC);
  67         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
  68                 (RADEON_HORZ_FP_LOOP_STRETCH |
  69                  RADEON_HORZ_AUTO_RATIO_INC);
  70
  71         crtc_more_cntl = 0;
  72         if ((rdev->family == CHIP_RS100) ||
  73             (rdev->family == CHIP_RS200)) {
  74                 /* This is to workaround the asic bug for RMX, some versions
  75                    of BIOS dosen't have this register initialized correctly. */
  76                 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
  77         }
  78
  79
  80         fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
  81                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
  82
  83         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
  84         if (!hsync_wid)
  85                 hsync_wid = 1;
  86         hsync_start = mode->crtc_hsync_start - 8;
  87
  88         fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
  89                               | ((hsync_wid & 0x3f) << 16)
  90                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
  91                                  ? RADEON_CRTC_H_SYNC_POL
  92                                  : 0));
  93
  94         fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
  95                                 | ((mode->crtc_vdisplay - 1) << 16));
  96
  97         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
  98         if (!vsync_wid)
  99                 vsync_wid = 1;
 100
 101         fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 102                               | ((vsync_wid & 0x1f) << 16)
 103                               | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 104                                  ? RADEON_CRTC_V_SYNC_POL
 105                                  : 0));
 106
 107         fp_horz_vert_active = 0;
 108
 109         if (native_mode->hdisplay == 0 ||
 110             native_mode->vdisplay == 0) {
 111                 hscale = false;
 112                 vscale = false;
 113         } else {
 114                 if (xres > native_mode->hdisplay)
 115                         xres = native_mode->hdisplay;
 116                 if (yres > native_mode->vdisplay)
 117                         yres = native_mode->vdisplay;
 118
 119                 if (xres == native_mode->hdisplay)
 120                         hscale = false;
 121                 if (yres == native_mode->vdisplay)
 122                         vscale = false;
 123         }
 124
 125         switch (radeon_crtc->rmx_type) {
 126         case RMX_FULL:
 127         case RMX_ASPECT:
 128                 if (!hscale)
 129                         fp_horz_stretch |= ((xres/8-1) << 16);
 130                 else {
 131                         inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
 132                         scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
 133                                 / native_mode->hdisplay + 1;
 134                         fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
 135                                         RADEON_HORZ_STRETCH_BLEND |
 136                                         RADEON_HORZ_STRETCH_ENABLE |
 137                                         ((native_mode->hdisplay/8-1) << 16));
 138                 }
 139
 140                 if (!vscale)
 141                         fp_vert_stretch |= ((yres-1) << 12);
 142                 else {
 143                         inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
 144                         scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
 145                                 / native_mode->vdisplay + 1;
 146                         fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
 147                                         RADEON_VERT_STRETCH_ENABLE |
 148                                         RADEON_VERT_STRETCH_BLEND |
 149                                         ((native_mode->vdisplay-1) << 12));
 150                 }
 151                 break;
 152         case RMX_CENTER:
 153                 fp_horz_stretch |= ((xres/8-1) << 16);
 154                 fp_vert_stretch |= ((yres-1) << 12);
 155
 156                 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
 157                                 RADEON_CRTC_AUTO_VERT_CENTER_EN);
 158
 159                 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
 160                 if (blank_width > 110)
 161                         blank_width = 110;
 162
 163                 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
 164                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 165
 166                 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 167                 if (!hsync_wid)
 168                         hsync_wid = 1;
 169
 170                 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
 171                                 | ((hsync_wid & 0x3f) << 16)
 172                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 173                                         ? RADEON_CRTC_H_SYNC_POL
 174                                         : 0));
 175
 176                 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
 177                                 | ((mode->crtc_vdisplay - 1) << 16));
 178
 179                 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 180                 if (!vsync_wid)
 181                         vsync_wid = 1;
 182
 183                 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
 184                                         | ((vsync_wid & 0x1f) << 16)
 185                                         | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 186                                                 ? RADEON_CRTC_V_SYNC_POL
 187                                                 : 0)));
 188
 189                 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
 190                                 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
 191                 break;
 192         case RMX_OFF:
 193         default:
 194                 fp_horz_stretch |= ((xres/8-1) << 16);
 195                 fp_vert_stretch |= ((yres-1) << 12);
 196                 break;
 197         }
 198
 199         WREG32(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
 200         WREG32(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
 201         WREG32(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
 202         WREG32(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
 203         WREG32(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
 204         WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
 205         WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
 206         WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
 207 }
 208
 209 void radeon_restore_common_regs(struct drm_device *dev)
 210 {
 211         /* don't need this yet */
 212 }
 213
 214 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
 215 {
 216         struct radeon_device *rdev = dev->dev_private;
 217         int i = 0;
 218
 219         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 220            the cause yet, but this workaround will mask the problem for now.
 221            Other chips usually will pass at the very first test, so the
 222            workaround shouldn't have any effect on them. */
 223         for (i = 0;
 224              (i < 10000 &&
 225               RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 226              i++);
 227 }
 228
 229 static void radeon_pll_write_update(struct drm_device *dev)
 230 {
 231         struct radeon_device *rdev = dev->dev_private;
 232
 233         while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 234
 235         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 236                            RADEON_PPLL_ATOMIC_UPDATE_W,
 237                            ~(RADEON_PPLL_ATOMIC_UPDATE_W));
 238 }
 239
 240 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
 241 {
 242         struct radeon_device *rdev = dev->dev_private;
 243         int i = 0;
 244
 245
 246         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 247            the cause yet, but this workaround will mask the problem for now.
 248            Other chips usually will pass at the very first test, so the
 249            workaround shouldn't have any effect on them. */
 250         for (i = 0;
 251              (i < 10000 &&
 252               RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 253              i++);
 254 }
 255
 256 static void radeon_pll2_write_update(struct drm_device *dev)
 257 {
 258         struct radeon_device *rdev = dev->dev_private;
 259
 260         while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 261
 262         WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 263                            RADEON_P2PLL_ATOMIC_UPDATE_W,
 264                            ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
 265 }
 266
 267 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
 268                                        uint16_t fb_div)
 269 {
 270         unsigned int vcoFreq;
 271
 272         if (!ref_div)
 273                 return 1;
 274
 275         vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
 276
 277         /*
 278          * This is horribly crude: the VCO frequency range is divided into
 279          * 3 parts, each part having a fixed PLL gain value.
 280          */
 281         if (vcoFreq >= 30000)
 282                 /*
 283                  * [300..max] MHz : 7
 284                  */
 285                 return 7;
 286         else if (vcoFreq >= 18000)
 287                 /*
 288                  * [180..300) MHz : 4
 289                  */
 290                 return 4;
 291         else
 292                 /*
 293                  * [0..180) MHz : 1
 294                  */
 295                 return 1;
 296 }
 297
 298 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 299 {
 300         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 301         struct drm_device *dev = crtc->dev;
 302         struct radeon_device *rdev = dev->dev_private;
 303         uint32_t mask;
 304
 305         if (radeon_crtc->crtc_id)
 306                 mask = (RADEON_CRTC2_DISP_DIS |
 307                         RADEON_CRTC2_VSYNC_DIS |
 308                         RADEON_CRTC2_HSYNC_DIS |
 309                         RADEON_CRTC2_DISP_REQ_EN_B);
 310         else
 311                 mask = (RADEON_CRTC_DISPLAY_DIS |
 312                         RADEON_CRTC_VSYNC_DIS |
 313                         RADEON_CRTC_HSYNC_DIS);
 314
 315         switch (mode) {
 316         case DRM_MODE_DPMS_ON:
 317                 radeon_crtc->enabled = true;
 318                 /* adjust pm to dpms changes BEFORE enabling crtcs */
 319                 radeon_pm_compute_clocks(rdev);
 320                 if (radeon_crtc->crtc_id)
 321                         WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
 322                 else {
 323                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
 324                                                                          RADEON_CRTC_DISP_REQ_EN_B));
 325                         WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
 326                 }
 327                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 328                 radeon_crtc_load_lut(crtc);
 329                 break;
 330         case DRM_MODE_DPMS_STANDBY:
 331         case DRM_MODE_DPMS_SUSPEND:
 332         case DRM_MODE_DPMS_OFF:
 333                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 334                 if (radeon_crtc->crtc_id)
 335                         WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
 336                 else {
 337                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
 338                                                                                     RADEON_CRTC_DISP_REQ_EN_B));
 339                         WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
 340                 }
 341                 radeon_crtc->enabled = false;
 342                 /* adjust pm to dpms changes AFTER disabling crtcs */
 343                 radeon_pm_compute_clocks(rdev);
 344                 break;
 345         }
 346 }
 347
 348 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 349                          struct drm_framebuffer *old_fb)
 350 {
 351         return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
 352 }
 353
 354 int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
 355                                 struct drm_framebuffer *fb,
 356                                 int x, int y, int enter)
 357 {
 358         if (enter)
 359                 radeon_crtc_save_lut(crtc);
 360         else
 361                 radeon_crtc_restore_lut(crtc);
 362
 363         return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
 364 }
 365
 366 int radeon_crtc_do_set_base(struct drm_crtc *crtc,
 367                          struct drm_framebuffer *fb,
 368                          int x, int y, int atomic)
 369 {
 370         struct drm_device *dev = crtc->dev;
 371         struct radeon_device *rdev = dev->dev_private;
 372         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 373         struct radeon_framebuffer *radeon_fb;
 374         struct drm_framebuffer *target_fb;
 375         struct drm_gem_object *obj;
 376         struct radeon_bo *rbo;
 377         uint64_t base;
 378         uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
 379         uint32_t crtc_pitch, pitch_pixels;
 380         uint32_t tiling_flags;
 381         int format;
 382         uint32_t gen_cntl_reg, gen_cntl_val;
 383         int r;
 384
 385         DRM_DEBUG_KMS("\n");
 386         /* no fb bound */
 387         if (!atomic && !crtc->fb) {
 388                 DRM_DEBUG_KMS("No FB bound\n");
 389                 return 0;
 390         }
 391
 392         if (atomic) {
 393                 radeon_fb = to_radeon_framebuffer(fb);
 394                 target_fb = fb;
 395         }
 396         else {
 397                 radeon_fb = to_radeon_framebuffer(crtc->fb);
 398                 target_fb = crtc->fb;
 399         }
 400
 401         switch (target_fb->bits_per_pixel) {
 402         case 8:
 403                 format = 2;
 404                 break;
 405         case 15:      /*  555 */
 406                 format = 3;
 407                 break;
 408         case 16:      /*  565 */
 409                 format = 4;
 410                 break;
 411         case 24:      /*  RGB */
 412                 format = 5;
 413                 break;
 414         case 32:      /* xRGB */
 415                 format = 6;
 416                 break;
 417         default:
 418                 return false;
 419         }
 420
 421         /* Pin framebuffer & get tilling informations */
 422         obj = radeon_fb->obj;
 423         rbo = obj->driver_private;
 424         r = radeon_bo_reserve(rbo, false);
 425         if (unlikely(r != 0))
 426                 return r;
 427         r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
 428         if (unlikely(r != 0)) {
 429                 radeon_bo_unreserve(rbo);
 430                 return -EINVAL;
 431         }
 432         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 433         radeon_bo_unreserve(rbo);
 434         if (tiling_flags & RADEON_TILING_MICRO)
 435                 DRM_ERROR("trying to scanout microtiled buffer\n");
 436
 437         /* if scanout was in GTT this really wouldn't work */
 438         /* crtc offset is from display base addr not FB location */
 439         radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
 440
 441         base -= radeon_crtc->legacy_display_base_addr;
 442
 443         crtc_offset_cntl = 0;
 444
 445         pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
 446         crtc_pitch  = (((pitch_pixels * target_fb->bits_per_pixel) +
 447                         ((target_fb->bits_per_pixel * 8) - 1)) /
 448                        (target_fb->bits_per_pixel * 8));
 449         crtc_pitch |= crtc_pitch << 16;
 450
 451
 452         if (tiling_flags & RADEON_TILING_MACRO) {
 453                 if (ASIC_IS_R300(rdev))
 454                         crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
 455                                              R300_CRTC_MICRO_TILE_BUFFER_DIS |
 456                                              R300_CRTC_MACRO_TILE_EN);
 457                 else
 458                         crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
 459         } else {
 460                 if (ASIC_IS_R300(rdev))
 461                         crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
 462                                               R300_CRTC_MICRO_TILE_BUFFER_DIS |
 463                                               R300_CRTC_MACRO_TILE_EN);
 464                 else
 465                         crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
 466         }
 467
 468         if (tiling_flags & RADEON_TILING_MACRO) {
 469                 if (ASIC_IS_R300(rdev)) {
 470                         crtc_tile_x0_y0 = x | (y << 16);
 471                         base &= ~0x7ff;
 472                 } else {
 473                         int byteshift = target_fb->bits_per_pixel >> 4;
 474                         int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
 475                         base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
 476                         crtc_offset_cntl |= (y % 16);
 477                 }
 478         } else {
 479                 int offset = y * pitch_pixels + x;
 480                 switch (target_fb->bits_per_pixel) {
 481                 case 8:
 482                         offset *= 1;
 483                         break;
 484                 case 15:
 485                 case 16:
 486                         offset *= 2;
 487                         break;
 488                 case 24:
 489                         offset *= 3;
 490                         break;
 491                 case 32:
 492                         offset *= 4;
 493                         break;
 494                 default:
 495                         return false;
 496                 }
 497                 base += offset;
 498         }
 499
 500         base &= ~7;
 501
 502         if (radeon_crtc->crtc_id == 1)
 503                 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
 504         else
 505                 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
 506
 507         gen_cntl_val = RREG32(gen_cntl_reg);
 508         gen_cntl_val &= ~(0xf << 8);
 509         gen_cntl_val |= (format << 8);
 510         WREG32(gen_cntl_reg, gen_cntl_val);
 511
 512         crtc_offset = (u32)base;
 513
 514         WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
 515
 516         if (ASIC_IS_R300(rdev)) {
 517                 if (radeon_crtc->crtc_id)
 518                         WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
 519                 else
 520                         WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
 521         }
 522         WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
 523         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
 524         WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 525
 526         if (!atomic && fb && fb != crtc->fb) {
 527                 radeon_fb = to_radeon_framebuffer(fb);
 528                 rbo = radeon_fb->obj->driver_private;
 529                 r = radeon_bo_reserve(rbo, false);
 530                 if (unlikely(r != 0))
 531                         return r;
 532                 radeon_bo_unpin(rbo);
 533                 radeon_bo_unreserve(rbo);
 534         }
 535
 536         /* Bytes per pixel may have changed */
 537         radeon_bandwidth_update(rdev);
 538
 539         return 0;
 540 }
 541
 542 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
 543 {
 544         struct drm_device *dev = crtc->dev;
 545         struct radeon_device *rdev = dev->dev_private;
 546         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 547         struct drm_encoder *encoder;
 548         int format;
 549         int hsync_start;
 550         int hsync_wid;
 551         int vsync_wid;
 552         uint32_t crtc_h_total_disp;
 553         uint32_t crtc_h_sync_strt_wid;
 554         uint32_t crtc_v_total_disp;
 555         uint32_t crtc_v_sync_strt_wid;
 556         bool is_tv = false;
 557
 558         DRM_DEBUG_KMS("\n");
 559         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 560                 if (encoder->crtc == crtc) {
 561                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 562                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 563                                 is_tv = true;
 564                                 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
 565                                 break;
 566                         }
 567                 }
 568         }
 569
 570         switch (crtc->fb->bits_per_pixel) {
 571         case 8:
 572                 format = 2;
 573                 break;
 574         case 15:      /*  555 */
 575                 format = 3;
 576                 break;
 577         case 16:      /*  565 */
 578                 format = 4;
 579                 break;
 580         case 24:      /*  RGB */
 581                 format = 5;
 582                 break;
 583         case 32:      /* xRGB */
 584                 format = 6;
 585                 break;
 586         default:
 587                 return false;
 588         }
 589
 590         crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
 591                              | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 592
 593         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 594         if (!hsync_wid)
 595                 hsync_wid = 1;
 596         hsync_start = mode->crtc_hsync_start - 8;
 597
 598         crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
 599                                 | ((hsync_wid & 0x3f) << 16)
 600                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 601                                    ? RADEON_CRTC_H_SYNC_POL
 602                                    : 0));
 603
 604         /* This works for double scan mode. */
 605         crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
 606                              | ((mode->crtc_vdisplay - 1) << 16));
 607
 608         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 609         if (!vsync_wid)
 610                 vsync_wid = 1;
 611
 612         crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 613                                 | ((vsync_wid & 0x1f) << 16)
 614                                 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 615                                    ? RADEON_CRTC_V_SYNC_POL
 616                                    : 0));
 617
 618         if (radeon_crtc->crtc_id) {
 619                 uint32_t crtc2_gen_cntl;
 620                 uint32_t disp2_merge_cntl;
 621
 622                 /* if TV DAC is enabled for another crtc and keep it enabled */
 623                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
 624                 crtc2_gen_cntl |= ((format << 8)
 625                                    | RADEON_CRTC2_VSYNC_DIS
 626                                    | RADEON_CRTC2_HSYNC_DIS
 627                                    | RADEON_CRTC2_DISP_DIS
 628                                    | RADEON_CRTC2_DISP_REQ_EN_B
 629                                    | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 630                                       ? RADEON_CRTC2_DBL_SCAN_EN
 631                                       : 0)
 632                                    | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 633                                       ? RADEON_CRTC2_CSYNC_EN
 634                                       : 0)
 635                                    | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 636                                       ? RADEON_CRTC2_INTERLACE_EN
 637                                       : 0));
 638
 639                 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
 640                 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
 641                         crtc2_gen_cntl |= RADEON_CRTC2_EN;
 642
 643                 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
 644                 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 645
 646                 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
 647                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 648
 649                 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
 650                 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
 651         } else {
 652                 uint32_t crtc_gen_cntl;
 653                 uint32_t crtc_ext_cntl;
 654                 uint32_t disp_merge_cntl;
 655
 656                 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
 657                 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
 658                                  | (format << 8)
 659                                  | RADEON_CRTC_DISP_REQ_EN_B
 660                                  | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 661                                     ? RADEON_CRTC_DBL_SCAN_EN
 662                                     : 0)
 663                                  | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 664                                     ? RADEON_CRTC_CSYNC_EN
 665                                     : 0)
 666                                  | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 667                                     ? RADEON_CRTC_INTERLACE_EN
 668                                     : 0));
 669
 670                 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
 671                 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
 672                         crtc_gen_cntl |= RADEON_CRTC_EN;
 673
 674                 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 675                 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
 676                                   RADEON_CRTC_VSYNC_DIS |
 677                                   RADEON_CRTC_HSYNC_DIS |
 678                                   RADEON_CRTC_DISPLAY_DIS);
 679
 680                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
 681                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 682
 683                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 684                 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 685                 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 686         }
 687
 688         if (is_tv)
 689                 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
 690                                                  &crtc_h_sync_strt_wid, &crtc_v_total_disp,
 691                                                  &crtc_v_sync_strt_wid);
 692
 693         WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
 694         WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
 695         WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
 696         WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
 697
 698         return true;
 699 }
 700
 701 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 702 {
 703         struct drm_device *dev = crtc->dev;
 704         struct radeon_device *rdev = dev->dev_private;
 705         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 706         struct drm_encoder *encoder;
 707         uint32_t feedback_div = 0;
 708         uint32_t frac_fb_div = 0;
 709         uint32_t reference_div = 0;
 710         uint32_t post_divider = 0;
 711         uint32_t freq = 0;
 712         uint8_t pll_gain;
 713         bool use_bios_divs = false;
 714         /* PLL registers */
 715         uint32_t pll_ref_div = 0;
 716         uint32_t pll_fb_post_div = 0;
 717         uint32_t htotal_cntl = 0;
 718         bool is_tv = false;
 719         struct radeon_pll *pll;
 720
 721         struct {
 722                 int divider;
 723                 int bitvalue;
 724         } *post_div, post_divs[]   = {
 725                 /* From RAGE 128 VR/RAGE 128 GL Register
 726                  * Reference Manual (Technical Reference
 727                  * Manual P/N RRG-G04100-C Rev. 0.04), page
 728                  * 3-17 (PLL_DIV_[3:0]).
 729                  */
 730                 {  1, 0 },              /* VCLK_SRC                 */
 731                 {  2, 1 },              /* VCLK_SRC/2               */
 732                 {  4, 2 },              /* VCLK_SRC/4               */
 733                 {  8, 3 },              /* VCLK_SRC/8               */
 734                 {  3, 4 },              /* VCLK_SRC/3               */
 735                 { 16, 5 },              /* VCLK_SRC/16              */
 736                 {  6, 6 },              /* VCLK_SRC/6               */
 737                 { 12, 7 },              /* VCLK_SRC/12              */
 738                 {  0, 0 }
 739         };
 740
 741         if (radeon_crtc->crtc_id)
 742                 pll = &rdev->clock.p2pll;
 743         else
 744                 pll = &rdev->clock.p1pll;
 745
 746         pll->flags = RADEON_PLL_LEGACY;
 747
 748         if (mode->clock > 200000) /* range limits??? */
 749                 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 750         else
 751                 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 752
 753         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 754                 if (encoder->crtc == crtc) {
 755                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 756
 757                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 758                                 is_tv = true;
 759                                 break;
 760                         }
 761
 762                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 763                                 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
 764                         if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
 765                                 if (!rdev->is_atom_bios) {
 766                                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 767                                         struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
 768                                         if (lvds) {
 769                                                 if (lvds->use_bios_dividers) {
 770                                                         pll_ref_div = lvds->panel_ref_divider;
 771                                                         pll_fb_post_div   = (lvds->panel_fb_divider |
 772                                                                              (lvds->panel_post_divider << 16));
 773                                                         htotal_cntl  = 0;
 774                                                         use_bios_divs = true;
 775                                                 }
 776                                         }
 777                                 }
 778                                 pll->flags |= RADEON_PLL_USE_REF_DIV;
 779                         }
 780                 }
 781         }
 782
 783         DRM_DEBUG_KMS("\n");
 784
 785         if (!use_bios_divs) {
 786                 radeon_compute_pll(pll, mode->clock,
 787                                    &freq, &feedback_div, &frac_fb_div,
 788                                    &reference_div, &post_divider);
 789
 790                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 791                         if (post_div->divider == post_divider)
 792                                 break;
 793                 }
 794
 795                 if (!post_div->divider)
 796                         post_div = &post_divs[0];
 797
 798                 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n",
 799                           (unsigned)freq,
 800                           feedback_div,
 801                           reference_div,
 802                           post_divider);
 803
 804                 pll_ref_div   = reference_div;
 805 #if defined(__powerpc__) && (0) /* TODO */
 806                 /* apparently programming this otherwise causes a hang??? */
 807                 if (info->MacModel == RADEON_MAC_IBOOK)
 808                         pll_fb_post_div = 0x000600ad;
 809                 else
 810 #endif
 811                         pll_fb_post_div     = (feedback_div | (post_div->bitvalue << 16));
 812
 813                 htotal_cntl    = mode->htotal & 0x7;
 814
 815         }
 816
 817         pll_gain = radeon_compute_pll_gain(pll->reference_freq,
 818                                            pll_ref_div & 0x3ff,
 819                                            pll_fb_post_div & 0x7ff);
 820
 821         if (radeon_crtc->crtc_id) {
 822                 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
 823                                           ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
 824                                          RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
 825
 826                 if (is_tv) {
 827                         radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
 828                                                      &pll_ref_div, &pll_fb_post_div,
 829                                                      &pixclks_cntl);
 830                 }
 831
 832                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 833                              RADEON_PIX2CLK_SRC_SEL_CPUCLK,
 834                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 835
 836                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 837                              RADEON_P2PLL_RESET
 838                              | RADEON_P2PLL_ATOMIC_UPDATE_EN
 839                              | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
 840                              ~(RADEON_P2PLL_RESET
 841                                | RADEON_P2PLL_ATOMIC_UPDATE_EN
 842                                | RADEON_P2PLL_PVG_MASK));
 843
 844                 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 845                              pll_ref_div,
 846                              ~RADEON_P2PLL_REF_DIV_MASK);
 847
 848                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 849                              pll_fb_post_div,
 850                              ~RADEON_P2PLL_FB0_DIV_MASK);
 851
 852                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 853                              pll_fb_post_div,
 854                              ~RADEON_P2PLL_POST0_DIV_MASK);
 855
 856                 radeon_pll2_write_update(dev);
 857                 radeon_pll2_wait_for_read_update_complete(dev);
 858
 859                 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
 860
 861                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 862                              0,
 863                              ~(RADEON_P2PLL_RESET
 864                                | RADEON_P2PLL_SLEEP
 865                                | RADEON_P2PLL_ATOMIC_UPDATE_EN));
 866
 867                 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 868                           (unsigned)pll_ref_div,
 869                           (unsigned)pll_fb_post_div,
 870                           (unsigned)htotal_cntl,
 871                           RREG32_PLL(RADEON_P2PLL_CNTL));
 872                 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n",
 873                           (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 874                           (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
 875                           (unsigned)((pll_fb_post_div &
 876                                       RADEON_P2PLL_POST0_DIV_MASK) >> 16));
 877
 878                 mdelay(50); /* Let the clock to lock */
 879
 880                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 881                              RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
 882                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 883
 884                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 885         } else {
 886                 uint32_t pixclks_cntl;
 887
 888
 889                 if (is_tv) {
 890                         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
 891                         radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
 892                                                      &pll_fb_post_div, &pixclks_cntl);
 893                 }
 894
 895                 if (rdev->flags & RADEON_IS_MOBILITY) {
 896                         /* A temporal workaround for the occational blanking on certain laptop panels.
 897                            This appears to related to the PLL divider registers (fail to lock?).
 898                            It occurs even when all dividers are the same with their old settings.
 899                            In this case we really don't need to fiddle with PLL registers.
 900                            By doing this we can avoid the blanking problem with some panels.
 901                         */
 902                         if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
 903                             (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
 904                                                  (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
 905                                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 906                                          RADEON_PLL_DIV_SEL,
 907                                          ~(RADEON_PLL_DIV_SEL));
 908                                 r100_pll_errata_after_index(rdev);
 909                                 return;
 910                         }
 911                 }
 912
 913                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
 914                              RADEON_VCLK_SRC_SEL_CPUCLK,
 915                              ~(RADEON_VCLK_SRC_SEL_MASK));
 916                 WREG32_PLL_P(RADEON_PPLL_CNTL,
 917                              RADEON_PPLL_RESET
 918                              | RADEON_PPLL_ATOMIC_UPDATE_EN
 919                              | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 920                              | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
 921                              ~(RADEON_PPLL_RESET
 922                                | RADEON_PPLL_ATOMIC_UPDATE_EN
 923                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 924                                | RADEON_PPLL_PVG_MASK));
 925
 926                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 927                          RADEON_PLL_DIV_SEL,
 928                          ~(RADEON_PLL_DIV_SEL));
 929                 r100_pll_errata_after_index(rdev);
 930
 931                 if (ASIC_IS_R300(rdev) ||
 932                     (rdev->family == CHIP_RS300) ||
 933                     (rdev->family == CHIP_RS400) ||
 934                     (rdev->family == CHIP_RS480)) {
 935                         if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
 936                                 /* When restoring console mode, use saved PPLL_REF_DIV
 937                                  * setting.
 938                                  */
 939                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 940                                              pll_ref_div,
 941                                              0);
 942                         } else {
 943                                 /* R300 uses ref_div_acc field as real ref divider */
 944                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 945                                              (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
 946                                              ~R300_PPLL_REF_DIV_ACC_MASK);
 947                         }
 948                 } else
 949                         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 950                                      pll_ref_div,
 951                                      ~RADEON_PPLL_REF_DIV_MASK);
 952
 953                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
 954                              pll_fb_post_div,
 955                              ~RADEON_PPLL_FB3_DIV_MASK);
 956
 957                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
 958                              pll_fb_post_div,
 959                              ~RADEON_PPLL_POST3_DIV_MASK);
 960
 961                 radeon_pll_write_update(dev);
 962                 radeon_pll_wait_for_read_update_complete(dev);
 963
 964                 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
 965
 966                 WREG32_PLL_P(RADEON_PPLL_CNTL,
 967                              0,
 968                              ~(RADEON_PPLL_RESET
 969                                | RADEON_PPLL_SLEEP
 970                                | RADEON_PPLL_ATOMIC_UPDATE_EN
 971                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
 972
 973                 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 974                           pll_ref_div,
 975                           pll_fb_post_div,
 976                           (unsigned)htotal_cntl,
 977                           RREG32_PLL(RADEON_PPLL_CNTL));
 978                 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n",
 979                           pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
 980                           pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
 981                           (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
 982
 983                 mdelay(50); /* Let the clock to lock */
 984
 985                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
 986                              RADEON_VCLK_SRC_SEL_PPLLCLK,
 987                              ~(RADEON_VCLK_SRC_SEL_MASK));
 988
 989                 if (is_tv)
 990                         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 991         }
 992 }
 993
 994 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
 995                                    struct drm_display_mode *mode,
 996                                    struct drm_display_mode *adjusted_mode)
 997 {
 998         struct drm_device *dev = crtc->dev;
 999         struct radeon_device *rdev = dev->dev_private;
1000
1001         /* adjust pm to upcoming mode change */
1002         radeon_pm_compute_clocks(rdev);
1003
1004         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1005                 return false;
1006         return true;
1007 }
1008
1009 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1010                                  struct drm_display_mode *mode,
1011                                  struct drm_display_mode *adjusted_mode,
1012                                  int x, int y, struct drm_framebuffer *old_fb)
1013 {
1014         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1015
1016         /* TODO TV */
1017         radeon_crtc_set_base(crtc, x, y, old_fb);
1018         radeon_set_crtc_timing(crtc, adjusted_mode);
1019         radeon_set_pll(crtc, adjusted_mode);
1020         radeon_overscan_setup(crtc, adjusted_mode);
1021         if (radeon_crtc->crtc_id == 0) {
1022                 radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
1023         } else {
1024                 if (radeon_crtc->rmx_type != RMX_OFF) {
1025                         /* FIXME: only first crtc has rmx what should we
1026                          * do ?
1027                          */
1028                         DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1029                 }
1030         }
1031         return 0;
1032 }
1033
1034 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1035 {
1036         struct drm_device *dev = crtc->dev;
1037         struct drm_crtc *crtci;
1038
1039         /*
1040         * The hardware wedges sometimes if you reconfigure one CRTC
1041         * whilst another is running (see fdo bug #24611).
1042         */
1043         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1044                 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1045 }
1046
1047 static void radeon_crtc_commit(struct drm_crtc *crtc)
1048 {
1049         struct drm_device *dev = crtc->dev;
1050         struct drm_crtc *crtci;
1051
1052         /*
1053         * Reenable the CRTCs that should be running.
1054         */
1055         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1056                 if (crtci->enabled)
1057                         radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1058         }
1059 }
1060
1061 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1062         .dpms = radeon_crtc_dpms,
1063         .mode_fixup = radeon_crtc_mode_fixup,
1064         .mode_set = radeon_crtc_mode_set,
1065         .mode_set_base = radeon_crtc_set_base,
1066         .mode_set_base_atomic = radeon_crtc_set_base_atomic,
1067         .prepare = radeon_crtc_prepare,
1068         .commit = radeon_crtc_commit,
1069         .load_lut = radeon_crtc_load_lut,
1070 };
1071
1072
1073 void radeon_legacy_init_crtc(struct drm_device *dev,
1074                                struct radeon_crtc *radeon_crtc)
1075 {
1076         if (radeon_crtc->crtc_id == 1)
1077                 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1078         drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1079 }