1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
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40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
52 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
53 #define PLATFORM_SETUP1 _platform_setup1
54 #define CYGHWR_HAL_ARM_HAS_MMU
56 #ifdef CYG_HAL_STARTUP_ROMRAM
57 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
60 //#define NFC_2K_BI_SWAP
61 #define SDRAM_FULL_PAGE_BIT 0x100
62 #define SDRAM_FULL_PAGE_MODE 0x37
63 #define SDRAM_BURST_MODE 0x33
65 #define CYGHWR_HAL_ROM_VADDR 0x0
68 #define UNALIGNED_ACCESS_ENABLE
69 #define SET_T_BIT_DISABLE
70 #define BRANCH_PREDICTION_ENABLE
73 //#define ENABLE_IMPRECISE_ABORT
75 #define PLATFORM_PREAMBLE flash_header
77 //flash header & DCD @ 0x400
81 app_code_jump_v: .long reset_vector
82 app_code_barker: .long 0xB1
84 dcd_ptr_ptr: .long dcd_ptr
85 super_root_key: .long 0
86 dcd_ptr: .long dcd_data
87 app_dest_ptr: .long 0x47f00000
89 dcd_data: .long 0xB17219E9
90 dcd_len: .long (49*12)
260 // Precharge command 2
265 // refresh commands 3
275 // LMR with CAS=3 BL=3 5
281 // 13row 10 col 32 bit sref=4 micro model 6
287 // timing parameter 7
293 // mddr enable RLAT=2 8
305 image_len: .long REDBOOT_IMAGE_SIZE
312 // This macro represents the initial startup code for the platform
313 .macro _platform_setup1
314 FSL_BOARD_SETUP_START:
318 * - invalidate I/D cache/TLB and drain write buffer;
319 * - invalidate L2 cache
321 * - branch predictions
323 // mrc p15, 0, r0, c1, c1, 0 // Read Secure Configuration Register data. Why doesn't work???
324 // mcr p15, 0, <Rd>, c1, c1, 0 ; Write Secure Configuration Register data
325 #ifdef ENABLE_IMPRECISE_ABORT
326 mrs r1, spsr // save old spsr
327 mrs r0, cpsr // read out the cpsr
328 bic r0, r0, #0x100 // clear the A bit
329 msr spsr, r0 // update spsr
330 add lr, pc, #0x8 // update lr
331 movs pc, lr // update cpsr
336 msr spsr, r1 // restore old spsr
340 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
341 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
342 mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
344 /* Also setup the Peripheral Port Remap register inside the core */
345 ldr r0, ARM_PPMRR /* start from AIPS 2GB region */
346 mcr p15, 0, r0, c15, c2, 4
348 /* Reload data from spare area to 0x400 of main area if booting from NAND */
354 #ifdef BARKER_CODE_SWAP_LOC
355 #if BARKER_CODE_SWAP_LOC != 0x404
356 #error FIXME: the following depends on barker code to be 0x404
358 // Recover the word at 0x404 offset using the one stored in the spare area 0
367 /*** L2 Cache setup/invalidation/disable ***/
368 /* Disable L2 cache first */
369 mov r0, #L2CC_BASE_ADDR
371 str r2, [r0, #L2_CACHE_CTL_REG]
373 * Configure L2 Cache:
374 * - 128k size(16k way)
375 * - 8-way associativity
376 * - 0 ws TAG/VALID/DIRTY
380 add r2, r2, #0x00F00000
381 ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
383 ldr r2, L2CACHE_PARAM
385 str r1, [r0, #L2_CACHE_AUX_CTL_REG]
389 str r1, [r0, #L2_CACHE_INV_WAY_REG]
391 /* Poll Invalidate By Way register */
392 ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
395 /*** End of L2 operations ***/
399 * End of ARM1136 init
417 /* If SDRAM has been setup, bypass clock/WEIM setup */
418 cmp pc, #SDRAM_BASE_ADDR
419 blo external_boot_cont
420 cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
421 blo internal_boot_cont
432 HWInitialise_skip_SDRAM_setup:
434 add r2, r0, #0x1000 // 4K window
436 blo Normal_Boot_Continue
438 bhi Normal_Boot_Continue
441 /* Copy image from flash to SDRAM first */
442 ldr r1, MXC_REDBOOT_ROM_START
443 1: ldmia r0!, {r3-r10}
450 and r0, pc, r1 /* offset of pc */
451 ldr r1, MXC_REDBOOT_ROM_START
461 // Check if x16/2kb page
462 // ldr r7, CCM_BASE_ADDR_W
463 // ldr r7, [r7, #0xC]
464 // ands r7, r7, #(1 << 30)
465 ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
466 mov r1, #0x1000 //r1: starting flash addr to be copied. Updated constantly
467 // ???? should be dynamic based on the page size kevin todo
468 add r2, r0, #0x1000 //r2: end of 3rd RAM buf. Doesn't change ?? dynamic
470 ldr r11, NFC_IP_BASE_W //r11: NFC IP register base. Doesn't change
471 add r12, r0, #0x1E00 //r12: NFC AXI register base. Doesn't change
472 ldr r14, MXC_REDBOOT_ROM_START
473 add r13, r14, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
474 add r14, r14, r1 //r14: starting SDRAM address for copying. Updated constantly
476 //unlock internal buffer
478 add r3, r3, #0x00FF0000
485 str r3, [r11, #0x0] // kevin - revist for multiple CS ??
490 // writew(FLASH_Read_Mode1, NAND_ADD_CMD_REG);
493 mov r3, #NAND_LAUNCH_FCMD
497 // start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
501 do_addr_input //1st addr cycle
505 do_addr_input //2nd addr cycle
509 do_addr_input //3rd addr cycle
513 do_addr_input //4th addr cycle
517 do_addr_input //5th addr cycle TODO
519 // writew(FLASH_Read_Mode1_2K, NAND_ADD_CMD_REG);
522 mov r3, #NAND_LAUNCH_FCMD
526 // write RBA=0 to NFC_CONFIGURATION1
530 // writel(mode & 0xFF, NAND_LAUNCH_REG);
539 1: ldmia r0!, {r3-r10}
544 bge NAND_Copy_Main_done
551 Normal_Boot_Continue:
553 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
554 /* Copy image from flash to SDRAM first */
557 ldr r1, MXC_REDBOOT_ROM_START
559 beq HWInitialise_skip_SDRAM_copy
561 add r2, r0, #REDBOOT_IMAGE_SIZE
563 1: ldmia r0!, {r3-r10}
569 and r0, pc, r1 /* offset of pc */
570 ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
576 #endif /* CYG_HAL_STARTUP_ROMRAM */
578 HWInitialise_skip_SDRAM_copy:
582 * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
586 // Set up a stack [for calling C code]
587 ldr r1, =__startup_stack
588 ldr r2, =RAM_BANK0_BASE
596 mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
597 orr r1, r1, #7 // enable MMU bit
598 orr r1, r1, #0x800 // enable z bit
599 mcr MMU_CP, 0, r1, MMU_Control, c0
600 mov pc,r2 /* Change address spaces */
606 // Save shadow copy of BCR, also hardware configuration
610 str r9, [r1] // Saved far above...
612 .endm // _platform_setup1
614 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
615 #define PLATFORM_SETUP1
620 .endm /* init_spba */
622 /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
625 * Set all MPROTx to be non-bufferable, trusted for R/W,
626 * not forced to user-mode.
628 ldr r0, AIPS1_CTRL_BASE_ADDR_W
629 ldr r1, AIPS1_PARAM_W
632 ldr r0, AIPS2_CTRL_BASE_ADDR_W
636 .endm /* init_aips */
638 /* MAX (Multi-Layer AHB Crossbar Switch) setup */
640 ldr r0, MAX_BASE_ADDR_W
642 /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
644 str r1, [r0, #0x000] /* for S0 */
645 str r1, [r0, #0x100] /* for S1 */
646 str r1, [r0, #0x200] /* for S2 */
647 str r1, [r0, #0x300] /* for S3 */
648 str r1, [r0, #0x400] /* for S4 */
649 /* SGPCR - always park on last master */
651 str r1, [r0, #0x010] /* for S0 */
652 str r1, [r0, #0x110] /* for S1 */
653 str r1, [r0, #0x210] /* for S2 */
654 str r1, [r0, #0x310] /* for S3 */
655 str r1, [r0, #0x410] /* for S4 */
656 /* MGPCR - restore default values */
658 str r1, [r0, #0x800] /* for M0 */
659 str r1, [r0, #0x900] /* for M1 */
660 str r1, [r0, #0xA00] /* for M2 */
661 str r1, [r0, #0xB00] /* for M3 */
662 str r1, [r0, #0xC00] /* for M4 */
663 str r1, [r0, #0xD00] /* for M5 */
673 ===========================
679 * All other clocks can be figured out based on this.
682 * Step 1: Switch to step clock
684 ldr r0, CCM_BASE_ADDR_W
686 str r1, [r0, #CLKCTL_CCSR]
688 /* Step 2: Setup PLL's */
689 /* Set PLL1 to be 532MHz */
690 ldr r0, PLL1_BASE_ADDR_W
694 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
696 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
699 str r1, [r0, #PLL_DP_OP]
701 str r1, [r0, #PLL_DP_MFD]
703 str r1, [r0, #PLL_DP_MFN]
706 str r1, [r0, #PLL_DP_HFS_OP]
708 str r1, [r0, #PLL_DP_HFS_MFD]
710 str r1, [r0, #PLL_DP_HFS_MFN]
712 /* Now restart PLL 1 */
713 ldr r1, PLL_VAL_0x1232
714 str r1, [r0, #PLL_DP_CTL]
716 ldr r1, [r0, #PLL_DP_CTL]
721 * Step 2: Setup PLL2 to 665 MHz.
723 ldr r0, PLL2_BASE_ADDR_W
727 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
729 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
732 str r1, [r0, #PLL_DP_OP]
734 str r1, [r0, #PLL_DP_MFD]
736 str r1, [r0, #PLL_DP_MFN]
739 str r1, [r0, #PLL_DP_HFS_OP]
741 str r1, [r0, #PLL_DP_HFS_MFD]
743 str r1, [r0, #PLL_DP_HFS_MFN]
745 /* Now restart PLL 2 */
746 ldr r1, PLL_VAL_0x1232
747 str r1, [r0, #PLL_DP_CTL]
749 ldr r1, [r0, #PLL_DP_CTL]
754 * Set PLL 3 to 216MHz
756 ldr r0, PLL3_BASE_ADDR_W
758 ldr r1, PLL_VAL_0x222
759 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
761 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
764 str r1, [r0, #PLL_DP_OP]
766 str r1, [r0, #PLL_DP_MFD]
768 str r1, [r0, #PLL_DP_MFN]
771 str r1, [r0, #PLL_DP_HFS_OP]
773 str r1, [r0, #PLL_DP_HFS_MFD]
775 str r1, [r0, #PLL_DP_HFS_MFN]
777 /* Now restart PLL 3 */
778 ldr r1, PLL_VAL_0x232
779 str r1, [r0, #PLL_DP_CTL]
782 ldr r1, [r0, #PLL_DP_CTL]
785 /* End of PLL 3 setup */
787 /* Setup the ARM platform clock dividers */
788 ldr r0, PLATFORM_BASE_ADDR_W
789 ldr r1, PLATFORM_CLOCK_DIV_W
793 * Step 3: switching to PLL 1 and restore default register values.
795 ldr r0, CCM_BASE_ADDR_W
797 str r1, [r0, #CLKCTL_CCSR]
800 add r1, r1, #0x00000F0
801 str r1, [r0, #CLKCTL_CCOSR]
802 /* Use 133MHz for DDR clock */
804 str r1, [r0, #CLKCTL_CAMR]
805 /* Use PLL 2 for UART's, get 66.5MHz from it */
806 ldr r1, CCM_VAL_0xA5A6A020
807 str r1, [r0, #CLKCTL_CSCMR1]
808 ldr r1, CCM_VAL_0x01450B21
809 str r1, [r0, #CLKCTL_CSCDR1]
812 str r1, [r0, #CLKCTL_CBCDR7]
815 .endm /* init_clock */
819 /* Configure M4IF registers, VPU and IPU given higher priority (=0x4)
820 IPU accesses with ID=0x1 given highest priority (=0xA) */
822 ldr r0, M4IF_0x00000a01
823 str r0, [r1, #M4IF_FIDBP]
825 ldr r0, M4IF_0x00000404
826 str r0, [r1, #M4IF_FBPM0]
827 .endm /* init_m4if */
830 ldr r0, ESDCTL_BASE_W
833 str r1, [r0, #ESDCTL_ESDCTL0]
834 /* Precharge command */
835 ldr r1, SDRAM_0x04008008
836 str r1, [r0, #ESDCTL_ESDSCR]
837 /* 2 refresh commands */
838 ldr r1, SDRAM_0x00008010
839 str r1, [r0, #ESDCTL_ESDSCR]
840 str r1, [r0, #ESDCTL_ESDSCR]
841 /* LMR with CAS=3 and BL=3 */
842 ldr r1, SDRAM_0x00338018
843 str r1, [r0, #ESDCTL_ESDSCR]
844 /* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
845 ldr r1, SDRAM_0xB2220000
846 str r1, [r0, #ESDCTL_ESDCTL0]
847 /* Timing parameters */
848 ldr r1, SDRAM_0x899F6BBA
849 str r1, [r0, #ESDCTL_ESDCFG0]
850 /* MDDR enable, RLAT=2 */
851 ldr r1, SDRAM_0x000A1104
852 str r1, [r0, #ESDCTL_ESDMISC]
855 str r1, [r0, #ESDCTL_ESDSCR]
858 .macro do_wait_op_done
861 ands r3, r3, #NFC_IPC_INT
865 .endm // do_wait_op_done
869 mov r3, #NAND_LAUNCH_FADD
872 .endm // do_addr_input
874 /* To support 133MHz DDR */
876 ldr r0, IOMUXC_BASE_ADDR_W
878 // DDR signal setup for D16-D31 and drive strength
911 .endm /* init_iomux */
913 #define PLATFORM_VECTORS _platform_vectors
914 .macro _platform_vectors
915 .globl _board_BCR, _board_CFG
916 _board_BCR: .long 0 // Board Control register shadow
917 _board_CFG: .long 0 // Board Configuration (read at RESET)
920 ARM_PPMRR: .word 0x80000016
921 L2CACHE_PARAM: .word 0x0003001B
922 WDOG1_BASE_W: .word WDOG1_BASE_ADDR
923 IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
924 AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
925 AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
926 AIPS1_PARAM_W: .word 0x77777777
927 MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
928 MAX_PARAM1: .word 0x00302154
929 ESDCTL_BASE_W: .word ESDCTL_BASE
930 M4IF_BASE_W: .word M4IF_BASE
931 M4IF_0x00000a01: .word 0x00000a01
932 M4IF_0x00000404: .word 0x00000404
933 NFC_BASE_W: .word NFC_BASE
934 NFC_IP_BASE_W: .word NFC_IP_BASE
935 SDRAM_0x04008008: .word 0x04008008
936 SDRAM_0x00008010: .word 0x00008010
937 SDRAM_0x00338018: .word 0x00338018
938 SDRAM_0xB2220000: .word 0xB2220000
939 SDRAM_0x899F6BBA: .word 0x899F6BBA
940 SDRAM_0x000A1104: .word 0x000A1104
941 IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
942 MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
943 CONST_0x0FFF: .word 0x0FFF
944 CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
945 PLATFORM_BASE_ADDR_W: .word PLATFORM_BASE_ADDR
946 PLATFORM_CLOCK_DIV_W: .word 0x00077713
947 CCM_VAL_0x01450B21: .word 0x01450B21
948 CCM_VAL_0xA5A6A020: .word 0xA5A6A020
949 PLL_VAL_0x222: .word 0x222
950 PLL_VAL_0x232: .word 0x232
951 PLL1_BASE_ADDR_W: .word PLL1_BASE_ADDR
952 PLL2_BASE_ADDR_W: .word PLL2_BASE_ADDR
953 PLL3_BASE_ADDR_W: .word PLL3_BASE_ADDR
954 PLL_VAL_0x1232: .word 0x1232
956 /*---------------------------------------------------------------------------*/
957 /* end of hal_platform_setup.h */
958 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */