1 //==========================================================================
5 // HAL misc board support code
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
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17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
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34 // this file might be covered by the GNU General Public License.
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37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //========================================================================*/
43 #include <pkgconf/hal.h>
44 #include <pkgconf/system.h>
45 #include CYGBLD_HAL_PLATFORM_H
47 #include <cyg/infra/cyg_type.h> // base types
48 #include <cyg/infra/cyg_trac.h> // tracing macros
49 #include <cyg/infra/cyg_ass.h> // assertion macros
51 #include <cyg/hal/hal_misc.h> // Size constants
52 #include <cyg/hal/hal_io.h> // IO macros
53 #include <cyg/hal/hal_arch.h> // Register state info
54 #include <cyg/hal/hal_diag.h>
55 #include <cyg/hal/hal_intr.h> // Interrupt names
56 #include <cyg/hal/hal_cache.h> // Cache control
57 #include <cyg/hal/hal_soc.h> // Hardware definitions
58 #include <cyg/hal/hal_mm.h> // MMap table definitions
60 #include <cyg/infra/diag.h> // diag_printf
62 // Most initialization has already been done before we get here.
63 // All we do here is set up the interrupt environment.
64 // FIXME: some of the stuff in hal_platform_setup could be moved here.
66 externC void plf_hardware_init(void);
67 int _mxc_boot, _mxc_fis;
69 #define IIM_PROD_REV_SH 3
70 #define IIM_PROD_REV_LEN 5
71 #define IIM_SREV_REV_SH 4
72 #define IIM_SREV_REV_LEN 4
73 #define PROD_SIGNATURE_MX37 0x1
75 #define PROD_SIGNATURE_SUPPORTED PROD_SIGNATURE_MX37
77 #define CHIP_VERSION_NONE 0xFFFFFFFF // invalid product ID
78 #define CHIP_VERSION_UNKNOWN 0xDEADBEEF // invalid chip rev
81 * System_rev will have the following format
82 * 31-12 = part # (0x31, 0x32, 0x27, 0x91131, 0x91321, etc)
87 unsigned int system_rev = CHIP_REV_1_0;
88 static int find_correct_chip;
89 extern char HAL_PLATFORM_EXTRA[20];
92 * This functions reads the IIM module and returns the system revision number.
93 * It returns the IIM silicon revision reg value if valid product rev is found.
94 . Otherwise, it returns -1.
96 static int read_system_rev(void)
100 val = readl(IIM_BASE_ADDR + IIM_PREV_OFF);
102 system_rev = 0x37 << PART_NUMBER_OFFSET; /* For MX37 Platform*/
104 /* Now trying to retrieve the silicon rev from IIM's SREV register */
105 return readl(IIM_BASE_ADDR + IIM_SREV_OFF);
108 extern nfc_setup_func_t *nfc_setup;
109 unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz,
110 unsigned int is_mlc, unsigned int num_of_chips);
111 void hal_hardware_init(void)
113 volatile unsigned int esdmisc = readl(ESDCTL_BASE + 0x10);
114 volatile unsigned int esdctl0 = readl(ESDCTL_BASE);
115 volatile unsigned int sbmr;
116 int bt_mem_type = 0, bt_mem_control = 0;
117 int ver = read_system_rev();
118 unsigned int *fis_addr = (unsigned int *)IRAM_BASE_ADDR;
122 _mxc_fis = FROM_MMC_FLASH;
124 case FROM_NAND_FLASH:
125 _mxc_fis = FROM_NAND_FLASH;
128 sbmr = readl(SRC_BASE_ADDR + 0x4);
129 bt_mem_control = sbmr & 0x3;
130 bt_mem_type = (sbmr & 0x180) >> 7;
131 if (bt_mem_control == 0x3) {
132 if (bt_mem_type == 0) {
133 _mxc_fis = FROM_MMC_FLASH;
134 _mxc_boot = FROM_MMC_FLASH;
135 } else if (bt_mem_type == 3) {
136 _mxc_fis = FROM_SPI_NOR_FLASH;
137 _mxc_boot = FROM_SPI_NOR_FLASH;
139 } else if (bt_mem_control == 0x1) {
140 _mxc_fis = FROM_NAND_FLASH;
141 _mxc_boot = FROM_NAND_FLASH;
145 find_correct_chip = ver;
147 if (ver != CHIP_VERSION_NONE) {
148 /* Valid product revision found. Check actual silicon rev and
149 * NOT use the version from the ROM code. */
150 if (((ver >> 4) & 0xF) == 0x0) {
151 HAL_PLATFORM_EXTRA[5] = '1';
152 HAL_PLATFORM_EXTRA[7] = '0';
153 system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
154 system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/
155 } else if (((ver >> 4) & 0xF) == 0x1) {
156 HAL_PLATFORM_EXTRA[5] = '1';
157 HAL_PLATFORM_EXTRA[7] = '1';
158 system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
159 system_rev |= 1 << MINOR_NUMBER_OFFSET; /*Minor Number*/
161 HAL_PLATFORM_EXTRA[5] = 'x';
162 HAL_PLATFORM_EXTRA[7] = 'x';
163 system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
164 system_rev |= 1 << MINOR_NUMBER_OFFSET; /*Minor Number*/
165 find_correct_chip = CHIP_VERSION_UNKNOWN;
169 if ((esdmisc & 0x4) == 0) {
170 HAL_PLATFORM_EXTRA[14] = 'S';
172 if ((esdctl0 & 0x30000) != 0x20000) {
173 HAL_PLATFORM_EXTRA[11] = '1';
174 HAL_PLATFORM_EXTRA[12] = '6';
181 // enable EPIT and start it with 32KHz input clock
182 writel(0x00010000, EPIT_BASE_ADDR + EPITCR);
184 // make sure reset is complete
185 while ((readl(EPIT_BASE_ADDR + EPITCR) & 0x10000) != 0) {
188 writel(0x030E0002, EPIT_BASE_ADDR + EPITCR);
189 writel(0x030E0003, EPIT_BASE_ADDR + EPITCR);
191 writel(0, EPIT_BASE_ADDR + EPITCMPR); // always compare with 0
193 if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
194 // increase the WDOG timeout value to the max
195 writew(readw(WDOG_BASE_ADDR) | 0xFF00, WDOG_BASE_ADDR);
198 // Perform any platform specific initializations
201 // Set up eCos/ROM interfaces
204 nfc_setup = (nfc_setup_func_t*)mxc_nfc_soc_setup;
207 // -------------------------------------------------------------------------
208 void hal_clock_initialize(cyg_uint32 period)
212 // This routine is called during a clock interrupt.
214 // Define this if you want to ensure that the clock is perfect (i.e. does
215 // not drift). One reason to leave it turned off is that it costs some
216 // us per system clock interrupt for this maintenance.
217 #undef COMPENSATE_FOR_CLOCK_DRIFT
219 void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
223 // Read the current value of the clock, returning the number of hardware
224 // "ticks" that have occurred (i.e. how far away the current value is from
227 // Note: The "contract" for this function is that the value is the number
228 // of hardware clocks that have happened since the last interrupt (i.e.
229 // when it was reset). This value is used to measure interrupt latencies.
230 // However, since the hardware counter runs freely, this routine computes
231 // the difference between the current clock period and the number of hardware
232 // ticks left before the next timer interrupt.
233 void hal_clock_read(cyg_uint32 *pvalue)
237 // This is to cope with the test read used by tm_basic with
238 // CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY defined; we read the count ASAP
239 // in the ISR, *before* resetting the clock. Which returns 1tick +
240 // latency if we just use plain hal_clock_read().
241 void hal_clock_latency(cyg_uint32 *pvalue)
245 unsigned int hal_timer_count(void)
247 return (0xFFFFFFFF - readl(EPIT_BASE_ADDR + EPITCNR));
250 #define WDT_MAGIC_1 0x5555
251 #define WDT_MAGIC_2 0xAAAA
252 #define MXC_WDT_WSR 0x2
254 unsigned int i2c_base_addr[] = {
259 unsigned int i2c_num = 3;
262 // Delay for some number of micro-seconds
264 void hal_delay_us(unsigned int usecs)
267 * This causes overflow.
268 * unsigned int delayCount = (usecs * 32768) / 1000000;
269 * So use the following one instead
271 unsigned int delayCount = (usecs * 512) / 15625;
273 if (delayCount == 0) {
277 // issue the service sequence instructions
278 if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
279 writew(WDT_MAGIC_1, WDOG_BASE_ADDR + MXC_WDT_WSR);
280 writew(WDT_MAGIC_2, WDOG_BASE_ADDR + MXC_WDT_WSR);
283 writel(0x01, EPIT_BASE_ADDR + EPITSR); // clear the compare status bit
285 writel(delayCount, EPIT_BASE_ADDR + EPITLR);
287 while ((0x1 & readl(EPIT_BASE_ADDR + EPITSR)) == 0); // return until compare bit is set
290 // -------------------------------------------------------------------------
292 // This routine is called to respond to a hardware interrupt (IRQ). It
293 // should interrogate the hardware and return the IRQ vector number.
294 int hal_IRQ_handler(void)
296 #ifdef HAL_EXTENDED_IRQ_HANDLER
299 // Use platform specific IRQ handler, if defined
300 // Note: this macro should do a 'return' with the appropriate
301 // interrupt number if such an extended interrupt exists. The
302 // assumption is that the line after the macro starts 'normal' processing.
303 HAL_EXTENDED_IRQ_HANDLER(index);
306 return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
313 void hal_interrupt_mask(int vector)
315 // diag_printf("6hal_interrupt_mask(vector=%d) \n", vector);
316 #ifdef HAL_EXTENDED_INTERRUPT_MASK
317 // Use platform specific handling, if defined
318 // Note: this macro should do a 'return' for "extended" values of 'vector'
319 // Normal vectors are handled by code subsequent to the macro call.
320 HAL_EXTENDED_INTERRUPT_MASK(vector);
324 void hal_interrupt_unmask(int vector)
326 // diag_printf("7hal_interrupt_unmask(vector=%d) \n", vector);
328 #ifdef HAL_EXTENDED_INTERRUPT_UNMASK
329 // Use platform specific handling, if defined
330 // Note: this macro should do a 'return' for "extended" values of 'vector'
331 // Normal vectors are handled by code subsequent to the macro call.
332 HAL_EXTENDED_INTERRUPT_UNMASK(vector);
336 void hal_interrupt_acknowledge(int vector)
339 // diag_printf("8hal_interrupt_acknowledge(vector=%d) \n", vector);
340 #ifdef HAL_EXTENDED_INTERRUPT_UNMASK
341 // Use platform specific handling, if defined
342 // Note: this macro should do a 'return' for "extended" values of 'vector'
343 // Normal vectors are handled by code subsequent to the macro call.
344 HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector);
348 void hal_interrupt_configure(int vector, int level, int up)
351 #ifdef HAL_EXTENDED_INTERRUPT_CONFIGURE
352 // Use platform specific handling, if defined
353 // Note: this macro should do a 'return' for "extended" values of 'vector'
354 // Normal vectors are handled by code subsequent to the macro call.
355 HAL_EXTENDED_INTERRUPT_CONFIGURE(vector, level, up);
359 void hal_interrupt_set_level(int vector, int level)
362 #ifdef HAL_EXTENDED_INTERRUPT_SET_LEVEL
363 // Use platform specific handling, if defined
364 // Note: this macro should do a 'return' for "extended" values of 'vector'
365 // Normal vectors are handled by code subsequent to the macro call.
366 HAL_EXTENDED_INTERRUPT_SET_LEVEL(vector, level);
369 // Interrupt priorities are not configurable.
372 unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz, unsigned int is_mlc, unsigned int num_of_chips)
374 return 0x20; // NFC version 2
377 static void check_correct_chip(void)
379 if (find_correct_chip == CHIP_VERSION_UNKNOWN) {
380 diag_printf("Unrecognized chip version: 0x%x!!!\n", read_system_rev());
381 diag_printf("Assuming chip version=0x%x\n", system_rev);
382 } else if (find_correct_chip == CHIP_VERSION_NONE) {
383 diag_printf("Unrecognized chip: 0x%x!!!\n", readl(IIM_BASE_ADDR + IIM_PREV_OFF));
387 RedBoot_init(check_correct_chip, RedBoot_INIT_LAST);