1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
52 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
53 #define PLATFORM_SETUP1 _platform_setup1
54 #define CYGHWR_HAL_ARM_HAS_MMU
56 #ifdef CYG_HAL_STARTUP_ROMRAM
57 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
60 //#define NFC_2K_BI_SWAP
61 #define SDRAM_FULL_PAGE_BIT 0x100
62 #define SDRAM_FULL_PAGE_MODE 0x37
63 #define SDRAM_BURST_MODE 0x33
65 #define CYGHWR_HAL_ROM_VADDR 0x0
68 #define UNALIGNED_ACCESS_ENABLE
69 #define SET_T_BIT_DISABLE
70 #define BRANCH_PREDICTION_ENABLE
73 #define DCDGEN(i,type, addr, data) \
79 #define PLATFORM_PREAMBLE flash_header
80 //flash header & DCD @ 0x400
84 app_code_jump_v: .long reset_vector
85 app_code_barker: .long 0xB1
87 dcd_ptr_ptr: .long dcd_ptr
88 super_root_key: .long 0
89 dcd_ptr: .long dcd_data
90 app_dest_ptr: .long 0xAFF00000
92 dcd_data: .long 0xB17219E9 // Fixed. can't change.
93 dcd_len: .long (20*12)
96 // ldr r0, ESDCTL_BASE_W
98 // ldr r1, =0x80000000
99 // str r1, [r0, #ESDCTL_ESDCTL0]
100 DCDGEN(1, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x80000000)
101 // /* Precharge command */
102 // ldr r1, SDRAM_0x04008008
103 // str r1, [r0, #ESDCTL_ESDSCR]
104 DCDGEN(2, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
105 // /* 2 refresh commands */
106 // ldr r1, SDRAM_0x00008010
107 // str r1, [r0, #ESDCTL_ESDSCR]
108 DCDGEN(3, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
109 // str r1, [r0, #ESDCTL_ESDSCR]
110 DCDGEN(4, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
111 // /* LMR with CAS=3 and BL=3 */
112 // ldr r1, SDRAM_0x00338018
113 // str r1, [r0, #ESDCTL_ESDSCR]
114 DCDGEN(5, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00338018)
115 // /* 14 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
116 // ldr r1, SDRAM_0xB2220000
117 // str r1, [r0, #ESDCTL_ESDCTL0]
118 DCDGEN(6, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xC3220000)
119 // /* Timing parameters */
120 // ldr r1, SDRAM_0xB02567A9
121 // str r1, [r0, #ESDCTL_ESDCFG0]
122 DCDGEN(7, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0xB08567A9)
123 // /* MDDR enable, RLAT=2 */
124 // ldr r1, SDRAM_0x000A0104
125 // str r1, [r0, #ESDCTL_ESDMISC]
126 DCDGEN(8, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000A0104)
128 // ldr r1, =0x00000000
129 // str r1, [r0, #ESDCTL_ESDSCR]
130 DCDGEN(9, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0)
132 //////////////////// csd1 //////////////////
133 DCDGEN(10, 4, 0x83fd9008, 0x80000000)
135 //setmem /32 0x83fd9014 = 0x0400800C // [MK]
136 DCDGEN(11, 4, 0x83fd9014, 0x0400800C)
138 //setmem /32 0x83fd9014 = 0x00008014 // [MK]
139 DCDGEN(12, 4, 0x83fd9014, 0x00008014)
140 //setmem /32 0x83fd9014 = 0x00008014 // [MK]
141 DCDGEN(13, 4, 0x83fd9014, 0x00008014)
142 //LMR with CAS=3 and BL=3
143 //setmem /32 0x83fd9014 = 0x0033801C // [MK]
144 DCDGEN(14, 4, 0x83fd9014, 0x0033801C)
145 //14 ROW, 10 COL, 32Bit, SREF=8 Micron Model
146 //setmem /32 0x83fd9008 = 0xC3220000
147 DCDGEN(15, 4, 0x83fd9008, 0xC3220000)
149 //setmem /32 0x83fd900C = 0xB08567A9
150 DCDGEN(16, 4, 0x83fd900C, 0xB08567A9)
151 //MDDR enable, RLAT=2
152 //setmem /32 0x83fd9010 = 0x000a0104
153 DCDGEN(17, 4, 0x83fd9010, 0x000a0104)
155 //setmem /32 0x83fd9014 = 0x00000004 // [DB]
156 DCDGEN(18, 4, 0x83fd9014, 0x00000004)
157 //setmem /32 0x90000000 = 0x00000000
158 DCDGEN(19, 4, 0x90000000, 0x00000000)
159 //setmem /32 0xA0000000 = 0x00000000
160 DCDGEN(20, 4, 0xA0000000, 0x00000000)
162 image_len: .long 256*1024
166 //#define ENABLE_IMPRECISE_ABORT
168 // This macro represents the initial startup code for the platform
169 .macro _platform_setup1
170 FSL_BOARD_SETUP_START:
171 // mrc p15, 0, r0, c1, c1, 0 // Read Secure Configuration Register data. Why doesn't work???
172 // mcr p15, 0, <Rd>, c1, c1, 0 ; Write Secure Configuration Register data
173 #ifdef ENABLE_IMPRECISE_ABORT
174 mrs r1, spsr // save old spsr
175 mrs r0, cpsr // read out the cpsr
176 bic r0, r0, #0x100 // clear the A bit
177 msr spsr, r0 // update spsr
178 add lr, pc, #0x8 // update lr
179 movs pc, lr // update cpsr
184 msr spsr, r1 // restore old spsr
186 // explicitly disable L2 cache
187 mrc 15, 0, r0, c1, c0, 1
189 mcr 15, 0, r0, c1, c0, 1
191 // reconfigure L2 cache aux control reg
192 mov r0, #0xC0 // tag RAM
193 add r0, r0, #0x4 // data RAM
194 orr r0, r0, #(1 << 25) // disable write combine
195 orr r0, r0, #(1 << 24) // disable write allocate delay
196 orr r0, r0, #(1 << 23) // disable write allocate combine
197 orr r0, r0, #(1 << 22) // disable write allocate
199 mcr 15, 1, r0, c9, c0, 2
220 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
221 /* Copy image from flash to SDRAM first */
224 ldr r1, MXC_REDBOOT_ROM_START
226 beq HWInitialise_skip_SDRAM_copy
228 add r2, r0, #REDBOOT_IMAGE_SIZE
230 1: ldmia r0!, {r3-r10}
236 and r0, pc, r1 /* offset of pc */
237 ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
243 #endif /* CYG_HAL_STARTUP_ROMRAM */
245 HWInitialise_skip_SDRAM_copy:
248 // init_cs1 -- moved to plf_hardware_init()
252 * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
255 // Set up a stack [for calling C code]
256 ldr r1, =__startup_stack
257 ldr r2, =RAM_BANK0_BASE
265 ldr r0, =ROM_BASE_ADDRESS
266 ldr r3, [r0, #ROM_SI_REV_OFFSET]
268 bne skip_L1_workaround
269 // Workaround for L1 cache issue
270 mrc MMU_CP, 0, r1, c10, c2, 1 // Read normal memory remap register
271 bic r1, r1, #(3 << 14) // Remap inner attribute for TEX[0],C,B = b111 as noncacheable
272 bic r1, r1, #(3 << 6) // Remap inner attribute for TEX[0],C,B = b011 as noncacheable
273 bic r1, r1, #(3 << 4) // Remap inner attribute for TEX[0],C,B = b010 as noncacheable
274 mcr MMU_CP, 0, r1, c10, c2, 1 // Write normal memory remap register
276 mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
277 orr r1, r1, #7 // enable MMU bit
278 orr r1, r1, #0x800 // enable z bit
279 orrne r1, r1, #(1 << 28) // Enable TEX remap, workaround for L1 cache issue
280 mcr MMU_CP, 0, r1, MMU_Control, c0
281 mov pc,r2 /* Change address spaces */
287 // Save shadow copy of BCR, also hardware configuration
291 str r9, [r1] // Saved far above...
293 .endm // _platform_setup1
295 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
296 #define PLATFORM_SETUP1
301 .endm /* init_spba */
303 /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
306 * Set all MPROTx to be non-bufferable, trusted for R/W,
307 * not forced to user-mode.
309 ldr r0, AIPS1_CTRL_BASE_ADDR_W
310 ldr r1, AIPS1_PARAM_W
313 ldr r0, AIPS2_CTRL_BASE_ADDR_W
317 .endm /* init_aips */
319 /* MAX (Multi-Layer AHB Crossbar Switch) setup */
324 ldr r0, CCM_BASE_ADDR_W
325 /* Disable IPU and HSC dividers */
327 str r1, [r0, #CLKCTL_CCDR]
329 /* Switch ARM to step clock */
331 str r1, [r0, #CLKCTL_CCSR]
334 /* Switch peripheral to PLL 3 */
335 ldr r0, CCM_BASE_ADDR_W
336 ldr r1, CCM_VAL_0x0000D3C0
337 str r1, [r0, #CLKCTL_CBCMR]
338 ldr r1, CCM_VAL_0x033B9145
339 str r1, [r0, #CLKCTL_CBCDR]
341 /* Switch peripheral to PLL 2 */
342 ldr r0, CCM_BASE_ADDR_W
343 ldr r1, CCM_VAL_0x013B9145
344 str r1, [r0, #CLKCTL_CBCDR]
345 ldr r1, CCM_VAL_0x0000E3C0
346 str r1, [r0, #CLKCTL_CBCMR]
350 /* Set the platform clock dividers */
351 ldr r0, PLATFORM_BASE_ADDR_W
352 ldr r1, PLATFORM_CLOCK_DIV_W
353 str r1, [r0, #PLATFORM_ICGC]
355 /* Switch ARM back to PLL 1. */
356 ldr r0, CCM_BASE_ADDR_W
358 str r1, [r0, #CLKCTL_CCSR]
362 str r1, [r0, #CLKCTL_CACRR]
364 /* Use lp_apm (24MHz) source for perclk */
365 ldr r1, CCM_VAL_0x0000E3C2
366 str r1, [r0, #CLKCTL_CBCMR]
367 // emi=ahb, all perclk dividers are 1 since using 24MHz
368 // DDR divider=6 to have 665/6=110MHz
369 ldr r1, CCM_VAL_0x013D9100
370 str r1, [r0, #CLKCTL_CBCDR]
372 /* Use PLL 2 for UART's, get 66.5MHz from it */
373 ldr r1, CCM_VAL_0xA5A2A020
374 str r1, [r0, #CLKCTL_CSCMR1]
375 ldr r1, CCM_VAL_0x00C30321
376 str r1, [r0, #CLKCTL_CSCDR1]
378 /* make sure divider effective */
379 1: ldr r1, [r0, #CLKCTL_CDHIPR]
384 str r1, [r0, #CLKCTL_CCDR]
386 // for cko - for ARM div by 8
388 add r1, r1, #0x00000F0
389 str r1, [r0, #CLKCTL_CCOSR]
390 .endm /* init_clock */
392 .macro setup_pll pll_nr, mhz
393 ldr r0, BASE_ADDR_W_\pll_nr
394 ldr r1, PLL_VAL_0x1232
395 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
397 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
400 str r1, [r0, #PLL_DP_OP]
401 str r1, [r0, #PLL_DP_HFS_OP]
403 ldr r1, W_DP_MFD_\mhz
404 str r1, [r0, #PLL_DP_MFD]
405 str r1, [r0, #PLL_DP_HFS_MFD]
407 ldr r1, W_DP_MFN_\mhz
408 str r1, [r0, #PLL_DP_MFN]
409 str r1, [r0, #PLL_DP_HFS_MFN]
411 /* Now restart PLL */
412 ldr r1, PLL_VAL_0x1232
413 str r1, [r0, #PLL_DP_CTL]
414 wait_pll_lock\pll_nr:
415 ldr r1, [r0, #PLL_DP_CTL]
417 beq wait_pll_lock\pll_nr
422 /* Configure M4IF registers, VPU and IPU given higher priority (=0x4)
423 IPU accesses with ID=0x1 given highest priority (=0xA) */
425 ldr r0, M4IF_0x00000a01
426 str r0, [r1, #M4IF_FIDBP]
428 ldr r0, M4IF_0x00000404
429 str r0, [r1, #M4IF_FBPM0]
430 .endm /* init_m4if */
434 .endm /* init_iomux */
436 #define PLATFORM_VECTORS _platform_vectors
437 .macro _platform_vectors
438 .globl _board_BCR, _board_CFG
439 _board_BCR: .long 0 // Board Control register shadow
440 _board_CFG: .long 0 // Board Configuration (read at RESET)
443 WDOG1_BASE_W: .word WDOG1_BASE_ADDR
444 IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
445 AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
446 AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
447 AIPS1_PARAM_W: .word 0x77777777
448 MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
449 MAX_PARAM1: .word 0x00302154
450 ESDCTL_BASE_W: .word ESDCTL_BASE_ADDR
451 M4IF_BASE_W: .word M4IF_BASE_ADDR
452 M4IF_0x00000a01: .word 0x00000a01
453 M4IF_0x00000404: .word 0x00000404
454 NFC_BASE_W: .word NFC_BASE_ADDR_AXI
455 NFC_IP_BASE_W: .word NFC_IP_BASE
456 IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
457 MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
458 CONST_0x0FFF: .word 0x0FFF
459 CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
460 CCM_VAL_0x0000E3C2: .word 0x0000E3C2
461 CCM_VAL_0x013D9100: .word 0x013D9100
462 CCM_VAL_0xA5A2A020: .word 0xA5A2A020
463 CCM_VAL_0x00C30321: .word 0x00C30321
464 CCM_VAL_0x0000D3C0: .word 0x0000D3C0
465 CCM_VAL_0x033B9145: .word 0x033B9145
466 CCM_VAL_0x013B9145: .word 0x013B9145
467 CCM_VAL_0x0000E3C0: .word 0x0000E3C0
468 PLL_VAL_0x222: .word 0x222
469 PLL_VAL_0x232: .word 0x232
470 BASE_ADDR_W_PLL1: .word PLL1_BASE_ADDR
471 BASE_ADDR_W_PLL2: .word PLL2_BASE_ADDR
472 BASE_ADDR_W_PLL3: .word PLL3_BASE_ADDR
473 PLL_VAL_0x1232: .word 0x1232
474 W_DP_OP_850: .word DP_OP_850
475 W_DP_MFD_850: .word DP_MFD_850
476 W_DP_MFN_850: .word DP_MFN_850
477 W_DP_OP_800: .word DP_OP_800
478 W_DP_MFD_800: .word DP_MFD_800
479 W_DP_MFN_800: .word DP_MFN_800
480 W_DP_OP_700: .word DP_OP_700
481 W_DP_MFD_700: .word DP_MFD_700
482 W_DP_MFN_700: .word DP_MFN_700
483 W_DP_OP_400: .word DP_OP_400
484 W_DP_MFD_400: .word DP_MFD_400
485 W_DP_MFN_400: .word DP_MFN_400
486 W_DP_OP_532: .word DP_OP_532
487 W_DP_MFD_532: .word DP_MFD_532
488 W_DP_MFN_532: .word DP_MFN_532
489 W_DP_OP_665: .word DP_OP_665
490 W_DP_MFD_665: .word DP_MFD_665
491 W_DP_MFN_665: .word DP_MFN_665
492 W_DP_OP_216: .word DP_OP_216
493 W_DP_MFD_216: .word DP_MFD_216
494 W_DP_MFN_216: .word DP_MFN_216
495 PLATFORM_BASE_ADDR_W: .word PLATFORM_BASE_ADDR
496 PLATFORM_CLOCK_DIV_W: .word 0x00000725
499 /*---------------------------------------------------------------------------*/
500 /* end of hal_platform_setup.h */
501 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */