1 #ifndef CYGONCE_VAR_CACHE_H
2 #define CYGONCE_VAR_CACHE_H
4 //=============================================================================
8 // HAL cache control API
10 //=============================================================================
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42 //####ECOSGPLCOPYRIGHTEND####
43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: nickg, dmoseley
49 // Purpose: Cache control API
50 // Description: The macros defined here provide the HAL APIs for handling
51 // cache control operations.
53 // #include <cyg/hal/var_cache.h>
57 //####DESCRIPTIONEND####
59 //=============================================================================
61 #include <pkgconf/hal.h>
62 #include <cyg/infra/cyg_type.h>
64 //#include <cyg/hal/plf_cache.h>
66 //=============================================================================
67 // AM33 implementation
69 //-----------------------------------------------------------------------------
74 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
75 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
76 #define HAL_DCACHE_WAYS 4 // Associativity of the cache
79 #define HAL_ICACHE_SIZE 8192 // Size of cache in bytes
80 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
81 #define HAL_ICACHE_WAYS 4 // Associativity of the cache
83 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
84 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
86 //-----------------------------------------------------------------------------
89 #define HAL_CHCTR ((volatile CYG_ADDRWORD *)0xC0000070)
91 #define HAL_CHCTR_ICEN 0x0001
92 #define HAL_CHCTR_DCEN 0x0002
93 #define HAL_CHCTR_ICBUSY 0x0004
94 #define HAL_CHCTR_DCBUSY 0x0008
95 #define HAL_CHCTR_ICINV 0x0010
96 #define HAL_CHCTR_DCINV 0x0020
97 #define HAL_CHCTR_DCWTMD 0x0040
98 #define HAL_CHCTR_ICWMD 0x0300
99 #define HAL_CHCTR_DCWMD 0x3000
101 #define HAL_DCACHE_PURGE_WAY0 ((volatile CYG_BYTE *)0xC8400000)
102 #define HAL_DCACHE_PURGE_WAY1 ((volatile CYG_BYTE *)0xC8401000)
103 #define HAL_DCACHE_PURGE_WAY2 ((volatile CYG_BYTE *)0xC8402000)
104 #define HAL_DCACHE_PURGE_WAY3 ((volatile CYG_BYTE *)0xC8403000)
106 //-----------------------------------------------------------------------------
107 // Global control of data cache
109 // Enable the data cache
110 #define HAL_DCACHE_ENABLE() \
112 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
113 chctr |= HAL_CHCTR_DCEN; \
114 *HAL_CHCTR = chctr; \
117 // Disable the data cache
118 #define HAL_DCACHE_DISABLE() \
120 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
121 chctr &= ~HAL_CHCTR_DCEN; \
122 *HAL_CHCTR = chctr; \
123 while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \
126 // Query the state of the data cache
127 #define HAL_DCACHE_IS_ENABLED(_state_) \
129 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
130 _state_ = (0 != (chctr & HAL_CHCTR_DCEN)); \
133 // Invalidate the entire cache
134 #define HAL_DCACHE_INVALIDATE_ALL() \
136 register CYG_ADDRWORD chctr; \
137 register CYG_ADDRWORD state; \
138 HAL_DCACHE_IS_ENABLED(state); \
140 HAL_DCACHE_DISABLE(); \
141 chctr = *HAL_CHCTR; \
142 chctr |= HAL_CHCTR_DCINV; \
143 *HAL_CHCTR = chctr; \
144 while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \
146 HAL_DCACHE_ENABLE(); \
149 // Synchronize the contents of the cache with memory.
150 #define HAL_DCACHE_SYNC() HAL_DCACHE_STORE( 0, HAL_DCACHE_SIZE )
152 // Set the data cache refill burst size
153 //#define HAL_DCACHE_BURST_SIZE(_size_)
155 // Set the data cache write mode
156 #define HAL_DCACHE_WRITE_MODE( _mode_ ) \
158 register CYG_ADDRWORD chctr; \
159 register CYG_ADDRWORD state; \
160 HAL_DCACHE_IS_ENABLED(state); \
162 HAL_DCACHE_DISABLE(); \
163 chctr = *HAL_CHCTR; \
164 chctr &= ~HAL_CHCTR_DCWTMD; \
165 chctr |= HAL_CHCTR_DCWTMD*(_mode_); \
166 *HAL_CHCTR = chctr; \
167 while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \
169 HAL_DCACHE_ENABLE(); \
172 #define HAL_DCACHE_WRITEBACK_MODE 0
173 #define HAL_DCACHE_WRITETHRU_MODE 1
175 // Load the contents of the given address range into the data cache
176 // and then lock the cache so that it stays there.
177 //#define HAL_DCACHE_LOCK(_base_, _size_)
179 // Undo a previous lock operation
180 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
182 // Unlock entire cache
183 //#define HAL_DCACHE_UNLOCK_ALL()
185 //-----------------------------------------------------------------------------
186 // Data cache line control
188 // Allocate cache lines for the given address range without reading its
189 // contents from memory.
190 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
192 // Write dirty cache lines to memory and invalidate the cache entries
193 // for the given address range.
194 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
196 // Invalidate cache lines in the given range without writing to memory.
197 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
199 // Write dirty cache lines to memory for the given address range.
201 // This functionality requires 4 register variables. To prevent register
202 // spilling, put the code in a separate function.
203 externC void cyg_hal_dcache_store(CYG_ADDRWORD base, int size);
205 #define HAL_DCACHE_STORE( _base_ , _size_ ) \
206 cyg_hal_dcache_store((CYG_ADDRWORD)(_base_), (_size_))
208 // Preread the given range into the cache with the intention of reading
210 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
212 // Preread the given range into the cache with the intention of writing
214 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
216 // Allocate and zero the cache lines associated with the given range.
217 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
219 //-----------------------------------------------------------------------------
220 // Global control of Instruction cache
222 // Enable the instruction cache
223 #define HAL_ICACHE_ENABLE() \
225 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
226 chctr |= HAL_CHCTR_ICEN; \
227 *HAL_CHCTR = chctr; \
230 // Disable the instruction cache
231 #define HAL_ICACHE_DISABLE() \
233 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
234 chctr &= ~HAL_CHCTR_ICEN; \
235 *HAL_CHCTR = chctr; \
236 while( HAL_CHCTR_ICBUSY & *HAL_CHCTR ); \
239 // Query the state of the instruction cache
240 #define HAL_ICACHE_IS_ENABLED(_state_) \
242 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
243 _state_ = (0 != (chctr & HAL_CHCTR_ICEN)); \
246 // Invalidate the entire cache
247 #define HAL_ICACHE_INVALIDATE_ALL() \
249 register CYG_ADDRWORD chctr; \
250 register CYG_ADDRWORD state; \
251 HAL_ICACHE_IS_ENABLED(state); \
253 HAL_ICACHE_DISABLE(); \
254 chctr = *HAL_CHCTR; \
255 chctr |= HAL_CHCTR_ICINV; \
256 *HAL_CHCTR = chctr; \
257 while( HAL_CHCTR_ICBUSY & *HAL_CHCTR ); \
259 HAL_ICACHE_ENABLE(); \
262 // Synchronize the contents of the cache with memory.
263 #define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
265 // Set the instruction cache refill burst size
266 //#define HAL_ICACHE_BURST_SIZE(_size_)
268 // Load the contents of the given address range into the instruction cache
269 // and then lock the cache so that it stays there.
270 //#define HAL_ICACHE_LOCK(_base_, _size_)
272 // Undo a previous lock operation
273 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
275 // Unlock entire cache
276 //#define HAL_ICACHE_UNLOCK_ALL()
278 //-----------------------------------------------------------------------------
279 // Instruction cache line control
281 // Invalidate cache lines in the given range without writing to memory.
282 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
284 //-----------------------------------------------------------------------------
285 // flash caching control
286 #ifdef CYGSEM_HAL_UNCACHED_FLASH_ACCESS
287 #define HAL_FLASH_CACHES_OFF(_d_, _i_) \
289 _d_ = 0; /* avoids warning */ \
290 _i_ = 0; /* avoids warning */ \
293 #define HAL_FLASH_CACHES_ON(_d_, _i_) \
298 //-----------------------------------------------------------------------------
299 #endif // ifndef CYGONCE_VAR_CACHE_H
300 // End of var_cache.h