1 # ====================================================================
5 # configuration data related to kernel interrupt handling
7 # ====================================================================
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40 # ====================================================================
41 ######DESCRIPTIONBEGIN####
44 # Original data: nickg
48 #####DESCRIPTIONEND####
50 # ====================================================================
52 # NOTE: the choice of list vs table should not be two separate
53 # options. There is a single option which must have one of
55 cdl_component CYGIMP_KERNEL_INTERRUPTS_DSRS {
56 display "Use delayed service routines (DSRs)"
59 In eCos the recommended way to handle device interrupts is to
60 do a minimum amount of work inside the low level interrupt
61 handler itself, and instead do as much as possible in a
62 Delayed Service Routine or DSR. If an application does not
63 make use of DSRs directly or indirectly then it is possible
64 to disable the DSR support completely, which reduces the
65 overheads of context switches and interrupt handling. Note
66 that the kernel real-time clock makes use of DSRs, as do many
67 of the device drivers. "
69 cdl_interface CYGINT_KERNEL_INTERRUPTS_DSRS {
70 requires 1 == CYGINT_KERNEL_INTERRUPTS_DSRS
74 # NOTE: the choice of list vs table should not be two separate
75 # options. There is a single option which must have one of
77 cdl_component CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST {
78 display "Use linked lists for DSRs"
80 implements CYGINT_KERNEL_INTERRUPTS_DSRS
82 When DSR support is enabled the kernel must keep track of all
83 the DSRs that are pending. This information can be kept in a
84 fixed-size table or in a linked list. The list implementation
85 requires that the kernel disable interrupts for a very short
86 period of time outside interrupt handlers, but there is no
87 possibility of a table overflow occurring."
89 cdl_option CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO {
90 display "Schedule DSRs in FIFO order"
93 description "When this option is set, DSRs are scheduled
94 in the natural FIFO (first in, first out) order,
95 otherwise they are scheduled in LIFO (last in, first
96 out) order. Applications should not rely on any
97 particular order of scheduling of DSRs. LIFO
98 scheduling is kept for backward compatibility only and
99 is not recommended as it may lead to high (up to 2
100 times higher then FIFO) IRQ-to-DSR latencies at some
101 (typically rare) conditions. If unsure, leave this set."
106 cdl_component CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE {
107 display "Use fixed-size table for DSRs"
109 implements CYGINT_KERNEL_INTERRUPTS_DSRS
111 When DSR support is enabled the kernel must keep track of all
112 the DSRs that are pending. This information can be kept in a
113 fixed-size table or in a linked list. The table
114 implementation involves a very small risk of overflow at
115 run-time if a given interrupt source is able to have more
116 than one pending DSR. However it has the advantage that
117 the kernel does not need to disable interrupts outside
120 cdl_option CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE {
121 display "Number of entries in fixed-size DSR table"
123 legal_values 2 to 1024
126 When DSR support is enabled the kernel must keep track of all
127 the DSRs that are pending. One approach involves a fixed-size
128 table, which involves a very small risk of overflow at
129 run-time. By increasing the table size it is possible to reduce
134 cdl_option CYGIMP_KERNEL_INTERRUPTS_CHAIN {
135 display "Chain all interrupts together"
136 requires CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
139 Interrupts can be attached to vectors either singly, or be
140 chained together. The latter is necessary if there is no way
141 of discovering which device has interrupted without
142 inspecting the device itself. It can also reduce the amount
143 of RAM needed for interrupt decoding tables and code."