ldr r2, =10f
mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
orr r1, r1, #7 // enable MMU bit
+ orr r1, r1, #0x800 // enable z bit
mcr MMU_CP, 0, r1, MMU_Control, c0
mov pc,r2 /* Change address spaces */
nop
/* CS0 sync mode setup */
.macro init_cs0_sync
/*
- * Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz):
+ * Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz)
*/
/* Flash reset command */
- mov r0, #CS0_BASE_ADDR
+ mov r0, #CS0_BASE_ADDR
ldr r1, =0xF0F0
strh r1, [r0]
/* 1st command */
ldr r2, =0xAAA
- add r2, r2, r0
+ add r2, r2, r0
ldr r1, =0xAAAA
- strh r1, [r2]
+ strh r1, [r2]
/* 2nd command */
ldr r2, =0x554
add r2, r2, r0
.endm /* init_cs4 */
// DDR SDRAM setup
- * r4 = burst mode vs full-page mode */
+ /* r4 = burst mode vs full-page mode */
.macro init_ddr_sdram
ldr r3, SDRAM_0x82216080 /* 16 bit memory */
ldr r0, ESDCTL_BASE_W